Advanced Computer Architecture

CS-522

MS – Computer Science

Credit Hours : 3-0

Dr. Shahid Latif (Associate Professor)

Department of Computer Science & IT

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Sarhad University of Science and Information Technology, Peshawar
Course Details
Course title/code: Adv. Computer Architecture/CS-522

Lecture: 01

Topic: Introduction to the Course

Introduction to Comp. Architecture (Chap-1)

Program: MS – Computer Science (Sem: 1st, 2nd, 3rd & 4th)

Department of Computer Science & IT

Sarhad University of Science and Information Technology, Peshawar 2
Introduction to the Course

Department of Computer Science & IT

Sarhad University of Science and Information Technology, Peshawar
Lecture Outlines
• • Course
CourseDescription
Description • Computer Architecture
• • Course
CourseOutlines
Outlines • Definition
• • Grading
GradingPolicy
Policy • Computer Organization
• • Recommended
Recommended Books
Books • Definition
• • Detailed
DetailedObjectives
Objectives • Difference between Computer
• • Prerequisite
Prerequisite
to to
thethe
course
course Architecture and Organization
• • Number
Number Systems
Systems • Structure & Function
• Computer Functions
• • Data
DataFormats
Formats
• Data processing, Data storage,
• • Microprocessor
Microprocessor Architecture
Architecture Data movement, Control
• • General
GeneralBuses
Buses • Operations
• • Memory
Memory Management
Management
• • Instruction
InstructionSetSet
• • Addressing
Addressing modes
modes
• • PIN
PINDiagram
Diagram
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Course Description
• This course is designed to
• Familiarize the students with the Architecture and Organization of a
Computer Systems

• It explores
• Advanced principles, design methodologies, and innovations in
computer systems

• This course investigates

• Optimizing performance, scalability, memory hierarchy, instruction-
level parallelism, high-performance computing, parallel architectures,
and energy efficiency in modern computer architectures
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Course Outlines (Tentative)
• History and Evolution of Computers
• Data path (data buses) design
• Memory management (Internal, Main & External memory)
• Internal/external devices & their architectural requirements
• ALUs
• Pipelining
• Control mechanism
• Parallel processing etc. etc.

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Grading Policy
Grading policy for this course is such that:

• Mid Exam: 25-30%

• Final Exam: 50%
• Assign(s)/Quizzes 10-15%
• Research Paper/Presentations: 10%

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Reference Material
• Computer Organization and Architecture
• by William Stallings, 8th or Latest Edition
• Computer Organization and Design: The Hardware /
Software Interface
• by David A. Patterson and John L. Hennessy
• Computer System Architecture
• by Morris Mano, 3rd Edition
• Computer Architecture and Organization
• by John P. Hayes, International Edition
• Research papers and articles
• Conference and Journal research papers from various publishers 8
Detailed Objectives
1. To overview the History and Evolution of Computers
2. To examine
• Major components of a computer and their interconnections
• Internal and external memory and of input–output (I/O)
3. To examine the internal architecture and organization of the
processor
• Computer arithmetic, The Instruction set, Addressing modes, Reduced
instruction set computer (RISC), Superscalar approaches
4. To examine
• Internal structure of control unit, and use of Microprogramming
5. To deal with
• Parallel Organization and the Multicore Architecture
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Pre-requisite

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Pre-requisites

This course is build on the already acquired knowledge of

• Digital Logic Design
• Basic Electronics
• Microprocessor Architecture and Assembly Language

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Number Systems
• The symbolic representation
• Used to express quantities and perform mathematical
operations
• Different number systems use distinct sets of symbols and
rules for representing and manipulating numbers
• Some common number systems:
• Binary: 0, 1
• Octal: 0, 1, 2, 3, 4, 5, 6, 7
• Decimal: 0, 1, 2, 3, 4, 5, 6, 7, 8, 9
• Hexadecimal (alpha-numeric)
0, 1, 2, 3, 4, 5, 6, 7, 8, 9,
A(10), B(11), C(12), D(13), E(14), F(15) 12
Number Representation
Number representations in various number systems

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Arithmetic
Arithmetic in various number systems

25-7=18
15 in octal ki 13
13-7=6
1-0=1
result = 16 correct

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Number Conversion
Binary Octal Decimal Hexadecimal

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16
Exercise

• Convert the following numbers from one base to another:

• Convert the binary number 11012 to its decimal equivalent.

• Convert the decimal number 7310 to its binary equivalent.

• Convert the hexadecimal number 2A16 to its binary and

decimal equivalents. 2 in hexadecimal is 0010 in binary.
A in hexadecimal is 1010 in binary.
2A= 0010 1010 four bits
2A = 2 * 16¹ + 10 * 16 = 32 + 10 = 42
• Convert the binary number 111101012 to octal and decimal.

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Complements

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Exercise - 1’s and 2’s Compliment
• Find the 1's complement of the given binary numbers:

• 1010102 010101

• 1101112 001000

• Find the 2's complement of the given binary numbers:

100110
------
• 1001102 011001
+1
011010
• 0110102 011010
------
100101
• 111100012 100110
+1

11110001
--------------
00001110
+1
00001111
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Data Formats
• ASCII: American standard code for information interchange
➢ 7-bit code for alphanumeric characters in a computer system
➢ B → 42 (0101010)
➢ ? → 3F
➢ @ → 40

• BCD: Binary coded decimal

➢ 0 = 0000, 1 = 0001, … , 9 = 1001

• Singed & Unsigned integers/data: ± XXXXXXXX

➢ Leftmost bit (MSB) represents the sign bit of the number, as well as
a weight of -128
➢ 80H → 128 as an unsigned number
➢ 80H → -128 as a signed number
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 Microprocessor Architecture
General Architecture of Micro-processor: the arrangement
of various devices in a complete system or network. E.g.

• ALU
• Registers Array
• Control Unit

Reference: Barry. B. Brey “The Intel Microprocessors” Pearson Education, Inc. 21

 Architecture 0f 8086
• ALU
• Registers
• GPRs & SPRs
• Instruction queue
• Buses
• Data
• Control
• Address
• O.S.

Reference: Barry. B. Brey “The Intel Microprocessors” Pearson Education, Inc. 22

General Buses (in 8086)
• Data Bus
• 16 bits

• Control Bus
• 16 bits

• Address Bus
• 20 bits

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 Memory (along mapped I/O)

Reference: Barry. B. Brey “The Intel Microprocessors” Pearson Education, Inc. 24

Addressable Memory
Address lines Vs. Addressable Memory

(20 address lines can address 1MB, similarly 32GB memory can
be addressed using 35 address lines)

20=1, 21=2, 22=4, 23=8, --------

210=1024=1K, 211=1K*2= 2K, ------ -----

220=1K*1K=1M, 221=1M*2=2M, ----- -----

230=1M*1K=1G, And so on -----

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Exercise
• A computer system has 12 address lines
• Total amount of addressable memory = ?

• A system has 20 address lines, providing an addressable memory

of 1 MB
• If the memory capacity needs to be expanded to 44 MB,
• How many additional address lines are required?

• How much memory could the system address if the number of

address lines are 36?

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Instruction Set
Data transfer instructions → Move, Push, Pop, In, Out etc.

Arithmetic instructions → +, -, *, /, INC, DCR etc.

Logic/bit-manipulated instr. → AND, OR, XOR, NOT,

CMP, Shift and Rotate etc.

String manipulated instr. → MOVS, LODS, STOS,

CMPS, SCNS etc.

Program Control instr. → JMP, Conditional JMPs, CALL,

RET etc.

Machine Control instr. → NOP, wait, HLT etc.

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Addressing Modes
1. Register addressing mode MOV AX, BX

2. Immediate addressing mode MOV AX, 1234H

3. Direct addressing mode MOV [0345H], AX

4. Register indirect addressing mode MOV [BX], CX

5. Base-plus-index addressing mode MOV [BX+SI], BP

6. Register relative addressing mode MOV CL, [BX+4]

7. Base-relative-plus-index MOV Array[BX+SI], DX

Addressing mode
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Pin Diagram (8086)

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 Chapter # 1
Introduction

Department of Computer Science & IT

Sarhad University of Science and Information Technology, Peshawar
Architecture & Organization (1)
• Architecture: those attributes (features/elements) of a system
– visible to a programmer, or
– have a direct impact on the logical execution of a program
Such as:
– Instruction set, number of bits used for data representation, I/O
mechanisms, memory addressing techniques
– e.g. Is there a multiply instruction?

• Organization is how features are implemented, such as:

– Control signals, interfaces (computer → peripherals), memory
technology
– e.g. Is there a spherical multiply unit (hardware) or
– is it done by repeated addition?
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Architecture & Organization (2)
• Many computer manufacturers offer a family of computer
models
– all with same architecture but with differences in organization
e.g.
– All Intel x86 family (8086, 80286, 80386 etc.) share the same basic
architecture
– The IBM System/370 family share the same basic architecture
– This gives code compatibility
• At least backwards

• Organization differs between different versions

– for example 8086 & 8088

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Structure & Function
• Structure → is the way in which components relate to each
other (i.e. interrelated)

(e.g. Memory structure)

• Function→ is the operation of individual components as part

of the structure

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Computer Functions
• In general, basic functions all computers can perform include:

– Data processing
• To process or execute data of various forms
– Data storage
• Computers perform long-term data storage function
• As well as a short-term data storage function while processing data
on fly (i.e. data get in → processed→ result go out)
– Data movement
• Between computer and outside world (source or destination)
– Control
• An unit/section that provides the computer with instructions
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Functional View
of a computer

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Operations (a): Data movement

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Operations (b): Data Storage

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Operation (c) Processing from/to
storage

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Operation (d) Processing from
storage to I/O

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Computer Structure - Top Level

Peripherals Computer

Central Main
Processing Memory
Unit
Computer
(Storage, Systems
Processing)
Interconnection

Input
Output
Communication
lines

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Structure - The CPU

CPU

Computer Arithmetic
Registers and
I/O Login Unit
System CPU
Bus
Internal CPU
Memory Interconnection

Control
Unit

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Structure - The Control Unit

Control Unit

CPU
Sequencing
ALU Logic
Control
Internal
Unit
Bus
Control Unit
Registers Registers and
Decoders

Control
Memory

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 Thank you

[email protected]

Department of Computer Science & IT

Sarhad University of Science and Information Technology, Peshawar

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