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SNS COLLEGE OF ENGINEERING

Kurumbapalayam (Po), Coimbatore – 641 107
AN AUTONOMOUS INSTITUTION
Approved by AICTE, New Delhi and Affiliated to Anna University, Chennai

Question Bank - Unit no.: I

Program: B.E.
Course Name: Digital Electronics Course Code: 19EC306
Academic year: 2023-24 Sem/Year: III/2nd
Level A. Easy Questions (2 marks each)
S. Questions
CO*
No.
Q1 Represent the following decimal numbers in both binary sign/magnitude and
twos complement using 16 bits: +512; -29.
Q2 Calculate (72530 - 13250) using tens complement arithmetic. Assume rules
similar to those for twos complement arithmetic.
Q3 Determine base r in each of the following :
- a) (121)r = (144)8
b)(361)10 = (551)r
Q4 Write the BCD code for the following numbers:- a) (11101) 2 b) (27) 10
Q5 Represent the following twos complement values in decimal: 1101011; 0101101.
Q6 How many binary numbers are created with 8 bits
Q7 If 52/4=12, the base of the number system is
Q8 The highest decimal number that can be represented with 10 binary digits is
Q9 11001, 1001, 111001 correspond to the 2’s complement representation of
which numbers?
Q10 Convert (634) 8 to binary
Q11 Convert gray code 101011 into its binary equivalent
Q12 Add (1 0 1 0) 2 and (0 0 1 1) 2
Q13 Substract (1 1 1 0 0 1)2 from (1 0 1 0 1 1)2 using 2’s complement method
Q14 List the different number systems?
Q15 Given the two binary numbers X = 1010100 and Y = 1000011, perform the
subtraction (a) X -Y and (b) Y - X using 2's complements.
Q16 Write the names of basic logical operators.
Q17 How Do You Detect If Two 8-bit Signals Are Same?
Q18 Convert (1001)2 to gray code.
Q19 What is Digital System?
Q20 Calculate (72530 - 13250) using tens complement arithmetic. Assume rules

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similar to those for twos complement arithmetic.

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Level B. Intermediate Questions (5 marks each)

Q21 Assume numbers are represented in 4-bit twos complement representation.
Show the calculation of the following:
(i) 6 + 1 (ii) -6 + 2 (iii). - 4 – 3
Q22 What is error correcting and detecting code also explain Hamming code?
Q23 Detect and correct errors, if any, in the even parity Hamming code words and
write the correct code 1100110.
Q24 Perform the following subtraction using 2’s complement
method. (i) 100- 11000
(ii) 11010-10000
Q25 Realize following expression with the help of NAND gate
a) Y = AB + CD
b) Y= A’B + AB’
Q26 Convert the following number from one base to another
a) (43.325) 8 = ( ) 2 ?
b) (A2F.22) 16 = ( ) 8 ?
c) (124) 5 = ( ) 2 ?
d) (1111.00011) 2 = ( ) 16 ?
e) (23456) 7 = ( ) 10 ?
Q27 Explain the Excess-3 code? Write about Error correction & Detection?
Q28 Explain binary to Gray & Gray to binary conversion with example?
Q29 Represent the following decimal numbers in binary unsigned, sign/magnitude and
twos complement using 16 bits: +1024; - 49.
Q30 Explain the difference between analog and digital systems.
Level C. Difficult Questions (10 marks each)
Q31 ‘A’ transmits hamming code (even parity) for a BCD digit and ‘B’ receives
‘0110000’ assuming that only one bit can be in error during the transmission. Find
out the BCD digit that was transmitted by A.
Q32 a) Convert the following numbers (L5) (3M) i) (250.5)10 = ( )2 ii) ) (673.23)10 = ( )8
iii)(101110.01)2=( )8
b) Convert the following to binary and then to gray code (AB33)16
c) Perform the following Using BCD arithmetic (7129) 10 + (7711) 10
Q33 Convert the following number from one base to another
a) (43.325) 8 = ( ) 2 ?
b) (A2F.22) 16 = ( ) 8 ?
c) (124) 5 = ( ) 2 ?
d) (1111.00011) 2 = ( ) 16 ?
e) (23456) 7 = ( ) 10 ?
Q34 Perform the following subtraction using 2’s complement method

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a) (110100) 2 – (10101) 2
b) (22) 10 – (27) 10
c) (0011.1001) 2 – (0001.1110) 2
Q35 a) Represent the decimal number 3452 in i)BCD ii)Excess-3
b) perform (-50)-(-10) in binary using the signed-2’s complement
c) Determine the value of base x if(211)x=(152)8
Q36 a) Convert the following numbers
i)(163.789)10 to Octal number ii)(11001101.0101)2 to base-8 and base-4 iii)
(4567)10 to base2 iv) (4D.56)16 to Binary
b) Subtract (111001)2 from (101011) using 1’s complement?

Question Bank - Unit no.: II

Program: B. Tech.
Course Name: Digital Electronics Course Code: 21BTCS302
Academic year: 2022-23 Sem/Year: III/2nd
Level A. Easy Questions (2 marks each)
S. Questions
CO*
No.
Q1 What is meant by a universal gate?
Q2 Implement the NOT gate using NAND gate.
Q3 Simplify the given Boolean Expression F= x’+x’y+xz’+xz.
Q4 State the limitations of karnaugh map.
Q5 State the associative property of Boolean algebra.
Q6 State the commutative property of Boolean algebra.
Q7 State the distributive property of Boolean algebra.
Q8 State De Morgan's theorem.
Q9 The output of a gate is low if and only if all its inputs are HIGH. It is true for
Q10 Which gates is known Coincidence detector?
Q11 What is a prime implicant?
Q12 What is a Logic gate?
Q13 Which gates are called as the universal gates? What are its advantages?
Q14 What is a karnaugh map?
Q15 Simplify the following expression Y = (A + B) (A = C) (B + C)

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Q16 Show that (X + Y' + XY) (X + Y') (X'Y) = 0

Q17 Implement OR gate using NAND gate.
Q18 Implement AND gate using NOR gate.
Q19 State the Duality theorem.
Q20 Simplify the following function using K
map F(A,B) =∑ m(0,1,2,3)
Level B. Intermediate Questions (5 marks each)
Q21 Using theorem of Boolean algebra simplify the following expression:-
F (A, B, C) = A+ABC+AB’C’+ABC’
Q22 Realize following expression with the help of NAND gate
a) Y = AB + CD
b) Y= A’B + AB’
Q23 Simplify the following function using K
map F(A,B,C,D) =∑ m(1, 3, 4, 6, 8, 9, 11, 13,
15)
Q24 Realize EXOR and EXNOR gates with the help of NAND gate only?
Q25 Prove that ABC + ABC' + AB'C + A'BC = AB + AC + BC
Q26 Reduce the following expression using K- map and implement them in Universal
logic. Σm (5, 6, 7, 9, 10, 11, 13, 14, 15)
Q27 Minimize and implement the following function in SOP form using K- map.
F1= Σm (0, 1, 4, 6, 8, 9, 11) + d (2, 7, 13)
Q28 Realize following expression with the help of NAND gate
a) Y = UV + WX + YZ
b) Y= AB + A’B’ where A, B, U, V, W, X, Y, Z are input variables.
Q29 Simplify the Boolean expressions to minimum number of literals
i) X’ + XY + X Z’ + XYZ’
ii) (X+Y) (X+Y’)
Q30 Obtain the Complement of Boolean Expression
i) A+B+A’B’C
ii) AB + A (B +C) + B’(B+D)
Level C. Difficult Questions (10 marks each)
Q31 Simplify the following using k-
map:- (i) f (A, B, C) =∑ m(0,3,4,5,7)
(ii) f (A,B,C,)=πM(0, 1, 3, 4, 7)
Q32 Using the Qunine- McCluskey method of tabular reduction minimize the given
combinational single output function F (A, B, C, D) = Σm (0, 1, 5, 7, 8, 10, 14, 15)
Q33 Minimize the following function and implement the minimized function using
only NAND gates:
f(A, B, C ,D) = ∑(0, 2, 8, 9, 10, 12, 13, 14)

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Q34 Simplify the following function using Tabular Method (Quinne-McClusky method)
F(A,B,C,D) =∑ m(1, 3, 4, 6, 8, 9, 11, 13, 15)
Q35 Simplify the Boolean expressions to minimum number of literals
i) (A + B)(A + C’ )(B’ + C’ )
ii) AB + (AC)’ + AB’C (AB + C)
iii) (A+B)’ (A’+B’)’
Q36 Reduce the expression f(x,y,z,w)= πM(0,2,7,8,9,10,11,15) .d (3,4) using K-Map?

Question Bank - Unit no.: III

Program: B. Tech.
Course Name: Digital Electronics Course Code: 21BTCS302
Academic year: 2022-23 Sem/Year: III/2nd
Level A. Easy Questions (2 marks each)
S. Questions
CO*
No.
Q1 How many possible outputs would a decoder have with 6-bit binary inputs?
Q2 Which combinational logic device is also known as data distributer?
Q3 Define combinational logic.
Q4 Define Half adder and full adder
Q5 Define Decoder?
Q6 Define multiplexer?
Q7 What do you mean by comparator?
Q8 What is meant by parity bit?
Q9 Compare the decoder and Demultiplexer.
Q10 What are the steps to design a combinational logic circuit?
Q11 What minimum distance is required for a single error correction according to
Hamming’s analysis in Digital Electronics?
Q12 How many errors can the Digital Electronics parity method can find in a single
word?
Q13 The result “X + XY = X” follows which of these laws?
Q14 Which of these flip – flops cannot be used to construct a serial shift register?
Q15 Which of these options represent the other name of Inter – Integrated logic?
Q16 How many cycles of addition and shifting in a 4 – bit multiplier are required to
perform multiplication using the shift method?

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Q17 What is the truth table of Half-subtractor?

Q18 Define priority encoder?
Q19 design procedure for combinational circuit?
Q20 How many 8 the correct number of multiplexers required to build a 32 x 1
multiplexer?
Level B. Intermediate Questions (5 marks each)
Q21 Design 4-to-1 multiplexer by using only 2-to-1 multiplexers.
Q22 Implement the following Boolean function with a Multiplexer F (A, B, C, D) = Σm
(1, 3, 4, 11, 12, 12, 13, 14, 15)
Q23 Design the circuit of BCD adder.
Q24 Design the circuit of half subtractor using NAND gate only.
Q25 Design All The Gates (not, And, Or, Nand, Nor, Xor, Xnor) Using 2:1 Multiplexer?
Q26 How Will You Implement A Full Subtractor From A Full Adder?
Q27 Explain the functionality of a Multiplexer?
Q28 Explain The Half adder? Implement the full adder using two half adders
Q29 Explain about Full Adder?
Q30 Explain Full binary subtractor in detail?
Level C. Difficult Questions (10 marks each)
Q31 What is Multiplexer? Realize the following logic expression using 4×1 MUX
taking A, C as a select line
F(A,B,C) = ∑ m(1, 2, 4, 6, 7)
Q32 Describe 3×8 decoder in brief also implement Full Adder using 3×8 decoder?
Q33 Design the circuit of BCD-to-7 Segment decoder.
Q34 Design the combinational circuit binary to gray code?
Q35 a) What is the truth table of Half-subtractor?
b) Define priority encoder?
c) Explain the design procedure for combinational circuit?
d) Design 4 bit parallel Adder?
e) Define Multiplexer and applications of multiplexer?
Q36 A) Design a 4 bit binary parallel subtractor and the explain operation in detail?
B) Design the combinational circuit of 4 Bit Parallel Adder?

Question Bank - Unit no.: IV

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Program: B. Tech.
Course Name: Digital Electronics Course Code: 21BTCS302
Academic year: 2022-23 Sem/Year: III/2nd
Level A. Easy Questions (2 marks each)
S. Questions
CO*
No.
Q1 What is the disadvantage of SR flip-flop?
Q2 Give any 3 example of the sequential circuit?
Q3 Define the function of the counter.
Q4 What are the different types of flip-flop?
Q5 What are the classifications of sequential circuits?
Q6 What is the operation of D flip-flop?
Q7 What is the operation of T flip-flop?
Q8 Define race around condition.
Q9 What is a master-slave flip-flop?
Q10 Define registers.
Q11 Define sequential circuit?
Q12 7 Bit Ring Counter's Initial State Is 0100010. After How Many Clock Cycles Will It
Return To The Initial State?
Q13 What do you meant by triggering.
Q14 Define the latch.
Q15 What will be the output from a D flip-flop if D = 1 and the clock is low?
Q16 What will be the output from a D flip – flop if the clock is low and D = 0?
Q17 What must be used along with synchronous control inputs to trigger a change in
the flip flop?
Q18 When does a negative level triggered flip-flop in Digital Electronics changes its
state?
Level B. Intermediate Questions (5 marks each)
Q21 What is race around condition and how it can be removed?
Q22 Describe the basic operation of JK flip flop?
Q23 Illustrate the basic difference between Latch and Flip flop?

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Q24 Explain the operation of ring counter and give its state diagram.
Q25 Write the difference between synchronous and Asysnchronous counter?
Q26 Explain excitation tables for JK and T flipflops.
Q27 Construct the D flipflop with the help of truth table and excitation
table.
Q28 Design a T FlipFlop from SR FlipFlop.
Q29 Classify different types of Counters.
Q30 Illustrate the operation of basic flipflop using NOR gates.
Level C. Difficult Questions (10 marks each)
Q31 Design a sequential circuit from the state diagram given below using
Dflipflop

Q32 Design a synchronous counter for the count sequence using D-FF
0→3→5→4→1→6→2→7
Q33 Build a 4bit universal shift register using D flipflops and multiplexers?

Q34 Build 4bit ring counter with circuit diagram, state transition diagram
and state table. Draw the corresponding timing diagrams?
Q35 With suitable logic diagram explain a 4bit bidirectional shift register?
Q36 Draw the state diagram and circuit excitation table of mod13
synchronous counter using T flipflops?

Question Bank - Unit no.: V

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Program: B. Tech.
Course Name: Digital Electronics Course Code: 21BTCS302
Academic year: 2022-23 Sem/Year: III/2nd
Level A. Easy Questions (2 marks each)
S. Questions
CO*
No.
Q1 The fastest logic family is
Q2 Give the classification of logic families
Q3 Define Fan-out?
Q4 Define power dissipation?
Q5 What is propagation delay?
Q6 Define noise margin?
Q7 Define fan in?
Q8 What are the types of ROM?
Q9 Define fan in?
Q10 What is mask - programmable?
Q11 Define PROM.
Q12 How many words can a 16x8 memory can store?
Q13 Define address of a memory.
Q14 What is Read and Write operation?
Q15 Draw the block diagram of the analog to digital converter.
Q16 Define a bus.
Q17 Give the feature of UV EPROM.
Q18 What are Flash memories?
Q19 What is a FIFO memory?
Q20 What is the tri-state logic.
Level B. Intermediate Questions (5 marks each)
Q21 What are PLA and PAL? Explain with suitable Example
Q22 Draw and Explain the of TTL NAND gate?
Q23 Compare PROM, EPROM and EEPROM technologies.
Q24 Describe the operation of basic circuit of ECL gate.

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Q25 Write a short note on: - (i) PLA (ii) PLD (iii) PROM
Q26 Differentiate between static and dynamic memory. Also explain SRAM and DRAM
in detail?
Q27 Explain the Classification of memory
Q28 What is Read and Write Operations
Q29 Differentiate volatile and non-volatile memory
Q30 What is Cache Memory
Level C. Difficult Questions (10 marks each)
Q31 explain the following characteristics of digital logic circuits:-
a ) propagation delay
b) Figure of merit
c) Noise margin
d) fan_in and fan_out
Q32 Explain the working of TTL circuit with suitable diagram? Also explain which
member of logic family has lowest propagation delay and why?
Q33 Differentiate between static and dynamic memory. Also explain SRAM and DRAM
in detail?
Q34 Describe the memories on the basis of classification and characteristics? Also
draw the static RAM & explain its working.
Q35 Define the following terms:
(i) Noise Margin
(ii) Fan-in
(iii) Fan- out
(iv) Propagation delay
(v) Power dissipation
Q36 Explain the operation of CMOS inverter. With the help of a neat diagram,
explain the working of a two-input TTL NAND gate.

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