LTC2345-16

Octal, 16-Bit, 200ksps

Differential SoftSpan ADC with
Wide Input Common Mode Range
Features Description
nn 200ksps per Channel Throughput The LTC®2345-16 is a 16-bit, low noise 8-channel si-
nn Eight Simultaneous Sampling Channels multaneous sampling successive approximation register
nn ±1.25LSB INL (Maximum) (SAR) ADC with differential, wide common mode range
nn Guaranteed 16-Bit, No Missing Codes inputs. Operating from a 5V low voltage supply and us-
nn Differential, Wide Common Mode Range Inputs ing the internal reference and buffer, each channel of this
nn Per-Channel SoftSpan Input Ranges: SoftSpanTM ADC can be independently configured on a
±4.096V, 0V to 4.096V, ±2.048V, 0V to 2.048V conversion-by-conversion basis to accept ±4.096, 0V
±5V, 0V to 5V, ±2.5V, 0V to 2.5V to 4.096V, ±2.048V, or 0V to 2.048V signals. Individual
nn 91dB Single-Conversion SNR (Typical) channels may also be disabled to increase throughput on
nn −113dB THD (Typical) at f = 2kHz
IN
the remaining channels.
nn 102dB CMRR (Typical) at f = 200Hz
IN The wide input common mode range and 102dB CMRR of
nn Rail-to-Rail Input Overdrive Tolerance the LTC2345-16 analog inputs allow the ADC to directly
nn Guaranteed Operation to 125°C digitize a variety of signals, simplifying signal chain design.
nn Integrated Reference and Buffer (4.096V) This input signal flexibility, combined with ±1.25LSB INL,
nn SPI CMOS (1.8V to 5V) and LVDS Serial I/O no missing codes at 16 bits, and 91dB SNR, makes the
nn Internal Conversion Clock, No Cycle Latency LTC2345-16 an ideal choice for many applications requir-
nn 81mW Power Dissipation (Typical) ing wide dynamic range.
nn 48-Lead (7mm x 7mm) QFN Package
The LTC2345-16 supports pin-selectable SPI CMOS (1.8V
to 5V) and LVDS serial interfaces. Between one and eight
Applications lanes of data output may be employed in CMOS mode,
nn Programmable Logic Controllers allowing the user to optimize bus width and throughput.
nn Industrial Process Control L, LT, LTC, LTM, Linear Technology and the Linear logo are registered trademarks and
SoftSpan is a trademark of Linear Technology Corporation. All other trademarks are the property
nn Medical Imaging of their respective owners. Protected by U.S. Patents, including 7705765, 7961132, 8319673.
Other Patents pending.
nn High Speed Data Acquisition

Typical Application
5V 1.8V TO 5V Integral Nonlinearity vs
0.1µF 2.2µF 0.1µF
Output Code and Channel
CMOS OR LVDS
1.00
I/O INTERFACE
±4.096V RANGE
FULLY
VDD VDDLBYP OVDD LVDS/CMOS 0.75 FULLY DIFFERENTIAL DRIVE (IN– = –IN+)
ARBITRARY DIFFERENTIAL IN0+ S/H PD ALL CHANNELS
5V 5V IN0– 0.50
S/H LTC2345-16
INL ERROR (LSB)

SDO0 0.25
S/H
0V 0V
• • •

S/H 0
16-BIT
• • •

MUX SAR ADC SDO7

BIPOLAR UNIPOLAR S/H SCKO –0.25
5V 5V SCKI
S/H SDI –0.50
CS
S/H –0.75
BUSY
0V 0V IN7+ CNV
SAMPLE
S/H
IN7– CLOCK
–1.00
DIFFERENTIAL INPUTS IN+/IN– WITH REFBUF REFIN GND –32768 –16384 0 16384 32768
WIDE INPUT COMMON MODE RANGE 234516 TA01a
OUTPUT CODE
47µF 0.1µF
EIGHT SIMULTANEOUS 234516 TA01b

SAMPLING CHANNELS
234516f

For more information www.linear.com/LTC2345-16 1

LTC2345-16
Absolute Maximum Ratings Pin Configuration
(Notes 1, 2)
TOP VIEW
Supply Voltage (VDD)...................................................6V

VDDLBYP

BUSY
Supply Voltage (OVDD).................................................6V

IN7+
IN7–
GND
GND
GND

GND
VDD
VDD

SDI
CS
Internal Regulated Supply Bypass (VDDLBYP).... (Note 3)

48
47
46
45
44
43
42
41
40
39
38
37
Analog Input Voltage IN6– 1 36 SDO7
IN0+ to IN7+, IN6+ 2 35 SDO–/SDO6
IN5– SDO+/SDO5
IN0– to IN7– (Note 4).................(–0.3V) to (VDD + 0.3V)
3 34
IN5+ 4 33 SCKO–/SDO4
IN4– SCKO+/SCKO
REFIN..................................................... –0.3V to 2.8V IN4+
5
6
32
31 OVDD
49
REFBUF, CNV (Note 4).............. –0.3V to (VDD + 0.3V) IN3– 7 GND 30 GND
IN3+ 8 29 SCKI–/SCKI
Digital Input Voltage (Note 4)...... –0.3V to (OVDD + 0.3V) IN2– 9 28 SCKI+/SDO3
Digital Output Voltage (Note 4)... –0.3V to (OVDD + 0.3V) IN2+ 10 27 SDI–/SDO2
IN1– 11 26 SDI+/SDO1
Power Dissipation............................................... 500mW IN1+ 12 25 SDO0

Operating Temperature Range

13
14
15
16
17
18
19
20
21
22
23
24
LTC2345C................................................. 0°C to 70°C

IN0–
IN0+
GND
GND
GND
GND
REFIN
GND
REFBUF
PD
LVDS/CMOS
CNV
LTC2345I..............................................–40°C to 85°C
LTC2345H........................................... –40°C to 125°C
UK PACKAGE
Storage Temperature Range................... –65°C to 150°C 48-LEAD (7mm × 7mm) PLASTIC QFN
TJMAX = 150°C, θJA = 34°C/W
EXPOSED PAD (PIN 49) IS GND, MUST BE SOLDERED TO PCB

Order Information
(http://www.linear.com/product/LTC2345-16#orderinfo)
LEAD FREE FINISH TAPE AND REEL PART MARKING* PACKAGE DESCRIPTION TEMPERATURE RANGE
LTC2345CUK-16#PBF LTC2345CUK-16#TRPBF LTC2345UK-16 48-Lead (7mm × 7mm) Plastic QFN 0°C to 70°C
LTC2345IUK-16#PBF LTC2345IUK-16#TRPBF LTC2345UK-16 48-Lead (7mm × 7mm) Plastic QFN –40°C to 85°C
LTC2345HUK-16#PBF LTC2345HUK-16#TRPBF LTC2345UK-16 48-Lead (7mm × 7mm) Plastic QFN –40°C to 125°C
Consult LTC Marketing for parts specified with wider operating temperature ranges. *The temperature grade is identified by a label on the shipping container.
For more information on lead free part marking, go to: http://www.linear.com/leadfree/
For more information on tape and reel specifications, go to: http://www.linear.com/tapeandreel/. Some packages are available in 500 unit reels through
designated sales channels with #TRMPBF suffix.

234516f

2 For more information www.linear.com/LTC2345-16

 LTC2345-16
Electrical Characteristics The l denotes the specifications which apply over the full operating
temperature range, otherwise specifications are at TA = 25°C. (Note 5)
SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS
VIN+ Absolute Input Range (Note 6) l 0 VDD V
(IN0+ to IN7+)
VIN– Absolute Input Range (Note 6) l 0 VDD V
(IN0– to IN7–)
VIN+ – VIN– Input Differential Voltage SoftSpan 7: ±VREFBUF Range (Note 6) l – VREFBUF VREFBUF V
Range SoftSpan 6: ±VREFBUF/1.024 Range (Note 6) l – VREFBUF/1.024 VREFBUF/1.024 V
SoftSpan 5: 0V to VREFBUF Range (Note 6) l 0 VREFBUF V
SoftSpan 4: 0V to VREFBUF/1.024 Range (Note 6) l 0 VREFBUF/1.024 V
SoftSpan 3: ±0.5 • VREFBUF Range (Note 6) l –0.5 • VREFBUF 0.5 • VREFBUF V
SoftSpan 2: ±0.5 • VREFBUF/1.024 Range (Note 6) l –0.5 • VREFBUF/1.024 0.5 • VREFBUF/1.024 V
SoftSpan 1: 0V to 0.5 • VREFBUF Range (Note 6) l 0 0.5 • VREFBUF V
VCM Input Common Mode Voltage (Note 6) l 0 VDD V
Range
VIN+ – VIN– Input Differential Overdrive (Note 7) l −VDD VDD V
Tolerance
IIN Analog Input Leakage Current l –1 1 µA
CIN Analog Input Capacitance Sample Mode 50 pF
Hold Mode 10 pF
CMRR Input Common Mode VIN+ = VIN− = 3.6VP-P 200Hz Sine l 84 102 dB
Rejection Ratio
VIHCNV CNV High Level Input Voltage l 1.3 V
VILCNV CNV Low Level Input Voltage l 0.5 V
IINCNV CNV Input Current VIN = 0V to VDD l –10 10 μA

Converter Characteristics The l denotes the specifications which apply over the full operating
temperature range, otherwise specifications are at TA = 25°C. (Note 8)
SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS
Resolution l 16 Bits
No Missing Codes l 16 Bits
Transition Noise SoftSpans 7 and 6: ±4.096V and ±4V Ranges 0.63 LSBRMS
SoftSpans 5 and 4: 0V to 4.096V and 0V to 4V Ranges 1.2 LSBRMS
SoftSpans 3 and 2: ±2.048V and ±2V Ranges 1.2 LSBRMS
SoftSpan 1: 0V to 2.048V Range 2.3 LSBRMS
INL Integral Linearity Error (Note 9) l –1.25 ±0.50 1.25 LSB
DNL Differential Linearity Error (Note 10) l −0.9 ±0.20 0.9 LSB
ZSE Zero-Scale Error (Note 11) l −750 ±65 750 μV
Zero-Scale Error Drift ±2 μV/°C
FSE Full-Scale Error (Note 11) l −0.13 ±0.025 0.13 %FS
Full-Scale Error Drift ±2.5 ppm/°C

234516f

For more information www.linear.com/LTC2345-16 3

LTC2345-16
Dynamic Accuracy The l denotes the specifications which apply over the full operating temperature range,
otherwise specifications are at TA = 25°C. AIN = –1dBFS. (Notes 8, 12)
SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS
SINAD Signal-to-(Noise + SoftSpans 7 and 6: ±4.096V and ±4V Ranges, fIN = 2kHz l 87.2 91.0 dB
Distortion) Ratio SoftSpans 5 and 4: 0V to 4.096V and 0V to 4V Ranges, fIN = 2kHz l 81.3 85.6 dB
SoftSpans 3 and 2: ±2.048V and ±2V Ranges, fIN = 2kHz l 81.4 85.8 dB
SoftSpan 1: 0V to 2.048V Range, fIN = 2kHz l 75.7 80.0 dB
SNR Signal-to-Noise Ratio SoftSpans 7 and 6: ±4.096V and ±4V Ranges, fIN = 2kHz l 87.3 91.0 dB
SoftSpans 5 and 4: 0V to 4.096V and 0V to 4V Ranges, fIN = 2kHz l 81.5 85.6 dB
SoftSpans 3 and 2: ±2.048V and ±2V Ranges, fIN = 2kHz l 81.6 85.8 dB
SoftSpan 1: 0V to 2.048V Range, fIN = 2kHz l 75.8 80.0 dB
THD Total Harmonic Distortion SoftSpans 7 and 6: ±4.096V and ±4V Ranges, fIN = 2kHz l –113 –99 dB
SoftSpans 5 and 4: 0V to 4.096V and 0V to 4V Ranges, fIN = 2kHz l –111 –95 dB
SoftSpans 3 and 2: ±2.048V and ±2V Ranges, fIN = 2kHz l –110 –96 dB
SoftSpan 1: 0V to 2.048V Range, fIN = 2kHz l –108 –95 dB
SFDR Spurious Free Dynamic SoftSpans 7 and 6: ±4.096V and ±4V Ranges, fIN = 2kHz l 99 114 dB
Range SoftSpans 5 and 4: 0V to 4.096V and 0V to 4V Ranges, fIN = 2kHz l 95 113 dB
SoftSpans 3 and 2: ±2.048 and ±2V Ranges, fIN = 2kHz l 96 112 dB
SoftSpan 1: 0V to 2.048V Range, fIN = 2kHz l 96 109 dB
Channel-to-Channel One Channel Converting 3.6VP-P 200Hz Sine in ±2.048V Range, −107 dB
Crosstalk Crosstalk to All Other Channels
–3dB Input Bandwidth 31 MHz
Aperture Delay 1 ns
Aperture Delay Matching 150 ps
Aperture Jitter 3 psRMS
Transient Response Full-Scale Step, 0.005% Settling 200 ns

Internal Reference Characteristics

The l denotes the specifications which apply over the full
operating temperature range, otherwise specifications are at TA = 25°C. (Note 8)
SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS
VREFIN Internal Reference Output Voltage 2.043 2.048 2.053 V
Internal Reference Temperature Coefficient (Note 13) l 5 20 ppm/°C
Internal Reference Line Regulation VDD = 4.75V to 5.25V 0.1 mV/V
Internal Reference Output Impedance 20 kΩ
VREFIN REFIN Voltage Range REFIN Overdriven (Note 6) 1.25 2.2 V

234516f

4 For more information www.linear.com/LTC2345-16

 LTC2345-16
Reference Buffer Characteristics
The l denotes the specifications which apply over the full
operating temperature range, otherwise specifications are at TA = 25°C. (Note 8)

SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS

VREFBUF Reference Buffer Output Voltage REFIN Overdriven, VREFIN = 2.048V l 4.091 4.096 4.101 V
REFBUF Voltage Range REFBUF Overdriven (Notes 6, 14) l 2.5 5 V
REFBUF Input Impedance VREFIN = 0V, Buffer Disabled 13 kΩ
IREFBUF REFBUF Load Current VREFBUF = 5V, 8 Channels Enabled (Notes 14, 15) l 1.5 1.9 mA
VREFBUF = 5V, Acquisition Mode (Note 14) 0.39 mA

Digital Inputs and Digital Outputs The l denotes the specifications which apply over the
full operating temperature range, otherwise specifications are at TA = 25°C. (Note 8)
SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS
CMOS Digital Inputs and Outputs
VIH High Level Input Voltage l 0.8 • OVDD V
VIL Low Level Input Voltage l 0.2 • OVDD V
IIN Digital Input Current VIN = 0V to OVDD l –10 10 μA
CIN Digital Input Capacitance 5 pF
VOH High Level Output Voltage IOUT = –500μA l OVDD – 0.2 V
VOL Low Level Output Voltage IOUT = 500μA l 0.2 V
IOZ Hi-Z Output Leakage Current VOUT = 0V to OVDD l –10 10 μA
ISOURCE Output Source Current VOUT = 0V –50 mA
ISINK Output Sink Current VOUT = OVDD 50 mA
LVDS Digital Inputs and Outputs
VID Differential Input Voltage l 200 350 600 mV
RID On-Chip Input Termination CS = 0V, VICM = 1.2V l 80 106 130 Ω
Resistance CS = OVDD 10 MΩ
VICM Common-Mode Input Voltage l 0.3 1.2 2.2 V
IICM Common-Mode Input Current VIN+ = VIN– = 0V to OVDD l –10 10 μA
VOD Differential Output Voltage RL = 100Ω Differential Termination l 275 350 425 mV
VOCM Common-Mode Output Voltage RL = 100Ω Differential Termination l 1.1 1.2 1.3 V
IOZ Hi-Z Output Leakage Current VOUT = 0V to OVDD l –10 10 μA

234516f

For more information www.linear.com/LTC2345-16 5

LTC2345-16
Power Requirements The l denotes the specifications which apply over the full operating temperature
range, otherwise specifications are at TA = 25°C. (Note 8)
SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS
CMOS I/O Mode
VDD Supply Voltage l 4.75 5.00 5.25 V
OVDD Supply Voltage l 1.71 5.25 V
IVDD Supply Current 200ksps Sample Rate, 8 Channels Enabled l 15.3 17.6 mA
200ksps Sample Rate, 8 Channels Enabled, VREFBUF = 5V (Note 14) l 13.7 15.8 mA
Acquisition Mode l 1.3 2.1 mA
Power Down Mode (C-Grade and I-Grade) l 65 225 μA
Power Down Mode (H-Grade) l 65 500 µA
IOVDD Supply Current 200ksps Sample Rate, 8 Channels Enabled (CL = 25pF) l 1.8 2.6 mA
Acquisition Mode l 1 20 μA
Power Down Mode l 1 20 μA
PD Power Dissipation 200ksps Sample Rate, 8 Channels Enabled l 81 95 mW
Acquisition Mode l 6.5 11 mW
Power Down Mode (C-Grade and I-Grade) l 0.33 1.2 mW
Power Down Mode (H-Grade) l 0.33 2.6 mW
LVDS I/O Mode
VDD Supply Voltage l 4.75 5.00 5.25 V
OVDD Supply Voltage l 2.375 5.25 V
IVDD Supply Current 200ksps Sample Rate, 8 Channels Enabled l 17.9 20.6 mA
200ksps Sample Rate, 8 Channels Enabled, VREFBUF = 5V (Note 14) l 16.2 18.6 mA
Acquisition Mode l 2.8 3.8 mA
Power Down Mode (C-Grade and I-Grade) l 65 225 μA
Power Down Mode (H-Grade) l 65 500 µA
IOVDD Supply Current 200ksps Sample Rate, 8 Channels Enabled (RL = 100Ω) l 7 8.5 mA
Acquisition or (RL = 100Ω) l 7 8.0 mA
Power Down Mode l 1 20 μA
PD Power Dissipation 200ksps Sample Rate, 8 Channels Enabled l 107 125 mW
Acquisition Mode l 32 39 mW
Power Down Mode (C-Grade and I-Grade) l 0.33 1.2 mW
Power Down Mode (H-Grade) l 0.33 2.6 mW

ADC Timing Characteristics The l denotes the specifications which apply over the full operating
temperature range, otherwise specifications are at TA = 25°C. (Note 8)
SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS
fSMPL Maximum Sampling Frequency 8 Channels Enabled l 200 ksps
7 Channels Enabled l 225 ksps
6 Channels Enabled l 266 ksps
5 Channels Enabled l 300 ksps
4 Channels Enabled l 375 ksps
3 Channels Enabled l 450 ksps
2 Channels Enabled l 625 ksps
1 Channel Enabled l 1000 ksps
tCYC Time Between Conversions 8 Channels Enabled, fSMPL = 200ksps l 5000 ns
7 Channels Enabled, fSMPL = 225ksps l 4444 ns
6 Channels Enabled, fSMPL = 266ksps l 3750 ns
5 Channels Enabled, fSMPL = 300ksps l 3333 ns
4 Channels Enabled, fSMPL = 375ksps l 2666 ns
3 Channels Enabled, fSMPL = 450ksps l 2222 ns
2 Channels Enabled, fSMPL = 625ksps l 1600 ns
1 Channel Enabled, fSMPL = 1000ksps l 1000 ns

234516f

6 For more information www.linear.com/LTC2345-16

 LTC2345-16
ADC Timing Characteristics The l denotes the specifications which apply over the full operating
temperature range, otherwise specifications are at TA = 25°C. (Note 8)
SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS
tCONV Conversion Time N Channels Enabled, 1 ≤ N ≤ 8 l 455 • N – 35 505 • N – 35 555 • N – 35 ns
tACQ Acquisition Time 8 Channels Enabled, fSMPL = 200ksps l 565 975 ns
(tACQ = tCYC – tCONV – tBUSYLH) 7 Channels Enabled, fSMPL = 225ksps l 564 924 ns
6 Channels Enabled, fSMPL = 266ksps l 425 735 ns
5 Channels Enabled, fSMPL = 300ksps l 563 823 ns
4 Channels Enabled, fSMPL = 375ksps l 451 661 ns
3 Channels Enabled, fSMPL = 450ksps l 562 722 ns
2 Channels Enabled, fSMPL = 625ksps l 495 605 ns
1 Channel Enabled, fSMPL = 1000ksps l 450 510 ns
tCNVH CNV High Time l 40 ns
tCNVL CNV Low Time l 420 ns
tBUSYLH CNV↑ to BUSY Delay CL = 25pF l 30 ns
tQUIET Digital I/O Quiet Time from CNV↑ l 20 ns
tPDH PD High Time l 40 ns
tPDL PD Low Time l 40 ns
tWAKE REFBUF Wake-Up Time CREFBUF = 47μF, CREFIN = 0.1μF 200 ms
CMOS I/O Mode
tSCKI SCKI Period (Notes 16, 17) l 10 ns
tSCKIH SCKI High Time l 4 ns
tSCKIL SCKI Low Time l 4 ns
tSSDISCKI SDI Setup Time from SCKI↑ (Note 16) l 2 ns
tHSDISCKI SDI Hold Time from SCKI↑ (Note 16) l 1 ns
tDSDOSCKI SDO Data Valid Delay from SCKI↑ CL = 25pF (Note 16) l 7.5 ns
tHSDOSCKI SDO Remains Valid Delay from SCKI↑ CL = 25pF (Note 16) l 1.5 ns
tSKEW SDO to SCKO Skew (Note 16) l –1 0 1 ns
tDSDOBUSYL SDO Data Valid Delay from BUSY↓ CL = 25pF (Note 16) l 0 ns
tEN Bus Enable Time After CS↓ (Note 16) l 15 ns
tDIS Bus Relinquish Time After CS↑ (Note 16) l 15 ns
LVDS I/O Mode
tSCKI SCKI Period (Note 18) l 4 ns
tSCKIH SCKI High Time (Note 18) l 1.5 ns
tSCKIL SCKI Low Time (Note 18) l 1.5 ns
tSSDISCKI SDI Setup Time from SCKI (Notes 10, 18) l 1.2 ns
tHSDISCKI SDI Hold Time from SCKI (Notes 10, 18) l –0.2 ns
tDSDOSCKI SDO Data Valid Delay from SCKI (Notes 10, 18) l 6 ns
tHSDOSCKI SDO Remains Valid Delay from SCKI (Notes 10, 18) l 1 ns
tSKEW SDO to SCKO Skew (Note 10) l –0.4 0 0.4 ns
tDSDOBUSYL SDO Data Valid Delay from BUSY↓ (Note 10) l 0 ns
tEN Bus Enable Time After CS↓ l 50 ns
tDIS Bus Relinquish Time After CS↑ l 15 ns

234516f

For more information www.linear.com/LTC2345-16 7

LTC2345-16
ADC Timing Characteristics
Note 1: Stresses beyond those listed under Absolute Maximum Ratings Note 10: Guaranteed by design, not subject to test.
may cause permanent damage to the device. Exposure to any Absolute Note 11: For bipolar SoftSpan ranges 7, 6, 3, and 2, zero-scale error is
Maximum Rating condition for extended periods may affect device the offset voltage measured from –0.5LSB when the output code flickers
reliability and lifetime. between 0000 0000 0000 0000 and 1111 1111 1111 1111. Full-scale
Note 2: All voltage values are with respect to ground. error for these SoftSpan ranges is the worst-case deviation of the first and
Note 3: VDDLBYP is the output of an internal voltage regulator, and should last code transitions from ideal and includes the effect of offset error. For
only be connected to a 2.2μF ceramic capacitor to bypass the pin to GND, unipolar SoftSpan ranges 5, 4, and 1, zero-scale error is the offset voltage
as described in the Pin Functions section. Do not connect this pin to any measured from 0.5LSB when the output code flickers between 0000 0000
external circuitry. 0000 0000 and 0000 0000 0000 0001. Full-scale error for these SoftSpan
Note 4: When these pin voltages are taken below ground or above VDD or ranges is the worst-case deviation of the last code transition from ideal
OVDD, they will be clamped by internal diodes. This product can handle and includes the effect of offset error.
currents of up to 100mA below ground or above VDD or OVDD without Note 12: All specifications in dB are referred to a full-scale input in the
latch-up. relevant SoftSpan input range, except for crosstalk, which is referred to
Note 5: VDD = 5V unless otherwise specified. the crosstalk injection signal amplitude.
Note 6: Recommended operating conditions. Note 13: Temperature coefficient is calculated by dividing the maximum
change in output voltage by the specified temperature range.
Note 7: Exceeding these limits on any channel may corrupt conversion
results on other channels. Refer to Absolute Maximum Ratings section for Note 14: When REFBUF is overdriven, the internal reference buffer must
pin voltage limits related to device reliability. be disabled by setting REFIN = 0V.
Note 8: VDD = 5V, OVDD = 2.5V, fSMPL = 200ksps, internal reference and Note 15: IREFBUF varies proportionally with sample rate and the number of
buffer, fully differential input signal drive in SoftSpan ranges 7 and 6, active channels.
bipolar input signal drive in SoftSpan ranges 3 and 2, unipolar input signal Note 16: Parameter tested and guaranteed at OVDD = 1.71V, OVDD = 2.5V,
drive in SoftSpan ranges 5, 4 and 1, unless otherwise specified. and OVDD = 5.25V.
Note 9: Integral nonlinearity is defined as the deviation of a code from a Note 17: A tSCKI period of 10ns minimum allows a shift clock frequency of
straight line passing through the actual endpoints of the transfer curve. up to 100MHz for rising edge capture.
The deviation is measured from the center of the quantization band. Note 18: VICM = 1.2V, VID = 350mV for LVDS differential input pairs.

CMOS Timings

0.8 • OVDD
tWIDTH
0.2 • OVDD

tDELAY tDELAY 50% 50%

0.8 • OVDD 0.8 • OVDD 234516 F01

0.2 • OVDD 0.2 • OVDD

LVDS Timings (Differential)

+200mV
tWIDTH
–200mV

tDELAY tDELAY 0V 0V

+200mV +200mV 234516 F01b

–200mV –200mV

Figure 1. Voltage Levels for Timing Specifications

234516f

8 For more information www.linear.com/LTC2345-16

 LTC2345-16
Typical Performance Characteristics
TA = 25°C, VDD = 5V, OVDD = 2.5V, Internal
Reference and Buffer (VREFBUF = 4.096V), fSMPL = 200ksps, unless otherwise noted.

Integral Nonlinearity Differential Nonlinearity Integral Nonlinearity

vs Output Code and Channel vs Output Code and Channel vs Output Code and Range
1.00 1.00 1.00
±4.096V RANGE ALL RANGES BIPOLAR DRIVE (IN– = 2.5V)
0.75 FULLY DIFFERENTIAL DRIVE (IN– = –IN+) 0.75 ALL CHANNELS 0.75 ONE CHANNEL
ALL CHANNELS
0.50 0.50 0.50

DNL ERROR (LSB)

INL ERROR (LSB)

INL ERROR (LSB)

0.25 0.25 0.25 ±2.048V AND ±2V
RANGES
0 0 0

–0.25 –0.25 –0.25

–0.50 –0.50 –0.50

–0.75 –0.75 –0.75

–1.00 –1.00 –1.00

–32768 –16384 0 16384 32768 0 16384 32768 49152 65536 –32768 –16384 0 16384 32768
OUTPUT CODE OUTPUT CODE OUTPUT CODE
234516 G01 234516 G02 234516 G03

Integral Nonlinearity Integral Nonlinearity Integral Nonlinearity

vs Output Code and Range vs Output Code and Range vs Output Code
1.00 1.00 1.00
FULLY DIFFERENTIAL DRIVE (IN– = –IN+) UNIPOLAR DRIVE (IN– = 0V) ±4.096V RANGE
0.75 ONE CHANNEL 0.75 ONE CHANNEL 0.75
ARBITRARY DRIVE
0V TO 2.048V RANGE IN+/IN– COMMON MODE
0.50 0.50 0.50
±2.048V AND ±2V
SWEPT 0V TO 5V
RANGES
INL ERROR (LSB)
INL ERROR (LSB)

INL ERROR (LSB)

0.25 0.25 0.25

0 0 0
0V TO 4.096V AND 0V TO 4V RANGES
–0.25 –0.25 –0.25
±4.096V AND ±4V
–0.50 RANGES –0.50 –0.50
FULLY DIFFERENTIAL DRIVE (IN– = –IN+)
–0.75 –0.75 –0.75

–1.00 –1.00 –1.00

–32768 –16384 0 16384 32768 0 16384 32768 49152 65536 –32768 –16384 0 16384 32768
OUTPUT CODE OUTPUT CODE OUTPUT CODE
234516 G04 234516 G05 234516 G06

32k Point FFT fSMPL = 200kHz,

DC Histogram (Zero-Scale) DC Histogram (Near Full-Scale) fIN = 2kHz
200000 200000 0
±4.096V RANGE ±4.096V RANGE ±4.096V RANGE
–20 FULLY DIFFERENTIAL DRIVE (IN– = –IN+)
160000 160000 –40 SNR = 91.1dB
THD = –111dB
AMPLITUDE (dBFS)

–60 SINAD = 91.1dB

120000 120000 SFDR = 112dB
COUNTS

–80
COUNTS

–100
80000 80000
–120

40000 –140
40000
–160

0 0 –180
–4 –3 –2 –1 0 1 2 3 4 32753 32755 32757 32759 32761 0 20 40 60 80 100
CODE CODE FREQUENCY (KHz)
234516 G07 234516 G08 234516 G09

234516f

For more information www.linear.com/LTC2345-16 9

LTC2345-16
Typical Performance Characteristics
TA = 25°C, VDD = 5V, OVDD = 2.5V, Internal
Reference and Buffer (VREFBUF = 4.096V), fSMPL = 200ksps, unless otherwise noted.
32k Point Arbitrary Two-Tone FFT
fSMPL = 200kHz, IN+ = –7dBFS 2kHz 32k Point FFT fSMPL = 200kHz, SNR, SINAD vs VREFBUF,
Sine, IN– = –7dBFS 3.1kHz Sine fIN = 2kHz fIN = 2kHz
0 0 96
±4.096V RANGE 0V TO 4.096V RANGE ±VREFBUF RANGE
–20 ARBITRARY DRIVE –20 UNIPOLAR DRIVE (IN– = 0V) FULLY DIFFERENTIAL DRIVE (IN– = –IN+)
SFDR = 120dB SNR = 85.8dB 94
–40 –40
SNR = 91.3dB THD = –111dB

AMPLITUDE (dBFS)
AMPLITUDE (dBFS)

–60 –60 SINAD = 85.8dB

SNR, SINAD (dBFS)

SNR
SFDR = 112dB 92
–80 –80
SINAD
–100 –100
90
–120 –120

–140 –140
88
–160 –160

–180 –180 86
0 20 40 60 80 100 0 20 40 60 80 100 2.5 3 3.5 4 4.5 5
FREQUENCY (kHz) FREQUENCY (kHz) REFBUF VOLTAGE (V)
234516 G10 234516 G11 234516 G12

THD, Harmonics vs VREFBUF, SNR, SINAD THD, Harmonics

fIN = 2kHz vs Input Frequency vs Input Frequency
–100 102 –70
±VREFBUF RANGE ±4.096V RANGE ±4.096V RANGE
–105 FULLY DIFFERENIAL DRIVE (IN– = –IN+) FULLY DIFFERENTIAL DRIVE (IN– = –IN+) FULLY DIFFERENTIAL DRIVE (IN– = –IN+)
98 –80
–110 THD
THD, HARMONICS (dBFS)

THD, HARMONICS (dBFS)

SNR, SINAD (dBFS)

94 –90
–115
SNR
2ND
–120 90 –100
SINAD THD
–125
3RD 86 –110
–130 2ND
82 –120
–135
3RD
–140 78 –130
2.5 3 3.5 4 4.5 5 100 1k 10k 100k 100 1k 10k 100k
REFBUF VOLTAGE (V) FREQUENCY (Hz) FREQUENCY (Hz)
234516 G13 234516 G14 234516 G15

THD, Harmonics vs Input SNR, SINAD vs Input Level, CMRR vs Input Frequency and
Common Mode, fIN = 2kHz fIN = 2kHz Channel
–100 92.0 150
±4.096V RANGE ±4.096V RANGE ±4.096V RANGE
1VPP FULLY DIFFERENTIAL DRIVE FULLY DIFFERENTIAL DRIVE (IN– = –IN+) IN+ = IN– = 3.6Vpp SINE
–105 140
ALL CHANNELS
91.8
THD, HARMONICS (dBFS)

130
SNR
SNR, SINAD (dBFS)

–110
91.6
CMRR (dB)

THD 120
–115 SINAD
110
91.4
–120 3RD
100
91.2
–125 90
2ND
–130 91.0 80
0 1 2 3 4 5 –40 –30 –20 –10 0 10 100 1k 10k 100k 1M
INPUT COMMON MODE (V) INPUT LEVEL (dBFS) FREQUENCY (Hz)
234516 G16 234516 G17 234516 G18

234516f

10 For more information www.linear.com/LTC2345-16

 LTC2345-16
Typical Performance Characteristics
TA = 25°C, VDD = 5V, OVDD = 2.5V, Internal
Reference and Buffer (VREFBUF = 4.096V), fSMPL = 200ksps, unless otherwise noted.

Crosstalk vs Input Frequency and SNR, SINAD vs Temperature, THD, Harmonics vs Temperature,
Channel fIN = 2kHz fIN = 2kHz
–80 93.0 –105
±4.096V RANGE ±4.096V RANGE ±4.096V RANGE
–85 IN0+ = –IN0– = 3.6V FULLY DIFFERENTIAL DRIVE (IN– = –IN+) FULLY DIFFERENTIAL DRIVE (IN– = –IN+)
PP SINE 92.5
–90 ALL CHANNELS CONVERTING –110
92.0

THD, HARMONICS (dBFS)

–95

SNR, SINAD (dBFS)

–115
CROSSTALK (dB)

–100 CH1 91.5 THD

–105
91.0 SNR –120
–110 2ND
–115 90.5 SINAD
–125
–120 90.0
–125 –130 3RD
89.5
–130
CH7
–135 89.0 –135
10 100 1k 10k 100k 1M –55 –35 –15 5 25 45 65 85 105 125 –55 –35 –15 5 25 45 65 85 105 125
FREQUENCY (Hz) TEMPERATURE (°C) TEMPERATURE (°C)
234516 G19 234516 G20 234516 G21

Positive Full-Scale Error vs Negative Full-Scale Error vs

INL, DNL vs Temperature Temperature and Channel Temperature and Channel
0.5 0.100 0.100
±4.096V RANGE ±4.096V RANGE ±4.096V RANGE
0.4 FULLY DIFFERENTIAL DRIVE (IN– = –IN+) 0.075 ALL CHANNELS 0.075 ALL CHANNELS
0.3
0.050 0.050
FULL–SCALE ERROR (%)

FULL-SCALE ERROR (%)

INL, DNL ERROR (LSB)

0.2 MAX INL

0.025 0.025
0.1
MAX DNL
0.0 0.000 0.000
MIN DNL
–0.1 –0.025 –0.025
–0.2
MIN INL –0.050 –0.050
–0.3
–0.075 –0.075
–0.4
–0.5 –0.100 –0.100
–55 –35 –15 5 25 45 65 85 105 125 –55 –35 –15 5 25 45 65 85 105 125 –55 –35 –15 5 25 45 65 85 105 125
TEMPERATURE (°C) TEMPERATURE (°C) TEMPERATURE (°C)
234516 G22 234516 G23 234516 G24

Zero-Scale Error vs Power-Down Current

Temperature and Channel Supply Current vs Temperature vs Temperature
5 20 1000
±4.096V RANGE
4 18
ALL CHANNELS
16 IVDD IVDD
3 100
POWER-DOWN CURRENT (µA)
ZERO–SCALE ERROR (LSB)

14
SUPPLY CURRENT (mA)

2
12
1 10 10
0 8
–1 6 1
4
–2
2
–3 0.1 IOVDD
0 IOVDD
–4 –2
–5 –4 0.01
–55 –35 –15 5 25 45 65 85 105 125 –55 –35 –15 5 25 45 65 85 105 125 –55 –35 –15 5 25 45 65 85 105 125
TEMPERATURE (°C) TEMPERATURE (°C) TEMPERATURE (°C)
234516 G25 234516 G26 234516 G27

234516f

For more information www.linear.com/LTC2345-16 11

LTC2345-16
Typical Performance Characteristics
TA = 25°C, VDD = 5V, OVDD = 2.5V, Internal
Reference and Buffer (VREFBUF = 4.096V), fSMPL = 200ksps, unless otherwise noted.

Offset Error vs Input Common Internal Reference Output

Mode and Channel vs Temperature PSRR vs Frequency
1.0 2.052 150
±4.096V RANGE 15 UNITS IN+ = IN– = 0V
0.8 ALL CHANNELS 140 OVDD
2.051

INTERNAL REFERENCE OUTPUT (V)

0.6 130
2.050
0.4
OFFSET ERROR (LSB)

120
0.2 2.049 110

PSRR (dB)
0.0 2.048 100
–0.2 90
2.047
–0.4 80
2.046
–0.6 70 VDD
–0.8 2.045 60
–1.0 2.044 50
0 1 2 3 4 5 –55 –35 –15 5 25 45 65 85 105 125 10 100 1k 10k 100k 1M
INPUT COMMON MODE (V) TEMPERATURE (°C) FREQUENCY (Hz)
234516 G28 234516 G29 234516 G30

Power Dissipation vs Sampling

Supply Current vs Sampling Rate Rate, N Channels Enabled
18 90

16 80 N=8 N=4
N=2
14 70
POWER DISSIPATION (mW)

N=1
SUPPLY CURRENT (mA)

IVDD
12 60

10 50

8 40

6 30

4 20

2 10
IOVDD
0 0
0 40 80 120 160 200 0 200 400 600 800 1000
SAMPLING FREQUENCY (kHz) SAMPLING FREQUENCY (kHz)
234516 G31 234516 G32

Step Response
(Large-Signal Settling) Step Response (Fine Settling)
32768 100
80
DEVIATION FROM FINAL VALUE (LSB)

24576
60
16384
40
OUTPUT CODE (LSB)

8192 20
±2.048V RANGE
IN+ = 200.0061kHz SQUARE WAVE 0
0
IN– = 2.048V
DRIVEN BY 50Ω SOURCE –20
–8192
±2.048V RANGE
–40 IN+ = 200.0061kHz
–16384
–60 SQUARE WAVE
IN– = 2.048V
–24576 –80 DRIVEN BY 50Ω SOURCE
–32768 –100
–50 0 50 100 150 200 250 300 350 400 450 –50 0 50 100 150 200 250 300 350 400 450
SETTLING TIME (ns) SETTLING TIME (ns)
234516 G33 234516 G34

234516f

12 For more information www.linear.com/LTC2345-16

 LTC2345-16
Pin Functions
Pins that are the Same for All Digital I/O Modes PD (Pin 22): Power Down Input. When this pin is brought
IN0+ to IN7+, IN0− to IN7− (Pins 1, 2, 3, 4, 5, 6, 7, 8, 9, high, the LTC2345-16 is powered down and subsequent
10, 11, 12, 13, 14, 47, and 48): Positive and Negative conversion requests are ignored. If this occurs during a
Analog Inputs, Channels 0 to 7. The converter simultane- conversion, the device powers down once the conversion
ously samples and digitizes (VIN+ – VIN–) for all channels. completes. If this pin is brought high twice without an
Wide input common mode range (0V ≤ VCM ≤ VDD) and intervening conversion, an internal global reset is initi-
high common mode rejection allow the inputs to accept ated, equivalent to a power-on-reset event. Logic levels
are determined by OVDD.
a wide variety of signal swings. Full-scale input range is
determined by the channel’s SoftSpan configuration. LVDS/CMOS (Pin 23): I/O Mode Select. Tie this pin to OVDD
to select LVDS I/O mode, or to ground to select CMOS I/O
GND (Pins 15, 16, 17, 18, 20, 30, 41, 44, 45, 46, 49):
mode. Logic levels are determined by OVDD.
Ground. Solder all GND pins to a solid ground plane.
CNV (Pin 24): Conversion Start Input. A rising edge on
REFIN (Pin 19): Bandgap Reference Output/Reference
this pin puts the internal sample-and-holds into the hold
Buffer Input. An internal bandgap reference nominally
mode and initiates a new conversion. CNV is not gated
outputs 2.048V on this pin. An internal reference buffer
by CS, allowing conversions to be initiated independent
amplifies VREFIN to create the converter master reference
voltage VREFBUF = 2 • VREFIN on the REFBUF pin. When of the state of the serial I/O bus.
using the internal reference, bypass REFIN to GND (Pin BUSY (Pin 38): Busy Output. The BUSY signal indicates
20) close to the pin with a 0.1μF ceramic capacitor to filter that a conversion is in progress. This pin transitions low-
the bandgap output noise. If more accuracy is desired, to-high at the start of each conversion and stays high until
overdrive REFIN with an external reference in the range the conversion is complete. Logic levels are determined
of 1.25V to 2.2V. by OVDD.
REFBUF (Pin 21): Internal Reference Buffer Output. An VDDLBYP (Pin 40): Internal 2.5V Regulator Bypass Pin. The
internal reference buffer amplifies VREFIN to create the voltage on this pin is generated via an internal regulator
converter master reference voltage VREFBUF = 2 • VREFIN on operating off of VDD. This pin must be bypassed to GND
this pin, nominally 4.096V when using the internal bandgap close to the pin with a 2.2μF ceramic capacitor. Do not
reference. Bypass REFBUF to GND (Pin 20) close to the connect this pin to any external circuitry.
pin with a 47μF ceramic capacitor. The internal reference VDD (Pins 42, 43): 5V Power Supply. The range of VDD
buffer may be disabled by grounding its input at REFIN. is 4.75V to 5.25V. Connect Pins 42 and 43 together and
With the buffer disabled, overdrive REFBUF with an ex- bypass the VDD network to GND with a shared 0.1μF
ternal reference voltage in the range of 2.5V to 5V. When
ceramic capacitor close to the pins.
using the internal reference buffer, limit the loading of any
external circuitry connected to REFBUF to less than 10µA.
Using a high input impedance amplifier to buffer VREFBUF
to any external circuits is recommended.

234516f

For more information www.linear.com/LTC2345-16 13

LTC2345-16
Pin Functions
CMOS I/O Mode LVDS I/O Mode
SDO0 to SDO7 (Pins 25, 26, 27, 28, 33, 34, 35, and 36): SDO0, SDO7, SDI (Pins 25, 36 and 37): CMOS Serial
CMOS Serial Data Outputs, Channels 0 to 7. The most Data I/O. In LVDS I/O mode, these pins are Hi-Z.
recent conversion result along with channel configuration
SDI+, SDI– (Pins 26 and 27): LVDS Positive and Negative
information is clocked out onto the SDO pins on each ris- Serial Data Input. Differentially drive SDI+/SDI– with the
ing edge of SCKI. Output data formatting is described in desired 24-bit SoftSpan configuration word (see Table
the Digital Interface section. Leave unused SDO outputs 1a), latched on both the rising and falling edges of SCKI+/
unconnected. Logic levels are determined by OVDD. SCKI–. The SDI+/SDI– input pair is internally terminated
SCKI (Pin 29): CMOS Serial Clock Input. Drive SCKI with with a 100Ω differential resistor when CS = 0.
the serial I/O clock. SCKI rising edges latch serial data in SCKI+, SCKI– (Pins 28 and 29): LVDS Positive and Negative
on SDI and clock serial data out on SDO0 to SDO7. For Serial Clock Input. Differentially drive SCKI+/SCKI– with
standard SPI bus operation, capture output data at the the serial I/O clock. SCKI+/SCKI– rising and falling edges
receiver on rising edges of SCKI. SCKI is allowed to idle latch serial data in on SDI+/SDI– and clock serial data out
either high or low. Logic levels are determined by OVDD. on SDO+/SDO–. Idle SCKI+/SCKI– low, including when
OVDD (Pin 31): I/O Interface Power Supply. In CMOS I/O transitioning CS. The SCKI+/SCKI– input pair is internally
mode, the range of OVDD is 1.71V to 5.25V. Bypass OVDD terminated with a 100Ω differential resistor when CS = 0.
to GND (Pin 30) close to the pin with a 0.1μF ceramic
OVDD (Pin 31): I/O Interface Power Supply. In LVDS I/O
capacitor. mode, the range of OVDD is 2.375V to 5.25V. Bypass OVDD
SCKO (Pin 32): CMOS Serial Clock Output. SCKI rising to GND (Pin 30) close to the pin with a 0.1μF ceramic
edges trigger transitions on SCKO that are skew-matched capacitor.
to the serial output data streams on SDO0 to SDO7. The SCKO+, SCKO– (Pins 32 and 33): LVDS Positive and
resulting SCKO frequency is half that of SCKI. Rising and Negative Serial Clock Output. SCKO+/SCKO– outputs a
falling edges of SCKO may be used to capture SDO data at copy of the input serial I/O clock received on SCKI+/SCKI–,
the receiver (FPGA) in double data rate (DDR) fashion. For skew-matched with the serial output data stream on SDO+/
standard SPI bus operation, SCKO is not used and should SDO–. Use the rising and falling edges of SCKO+/SCKO–
be left unconnected. SCKO is forced low at the falling edge to capture SDO+/SDO– data at the receiver (FPGA). The
of BUSY. Logic levels are determined by OVDD. SCKO+/SCKO– output pair must be differentially terminated
SDI (Pin 37): CMOS Serial Data Input. Drive this pin with the with a 100Ω resistor at the receiver (FPGA).
desired 24-bit SoftSpan configuration word (see Table 1a), SDO+, SDO– (Pins 34 and 35): LVDS Positive and Nega-
latched on the rising edges of SCKI. If all channels will be tive Serial Data Output. The most recent conversion result
configured to operate only in SoftSpan 7, tie SDI to OVDD. along with channel configuration information is clocked
Logic levels are determined by OVDD.
out onto SDO+/SDO– on both rising and falling edges of
CS (Pin 39): Chip Select Input. The serial data I/O bus is SCKI+/SCKI–, beginning with channel 0. The SDO+/SDO–
enabled when CS is low and is disabled and Hi-Z when output pair must be differentially terminated with a 100Ω
CS is high. CS also gates the external shift clock, SCKI. resistor at the receiver (FPGA).
Logic levels are determined by OVDD. CS (Pin 39): Chip Select Input. The serial data I/O bus is
enabled when CS is low, and is disabled and Hi-Z when
CS is high. CS also gates the external shift clock, SCKI+/
SCKI–. The internal 100Ω differential termination resistors
on the SCKI+/SCKI– and SDI+/SDI– input pairs are disabled
when CS is high. Logic levels are determined by OVDD.
234516f

14 For more information www.linear.com/LTC2345-16

 LTC2345-16
Configuration Tables
Table 1a. SoftSpan Configuration Table. Use This Table with Table 1b to Choose Independent Binary SoftSpan Codes SS[2:0] for Each
Channel Based on Desired Analog Input Range. Combine SoftSpan Codes to Form 24-Bit SoftSpan Configuration Word S[23:0]. Use
Serial Interface to Write SoftSpan Configuration Word to LTC2345-16, as shown in Figure 19
BINARY SoftSpan CODE BINARY FORMAT OF
ANALOG INPUT RANGE FULL SCALE RANGE
SS[2:0] CONVERSION RESULT
111 ±VREFBUF 2 • VREFBUF Two’s Complement
110 ±VREFBUF/1.024 2 • VREFBUF/1.024 Two’s Complement
101 0V to VREFBUF VREFBUF Straight Binary
100 0V to VREFBUF/1.024 VREFBUF/1.024 Straight Binary
011 ±0.5 • VREFBUF VREFBUF Two’s Complement
010 ±0.5 • VREFBUF/1.024 VREFBUF/1.024 Two’s Complement
001 0V to 0.5 • VREFBUF 0.5 • VREFBUF Straight Binary
000 Channel Disabled Channel Disabled All Zeros

Table 1b. Reference Configuration Table. The LTC2345-16 Supports Three Reference Configurations. Analog Input Range Scales with
the Converter Master Reference Voltage, VREFBUF
BINARY SoftSpan CODE
REFERENCE CONFIGURATION VREFIN VREFBUF ANALOG INPUT RANGE
SS[2:0]
111 ±4.096V
110 ±4V
101 0V to 4.096V
Internal Reference with
2.048V 4.096V 100 0V to 4V
Internal Buffer
011 ±2.048V
010 ±2V
001 0V to 2.048V
111 ±2.5V
110 ±2.441V
101 0V to 2.5V
1.25V
2.5V 100 0V to 2.441V
(Min Value)
011 ±1.25V
010 ±1.221V
External Reference with
Internal Buffer 001 0V to 1.25V
(REFIN Pin Externally 111 ±4.4V
Overdriven) 110 ±4.297V
101 0V to 4.4V
2.2V
4.4V 100 0V to 4.297V
(Max Value)
011 ±2.2V
010 ±2.148V
001 0V to 2.2V

234516f

For more information www.linear.com/LTC2345-16 15

LTC2345-16
Configuration Tables
Table 1b. Reference Configuration Table (Continued). The LTC2345-16 Supports Three Reference Configurations. Analog Input Range
Scales with the Converter Master Reference Voltage, VREFBUF
BINARY SoftSpan CODE
REFERENCE CONFIGURATION VREFIN VREFBUF ANALOG INPUT RANGE
SS[2:0]
111 ±2.5V
110 ±2.441V
101 0V to 2.5V
2.5V
0V 100 0V to 2.441V
(Min Value)
011 ±1.25V
External Reference 010 ±1.221V
Unbuffered
001 0V to 1.25V
(REFBUF Pin
111 ±5V
Externally Overdriven,
REFIN Pin Grounded) 110 ±4.883V
101 0V to 5V
5V
0V 100 0V to 4.883V
(Max Value)
011 ±2.5V
010 ±2.441V
001 0V to 2.5V

234516f

16 For more information www.linear.com/LTC2345-16

 LTC2345-16
Functional Block Diagram

CMOS I/O Mode

VDD VDDLBYP OVDD

LTC2345-16
IN0+
IN0– S/H
2.5V
+ REGULATOR SDO0
IN1
IN1– S/H

• • •
IN2+

IN2– S/H CMOS SDO7

16-BIT
8-CHANNEL MULTIPLEXER

16 BITS SERIAL
IN3+ SAR ADC SCKO
I/O
S/H INTERFACE
IN3– SDI

IN4+ SCKI

IN4– S/H CS

IN5+

IN5– S/H

IN6+
REFERENCE
IN6– S/H BUFFER
2.048V 20k CONTROL BUSY
IN7+ 2×
REFERENCE LOGIC
IN7– S/H

GND REFIN REFBUF CNV PD LVDS/CMOS

234516 BD01

234516f

For more information www.linear.com/LTC2345-16 17

LTC2345-16
Functional Block Diagram

LVDS I/O Mode

VDD VDDLBYP OVDD

LTC2345-16
+
IN0
IN0– S/H
2.5V SDO+
+ REGULATOR
IN1
SDO–
IN1– S/H
SCKO+
IN2+
SCKO–
S/H LVDS
IN2–
16-BIT SERIAL SDI+
8-CHANNEL MULTIPLEXER

16 BITS
IN3+ SAR ADC I/O
INTERFACE SDI–
IN3– S/H
SCKI+
IN4+
SCKI–
IN4– S/H
CS
IN5+

IN5– S/H

IN6+
REFERENCE
IN6– S/H BUFFER
2.048V 20k CONTROL BUSY
IN7+ 2×
REFERENCE LOGIC
IN7– S/H

GND REFIN REFBUF CNV PD LVDS/CMOS

234516 BD02

234516f

18 For more information www.linear.com/LTC2345-16

 LTC2345-16
Timing Diagram
CMOS I/O Mode
CS = PD = 0
SAMPLE N SAMPLE N + 1
CNV

BUSY CONVERT ACQUIRE

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24
SCKI

SDI DON’T CARE S23 S22 S21 S20 S19 S18 S17 S16 S15 S14 S13 S12 S11 S10 S9 S8 S7 S6 S5 S4 S3 S2 S1 S0

SoftSpan CONFIGURATION WORD FOR CONVERSION N + 1

SCKO

SDO0 DON’T CARE D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 0 0 C2 C1 C0 SS2 SS1 SS0 D15

CONVERSION RESULT CHANNEL ID SoftSpan CONVERSION RESULT

• • •

CHANNEL 0 CHANNEL 1
CONVERSION N CONVERSION N

SDO7 DON’T CARE D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 0 0 C2 C1 C0 SS2 SS1 SS0 D15

CONVERSION RESULT CHANNEL ID SoftSpan CONVERSION RESULT

CHANNEL 7 CHANNEL 0
CONVERSION N CONVERSION N
234516 TD01

LVDS I/O Mode

CS = PD = 0
SAMPLE
SAMPLE N N+1
CNV
(CMOS)
BUSY
ACQUIRE
(CMOS) CONVERT
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 186 187 188 189 190 191 192
SCKI
(LVDS)

SDI
DON’T CARE S23 S22 S21 S20 S19 S18 S17 S16 S15 S14 S13 S12 S11 S10 S9 S8 S7 S6 S5 S4 S3 S2 S1 S0
(LVDS)

SoftSpan CONFIGURATION WORD FOR CONVERSION N + 1

SCKO
(LVDS)
SDO
(LVDS) DON’T CARE D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 0 0 C2 C1 C0 SS2 SS1 SS0 D15 D14 D13 0 C2 C1 C0 SS2 SS1 SS0 D15
CONVERSION
CONVERSION RESULT CHANNEL ID SoftSpan CHANNEL ID SoftSpan
RESULT
CHANNEL 0 CHANNEL 1 CHANNEL 7 CHANNEL 0
CONVERSION N CONVERSION N CONVERSION N CONVERSION N
234516 TD02

234516f

For more information www.linear.com/LTC2345-16 19

LTC2345-16
Applications Information
Overview tions all channels’ S/H circuits from track mode to hold
mode, simultaneously sampling the input signals on all
The LTC2345-16 is a 16-bit, low noise 8-channel simul-
channels and initiating a conversion. During the conversion
taneous sampling successive approximation register
phase, each channel’s sampling capacitors are connected,
(SAR) ADC with differential, wide common mode range
inputs. Using the integrated low-drift reference and buffer one channel at a time, to a 16-bit charge redistribution
(VREFBUF = 4.096V nominal), each channel of this SoftSpan capacitor D/A converter (CDAC). The CDAC is sequenced
ADC can be independently configured on a conversion- through a successive approximation algorithm, effectively
by-conversion basis to accept ±4.096V, 0V to 4.096V, comparing the sampled input voltage with binary-weighted
±2.048V, or 0V to 2.048V signals. The input signal range fractions of the channel’s SoftSpan full-scale range
may be expanded up to ±5V using an external 5V refer- (e.g., VFSR/2, VFSR/4 … VFSR/65536) using a differential
comparator. At the end of this process, the CDAC output
ence. Individual channels may also be disabled to increase
approximates the channel’s sampled analog input. Once
throughput on the remaining channels.
all channels have been converted in this manner, the ADC
The wide input common mode range and high CMRR control logic prepares the 16-bit digital output codes from
(102dB typical, VIN+ = VIN– = 3.6VP-P 200Hz Sine) of the each channel for serial transfer.
LTC2345-16 analog inputs allow the ADC to directly digi-
tize a variety of signals, simplifying signal chain design.
Transfer Function
This input signal flexibility, combined with ±1.25LSB INL,
no missing codes at 16-bits, and 91dB SNR, makes the The LTC2345-16 digitizes each channel’s full-scale voltage
LTC2345-16 an ideal choice for many applications requir- range into 216 levels. In conjunction with the ADC master
ing wide dynamic range. reference voltage, VREFBUF, a channel’s SoftSpan configu-
ration determines its input voltage range, full-scale range,
The LTC2345-16 supports pin-selectable SPI CMOS (1.8V LSB size, and the binary format of its conversion result, as
to 5V) and LVDS serial interfaces, enabling it to com- shown in Tables 1a and 1b. For example, employing the
municate equally well with legacy microcontrollers and
internal reference and buffer (VREFBUF = 4.096V nominal),
modern FPGAs. In CMOS mode, applications may employ SoftSpan 7 configures a channel to accept a ±4.096V bi-
between one and eight lanes of serial output data, allowing polar analog input voltage range, which corresponds to a
the user to optimize bus width and data throughput. The 8.192V full-scale range with a 125μV LSB. Other SoftSpan
LTC2345-16 typically dissipates 81mW when converting configurations and reference voltages may be employed to
eight analog input channels simultaneously at 200ksps convert both larger and smaller bipolar and unipolar input
per channel throughput. An optional power-down mode ranges. Conversion results are output in two’s comple-
may be employed to further reduce power consumption ment binary format for all bipolar SoftSpan ranges, and
during inactive periods. in straight binary format for all unipolar SoftSpan ranges.
The ideal two’s complement transfer function is shown in
Converter Operation Figure 2, while the ideal straight binary transfer function
The LTC2345-16 operates in two phases. During the ac- is shown in Figure 3.
quisition phase, the sampling capacitors in each channel’s
sample-and-hold (S/H) circuit connect to their respective
analog input pins and track the differential analog input
voltage (VIN+ – VIN–). A rising edge on the CNV pin transi-

234516f

20 For more information www.linear.com/LTC2345-16

 LTC2345-16
Applications Information
high CMRR allows the IN+/IN– analog inputs to swing
011...111
with an arbitrary relationship to each other, provided
OUTPUT CODE (TWO’S COMPLEMENT)

011...110 BIPOLAR
ZERO each pin remains between ground and VDD. This unique
000...001 feature of the LTC2345-16 enables it to accept a wide
000...000 variety of signal swings, including traditional classes of
111...111 analog input signals such as pseudo-differential unipolar,
111...110
pseudo-differential bipolar, and fully differential, simplify-
100...001
ing signal chain design.
FSR = +FS – –FS
100...000 1LSB = FSR/65536 In all SoftSpan ranges, each channel’s analog inputs can
–FSR/2 –1 0V 1 FSR/2 – 1LSB
be modeled by the equivalent circuit shown in Figure 4.
LSB LSB
INPUT VOLTAGE (V)
At the start of acquisition, the 40pF sampling capacitors
(CIN) connect to the analog input pins IN+/IN– through the
234516 F02

Figure 2. LTC2345-16 Two’s Complement Transfer Function sampling switches, each of which has approximately 130Ω
(RIN) of on-resistance. The initial voltage on both sampling
capacitors at the start of acquisition is approximately equal
111...111 to the sampled common-mode voltage (VIN+ + VIN–)/2
OUTPUT CODE (STRAIGHT BINARY)

111...110
from the prior conversion. The external circuitry connected
100...001
to IN+ and IN– must source or sink the charge that flows
100...000 through RIN as the sampling capacitors settle from their
011...111 UNIPOLAR initial voltages to the new input pin voltages over the course
ZERO
011...110 of the acquisition interval. During conversion and power
down modes, the analog inputs draw only a small leakage
000...001 FSR = +FS current. The diodes at the inputs provide ESD protection.
000...000 1LSB = FSR/65536

0V FSR – 1LSB
INPUT VOLTAGE (V) 235816 F03

VDD
CIN
Figure 3. LTC2345-16 Straight Binary Transfer Function RIN 40pF
130Ω
IN+

Analog Inputs BIAS

VDD VOLTAGE
Each channel of the LTC2345-16 simultaneously samples CIN
RIN 40pF
the voltage difference (VIN+ – VIN–) between its analog 130Ω
IN– 234516 F04

input pins over a wide common mode input range while

attenuating unwanted signals common to both input
pins by the common-mode rejection ratio (CMRR) of
Figure 4. Equivalent Circuit for Differential Analog Inputs,
the ADC. Wide common mode input range coupled with Single Channel Shown

234516f

For more information www.linear.com/LTC2345-16 21

LTC2345-16
Applications Information
Bipolar SoftSpan Input Ranges The LTC2345-16 sampling network RC time constant of
5.2ns implies a 16-bit settling time to a full-scale step of
For channels configured in SoftSpan ranges 7, 6, 3, or
approximately 11 • (RIN • CIN) = 57ns. The impedance and
2, the LTC2345-16 digitizes the differential analog input
self-settling of external circuitry connected to the analog
voltage (VIN+ – VIN–) over a bipolar span of ±VREFBUF,
±VREFBUF/1.024, ±0.5 • VREFBUF, or ±0.5 • VREFBUF/1.024, input pins will increase the overall settling time required.
respectively, as shown in Table 1a. These SoftSpan ranges Low impedance sources can directly drive the inputs of
are useful for digitizing input signals where IN+ and IN– the LTC2345-16 without gain error, but high impedance
swing above and below each other. Traditional examples sources should be buffered to ensure sufficient settling
include fully differential input signals, where IN+ and during acquisition and to optimize the linearity and distor-
tion performance of the ADC. Settling time is an important
IN– are driven 180 degrees out-of-phase with respect
to each other centered around a common mode voltage consideration even for DC input signals, as the voltages on
the sampling capacitors will differ from the analog input
(VIN+ + VIN–)/2, and pseudo-differential bipolar input
signals, where IN+ swings above and below a reference pin voltages at the start of acquisition.
level, driven on IN–. Regardless of the chosen SoftSpan Most applications should use a buffer amplifier to drive the
range, the wide common mode input range and high CMRR analog inputs of the LTC2345-16. The amplifier provides
of the IN+/IN– analog inputs allow them to swing with an low output impedance, enabling fast settling of the analog
arbitrary relationship to each other, provided each pin signal during the acquisition phase. It also provides isola-
remains between ground and VDD. The output data format tion between the signal source and the charge flow at the
for all bipolar SoftSpan ranges is two’s complement. analog inputs when entering acquisition.

Unipolar SoftSpan Input Ranges Input Filtering

For channels configured in SoftSpan ranges 5, 4, or 1, the The noise and distortion of an input buffer amplifier and
LTC2345-16 digitizes the differential analog input voltage other supporting circuitry must be considered since they
(VIN+ – VIN–) over a unipolar span of 0V to VREFBUF, 0V add to the ADC noise and distortion. Noisy input signals
to VREFBUF/1.024, or 0V to 0.5 • VREFBUF, respectively, as should be filtered prior to the buffer amplifier with a low-
shown in Table 1a. These SoftSpan ranges are useful for bandwidth filter to minimize noise. The simple one-pole
digitizing input signals where IN+ remains above IN–. A RC lowpass filter shown in Figure 5 is sufficient for many
traditional example includes pseudo-differential unipolar applications.
input signals, where IN+ swings above a ground reference
At the output of the buffer, a lowpass RC filter network
level, driven on IN–. Regardless of the chosen SoftSpan
formed by the 130Ω sampling switch on-resistance (RIN)
range, the wide common mode range and high CMRR of and the 40pF sampling capacitance (CIN) limits the input
the IN+/IN– analog inputs allow them to swing with an bandwidth on each channel to 31MHz, which is fast enough
arbitrary relationship to each other, provided each pin
to allow for sufficient transient settling during acquisition
remains between ground and VDD. The output data format
while simultaneously filtering driver wideband noise. A
for all unipolar SoftSpan ranges is straight binary.
buffer amplifier with low noise density should be selected
to minimize SNR degradation over this bandwidth. An
Input Drive Circuits additional filter network may be placed between the buf-
The initial voltage on each channel’s sampling capacitors fer output and ADC input to further minimize the noise
at the start of acquisition must settle to the new input contribution of the buffer and reduce disturbances to the
pin voltages during the acquisition interval. The external buffer from ADC acquisition transients. A simple one-pole
circuitry connected to IN+ and IN– must source or sink lowpass RC filter is sufficient for many applications. It is
the charge that flows through RIN as this settling occurs. important that the RC time constant of this filter be small

234516f

22 For more information www.linear.com/LTC2345-16

 LTC2345-16
Applications Information
LOWPASS
SIGNAL FILTER
UNIPOLAR
160Ω
+
INPUT SIGNAL BUFFER
5V AMPLIFIER
– IN0+
10nF IN0–
0V LTC2345-16

BW = 100kHz

ONLY CHANNEL 0 SHOWN FOR CLARITY 234516 F05

Figure 5. Unipolar Signal Chain with Input Filtering

enough to allow the analog inputs to completely settle to design. In many applications, connecting a channel’s IN+
16-bit resolution within the ADC acquisition time (tACQ), and IN– pins directly to the existing signal chain circuitry
as insufficient settling can limit INL and THD performance. will not allow the channel’s sampling network to settle to
Also note that the minimum acquisition time varies with 16-bit resolution within the ADC acquisition time (tACQ). In
sampling frequency (fSMPL) and the number of enabled these cases, it is recommended that two unity-gain buffers
channels. be inserted between the signal source and the ADC input
High quality capacitors and resistors should be used in pins, as shown in Figure 6a. Table 2 lists several amplifier
the RC filters since these components can add distortion. and lowpass filter combinations recommended for use
NPO/COG and silver mica type dielectric capacitors have in this circuit. The LT6237 combines fast settling, high
excellent linearity. Carbon surface mount resistors can linearity, and low offset with 1.1nV/√Hz input-referred
generate distortion from self-heating and from damage noise density, enabling it to achieve the full ADC data
that may occur during soldering. Metal film surface mount sheet SNR and THD specifications, as shown in the FFT
resistors are much less susceptible to both problems. plots in Figures 6b to 6e. In applications where slightly
degraded SNR performance is acceptable, it is possible
Buffering Arbitrary and Fully Differential Analog Input to drive the LTC2345-16 using the lower-power LT6234.
Signals The LT6234 combines fast settling, good linearity, and
low offset with 1.9nV/√Hz input-referred noise density,
The wide common mode input range and high CMRR of enabling it to drive the LTC2345-16 with only 0.3dB SNR
the LTC2345-16 allow each channel’s IN+ and IN– pins loss compared with the LT6237 when a 40.2Ω, 1nF filter
to swing with an arbitrary relationship to each other, is employed. As shown in Table 2, the LT6237 may be
provided each pin remains between ground and VDD. This used without a lowpass filter at a loss of ≤1dB SNR due
unique feature of the LTC2345-16 enables it to accept a to increased wideband noise.
wide variety of signal swings, simplifying signal chain

Table 2. Recommended Amplifier and Filter Combinations for the Buffer Circuits in Figures 6a and 9. AC Performance Measured
Using Circuit in Figure 6a, ±4.096V Range for Fully Differential Input Drive, ±2.048V Range for Bipolar Input Drive
RFILT CFILT SNR THD SINAD SFDR
AMPLIFIER INPUT SIGNAL DRIVE
(Ω) (nF) (dB) (dB) (dB) (dB)
½ LT6237 40.2 1 FULLY DIFFERENTIAL 91.0 −114 91.0 115
½ LT6234 40.2 1 FULLY DIFFERENTIAL 90.7 −114 90.7 115
½ LT6237 40.2 1 BIPOLAR 85.8 −110 85.8 112
½ LT6234 40.2 1 BIPOLAR 85.5 −110 85.5 112
½ LT6237 0 0 BIPOLAR 85.4 −110 85.4 112
½ LT6234 0 0 BIPOLAR 82.1 −108 82.1 110
234516f

For more information www.linear.com/LTC2345-16 23

LTC2345-16
Applications Information
FULLY OPTIONAL
ARBITRARY DIFFERENTIAL 6V LOWPASS FILTERS
5V 5V –
RFILT
AMPLIFIER
IN+
+ CFILT
0V 0V IN0+
IN0–
BIPOLAR UNIPOLAR LTC2345-16
5V 5V IN– + CFILT
AMPLIFIER REFBUF REFIN
RFILT
0V 0V – 47µF 0.1µF
–2V
DIFFERENTIAL INPUTS IN+/IN– WITH
WIDE INPUT COMMON MODE RANGE
ONLY CHANNEL 0 SHOWN FOR CLARITY 234516 F06a

Figure 6a. Buffering Arbitrary, Fully Differential, Bipolar, and Unipolar Signals. See
Table 2 For Recommended Amplifier and Filter Combinations

Arbitrary Drive Fully Differential Drive

0 0
±4.096V RANGE ±4.096V RANGE
–20 ARBITRARY DRIVE –20 FULLY DIFFERENTIAL DRIVE (IN– = –IN+)
–40 SFDR = 120dB –40 SNR = 91.3dB
SNR = 91.3dB THD = –113dB
AMPLITUDE (dBFS)

–60
AMPLITUDE (dBFS)
–60 SINAD = 91.2dB
SFDR = 115dB
–80 –80
–100 –100
–120 –120
–140 –140
–160 –160
–180 –180
0 20 40 60 80 100 0 20 40 60 80 100
FREQUENCY (kHz) FREQUENCY (kHz)
234516 F06b 234516 F06c

Figure 6b. Two-Tone Test. IN+ = –7dBFS 2kHz Sine, IN – = Figure 6c. IN+/IN – = –1dBFS 2kHz Fully Differential Sine,
–7dBFS 3.1kHz Sine, Common Mode = 2.5V, 32k Point FFT, Common Mode = 2.5V, 32k Point FFT, fSMPL = 200ksps. Circuit
fSMPL = 200ksps. Circuit Shown in Figure 6a with LT6237 Shown in Figure 6a with LT6237 Amplifiers, RFILT = 40.2Ω,
Amplifiers, RFILT = 40.2Ω, CFILT = 1nF CFILT = 1nF

Bipolar Drive Unipolar Drive

0 0
±2.048V RANGE 0V TO 4.096V RANGE
–20 BIPOLAR DRIVE (IN– = 2.5V) –20 UNIPOLAR DRIVE (IN– = 0V)

–40 SNR = 86.0dB –40 SNR = 86.1dB

THD = –110dB THD = –109dB
SINAD = 86.0dB
AMPLITUDE (dBFS)

AMPLITUDE (dBFS)

–60 SINAD = 86.0dB –60

SFDR = 113dB SFDR = 110dB
–80 –80

–100 –100

–120 –120

–140 –140

–160 –160

–180 –180
0 20 40 60 80 100 0 20 40 60 80 100
FREQUENCY (kHz) FREQUENCY (kHz)
234516 F06d 234516 F06e

Figure 6d. IN+ = –1dBFS 2kHz Bipolar Sine, IN – = 2.5V, 32k Figure 6e. IN+ = –1dBFS 2kHz Unipolar Sine, IN – = 0V, 32k Point
Point FFT, fSMPL = 200ksps. Circuit Shown in Figure 6a with FFT, fSMPL = 200ksps. Circuit Shown in Figure 6a with LT6237
LT6237 Amplifiers, RFILT = 40.2Ω, CFILT = 1nF Amplifiers, RFILT = 40.2Ω, CFILT = 1nF
234516f

24 For more information www.linear.com/LTC2345-16

 LTC2345-16
Applications Information
The two-tone test shown in Figure 6b demonstrates the
IN0+
arbitrary input drive capability of the LTC2345-16. This test VS1 IN0–
simultaneously drives IN+ with a −7dBFS 2kHz single-ended LTC2345-16
IN1+
sine wave and IN− with a −7dBFS 3.1kHz single-ended sine RSENSE ISENSE
IN1–
wave. Together, these signals sweep the analog inputs REFBUF REFIN

across a wide range of common mode and differential VS2 47µF 0.1µF

mode voltage combinations, similar to the more general 234516 F07

arbitrary input signal case. They also have a simple spec-

tral representation. An ideal differential converter with no ONLY CHANNELS 0 AND 1 SHOWN FOR CLARITY
V – VS2 0V ≤ VS1 ≤ 5V
common-mode sensitivity will digitize this signal as two ISENSE = S1
RSENSE 0V ≤ VS2 ≤ 5V
−7dBFS spectral tones, one at each sine wave frequency.
The FFT plot in Figure 6b demonstrates the LTC2345-16 Figure 7. Simultaneously Sense Voltage (CH0) and Current
(CH1) Over a Wide Common Mode Range
response approaches this ideal, with 120dB of SFDR
limited by the converter's second harmonic distortion
response to the 2kHz sine wave on IN+.
5V

The ability of the LTC2345-16 to accept arbitrary signal

2.49k VDD
swings over a wide input common mode range with high IN0+
1Ω 274Ω IN0–
CMRR can simplify application solutions. Figure 7 depicts –
5V
LTC2345-16
one way of using the LTC2345-16 to digitize signals of +
ILOAD LTC6252
this type. Two channels of the LTC2345-16 simultaneously REFBUF REFIN
sense the voltage on and bidirectional current through a LOAD 47µF 0.1µF
sense resistor over a wide common mode range. In many ONLY CHANNEL 0 SHOWN FOR CLARITY
applications of this type, the impedance of the external 234516 F08a

circuitry is low enough that the ADC sampling network

Figure 8a. Sense 50mA to 450mA Current from Single 5V
can fully settle without buffering. Supply with Amplification
The common mode input range of the LTC2345-16 includes
VDD, allowing the circuit shown in Figure 8a to amplify and 200
measure a load current (ILOAD) from a single 5V supply. 0V TO 4.096V RANGE

Figure 8b shows a measured transient supply current 180

step of an LTC3207 LED driver load. Note the LTC6252

160
supplies limit the usable current sense range of this circuit
ILOAD (mA)

to 50mA to 450mA. 140

Figure 9a illustrates a more general method of amplifying 120

an input signal. The amplifier stage provides a differential
gain of approximately 10V/V to the desired sensor signal 100

while the unwanted common mode signal is attenuated 80

by the ADC CMRR. Figure 9b shows measured CMRR 0 10 20 30 40 50 60 70 80 90 100
TIME (µs)
performance of this solution, which is competitive with 234516 F08b

the best commercially available instrumentation amplifiers. Figure 8b. Transient Supply Current Step Measured Using
Circuit in Figure 8a Loaded with LTC3207 LED Driver

234516f

For more information www.linear.com/LTC2345-16 25

LTC2345-16
Applications Information
6V Buffering Single-Ended Analog Input Signals
IN+ + ½ LT6237 LOWPASS FILTERS
– 40.2Ω While the circuit shown in Figure 6a is capable of buffering
single-ended input signals, the circuit shown in Figure 10
2.49k
1nF is preferable when the single-ended signal reference level
549Ω
IN0+
IN0–
is inherently low impedance and doesn't require buffering.
2.49k
1nF
LTC2345-16 This circuit eliminates one driver and lowpass filter, reduc-
40.2Ω ing part count, power dissipation, and SNR degradation
– REFBUF REFIN
due to driver noise. Using the recommended driver and
IN–
+ ½ LT6237 BW ~ 4MHz
47µF 0.1µF
filter combinations in Table 2, the performance of this
–2V ONLY CHANNEL 0 SHOWN FOR CLARITY 234516 F09a
circuit with single-ended input signals is on par with the
performance of the circuit in Figure 6a.
Figure 9a. Digitize Differential Signals with High CMRR
ADC Reference
150
±4.096V RANGE As shown previously in Table 1b, the LTC2345-16 supports
IN+ = IN– = 5Vpp SINE
140 three reference configurations. The first uses both the in-
130 ternal bandgap reference and reference buffer. The second
externally overdrives the internal reference but retains the
CMRR (dB)

120
internal buffer, which isolates the external reference from
110
ADC conversion transients. This configuration is ideal
100 for sharing a single precision external reference across
90 multiple ADCs. The third disables the internal buffer and
80
overdrives the REFBUF pin externally.
10 100 1k 10k 100k
FREQUENCY (Hz)
234516 F09b Internal Reference with Internal Buffer
Figure 9b. CMRR vs Input Frequency. Circuit Shown in Figure 9a The LTC2345-16 has an on-chip, low noise, low drift
(20ppm/°C maximum), temperature compensated band-
gap reference that is factory trimmed to 2.048V. The
reference output connects through a 20kΩ resistor to

6V OPTIONAL
LOWPASS FILTER
IN+ + RFILT
UNIPOLAR
AMPLIFIER
5V
– CFILT IN0+
–2V IN0–
0V LTC2345-16

IN–
REFBUF REFIN

47µF 0.1µF

ONLY CHANNEL 0 SHOWN FOR CLARITY

234516 F10

Figure 10. Buffering Single-Ended Input Signals. See Table 2 For Recommended
Amplifier and Filter Combinations
234516f

26 For more information www.linear.com/LTC2345-16

 LTC2345-16
Applications Information
the REFIN pin, which serves as the input to the on-chip External Reference with Internal Buffer
reference buffer, as shown in Figure 11a. When employing If more accuracy and/or lower drift is desired, REFIN can
the internal bandgap reference, the REFIN pin should be be easily overdriven by an external reference since 20kΩ
bypassed to GND (Pin 20) close to the pin with a 0.1μF of resistance separates the internal bandgap reference
ceramic capacitor to filter wideband noise. The reference output from the REFIN pin, as shown in Figure 11b. The
buffer amplifies VREFIN to create the converter master valid range of external reference voltage overdrive on the
reference voltage VREFBUF = 2 • VREFIN on the REFBUF pin, REFIN pin is 1.25V to 2.2V, resulting in converter mas-
nominally 4.096V when using the internal bandgap refer- ter reference voltages VREFBUF between 2.5V and 4.4V,
ence. Bypass REFBUF to GND (Pin 20) close to the pin with respectively. Linear Technology offers a portfolio of high
at least a 47μF ceramic capacitor (X7R, 10V, 1210 size or performance references designed to meet the needs of
X5R, 10V, 0805 size) to compensate the reference buffer, many applications. With its small size, low power, and high
absorb transient conversion currents, and minimize noise. accuracy, the LTC6655-2.048 is well suited for use with the
LTC2345-16 when overdriving the internal reference. The
LTC6655-2.048 offers 0.025% (maximum) initial accuracy
and 2ppm/°C (maximum) temperature coefficient for high
LTC2345-16 precision applications. The LTC6655-2.048 is fully speci-
REFIN 20k BANDGAP fied over the H-grade temperature range, complementing
0.1µF
REFERENCE the extended temperature range of the LTC2345-16 up to
125°C. Bypassing the LTC6655-2.048 with a 2.7µF to 100µF
REFBUF REFERENCE
BUFFER
ceramic capacitor close to the REFIN pin is recommended.

47µF
6.5k External Reference with Disabled Internal Buffer
6.5k The internal reference buffer supports VREFBUF = 4.4V
GND maximum. By grounding REFIN, the internal buffer may
234516 F11a
be disabled allowing REFBUF to be overdriven with an
external reference voltage between 2.5V and 5V, as shown
Figure 11a. Internal Reference with Internal Buffer Configuration

LTC2345-16
REFIN 20k BANDGAP
REFERENCE
2.7µF

REFBUF REFERENCE
BUFFER

6.5k
LTC6655-2.048 47µF

6.5k

GND
234516 F11b

Figure 11b. External Reference with Internal Buffer Configuration

234516f

For more information www.linear.com/LTC2345-16 27

LTC2345-16
Applications Information
LTC2345-16 The LTC2345-16 converter draws a charge (QCONV) from
REFIN 20k BANDGAP the REFBUF pin during each conversion cycle. On short
REFERENCE time scales most of this charge is supplied by the external
REFBUF bypass capacitor, but on longer time scales all of
REFBUF REFERENCE
BUFFER the charge is supplied by either the reference buffer, or
when the internal reference buffer is disabled, the external
LTC6655-5 47µF
6.5k
reference. This charge draw corresponds to a DC current
6.5k equivalent of IREFBUF = QCONV • fSMPL, which is proportional
GND
to sample rate. In applications where a burst of samples
234516 F11c
is taken after idling for long periods of time, as shown in
Figure 12, IREFBUF quickly transitions from approximately
0.4mA to 1.5mA (VREFBUF = 5V, fSMPL = 200kHz). This
Figure 11c. External Reference with Disabled Internal
Buffer Configuration current step triggers a transient response in the external
reference that must be considered, since any deviation in
VREFBUF affects converter accuracy. If an external reference
in Figure 11c. Maximum input signal swing and SNR are is used to overdrive REFBUF, the fast settling LTC6655
achieved by overdriving REFBUF using an external 5V family of references is recommended.
reference. The buffer feedback resistors load the REFBUF
pin with 13kΩ even when the reference buffer is disabled. Internal Reference Buffer Transient Response
The LTC6655-5 offers the same small size, accuracy, drift,
For optimum performance in applications employing burst
and extended temperature range as the LTC6655-2.048,
sampling, the external reference with internal reference
and achieves a typical SNR of 92dB when paired with the
buffer configuration should be used. The internal reference
LTC2345-16. Bypass the LTC6655-5 to GND (Pin 20) close
buffer incorporates a proprietary design that minimizes
to the REFBUF pin with at least a 47μF ceramic capacitor
movements in VREFBUF when responding to a burst of
(X7R, 10V, 1210 size or X5R, 10V, 0805 size) to absorb
transient conversion currents and minimize noise.

CNV
234516 F12
IDLE IDLE
PERIOD PERIOD

Figure 12. CNV Waveform Showing Burst Sampling

234516f

28 For more information www.linear.com/LTC2345-16

 LTC2345-16
Applications Information
conversions following an idle period. Figure 13 compares to frequencies below half the sampling frequency, exclud-
the burst conversion response of the LTC2345-16 with an ing DC. Figure 14 shows that the LTC2345-16 achieves a
input near full scale for two reference configurations. The typical SINAD of 91.1dB in the ±4.096V range at a 200kHz
first configuration employs the internal reference buffer sampling rate with a fully differential 2kHz input signal.
with REFIN externally overdriven by an LTC6655-2.048,
while the second configuration disables the internal ref- 0
±4.096V RANGE
erence buffer and overdrives REFBUF with an external –20 FULLY DIFFERENTIAL DRIVE (IN– = –IN+)

LTC6655-4.096. In both cases REFBUF is bypassed to –40 SNR = 91.1dB

THD = –111dB
GND with a 47µF ceramic capacitor.

AMPLITUDE (dBFS)
–60 SINAD = 91.1dB
SFDR = 112dB
–80
6 –100
±4.096V SOFTSPAN
5 IN+ = 4V
DEVIATION FROM FINAL VALUE (LSB)

–120
IN– = 0V
4 –140

3 –160

EXTERNAL REFERENCE ON REFBUF –180

2 0 20 40 60 80 100
FREQUENCY (KHz)
1 234516 F14

0
Figure 14. 32k Point FFT fSMPL = 200ksps, fIN = 2kHz
–1 INTERNAL REFERENCE BUFFER

–2
0 100 200 300 400 500 Signal-to-Noise Ratio (SNR)
TIME (µs)
The signal-to-noise ratio (SNR) is the ratio between the
234516 F13

Figure 13. Burst Conversion Response of the LTC2345-16, RMS amplitude of the fundamental input frequency and
fSMPL = 200ksps the RMS amplitude of all other frequency components
except the first five harmonics and DC. Figure 14 shows
that the LTC2345-16 achieves a typical SNR of 91.1dB in
Dynamic Performance
the ±4.096V range at a 200kHz sampling rate with a fully
Fast Fourier transform (FFT) techniques are used to test differential 2kHz input signal.
the ADC’s frequency response, distortion, and noise at the
rated throughput. By applying a low distortion sine wave Total Harmonic Distortion (THD)
and analyzing the digital output using an FFT algorithm, Total harmonic distortion (THD) is the ratio of the RMS sum
the ADC’s spectral content can be examined for frequen- of all harmonics of the input signal to the fundamental itself.
cies outside the fundamental. The LTC2345-16 provides The out-of-band harmonics alias into the frequency band
guaranteed tested limits for both AC distortion and noise between DC and half the sampling frequency (fSMPL/2).
measurements. THD is expressed as:
Signal-to-Noise and Distortion Ratio (SINAD)
V22 + V32 + V42 ...VN2
The signal-to-noise and distortion ratio (SINAD) is the THD = 20log
V1
ratio between the RMS amplitude of the fundamental input
frequency and the RMS amplitude of all other frequency where V1 is the RMS amplitude of the fundamental fre-
components at the A/D output. The output is band-limited quency and V2 through VN are the amplitudes of the second
through Nth harmonics, respectively. Figure 14 shows

234516f

For more information www.linear.com/LTC2345-16 29

LTC2345-16
Applications Information
that the LTC2345-16 achieves a typical THD of –111dB avoid transitions on data I/O lines leading up to the rising
(N = 6) in the ±4.096V range at a 200kHz sampling rate edge of CNV. Additionally, to minimize channel-to-channel
with a fully differential 2kHz input signal. crosstalk, avoid high slew rates on the analog inputs for
100ns before and after the rising edge of CNV. Converter
Power Considerations status is indicated by the BUSY output, which transitions
low-to-high at the start of each conversion and stays high
The LTC2345-16 provides two power supply pins: the 5V until the conversion is complete. Once CNV is brought high
core power supply (VDD) and the digital input/output (I/O) to begin a conversion, it should be returned low between
interface power supply (OVDD). The flexible OVDD supply 40ns and 60ns later or after the falling edge of BUSY to
allows the LTC2345-16 to communicate with CMOS logic minimize external disturbances during the internal conver-
operating between 1.8V and 5V, including 2.5V and 3.3V sion process. If CNV is returned low after the falling edge
systems. When using LVDS I/O mode, the range of OVDD of BUSY, it should be held low for at least 420ns before
is 2.375V to 5.25V. bringing it high again, since the converter acquisition
time (tACQ) is set by the CNV low time (tCNVL) in this case.
Power Supply Sequencing
The LTC2345-16 does not have any specific power supply Internal Conversion Clock
sequencing requirements. Care should be taken to adhere The LTC2345-16 has an internal clock that is trimmed to
to the maximum voltage relationships described in the achieve a maximum conversion time of 555 • N – 35ns
Absolute Maximum Ratings section. The LTC2345-16 has with N channels enabled. With a minimum acquisition time
an internal power-on-reset (POR) circuit which resets the of 565ns when converting eight channels simultaneously,
converter on initial power-up and whenever VDD drops throughput performance of 200ksps is guaranteed without
below 2V. Once the supply voltage re-enters the nominal any external adjustments.
supply voltage range, the POR reinitializes the ADC. No
conversions should be initiated until at least 10ms after Power Down Mode
a POR event to ensure the initialization period has ended.
When PD is brought high, the LTC2345-16 is powered
When employing the internal reference buffer, allow 200ms
down and subsequent conversion requests are ignored. If
for the buffer to power up and recharge the REFBUF bypass
this occurs during a conversion, the device powers down
capacitor. Any conversion initiated before these times will
once the conversion completes. In this mode, the device
produce invalid results.
draws only a small regulator standby current resulting in a
typical power dissipation of 0.33mW. To exit power down
Timing and Control mode, bring the PD pin low and wait at least 10ms before
initiating a conversion. When employing the internal refer-
CNV Timing ence buffer, allow 200ms for the buffer to power up and
The LTC2345-16 sampling and conversion is controlled by recharge the REFBUF bypass capacitor. Any conversion
CNV. A rising edge on CNV transitions all channels’ S/H initiated before these times will produce invalid results.
circuits from track mode to hold mode, simultaneously
sampling the input signals on all channels and initiating Reset Timing
a conversion. Once a conversion has been started, it A global reset of the LTC2345-16, equivalent to a power-
cannot be terminated early except by resetting the ADC, on-reset event, may be executed without needing to cycle
as discussed in the Reset Timing section. For optimum the supplies. This feature is useful when recovering from
performance, drive CNV with a clean, low jitter signal and system-level events that require the state of the entire sys-

234516f

30 For more information www.linear.com/LTC2345-16

 LTC2345-16
Applications Information
tem to be reset to a known synchronized value. To initiate 18

a global reset, bring PD high twice without an intervening 16

conversion, as shown in Figure 15. The reset event is trig- 14 IVDD

SUPPLY CURRENT (mA)

gered on the second rising edge of PD, and asynchronously 12

ends based on an internal timer. Reset clears all serial data 10

output registers and restores the internal SoftSpan configu- 8
ration register default state of all channels in SoftSpan 7. 6
If reset is triggered during a conversion, the conversion 4
is immediately halted. The normal power down behavior 2 IOVDD
associated with PD going high is not affected by reset. Once 0
PD is brought low, wait at least 10ms before initiating a 0 40 80 120 160
SAMPLING FREQUENCY (kHz)
200

conversion. When employing the internal reference buffer, 234516 F16

allow 200ms for the buffer to power up and recharge the Figure 16. Power Dissipation of the LTC2345-16
REFBUF bypass capacitor. Any conversion initiated before Decreases with Decreasing Sampling Frequency
these times will produce invalid results.

Auto Nap Mode Digital Interface

The LTC2345-16 automatically enters nap mode after a The LTC2345-16 features CMOS and LVDS serial interfaces,
conversion has finished and completely powers up once a selectable using the LVDS/CMOS pin. The flexible OVDD
new conversion is initiated on the rising edge of CNV. Auto supply allows the LTC2345-16 to communicate with any
nap mode causes the power dissipation of the LTC2345- CMOS logic operating between 1.8V and 5V, including
16 to decrease as the sampling frequency is reduced, 2.5V and 3.3V systems, while the LVDS interface supports
as shown in Figure 16. This decrease in average power low noise digital designs. In CMOS mode, applications
dissipation occurs because a portion of the LTC2345-16 may employ between one and eight lanes of serial data
circuitry is turned off during nap mode, and the fraction output, allowing the user to optimize bus width and data
of the conversion cycle (tCYC) spent napping increases as
the sampling frequency (fSMPL) is decreased.

tPDH
PD t WAKE

tCNVH tPDL
CNV
SECOND RISING EDGE OF
BUSY tCONV PD TRIGGERS RESET

RESET RESET TIME

SET INTERNALLY
234516 F15

Figure 15. Reset Timing for the LTC2345-16

234516f

For more information www.linear.com/LTC2345-16 31

LTC2345-16
Applications Information
CS = PD = 0
SAMPLE N SAMPLE N + 1
tCYC
tCNVH
CNV tCNVL

BUSY tCONV tACQ

tBUSYLH RECOMMENDED DATA TRANSACTION WINDOW
tQUIET
tSCKI tSCKIH tSSDISCKI

SCKI 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24
tSCKIL tHSDISCKI
SDI DON’T CARE S23 S22 S21 S20 S19 S18 S17 S16 S15 S14 S13 S12 S11 S10 S9 S8 S7 S6 S5 S4 S3 S2 S1 S0

SOFTSPAN CONFIGURATION WORD FOR CONVERSION N + 1

tDSDOBUSYL tHSDOSCKI tSKEW

SCKO
tDSDOSCKI
SDO0 DON’T CARE D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 0 0 C2 C1 C0 SS2 SS1 SS0 D15

CONVERSION RESULT CHANNEL ID SOFTSPAN CONVERSION RESULT

CHANNEL 0 CHANNEL 1
• • •

24-BIT PACKET 24-BIT PACKET

CONVERSION N CONVERSION N

SDO7 DON’T CARE D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 0 0 C2 C1 C0 SS2 SS1 SS0 D15
CONVERSION RESULT CHANNEL ID SOFTSPAN CONVERSION RESULT

CHANNEL 7 CHANNEL 0
24-BIT PACKET 24-BIT PACKET
CONVERSION N CONVERSION N
234516 TD01

Figure 17. Serial CMOS I/O Mode

throughput. Together, these I/O interface options enable use case, the data transaction should be completed with
the LTC2345-16 to communicate equally well with legacy a minimum tQUIET time of 20ns prior to the start of the
microcontrollers and modern FPGAs. next conversion, as shown in Figure 17. New SoftSpan
configuration words are only accepted within this recom-
Serial CMOS I/O Mode mended data transaction window, but SoftSpan changes
As shown in Figure 17, in CMOS I/O mode the serial data take effect immediately with no additional analog input
bus consists of a serial clock input, SCKI, serial data settling time required before starting the next conversion.
input, SDI, serial clock output, SCKO, and eight lanes of It is still possible to read conversion data after starting the
serial data output, SDO0 to SDO7. Communication with next conversion, but this will degrade conversion accuracy
the LTC2345-16 across this bus occurs during predefined and therefore is not recommended.
data transaction windows. Within a window, the device Just prior to the falling edge of BUSY and the opening of
accepts 24-bit SoftSpan configuration words for the next a new data transaction window, SCKO is forced low and
conversion on SDI and outputs 24-bit packets containing SDO0 to SDO7 are updated with the latest conversion
conversion results and channel configuration information results from analog input channels 0 to 7, respectively.
from the previous conversion on SDO0 to SDO7. New Rising edges on SCKI serially clock conversion results
data transaction windows open 10ms after powering up and analog input channel configuration information out
or resetting the LTC2345-16, and at the end of each con- on SDO0 to SDO7 and trigger transitions on SCKO that are
version on the falling edge of BUSY. In the recommended skew-matched to the data on SDO0 to SDO7. The resulting

234516f

32 For more information www.linear.com/LTC2345-16

 LTC2345-16
Applications Information
SCKO frequency is half that of SCKI. SCKI rising edges are also usually not useful in this case. In other applica-
also latch SoftSpan configuration words provided on SDI, tions, such as interfacing the LTC2345-16 with an FPGA
which are used to program the internal 24-bit SoftSpan or CPLD, rising and falling edges of SCKO may be used
configuration register. See the section Programming the to capture serial output data on SDO0 to SDO7 in double
SoftSpan Configuration Register in CMOS I/O Mode for data rate (DDR) fashion. Capturing data using SCKO adds
further details. SCKI is allowed to idle either high or low robustness to delay variations over temperature and supply.
in CMOS I/O mode. As shown in Figure 18, the CMOS
bus is enabled when CS is low and is disabled and Hi-Z Full Eight Lane Serial CMOS Output Data Capture
when CS is high, allowing the bus to be shared across As shown in Table 3, full 200ksps per channel throughput
multiple devices. can be achieved with a 45MHz SCKI frequency by capturing
The data on SDO0 to SDO7 are grouped into 24-bit the first packet (24 SCKI cycles total) from all eight serial
packets consisting of a 16-bit conversion result plus data output lanes SDO0 to SDO7. This configuration also
2-bit trailing zero pad, 3-bit analog channel ID, and 3-bit allows conversion results from all channels to be captured
SoftSpan code, all presented MSB first. As suggested in using as few as 16 SCKI cycles if the 3-bit analog channel
Figures 17 and 18, each SDO lane outputs these packets ID and 3-bit SoftSpan code are not needed and the device
for all analog input channels in a sequential, circular SoftSpan configuration is not being changed. Multi-lane
manner. For example, the first 24-bit packet output on data capture is usually best suited for use with FPGA
SDO0 corresponds to analog input channel 0, followed or CPLD capture hardware, but may be useful in other
by the packets for channels 1 through 7. The data output application-specific cases.
on SDO0 then wraps back to channel 0, and this pattern
repeats indefinitely. Other SDO lanes follow a similar Fewer Than Eight Lane Serial CMOS Output Data Capture
circular pattern, except the first packet presented on each Applications that cannot accommodate the full eight lanes
lane corresponds to its associated analog input channel. of serial data capture may employ fewer lanes without
When interfacing the LTC2345-16 with a standard SPI reconfiguring the LTC2345-16. For example, capturing
bus, capture output data at the receiver on rising edges of the first two packets (48 SCKI cycles total) from SDO0,
SCKI. SCKO is not used in this case. Multiple SDO lanes SDO2, SDO4, and SDO6 provides data for analog input

PD = 0

BUSY

CS

SCKI DON’T CARE DON’T CARE

SDI DON’T CARE NEW SoftSpan CONFIGURATION WORD TWO ALL-ZERO WORDS AND ONE PARTIAL WORD DON’T CARE
(OVERWRITES INTERNAL CONFIG REGISTER) (INTERNAL CONFIG REGISTER RETAINS CURRENT VALUE)

Hi-Z Hi-Z
SCKO

Hi-Z CHANNEL 3 PACKET Hi-Z

SDO0 CHANNEL 0 PACKET CHANNEL 1 PACKET CHANNEL 2 PACKET
(PARTIAL)

tEN t DIS
• • •

Hi-Z CHANNEL 2 PACKET Hi-Z

SDO7 CHANNEL 7 PACKET CHANNEL 0 PACKET CHANNEL 1 PACKET
(PARTIAL)
234516 F18

Figure 18. Internal SoftSpan Configuration Register Behavior. Serial CMOS Bus Response to CS
234516f

For more information www.linear.com/LTC2345-16 33

LTC2345-16
Applications Information
channels 0 and 1, 2 and 3, 4 and 5, and 6 and 7, respec- the next conversion. Setting a channel’s SoftSpan code to
tively, using four output lanes. Similarly, capturing the first SS[2:0] = 000 immediately disables the channel, resulting
four packets (96 SCKI cycles total) from SDO0 and SDO4 in a corresponding reduction in tCONV on the next conver-
provides data for analog input channels 0 to 3 and 4 to sion. Similarly, enabling a previously disabled channel
7, respectively, using two output lanes. If only one lane requires no additional analog input settling time before
can be accommodated, capturing the first eight packets starting the next conversion. The mapping between the
(192 SCKI cycles total) from SDO0 provides data for all serial SoftSpan configuration word, the internal SoftSpan
analog input channels. As shown in Table 3, full 200ksps configuration register, and each channel’s 3-bit SoftSpan
per channel throughput can be achieved with a 90MHz code is illustrated in Figure 19.
SCKI frequency in the four lane case, but the maximum If fewer than 24 SCKI rising edges are provided during a
CMOS SCKI frequency of 100MHz limits the throughput data transaction window, the partial word received on SDI
to less than 200ksps per channel in the two lane and one will be ignored and the SoftSpan configuration register will
lane cases. Finally, note that in choosing the number of not be updated. If exactly 24 SCKI rising edges are provided,
lanes and which lanes to use for data capture, the user is the SoftSpan configuration register will be updated to
not restricted to the specific cases mentioned above. Other match the received SoftSpan configuration word, S[23:0].
choices may be more optimal in particular applications. The one exception to this behavior occurs when S[23:0] is
all zeros. In this case, the SoftSpan configuration register
Programming the SoftSpan Configuration Register in
will not be updated, allowing applications to retain the
CMOS I/O Mode
current SoftSpan configuration state by idling SDI low. If
The internal 24-bit SoftSpan configuration register con- more than 24 SCKI rising edges are provided during a data
trols the SoftSpan range for all analog input channels of transaction window, each complete 24-bit word received
the LTC2345-16. The default state of this register after on SDI will be interpreted as a new SoftSpan configuration
power-up or resetting the device is all ones, configuring word and applied to the SoftSpan configuration register
each channel to convert in SoftSpan 7, the ± VREFBUF range as described above. Any partial words are ignored.
(see Table 1a). The state of this register may be modified
by providing a new 24-bit SoftSpan configuration word on Typically, applications will update the SoftSpan configura-
tion register in the manner shown in Figures 17 and 18.
SDI during the data transaction window shown in Figure
After the opening of a new data transaction window at the
17. New SoftSpan configuration words are only accepted
falling edge of BUSY, the user supplies a 24-bit SoftSpan
within this recommended data transaction window, but
configuration word on SDI during the first 24 SCKI cycles.
SoftSpan changes take effect immediately with no addi-
tional analog input settling time required before starting This new word overwrites the internal configuration register

Table 3. Required SCKI Frequency to Achieve Various Throughputs in Common Output Bus Configurations with Eight Channels
Enabled. Shaded Entries Denote Throughputs That Are Not Achievable In a Given Configuration. Calculated Using fSCKI = (Number of
SCKI Cycles)/(tACQ,MIN – tQUIET)
REQUIRED fSCKI (MHz) TO ACHIEVE THROUGHPUT OF
NUMBER OF SDO NUMBER OF SCKI
I/O MODE 200ksps/CHANNEL 100ksps/CHANNEL 50ksps/CHANNEL
LANES CYCLES
(tACQ = 565ns) (tACQ = 5565ns) (tACQ = 15565ns)
8 16 30 3 2
8 24 45 5 2
CMOS 4 48 90 9 4
2 96 Not Achievable 18 7
1 192 Not Achievable 35 13
LVDS 1 96 180 (360Mbps) 18 (36Mbps) 7 (14Mbps)

234516f

34 For more information www.linear.com/LTC2345-16

 LTC2345-16
Applications Information
CMOS I/O MODE
tSCKI tSCKIH tSSDISCKI

SCKI 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24
tSCKIL tHSDISCKI

SDI DON’T CARE S23 S22 S21 S20 S19 S18 S17 S16 S15 S14 S13 S12 S11 S10 S9 S8 S7 S6 S5 S4 S3 S2 S1 S0

SoftSpan CONFIGURATION WORD

LVDS I/O MODE

tSCKI tSCKIH

SCKI
(LVDS) 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24
tSCKIL tSSDISCKI tSSDISCKI tHSDISCKI tHSDISCKI
SDI
DON’T CARE S23 S22 S21 S20 S19 S18 S17 S16 S15 S14 S13 S12 S11 S10 S9 S8 S7 S6 S5 S4 S3 S2 S1 S0
(LVDS)

SoftSpan CONFIGURATION WORD

INTERNAL 24-BIT SoftSpan CONFIGURATION REGISTER

(SAME FOR CMOS AND LVDS)
23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CHANNEL 7 SoftSpan CHANNEL 6 SoftSpan CHANNEL 5 SoftSpan CHANNEL 4 SoftSpan CHANNEL 3 SoftSpan CHANNEL 2 SoftSpan CHANNEL 1 SoftSpan CHANNEL 0 SoftSpan
CODE SS[2:0] CODE SS[2:0] CODE SS[2:0] CODE SS[2:0] CODE SS[2:0] CODE SS[2:0] CODE SS[2:0] CODE SS[2:0]
234516 F19

Figure 19. Mapping Between Serial SoftSpan Configuration Word, Internal SoftSpan
Configuration Register, and SoftSpan Code for Each Analog Input Channel

contents following the 24th SCKI rising edge. The user then As shown in Figure 20, in LVDS I/O mode the serial data
holds SDI low for the remainder of the data transaction bus consists of a serial clock differential input, SCKI, serial
window causing the register to retain its contents regardless data differential input, SDI, serial clock differential output,
of the number of additional SCKI cycles applied. SoftSpan SCKO, and serial data differential output, SDO. Communi-
settings may be retained across multiple conversions by cation with the LTC2345-16 across this bus occurs during
holding SDI low for the entire data transaction window, predefined data transaction windows. Within a window,
regardless of the number of SCKI cycles applied. the device accepts 24-bit SoftSpan configuration words
for the next conversion on SDI and outputs 24-bit packets
Serial LVDS I/O Mode containing conversion results and channel configuration
In LVDS I/O mode, information is transmitted using posi- information from the previous conversion on SDO. New
tive and negative signal pairs (LVDS+/LVDS−) with bits data transaction windows open 10ms after powering up
differentially encoded as (LVDS+ − LVDS−). These signals or resetting the LTC2345-16, and at the end of each con-
are typically routed using differential transmission lines version on the falling edge of BUSY. In the recommended
with 100Ω characteristic impedance. Logical 1’s and 0’s use case, the data transaction should be completed with
are nominally represented by differential +350mV and a minimum tQUIET time of 20ns prior to the start of the
−350mV, respectively. For clarity, all LVDS timing diagrams next conversion, as shown in Figure 20. New SoftSpan
and interface discussions adopt the logical rather than configuration words are only accepted within this recom-
physical convention. mended data transaction window, but SoftSpan changes
take effect immediately with no additional analog input

234516f

For more information www.linear.com/LTC2345-16 35

LTC2345-16
Applications Information
CS = PD = 0
SAMPLE N SAMPLE N + 1
t CYC
tCNVH
CNV t CNVL
(CMOS)

BUSY tCONV t ACQ

(CMOS)
tBUSYLH RECOMMENDED DATA TRANSACTION WINDOW
t SCKI tQUIET
t SCKIH
SCKI
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 185 186 187 188 189 190 191 192
(LVDS)
t SCKIL t SSDISCKI t HSDISCKI t HSDISCKI
t SSDISCKI
SDI
DON’T CARE S23 S22 S21 S20 S19 S18 S17 S16 S15 S14 S13 S12 S11 S10 S9 S8 S7 S6 S5 S4 S3 S2 S1 S0
(LVDS)

t DSDOBUSYL SoftSpan CONFIGURATION WORD FOR CONVERSION N + 1

t HSDOSCKI t SKEW
SCKO
(LVDS)
t DSDOSCKI
SDO
DON’T CARE D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 0 0 C2 C1 C0 SS2 SS1 SS0 D15 D14 D13 0 C2 C1 C0 SS2 SS1 SS0 D15
(LVDS)
CONVERSION
CONVERSION RESULT CHANNEL ID SoftSpan CHANNEL ID SoftSpan
RESULT
CHANNEL 0 CHANNEL 1 CHANNEL 7 CHANNEL 0
24-BIT PACKET 24-BIT PACKET 24-BIT PACKET 24-BIT PACKET
CONVERSION N CONVERSION N CONVERSION N CONVERSION N
234516 F20

Figure 20. Serial LVDS I/O Mode

settling time required before starting the next conversion. disabled and Hi-Z when CS is high, allowing the bus to be
It is still possible to read conversion data after starting the shared across multiple devices. Due to the high speeds
next conversion, but this will degrade conversion accuracy involved in LVDS signaling, LVDS bus sharing must be
and therefore is not recommended. carefully considered. Transmission line limitations imposed
Just prior to the falling edge of BUSY and the opening of by the shared bus may limit the maximum achievable bus
a new data transaction window, SDO is updated with the clock speed. LVDS inputs are internally terminated with
latest conversion results from analog input channel 0. Both a 100Ω differential resistor when CS = 0, while outputs
rising and falling edges on SCKI serially clock conversion must be differentially terminated with a 100Ω resistor at
results and analog input channel configuration information the receiver (FPGA). SCKI must idle in the low state in
out on SDO. SCKI is also echoed on SCKO, skew-matched LVDS I/O mode, including when transitioning CS.
to the data on SDO. Whenever possible, it is recommended The data on SDO are grouped into 24-bit packets consist-
that rising and falling edges of SCKO be used to capture ing of a 16-bit conversion result plus 2-bit trailing zero
DDR serial output data on SDO, as this will yield the best pad, 3-bit analog channel ID, and 3-bit SoftSpan code, all
robustness to delay variations over supply and tempera- presented MSB first. As suggested in Figures 20 and 21,
ture. SCKI rising and falling edges also latch SoftSpan SDO outputs these packets for all analog input channels
configuration words provided on SDI, which are used to in a sequential, circular manner. For example, the first
program the internal 24-bit SoftSpan configuration register. 24-bit packet output on SDO corresponds to analog input
See the section Programming the SoftSpan Configuration channel 0, followed by the packets for channels 1 through
Register in LVDS I/O Mode for further details. As shown in 7. The data output on SDO then wraps back to channel 0,
Figure 21, the LVDS bus is enabled when CS is low and is and this pattern repeats indefinitely.
234516f

36 For more information www.linear.com/LTC2345-16

 LTC2345-16
Applications Information
Serial LVDS Output Data Capture If fewer than 24 SCKI edges (rising plus falling) are
As shown in Table 3, full 200ksps per channel throughput provided during a data transaction window, the partial
can be achieved with a 180MHz SCKI frequency by captur- word received on SDI will be ignored and the SoftSpan
ing eight packets (96 SCKI cycles total) of DDR data from configuration register will not be updated. If exactly 24
SDO. The LTC2345-16 supports LVDS SCKI frequencies SCKI edges are provided, the SoftSpan configuration
up to 250MHz. register will be updated to match the received SoftSpan
configuration word, S[23:0]. The one exception to this
Programming the SoftSpan Configuration Register in behavior occurs when S[23:0] is all zeros. In this case,
LVDS I/O Mode the SoftSpan configuration register will not be updated,
allowing applications to retain the current SoftSpan con-
The internal 24-bit SoftSpan configuration register con- figuration state by idling SDI low. If more than 24 SCKI
trols the SoftSpan range for all analog input channels of edges are provided during a data transaction window, each
the LTC2345-16. The default state of this register after complete 24-bit word received on SDI will be interpreted
power-up or resetting the device is all ones, configuring as a new SoftSpan configuration word and applied to the
each channel to convert in SoftSpan 7, the ± VREFBUF range SoftSpan configuration register as described above. Any
(see Table 1a). The state of this register may be modified partial words are ignored.
by providing a new 24-bit SoftSpan configuration word on
SDI during the data transaction window shown in Figure Typically, applications will update the SoftSpan configura-
20. New SoftSpan configuration words are only accepted tion register in the manner shown in Figures 20 and 21.
within this recommended data transaction window, but After the opening of a new data transaction window at
SoftSpan changes take effect immediately with no addi- the falling edge of BUSY, the user supplies a 24-bit DDR
tional analog input settling time required before starting SoftSpan configuration word on SDI during the first 12
the next conversion. Setting a channel’s SoftSpan code to SCKI cycles. This new word overwrites the internal con-
SS[2:0] = 000 immediately disables the channel, resulting figuration register contents following the 12th SCKI falling
in a corresponding reduction in tCONV on the next conver- edge. The user then holds SDI low for the remainder of
sion. Similarly, enabling a previously disabled channel the data transaction window causing the register to retain
requires no additional analog input settling time before its contents regardless of the number of additional SCKI
starting the next conversion. The mapping between the cycles applied. SoftSpan settings may be retained across
serial SoftSpan configuration word, the internal SoftSpan multiple conversions by holding SDI low for the entire
configuration register, and each channel’s 3-bit SoftSpan data transaction window, regardless of the number of
code is illustrated in Figure 19. SCKI cycles applied.

PD = 0

BUSY
(CMOS)

CS tEN tDIS
(CMOS)

SCKI
DON’T CARE DON’T CARE
(LVDS)

SDI NEW SoftSpan CONFIGURATION WORD TWO ALL-ZERO WORDS AND ONE PARTIAL WORD
DON’T CARE DON’T CARE
(LVDS) (OVERWRITES INTERNAL CONFIG REGISTER) (INTERNAL CONFIG REGISTER RETAINS CURRENT VALUE)

SCKO Hi-Z Hi-Z

(LVDS)

SDO Hi-Z CHANNEL 3 PACKET Hi-Z

CHANNEL 0 PACKET CHANNEL 1 PACKET CHANNEL 2 PACKET
(LVDS) (PARTIAL) 234516 F21

Figure 21. Internal SoftSpan Configuration Register Behavior. Serial LVDS Bus Response to CS
234516f

For more information www.linear.com/LTC2345-16 37

LTC2345-16
Board Layout
To obtain the best performance from the LTC2345-16, a Supply bypass capacitors should be placed as close as
four-layer printed circuit board (PCB) is recommended. possible to the supply pins. Low impedance common re-
Layout for the PCB should ensure the digital and analog turns for these bypass capacitors are essential to the low
signal lines are separated as much as possible. In particu- noise operation of the ADC. A single solid ground plane
lar, care should be taken not to run any digital clocks or is recommended for this purpose. When possible, screen
signals alongside analog signals or underneath the ADC. the analog input traces using ground.
Also minimize the length of the REFBUF to GND (Pin 20)
bypass capacitor return loop, and avoid routing CNV near Reference Design
signals which could potentially disturb its rising edge. For a detailed look at the reference design for this con-
verter, including schematics and PCB layout, please refer
to DC2326A, the evaluation kit for the LTC2345-16.

234516f

38 For more information www.linear.com/LTC2345-16

 LTC2345-16
Package Description
Please refer to http://www.linear.com/product/LTC2345-16#packaging for the most recent package drawings.

UK Package
48-Lead Plastic QFN (7mm × 7mm)
(Reference LTC DWG # 05-08-1704 Rev C)

0.70 ±0.05

5.15 ±0.05
5.50 REF
6.10 ±0.05 7.50 ±0.05
(4 SIDES)

5.15 ±0.05

PACKAGE OUTLINE

0.25 ±0.05
0.50 BSC

RECOMMENDED SOLDER PAD PITCH AND DIMENSIONS

APPLY SOLDER MASK TO AREAS THAT ARE NOT SOLDERED

7.00 ±0.10 0.75 ±0.05 R = 0.115

R = 0.10 TYP
(4 SIDES) TYP 47 48

0.40 ±0.10
PIN 1 TOP MARK
(SEE NOTE 6)
1
2
PIN 1
CHAMFER
C = 0.35

5.15 ±0.10
5.50 REF
(4-SIDES)

5.15 ±0.10

(UK48) QFN 0406 REV C

0.200 REF
0.25 ±0.05
0.00 – 0.05
0.50 BSC
NOTE:
1. DRAWING CONFORMS TO JEDEC PACKAGE OUTLINE MO-220 VARIATION (WKKD-2) BOTTOM VIEW—EXPOSED PAD
2. DRAWING NOT TO SCALE
3. ALL DIMENSIONS ARE IN MILLIMETERS
4. DIMENSIONS OF EXPOSED PAD ON BOTTOM OF PACKAGE DO NOT INCLUDE
MOLD FLASH. MOLD FLASH, IF PRESENT, SHALL NOT EXCEED 0.20mm ON ANY SIDE, IF PRESENT
5. EXPOSED PAD SHALL BE SOLDER PLATED
6. SHADED AREA IS ONLY A REFERENCE FOR PIN 1 LOCATION ON THE TOP AND BOTTOM OF PACKAGE

234516f

Information furnished by Linear Technology Corporation is believed to be accurate and reliable.

However, no responsibility is assumed for its use. Linear Technology Corporation makes no representa-
For more
tion that the interconnection of itsinformation www.linear.com/LTC2345-16
circuits as described herein will not infringe on existing patent rights. 39
LTC2345-16
Typical Application
Sense Current from Rail with Amplification
5V

2.49k VDD
IN0+
1Ω 274Ω 5V IN0–
– LTC2345-16
+
ILOAD LTC6252
REFBUF REFIN
LOAD 47µF 0.1µF

ONLY CHANNEL 0 SHOWN FOR CLARITY

234516 TA02

Related Parts
PART NUMBER DESCRIPTION COMMENTS
ADCs
LTC2345-18 18-Bit, 200ksps, 8-Channel Simultaneous 5V Supply, SoftSpan Inputs with Wide Common Mode Range, 91.8dB SNR,
Sampling, ±5LSB INL, Serial ADC Serial CMOS and LVDS I/O, 7mm × 7mm QFN-48 Package
LTC2348-18/LTC2348-16 18-/16-Bit, 200ksps, 8-Channel Simultaneous ±10.24V SoftSpan Inputs with Wide Common Mode Range, 97/94dB SNR,
Sampling, ±3/±1LSB INL, Serial ADC Serial CMOS and LVDS I/O, 7mm × 7mm LQFP-48 Package
LTC2378-20/LTC2377-20/ 20-Bit, 1Msps/500ksps/250ksps, 2.5V Supply, ±5V Fully Differential Input, 104dB SNR, MSOP-16 and
LTC2376-20 ±0.5ppm INL Serial, Low Power ADC 4mm × 3mm DFN-16 Packages
LTC2338-18/LTC2337-18/ 18-Bit, 1Msps/500ksps/250ksps, Serial, 5V Supply, ±10.24V Fully Differential Input, 100dB SNR, MSOP-16 Package
LTC2336-18 Low Power ADC
LTC2328-18/LTC2327-18/ 18-Bit, 1Msps/500ksps/250ksps, Serial, 5V Supply, ±10.24V Pseudo-Differential Input, 95dB SNR,
LTC2326-18 Low Power ADC MSOP-16 Package
LTC2373-18/LTC2372-18 18-Bit, 1Msps/500ksps, 8-Channel, Serial ADC 5V Supply, 8 Channel Multiplexed, Configurable Input Range, 100dB SNR,
DGC, 5mm × 5mm QFN-32 Package
LTC2379-18/LTC2378-18/ 18-Bit,1.6Msps/1Msps/500ksps/250ksps, Serial, 2.5V Supply, Differential Input, 101.2dB SNR, ±5V Input Range, DGC, Pin
LTC2377-18/LTC2376-18 Low Power ADC Compatible Family in MSOP-16 and 4mm × 3mm DFN-16 Packages
LTC2380-16/LTC2378-16/ 16-Bit, 2Msps/1Msps/500ksps/250ksps, Serial, 2.5V Supply, Differential Input, 96.2dB SNR, ±5V Input Range, DGC, Pin
LTC2377-16/LTC2376-16 Low Power ADC Compatible Family in MSOP-16 and 4mm × 3mm DFN-16 Packages
LTC2389-18/LTC2389-16 18-Bit/16-Bit, 2.5Msps, Parallel/Serial ADC 5V Supply, Pin-Configurable Input Range, 99.8dB/96dB SNR, Parallel or
Serial I/O 7mm × 7mm LQFP-48 and QFN-48 Packages
LTC1859/LTC1858/ 16-/14-/12-Bit, 8-Channel, 100ksps, Serial ADC ±10V, SoftSpan, Single-Ended or Differential Inputs, Single 5V Supply,
LTC1857 SSOP-28 Package
LTC1606/LTC1605 16-Bit, 250ksps/100ksps, Parallel ADC ±10V Input, 5V Supply, 75mW/55mW, SSOP-28 and SO-28 Packages
DACs
LTC2756/LTC2757 18-Bit, Serial/Parallel IOUT SoftSpan DAC ±1LSB INL/DNL, Software-Selectable Ranges,
SSOP-28/7mm × 7mm LQFP-48 Package
LTC2668 16-Channel 16-/12-Bit ±10V VOUT SoftSpan DACs ±4LSB INL, Precision Reference 10ppm/°C Max, 6mm × 6mm QFN-40 Package
References
LTC6655 Precision Low Drift Low Noise Buffered Reference 5V/2.5V/2.048V/1.25V, 2ppm/°C, 0.25ppm Peak-to-Peak Noise, MSOP-8 Package
LTC6652 Precision Low Drift Low Noise Buffered Reference 5V/2.5V/2.048V/1.25V, 5ppm/°C, 2.1ppm Peak-to-Peak Noise, MSOP-8 Package
Amplifiers
LT6236/LT6237/LT6238 Single/Dual/Quad Operational Amplifier with 215MHz, 3.5mA/Amplifier, 1.1nV/√Hz
Low Wideband Noise
LT6233/LT6234/LT6235 Single/Dual/Quad Low Noise Rail-to-Rail Output 60MHz,1.2mA,1.2nV/√Hz,15V/μs,0.5mV
Op Amps
LTC6252/LTC6253/ 720MHz, 3.5mA Power Efficient Rail-to-Rail I/O 720MHz GBW, Unity Gain Stable, Low Noise
LTC6254 Op Amp
234516f

40 Linear Technology Corporation

LT 0216 • PRINTED IN USA

1630 McCarthy Blvd., Milpitas, CA 95035-7417

For more information www.linear.com/LTC2345-16
(408) 432-1900 ● FAX: (408) 434-0507 ● www.linear.com/LTC2345-16  LINEAR TECHNOLOGY CORPORATION 2016