8086 microprocessor

Intel 8086
o Intel 8086 microprocessor is the enhanced version of Intel 8085 microprocessor. It was
designed by Intel in 1976.
o The 8086 microprocessor is a16-bit, N-channel, HMOS microprocessor. Where the
HMOS is used for "High-speed Metal Oxide Semiconductor".
o Intel 8086 is built on a single semiconductor chip and packaged in a 40-pin IC
package. The type of package is DIP (Dual Inline Package).
o Intel 8086 uses 20 address lines and 16 data- lines. It can directly address up to 220 = 1
Mbyte of memory.
o It consists of a powerful instruction set, which provides operation like division and
multiplication very quickly.
o 8086 is designed to operate in two modes, i.e., Minimum and Maximum mode.

Difference between 8085 and 8086 Microprocessor

8085 Microprocessor 8086 Microprocessor

It is an 8-bit microprocessor. It is a 16-bit microprocessor.

It has a 16-bit address line. It has a 20-bit address line.

It has a 8-bit data bus. It has a 16-bit data bus.

The memory capacity is 64 KB. The memory capacity is 1 MB.

The Clock speed of this microprocessor is 3 MHz. The Clock speed of this microprocessor varies
between 5, 8 and 10 MHz for different versions.

It has five flags. It has nine flags.

8085 microprocessor does not support memory 8086 microprocessor supports memory
segmentation. segmentation.

It does not support pipelining. It supports pipelining.

It is accumulator based processor. It is general purpose register based processor.

It has no minimum or maximum mode. It has minimum and maximum modes.

In 8085, only one processor is used. In 8086, more than one processor is used. An
 additional external processor can also be
employed.

It contains less number of transistors compare to It contains more number of transistors compare
8086 microprocessor. It contains about 6500 to 8085 microprocessor. It contains about 29000
transistor. in size.

The cost of 8085 is low. The cost of 8086 is high.

8086 pins configuration

The description of the pins of 8086 is as follows:

AD0-AD15 (Address Data Bus): Bidirectional

address/data lines. These are low order address bus.
They are multiplexed with data.

When these lines are used to transmit memory

address, the symbol A is used instead of AD, for
example, A0- A15.

A16 - A19 (Output): High order address lines. These

are multiplexed with status signals.

A16/S3, A17/S4: A16 and A17 are multiplexed with

segment identifier signals S3 and S4.

A18/S5: A18 is multiplexed with interrupt status S5.

A19/S6: A19 is multiplexed with status signal S6.

BHE/S7 (Output): Bus High Enable/Status. During

T1, it is low. It enables the data onto the most significant half of data bus, D8-D15. 8-bit
device connected to upper half of the data bus use BHE signal. It is multiplexed with status
signal S7. S7 signal is available during T3 and T4.

RD (Read): For read operation. It is an output signal. It is active when LOW.

Ready (Input): The addressed memory or I/O sends acknowledgment through this pin.
When HIGH, it denotes that the peripheral is ready to transfer data.

RESET (Input): System reset. The signal is active HIGH.

CLK (input): Clock 5, 8 or 10 MHz.

INTR: Interrupt Request.

NMI (Input): Non-maskable interrupt request.

TEST (Input): Wait for test control. When LOW the microprocessor continues execution
otherwise waits.

VCC: Power supply +5V dc.

GND: Ground.

Operating Modes of 8086

There are two operating modes of operation for Intel 8086, namely the minimum mode and
the maximum mode.

When only one 8086 CPU is to be used in a microprocessor system, the 8086 is used in
the Minimum mode of operation.

In a multiprocessor system 8086 operates in the Maximum mode.

Pin Description for Minimum Mode

In this minimum mode of operation, the pin MN/MX is connected to 5V D.C. supply i.e.
MN/MX = VCC.

The description about the pins from 24 to 31 for the minimum mode is as follows:

INTA (Output): Pin number 24 interrupts acknowledgement. On receiving interrupt signal,

the processor issues an interrupt acknowledgment signal. It is active LOW.

ALE (Output): Pin no. 25. Address latch enable. It goes HIGH during T1. The microprocessor
8086 sends this signal to latch the address into the Intel 8282/8283 latch.

DEN (Output): Pin no. 26. Data Enable. When Intel 8287/8286 octal bus transceiver is used
this signal. It is active LOW.

DT/R (output): Pin No. 27 data Transmit/Receives. When Intel 8287/8286 octal bus
transceiver is used this signal controls the direction of data flow through the transceiver.
When it is HIGH, data is sent out. When it is LOW, data is received.

M/IO (Output): Pin no. 28, Memory or I/O access. When this signal is HIGH, the CPU wants
to access memory. When this signal is LOW, the CPU wants to access I/O device.

WR (Output): Pin no. 29, Write. When this signal is LOW, the CPU performs memory or I/O
write operation.
HLDA (Output): Pin no. 30, Hold Acknowledgment. It is sent by the processor when it
receives HOLD signal. It is active HIGH signal. When HOLD is removed HLDA goes LOW.

HOLD (Input): Pin no. 31, Hold. When another device in microcomputer system wants to use
the address and data bus, it sends HOLD request to CPU through this pin. It is an active HIGH
signal.

Pin Description for Maximum Mode

In the maximum mode of operation, the pin MN/¯MX is made LOW. It is grounded. The
description about the pins from 24 to 31 is as follows:

QS1, QS0 (Output): Pin numbers 24, 25, Instruction Queue Status. Logics are given below:

QS1 QS0 Operation

0 0 No operation

0 1 1st byte of opcode from queue.

1 0 Empty the queue

1 1 Subsequent byte from queue

S0, S1, S2 (Output): Pin numbers 26, 27, 28 Status Signals. These signals are connected to
the bus controller of Intel 8288. This bus controller generates memory and I/O access control
signals. Logics for status signal are given below:

S2 S1 S0 Operation

0 0 0 Interrupt acknowledgement

0 0 1 Read data from I/O port

0 1 0 Write data from I/O port

0 1 1 Halt

1 0 0 Opcode fetch

1 0 1 Memory read

1 1 0 Memory write

1 1 1 Passive state
LOCK (Output): Pin no. 29. It is an active LOW signal. When this signal is LOW, all interrupts
are masked and no HOLD request is granted. In a multiprocessor system all other processors
are informed through this signal that they should not ask the CPU for relinquishing the bus
control.

RG/GT1, RQ/GT0 (Bidirectional): Pin numbers 30, 31, Local Bus Priority Control. Other
processors ask the CPU by these lines to release the local bus.

In the maximum mode of operation signals WR, ALE, DEN, DT/R etc. are not available directly
from the processor. These signals are available from the controller 8288.

Functional units of 8086

8086 contains two independent functional units: a Bus Interface Unit (BIU) and
an Execution Unit (EU).

Fig: Block Diagram of Intel 8086 Microprocessor (8086 Architecture)

Bus Interface Unit (BIU)
The segment registers, instruction pointer and 6-byte instruction queue are associated with
the bus interface unit (BIU).

The BIU:

o Handles transfer of data and addresses,

o Fetches instruction codes, stores fetched instruction codes in first-in-first-out register
set called a queue,
o Reads data from memory and I/O devices,
o Writes data to memory and I/O devices,
o It relocates addresses of operands since it gets un-relocated operand addresses from
EU. The EU tells the BIU from where to fetch instructions or where to read data.

It has the following functional parts:

o Instruction Queue: When EU executes instructions, the BIU gets 6-bytes of the next
instruction and stores them in the instruction queue and this process is known as
instruction pre fetch. This process increases the speed of the processor.
o Segment Registers: A segment register contains the addresses of instructions and
data in memory which are used by the processor to access memory locations. It points
to the starting address of a memory segment currently being used.
There are 4 segment registers in 8086 as given below:
o Code Segment Register (CS): Code segment of the memory holds instruction
codes of a program.
o Data Segment Register (DS): The data, variables and constants given in the
program are held in the data segment of the memory.
o Stack Segment Register (SS): Stack segment holds addresses and data of
subroutines. It also holds the contents of registers and memory locations given
in PUSH instruction.
o Extra Segment Register (ES): Extra segment holds the destination addresses
of some data of certain string instructions.

o Instruction Pointer (IP): The instruction pointer in the 8086 microprocessor acts as a
program counter. It indicates to the address of the next instruction to be executed.
Execution Unit (EU)

o The EU receives opcode of an instruction from the queue, decodes it and then
executes it. While Execution, unit decodes or executes an instruction, then the BIU
fetches instruction codes from the memory and stores them in the queue.
o The BIU and EU operate in parallel independently. This makes processing faster.
o General purpose registers, stack pointer, base pointer and index registers, ALU, flag
registers (FLAGS), instruction decoder and timing and control unit constitute execution
unit (EU). Let's discuss them:

o General Purpose Registers: There are four 16-bit general purpose registers: AX
(Accumulator Register), BX (Base Register), CX (Counter) and DX. Each of these 16-bit
registers are further subdivided into 8-bit registers as shown below:

16-bit registers 8-bit high-order registers 8-bit low-order registers

AX AH AL

BX BH BL

CX CH CL

DX DH DL

o Index Register: The following four registers are in the group of pointer and index
registers:
o Stack Pointer (SP)
o Base Pointer (BP)
o Source Index (SI)
o Destination Index (DI)
o ALU: It handles all arithmetic and logical operations. Such as addition, subtraction,
multiplication, division, AND, OR, NOT operations.
o Flag Register: It is a 16?bit register which exactly behaves like a flip-flop, means it
changes states according to the result stored in the accumulator. It has 9 flags and
they are divided into 2 groups i.e. conditional and control flags.
o Conditional Flags: This flag represents the result of the last arithmetic or
logical instruction executed. Conditional flags are:
o Carry Flag
o Auxiliary Flag
o Parity Flag
 o Zero Flag
o Sign Flag
o Overflow Flag
o Control Flags: It controls the operations of the execution unit. Control flags
are:
o Trap Flag
o Interrupt Flag
o Direction Flag

Interrupts
Interrupt is a process of creating a temporary halt during program execution and allows
peripheral devices to access the microprocessor.

Microprocessor responds to these interrupts with an interrupt service routine (ISR), which
is a short program or subroutine to instruct the microprocessor on how to handle the
interrupt.

There are different types of interrupt in 8086:

Hardware Interrupts
Hardware interrupts are that type of interrupt which are caused by any peripheral device by
sending a signal through a specified pin to the microprocessor.

The Intel 8086 has two hardware interrupt pins:

 o NMI (Non-Maskbale Interrupt)
o INTR (Interrupt Request) Maskable Interrupt.

NMI: NMI is a single Non-Maskable Interrupt having higher priority than the maskable
interrupt.

o It cannot be disabled (masked) by user using software.

o It is used by the processor to handle emergency conditions.
For example: It can be used to save program and data in case of power failure. An
external electronic circuitry is used to detect power failure, and to send an interrupt
signal to 8086 through NMI line.

INTR: The INTR is a maskable interrupt. It can be enabled/disabled using interrupt flag (IF).
After receiving INTR from external device, the 8086 acknowledges through INTA signal.

It executes two consecutive interrupt acknowledge bus cycles.

Software Interrupt
A microprocessor can also be interrupted by internal abnormal conditions such as overflow;
division by zero; etc. A programmer can also interrupt microprocessor by inserting INT
instruction at the desired point in the program while debugging a program. Such an interrupt
is called a software interrupt.

The interrupt caused by an internal abnormal

conditions also came under the heading of
software interrupt.

Example of software interrupts are:

o TYPE 0 (division by zero)

o TYPE 1 (single step execution for debugging
a program)
o TYPE 2 represents NMI (power failure
condition)
o TYPE 3 (break point interrupt)
o TYPE 4 (overflow interrupt)

Interrupt pointer table for 8086

Fig: Interrupt pointer table for 8086

The 8086 can handle up to 256, hardware and

software interrupts.
1KB memory acts as a table to contain interrupt vectors (or interrupt pointers), and it is called
interrupt vector table or interrupt pointer table. The 256 interrupt pointers have been
numbered from 0 to 255 (FF hex). The number assigned to an interrupt pointer is known as
type of that interrupt. For example, Type 0, Type 1, Type 2,...........Type 255 interrupt.

Addressing modes of 8086

The way for which an operand is specified for an instruction in the accumulator, in a general
purpose register or in memory location, is called addressing mode.

The 8086 microprocessors have 8 addressing modes. Two addressing modes have been
provided for instructions which operate on register or immediate data.

These two addressing modes are:

Register Addressing: In register addressing, the operand is placed in one of the 16-bit or 8-
bit general purpose registers.

Example

o MOV AX, CX
o ADD AL, BL
o ADD CX, DX

Immediate Addressing: In immediate addressing, the operand is specified in the instruction

itself.

Example

o MOV AL, 35H

o MOV BX, 0301H
o MOV [0401], 3598H
o ADD AX, 4836H

The remaining 6 addressing modes specify the location of an operand which is placed in a
memory.

These 6 addressing modes are:

Direct Addressing: In direct addressing mode, the operand?s offset is given in the
instruction as an 8-bit or 16-bit displacement element.
Example

o ADD AL, [0301]

The instruction adds the content of the offset address 0301 to AL. the operand is placed at
the given offset (0301) within the data segment DS.

Register Indirect Addressing: The operand's offset is placed in any one of the registers BX,
BP, SI or DI as specified in the instruction.

Example

o MOV AX, [BX]

It moves the contents of memory locations addressed by the register BX to the register AX.

Based Addressing: The operand's offset is the sum of an 8-bit or 16-bit displacement and
the contents of the base register BX or BP. BX is used as base register for data segment, and
the BP is used as a base register for stack segment.

Effective address (Offset) = [BX + 8-bit or 16-bit displacement].

Example

o MOV AL, [BX+05]; an example of 8-bit displacement.

o MOV AL, [BX + 1346H]; example of 16-bit displacement.

Indexed Addressing: The offset of an operand is the sum of the content of an index register
SI or DI and an 8-bit or 16-bit displacement.

Offset (Effective Address) = [SI or DI + 8-bit or 16-bit displacement]

Example

o MOV AX, [SI + 05]; 8-bit displacement.

o MOV AX, [SI + 1528H]; 16-bit displacement.

Based Indexed Addressing: The offset of operand is the sum of the content of a base
register BX or BP and an index register SI or DI.

Effective Address (Offset) = [BX or BP] + [SI or DI]

Here, BX is used for a base register for data segment, and BP is used as a base register for
stack segment.
Example

o ADD AX, [BX + SI]

o MOV CX, [BX + SI]

Based Indexed with Displacement: In this mode of addressing, the operand's offset is given
by:

Effective Address (Offset) = [BX or BP] + [SI or DI] + 8-bit or 16-bit displacement

Example

o MOV AX, [BX + SI + 05]; 8-bit displacement

o MOV AX, [BX + SI + 1235H]; 16-bit displacement

Instruction Set of 8086

o Instructions are classified on the basis of functions they perform. They are categorized
into the following main types:

Data Transfer instruction

All the instructions which perform data movement come under this category. The
source data may be a register, memory location, port etc. the destination may be a
register, memory location or port. The following instructions come under this category:

Instruction Description

MOV Moves data from register to register, register to memory, memory to register, memory
to accumulator, accumulator to memory, etc.

LDS Loads a word from the specified memory locations into specified register. It also loads
a word from the next two memory locations into DS register.

LES Loads a word from the specified memory locations into the specified register. It also
loads a word from next two memory locations into ES register.

LEA Loads offset address into the specified register.

LAHF Loads low order 8-bits of the flag register into AH register.

SAHF Stores the content of AH register into low order bits of the flags register.

XLAT/XLATB Reads a byte from the lookup table.

XCHG Exchanges the contents of the 16-bit or 8-bit specified register with the contents of AX
 register, specified register or memory locations.

PUSH Pushes (sends, writes or moves) the content of a specified register or memory
location(s) onto the top of the stack.

POP Pops (reads) two bytes from the top of the stack and keeps them in a specified register,
or memory location(s).

POPF Pops (reads) two bytes from the top of the stack and keeps them in the flag register.

IN Transfers data from a port to the accumulator or AX, DX or AL register.

OUT Transfers data from accumulator or AL or AX register to an I/O port identified by the
second byte of the instruction.

o Arithmetic Instructions
Instructions of this group perform addition, subtraction, multiplication, division,
increment, decrement, comparison, ASCII and decimal adjustment etc.
The following instructions come under this category:
o 37.3M
o 705
o Java Try Catch

Instruction Description

ADD Adds data to the accumulator i.e. AL or AX register or memory locations.

ADC Adds specified operands and the carry status (i.e. carry of the previous stage).

SUB Subtract immediate data from accumulator, memory or register.

SBB Subtract immediate data with borrow from accumulator, memory or register.

MUL Unsigned 8-bit or 16-bit multiplication.

IMUL Signed 8-bit or 16-bit multiplication.

DIV Unsigned 8-bit or 16-bit division.

IDIV Signed 8-bit or 16-bit division.

INC Increment Register or memory by 1.

DEC Decrement register or memory by 1.

DAA Decimal Adjust after BCD Addition: When two BCD numbers are added, the DAA is
used after ADD or ADC instruction to get correct answer in BCD.

DAS Decimal Adjust after BCD Subtraction: When two BCD numbers are added, the DAS
 is used after SUB or SBB instruction to get correct answer in BCD.

AAA ASCII Adjust for Addition: When ASCII codes of two decimal digits are added, the
AAA is used after addition to get correct answer in unpacked BCD.

AAD Adjust AX Register for Division: It converts two unpacked BCD digits in AX to the
equivalent binary number. This adjustment is done before dividing two unpacked BCD
digits in AX by an unpacked BCD byte.

AAM Adjust result of BCD Multiplication: This instruction is used after the multiplication of
two unpacked BCD.

AAS ASCII Adjust for Subtraction: This instruction is used to get the correct result in
unpacked BCD after the subtraction of the ASCII code of a number from ASCII code
another number.

CBW Convert signed Byte to signed Word.

CWD Convert signed Word to signed Doubleword.

NEG Obtains 2's complement (i.e. negative) of the content of an 8-bit or 16-bit specified
register or memory location(s).

CMP Compare Immediate data, register or memory with accumulator, register or memory
location(s).

o Logical Instructions
Instruction of this group perform logical AND, OR, XOR, NOT and TEST
operations. The following instructions come under this category:

Instruction Description

AND Performs bit by bit logical AND operation of two operands and places the result in the
specified destination.

OR Performs bit by bit logical OR operation of two operands and places the result in the
specified destination.

XOR Performs bit by bit logical XOR operation of two operands and places the result in the
specified destination.

NOT Takes one's complement of the content of a specified register or memory location(s).

TEST Perform logical AND operation of a specified operand with another specified operand.
Rotate Instructions
The following instructions come under this category:

Instruction Description

RCL Rotate all bits of the operand left by specified number of bits through carry flag.

RCR Rotate all bits of the operand right by specified number of bits through carry flag.

ROL Rotate all bits of the operand left by specified number of bits.

ROR Rotate all bits of the operand right by specified number of bits.

Shift Instructions
The following instructions come under this category:

Instruction Description

SAL or SHL Shifts each bit of operand left by specified number of bits and put zero in LSB position.

SAR Shift each bit of any operand right by specified number of bits. Copy old MSB into new
MSB.

SHR Shift each bit of operand right by specified number of bits and put zero in MSB
position.

Branch Instructions
It is also called program execution transfer instruction. Instructions of this group
transfer program execution from the normal sequence of instructions to the specified
destination or target. The following instructions come under this category:

Instruction Description

JA or JNBE Jump if above, not below, or equal i.e. when CF and ZF = 0

JAE/JNB/JNC Jump if above, not below, equal or no carry i.e. when CF = 0

JB/JNAE/JC Jump if below, not above, equal or carry i.e. when CF = 0

JBE/JNA Jump if below, not above, or equal i.e. when CF and ZF = 1

JCXZ Jump if CX register = 0

JE/JZ Jump if zero or equal i.e. when ZF = 1

JG/JNLE Jump if greater, not less or equal i.e. when ZF = 0 and CF = OF

JGE/JNL Jump if greater, not less or equal i.e. when SF = OF

JL/JNGE Jump if less, not greater than or equal i.e. when SF ≠ OF

JLE/JNG Jump if less, equal or not greater i.e. when ZF = 1 and SF ≠ OF

JMP Causes the program execution to jump unconditionally to the memory address or
label given in the instruction.

CALL Calls a procedure whose address is given in the instruction and saves their return
address to the stack.

RET Returns program execution from a procedure (subroutine) to the next instruction
or main program.

IRET Returns program execution from an interrupt service procedure (subroutine) to

the main program.

INT Used to generate software interrupt at the desired point in a program.

INTO Software interrupts to indicate overflow after arithmetic operation.

LOOP Jump to defined label until CX = 0.

LOOPZ/LOOPE Decrement CX register and jump if CX ≠ 0 and ZF = 1.

LOOPNZ/LOOPNE Decrement CX register and jump if CX ≠ 0 and ZF = 0.

o Here,CF=Carry..Flag
ZF=Zero..Flag
OF=Overflow..Flag
SF=Sign..Flag
CX = Register

Flag Manipulation and Processor Control Instructions

Instructions of this instruction set are related to flag manipulation and machine
control. The following instructions come under this category:
Instruction Description

CLC Clear Carry Flag: This instruction resets the carry flag CF to 0.

CLD Clear Direction Flag: This instruction resets the direction flag DF to 0.

CLI Clear Interrupt Flag: This instruction resets the interrupt flag IF to 0.

CMC This instruction take complement of carry flag CF.

STC Set carry flag CF to 1.

STD Set direction flag to 1.

STI Set interrupt flag IF to 1.

HLT Halt processing. It stops program execution.

NOP Performs no operation.

ESC Escape: makes bus free for external master like a coprocessor or peripheral device.

WAIT When WAIT instruction is executed, the processor enters an idle state in which the
processor does no processing.

LOCK It is a prefix instruction. It makes the LOCK pin low till the execution of the next
instruction.

String Instructions
String is series of bytes or series of words stored in sequential memory locations. The
8086 provides some instructions which handle string operations such as string
movement, comparison, scan, load and store.
The following instructions come under this category:

Instruction Description

MOVS/MOVSB/MOVSW Moves 8-bit or 16-bit data from the memory location(s) addressed by SI
register to the memory location addressed by DI register.

CMPS/CMPSB/CMPSW Compares the content of memory location addressed by DI register with

the content of memory location addressed by SI register.

SCAS/SCASB/SCASW Compares the content of accumulator with the content of memory location
addressed by DI register in the extra segment ES.

LODS/LODSB/LODSW Loads 8-bit or 16-bit data from memory location addressed by SI register
 into AL or AX register.

STOS/STOSB/STOSW Stores 8-bit or 16-bit data from AL or AX register in the memory location
addressed by DI register.

REP Repeats the given instruction until CX ≠ 0

REPE/ REPZ Repeats the given instruction till CX ≠ 0 and ZF = 1

REPNE/REPNZ Repeats the given instruction till CX ≠ 0 and ZF = 0

Stacks

The stack is a block of memory that may be used for temporarily storing the
contents of the registers inside the CPU. It is a top-down data structure whose elements
are accessed using the stack pointer (SP) which gets decremented by two as we store a
data word into the stack and gets incremented by two as we retrieve a data word from
the stack back to the CPU register.

The process of storing the data in the stack is called ‘pushing into’ the stack and
the
reverse process of transferring the data back from the stack to the CPU register is
known as
‘popping off’ the stack. The stack is essentially Last-In-First-Out (LIFO) data segment.
This

means that the data which is pushed into the stack last will be on top of stack and will
be popped off the stack first.

The stack pointer is a 16-bit register that contains the offset address of the
memory location in the stack segment. The stack segment, like any other segment, may
have a memory block of a maximum of 64 Kbytes locations, and thus may overlap with
any other segments. Stack Segment register (SS) contains the base address of the stack
segment in the memory.

The Stack Segment register (SS) and Stack pointer register (SP) together address the
stack-top as explained below:
 If the stack top points to a memory location 52050H, it means that the location 52050H
is already occupied with the previously pushed data. The next 16 bit push operation will
decrement the stack pointer by two, so that it will point to the new stack-top 5204EH
and the decremented contents of SP will be 204EH. This location will now be occupied
by the recently pushed data.

Thus for a selected value of SS, the maximum value of SP=FFFFH and the segment can
have maximum of 64K locations. If the SP starts with an initial value of FFFFH, it will
be decremented by two whenever a 16-bit data is pushed onto the stack. After
successive push operations, when the stack pointer contains 0000H, any attempt to
further push the data to the stack will result in stack overflow.
After a procedure is called using the CALL instruction, the IP is incremented to the next
instruction. Then the contents of IP, CS and flag register are pushed automatically to the
stack. The control is then transferred to the specified address in the CALL instruction
i.e. starting address of the procedure. Then the procedure is executed.

Difference between Macro and Procedure

 Difficulty Level : Medium
 Last Updated : 15 Feb, 2021

Assembly language is a common intermediate level programming language which is used

for microprocessor programming. This macro and procedure are two concepts in assembly by
which modular programming is implemented. So now let’s understand how macro and
procedure are different from each other.
1. Macro :
Macro is a set of instruction and the programmer can use it anywhere in the program by using
its name. It is mainly used to achieve modular programming. So same set of instructions can
be used multiple times when ever required by the help of macro. Wherever macro’s identifier
is used, it is replaced by the actual defined instructions during compilation thereby no calling
and return occurs.
Syntax of macro :
%macro macro_name number_of_parameters
<macro body>
%endmacro
2. Procedure :
Procedures are also like macro, but they are used for large set of instruction when macro is
useful for small set of instructions. It contains a set of instructions which performs a specific
task. It contains three main parts i.e Procedure name to identify the procedure, procedure body
which contains set of instructions, and RET statement which denotes return statement. Unlike
macros, procedures follow call-return method thereby achieving true modularity.
Syntax of Procedure :
procedure_name :
procedure body
….......................
RET
To call a procedure

CALL procedure_name
After execution of procedure control passes to the calling procedure using RET statement.
Difference between Macro and Procedure :

S.No.MACRO PROCEDURE
Macro definition contains a set of Procedure contains a set of instructions
instruction to support modular which can be called repetitively which can
01. programming. perform a specific task.
It is used for small set of instructions mostly It is used for large set of instructions mostly
02. less than ten instructions. more than ten instructions.
In case of macro memory requirement is In case of procedure memory requirement is
03. high. less.
CALL and RET instruction/statements are CALL and RET instruction/statements are
04. not required in macro. required in procedure.
Assembler directive MACRO is used to Assembler directive PROC is used to define
define macro and assembler directive procedure and assembler directive ENDP is
05. ENDM is used to indicate the body is over. used to indicate the body is over.
Execution time of macro is less than it Execution time of procedures is high as it
06. executes faster than procedure. executes slower than macro.
Here machine code is created multiple times Here machine code is created only once, it is
as each time machine code is generated generated only once when the procedure is
07. when macro is called. defined.
In a macro parameter is passed as part of In a procedure parameters are passed in
08. statement that calls macro. registers and memory locations of stack.
09. Overhead time does not take place as there Overhead time takes place during calling
 is no calling and returning. procedure and returning control to calling
program.

Memory and I/O Interfacing

Several memory chips and I/O devices are connected to a microprocessor.

The following figure shows a schematic diagram to interface memory chips and I/O devices
to a microprocessor.

Memory Interfacing
When we are executing any instruction, the address of memory location or an I/O device is
sent out by the microprocessor. The corresponding memory chip or I/O device is selected by
a decoding circuit.

Memory requires some signals to read from and write to registers and microprocessor
transmits some signals for reading or writing data.

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The interfacing process includes matching the memory requirements with the microprocessor
signals. Therefore, the interfacing circuit should be designed in such a way that it matches the
memory signal requirements with the microprocessor's signals.

I/O interfacing
As we know, keyboard and displays are used as communication channel with outside world.
Therefore, it is necessary that we interface keyboard and displays with the microprocessor.
This is called I/O interfacing. For this type of interfacing, we use latches and buffers for
interfacing the keyboards and displays with the microprocessor.

But the main drawback of this interfacing is that the microprocessor can perform only one
function.

8279 Programmable Keyboard

The Intel 8279 is a programmable keyboard interfacing device. Data input and display are the
integral part of microprocessor kits and microprocessor-based systems.

8279 has been designed for the purpose of 8-bit Intel microprocessors.

8279 has two sections namely keyboard section and display section.

The function of the keyboard section is to interface the keyboard which is used as input
device for the microprocessor. It can also interface toggle or thumb switches.

The purpose of the display section is to drive alphanumeric displays or indicator lights. It is
directly connected to the microprocessor bus.

The microprocessor is relieved from the burden of scanning the keyboard or refreshing the
display.

Some important Features are:

o Simultaneous keyboard display operations

o Scanned sensor mode
o Scanned keyboard mode
o 8-character keyboard FIFO
o Strobed input entry mode
o 2-key lock out or N-key roll over with contact debounce
o Single 16-charcter display
o Dual 8 or 16 numerical display
o Interrupt output on key entry
o Programmable scan timing and mode programmable from CPU

8257 DMA Controller

The data transfer from fast I/O devices to the memory or from the memory to I/O devices
through the accumulator is a time consuming process. For this situation, the Direct Memory
Access (DMA) technique is preferred. In DMA data transfer scheme, data is directly
transferred from an I/O device to RAM or from RAM to an I/O device.

Using a DMA controller, the device requests the CPU to hold its address, data and control
bus, so the device is free to transfer data directly to/from the memory. The DMA data transfer
is initiated only after receiving HLDA signal from the CPU.

How DMA operations are performed?

Following are the operations performed by a DMA:

o Initially, the device has to send DMA request (DRQ) to DMA controller for sending the data
between the device and the memory.
o The DMA controller sends Hold request (HRQ) to the CPU and waits for the CPU for the HLDA.
o When CPU gets the HLDA signal then, it leaves the control over the bus and acknowledges the
HOLD request through HLDA signal.
o Now the CPU is in the HOLD state and the DMA controller has to manage the operations over
the buses between the CPU, memory and I/O devices.

Intel 8257
o The Intel 8257 is a programmable DMA controller.
o It is a 4-channel programmable Direct Memory Access (DMA) controller.
o It is a 40 pin I.C. package and requires +5V supply for its operation.
o It can perform three operations, namely read, write, and verify.
o Each channel incorporates two 16-bit registers, namely DMA address register and byte count
register.
o Each channel can transfer data up to 64kb and can be programmed independently.
o It operates in 2 -modes: Master mode and Slave mode.

8257 Architecture
The following diagram is the architecture of Intel 8257:
8257 Pin Description

DRQ0 - DRQ3: These are DMA request lines. An I/O device sends the DMA request on one of
these lines. On the line, a HIGH status generates a DMA request.

DACK0 - DACK3 : These are DMA acknowledge lines. The Intel 8257 sends an acknowledge
signal through one of these lines informing an I/O device that it has been selected for DMA
data transfer. On the line, a LOW acknowledges the I/O device.

A0 - A7: These are address lines. A0 - A3 are bidirectional lines. These lines carry 4 LSBs of 16-
bit memory address generated by the 8257 in the master mode. In the slave mode, these
lines are all the input lines. The inputs select one from the registers to be read or
programmed. A4 - A7 lines gives tristated outputs in the master mode which carry 4 through
7 of the 16-bit memory address generated by the Intel 8257.

D0 - D7: These are data lines. These are bidirectional three state lines. While programming the
controller the CPU sends data for the DMA address register, the byte count register and the
mode set register through these data lines.

AEN: Address latch enable.

ADSTB: A HIGH on this line latches the 8MSBs of the address, which are sent on D-bus, into
Intel 8212 connected for this purpose.
CS: It is chip select.

(I/OR): I/O read. It is a bidirectional line. In output mode it is used to access data from the
I/O device during the DMA write cycle.

(I/OW): I/O write. It is a bidirectional line. In output mode it allows the transfer of data to the
I/O device during the DMA read cycle. Data is transferred from the memory.

MEMR: Memory read

MEMW: Memory write

TC: Byte count (Terminal count).

MARK: Modulo 128 Mark.

CLK: Clock

HRQ: Hold request

HLDA: Hold acknowledge