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IO Management

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11 views

IO Management

Uploaded by

ashokabc2001
Copyright
© © All Rights Reserved
Available Formats
Download as PDF, TXT or read online on Scribd
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IO management

1
IO Subsystem
● IO – input output
● Deals with controlling the devices for IO
● Very large number of IO devices
● With different properties
Managing IO devices
● Devices with different requirements
● They seem to require different interfaces to
manipulate and manage them
● We don’t want a different interface for every
device
● How can we have a uniform and efficient
approach to handling I/O devices?
Type of devices
● Human interface
● Interact with the user
● Ex: Printers, Video Display, Keyboard, Mouse
● Machine interface
● Interact with electronic equipment
● Ex: Disk and tape drives, Sensors, Controllers, Actuators
● Communication
● Used to communicate with remote devices
● Ex: Ethernet, Modems, Wireless
Differences between devices
● Data rate
● May be differences of several orders of magnitude
between the data transfer rates
● Example:
● Keyboard vs Gigabit Ethernet
● Disk vs USB
● Can we use the same strategy?
Data rates
Handling IO devices
● We have two main paths
● Control path
● Deals with controlling the device
● Less overhead and usually does not cause
bottlenecks
● Data path
● Deals with moving data from/to device and main
memory
● May cause bottlenecks
Considerations
● Complexity of control
● Unit of transfer
● Should we transfer a byte, or a block or should we
stream?
● Data representation
● Encoding schemes
● Error conditions
● Devices respond to errors differently
● Expected error rate also differs
Considerations
● Need a common interface
● At least user-level applications should see a
common interface
● Dissimilar but similar devices
● Examples: USB stick vs magnetic disk
● Need to have a common interface
● Achieved via having another layer ;)
● Priority
● Which device should we server first?
How to access devices

A) Separate I/O and memory space


● Controller registers appear in a different space,
● Accessed via special instructions
b) Memory-mapped I/O
● Controller registers appear as memory
● Use normal load/store instructions to access
c) Hybrid
● x86 has both ports and memory mapped I/O
Bus architecture

A) Same buss for access memory and IO


B) Different busses
Controlling a device
● Issue an instruction for a device
● Wait for an character
● Wait for network packet
● How do we know when the
● Character is read?
● Packet is sent?
Programmed IO
● Also called polling, or busy
waiting
● I/O module performs the
command and set appropriate
bits in some status register
● Processor checks status until
operation is complete
● Stay in a while loop
● Wastes CPU cycles: may be
Interrupt

● The device controller finishes the command and


generates an interrupt
● Interrupt goes to the interrupt controller and then
from there to the CPU
● Details depends on architecture
Interrupt IO
● Issue the command
● Device finishes the job and
generates an interrupt which
is handled by the CPU
● CPU does not have a busy
wait till the completion
● After issuing the command
CPU switches to a different
process (thread)
Which is better?
● Interrupt or programmed IO?
Which is better?
● Interrupt or programmed IO?
● Depends
● For very fast devices 🡺 programmed IO is better
● Saves the time for switching
● Example: Gigabit ethernet
● For slow devices 🡺 interrupt driven IO
● Context switching is negligible compared to pooling
time
● Example: Key board
DMA – Direct Memory Access
● Idea: offload the data
movement operations from
the CPU to the DMA unit
● DMA does the memory copy
● CPU does something else
● DMA generates an interrupt
when the transfer is
complete
DMA – considerations
● Reduces number of interrupts
● Less (expensive) context switches or kernel entry-exits
● Requires contiguous regions
● Uses direct physical address
● Copying
● Scatter-gather
● Bypasses MMU
● Security issues
● Shared bus must be arbitrated
Modern IO devices
● Highly complex
● Have their own processing units + memory
● Offload data process from the main CPU
● Example: Myrinet 10 gigabit NIC
Next level: NetFPGA
● Specification
● Field Programmable Gate Array (FPGA) Logic
(Xilinx Virtex-7)
● 10-Gigabit Ethernet networking ports
● Quad Data Rate Static Random Access Memory
(QDRII+ SRAM)
● Double-Date Rate Random Access Memory
(DDR3 DRAM)
● …..
● Comes with its own FPGA
● Verilog → FPGA
● Develop your own HW to process packets on
the card itself

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