Integer arithmetic

Arithmetic unit
Basic Processing Unit
Module 4
Text book 1: Chapter 2- 2.1,
Chapter 6 – 6.3 to 6.6,
Chapter 7- 7.1 to 7.3
 Outline
Integer arithmetic:
• Numbers
• Arithmetic operations and characters
• Overflow in integer arithmetic
Arithmetic unit:
• Multiplication of two numbers
• A signed operand multiplication
• Booth algorithm
• Fast Multiplication-Bit pair recoding and CSA – integer division
Basic Processing Unit:
• Fundamental concepts
• Execution of complete instruction
• Multiple bus organization

2
Number, Arithmetic Operations
• Signed Integer
• 3 major representations:
Sign and magnitude
One’s complement
Two’s complement
• Assumptions:
4-bit machine word
16 different values can be represented
Roughly half are positive, half are negative
3
Binary, Signed-Integer Representations

B Values represented

Sign and
b3 b2b1b0 magnitude 1's complement 2's complement

0 1 1 1 +7 +7 +7
0 1 1 0 +6 +6 +6
0 1 0 1 +5 +5 +5
0 1 0 0 +4 +4 +4
0 0 1 1 +3 +3 +3
0 0 1 0 +2 +2 +2
0 0 0 1 +1 +1 +1
0 0 0 0 +0 +0 +0
1 0 0 0 -0 -7 -8
1 0 0 1 -1 -6 -7
1 0 1 0 -2 -5 -6
1 0 1 1 -3 -4 -5
1 1 0 0 -4 -3 -4
1 1 0 1 -5 -2 -3
1 1 1 0 -6 -1 -2
1 1 1 1 -7 -0 -1

Figure 2.1. Binary, signed-integer representations.

4
Addition and Subtraction – 2’s Complement

4 0100 -4 1100

If carry-in to the high +3 0011 + (-3) 1101

order bit =
carry-out then ignore carry 7 0111 -7 11001
If carry-in differs from 4 0100 -4 1100
carry-out then overflow
-3 1101 +3 0011
1 10001 -1 1111

Simpler addition scheme makes twos complement the most common

choice for integer number systems within digital systems
5
 Modular number systems and 2’s complement systems

The technique works for the computation of (a+b) mod N for any
positive numbers a and b to perform addition, locate A nd move b in
clockwise direction to arrive at (a+b) mod 16 6
 Two’s Complement Representation

-1 +0
-2 1111 0000 +1
1110 0001
-3 +2 +
1101 0010
-4 1100 0011 +3 0 100 = + 4

-5 1011 0100 +4 1 100 = - 4

1010 0101
-6 +5 -
1001 0110
-7 1000 0111 +6
-8 +7

Ignoring the carry out is the natural result of using Mod N arithmetic
7
 Addition and Subtraction of signed numbers

• Rules governing the addition and subtraction of n bit signed

numbers using the 2’s complement method:
• To add 2 numbers, add their bit representations, ignoring the
carry out bit from the MSB. The sum will be the algebraically
correct value in the 2’s complement representation as long as the
answer is in the range -2n-1 to +2n-1 -1
• To subtract 2 numbers X and Y (X-Y), form the 2s complement of Y
then add it to x, as in rule 1. The sum will be the algebraically
correct value in the 2’s complement representation as long as the
answer is in the range -2n-1 to +2n-1 -1

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9
 Overflow in Integer arithmetic
• When the result of the arithmetic operation is outside the representable range,
an arithmetic overflow occurs.
• When adding unsigned numbers the carry out Cn from the MSB position serves as
the overflow indicator.
• Ex : adding +7 and +4 output is 1011, which is the code for -5
• -4 and -6 addition result is 0110=+6
• 2 conclusions:
• Overflow can occur only when adding two numbers that have the same
sign.
• Carryout signal from the sign bit position is not a sufficient indicator of
overflow when adding signed numbers.
• When both the operands X and Y have the same sign, overflow occurs when
the sign S is not the same as the signs X and Y.
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Perform the following operation on 5 bit signed numbers using
2’s complement system. Also indicate whether overflow has
occurred.
1) -9+(-7)
2) +7-(-8)
3) -10+(-13)
4) -10-(-13)

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Multiplication of unsigned numbers

Product of 2 n-bit numbers is at most a 2n-bit number.

Unsigned multiplication can be viewed as addition of shifted versions of the multiplicand.

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Multiplication of unsigned numbers

— We added the partial products at end.

— Alternative would be to add the partial products at each stage.
— Rules to implement multiplication are:
— If the ith bit of the multiplier is 1, shift the multiplicand and add the
shifted multiplicand to the current value of the partial product.
— Hand over the partial product to the next stage
— Value of the partial product at the start stage is 0.

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 Multiplication of unsigned numbers
Typical multiplication cell

Bit of incoming partial product (PPi)

jth multiplicand bit

ith multiplier bit ith multiplier bit

carry out FA carry in

Bit of outgoing partial product (PP(i+1))

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Multiplication of unsigned numbers

Multiplicand
Combinatorial array multiplier
0 m 0 m 0 m
3 2 1 0 m 0
(PP0)
q
0
0
PP1 p
0
q
1
0

r
lie
PP2

tip
p
1

ul
q

M
2
0
PP3 p
2
q
3
0
,
p p p p p
7 6 5 4 3

Product is: p7,p6,..p0

Multiplicand is shifted by displacing it through an array of adders.

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Multiplication of unsigned numbers

Product of 2 n-bit numbers is at most a 2n-bit number.

Unsigned multiplication can be viewed as addition of shifted versions of the multiplicand.

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Multiplication of Positive (unsigned) numbers

• Combinatorial array multipliers are:

• Extremely inefficient.
• Have a high gate count for multiplying numbers of practical size such as
32-bit or 64-bit numbers.
• Perform only one function, namely, unsigned integer product.
• Improve gate efficiency by using a mixture of combinatorial array
techniques and sequential techniques requiring less combinational
logic.

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Multiplication of Positive (unsigned) numbers
Sequential Circuit Multiplier
Register A (initially 0)

Shift right

a a q q
C n - 1 0 n - 1 0

Multiplier Q
Add/Noadd
control

n-bit
Adder
MUX Control
sequencer

0 0

m m
n - 1 0

Multiplicand M

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19
 Sequential multiplication
13 *11 = 143

M
1 1 0 1
Initial configuration
0 0 0 0 0 1 0 1 1
C A Q
0 1 1 0 1 1 0 1 1 Add First cycle
0 0 1 1 0 1 1 0 1 Shift

1 0 0 1 1 1 1 0 1 Add Second cycle

0 1 0 0 1 1 1 1 0 Shift

0 1 0 0 1 1 1 1 0 No add
Shift Third cycle
0 0 1 0 0 1 1 1 1

1 0 0 0 1 1 1 1 1 Add
0 1 0 0 0 1 1 1 1 Shift Fourth cycle

Product

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• Perform sequential multiplication : 12 *15 (=180)

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Signed-operand Multiplication

• Considering 2’s-complement signed operands, what will

happen to (-13)´(+11) if following the same method of
unsigned multiplication?
1 0 0 1 1 (- 13)
0 1 0 1 1 (+11)
1 1 1 1 1 1 0 0 1 1
1 1 1 1 1 0 0 1 1
Sign extension is
shown in red 0 0 0 0 0 0 0 0
1 1 1 0 0 1 1
0 0 0 0 0 0
1 1 0 1 1 1 0 0 0 1 (- 143)
Sign extension of negative multiplicand.

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Signed-operand Multiplication

—For a negative multiplier, a straightforward solution is to form

the 2’s-complement of both the multiplier and the multiplicand
and proceed as in the case of a positive multiplier.
—This is possible because complementation of both operands
does not change the value or the sign of the product.
—A technique that works equally well for both negative and
positive multipliers – Booth algorithm.

23
Booth Algorithm Steps

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Booth Algorithm

Multiplier Version of multiplicand

selected by biti
Biti Biti -1

0 0 0 xM
0 1 +1 xM
1 0 -1 x M
1 1 0 xM

Booth multiplier recoding table.

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Booth Algorithm

0 1 1 0 1 (+13 ) 01101
X 1 1 0 1 0 (-6 ) 0-1+1-1 0
0000000000
111110011
00001101
1110011
000000
1 1 1 0 1 1 0 0 1 0 (-78 )

Booth multiplication with a negative multiplier.

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• Multiply each of the following pairs of signed 2’s complement
number using the Booths algorithm. (A=Multiplicand and
B=Multiplier)
• A=010111 and B=110110
• A=110011 and B=101100
• A=110101 and B=011011
• A=001111 and B=001111

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Fast Multiplication

• Bit-Pair Recoding of Multipliers

• Carry-Save Addition of Summands
• Bit-pair recoding halves the maximum number of summands
• The second technique reduces the time needed to add the summands

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29
Fast Multiplication
Bit-Pair Recoding of Multipliers

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Fast Multiplication
Bit-Pair Recoding of Multipliers

0 1 1 0 1
0 - 1 +1 - 1 0
0 0 0 0 0 0 0 0 0 0
1 1 1 1 1 0 0 1 1
0 0 0 0 1 1 0 1
1 1 1 0 0 1 1
0 1 1 0 1 ( + 13) 0 0 0 0 0 0
´ 1 1 0 1 0 (- 6) 1 1 1 0 1 1 0 0 1 0 ( - 78)

0 1 1 0 1
0 -1 - 2
1 1 1 1 1 0 0 1 1 0
1 1 1 1 0 0 1 1
0 0 0 0 0 0
1 1 1 0 1 1 0 0 1 0

Figure 6.15. Multiplication requiring only n/2 summands.

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Fast Multiplication
Carry-Save Addition of Summands
• Ripple carry array

P P P P P P P P
7 6 5 4 3 2 1 0

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Fast Multiplication
Carry-Save Addition of Summands

1 0 1 1 0 1 (45) M
X 1 1 1 1 1 1 (63) Q
1 0 1 1 0 1 A
1 0 1 1 0 1 B
1 0 1 1 0 1 C
1 0 1 1 0 1 D
1 0 1 1 0 1 E
1 0 1 1 0 1 F
1 0 1 1 0 0 0 1 0 0 1 1 (2,835) Product

Figure 6.17. A multiplication example used to illustrate carry-save addition as shown in Figure 6.18.

33
Fast Multiplication
Carry-Save Addition of Summands

• Carry-save array

P P P P P P P P
7 6 5 4 3 2 1 0

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Fast Multiplication
Carry-Save Addition of Summands

• Consider the addition of many summands, we can:

1. Group the summands in threes and perform carry-save addition on
each of these groups in parallel to generate a set of S and C vectors
in one full-adder delay
2. Group all of the S and C vectors into threes, and perform carry-
save addition on them, generating a further set of S and C vectors in
one more full-adder delay
3. Continue with this process until there are only two vectors
remaining
4. They can be added in a Ripple Carry Adder(RCA) or Carry Look
Ahead adder (CLA) to produce the desired product.
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 1 0 1 1 0 1 M
x 1 1 1 1 1 1 Q

1 0 1 1 0 1 A
1 0 1 1 0 1 B
1 0 1 1 0 1 C
1 1 0 0 0 0 1 1 S1
0 0 1 1 1 1 0 0 C1
1 0 1 1 0 1 D
1 0 1 1 0 1 E
1 0 1 1 0 1 F
1 1 0 0 0 0 1 1 S2
0 0 1 1 1 1 0 0 C2
1 1 0 0 0 0 1 1 S1
0 0 1 1 1 1 0 0 C1
1 1 0 0 0 0 1 1 S2
1 1 0 1 0 1 0 0 0 1 1 S3
0 0 0 0 1 0 1 1 0 0 0 C3
0 0 1 1 1 1 0 0 C2
0 1 0 1 1 1 0 1 0 0 1 1 S4
+ 0 1 0 1 0 1 0 0 0 0 0 C4
1 0 1 1 0 0 0 1 0 0 1 1 Product

Figure 6.18. The multiplication example from Figure 6.17 performed using carry-save addition.

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Integer Division
Manual Division

21 10101
13 274 1101 100010010
26 1101
14 10000
13 1101
1 1110
1101
1

Longhand division examples.

37
Integer Division
Longhand Division Steps

• Position the divisor appropriately with respect to the dividend

and performs a subtraction.
• If the remainder is zero or positive, a quotient bit of 1 is
determined, the remainder is extended by another bit of the
dividend, the divisor is repositioned, and another subtraction is
performed.
• If the remainder is negative, a quotient bit of 0 is determined,
the dividend is restored by adding back the divisor, and the
divisor is repositioned for another subtraction.

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Integer Division
Circuit Arrangement

Shift left

an an-1 a0 qn-1 q0
Dividend Q
A Quotient
Setting

N+1 bit Add/Subtract

adder
Control
Sequencer

0 mn-1 m0

Divisor M

Figure 6.21. Circuit arrangement for binary division.

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Integer Division
Restoring Division
1. Initialize registers for two n-bit division operation, register M with
divisor, register Q with dividend, n+1(sign bit) bits register A with zero
2. Repeat n times
i. Left shift Q to A by one binary position.
ii. Subtract M from A, and place the answer back in A i,e., A=A-M
iii. If the sign of A is 1, set q0=0 and add M back to A (A=A+M -restore A);
otherwise, set q0 to 1 (no restore)
iv. Repeat these steps n times
3. After n cycles, A will contain remainder and Q contains Quotient

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Restoring Division Example
Initially 0 0 0 0 0 1 0 0 0
0 0 0 1 1
Shift 0 0 0 0 1 0 0 0
Subtract 1 1 1 0 1 First cycle
Set q0 1 1 1 1 0
Restore 1 1
0 0 0 0 1 0 0 0 0
1 0
Shift 0 0 0 1 0 0 0 0
1 1 10 0 0 Subtract 1 1 1 0 1
1 1 Set q0 1 1 1 1 1 Second cycle
Restore 1 1
1 0 0 0 0 1 0 0 0 0 0
Shift 0 0 1 0 0 0 0 0
Subtract 1 1 1 0 1
Set q0 0 0 0 0 1 Third cycle

Shift 0 0 0 1 0 0 0 0 1
Subtract 1 1 1 0 1 0 0 1
Set q0 1 1 1 1 1 Fourth cycle
Restore 1 1
0 0 0 1 0 0 0 1 0

Remainder Quotient
Figure 6.22. A restoring-division example.

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Integer Division
Nonrestoring Division

1. Initialize registers for two n-bit division operation, register

M with divisor, register Q with dividend, n+1(sign bit) bits
register A with zero
2. Repeat n times
i. Left shift Q to A by one binary position.
ii. If the sign of A is 0, subtract M from A i.e., A=A-M; else if the
sign of A is 1 add M to A i.e., A=A+M.
iii. If the sign of A is 0, set q0 to 1; otherwise, set q0 to 0.
3. After n cycles, If the sign of A is 1, add M to A i.e., A=A+M

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Nonrestoring Division Examples
Initially 0 0 0 0 0 1 0 0 0
0 0 0 1 1
Shift 0 0 0 0 1 0 0 0 First cycle
Subtract 1 1 1 0 1
Set q 0 1 1 1 1 0 0 0 0 0

Shift 1 1 1 0 0 0 0 0
Add 0 0 0 1 1 Second cycle

Set q 1 1 1 1 1 0 0 0 0
0

Shift 1 1 1 1 0 0 0 0
1 1 1 1 1 Add 0 0 0 1 1 Third cycle
Restore
0 0 0 1 1 Set q 0 0 0 0 1 0 0 0 1
remainder 0
Add 0 0 0 1 0
Remainder Shift 0 0 0 1 0 0 0 1
Subtract 1 1 1 0 1 Fourth cycle
Set q 1 1 1 1 1 0 0 1 0
0

Quotient
A nonrestoring-division example.

43
Outline: Basic Processing Unit
• Some Fundamental concepts
• Execution of a Complete Instruction
• Multiple bus organization

44
 Fundamental Concepts
• Processor fetches one instruction at a time and perform the operation
specified.
• Instructions are fetched from successive memory locations until a branch
or a jump instruction is encountered.
• Processor keeps track of the address of the memory location containing
the next instruction to be fetched using Program Counter (PC).
• Instruction Register (IR)

46
 Executing an Instruction
• Fetch the contents of the memory location pointed to by the PC.
The contents of this location are loaded into the IR (fetch phase).
IR ← [[PC]]
• Assuming that the memory is byte addressable, increment the
contents of the PC by 4 (fetch phase).
PC ← [PC] + 4
• Carry out the actions specified by the instruction in the IR
(execution phase).

47
Processor Organization – Single Bus Structure

48
49
50
Executing an Instruction
• Transfer a word of data from one processor register to another or to
the ALU.
• Perform an arithmetic or a logic operation and store the result in a
processor register.
• Fetch the contents of a given memory location and load them into a
processor register.
• Store a word of data from a processor register into a given memory
location.

51
 Internal processor
b us

R i in

Register Transfers
R i

R i out

Y in

Constant 4

Select MUX

A B

ALU

Z in

Z out

52
Figure 7.2. Input and output gating for the registers in Figure 7.1.
Performing an Arithmetic or Logic Operation

• The ALU is a combinational circuit that has no internal storage.

• ALU gets the two operands from MUX and bus. The result is
temporarily stored in register Z.
• What is the sequence of operations to add the contents of
register R1 to those of R2 and store the result in R3?
1. R1out, Yin
2. R2out, Select Y, Add, Zin
3. Zout, R3in

53
Control Sequence for the Instruction

54
Processor Organization – Single Bus Structure

56
 Fetching a Word from Memory

• Address into MAR;

• Issue Read
operation;
• Data into MDR;
• Wait for MFC
Signal;
• Place MDR into
bus;
• Let data into MDR

57
Fetching a Word from Memory
• The response time of each memory access varies (cache miss, memory-mapped
I/O,…).
• To accommodate this, the processor waits until it receives an indication that the
requested operation has been completed (MFC).
• Move (R1), R2

58
59
Storing A Word to Memory

60
Execution of a Complete Instruction
Add (R3), R1
1. Fetch the instruction
2. Fetch the first operand (the contents of the memory location
pointed to by R3)
3. Perform the addition
4. Load the result into R1

61
Execution of a Complete Instruction

Add (R3), R1

62
 Execution of Branch Instructions

• A branch instruction replaces the contents of PC with the branch

target address, which is usually obtained by adding an offset X
given in the branch instruction.
• The offset X is usually the difference between the branch target
address and the address immediately following the branch
instruction.
• Unconditional branch

63
Execution of Branch Instructions

64
Multiple-Bus Organization
• While the steps still have to be performed by sequentially changing
from one step to another, the number of independent steps can be
clubbed into single step in a multiple bus organization.
• Improvement in performance in a multiple bus organization

65
Multiple-Bus Organization

66
Multiple-Bus Organization
Add R4, R5, R6

67