V il

Verilog HDL Basics

B i

ECE301 - VLSI System Design

Fall 2010
 What is Verilog

• Hardware Description Language (HDL)

• Developed in 1984

• Standard: IEEE 1364, Dec 1995

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 Basic Limitation of Verilog

Description of digital systems only

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 Abstraction Levels in Verilog

B h i l
Behavioral

RTL Our focus

Gate

Layout
ayou (V
(VLSI)
S)

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 Main Language Concepts (i)

• Concurrency

• Structure

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 Main Language Concepts (ii)

• Procedural
P d l Statements
St t t

• Time

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 User Identifiers

• Formed from {[A{[A-Z],

Z], [a
[a-z],
z], [0
[0-9],
9], _,, $}, but ..
• .. can’t begin with $ or [0-9]
– myidentifier 
– m_y_identifier 
– 3my_identifier
_ 
– $my_identifier 
– _myidentifier$
y $ 
• Case sensitivity
– myid ≠ Myid

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 Comments

• // The rest of the line is a comment

• /* Multiple line
comment */

• /* Nesting /* comments */ do NOT work */

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 Verilog Value Set

• 0 represents low logic level or false condition

• 1 represents high logic level or true condition

• x represents unknown logic level

• z represents high impedance logic level

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 Numbers in Verilog (i)

<size>’<radix> <value>

Binary
Bi → b or B
No of
Octal → o or O Consecutive chars
bits
Decimal → d or D 0-f, x, z
Hexadecimal → h or H

– 8’h ax = 1010xxxx
– 12
12’o
o 3zx7 = 011zzzxxx111

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 Numbers in Verilog (ii)

• You can insert “_” for readability

– 12’b 000_111_010_100
– 12’b 000111010100
– 12’o 07_24 Represent the same number

• Bit extension
– MS bit = 0, x or z ⇒ extend this
• 4’b x1 = 4’b xx_x1

– MS bit = 1 ⇒ zero extension

• 4’b 1x = 4’b 00_1x

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 Numbers in Verilog (iii)

• If size is ommitted it
– is inferred from the value or
– takes the simulation specific number of
bits or
– takes the machine specific number of
bits
• If radix is ommitted too .. decimal is assumed

– 15 = <size>’d 15

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 Nets (i)

• Can be thought as hardware wires driven by logic

• Equal z when unconnected
• Various types of nets
– wire
– wand (wired-AND)
– wor ( i d OR)
(wired-OR)
– tri (tri-state)
• IIn following
f ll i examples:
l Y iis evaluated,
l t d automatically,
t ti ll
every time A or B changes

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 Nets (ii)
A wire Y; // declaration
Y
B assign Y = A & B;

wand Y; // declaration
assign
i Y = A
A;
A assign Y = B;
Y
B
wor Y; // declaration
assign Y = A;
assign Y = B;

dr
tri Y; // declaration
A Y
assign Y = (dr) ? A : z;

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 Registers
• Variables that store values
• Do not represent real hardware but ..
• .. real hardware can be implemented with registers
• Only one type: reg
reg A, C; // declaration
// assignments are always done inside a procedure
A = 1;

C = A; // C gets the logical value 1

A = 0; // C is still 1
C = 0; // C is now 0
• Register values are updated explicitly!!

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 Vectors

• Represent buses
wire [
[3:0]
] busA;
reg [1:4] busB;
reg [1:0] busC;
• Left number is MS bit
• Slice management

busC = busA[2:1]; ⇔ busC[1] = busA[2];

busC[0] = busA[1];
• Vector assignment (by position!!)
busB[1] = busA[3];
busB[2] = busA[2];
busB = busA; ⇔ busB[3] = busA[1];
busB[4] = busA[0];

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 Integer & Real Data Types

• Declaration
integer i, k;
real r;
• Use as registers (inside procedures)
i = 1; // assignments occur inside procedure
r = 2.9;
.9;
k = r; // k is rounded to 3
• Integers are not initialized!!
• Reals
R l are iinitialized
iti li d tto 0.0
00

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 Time Data Type

• Special data type for simulation time measuring

• Declaration

y_time;
time my ;
• Use inside procedure

my time = $time; // get current sim time

my_time
• Simulation runs at simulation time, not real time

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 Arrays (i)

• Syntax
integer count[1:5]; // 5 integers
reg var[-15:16]; // 32 1-bit regs
reg [7:0] mem[0:1023]; // 1024 8-bit
8 bit regs
• Accessing array elements
– Entire element: mem[10] = 8’b 10101010;
– Element subfield (needs temp
storage):
reg [7:0] temp;
..
temp = mem[10];
var[6] = temp[2];

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 Arrays (ii)

• Limitation: Cannot access array subfield or entire array at

once
var[2:9] = ???; // WRONG!!
var = ???;
??? // WRONG!!
• No multi-dimentional arrays
eg var[1:10]
reg a [ : 0] [
[1:100];
: 00]; // WRONG!!
O G!!
• Arrays don’t work for the Real data type
real r[1:10]; // WRONG !!

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 Strings
• Implemented with regs:
reg [8*13:1] string_val; // can hold up to 13 chars
..
string_val = “Hello Verilog”;
string_val = “hello”; // MS Bytes are filled with 0
string_val = “I am overflowed”; // “I ” is truncated
• Escaped chars:
– \n newline
– \t tab
– %% %
– \\ \
– \“ “

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 Logical Operators

• && → logical AND

• || → logical OR
• ! → logical NOT
• Operandsd evaluated
l d to ONE bbit value:
l 0, 1 or x
• Result is ONE bit value: 0, 1 or x
A = 6; A && B → 1 && 0 → 0
B = 0; A || !B → 1 || 1 → 1
C = x; C || B → x || 0 → x

but C&&B=0

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 Bitwise Operators (i)

• & → bitwise AND

• | → bitwise OR
• ~ → bitwise NOT
• ^ → bitwise XOR
• ~^ or ^~ → bitwise XNOR

• Operation on bit by bit basis

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 Bitwise Operators (ii)

c = ~a; c = a & b;

• a = 4’b1010;
b = 4’b1100;

c = a ^ b;

• a = 4’b1010;
b = 2’b11;

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 Reduction Operators

• & → AND
• | → OR
• ^ → XOR
• ~& → NAND
• ~| → NOR
• ~^ or ^~ → XNOR

• One multi-bit operand

p → One single-bit
g result
a = 4’b1001;
..
c = |a; // c = 1|0|0|1 = 1

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 Shift Operators

• >> → shift right

• << → shift left

• Result is same size as first operand, always zero

filled

a = 4’b1010
4’b1010;
...
d = a >> 2; // d = 0010
c = a << 1;
1 // c = 0100

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 Concatenation Operator

• {op1, op2, ..} → concatenates op1, op2, .. to

single
g number
• Operands must be sized !!
reg a;
reg [2:0]
[2 0] b
b, c;
..
a = 1’b 1;
b = 3’b 010;
c = 3’b 101;
catx = {a, b, c}; // catx = 1_010_101
caty = {b, 2’b11, a}; // caty = 010_11_1
catz = {b, 1}; // WRONG !!
• Replication ..
catr = {4{a}, b, 2{c}}; // catr = 1111_010_101101
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 Relational Operators

• > → greater than

• < → less than
• >= → greater or equal than
• <= → less or equal than

• Result is one bit value: 0, 1 or x

1 > 0 →1
’b1x1 <
<= 0 →x
10 < z →x

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 Equality Operators

• == → logical equality
Return 0, 1 or x
• != → logical inequality
• === → case equality
• !== → case inequality Return 0 or 1

– 4’b 1z0x == 4’b 1z0x →x

– 4’b
4 b 1z0x !=
! 44’b
b 1z0x →x
– 4’b 1z0x === 4’b 1z0x →1
– 4’b
4 b 1z0x !== 4’b
4 b 1z0x →0
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 Conditional Operator

• cond_expr ? true_expr : false_expr

• Like a 2-to-1 mux ..

A
1
Y
Y = (sel)? A : B;
B 0
sel

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 A ith
Arithmetic
ti OOperators
t (i)

• +, -, *, /, %
• If any operand is x the result is x
• Negative registers:

– regs can be assigned negative but are

treated
d as unsigned
i d
reg [15:0] regA;
..
regA = -4’d12; // stored as 216-12 = 65524
regA/3
g / evaluates to 21861

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 A ith
Arithmetic
ti OOperators
t (ii)

• Negative integers:

– can be assigned negative values

– different treatment depending on base
specification or not
reg [15:0] regA;
integer
g intA;
;
..
intA = -12/3; // evaluates to -4 (no base spec)
intA = -’d12/3; // evaluates to 1431655761 (base spec)
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 Operator Precedence

Use parentheses
U th tto
enforce your
priority

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 Hierarchical Design

Top Level
E.g.
Module

Full Adder
Sub-Module Sub-Module
1 2

Half Adder Half Adder

Basic Module Basic Module Basic Module
1 2 3

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 Module

module my_module(out1,
my module(out1 .., inN);

in1 my_module out1 output out1, .., outM;

out2 input in1, .., inN;

in2

f .. // declarations
inN outM .. // description of f (maybe
.. // sequential)

endmodule

Everything you write in Verilog must be inside a module

exception: compiler directives

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 Example: Half Adder

A module half_adder(S, C, A, B);

S
output S, C;
B input A, B;
C
wire S, C, A, B;

assign S = A ^ B;
A S
Half assign C = A & B;
B Adder C
endmodule
d d l

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 Example: Full Adder

in1 A Half S I1 A Half S sum

Adder 1 Adder
i 2
in2 B C I2 B C I3
ha1 ha2 cout

ccin
module full_adder(sum, cout, in1, in2, cin);
output sum, cout;
input in1, in2, cin;

wire sum, cout, in1, in2, cin;

Module wire I1, I2, I3; Instance
name name
half_adder
h lf dd h
ha1(I1,
1( 1 I2,
2 iin1,
1 iin2);
2)
half_adder ha2(sum, I3, I1, cin);

assign cout = I2 || I3;

endmodule
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 Hierarchical Names

ha2.A

in1 A Half S I1 A Half S sum

Adder 1 Adder
in2 B C I2 B C I3
ha1 ha2 cout

cin

Remember to use instance names,

not module names

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 Port Assignments

module
• Inputs
I reg or net net

module

• Outputs reg or net net

module
net net
• Inouts

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 Continuous Assignements a closer look
• Syntax:
assign #del <id> = <expr>;

optional net type !!

• Where to write them:
– inside a module
– outside
t id procedures
d
• Properties:
– they all execute in parallel
– are order independent
– are continuously active
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 Structural Model (Gate Level)

• Built-in gate primitives:

and, nand, nor, or, xor, xnor, buf, not, bufif0,
bufif1, notif0, notif1

• Usage:
U
nand (out, in1, in2); 2-input NAND without delay
and #2 (out, in1, in2, in3); 3-input AND with 2 t.u.
d l
delay
not #1 N1(out, in); NOT with 1 t.u. delay and instance
name
xor X1(out in1, in2); 2-input XOR with instance name
X1(out, in1
• Write them inside module, outside procedures

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 Example: Half Adder,
2 d Implementation
2nd I l t ti

A module half_adder(S, C, A, B);

S
output S, C;
B input A, B;
C
wire S, C, A, B;

xor #2 (S, A, B);

and #1 (C, A, B);
Assuming:
• XOR: 2 t.u.
t u delay endmodule
d d l
• AND: 1 t.u. delay

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 Behavioral Model - Procedures (i)

• Procedures = sections of code that we know they

execute sequentially
• Procedural statements = statements inside a procedure
(they execute sequentially)
• e.g. another 2-to-1 mux implem:
begin
if (sel == 0)
Y = B;
else
Execution
Y = A
A;
Flow Procedural assignments:
end Y must be reg !!

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 Behavioral Model - Procedures (ii)

• Modules can contain any number of procedures

• Procedures execute in parallel (in respect to each other)
and ..
• .. can be expressed in two types of blocks:

– initial → they execute only once

– always
y → they
y execute for ever
(until simulation finishes)

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 “Initial”
Initial Blocks
• Start execution at sim time zero and finish when their
last statement executes
module nothing;

initial
$display(“I’m first”);
Will be displayed
initial begin at sim time 0
#50;
$display(“Really?”);
Will be displayed
end
at sim time 50
endmodule

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 “Always”
Always Blocks
• Start execution at sim time zero and continue until sim
finishes

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 Events (i)
• @
always @(signal1 or signal2 or ..) begin
..
end execution triggers every
time any signal changes

always @(posedge clk) begin

.. execution triggers every
end time clk changes
from 0 to 1
always @(negedge clk) begin
..
execution triggers every
end time clk changes
f
from 1 to
t 0
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 Examples

• 3rd half adder implem • Behavioral edge-

module half_adder(S, C, A, B); triggered DFF implem
output S, C; module dff(Q, D, Clk);
input A, B; output Q;
input D, Clk;
reg S,C;
wire A, B; reg Q;
wire D, Clk;
always @(A or B) begin
S = A ^ B; always @(posedge Clk)
C = A && B; Q = D;
end
d
endmodule
endmodule

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 Events (ii)

• wait (expr)
always begin
wait (ctrl)
#10 cnt = cnt + 1;
#10 cnt2 = cnt2 + 2; execution loops every
time ctrl = 1 (level
end
sensitive timing
g control))

• e.g. Level triggered DFF ?

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 Example

always @(res or posedge clk) begin

res if (res) begin
a Y = 0;
b Y W = 0;
end
else begin
c W Y = a & b;
W = ~c;
clk end
end

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 Timing (i)

d
initial begin
g
#5 c = 1; c
#5 b = 0;
#5 d = c; b
end
0 5 10 15
Time
Each assignment
g is
blocked by its previous one

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 Timing (ii)

d
initial begin
g
fork c
#5 c = 1;
#5 b = 0; b
#5 d = c;
join 0 5 10 15
end Time

Assignments are
not blocked here

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 Procedural Statements: if
E.g. 4-to-1 mux:
module mux4_1(out, in, sel);
output out;
if (expr1)
( ) input [3:0] in;
true_stmt1; input [1:0] sel;

reg out;
else if (expr2) wire [3:0] in;
wire [1:0] sel;
true_stmt2;
.. always @(in or sel)
if (sel == 0)
else out = in[0];
def_stmt; else if (sel == 1)
out = in[1];
else if (sel == 2)
out = in[2];
else
out = in[3];
endmodule

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 Procedural Statements: case

E.g. 4-to-1 mux:

module mux4
mux4_1(out,
1(out in
in, sel);
case (expr) output out;
input [3:0] in;
input [1:0] sel;
item_1,
item 1 .., item_n:
item n: stmt1;
reg out;
item_n+1, .., item_m: stmt2; wire [3:0] in;
.. wire [1:0] sel;

default: def_stmt; always @(in or sel)

case (sel)
0: out = in[0];
endcase 1: out = in[1];
2: out = in[2];
3: out = in[3];
endcase
endmodule

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 Procedural Statements: for
for (init_assignment; cond; step_assignment)
stmt;;
E.g.
module count(Y, start);
output [3:0] Y;
input start;

reg [3:0] Y;
wire start;
integer i;

initial
Y = 0;

always @(posedge start)

for (i = 0; i < 3; i = i + 1)
#10 Y = Y + 1;
endmodule

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 Procedural Statements: while

E.g.
module count(Y, start);
output [3:0]
[3 0] Y;
input start;

reg [3:0] Y;
wire
i start;
t t
integer i;
while (expr) stmt;
initial
Y = 0
0;

always @(posedge start) begin

i = 0;
while
hil (i < 3) bbegin
i
#10 Y = Y + 1;
i = i + 1;
end
end
d
endmodule
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 Procedural Statements: repeat

E.g.
module count(Y, start);
output [3:0] Y;
i
input
t start;
t t

repeat (times) stmt; reg [3:0] Y;

wire start;

initial
Can be either an Y = 0;
integer or a variable
always
l @(
@(posedge
d start)
t t)
repeat (4) #10 Y = Y + 1;
endmodule

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 Procedural Statements: forever

Typical example:
clock generation in test modules
module test;

reg clk; Tclk = 20 time units

forever stmt;
initial begin
clk = 0;
forever #10 clk = ~clk;
Executes until sim end
finishes
other_module1
other module1 o1(clk
o1(clk, ..);
);
other_module2 o2(.., clk, ..);

endmodule

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 Mixed Model

Code that contains various both structure and behavioral styles

module simple(Y
simple(Y, c,
c clk,
clk res);
output Y;
input c, clk, res;

reg Y;
wire c, clk, res;
res wire n;
c n Y not(n, c); // gate-level
clk
always @(res or posedge clk)
if (
(res)
)
Y = 0;
else
Y = n;
endmodule

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 System Tasks

Always written inside procedures

• $display(“..”, arg2, arg3, ..); → much like printf(), displays

formatted string in std output when encountered
• $monitor(“..”,
$ it (“ ” arg2,2 arg3,
3 ..);
) → like
lik $display(),
$di l () b butt ..
displays string each time any of arg2, arg3, .. Changes
• $stop; → suspends sim when encountered
• $finish; → finishes sim when encountered
• $fopen(“filename”); → returns file descriptor (integer); then,
you can use $fdisplay(fd, “..”, arg2, arg3, ..); or
$fmonitor(fd, “..”, arg2, arg3, ..); to write to file
• $fclose(fd); → closes file
• $
$random(seed);
( ); → returns random integer;
g ;g give her an
integer as a seed
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 $display
$d sp ay & $monitor
$ o to string
st g format
o at

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 Compiler Directives

• `include “filename” → inserts contents of file into current

file; write it anywhere in code ..

• `define <text1> <text2> → text1 substitutes text2;

– e.g. `define BUS reg [31:0] in declaration part: `BUS
data;

• `timescale <time unit>/<precision>

– e.g.
g `timescale 10ns/1ns later: #5 a = b;

50ns

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 Parameters

in[3:0] p_in[3:0]
out[2:0]
A. Implelementation
wu
without parameters

wd
clk module
d l dff2bit(Q
dff2bit(Q, D,
D clk);
lk)
module dff4bit(Q, D, clk); output [1:0] Q;
output [3:0] Q; input [1:0] D;
p
input [
[3:0]] D; input clk;
input clk;
reg [1:0] Q;
reg [3:0] Q; wire [1:0] D;
wire [
[3:0]] D;
; wire clk;
wire clk;
always @(posedge clk)
always @(posedge clk) Q = D;
Q = D;
;
endmodule
endmodule
FALL2010 ECE301 – VLSI System Design 65
 Parameters (ii)
module top(out, in, clk);
A. Implelementation output [1:0] out;
without parameters (cont.) input [3:0] in;
input clk;

wire [1:0] out;

wire [3:0] in;
wire clk;

wire [
[3:0]
] p_
p in; // internal nets
wire wu, wd;

assign wu = p_in[3] & p_in[2];

assign
g wd = p_
p in[1]
[ ] & p_
p in[0];
[ ];

dff4bit instA(p_in, in, clk);

dff2bit instB(out, {wu, wd}, clk);
// notice the concatenation!!

endmodule
FALL2010 ECE301 – VLSI System Design 66
 Parameters (iii)
module top(out, in, clk);
B. Implelementation p
output [1:0] out;
input [3:0] in;
with parameters input clk;
wire [1:0] out;
module
d l dff(
dff(Q, D, clk);
lk) wire [3:0] in;
parameter WIDTH = 4; wire clk;
output [WIDTH-1:0] Q; wire [3:0] p_in;
input [WIDTH-1:0] D; wire wu,
, wd;
;
input clk;
assign wu = p_in[3] & p_in[2];
reg [WIDTH-1:0] Q; assign wd = p_in[1] & p_in[0];
wire [WIDTH-1:0] D;
wire clk; dff instA(p
instA(p_in,
in in
in, clk)
clk);
// WIDTH = 4, from declaration
always @(posedge clk) dff instB(out, {wu, wd}, clk);
Q = D; p
defparam instB.WIDTH = 2;
;
// We changed WIDTH for instB only
endmodule
FALL2010 ECE301 –endmodule
VLSI System Design 67
 Testing
g Your Modules

module top_test;
wire [
[1:0]
] t_out;; // Top’s
p signals
g
reg [3:0] t_in;
reg clk;

top inst(t_out, t_in, clk); // Top’s instance

initial begin // Generate clock

clk = 0;
forever #10 clk = ~clk;
end
d

initial begin // Generate remaining inputs

$monitor($time, " %b -> %b", t_in, t_out);
#5 t
t_in
in = 4'b0101;
4 b0101;
#20 t_in = 4'b1110;
#20 t_in[0] = 1;
#300 $finish;
end

endmodule
FALL2010 ECE301 – VLSI System Design 68