Lecture: II

Course Title: Hardware Model

Course Code: CPE201
January 24, 2023

1 Introduction
Engineers create computer programs to solve a given task, in order to do this, the engi-
neers instruct the computer the way the operation needs to be carried-out. The engineers
needs to:

• Understand the problem

• Define the problem

• Break the problem into smaller chunks

• Subject the problem into algorithm

• Solve the problem piece by piece

• Result interpretation

The above listed process needed to be written in such a way that the computer can
understand it. It can be inform of pseudocode, algorithm, flowchart, etc.

The problem needs to be represented in assembly language or machine language. This

might be too complex and inefficient for human to write. Base on these, there are high/low
level programming languages that have been developed to addressed these issues, example
will have C/C++ & Rust. However, knowing selected parts of these languages will
enable us to write a large number of programs. In this lecture, we will discuss on the
hardware model and how its relation to program execution.

2 Hardware Model
Computer systems are highly integrated and also complicated machine that is composed
of dozens of chips, each chips composed of thousands of transistors, capacitors, ect. Mod-
eling is the act of creating models. Models is the virtual representation of a physical/real-
world system, that is, it is the process of simplifying reality to expose some of the most
important features that are necessary to explain part of that reality. The diagram shown

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in the fig:1 is a computational model of a computer systems equipped with a multi-core
processor, main memory, a system support chipset, as well as a number of connected
external devices, such as a keyboard, a screen, disks, and network devices.
The central part consists of a processor with a number of cores that are independent

Figure 1: Model of a Computer System by Boguslaw Cyganek)

computational units. A processor is usually augmented by a system support chipset,

which is responsible for interfacing with various modules external to the processor. The
most important is the main memory that contains code and data. In addition to the
main processor with its cores, computations can be performed by cores in the graphics
processing unit (GPU).

Fig:2 depicts a model of a multi-core processor with various types of memory. The multi-
core processor has a series of onboard memory caches and has an external main memory
module attached. The arithmetic logic unit (ALU) performs low-level machine opera-
tions. The closest memory storage consists of registers. In addition to the universal
registers, there are two special ones: PC (the program counter that indicates the current
position of the executed code) and SP (the stack pointer, which points at the memory
region called the stack, containing return addresses to the procedures and some parame-
ters). L1, L2, and L3 are memory caches with different sizes and access times (1c denotes
a single processor cycle). The cores can operate independently, sharing only part of the
upper-level memory. The processor is connected with external main memory that stores

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Figure 2: A model of a multi-core processor with various types of memory by Boguslaw
Cyganek)

both code and data (von Neumann architecture).

The arithmetic logic unit (ALU) is the heart of every core and performs basic low-level
opera- tions. These are in the form of binary-encoded commands stored in memory,
which, after decod- ing, tell the ALU what to do: for example, with values stored in
other memory regions. These commands are in an encoded form called machine language
and are not human-readable. They can be represented in an equivalent assembly lan-
guage that can be understood and even, in rare cases, used to write software; however,
each processor has its own machine language, so writing in assembly is tedious, error-
prone, and decidedly hardware dependent. Fortunately, these days we can avoid such
inconvenience with the help of high-level languages such as C++. These are much easier
for humans to understand and are independent of processors and operating systems. In
addition, code written with their help can be easily translated into almost any known
machine representation with the help of a compiler.

As shown in fig:2 the ALU usually has relatively limited access to a particular block of
the core’s registers. Depending on the processor, these are a few memory locations that
are able to store only a very limited number of computer words, mostly for ALU opera-
tions. In addition to the universal registers, there are two special ones: PC, the program
counter, which indicates the current position of the executed code; and SP, the stack
pointer, which points at an external memory region called the stack that contains re-

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turn addresses to procedures and sometimes call parameters. The figure also two specific
flags: zero (Z) and carry (C). In practice, these are two of many flags, usually encoded
as specific bits in one of the control registers. The reason we have highlighted them is
that they help to understand some numerical operations.

L1, L2, and L3 are memory blocks called memory caches and have different sizes and ac-
cess times. Their characteristic feature is that the further from the ALU such a memory
cache is, the larger its capacity – but its access time is also longer. At the very end of this
specific capacity-speed triangle is the main memory: its capacity is a few orders of mag-
nitude greater than that of the memory caches, but it also has the longest access times.
This is due to the hardware technologies used to manufacture it. Registers and caches
are internal processor memory (cores). But this is the external main memory, which, in
the von Neumann architecture,1 contains the entire body of com- piled executable code
for a program as well as most of its data. More specifically, this is operational memory,
which, unlike disk storage, can be directly addressed by a processor in order to execute a
program. From the programming point of view, it is important to realize that to access
any cell in the operational memory.

The following two specialized signal buses need to be handled by the pro- cessor and the
chipset:

• Address – All of this bus’s signals specify the location of a memory cell to access.
For historical reasons, the smallest possible cell to address is a byte, i.e. 8 bits of
data. The logical addresses cor- respond to the C/C++ pointers.

• Data – This bidirectional bus contains data to be read from or written to memory

Let’s stress that this flat memory model greatly simplifies what is really going on in the
hardware. Briefly, in many contemporary architectures, data buses are either 32 or 64 bits
long. These even multiples of bytes specify what is called a computer word. Although, as
mentioned, a logical address can refer to a single byte, due to the width of the data bus,
memory accesses are related to opera- tions on words. For this reason, the lower address
bits need not be directly set on the bus. Together with the mechanisms of memory paging
and address translation lookahead buffers (TLBs), this makes the physical number of lines
in common architectures usually in the range of 40–52. Nevertheless, such a flat memory
model is a fair trade-off between the variability of hardware architectures and what is
seen from the software perspective.

On the other hand, the much faster cache memory cannot be directly addressed from
a C++ program. There is no need to do this, since caches only store copies of
data from the main memory to allow for faster access. Nevertheless, they can be
efficiently employed in the execution of C++ programs by proper data placement in the

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operational memory. We will address these issues in Chapter 8 when discussing memory
access and concurrent operations of the cores.

Please Note: releasing this material out for you is not the
main important things for not coming to class. Is from the class
we discuss the main problems behind them, even with examples.