inst.eecs.berkeley.

edu/~cs61c
CS61C : Machine Structures
Lecture 31 – RISC-V Control

Instructors
Dan Garcia and Bora Nikolic
2018-11-02
Berkeley’s SkyDeck Offers Chip Design Support
Worth Millions to Startups
Xconomy San Francisco — The current land rush in chip development,
spurred as new technologies such as artificial intelligence create new needs,
is pitting established semiconductor companies like Intel and Nvidia against
tech titans like Facebook that are building their own chips. A wave of next-
generation chip companies has also entered the fray. So how much room
remains for startups that are relative latecomers? Oct 25, 2018.
xconomy.com
CS61C L31 Control Garcia, Nikolić, Fall 2018 © UCB
 Review

• We have designed a complete datapath

•Capable of executing all RISC-V instructions in one cycle
each
•Not all units (hardware) used by all instructions
•5 Phases of execution
•IF, ID, EX, MEM, WB
•Not all instructions are active in all phases
•Controller specifies how to execute instructions
•New instructions can be added with just control?

CS61C L31 Control 2 Garcia, Nikolić, Fall 2018 © UCB

 Recap: Complete RV32I ISA

Not in CS61C

•RV32I has 47 instructions

•37 instructions are enough to run any C program
CS61C L31 Control 3 Garcia, Nikolić, Fall 2018 © UCB
 Complete Single-Cycle RV32I Datapath!

+4
Add
Add
pc+4 2
wb pc
DataD alu
Reg[rs1] 1
alu Inst[11:7]
1 0 wb
PC AddrD 1
addr
addr Inst[19:15]
0 DataR
inst
inst AddrA DataA 0 alu
pc+4
Inst[24:20]
Branch + addr mem
AddrB DataB Comp 0 ALU
clk DataW
IMEM
IMEM Reg [ ] 1 DMEM
Inst
clk Reg[rs2] clk
[31:7] Imm.
Gen Imm[31:0]

PCSel Inst[31:0] ImmSel RegWEn BrUn BrLT Bsel ALUSel MemRW WBSel
Asel
Control logic BrEq

CS61C L31 Control 4 Garcia, Nikolić, Fall 2018 © UCB

 Register Transfer Level (RTL)
•RTL describes instructions in figures or text
•Can use C (or Verilog) to describe RTL

Inst Register Transfers

add R[rd]  R[rs1] + R[rs2]; PC  PC + 4
sub R[rd]  R[rs1] – R[rs2]; PC  PC + 4
ori R[rd]  R[rs1] | Imm; PC  PC + 4
jal R[rd]  PC + 4; PC  R[rs1] + Imm
beq if ( R[rs1] == R[rs2] )
PC  PC + Imm
else PC  PC + 4

CS61C L31 Control 5 Garcia, Nikolić, Fall 2018 © UCB

 Our Single-Core Computer (w/o FPU, SIMD)

Processor Memory
Enable? Input
Read/Write
Control

Cache Program
Datapath Memory (including
Address cache) organized
PC Bytes around blocks,
which are typically
Write multiple words
Registers Data

Arithmetic & Logic Unit Data

ReadD Output
(ALU)
ata

Processor organized
around words and bytes
Processor‐Memory Interface I/O‐Memory Interfaces

CS61C L31 Control 6 Garcia, Nikolić, Fall 2018 © UCB

 Single-Cycle RV32I Datapath and Control

+4
Add
Add
pc+4 2
DataD Reg[rs1] 1
1 Inst[11:7] 0 wb
PC AddrD 1
addr
addr Inst[19:15]
0 DataR
inst
inst AddrA DataA 0 alu
pc+4
Inst[24:20]
Branch + addr mem
AddrB DataB Comp 0 ALU
clk DataW
IMEM
IMEM Reg [ ] 1 DMEM
Inst
clk Reg[rs2] clk
[31:20] Imm.
Gen Imm[31:0]

PCSel Inst[31:0] ImmSel RegWEn BrUn BrLT Bsel ALUSel MemRW WBSel
Asel
Control logic BrEq

CS61C L31 Control 7 Garcia, Nikolić, Fall 2018 © UCB

 Example: add

+4
Add
Add
pc+4 2
wb pc
DataD alu
Reg[rs1] 1
alu Inst[11:7]
1 0 wb
PC AddrD 1
addr
addr Inst[19:15]
0 DataR
inst
inst AddrA DataA 0 alu
pc+4
Inst[24:20]
Branch + addr mem
AddrB DataB Comp 0 ALU
clk DataW
IMEM
IMEM Reg [ ] 1 DMEM
Inst
clk Reg[rs2] clk
[31:7] Imm.
Gen Imm[31:0]

PCSel Inst[31:0] ImmSel RegWEn BrUn BrLT Bsel

=0
ALUSel MemRW WBSel
=pc+4 =* =1 =* =* =Read =1
Asel =add
Control logic BrEq =* =0
31 25 24 20 19 15 14 12 11 7 6 0
funct7 rs2 rs1 funct3 rd opcode
7 5 5 3 5 7
CS61C L31 Control 8 Garcia, Nikolić, Fall 2018 © UCB
 add Execution
+4
Add
Add
wb pc alu 2
alu DataD Reg[rs1] 1
1 Inst[11:7] 0
AddrD 1 wb
0
PC addr
addr Inst[19:15] alu
inst
inst AddrA DataA 0 DataR
pc+4 Inst[24:20] Branch + addr mem
AddrB DataB Comp 0 ALU
clk DataW
IMEM
IMEM Reg [ ] 1 DMEM
Inst
[31:7] clk Reg[rs2] clk
Imm.
Gen Imm[31:0]

PCSel Inst[31:0] ImmSel RegWEn BrUn BrLT Bsel ALUSel MemRW WBSel
=* =* =0 =Read =1
=pc+4 Control logic =* =1 BrEq =* Asel =add
=0

Clock
PC 1000 1004

PC+4 1004 1008

inst[31:0] add x1,x2,x3 add x6,x7,x9

Control logic add control add control
Reg[rs1] Reg[2] Reg[7]

Reg[rs2] Reg[3] Reg[9]

alu Reg[2]+Reg[3] Reg[7]+Reg[9]

wb Reg[2]+Reg[3] Reg[7]+Reg[9]
Reg[1] ??? Reg[2]+Reg[3]
CS61C L31 Control 9 Garcia, Nikolić, Fall 2018 © UCB
 Example: sw

+4
Add
Add
pc+4 2
wb pc
DataD alu
Reg[rs1] 1
alu Inst[11:7]
1 0 wb
PC AddrD 1
addr
addr Inst[19:15]
0 DataR
inst
inst AddrA DataA 0 alu
pc+4
Inst[24:20]
Branch + addr mem
AddrB DataB Comp 0 ALU
clk DataW
IMEM
IMEM Reg [ ] 1 DMEM
Inst
clk Reg[rs2] clk
[31:7] Imm.
Gen Imm[31:0]

PCSel Inst[31:0] ImmSel RegWEn BrUn BrLT Bsel

=1
ALUSel MemRW WBSel
=pc+4 =S =0 =* =* =Write =*
Asel =add
Control logic BrEq =* =0
31 25 24 20 19 15 14 12 11 7 6 0
Imm[11:5] rs2 rs1 funct3 imm[4:0] opcode
offset[11:5] src base width offset[4:0] STORE
CS61C L31 Control 10 Garcia, Nikolić, Fall 2018 © UCB
 Example: beq

+4
Add
Add
pc+4 2
wb pc
DataD alu
Reg[rs1] 1
alu Inst[11:7]
1 0 wb
PC AddrD 1
addr
addr Inst[19:15]
0 DataR
inst
inst AddrA DataA 0 alu
pc+4
Inst[24:20]
Branch + addr mem
AddrB DataB Comp 0 ALU
clk DataW
IMEM
IMEM Reg [ ] 1 DMEM
Inst
clk Reg[rs2] clk
[31:7] Imm.
Gen Imm[31:0]

PCSel Inst[31:0] ImmSel RegWEn BrUn BrLT Bsel ALUSel MemRW WBSel
=1 =Read
=B =0 =0 =* Asel =add =*
Control logic BrEq =1

CS61C L31 Control 11 Garcia, Nikolić, Fall 2018 © UCB

 Peer Instruction(s): Critical Path (citizen try)
+4
Add
Add pc+4
wb pc 2
DataD alu
Reg[rs1] 1
alu 1 Inst[11:7]
AddrD 1 0 wb
PC addr
addr
0 Inst[19:15] alu DataR
inst
inst AddrA DataA Branch 0
Critical pc+4
Inst[24:20] + addr mem
clk
AddrB DataB Comp 0 ALU DataW
path for a addi IMEM
IMEM
Inst
Reg [ ] 1 DMEM
[31:7] Imm. clk Reg[rs2] clk

Gen Imm[31:0]
R[rd] = R[rs1]+imm
PCSel Inst[31:0] ImmSelRegWEn BrUn BrLT Bsel ALUSel MemRW WBSel
BrEq Asel
Control logic

1) tclk-q + tAdd + tIMEM + tReg + tBComp + tALU + tDMEM + tmux + tSetup

2) tclk-q + tIMEM + max{tReg, tImm} + tALU + 2tmux + tSetup
3) tclk-q + tIMEM + max{tReg, tImm} + tALU + 3tmux + tDMEM + tSetup
4) None of the above
CS61C L31 Control 12 Garcia, Nikolić, Fall 2018 © UCB
 Peer Instruction(s): Critical Path (citizen try)
+4
Add
Add tsetup pc+4
wb pc 2
DataD alu
Reg[rs1] 1
alu 1 Inst[11:7]
AddrD 1 0 wb
PC addr
addr
0 Inst[19:15] alu DataR
inst
inst AddrA DataA Branch 0
Critical pc+4
Inst[24:20] + addr mem
clk
AddrB DataB Comp 0 ALU DataW
path for a addi IMEM
IMEM
Inst
Reg [ ] 1 DMEM
[31:7] Imm. clk Reg[rs2] clk

Gen Imm[31:0]
R[rd] = R[rs1]+imm
PCSel Inst[31:0] ImmSelRegWEn BrUn BrLT Bsel ALUSel MemRW WBSel
BrEq Asel
Control logic

1) tclk-q + tAdd + tIMEM + tReg + tBComp + tALU + tDMEM + tmux + tSetup

2) tclk-q + tIMEM + max{tReg, tImm} + tALU + 2tmux + tSetup
3) tclk-q + tIMEM + max{tReg, tImm} + tALU + 3tmux + tDMEM + tSetup
4) None of the above
CS61C L31 Control 13 Garcia, Nikolić, Fall 2018 © UCB
 Instruction Timing

IF ID EX MEM WB Total
I-MEM Reg ALU D-MEM Reg W
Read
200 ps 100 ps 200 ps 200 ps 100 ps 800 ps
CS61C L31 Control 14 Garcia, Nikolić, Fall 2018 © UCB
 Instruction Timing

Instr IF = 200ps ID = 100ps ALU = 200ps MEM=200ps WB = 100ps Total

add X X X X 600ps
beq X X X 500ps
jal X X X 500ps
lw X X X X X 800ps
sw X X X X 700ps

•Maximum clock frequency

•fmax = 1/800ps = 1.25 GHz
•Most blocks idle most of the time
•E.g. fmax,ALU = 1/200ps = 5 GHz!

CS61C L31 Control 15 Garcia, Nikolić, Fall 2018 © UCB

 Control Logic Truth Table
Inst[31:0] BrEq BrLT PCSel ImmSel BrUn ASel BSel ALUSel MemRW RegWEn WBSel
add * * +4 * * Reg Reg Add Read 1 ALU
sub * * +4 * * Reg Reg Sub Read 1 ALU
(R-R * * +4 * * Reg Reg (Op) Read 1 ALU
Op)
addi * * +4 I * Reg Imm Add Read 1 ALU
lw * * +4 I * Reg Imm Add Read 1 Mem
sw * * +4 S * Reg Imm Add Write 0 *
beq 0 * +4 B * PC Imm Add Read 0 *
beq 1 * ALU B * PC Imm Add Read 0 *
bne 0 * ALU B * PC Imm Add Read 0 *
bne 1 * +4 B * PC Imm Add Read 0 *
blt * 1 ALU B 0 PC Imm Add Read 0 *
CS 61c Lecture 12: Control & Performance
bltu * 1 ALU B 1 PC Imm Add Read 0 *
jalr * * ALU I * Reg Imm Add Read 1 PC+4
jal * * ALU J * PC Imm Add Read 1 PC+4
auipc * * +4 U * PC Imm Add Read 1 ALU
CS61C L31 Control 16 Garcia, Nikolić, Fall 2018 © UCB
 Control Realization Options

•ROM
•“Read-Only Memory”
•Regular structure
•Can be easily reprogrammed
 fix errors
 add instructions
•Popular when designing control logic manually
•Combinatorial Logic
•Today, chip designers use logic synthesis tools
to convert truth tables to networks of gates

CS61C L31 Control 17 Garcia, Nikolić, Fall 2018 © UCB

 RV32I, a nine-bit ISA!

inst[30] inst[14:12] inst[6:2]

Not in CS61C

Instruction type encoded using only 9 bits

inst[30],inst[14:12], inst[6:2]
CS61C L31 Control 18 Garcia, Nikolić, Fall 2018 © UCB
 Combinational Logic Control

•Simplest example: BrUn

inst[14:12] inst[6:2] = Branch

•How to decode whether BrUn is 1?

•BrUn = Inst[14]  Inst [13]  Branch

CS61C L31 Control 19 Garcia, Nikolić, Fall 2018 © UCB

 ROM-based Control

11‐bit address (inputs)

Inst[30,14:12,6:2] BrEq BrLT
9
PCSel
3 ImmSel[2:0]
BrUn
ASel
ROM 4
BSel
ALUSel[3:0]
MemRW
RegWEn
2 WBSel[1:0]

15 data bits (outputs)

CS61C L31 Control 20 Garcia, Nikolić, Fall 2018 © UCB
 ROM Controller Implementation
AND OR
add
Control Word for add
sub
Control Word for sub
or
Control Word for or

Decoder
.

Address
Inst[] 11 . .
BrEQ . .

BrLT .

jal

Controller output (PCSel, ImmSel, …)

CS61C L31 Control 21 Garcia, Nikolić, Fall 2018 © UCB
 Decode add
inst[30] inst[14:12] inst[6:2]
add =

CS61C L31 Control 22 Garcia, Nikolić, Fall 2018 © UCB

 Administrivia

CS61C L31 Control 23 Garcia, Nikolić, Fall 2018 © UCB

 Call home, we’ve made HW/SW contact!
temp = v[k];
High Level Language
Program (e.g., C) v[k] = v[k+1];
v[k+1] = temp;
Compiler
Assembly Language lw $t0, 0($2)
Program (e.g.,RISC-V) lw $t1, 4($2)
sw $t1, 0($2)
Assembler sw $t0, 4($2)
Machine Language 0000 1001 1100 0110 1010 1111 0101 1000
1010 1111 0101 1000 0000 1001 1100 0110
Program (RISC-V) 1100 0110 1010 1111 0101 1000 0000 1001
0101 1000 0000 1001 1100 0110 1010 1111

Machine
Interpretation
Hardware Architecture Description
(e.g., block diagrams)
Architecture
Implementation

Logic Circuit Description

(Circuit Schematic Diagrams)

CS61C L31 Control 24 Garcia, Nikolić, Fall 2018 © UCB

 “And In conclusion…”

• We have built a processor!

•Capable of executing all RISC-V instructions in one cycle
each
•Not all units (hardware) used by all instructions
•Critical path changes
•5 Phases of execution
•IF, ID, EX, MEM, WB
•Not all instructions are active in all phases
•Controller specifies how to execute instructions
•Implemented as ROM or logic
CS61C L31 Control 25 Garcia, Nikolić, Fall 2018 © UCB