Scribd
Upload
179 views4 pages

Exp 10 SISO and SIPO

The document describes an experiment to implement a 4-bit right shift register using D flip-flops in Logisim simulator. It discusses serial in serial out (SISO) shift registers where data is loaded and retrieved serially. For a rising edge clock pulse, the data moves one bit to the right within the register. It also describes a similar left shift register and a serial-in parallel-out register where serial input produces a parallel output.

Uploaded by

Aditya Gupta
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
Available Formats
Download as PDF, TXT or read online on Scribd
179 views4 pages

Exp 10 SISO and SIPO

The document describes an experiment to implement a 4-bit right shift register using D flip-flops in Logisim simulator. It discusses serial in serial out (SISO) shift registers where data is loaded and retrieved serially. For a rising edge clock pulse, the data moves one bit to the right within the register. It also describes a similar left shift register and a serial-in parallel-out register where serial input produces a parallel output.

Uploaded by

Aditya Gupta
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
Available Formats
Download as PDF, TXT or read online on Scribd
You are on page 1/ 4

Experiment 10

Objective - Implementation of a 4-bit Right Shift Registers (SISO & SIPO) Using D Flip Flop Using
Logisim Simulator.

Theory: Serial In Serial Out (SISO) shift registers are a kind of shift registers where both data loading
as well as data retrieval to/from the shift register occurs in serial-mode. Figure 1 shows a n-bit
synchronous SISO shift register sensitive to positive edge of the clock pulse. Here the data word which
is to be stored is fed bit-by-bit at the input of the first flip-flop. Further it is seen that the inputs of all
other flip-flops (except the first flip-flop FF1) are driven by the outputs of the preceding ones say for
example, the input of FF2 is driven by the output of FF1. At last, the data stored within the register is
obtained at the output pin of the nth flip-flop in serial-fashion.
Initially all the flip-flops in the register are cleared by applying high on their clear pins. Next the input
data word is fed serially to FF1. This causes the bit appearing at the D1 pin (B1) to be stored into FF1
as soon as the first leading edge of the clock appears. Further at the second clock tick, B1 gets stored
into FF2 while a new bit enters into FF1 (B2).

This kind of shift in data bits continues for every rising edge of the clock pulse. This indicates that for
every single clock pulse the data within the register moves towards right by a single bit. Thus, the
design shown in Figure 1 is regarded as a right-shift SISO shift register. Following the data transmission
as explained, one can note that the first bit of an input word appears at the output of nth flip-flop for
the nth clock tick. On applying further clock cycles, one gets the next successive bits of the input data
word as the serial output (Table I). The waveforms pertaining to the same are shown by Figure 2.
Similar to the right-shift SISO shift-register shown, there can exist a left-shift SISO shift-register also
(Figure 3). However, the working principle remains the same except the fact that the data movement
will be from right to left.
The shift register, which allows serial input (one bit after the other through a single data line)
and produces a parallel output is known as Serial-In Parallel-Out shift register.

The logic circuit given below shows a serial-in-parallel-out shift register. The circuit consists
of four D flip-flops which are connected. The clear (CLR) signal is connected in addition to
the clock signal to all the 4 flip flops in order to RESET them. The output of the first flip flop
is connected to the input of the next flip flop and so on. All these flip-flops are synchronous
with each other since the same clock signal is applied to each flip flop.

You might also like