Unit 1

Microprocessor Architecture
Basic Concepts of Microprocessors
• Microcomputer: a computer with a microprocessor as its
CPU. Includes memory, I/O etc.

• Microprocessor: silicon chip which includes ALU, register

circuits & control circuits

• Microcontroller: silicon chip which includes microprocessor,

memory & I/O in a single package
What is a Microprocessor?
• The word comes from the combination micro and processor.
• Processor means a device that processes whatever.
• In this context processor means a device that processes
numbers, specifically binary numbers, 0’s and 1’s.
• To process means to manipulate.
• It is a general term that describes all manipulation.
• Again in this content, it means to perform certain
operations on the numbers that depend on the
microprocessor’s design.
What about micro?
• Micro is a new addition.
• In the late 1960’s, processors were built using discrete elements.
• These devices performed the required operation, but were too large
and too slow.
• In the early 1970’s the microchip was invented.
• All of the components that made up the processor were now placed
on a single piece of silicon.
• The size became several thousand times smaller and the speed
became several hundred times faster.
• The Micro-Processor was born.
Was there ever a mini-processor?
• No.
• It went directly from discrete elements to a single chip.
• However, comparing today’s microprocessors to the
ones built in the early 1970’s you find an extreme
increase in the amount of integration.

• So, What is a microprocessor?

Definition of the Microprocessor
• The microprocessor is a programmable device that
• takes in numbers,
• performs on them arithmetic or logical operations
according to the program stored in memory and
• then produces other numbers as a result.
Definition …
• Programmable device: The microprocessor can perform
different sets of operations on the data it receives depending on
the sequence of instructions supplied in the given program.
• By changing the program, the microprocessor manipulates the
data in different ways.

• Instructions: Each microprocessor is designed to execute a

specific group of operations. This group of operations is called
an instruction set. This instruction set defines what the
microprocessor can and cannot do.
Definition …
• Takes in: The data that the microprocessor manipulates must
come from somewhere.
• It comes from what is called input devices.
• These are devices that bring data into the system from the
outside world.
• These represent devices such as a keyboard, a mouse, switches,
and the like.
Definition …
• Numbers: The microprocessor has a very narrow view on life. It only
understands binary numbers.

• A binary digit is called a bit (which comes from binary digit).

• The microprocessor recognizes and processes a group of bits together.

This group of bits is called a word.

• The number of bits in a Microprocessor’s word, is a measure of its

abilities.
Definition …
• Words, Bytes, etc.
• The earliest microprocessor (the Intel 8088 and Motorola’s 6800) recognized
8-bit words.
• They processed information 8-bits at a time. That’s why they are called 8-bit
processors. They can handle large numbers, but in order to process these
numbers, they broke them into 8-bit pieces and processed each group of 8-bits
separately.
• Later microprocessors (8086 and 68000) were designed with 16-bit words.
• A group of 8-bits were referred to as a half-word or byte.
• A group of 4 bits is called a nibble.
• Also, 32 bit groups were given the name long word.
• Today, all processors manipulate at least 32 bits at a time and there exists
microprocessors that can process 64, 80, 128 bits
Definition …
• Arithmetic and Logic Operations:
• Every microprocessor has arithmetic operations such as add and
subtract as part of its instruction set.
• Most microprocessors will have operations such as multiply and
divide.
• Some of the newer ones will have complex operations such as square
root.
• In addition, microprocessors have logic operations as well. Such as
AND, OR, XOR, shift left, shift right, etc.
• Again, the number and types of operations define the
microprocessor’s instruction set and depends on the specific
microprocessor.
Definition …
• Stored in memory :
• First, what is memory?
• Memory is the location where information is kept while not in current
use.
• Memory is a collection of storage devices. Usually, each storage device
holds one bit. Also, in most kinds of memory, these storage devices are
grouped into groups of 8. These 8 storage locations can only be accessed
together. So, one can only read or write in terms of bytes to and form
memory.
• Memory is usually measured by the number of bytes it can hold.
• It is measured in Kilos, Megas and lately Gigas. A Kilo in computer
language is 210 =1024. So, a KB (KiloByte) is 1024 bytes. Mega is
1024 Kilos and Giga is 1024 Mega.
Definition …
• Stored in memory:
• When a program is entered into a computer, it is stored in memory. Then
as the microprocessor starts to execute the instructions, it brings the
instructions from memory one at a time.

• Memory is also used to hold the data.

• The microprocessor reads (brings in) the data from memory when it
needs it and writes (stores) the results into memory when it is done.
Definition …
• Produces: For the user to see the result of the execution of the program,
the results must be presented in a human readable form.
• The results must be presented on an output device.

• This can be the monitor, a paper from the printer, a simple LED or many
other forms.
Functional blocks of computer
Computer is a system which process information.
1. Input unit: Responsible for inputting
information (code / data) eg. Keyboard,
Memory Unit
stylus etc.

2. ALU: Responsible to perform Arithmetic

and Logical operations
Input Output
Control Unit
Unit Unit 3. Control Unit: Responsible to generate
various control signals such as Read,
Write etc.
Arithmetic
Logic Unit 4. Memory: Stores code/data.
Read Only Memory - ROM
Read/write Memory - RAM

5. Output unit: Responsible for outputting

information (modified data) eg. Monitor,
Printer etc.
Definition
• A microprocessor is a
computer processor that
incorporates the functions of
a central processing unit on a
single integrated circuit of
MOSFET construction.

• It is abbreviated as μp
Features of 8085 μp
• It is a 8 bit microprocessor.
• Six 8-bit general purpose register arranged in pairs: BC, DE, HL.
• A 16 bit program counter (PC), A 16 bit stack pointer (SP)
• Data bus is a group of 8 lines AD0 – AD7.
• It has 16-bit address buses A0-A15. The first 8 lines of address bus and 8
lines of data bus are multiplexed AD0 – AD7.
• 8085 μp can address up to 64 KB (216= 65536 bytes) memory.
• It is enclosed with 40 pins DIP (Dual in line package).
• It requires a signal +5V power supply and operates at 3 MHZ single
phase clock.
Bus architecture of 8085 μp
System Bus
• System bus is a collection of wires carrying information within a
computer system.

• Three types of system buses:

• Address Bus
• Data Bus
• Control Bus
Address Bus
• Address bus are wires that carry CPU-generated address signals out to
memory and to I/O devices.
• Unidirectional – Travel outwards only
• Size of memory space depends on the number of address lines
• To calculate, memory space = 2n (n = no of address lines)
Address Bus
• Examples:
No of address lines Size of Mem. ( In Bytes)
8 28 = 256
16 216 = 65 536 = 64 K
20 220 = 1 048 576 = 1 M
32 232 = 4 294 967 296 = 4 G
Data Bus
• Data signals that travel out of and into the microprocessor
• Bi-directional
• The number of wires in the data bus depends on the word size that the
microprocessor operates with (no of bit of the computer)

• Example:
a) 8-bit μP will have a data bus of 8 wires
b) 32-bit μP will have a data bus with 32 wires
Control Bus
• Control bus consists of wires, carrying signals from CPU to external
devices or from external devices to CPU.
• The number of wires present in the control bus varies from one μP to
another.
• Examples are Memory read , Memory write, I/O read, I/O write.
The 8085 Programming Model
 Registers
• The 8085 has six general-purpose registers to store
8-bit data;
• B,C,D,E,H, and L
• They can be combined as register pairs –
• BC, DE, and HL – to perform some 16-bit operations.

Reg B D7 D6 D5 D4 D3 D2 D1 D0 Reg C D7 D6 D5 D4 D3 D2 D1 D0

Reg D D7 D6 D5 D4 D3 D2 D1 D0 Reg E D7 D6 D5 D4 D3 D2 D1 D0

Reg H D7 D6 D5 D4 D3 D2 D1 D0 Reg L D7 D6 D5 D4 D3 D2 D1 D0
Accumulator
The accumulator is an 8-bit register that is a part of arithmetic/logic unit
(ALU).

This register is used to store 8-bit data and to perform arithmetic and
logical operations.

The result of an operation is stored in the accumulator.

The accumulator is also known as register A.

Reg A D7 D6 D5 D4 D3 D2 D1 D0
Flags
The ALU includes five flip-flops, which are set or reset after an operation according
to data conditions of the result in the accumulator and other registers.
Zero(Z),
Carry (CY),
Sign (S),
Parity (P),
Auxiliary Carry (AC)
The microprocessor uses these flags to test data conditions.
Flags
CY→ Carry flag-
• If an operation perform in ALU generates a carry from D7 to next stage,
the CY flag is set.
• It works as 9th bit for addition and borrow flag for subtraction if there is
no carry borrow out of MSB bit that is D7 of result CY flag is reset.
1
1 0 0 0 1 0 0 1
+ 1 0 0 0 0 0 0 1
1 0 0 0 0 1 0 1 0
CY= 1
Flags
P → Parity flag-
• This bit is used to indicate the parity of result.
• If the result contain even number of 1’s this flag is set.
• If the result contains odd number of 1’s this flag is reset that is by
insertion of flag bit microprocessor maintains odd parity for result.
D7 D6 D5 D4 D3 D2 D1 D0
Result= 0 0 0 1 0 0 1 0
P= 1
D7 D6 D5 D4 D3 D2 D1 D0
Result= 1 0 0 1 0 0 1 0
P= 0
Flags
AC→ Auxiliary carry flag-
If an operation performed in ALU generates a carry from lower nibble
that is D0 to D3 to upper nibble that is D4 to D7 the AC flag is set that is a
carry given by D3 bit to D4 is a AC flag. This is not a general flag; it is
used internally by microprocessor to perform binary to BCD conversion.
1 1
1 0 0 0 1 0 0 1
+ 0 1 0 0 1 0 0 1
1 1 0 1 0 0 1 0
AC = 1
Flags
Z → Zero flag-
If an operation results in Zero as a result the zero flag is set. If the result
is not zero the zero flag is reset.
D7 D6 D5 D4 D3 D2 D1 D0
Result= 0 0 0 1 0 0 1 0
Z= 0
D7 D6 D5 D4 D3 D2 D1 D0
Result= 0 0 0 0 0 0 0 0
Z= 1
Flags
S → Sign flag-
• In sign magnitude format the sign of a number is indicated by MSB bit.
• If MSB bit = 0 the number is positive and if MSB bit = 1 the number is
negative.
• In 8085 MSB bit is D7 bit.
• The sign flag is exact replica of D7 bit of result. If D7 = 1 the flag is set &
if D7 = 0 the flag is reset.
Flags
S → Sign flag-

D7 D6 D5 D4 D3 D2 D1 D0
Result= 0 0 0 1 0 0 1 0
S= 0

D7 D6 D5 D4 D3 D2 D1 D0
Result= 1 0 0 0 1 0 0 0
S= 1
Example: 1
1 1 1
1 0 0 0 1 0 1 1
+ 1 1 0 0 1 0 0 1
1 0 1 0 1 0 1 0 0
CY = 1
P=0
AC = 1
Z=0
S=0
Example: 2
0 1 1 0 0 0 1 1
- 1 0 0 0 1 0 0 0
1 1

1 1 1 0 1 1 0 1 1
CY = 1
P=1
AC = 1
Z=0
S=1
Program Counter (PC)
• This 16-bit register deals with sequencing the execution of instructions.
This register is a memory pointer.
• Memory locations have 16-bit addresses, and that is why this is a 16-bit
register.
• Initial Value of PC = 0000H

PCH PCL

D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0

Stack Pointer (SP)
• The stack pointer is also a 16-bit register used as a memory pointer.
• It points to a memory location in R/W memory, called the stack.
• The beginning of the stack is defined by loading 16-bit address in the
stack pointer. SP SP
H L

D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0

Internal architecture of 8085 μp

RST 6.5

RST 7.5
RST 5.5
INTA’

TRAP
SID

INTR
SOD

Interrupt Controller Serial Controller

8-bit internal data bus

Instruction
ACC Reg (8) Temp Reg (8) Flag Reg (8) B Reg (8) C Reg (8)
Register
D Reg (8) E Reg (8)
H Reg (8) L Reg (8)
Instruction
Stack Pointer (16)
Decoder
and Program Counter (16)
ALU
Machine Increment / Decrement
Cycle Address Latch (16)
Encoder
X1 X2 +5V GND

Timing and Control Unit Address Address /

Control Status DMA Reset Buffer Data Buffer

CLK READY WR’ RD’ ALE S0 S1 IO/M’ HOLD HLDA RESETIN’ RESETOUT A8-A15 AD0-AD7
OUT
The ALU
• In addition to the arithmetic & logic circuits, the ALU includes
the accumulator, which is part of every arithmetic & logic
operation.

• Also, the ALU includes a temporary register used for holding

data temporarily during the execution of the operation. This
temporary register is not accessible by the programmer.
Internal architecture of 8085 μp
• Instruction register (IR)– holds the currently executing instruction.

• Instruction Decoder (ID)- decodes the instruction. Once decoded,

the instruction controls the remainder of the MPU, memory and IO
through the timing and control block.

• Temporary register- holds information from the memory or register

array. An input of the ALU.

• Increment/Decrement address latch – It adds or subtracts one from

any of other registers in register array.
Control and Status Signals.
Memory in 8085
• Memory stores information such as instructions and data in binary
format (0 and 1).
• It provides this information to the microprocessor whenever it is needed
• Usually, there is a memory sub-system in a microprocessor-based
system.
• This sub-system includes:
– The registers inside the microprocessor
– Read Only Memory (ROM)
• used to store information that does not change.
– Random Access Memory (RAM) (also known as Read/Write
Memory).
• used to store information supplied by the user.
• Such as programs and data.
Memory in 8085
D7 D6 D5 D4 D3 D2 D1 D0 0 0 0 0 (H)
0 0 0 1 (H)
0 0 0 2 (H)
0 0 0 3 (H)
0 0 0 4 (H)

F F F B (H)
F F F C (H)
F F F D (H)
F F F E (H)
F F F F (H)
Memory and Address
• The memory map is a picture representation of the address range and
shows where the different memory chips are located within the address
range.
0000
EPROM Address Range of EPROM Chip
3FFF
4400
RAM 1 Address Range of 1st RAM Chip
5FFF
6000
Address Range

RAM 2 Address Range of 2nd RAM Chip

8FFF
9000
RAM 3 Address Range of 3rd RAM Chip
A3FF
A400

RAM 4 Address Range of 4th RAM Chip

F7FF
FFFF
Memory and Address
• To execute a program the user enters its instructions in binary
format into the memory.

• The microprocessor then reads these instructions and whatever

data is needed from memory, executes the instructions and
places the results either in memory or produces it on an output
device.
MPU Communication and Bus Timing
MPU Communication and Bus Timing
Important terms related to timing diagrams
• T-state: Each clock cycle is called as T-states.

• Machine cycle: It is the time required by the microprocessor to complete

the operation of accessing the memory devices or I/O devices. In
machine cycle various operations like opcode fetch, memory read,
memory write, I/O read, I/O write are performed.

• Instruction cycle: this term is defined as the number of steps required by

the CPU to complete the entire process ie. Fetching and execution of one
instruction. The fetch and execute cycles are carried out in
synchronization with the clock.
Rules to identify number of machine cycles
in an instruction
• If an addressing mode is direct, immediate or implicit then
No. of machine cycles = No. of bytes.

• If the addressing mode is indirect then

No. of machine cycles = No. of bytes + 1.
Add +1 to the No. of machine cycles if it is memory read/write
operation.

• If the operand is 8-bit or 16-bit address then,

No. of machine cycles = No. of bytes +1.

• These rules are applicable to 80% of the instructions of 8085.

Timing Diagram

Instruction cycle = Fetch Cycle(FC) + Execute cycle(EC).

Opcode Fetch
Opcode Fetch …
• During T1 state, microprocessor uses IO/M(bar), S0, S1 signals are used
to instruct microprocessor to fetch opcode.
• Thus when IO/M(bar)=0, S0=S1= 1, it indicates opcode fetch operation.
• During this operation 8085 transmits 16-bit address and also uses ALE
signal for address latching.
• At T2 state microprocessor uses read signal and make data ready from
that memory location to read opcode from memory and at the same time
program counter increments by 1 and points next instruction to be
fetched.
• At T3, microprocessor reads opcode and store it into instruction register
to decode it further.
Opcode Fetch …
• During T4 microprocessor performs internal operation like decoding
opcode and providing necessary actions.
• The opcode is decoded to know whether T5 or T6 states are required, if
they are not required then µp performs next operation.
Memory Read
Memory Read …
• It is used to fetch one byte from the memory.
• It requires 3 T-States.
• It can be used to fetch operand or data from the memory.
• During T1, A8-A15 contains higher byte of address. At the same time
ALE is high. Therefore Lower byte of address A0-A7 is selected from
AD0-AD7.
• Since it is memory ready operation, IO/M(bar) goes low.
• During T2 ALE goes low, RD(bar) goes low. Address is removed from
AD0-AD7 and data D0-D7 appears on AD0-AD7.
• During T3, Data remains on AD0-AD7 till RD(bar) is at low signal.
Memory Write
Memory Write …
• It is used to send one byte into memory.
• It requires 3 T-States.
• During T1, ALE is high and contains lower address A0-A7 from AD0-
AD7.
• A8-A15 contains higher byte of address.
• As it is memory operation, IO/M(bar) goes low.
• During T2, ALE goes low, WR(bar) goes low and Address is removed
from AD0-AD7 and then data appears on AD0-AD7.
• Data remains on AD0-AD7 till WR(bar) is low.
IO Read
IO Read …
• It is used to fetch one byte from an IO port.
• It requires 3 T-States.
• During T1, The Lower Byte of IO address is duplicated into higher order
address bus A8-A15.
• ALE is high and AD0-AD7 contains address of IO device.
• IO/M (bar) goes high as it is an IO operation.
• During T2, ALE goes low, RD (bar) goes low and data appears on AD0-
AD7 as input from IO device.
• During T3 Data remains on AD0-AD7 till RD(bar) is low
IO Write
IO Write …
• It is used to writ one byte into IO device.
• It requires 3 T-States.
• During T1, the lower byte of address is duplicated into higher order
address bus A8-A15.
• ALE is high and A0-A7 address is selected from AD0-AD7.
• As it is an IO operation IO/M (bar) goes low.
• During T2, ALE goes low, WR (bar) goes low and data appears on AD0-
AD7 to write data into IO device.
• During T3, Data remains on AD0-AD7 till WR(bar) is low.
Pin Configuration of 8085
• 40 pins that can be divided into six groups
• Higher Order Address Bus
• Multiplexed Address / Data Bus
• Status & Control Signals
• Externally Started (Initiated) and Interrupt Signals
• Serial Input / Output Port Signal
• Power Supply & Clock Frequency.
Pin Configuration of 8085
Higher Order Address Bus
The address bus pins are ranges from
A15-A8 (28-21) and it carries the most
significant 8-bits of Memory or I/O
address.
Pin Configuration of 8085 …
Multiplexed Address / Data Bus
The multiplexed address / data bus pins
are ranges from AD7-AD0 (19-12) and it
carries the least significant 8-bit address
and 8-bit data.

Separated by ALE
ALE is High : AD7-AD0 Add Bus
ALE is Low : AD7-AD0 Data Bus
Pin Configuration of 8085 …
Status & Control Signals
ALE (30):
• It is an Address Latch Enable signal.
Used for demultiplexing of address
and data lines.
• It is a positive going pulse generated
when a new operation is started by the
microprocessor (during first T-State).
• When the pulse goes high, it indicates
address.
• When the pulse goes down it
indicates data.
Pin Configuration of 8085 …
Status & Control Signals
S0 (29), S1 (33):
• These are status signals.
• These signals are used to identify the
type of current operation.
• They distinguish the various types of
operations such as halt, reading,
instruction fetching or writing.
Pin Configuration of 8085 …
Status & Control Signals
IO/𝐌ഥ (34)
• This signal is used to differentiate
between IO and Memory operations.
• When it is high indicates IO operation
• When it is low then it indicates
memory operation.
Pin Configuration of 8085 …
ഥ
IO/𝐌 S1 S0 Operation
0 1 1 Opcode fetch
0 1 0 Memory read
0 0 1 Memory write
1 1 0 I/O read
1 0 1 I/O write
1 1 1 Interrupt acknowledge
0 0 0 Halt
Pin Configuration of 8085 …
Status & Control Signals
𝐑𝐃 (32)
• It is a signal to control READ
operation.
• When it is low the selected memory
or input-output device is read.
Pin Configuration of 8085 …
Status & Control Signals
𝐖𝐑 (31)
• It is a signal to control WRITE
operation.
• When it goes low the data on the data
bus is written into the selected
memory or I/O location.
Pin Configuration of 8085 …
Status & Control Signals
READY (35)
• It senses whether a peripheral is ready
to transfer data or not.
• If READY is high(1) the peripheral is
ready.
• If it is low(0) the microprocessor
waits till it goes high.
• It is useful for interfacing low speed
devices.
Pin Configuration of 8085 …
Externally Started (Initiated) and
Interrupt Signals
𝐑𝐄𝐒𝐄𝐓 𝐈𝐍 (36)
• When the signal on this pin is low(0),
the program-counter is set to zero, the
buses are tristated and the
microprocessor unit is reset.
Pin Configuration of 8085 …
Externally Started (Initiated) and
Interrupt Signals
RESET OUT (3)
• This signal indicates that the MPU is
being reset.
• The signal can be used to reset other
devices.
Pin Configuration of 8085 …
Externally Started (Initiated) and
Interrupt Signals
HOLD (39)
• It indicates that another device is
requesting the use of the address and
data bus.
• Having received HOLD request the
microprocessor relinquishes the use of
the buses as soon as the current machine
cycle is completed.
• Internal processing may continue.
• After the removal of the HOLD signal
the processor regains the bus.
Pin Configuration of 8085 …
Externally Started (Initiated) and
Interrupt Signals
HLDA (38)
• It is a signal which indicates that the
hold request has been received after
the removal of a HOLD request, the
HLDA goes low.
Pin Configuration of 8085 …
Externally Started (Initiated) and
Interrupt Signals
HOLD(39) and HLDA (38)
Pin Configuration of 8085 …
Externally Started (Initiated) and
Interrupt Signals
• The 8085 has five interrupt signals
that can be used to interrupt a
program execution.
1. TRAP
2. RST 7.5
3. RST 6.5
4. RST 5.5
5. INTR
• The microprocessor acknowledges
Interrupt Request by INTA signal.
Pin Configuration of 8085 …
Externally Started (Initiated) and
Interrupt Signals
TRAP (6)
• It is a non-maskable interrupt, having
the highest priority among all
interrupts.
• By default, it is enabled until it gets
acknowledged. In case of failure, it
executes as ISR and sends the data to
backup memory.
• This interrupt transfers the control to
the location 0024H.
Pin Configuration of 8085 …
Externally Started (Initiated) and
Interrupt Signals
RST 7.5 (7)
• It is a maskable interrupt, having the
second highest priority among all
interrupts.
• When this interrupt is executed, the
processor saves the content of the PC
register into the stack and branches to
003CH address.
Pin Configuration of 8085 …
Externally Started (Initiated) and
Interrupt Signals
RST 6.5 (8)
• It is a maskable interrupt, having the
third highest priority among all
interrupts.
• When this interrupt is executed, the
processor saves the content of the PC
register into the stack and branches to
0034H address.
Pin Configuration of 8085 …
Externally Started (Initiated) and
Interrupt Signals
RST 5.5 (9)
• It is a maskable interrupt.
• When this interrupt is executed, the
processor saves the content of the PC
register into the stack and branches to
002CH address.
Pin Configuration of 8085 …
Externally Started (Initiated) and
Interrupt Signals
INTR (10)
• It is a maskable interrupt, having the
lowest priority among all interrupts.
• It can be disabled by resetting the
microprocessor.
• When INTR signal goes high, the
following events can occur
1. The microprocessor checks the
status of INTR signal during the
execution of each instruction.
Pin Configuration of 8085 …
Externally Started (Initiated) and
Interrupt Signals
INTR (10)
2. When the INTR signal is high, then
the microprocessor completes its
current instruction and sends active
low interrupt acknowledge signal.

3. When instructions are received, then

the microprocessor saves the address
of the next instruction on stack and
executes the received instruction.
Pin Configuration of 8085 …
Externally Started (Initiated) and
Interrupt Signals
𝐈𝐍𝐓𝐀 (11)
• It is an interrupt acknowledgment sent
by the microprocessor after INTR is
received.
• When the 8085 microprocessor gets an
interrupt signal, then it should be
recognized.
• This will be done by INTA.
• As a result, when the interrupt will be
obtained then INTA will go high.
Pin Configuration of 8085 …
Serial Input / Output Port Signal.
SOD (4)
• Serial Output Data, is a data line for
serial output.
• The output SOD is set / reset as
specified by the SIM instruction.
Pin Configuration of 8085 …
Serial Input / Output Port Signal.
SID (5)
• Serial Input Data, is a data line for
serial input.
• The data on this line is loaded into
accumulator whenever a RIM
instruction is executed.
Pin Configuration of 8085 …
Power Supply & Clock Frequency.
VCC (40)
• VCC is +5 V pin

VSS (20)
• VSS is a ground pin
Pin Configuration of 8085 …
Power Supply & Clock Frequency.
X1 (1) and X2 (2)
• X1, X2 terminals that are associated
with the exterior oscillator for
generating the required as well as
appropriate operation of a clock.
Pin Configuration of 8085 …
Power Supply & Clock Frequency.
X1 (1) and X2 (2)
Pin Configuration of 8085 …
Power Supply & Clock Frequency.
X1 (1) and X2 (2)
Pin Configuration of 8085 …
Power Supply & Clock Frequency.
CLK OUT (37)
• Sometimes it is compulsory to
generate output clock signal from
8085 microprocessors so that it can be
used in favor of other peripherals or
else other digital integrated circuits.
• This is offered with CLK OUT pin.
Its frequency is continually similar
because the frequency at which the
microprocessor works.
Pin Configuration of 8085 …
Generation of Control Signals

ഥ
IO/𝐌
𝐌𝐄𝐌𝐑
𝐑𝐃

8085 𝐌𝐄𝐌𝐖
𝐖𝐑

𝐈𝐎𝐑

𝐈𝐎𝐖
Demultiplexing of AD7-AD0

A15 - A8 A15 - A8

ALE
8085
AD7 – AD0 Latch A7 – A0

D7 – D0
Demultiplexing of AD7-AD0
Generation of Control Signals and
Demultiplexing of AD7-AD0
The 8085 organization an example
• Putting all of the concepts together, we get:
Chip Selection
A15- A10 Circuit

8085
A15-A8 CS

ALE
A9-A0 1K Byte
AD7-AD0 Latch Memory
A7- A0
Chip

WR RD IO/M D7- D0

RD WR
The three cycle instruction execution model
• To execute a program,
• the microprocessor Reads each instruction from memory,
• Interprets it, then
• Executes it.
• To use the right names for the cycles:
• The microprocessor fetches each instruction,
• Decodes it, then
• Executes it.
• This sequence is continued until all instructions are performed.
Machine Language
• The number of bits that form the word of a microprocessor is fixed for
that particular processor.
• These bits define a maximum number of combinations.
• For example an 8-bit microprocessor can have at most 28 = 256
different combinations.
• However, in most microprocessors, not all of these combinations are
used.
• Certain patterns are chosen and assigned specific meanings.
• Each of these patterns forms an instruction for the microprocessor.
• The complete set of patterns makes up the microprocessor’s machine
language.
The 8085 Machine Language
• The 8085 (from Intel) is an 8-bit microprocessor.
• The 8085 uses a total of 246 bit patterns to form its instruction set.
• These 246 patterns represent only 74 instructions.
• The reason for the difference is that some (actually most) instructions
have multiple different formats.

• Because it is very difficult to enter the bit patterns correctly, they are
usually entered in hexadecimal instead of binary.
• For example, the combination 0011 1100 which translates into
increment the number in the register called the accumulator, is
usually entered as 3C.
Assembly Language
• Entering the instructions using hexadecimal is quite easier than entering
the binary combinations.

• However, it still is difficult to understand what a program written in

hexadecimal does.

• So, each company defines a symbolic code for the instructions.

• These codes are called mnemonics.

• The mnemonic for each instruction is usually a group of letters that

suggest the operation performed.
Assembly Language
• Example 1:
• 0011 1100 translates to 3C H (OPCODE)
• Its mnemonic is: INR A.
• INR stands for “increment register” and A is short for accumulator.

• Example 2:
• 1000 0000, translates to 80 H
• Its mnemonic is ADD B.
• Add register B to the accumulator and keep the result in the
accumulator.
Assembly Language
• It is important to remember that a machine language and its
associated assembly language are completely machine
dependent.
• In other words, they are not transferable from one
microprocessor to a different one.
• For example, Motorola has an 8-bit microprocessor called the
6800.
• The 8085 machine language is very different from that of the
6800; so is the assembly language.
• A program written for the 8085 cannot be executed on the 6800
and vice versa.
Assembling The Program
• How does assembly language get translated into machine
language?
• There are two ways:
• Hand assembly: The programmer translates each
assembly language instruction into its equivalent
hexadecimal code (machine language). Then the
hexadecimal code is entered into memory.

• The other possibility is a program called an assembler,

which does the translation automatically.
Data Formats
• In an 8-bit microprocessor, data can be represented in one of four
formats:
• ASCII
• BCD
• Signed Integer
• Unsigned Integer.

• It is important to recognize that the microprocessor deals with 0’s and

1’s.
• It deals with values as strings of bits.
• It is the job of the user to add a meaning to these strings.
Data Formats …
• Assume the accumulator contains the following value: 0100
0001.
• There are four ways of reading this value:
• It is an unsigned integer expressed in binary, the equivalent
decimal number would be 65.
• It is a number expressed in BCD (Binary Coded Decimal)
format. That would make it, 41.
• It is an ASCII representation of a letter. That would make it
the letter A.
• It is a string of 0’s and 1’s where the 0th and the 6th bits are
set to 1 while all other bits are set to 0.
Instruction Format of 8085
• Each Instruction Format of 8085 and Data Format of 8085
microprocessor has specific information fields. These
information fields of instructions are called elements of
instruction.
• Operation code :
• The operation code field in the instruction specifies the
operation to be performed.
• The operation is specified by binary code, hence the name
operation code or simply opcode.
• For example, for 8085 processor operation code for ADD
B instruction is 80H.
Instruction Format of 8085
• Source / destination operand :
• The source/destination operand field directly specifies the
source/destination operand for the instruction.
• In the Instruction Format of 8085, the instruction MOV
A,B has B register contents as a source operand and A
register contents as a destination operand because this
instruction copies the contents of register B to register A.
Instruction Format of 8085
• Source operand address :
• We know that the operation specified by the instruction
may require one or more operands.
• The source operand may be in the 8085 register or in the
memory.
• Many times the Instruction Format of 8085 specifies the
address of the source operand so that operand(s) can be
accessed and operated by the 8085 according to the
instruction.
• In 8085, the source operand address for instruction ADD
M is given by HL register pair.
Instruction Format of 8085 …
• Destination operand address :
• The operation executed by the 8085 may produce result.
• Most of the times the result is stored in one of the operand.
• Such operand is known as destination operand.
• The Instruction and Data Format of 8085 which produce
result specifies the destination operand address.
• In 8085, the destination operand address for instruction INR
M is given by HL register pair because INR M instruction
increments the contents of memory location specified by HL
register pair and stores the result in the same memory
location.
Instruction Format of 8085 …
• Next instruction address :
• The next instruction address tells the 8085 from where to
fetch the next instruction after completion of execution of
current instruction.
• For BRANCH instructions the address of the next instruction
is specified within the instruction.
• However, for other instructions, the next instruction to be
fetched immediately follows the current instruction.
• The instruction JMP 2000H specifies the next instruction
address as 2000H.
Instruction Formats
• The Instruction Format of 8085 set consists of
One byte instructions: OPCODE
• The byte is always the opcode
• ADD B (80 H)
Two byte instructions: OPCODE OPERAND
• In two-byte instructions the first byte is opcode and second byte is
usually data
• MVI B, 05H (06H,02H)
Three byte instructions: OPCODE OPERAND OPERAND
• In three byte instructions the first byte is opcode and last two bytes
present address or 16-bit data.
• LXI H, 2500H (21H, 00H, 25H)
Opcode Format of 8085
• The 8085 microprocessor has 8-bit opcodes.

• The opcode is unique for each Instruction and Data

Format of 8085 and contains the information about
operation, register to be used, memory to be used etc.

• The 8085 identifies all operations, registers and flags

with a specific code.
Opcode Format of 8085 …
Register Code Register Pair Code
B 000 B-C 00
C 001 D-E 01
D 010 H-L 10
E 011 AF or SP 11
H 100
L 101
M (Memory) 110
A 111
Opcode Format of 8085 …

Sr. Operation Code

Function
No. B7 B6 B5 B4 B3 B2 B1 B0
1 MVI r, data 0 0 D D D 1 1 0
2 LXI rp, data 0 0 D D 0 0 0 1
3 MOV rd, rs 0 1 D D D S S S
Addressing modes of 8085
• The term addressing modes refers to the way in which
the operand of an instruction is specified.

• The addressing mode specifies a rule for interpreting or

modifying the address field of the instruction before the
operand is actually executed.
Addressing modes of 8085 …
• 5 Addressing modes are available in 8085
• Immediate Addressing Mode
• Register Addressing Mode
• Direct Addressing Mode
• Register Indirect Addressing Mode
• Implied/Implicit Addressing Mode
Immediate Addressing Mode
• In immediate addressing mode the source operand is always
data.
• If the data is 8-bit, then the instruction will be of 2 bytes
• If the data is of 16-bit then the instruction will be of 3 bytes.
• Examples:
• MVI B, 45H (Move the data 45H immediately to register B)
• LXI H, 3050H (Load the H-L pair with the operand 3050H
immediately)
• JMP addr(16) (Jump to the operand address immediately)
Register Addressing Mode
• In register addressing mode, the data to be operated is available
inside the register(s) and register(s) is(are) operands.
• Therefore the operation is performed within various registers of
the microprocessor.
• Examples:
• MOV A, B (move the contents of register B to register A)
• ADD B (add contents of registers A and B and store the
result in register A)
• INR A (increment the contents of register A by one)
Direct Addressing Mode
• In direct addressing mode, the data to be operated is available
inside a memory location and that memory location is directly
specified as an operand.
• The address of the operand is directly available in the
instruction itself.
• Examples:
• LDA 2050H (load the contents of memory location into accumulator A)
• LHLD address (load contents of 16-bit memory location into H-L register pair)
• IN 35H (read the data from port whose address is 35H)
Register Indirect Addressing Mode
• In register indirect addressing mode, the data to be operated is
available inside a memory location and that memory location is
indirectly specified by a register pair.
• Examples:
• MOV A, M (move the contents of the memory location
pointed by the H-L pair to the accumulator)
• LDAX B (move contains of B-C register to the accumulator)
• LXI H 9570 (load immediate the H-L pair with the address
of the location 9570)
Implied/Implicit Addressing Mode
• In implied/implicit addressing mode the operand is hidden and
the data to be operated is available in the instruction itself.
• Examples:
• CMA (finds and stores the 1’s complement of the contains of
accumulator A in A)
• RRC (rotate accumulator A right by one bit)
• RLC (rotate accumulator A left by one bit)
Symbols and abbreviations used
addr 16-bit address of the memory location.
Data(8) or data 8-bit data
data(16) 16-bit data
R, Rs, Rd One of the registers A, B, C, D, E, H or L
A, B, C, D, H, L 8-bit register
A Accumulator
H-L Register pair H-L
B-C Register pair B-C
D-E Register pair D-E
PSW Program Status Word
M Memory whose address is in H-L pair
H Appearing at the end of the group of digits specifies hexadecimal, e.g.
2500H
Symbols and abbreviations used …
RP One of the register pairs.
RH The high order register of a register pair
RL The low order register of a register pair
PC 16 bit program counter, PCH is high order 8 bits and PCL low order 8 bits of register PC.
CS Carry Status
[] The contents of the register identified within bracket
[[ ]] The content of the memory location whose address is in the register pair identified
within brackets
^ AND operation
∨ OR operation
⊕ or ∀ Exclusive OR
← Move data in the direction of arrow
⇔ Exchange contents
The 8085 Instructions
• Since the 8085 is an 8-bit device it can have up to 28 (256) instructions.
• However, the 8085 only uses 246 combinations that represent a total
of 74 instructions.
• Most of the instructions have more than one format.

• These instructions can be grouped into five different groups:

• Data Transfer Operations
• Arithmetic Operations
• Logic Operations
• Branch Operations
• Machine Control Operations
Data Transfer Instructions
• Instructions in this group are used to Move or Copy data
(operand) from Source to Destination.

• The contents of the source register are not altered.

• Instructions in this group doesn't changes the status of Flag

register
Data Transfer Instructions . . .
Instruction: MOV RD, RS
Explanation: Move the content of the one register to another
Byte: 1 Byte
Operation Performed: [RD] ← [RS]
Addressing Mode: Register
Flags Affected: None
T-States / Machine Cycles: 4 / 1 (Fetch)
Example: MOV B, C

Before Execution After Execution

20 H 05 H 05 H 05 H
Reg B Reg C Reg B Reg C
Data Transfer Instructions . . .
Instruction: MOV R, M
Explanation: Move the content of memory to register
Byte: 1 Byte
Operation Performed: [R] ← [M] / [R] ← [[H-L]]
Addressing Mode: Register Indirect
Flags Affected: None
T-States / Machine Cycles: 7 / 2 (Fetch, Mem Rd)
Example: MOV B, M
Before Execution After Execution

2504 H 05 H
A5 H 25 H 05 H 2505 H 21 H 21 H
B H L 2506 H 32 H B
Data Transfer Instructions . . .
Instruction: MOV M, R
Explanation: Move the content of register to memory
Byte: 1 Byte
Operation Performed: [M] ← [R] / [[H-L]] ← [R]
Addressing Mode: Register Indirect
Flags Affected: None
T-States / Machine Cycles: 7 / 2 (Fetch, Mem Rd)
Example: MOV M, C
Before Execution After Execution

2504 H 05 H 2504 H 05 H
21 H 25 H 05 H 2505 H 00 H 2505 H 21 H 21 H
C H L 2506 H 32 H 2506 H 32 H C
Data Transfer Instructions . . .
Instruction: MVI R, data(8)
Explanation: Move immediate data to register
Byte: 2 Byte
Operation Performed: [R] ← data(8)
Addressing Mode: Immediate, Register
Flags Affected: None
T-States / Machine Cycles: 7 / 2 (Fetch, Mem Rd)
Example: MVI D, A2H
Before Execution After Execution

A2 H 21 H A2 H A2 H

Data D Data D
Data Transfer Instructions . . .
Instruction: MVI M, data(8)
Explanation: Move immediate data to memory
Byte: 2 Byte
Operation Performed: [M] ← data(8) / [[H-L]] ← data(8)
Addressing Mode: Immediate, Register Indirect
Flags Affected: None
T-States / Machine Cycles: 10 / 3 (Fetch, Mem Rd, Memory Wr)
Example: MVI M, B4H
Before Execution After Execution

2504 H 05 H 2504 H 05 H
B4 H 25 H 05 H 2505 H 00 H 2505 H B4 H B4 H
Data H L 2506 H 32 H 2506 H 32 H Data
Data Transfer Instructions . . .
Instruction: LXI RP , data(16)
Explanation: Load Register pair immediate
Byte: 3 Byte
Operation Performed: [RP] ← data(16), [RH] ←8 MSBs, [RL] ←8 LSBs
Addressing Mode: Immediate
Flags Affected: None
T-States / Machine Cycles: 10 / 3 (Fetch, Mem Rd, Mem Rd)
Example: LXI H, 3240H
Before Execution After Execution

25 H 05 H 32 H 40 H

H L H L
Data Transfer Instructions . . .
Instruction: LDA addr(16)
Explanation: Load Accumulator direct
Byte: 3 Byte
Operation Performed: [A] ← [addr(16)]
Addressing Mode: Direct
Flags Affected: None
T-States / Machine Cycles: 13 / 4 (Fetch, Mem Rd, Mem Rd, Mem Rd)
Example: LDA 2034H
Before Execution After Execution

2033 H 05 H
C1 H
2034 H 23 H 23 H
A 2035 H 32 H A
Data Transfer Instructions . . .
Instruction: STA addr(16)
Explanation: Store Accumulator direct
Byte: 3 Byte
Operation Performed: [addr(16)] ← [A]
Addressing Mode: Direct
Flags Affected: None
T-States / Machine Cycles: 13 / 4 (Fetch, Mem Rd, Mem Rd, Mem Wr)
Example: STA 2034H
Before Execution After Execution
2033 H 05 H 2033 H 05 H
C1 H 2034 H 23 H 2034 H C1 H C1 H
A 2035 H 32 H 2035 H 32 H A
Data Transfer Instructions . . .
Instruction: LHLD addr(16)
Explanation: Load H-L pair direct
Byte: 3 Byte
Operation Performed: [L] ←[addr(16)], [H] ← [addr(16) + 1 ]
Addressing Mode: Direct
Flags Affected: None
T-States / Machine Cycles: 16 / 5 (Fetch, Mem Rd, Mem Rd, Mem Rd, Mem Rd)
Example: LHLD 2034H
Before Execution After Execution
2033 H 05 H 2033 H 05 H 32 H 21 H
A2 H C1 H 2034 H 21 H 2034 H 21 H
H L 2035 H 32 H 2035 H 32 H
H L
Data Transfer Instructions . . .
Instruction: SHLD addr(16)
Explanation: Store H-L pair direct
Byte: 3 Byte
Operation Performed: [addr(16)] ←[L], [addr(16) +1] ← [H]
Addressing Mode: Direct
Flags Affected: None
T-States / Machine Cycles: 16 / 5 (Fetch, Mem Rd, Mem Rd, Mem Wr, Mem Wr)
Example: SHLD 2034H
Before Execution After Execution
A2 H C1 H 2033 H 05 H A2 H C1 H 05 H 2033 H
H L 2034 H 21 H C1 H 2034 H
2035 H 32 H A2 H 2035 H
H L
Data Transfer Instructions . . .
Instruction: LDAX RP (Valid for B-C and D-E pair only)
Explanation: Load accumulator indirect
Byte: 1 Byte
Operation Performed: [A] ←[[RP]]
Addressing Mode: Register Indirect
Flags Affected: None
T-States / Machine Cycles: 7 / 2 (Fetch, Mem Rd)
Example: LDAX B
Before Execution After Execution
20 H C4 H 20C3 H 05 H 20C3 H 05 H
B C 20C4 H 23 H 20C4 H 23 H 23 H
20C5 H 32 H 20C5 H 32 H
F5 H A A
Data Transfer Instructions . . .
Instruction: STAX RP (Valid for B-C and D-E pair only)
Explanation: Store accumulator indirect
Byte: 1 Byte
Operation Performed: [[RP]] ← [A]
Addressing Mode: Register Indirect
Flags Affected: None
T-States / Machine Cycles: 7 / 2 (Fetch, Mem Wr)
Example: STAX D
Before Execution After Execution
25 H 04 H 2503 H 05 H 2503 H 05 H
D E 2504 H C1 H 2504 H E5 H E5 H
2505 H 32 H 2505 H 32 H
E5 H A A
Data Transfer Instructions . . .
Instruction: XCHG (Valid for H-L and D-E pair only)
Explanation: Change the contents of H-L with D-E pair
Byte: 1 Byte
Operation Performed: [H-L] ↔ [D-E]
Addressing Mode: Register
Flags Affected: None
T-States / Machine Cycles: 4 / 1 (Fetch)
Example: XCHG
Before Execution After Execution

25 H 04 H F2 H 4E H F2 H 4E H 25 H 04 H

H L D E H L D E
Arithmetic Instructions
• The instructions of this group perform arithmetic
operations such as addition, subtraction, increment
or decrement of the content of a register or a
memory.
Arithmetic Instructions
Instruction : ADD R
Explanation : Add register to accumulator
Byte : 1Byte
Operation Performed : [A] ← [A] + [R]
Addressing Mode : Register
Flags Affected : All
T-States / Machine Cycles : 4 /1 (Fetch)
Example : ADD E
Before Execution After Execution

05 H 04 H 05 H 09 H

E A E A
Arithmetic Instructions
Instruction : ADD M
Explanation : Add memory to accumulator
Byte : 1 Byte
Operation Performed : [A] ← [A] + [[H-L]]
Addressing Mode : Register indirect
Flags Affected : All
T-States / Machine Cycles : 7 / 2 (Fetch, Mem Rd)
Example : ADD M
Before Execution After Execution
25 H 04 H 2503 H 05 H 2503 H 05 H
2504 H 08 H 2504 H 08 H 0F H
H L
2505 H 32 H 2505 H 32 H A
07 H A
Arithmetic Instructions . . .
Instruction : ADC R
Explanation : Add register with carry to accumulator
Byte : 1 Byte
Operation Performed : [A] ← [A] + [R] + [CS]
Addressing Mode : Register
Flags Affected : All
T-States / Machine Cycles : 4 / 1 (Fetch)
Example : ADC E
Before Execution After Execution

05 H 04 H 01 H 05 H 0A H 00 H

E A CS E A CS
 Arithmetic Instructions
Instruction : ADC M
Explanation : : Add memory with carry to accumulator
Byte : 1 Byte
Operation Performed : [A] ← [A] + [[H-L]] + [CS]
Addressing Mode : Register indirect
Flags Affected : All
T-States / Machine Cycles : 7 / 2 (Fetch, Mem Rd)
Example : ADC M
Before Execution After Execution
25 H 04 H 2503 H 05 H 2503 H 05 H
2504 H 08 H 2504 H 08 H A 10 H CS 00 H
H L
2505 H 32 H 2505 H 32 H
A 07 H CS 01 H
Arithmetic Instructions
Instruction : ADI data(8)
Explanation : Add immediate data to accumulator
Byte : 2 Byte
Operation Performed : [A] ← [A] + data(8)
Addressing Mode : Immediate
Flags Affected : All
T-States / Machine Cycles : 7 /2 (Fetch, Mem Rd)
Example : ADI 05 H
Before Execution After Execution

05 H 04 H 05 H 09 H

data A data A
Arithmetic Instructions
Instruction : ACI data(8)
Explanation : Add immediate data to accumulator with carry
Byte : 2 Byte
Operation Performed : [A] ← [A] + data(8) + [CS]
Addressing Mode : Immediate
Flags Affected : All
T-States / Machine Cycles : 7 /2 (Fetch, Mem Rd)
Example : ACI 05 H
Before Execution After Execution

05 H 04 H 01 H 05 H 0A H 00 H

data A CS data A CS
Arithmetic Instructions . . .
Instruction : DAD RP
Explanation : Add register pair to H-L pair
Byte : 1 Byte
Operation Performed : [H-L] ←[H-L] + [RP]
Addressing Mode : Register
Flags Affected : CS
T-States / Machine Cycles : 10 / 3 (Fetch, Bus Idle, Bus Idle)
Example : DAD B
Before Execution After Execution

05 H 04 H 02 H 04 H 07 H 08 H 02 H 04 H

H L B C H L B C
Arithmetic Instructions . . .
Instruction : DAD SP
Explanation : Add stack pointer to H-L pair
Byte : 1 Byte
Operation Performed : [H-L] ←[H-L] + [SP]
Addressing Mode : Register
Flags Affected : CS
T-States / Machine Cycles : 10 / 3 (Fetch, Bus Idle, Bus Idle)
Example : DAD SP
Before Execution After Execution

05 H 40 H 05 H 04 H 0A H 44 H 05 H 04 H

H L SPH SPL H L SPH SPL

Arithmetic Instructions . . .
Instruction : SUB R
Explanation : Subtract register from accumulator
Byte : 1 Byte
Operation Performed : [A] ← [A] - [R]
Addressing Mode : Register
Flags Affected : All
T-States / Machine Cycles : 4 / 1 (Fetch)
Example : SUB B
Before Execution After Execution

05 H 02 H 03 H 02 H

A B A B
 Arithmetic Instructions . . .
Instruction : SUB M
Explanation : Subtract memory from accumulator
Byte : 1 Byte
Operation Performed : [A] ← [A] - [[H-L]]
Addressing Mode : Register Indirect
Flags Affected : All
T-States / Machine Cycles : 7 / 2 (Fetch, Mem Rd)
Example : SUB M
Before Execution After Execution
20 H C4 H 20C3 H 65 H 20 H C4 H 20C3 H 65 H

H L 20C4 H 05 H H L 20C4 H 05 H
20C5 H 32 H 20C5 H 32 H
A F5 H A F0 H
Arithmetic Instructions . . .
Instruction : SBB R
Explanation : Subtract register from accumulator with borrow
Byte : 1 Byte
Operation Performed : [A] ← [A] - [R] - [CS]
Addressing Mode : Register
Flags Affected : All
T-States / Machine Cycles : 4 / 1 (Fetch)
Example : SBB B
Before Execution After Execution

05 H 02 H 01 H 02 H 02 H 00 H

A B CS A B CS
 Arithmetic Instructions . . .
Instruction : SBB M
Explanation : Subtract register from accumulator with Borrow
Byte : 1 Byte
Operation Performed : [A] ← [A] - [[H-L]] - [CS]
Addressing Mode : Register
Flags Affected : All
T-States / Machine Cycles : 7 / 2 (Fetch, Mem Rd)
Example : SBB M
Before Execution After Execution
20 H C4 H 20C3 H 65 H 20 H C4 H 20C3 H 65 H

H L 20C4 H 05 H H L 20C4 H 05 H
20C5 H 32 H 20C5 H 32 H
A F6 H CS 01 H A F0 H CS 00 H
Arithmetic Instructions . . .
Instruction : SUI data(8)
Explanation : Subtract immediate data from accumulator
Byte : 2 Byte
Operation Performed : [A] ← [A] - data(8)
Addressing Mode : Immediate
Flags Affected : All
T-States / Machine Cycles : 7 / 2 (Fetch, Mem Rd)
Example : SUI 02H
Before Execution After Execution

05 H 02 H 03 H 02 H

A data A data
Arithmetic Instructions . . .
Instruction : SBI data(8)
Explanation : Subtract immediate data from accumulator with borrow
Byte : 2 Byte
Operation Performed : [A] ← [A] - data(8) - [CS]
Addressing Mode : Immediate
Flags Affected : All
T-States / Machine Cycles : 7 / 2 (Fetch, Mem Rd)
Example : SBI 02H
Before Execution After Execution

05 H 02 H 01 H 02 H 02 H 00 H

A data CS A data CS
Arithmetic Instructions . . .
Instruction : INR R
Explanation : Increment register content by 1
Byte : 1 Byte
Operation Performed : [R] ← [R] + 1
Addressing Mode : Register
Flags Affected : All except CS
T-States / Machine Cycles : 4 / 1 (Fetch)
Example : INR A
Before Execution After Execution

05 H 06 H

A A
Arithmetic Instructions . . .
Instruction : INR M
Explanation : Increment memory content by 1
Byte : 1 Byte
Operation Performed : [[H-L]] ← [[H-L]] + 1
Addressing Mode : Register Indirect
Flags Affected : All except CS
T-States / Machine Cycles : 10 / 3 (Fetch, Mem Rd, Mem Wr)
Example : INR M
Before Execution After Execution
20 H C4 H 20C3 H 65 H 20 H C4 H 20C3 H 65 H

H L 20C4 H 05 H H L 20C4 H 06 H
20C5 H 32 H 20C5 H 32 H
CS 00 H CS 00 H
Arithmetic Instructions . . .
Instruction : DCR R
Explanation : Decrement register content by 1
Byte : 1 Byte
Operation Performed : [R] ← [R] - 1
Addressing Mode : Register
Flags Affected : All except CS
T-States / Machine Cycles : 4 / 1 (Fetch, Mem Rd)
Example : DCR A
Before Execution After Execution

05 H 04 H

A A
Arithmetic Instructions . . .
Instruction : DCR M
Explanation : Decrement memory content by 1
Byte : 1 Byte
Operation Performed : [[H-L]] ← [[H-L]] - 1
Addressing Mode : Register Indirect
Flags Affected : All except CS
T-States / Machine Cycles : 10 / 3 (Fetch, Mem Rd, Mem Wr)
Example : DCR M
Before Execution After Execution
20 H C4 H 20C3 H 65 H 20 H C4 H 20C3 H 65 H

H L 20C4 H 05 H H L 20C4 H 04 H
20C5 H 32 H 20C5 H 32 H
CS 00 H CS 00 H
Arithmetic Instructions . . .
Instruction : INX RP
Explanation : Increment register pair
Byte : 1 Byte
Operation Performed : [RP] ←[RP] + 1
Addressing Mode : Register
Flags Affected : None
T-States / Machine Cycles : 6 / 1 (Fetch)
Example : INX H
Before Execution After Execution

20 H C4 H 20 H C5 H
H L H L
Arithmetic Instructions . . .
Instruction : DCX RP
Explanation : Decrement register pair
Byte : 1 Byte
Operation Performed : [RP] ←[RP] - 1
Addressing Mode : Register
Flags Affected : None
T-States / Machine Cycles : 6 / 1 (Fetch)
Example : DCX H
Before Execution After Execution

20 H C4 H 20 H C3 H
H L H L
Arithmetic Instructions . . .
Instruction : DAA
Explanation : Decimal adjust accumulator
Byte : 1 Byte
Operation Performed : [A](10) ← [A] (H)
Addressing Mode : Implicit
Flags Affected : All
T-States / Machine Cycles : 4 / 1 (Fetch)
Example : DAA
Arithmetic Instructions . . .
Programming Examples
Place 05H in register B.
Address Mnemonics Hex Code Comment
2000, 2001 MVI B, 05H 06H, 05H Get 05H in Register B
2002 HLT 76H Stop

Place 32H in register A; then move it to register B.

Address Mnemonics Hex Code Comment
2000, 2001 MVI A, 32H 3EH, 32H Get 32H in Register A
2002 MOV B, A 47H Transfer 32H from register A to B
2003 HLT 76H Stop
Programming Examples …
Load the content in memory 2C50H directly to the accumulator, then
transfer it to register B.
Address Mnemonics Hex Code Comment
2000, 2001, 2002 LDA 2C50H 3AH, 50H, 2CH Get the content of memory location 2C50H in Acc
2003 MOV B, A 47H Move the contents of register A to B
2004 HLT 76H Stop
Data: 2C50H = [05H]

Move the content of memory location 2300H to register C.

Address Mnemonics Hex Code Comment
2000, 2001, 2002 LXI H, 2300H 21H, 00H, 23H Get the memory address 2300H in H-L Pair
2003 MOV C, M 4EH Move the contents of register A to B
2004 HLT 76H Stop
Data: 2300H = [55H]
Programming Examples …
Place the contents of memory location 2500H in register B and that of
2501H in register C.
Address Mnemonics Hex Code Comment
2000, 2001, 2002 LXI H, 2500H 21H, 00H, 25H Get the memory address 2500H in H-L Pair
2003 MOV B, M 46H Move the contents of 2500H to register B
2004 INX H 23H Increment H-L pair by 1
2005 MOV C, M 4EH Move the content of 2501H to register C
2006 HLT 76H Stop
Data: 2500H : 11H 2501H : 15H
Programming Examples …
Place 05H in accumulator. Increment it by one and store the result in
the memory location FC50H
Address Mnemonics Hex Code Comment
2000, 2001 MVI A, 05H 3EH, 05H Get 05H in accumulator
2002 INR A 3CH Increment the content by 1
2003, 2004, 2005 STA FC50H 32H, 50H, FCH Store result in FC50H
2006 HLT 76H Stop
Data: FC50H : 05H
Programming Examples …
Add 49H and 56H.
Get first number in 2501H
Get second number in 2502H
The result is to be stored at 2503H
All numbers are in Hexadecimal
Address Mnemonics Hex Code Comment
2000 LXI H, 2501 21, 01, 25 Get the address of first number in H-L pair.
2003 MOV A, M 7E Get first number in accumulator
2004 INX H 23 Increment content of H-L pair
2005 ADD M 86 Add 1st number with 2nd number
2006 STA 2503 32, 03, 25 Store the result in 2503
2009 HLT 76 Stop
Data: 2501 : [49] 2502 : [56] Result: 2503 : [9F]
Programming Examples …
Subtract 32H from 49H
Get first number 49H in 2501H
Get second number 32H in 2502H
The result is to be stored at 2503H
All numbers are in Hexadecimal
Address Mnemonics Hex Code Comment
2000 LXI H, 2501 21, 01, 25 Get the address of first number in H-L pair.
2003 MOV A, M 7E Get first number in accumulator
2004 INX H 23 Increment content of H-L pair
2005 SUB M 96 1st number - 2nd number
2006 STA 2503 32, 03, 25 Store the result in 2503
2009 HLT 76 Stop
Data: 2501 : [49] 2502 : [32] Result: 2503 : [17]
Logical Instructions
• The instruction in this group perform Logical Operations such as
• AND,
• OR,
• EXCLUSIVE-OR,
• NOT (Complement),
• compare
• Operand may be in
Logical Instructions …
Instruction : ANA R
Explanation : AND register with accumulator
Byte : 1 Byte
Operation Performed : [A] ← [A] ˄ [R]
Addressing Mode : Register
Flags Affected : All
T-States / Machine Cycles : 4 / 1 (Fetch)
Example : ANA B
Before Execution After Execution
A 1000 1111 A 1000 1001

B 1100 1001 B 1100 1001

Logical Instructions …
Instruction : ANA M
Explanation : AND memory with accumulator
Byte : 1 Byte
Operation Performed : [A] ← [A] ˄ [[H-L]]
Addressing Mode : Register Indirect
Flags Affected : All
T-States / Machine Cycles : 7 / 2 (Fetch, Mem Rd)
Example : ANA M
Before Execution After Execution
H-L 281AH H-L 281AH
2819H 1100 1001 2819H 1100 1001
A 1000 1111 281AH 1001 1000 A 1000 1000 281AH 1001 1000
281BH 1111 1100 281BH 1111 1100
Logical Instructions …
Instruction : ANI data(8)
Explanation : AND immediate data with accumulator
Byte : 2 Byte
Operation Performed : [A] ← [A] ˄ data(8)
Addressing Mode : Immediate
Flags Affected : All
T-States / Machine Cycles : 7 / 2 (Fetch, Mem Rd)
Example : ANI C9H
Before Execution After Execution
A 1000 1111 A 1000 1001

data 1100 1001 data 1100 1001

Logical Instructions …
Instruction : ORA R
Explanation : OR register with accumulator
Byte : 1 Byte
Operation Performed : [A] ← [A] ˅ [R]
Addressing Mode : Register
Flags Affected : All
T-States / Machine Cycles : 4 / 1 (Fetch)
Example : ORA B
Before Execution After Execution
A 1000 1111 A 1100 1111

B 1100 1001 B 1100 1001

Logical Instructions …
Instruction : ORA M
Explanation : OR memory with accumulator
Byte : 1 Byte
Operation Performed : [A] ← [A] ˅ [[H-L]]
Addressing Mode : Register Indirect
Flags Affected : All
T-States / Machine Cycles : 7 / 2 (Fetch, Mem Rd)
Example : ORA M
Before Execution After Execution
H-L 281AH H-L 281AH
2819H 1100 1001 2819H 1100 1001
A 1000 1111 281AH 1001 1000 A 1001 1111 281AH 1001 1000
281BH 1111 1100 281BH 1111 1100
Logical Instructions …
Instruction : ORI data(8)
Explanation : OR immediate data with accumulator
Byte : 2 Byte
Operation Performed : [A] ← [A] ˅ data(8)
Addressing Mode : Immediate
Flags Affected : All
T-States / Machine Cycles : 7 / 2 (Fetch, Mem Rd)
Example : ORI C9H
Before Execution After Execution
A 1000 1111 A 1100 1111

data 1100 1001 data 1100 1001

Logical Instructions …
Instruction : XRA R
Explanation : EXCLUSIVE-OR register with accumulator
Byte : 1 Byte
Operation Performed : [A] ← [A] Ɐ [R]
Addressing Mode : Register
Flags Affected : All
T-States / Machine Cycles : 4 / 1 (Fetch)
Example : XRA B
Before Execution After Execution
A 1000 1111 A 0100 0110

B 1100 1001 B 1100 1001

Logical Instructions …
Instruction : XRA M
Explanation : EXCLUSIVE-OR memory with accumulator
Byte : 1 Byte
Operation Performed : [A] ← [A] Ɐ [[H-L]]
Addressing Mode : Register Indirect
Flags Affected : All
T-States / Machine Cycles : 7 / 2 (Fetch, Mem Rd)
Example : XRA M
Before Execution After Execution
H-L 281AH H-L 281AH
2819H 1100 1001 2819H 1100 1001
A 1000 1111 281AH 1001 1000 A 0001 0111 281AH 1001 1000
281BH 1111 1100 281BH 1111 1100
Logical Instructions …
Instruction : XRI data(8)
Explanation : EXCLUSIVE-OR immediate data with accumulator
Byte : 2 Byte
Operation Performed : [A] ← [A] Ɐ data(8)
Addressing Mode : Immediate
Flags Affected : All
T-States / Machine Cycles : 7 / 2 (Fetch, Mem Rd)
Example : XRI C9H
Before Execution After Execution
A 1000 1111 A 0100 0110

data 1100 1001 data 1100 1001

Logical Instructions …
Instruction : CMA
Explanation : Complement the accumulator
Byte : 1 Byte
Operation Performed : [A] ← [A ഥ]
Addressing Mode : Implicit
Flags Affected : None
T-States / Machine Cycles : 4 / 1 (Fetch)
Example : CMA
Before Execution After Execution
A 1000 1111 A 0111 0000
Logical Instructions …
Instruction : CMC
Explanation : Complement the carry status
Byte : 1 Byte
Operation Performed : [CS] ← [CS]
Addressing Mode :
Flags Affected : Only Carry
T-States / Machine Cycles : 4 / 1 (Fetch)
Example : CMC
Before Execution After Execution
CS 1 CS 0

CS 0 CS 1
Logical Instructions …
Instruction : STC
Explanation : Set carry status
Byte : 1 Byte
Operation Performed : [CS] ← 1
Addressing Mode :
Flags Affected : Only Carry
T-States / Machine Cycles : 4 / 1 (Fetch)
Example : STC
Before Execution After Execution
CS 0 CS 1

CS 1 CS 1
Arithmetic Instructions . . .
Instruction : CMP R
Explanation : Compare register with accumulator
Byte : 1 Byte
Operation Performed : [A] - [R]
Addressing Mode : Register
Flags Affected : All
T-States / Machine Cycles : 4 / 1 (Fetch)
Example : CMP B
Before Execution After Execution

05 H 02 H 05 H 02 H

A B A B
 Arithmetic Instructions . . .
Instruction : CMP M
Explanation : Compare memory with accumulator
Byte : 1 Byte
Operation Performed : [A] - [[H-L]]
Addressing Mode : Register Indirect
Flags Affected : All
T-States / Machine Cycles : 7 / 2 (Fetch, Mem Rd)
Example : CMP M
Before Execution After Execution
20 H C4 H 20C3 H 65 H 20 H C4 H 20C3 H 65 H

H L 20C4 H 05 H H L 20C4 H 05 H
20C5 H 32 H 20C5 H 32 H
A F5 H A F0 H
Arithmetic Instructions . . .
Instruction : CPI data(8)
Explanation : Compare immediate data with accumulator
Byte : 2 Byte
Operation Performed : [A] - data(8)
Addressing Mode : Immediate
Flags Affected : All
T-States / Machine Cycles : 7 / 2 (Fetch, Mem Rd)
Example : CPI 02H
Before Execution After Execution

05 H 02 H 05 H 02 H

A data A data
Logical Instructions . . .
Instruction : RLC
Explanation : Rotate accumulator left
Byte : 1 Byte
Operation Performed : [An+1] ←[An], [A0] ←[A7], [CS] ←[A7]
Addressing Mode : Implicit
Flags Affected : Only Carry
T-States / Machine Cycles : 4 / 1 (Fetch)
Example : RLC
Before Execution After Execution

CS A7 A6 A5 A4 A3 A2 A1 A0 CS A7 A6 A5 A4 A3 A2 A1 A0

0 1 0 1 1 1 0 0 1 1 0 1 1 1 0 0 1 1
Logical Instructions . . .
Instruction : RRC
Explanation : Rotate accumulator right
Byte : 1 Byte
Operation Performed : [An] ←[An+1], [A7] ←[A0], [CS] ←[A0],
Addressing Mode : Implicit
Flags Affected : Only Carry
T-States / Machine Cycles : 4 / 1 (Fetch)
Example : RRC
Before Execution After Execution

CS A7 A6 A5 A4 A3 A2 A1 A0 CS A7 A6 A5 A4 A3 A2 A1 A0

0 1 0 1 1 1 0 0 1 1 1 1 0 1 1 1 0 0
Logical Instructions . . .
Instruction : RAL
Explanation : Rotate accumulator left through carry
Byte : 1 Byte
Operation Performed : [An+1] ←[An], [CS] ←[A7], [A0] ←[CS]
Addressing Mode : Implicit
Flags Affected : Only Carry
T-States / Machine Cycles : 4 / 1 (Fetch)
Example : RAL
Before Execution After Execution

CS A7 A6 A5 A4 A3 A2 A1 A0 CS A7 A6 A5 A4 A3 A2 A1 A0

0 1 0 1 1 1 0 0 1 1 0 1 1 1 0 0 1 0
Logical Instructions . . .
Instruction : RAR
Explanation : Rotate accumulator right through carry
Byte : 1 Byte
Operation Performed : [An] ←[An+1], [CS] ←[A0], [A7] ←[CS]
Addressing Mode : Implicit
Flags Affected : Only Carry
T-States / Machine Cycles : 4 / 1 (Fetch)
Example : RAR
Before Execution After Execution

CS A7 A6 A5 A4 A3 A2 A1 A0 CS A7 A6 A5 A4 A3 A2 A1 A0

0 1 0 1 1 1 0 0 1 1 0 1 0 1 1 1 0 0
Branch Control Instructions
• The instruction in this group changes the normal sequence of
the program
• There are two types of branch control instructions.
• Unconditional: It transfer the program to the specified
address (label) unconditionally (without checking any
condition).
• Conditional: It transfer the program to the specified address
(label) when a certain condition is satisfied.
Branch Control Instructions . . .
Instruction : JMP addr (label)
Explanation : Jump to the instruction specified by the addr (label)
Byte : 3 Byte
Operation Performed : [PC] ← addr (Label)
Addressing Mode : Immediate
Flags Affected : None
T-States / Machine Cycles : 10 / 3 (Fetch, Mem Rd, Mem Rd)
Example : JMP 2900H

2000 LXI H, 2800 PC = 2003 2900 ADD A, B PC = 2901

2003 MOV A, M PC = 2004 2901 STA 3200 PC = 2904
2004 JMP 2900 PC = 2900 2904 JMP 2007 PC = 2007
2007 INX H PC = 2008 2907 INR B PC = 2908
Branch Control Instructions . . .
Instruction : JZ addr (label)
Explanation : Jump if result is zero (ZF = 1)
Byte : 3 Byte
Operation Performed : [PC] ← addr (Label)
Addressing Mode : Immediate
Flags Affected : None
T-States / Machine Cycles : 7 /2 and 10 / 3
Example :
2000 LXI H, 2500 PC = 2003
2003 MVI A, 05 PC = 2005
2005 CMP M PC = 2006 False
2006 JZ 2800 PC = 2800 PC = 2009
2009 INX H PC = 2010
Branch Control Instructions . . .
Instruction : JNZ addr (label)
Explanation : Jump if result is not zero (ZF = 0)
Byte : 3 Byte
Operation Performed : [PC] ← addr (Label)
Addressing Mode : Immediate
Flags Affected : None
T-States / Machine Cycles : 7 /2 and 10 / 3
Example :
2000 LXI H, 2500 PC = 2003
2003 MVI A, 05 PC = 2005
2005 CMP M PC = 2006 False
2006 JNZ 2800 PC = 2800 PC = 2009
2009 INX H PC = 2010
Branch Control Instructions . . .
Instruction : JC addr (label)
Explanation : Jump if carry (CS = 1)
Byte : 3 Byte
Operation Performed : [PC] ← addr (Label)
Addressing Mode : Immediate
Flags Affected : None
T-States / Machine Cycles : 7 /2 and 10 / 3
Example :
2000 LXI H, 2500 PC = 2003
2003 MVI A, 05 PC = 2005
2005 CMP M PC = 2006 False
2006 JC 2800 PC = 2800 PC = 2009
2009 INX H PC = 2010
Branch Control Instructions . . .
Instruction : JNC addr (label)
Explanation : Jump if not carry (CS = 0)
Byte : 3 Byte
Operation Performed : [PC] ← addr (Label)
Addressing Mode : Immediate
Flags Affected : None
T-States / Machine Cycles : 7 /2 and 10 / 3
Example :
2000 LXI H, 2500 PC = 2003
2003 MVI A, 05 PC = 2005
2005 CMP M PC = 2006 False
2006 JNC 2800 PC = 2800 PC = 2009
2009 INX H PC = 2010
Branch Control Instructions . . .
Instruction : JP addr (label)
Explanation : Jump if result is plus / positive (S = 0)
Byte : 3 Byte
Operation Performed : [PC] ← addr (Label)
Addressing Mode : Immediate
Flags Affected : None
T-States / Machine Cycles : 7 /2 and 10 / 3
Example :
2000 LXI H, 2500 PC = 2003
2003 MVI A, 05 PC = 2005
2005 CMP M PC = 2006 False
2006 JP 2800 PC = 2800 PC = 2009
2009 INX H PC = 2010
Branch Control Instructions . . .
Instruction : JM addr (label)
Explanation : Jump if result is minus / negative (S = 1)
Byte : 3 Byte
Operation Performed : [PC] ← addr (Label)
Addressing Mode : Immediate
Flags Affected : None
T-States / Machine Cycles : 7 /2 and 10 / 3
Example :
2000 LXI H, 2500 PC = 2003
2003 MVI A, 05 PC = 2005
2005 CMP M PC = 2006 False
2006 JM 2800 PC = 2800 PC = 2009
2009 INX H PC = 2010
Branch Control Instructions . . .
Instruction : JPE addr (label)
Explanation : Jump if even parity (P = 1)
Byte : 3 Byte
Operation Performed : [PC] ← addr (Label)
Addressing Mode : Immediate
Flags Affected : None
T-States / Machine Cycles : 7 /2 and 10 / 3
Example :
2000 LXI H, 2500 PC = 2003
2003 MVI A, 05 PC = 2005
2005 CMP M PC = 2006 False
2006 JPE 2800 PC = 2800 PC = 2009
2009 INX H PC = 2010
Branch Control Instructions . . .
Instruction : JPO addr (label)
Explanation : Jump if odd parity (P = 0)
Byte : 3 Byte
Operation Performed : [PC] ← addr (Label)
Addressing Mode : Immediate
Flags Affected : None
T-States / Machine Cycles : 7 /2 and 10 / 3
Example :
2000 LXI H, 2500 PC = 2003
2003 MVI A, 05 PC = 2005
2005 CMP M PC = 2006 False
2006 JPO 2800 PC = 2800 PC = 2009
2009 INX H PC = 2010
Branch Control Instructions . . .
Instruction : CALL addr (label)
Explanation : Unconditional CALL: Call the subroutine identified by the address.
Byte : 3 Byte
Operation Performed : [[SP]-1] ← [PCH] , [[SP]-2] ← [PCL], [PC] ← addr (label), [SP] ← [SP]-2
Addressing Mode : Immediate / Register Indirect
Flags Affected : None
T-States / Machine Cycles : 18 / 5 (Fetch, Mem Rd, Mem Rd, Mem Wr, Mem Wr)
Example :

2000 LXI H, 2800 PC = 2003 2900 ADD A, B PC = 2901

2003 MOV A, M PC = 2004 2901 STA 3200 PC = 2904
2004 CALL 2900 PC = 2900 2904 RET PC = 2007
2007 INX H PC = 2008
Branch Control Instructions . . .
Instruction : CZ addr (label)
Explanation : Call if result is zero (Z = 1)
Byte : 3 Byte
Operation Performed : [[SP]-1] ← [PCH] , [[SP]-2] ← [PCL], [PC] ← addr (label), [SP] ← [SP]-2
Addressing Mode : Immediate / Register Indirect
Flags Affected : None
T-States / Machine Cycles : 9 /2 and 18 / 5
Example :
2000 LXI H, 2500 PC = 2003 2800 ADD A, B PC = 2801
2003 MVI A, 05 PC = 2004 2801 STA 3200 PC = 2804
2005 CMP M PC = 2900 False 2804 RET PC = 2009
2006 CZ 2800 PC = 2800 PC = 2009
2009 INX H PC = 2010
Branch Control Instructions . . .
Instruction : CNZ addr (label)
Explanation : Call if result is not zero (Z = 0)
Byte : 3 Byte
Operation Performed : [[SP]-1] ← [PCH] , [[SP]-2] ← [PCL], [PC] ← addr (label), [SP] ← [SP]-2
Addressing Mode : Immediate / Register Indirect
Flags Affected : None
T-States / Machine Cycles : 9 /2 and 18 / 5
Example :
2000 LXI H, 2500 PC = 2003 2800 ADD A, B PC = 2801
2003 MVI A, 05 PC = 2004 2801 STA 3200 PC = 2804
2005 CMP M PC = 2900 False 2804 RET PC = 2009
2006 CNZ 2800 PC = 2800 PC = 2009
2009 INX H PC = 2010
Branch Control Instructions . . .
Instruction : CC addr (label)
Explanation : Call if carry (CS = 1)
Byte : 3 Byte
Operation Performed : [[SP]-1] ← [PCH] , [[SP]-2] ← [PCL], [PC] ← addr (label), [SP] ← [SP]-2
Addressing Mode : Immediate / Register Indirect
Flags Affected : None
T-States / Machine Cycles : 9 /2 and 18 / 5
Example :
2000 LXI H, 2500 PC = 2003 2800 ADD A, B PC = 2801
2003 MVI A, 05 PC = 2004 2801 STA 3200 PC = 2804
2005 CMP M PC = 2900 False 2804 RET PC = 2009
2006 CC 2800 PC = 2800 PC = 2009
2009 INX H PC = 2010
Branch Control Instructions . . .
Instruction : CNC addr (label)
Explanation : Call if not carry (CS = 0)
Byte : 3 Byte
Operation Performed : [[SP]-1] ← [PCH] , [[SP]-2] ← [PCL], [PC] ← addr (label), [SP] ← [SP]-2
Addressing Mode : Immediate / Register Indirect
Flags Affected : None
T-States / Machine Cycles : 9 /2 and 18 / 5
Example :
2000 LXI H, 2500 PC = 2003 2800 ADD A, B PC = 2801
2003 MVI A, 05 PC = 2004 2801 STA 3200 PC = 2804
2005 CMP M PC = 2900 False 2804 RET PC = 2009
2007 CNC 2800 PC = 2800 PC = 2009
2009 INX H PC = 2010
Branch Control Instructions . . .
Instruction : CP addr (label)
Explanation : Call if result is plus / positive (S = 0)
Byte : 3 Byte
Operation Performed : [[SP]-1] ← [PCH] , [[SP]-2] ← [PCL], [PC] ← addr (label), [SP] ← [SP]-2
Addressing Mode : Immediate / Register Indirect
Flags Affected : None
T-States / Machine Cycles : 9 /2 and 18 / 5
Example :
2000 LXI H, 2500 PC = 2003 2800 ADD A, B PC = 2801
2003 MVI A, 05 PC = 2004 2801 STA 3200 PC = 2804
2005 CMP M PC = 2900 False 2804 RET PC = 2009
2006 CP 2800 PC = 2800 PC = 2009
2009 INX H PC = 2010
Branch Control Instructions . . .
Instruction : CM addr (label)
Explanation : Call if result is minus / negative(S = 1)
Byte : 3 Byte
Operation Performed : [[SP]-1] ← [PCH] , [[SP]-2] ← [PCL], [PC] ← addr (label), [SP] ← [SP]-2
Addressing Mode : Immediate / Register Indirect
Flags Affected : None
T-States / Machine Cycles : 9 /2 and 18 / 5
Example :
2000 LXI H, 2500 PC = 2003 2800 ADD A, B PC = 2801
2003 MVI A, 05 PC = 2004 2801 STA 3200 PC = 2804
2005 CMP M PC = 2900 False 2804 RET PC = 2009
2006 CM 2800 PC = 2800 PC = 2009
2009 INX H PC = 2010
Branch Control Instructions . . .
Instruction : CPE addr (label)
Explanation : Call if parity is even (P = 1)
Byte : 3 Byte
Operation Performed : [[SP]-1] ← [PCH] , [[SP]-2] ← [PCL], [PC] ← addr (label), [SP] ← [SP]-2
Addressing Mode : Immediate / Register Indirect
Flags Affected : None
T-States / Machine Cycles : 9 /2 and 18 / 5
Example :
2000 LXI H, 2500 PC = 2003 2800 ADD A, B PC = 2801
2003 MVI A, 05 PC = 2004 2801 STA 3200 PC = 2804
2005 CMP M PC = 2900 False 2804 RET PC = 2009
2006 CPE 2800 PC = 2800 PC = 2009
2009 INX H PC = 2010
Branch Control Instructions . . .
Instruction : CPO addr (label)
Explanation : Call if parity is odd (P = 0)
Byte : 3 Byte
Operation Performed : [[SP]-1] ← [PCH] , [[SP]-2] ← [PCL], [PC] ← addr (label), [SP] ← [SP]-2
Addressing Mode : Immediate / Register Indirect
Flags Affected : None
T-States / Machine Cycles : 9 /2 and 18 / 5
Example :
2000 LXI H, 2500 PC = 2003 2800 ADD A, B PC = 2801
2003 MVI A, 05 PC = 2004 2801 STA 3200 PC = 2804
2005 CMP M PC = 2900 False 2804 RET PC = 2009
2006 CPO 2800 PC = 2800 PC = 2009
2009 INX H PC = 2010
Branch Control Instructions . . .
Instruction : RET
Explanation : Unconditional RET: Return from subroutine
Byte : 1 Byte
Operation Performed : [PCL] ← [[SP]], [PCH] ← [[SP] + 1], [SP] ← [SP] + 2
Addressing Mode : Register Indirect
Flags Affected : None
T-States / Machine Cycles : 12 / 3 (Fetch, Mem Rd, Mem Rd)
Example :

2000 LXI H, 2800 PC = 2003 2900 ADD A, B PC = 2901

2003 MOV A, M PC = 2004 2901 STA 3200 PC = 2904
2004 CALL 2900 PC = 2900 2904 RET PC = 2007
2007 INX H PC = 2008
Branch Control Instructions . . .
Instruction : RZ
Explanation : Return if result is zero (Z = 1)
Byte : 1 Byte
Operation Performed : [PCL] ← [[SP]], [PCH] ← [[SP] + 1], [SP] ← [SP] + 2
Addressing Mode : Register Indirect
Flags Affected : None
T-States / Machine Cycles : 6 / 1 or 12 / 3
Example :
2000 LXI H, 2500 PC = 2003 2800 CMP B PC = 2801
2003 MVI A, 05 PC = 2004 2801 RZ PC = 2009 / 2802
2005 MOV B, M PC = 2900 2802 INR B
2006 CALL 2800 PC = 2800
2009 INX H
Branch Control Instructions . . .
Instruction : RNZ
Explanation : Return if result is not zero (Z = 0)
Byte : 1 Byte
Operation Performed : [PCL] ← [[SP]], [PCH] ← [[SP] + 1], [SP] ← [SP] + 2
Addressing Mode : Register Indirect
Flags Affected : None
T-States / Machine Cycles : 6 / 1 or 12 / 3
Example :
2000 LXI H, 2500 PC = 2003 2800 CMP B PC = 2801
2003 MVI A, 05 PC = 2004 2801 RNZ PC = 2009 / 2802
2005 MOV B, M PC = 2900 2802 INR B
2006 CALL 2800 PC = 2800
2009 INX H
Branch Control Instructions . . .
Instruction : RC
Explanation : Return if carry (CS = 1)
Byte : 1 Byte
Operation Performed : [PCL] ← [[SP]], [PCH] ← [[SP] + 1], [SP] ← [SP] + 2
Addressing Mode : Register Indirect
Flags Affected : None
T-States / Machine Cycles : 6 / 1 or 12 / 3
Example :
2000 LXI H, 2500 PC = 2003 2800 CMP B PC = 2801
2003 MVI A, 05 PC = 2004 2801 RC PC = 2009 / 2802
2005 MOV B, M PC = 2900 2802 INR B
2006 CALL 2800 PC = 2800
2009 INX H
Branch Control Instructions . . .
Instruction : RNC
Explanation : Return if no carry (CS = 0)
Byte : 1 Byte
Operation Performed : [PCL] ← [[SP]], [PCH] ← [[SP] + 1], [SP] ← [SP] + 2
Addressing Mode : Register Indirect
Flags Affected : None
T-States / Machine Cycles : 6 / 1 or 12 / 3
Example :
2000 LXI H, 2500 PC = 2003 2800 CMP B PC = 2801
2003 MVI A, 05 PC = 2004 2801 RNC PC = 2009 / 2802
2005 MOV B, M PC = 2900 2802 INR B
2006 CALL 2800 PC = 2800
2009 INX H
Branch Control Instructions . . .
Instruction : RP
Explanation : Return if result is plus / positive (S = 0)
Byte : 1 Byte
Operation Performed : [PCL] ← [[SP]], [PCH] ← [[SP] + 1], [SP] ← [SP] + 2
Addressing Mode : Register Indirect
Flags Affected : None
T-States / Machine Cycles : 6 / 1 or 12 / 3
Example :
2000 LXI H, 2500 PC = 2003 2800 CMP B PC = 2801
2003 MVI A, 05 PC = 2004 2801 RP PC = 2009 / 2802
2005 MOV B, M PC = 2900 2802 INR B
2006 CALL 2800 PC = 2800
2009 INX H
Branch Control Instructions . . .
Instruction : RM
Explanation : Return if result is minus / negative (S = 1)
Byte : 1 Byte
Operation Performed : [PCL] ← [[SP]], [PCH] ← [[SP] + 1], [SP] ← [SP] + 2
Addressing Mode : Register Indirect
Flags Affected : None
T-States / Machine Cycles : 6 / 1 or 12 / 3
Example :
2000 LXI H, 2500 PC = 2003 2800 CMP B PC = 2801
2003 MVI A, 05 PC = 2004 2801 RM PC = 2009 / 2802
2005 MOV B, M PC = 2900 2802 INR B
2006 CALL 2800 PC = 2800
2009 INX H
Branch Control Instructions . . .
Instruction : RPE
Explanation : Return if even parity (P = 1)
Byte : 1 Byte
Operation Performed : [PCL] ← [[SP]], [PCH] ← [[SP] + 1], [SP] ← [SP] + 2
Addressing Mode : Register Indirect
Flags Affected : None
T-States / Machine Cycles : 6 / 1 or 12 / 3
Example :
2000 LXI H, 2500 PC = 2003 2800 CMP B PC = 2801
2003 MVI A, 05 PC = 2004 2801 RPE PC = 2009 / 2802
2005 MOV B, M PC = 2900 2802 INR B
2006 CALL 2800 PC = 2800
2009 INX H
Branch Control Instructions . . .
Instruction : RPO
Explanation : Return if odd parity (P = 0)
Byte : 1 Byte
Operation Performed : [PCL] ← [[SP]], [PCH] ← [[SP] + 1], [SP] ← [SP] + 2
Addressing Mode : Register Indirect
Flags Affected : None
T-States / Machine Cycles : 6 / 1 or 12 / 3
Example :
2000 LXI H, 2500 PC = 2003 2800 CMP B PC = 2801
2003 MVI A, 05 PC = 2004 2801 RPO PC = 2009 / 2802
2005 MOV B, M PC = 2900 2802 INR B
2006 CALL 2800 PC = 2800
2009 INX H
Branch Control Instructions . . .
Instruction : RSTn
Explanation : Restart
Byte : 1 Byte
: [[SP]-1] ← [PCH], [[SP]-2] ← [PCL], [SP] ← [SP] - 2, [PC] ← 8 times n
Operation Performed
Addressing Mode : Register Indirect
Flags Affected : None
T-States / Machine Cycles : 12 / 3
One word CALL
Branch Control Instructions . . .
Instruction Opcode Restart Locations
RST 0 C7 0000
RST 1 CF 0008
RST 2 D7 0010
RST 3 DF 0018
RST 4 E7 0020
RST 5 EF 0028
RST 6 F7 0030
RST 7 FF 0038
Branch Control Instructions . . .
Instruction : PCHL
Explanation : Jump address specified by H-L pair
Byte : 1 Byte
Operation Performed : [PC] ← [H-L], [PCH] ←[H], [PCL] ←[L]
Addressing Mode : Register
Flags Affected : None
T-States / Machine Cycles : 6 / 1
Example : PCHL
Stack, I/O and Machine Instructions
• This group contains the instructions for
• input ports,
• output ports,
• stack and
• machine control.
Stack, I/O and Machine Instructions . . .
Instruction : IN port address (8)
Explanation : Input to accumulator from I/O port
Byte : 2 Byte
Operation Performed : [A] ← [Port]
Addressing Mode : Direct
Flags Affected : None
T-States / Machine Cycles : 10 /3
Example : IN 80H
Stack, I/O and Machine Instructions . . .
Instruction : OUT port address (8)
Explanation : Output from accumulator to I/O port
Byte : 2 Byte
Operation Performed : [Port] ← [A]
Addressing Mode : Direct
Flags Affected : None
T-States / Machine Cycles : 10 /3
Example : OUT 81H
Stack, I/O and Machine Instructions . . .
Instruction : OUT port address (8)
Explanation : Output from accumulator to I/O port
Byte : 2 Byte
Operation Performed : [Port] ← [A]
Addressing Mode : Direct
Flags Affected : None
T-States / Machine Cycles : 10 /3
Example : OUT 81H
Stack, I/O and Machine Instructions . . .
Instruction : PUSH RP
Explanation : Push the content of register pair to stack
Byte : 1 Byte
Operation Performed : [[SP] - 1] ← [RH], [[SP] - 2] ← [RL], [SP] ← [SP] - 2
Addressing Mode : Register (source) / Register Indirect (destination)
Flags Affected : None 8085 Register
F
T-States / Machine Cycles : 12 / 3 A
B C
D E
Example : PUSH H H 42 F2 L
SP 2097
Memory

F2 2097
42 2098
X 2099
Stack, I/O and Machine Instructions . . .
Instruction : PUSH PSW
Explanation : Push processor status word to stack
Byte : 1 Byte
Operation Performed : [[SP] - 1] ← [A], [[SP] - 2] ← [PSW], [SP] ← [SP] - 2
Addressing Mode : Register (source) / Register Indirect (destination)
Flags Affected : None A Flag
T-States / Machine Cycles : 12 / 3
12 80
Example : PUSH PSW

FFFB
FFFC
FFFD 80
FFFE 12
FFFF
Stack, I/O and Machine Instructions . . .
Instruction : POP RP
Explanation : Pop the content of stack to register pair
Byte : 1 Byte
Operation Performed : [RL] ← [[ SP ]], [RH] ← [[SP] + 1], [SP] ← [SP] + 2
Addressing Mode : Register Indirect (source) / Register (destination)
8085 Register
Flags Affected : None A F
B C
T-States / Machine Cycles : 10 / 3 D E
H 42 F2 L
Example : POP H SP 2099

MEMORY

F2 2097
42 2098
X 2099
Stack, I/O and Machine Instructions . . .
Instruction : POP PSW
Explanation : Pop content of stack to processor status word
Byte : 1 Byte
Operation Performed : [PSW] ← [[SP]], [A] ← [[SP] + 1], [SP] ← [SP] + 2
Addressing Mode : Register Indirect (source) / Register (destination)
Flags Affected : None A FLAG
T-States / Machine Cycles : 10 / 3 12 80

Example : POP PSW

FFFB
FFFC
FFFD 80
FFFE 12
FFFF
Stack, I/O and Machine Instructions . . .
Instruction : XTHL
Explanation : Exchange top stack with H-L
Byte : 1 Byte
Operation Performed : [L] ↔ [[SP]], [H] ↔ [[SP] + 1]
Addressing Mode : Register Indirect
Flags Affected : None
T-States / Machine Cycles : 16 / 5
Example : XTHL
Stack, I/O and Machine Instructions . . .
Instruction : SPHL
Explanation : Moves the contents of H-L pair to stack pointer
Byte : 1 Byte
Operation Performed : [SP] ↔ [H-L]
Addressing Mode : Register
Flags Affected : None
T-States / Machine Cycles : 6 / 1
Example : SPHL
Stack, I/O and Machine Instructions . . .
Instruction : EI
Explanation : Enable Interrupts
Byte : 1 Byte
Operation Performed :
Addressing Mode :
Flags Affected : None
T-States / Machine Cycles : 4 / 1
Example : EI
Stack, I/O and Machine Instructions . . .
Instruction : DI
Explanation : Disable Interrupts
Byte : 1 Byte
Operation Performed :
Addressing Mode :
Flags Affected : None
T-States / Machine Cycles : 4 / 1
Example : EI
Stack, I/O and Machine Instructions . . .
Instruction : SIM
Explanation : Set Interrupts Masks
Byte : 1 Byte
Operation Performed :
Addressing Mode :
Flags Affected : None
T-States / Machine Cycles : 4 / 1
Example : MVI A, 55
SIM
Stack, I/O and Machine Instructions . . .
Instruction : RIM
Explanation : Read Interrupts Masks
Byte : 1 Byte
Operation Performed :
Addressing Mode :
Flags Affected : None
T-States / Machine Cycles : 4 / 1
Example : RIM
Stack, I/O and Machine Instructions . . .
Instruction : NOP
Explanation : No operation
Byte : 1 Byte
Operation Performed :
Addressing Mode :
Flags Affected : None
T-States / Machine Cycles : 4 / 1
Example : MVI A, 32 H
NOP
NOP
OUT 81 H
Stack, I/O and Machine Instructions . . .
Instruction : HLT
Explanation : Halt / Stop
Byte : 1 Byte
Operation Performed :
Addressing Mode :
Flags Affected : None
T-States / Machine Cycles : 5 / 1
Example : MVI A, 32 H
NOP
OUT 81 H
HLT
 The stack
⚫ The stack is a group of memory location in the
R/W memory that is used for temporary storage
of binary information during the execution of a
program
⚫ The stack is a LIFO structure.
– Last In First Out.
⚫ The starting location of the stack is defined by
loading a 16 bit address into the stack pointer
that spaced is reserved, usually at the top of
the memory map.
 The stack
⚫ The stack normally grows backwards into
memory.
⚫ The stack can be initialized anywhere in the
user memory map , but stack is initialized at the
highest memory location so that there will not
be any interface with the program.
⚫ In 8085 microprocessor system the beginning of
the stack is defined in the program by using the
instruction
➢ LXI SP,16 bit.
➢ The LXI SP,a 16 bit state that load the 16 bit
address into the stack pointer register.
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Information is stored and retrieved from
the stack
•The 8085 provide two instruction PUSH & POP for storing infor
mation on the stack and retrieving it back.
•Information in the register pairs stored on the stack in reverse
order by using the instruction PUSH.

• Information retrieved from the stack by using the instruction

POP.
•PUSH & POP both instruction works with register pairs only.
•The storage and retrieval of the content of registers on the
stack fallows the LIFO(Last-In-First-Out) sequence.
•Information in the stack location may not be destroyed until
new information is stored in that memory location

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 The PUSH Instruction

2000 LXI SP,2099H Load the stack pointer register with the addre
ss 2099.
2003 LXI H ,42F2H Loads data in the HL register pair.

2006 PUSH H The content of the HL register pair pushed int

o stack.
2007 DELAY COUNTER
200F
2010 POP H Saved data in stack pointer register to HL regi
ster pair.

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 PUSH H
⚫ The stack pointer is decremented by one to 2098 H
, and the contents of the h register are copied to
memory location 2098H. 8085 Register
F
A
⚫ The stack pointer register is again B C
D E
decremented by one to 2097H,and H 42 F2 L
SP 2097
the contents of the L register are
Memory
copied to memory location 2097H.
⚫ The contents of the register pair F2 2097
42 2098
HL are not destroyed ; however X 2099

HL is made available for delay

counter. Contents on the stack &in the register
after the PUSH instruction
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 POP H
⚫ The contents of the top of the stack location shown by
the stack pointer are copied in the L register and the
stack pointer register is incremented by one to 2098
H. 8085 Register

⚫ The contents of the top of the stack A F

B C
(now it is 2098H) are copied in the D E
H 42 F2 L
H register,and the stack pointer is SP 2099
incremented by one. MEMORY
⚫ The contents of memory location
2097H and 2098 are not destroyed F2 2097
42 2098
until some other data bytes are X 2099

stored in these location. Contents on the stack and in the registers

after the POP instruction
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 Operation of the stack
⚫ During pushing, the stack operates in a “decrement
then store” style.
➢ The stack pointer is decremented first, then the
information is placed on the stack.
⚫ During poping, the stack operates in a “use then
increment” style.
➢ The information is retrieved from the top of the
stack and then the pointer is incremented.
⚫ The SP pointer always points to “the top of the
stack’’.

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 PUSH PSW Register Pair
⚫ PUSH PSW (1 Byte Instruction) A Flag
➢ Decrement SP
➢ Copy the contents of 12 80
register A to the memory
location pointed to by SP
➢ Decrement SP
➢ Copy the contents of
Flag register to the memory FFFB
FFFC
location pointed to by SP
FFFD 80
FFFE 12
FFFF

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 Pop PSW Register Pair
⚫ POP PSW (1 Byte Instruction)
A FLAG
➢ Copy the contents of the memory location pointed to by the SP to Flag
12 80
register
➢ Increment SP

➢ Copy the contents of the

FFFB
memory location pointed to FFFC
by the SP to register A FFFD 80
FFFE 12
➢ Increment SP FFFF

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 Subroutines
⚫ A subroutine is group of instruction written sepa
rately from the main program to perform a func
tion that occurs repeatedly in the main program
.
➢ When a main program calls a subroutine the pro
gram execution is transferred to the subroutine
after the completion of the subroutine ,the prog
ram execution returns to the main program.
➢ The microprocessor uses the stack to store the r
eturn address of the subroutine.

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 Subroutines
⚫ The 8085 has two instructions for dealing
with subroutines.
– The CALL instruction is used to redirect
program execution to the subroutine.
– The RET instruction is used to return to t
he main program at the end of the subro
utine .

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 The CALL instruction
⚫ CALL ,16 bit
➢ Call subroutine in conditionally located at
the memory address specified by the 16
bit operand.
➢ This instruction places the address of the
next instruction on the stack and transfer
the program execution to the subroutine
address.

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 The RET instruction
➢ Return unconditionally from the subrouti
ne.
➢ This instruction locates the return addre
ss on the top of the stack and transfers t
he program execution back to the calling
program.

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 General characteristics of CALL &
RTE instruction
1. The CALL instructions are 3-byte instruc
tion; the second byte specifies the low
order byte ,and the third byte specifies
the high order byte of the subroutine
address.
2. The return instruction are 1-byte instruc
tions.
3. A CALL instruction must be used in
conjunction with a return instruction in
the subroutine .
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Necessary steps to implement a
subroutine

⚫ The stack pointer register must be initiali

zed ,preferably at the highest memory lo
cation of the R/W memory.
⚫ The call instruction should be used in the
main program accompanied by the RET i
nstruction in the subroutine.
Conditional CALL and RTE Instructions
⚫ The 8085 supports conditional CALL and co
nditional RTE instructions.
–The same conditions used with conditional
JUMP instructions can be used.
– CC, call subroutine if Carry flag is set.
– CNC, call subroutine if Carry flag is not set
–RC, return from subroutine if Carry flag is
set
– RNC, return from subroutine if Carry
flag is not set.