HDD + DVD Recorder DVDR3455H

DVDR3455H/55/75/96/97

CLASS 1
LASER PRODUCT

Contents Page Contents Page

1 Technical Specifications and Connection Front: Standby 30
Facilities 2 Layout: Standby (Top View) 30
2 Safety Information, General Notes & Lead Digital: Back-end Processor 31
Free Requirements 4 Digital: Memory 32
3 Directions for Use 6 Digital: IEEE 1394 Physical Layer 33
4 Mechanical Instructions 9 Digital: Video Input Processor 34
5 Firmware Upgrading & Diagnostic Software 12 Digital: Interfaces 35
6 Block Diagrams,Waveforms, Wiring Diagram 15 Layout: Digital-Main Part (Top View) 36
Overall block diagram 15 Layout: Digital-Main Part (Bottom View) 37
Wiring diagram 16 Power Supply Unit: Schematic 38
Waveforms of Analog Board 17 Power Supply Unit: Layout 39
Waveforms of Digital Board 18 8 Circuit- and IC Description 41
Test Point Overview for Analog Board 19 PSU Board 41
Test Point Overview for Digital Board 20 Front Board (Panel – Display + Key) 42
7 Circuit Diagram and PWB Layout 21 Analog Board 42
Analog: Video Input/Output 21 Digital Board 46
Analog: Audio ADC/DAC 22 IC Description 49
Analog: Tuner and Multi-Sound Processor Analog Board 49
(MSP) 23 Digital Board 53
Analog: PSU and Interfaces 24 9 Exploded View & Spare Parts List 62
Layout: Analog-Main Part (Top View) 25 Exploded View of the set 62
Layout: Analog-Main Part (Bottom View) 26 Spare Parts List 63
Front: Front Panel - Display 27 10 Revision list 64
Front: Front Panel - Audio/Video-In 28
Layout: Front Panel (Top Copper Pattern)
- SMD + Components 29
Layout: Front Panel (Bottom Copper Pattern)
- Components 29
©Copyright 2006 Philips Consumer Electronics B.V. Eindhoven, The Netherlands.
All rights reserved. No part of this publication may be reproduced, stored in a
retrieval system or transmitted, in any form or by any means, electronic,
mechanical, photocopying, or otherwise without the prior permission of Philips.

Published by KC-TE 0636 AV Systems Printed in the Netherlands Subject to modification EN 3139 785 32201

Version 1.1
 EN 2 1. 3139 785 3220x Technical Specifications and Connection Facilities

1. Technical Specifications and Connection Facilities

1.1 PCB Locations

Front Board
Digital Board

Analogue Board
PSU

1.2 General: 1.3.5 Video Performance:

Power Supply : 127V /37 Channel 25 / 503,25 MHz,

: 110V - 240V /55 Test pattern: standard test pattern.
: 110V /96 RF Level 74dBμV
: 220V - 240V /75/97 Measured on Cinch Out
Consumption : 25 W (typical) Frequency response : 0.1 - 3.58 MHz -1 ± 3dB
Standby power consumption : <3W
1.3.6 Audio Performance:
1.3 RF Tuner Audio Performance Analogue - HiFi:
Frequency response at Cinch (L+R)
Test equipment: Fluke 54200 TV Signal generator output : 100 Hz - 10 kHz / 0 ±
Test streams: Philips Standard test pattern 3dB
S/N according to DIN 45405, 7, 1967
1.3.1 System and PHILIPS standard test pattern
video signal : ≥ 45dB
NTSC-M
Harmonic distortion (1 kHz, ± 25
1.3.2 RF - Loop Through: kHz deviation) : ≤ 1.5%

Frequency range : 45 - 860 MHz 1.3.7 Tuning

Gain: (ANT IN - ANT OUT) : ≥ -6dB
Radio Interference / max. input Automatic Search Tuning
voltage, at 75Ω, 3 tone method (≤ Scanning time without antenna : typ. 3 min.
-40dB) : no limit Stop level (vision carrier) : ≥ 37dBμV
Maximum tuning error during
1.3.3 Modulator: operation : ± 100 kHz

Video Modulation : 80%±15% Manual Tuning

Frequency response : 0 ± 3dB, 0...4.2MH Manual selection in “STORE” mode
Audio Modulation 1kHz tone : ± 12kHz, tol. ± 4kHz

1.3.4 Receiver:

PLL tuning with AFC for optimum reception

Frequency range : 55 - 805 MHz
Sensitivity at 40 dB S/N : ≤ 60dBμV at 75 Ω
(video unweighted)
 Technical Specifications and Connection Facilities 3139 785 3220x 1. EN 3

1.4 Analogue Inputs / Outputs 1.6 Audio Performance CD

1.4.1 External In (Rear) 1.6.1 Cinch Output Rear

Video - Y/C (Hosiden) Output voltage 2 channel mode : 2Vrms ± 1dB

according IEC 933-5 Channel unbalance (1kHz) : <1dB
Superimposed DC-level on pin 4 (load ≥ 100kΩ): Crosstalk 1kHz : >100dB
< 2.4V is detected as 4:3 aspect ratio Crosstalk 20Hz-20kHz : >87dB
> 3.5V is detected as 16:9 aspect ratio Frequency response 20Hz-20kHz : ±0.2dB max
Signal to noise ratio (A-weighted) : >90dB
Input voltage Y : 1 Vpp ± 3dB Dynamic range 1kHz : >83dB
Input impedance Y : 75 Ω Distortion and noise 1kHz : >83dB
Input voltage C : burst 300 mVpp ± 3dB Distortion and noise 20Hz-20kHz : >75dB
Input impedance C : 75 Ω Intermodulation distortion : >70dB
Mute : >95dB
Video Cinch Outband attenuation: : >40dB above 30kHz
Input voltage : 1 Vpp ± 3dB
Input impedance : 75 Ω 1.7 Digital Output
Audio Cinch 1.7.1 Coaxial
Input voltage : 2.2 Vrms max.
Input impedance : > 10kΩ CDDA / LPCM : according IEC60958
MPEG1, MPEG2, AC3 audio : according IEC61937
1.4.2 Audio/Video Front Input Connectors
DTS : according IEC61937
Audio amendment 1
Input voltage : 2 Vrms max.
Input impedance : > 10kΩ 1.8 Digital Video Input (IEEE 1394)

Video - Cinch 1.8.1 Applicable Standards

Input voltage : 1 Vpp ± 3dB
Implementation according:
Input impedance : 75 Ω
IEEE Std 1394-1995
Video - YC (Hosiden) IEC 61883 - Part 1
according IEC 933-5 IEC 61883 - Part 2 SD-DVCR (02-01-1997)
Superimposed DC-level on pin 4 (load ≥ 100 kΩ): Specification of consumer use digital VCR’s using 6.3 mm
< 2.4V is detected as 4:3 aspect ratio magnetic tape - dec. 1994
> 3.5V is detected as 16:9 aspect ratio Mechanical connection according:
Annex A of 61883-1
Input voltage Y : 1 Vpp ± 3dB
Input impedance Y : 75 Ω 1.9 Dimensions and Weight
Input voltage C : burst 300 mVpp ± 3dB
Input impedance C : 75 Ω Height of feet : 5.5mm
Apparatus tray closed : WxDxH:360x43x322mm
1.4.3 Out 1 Weight without packaging : 3 kg
Weight in packaging : 4 kg
Component Video Cinch Y/Pb/Pr / Progressive Scan
according EIO-770-1-A, EIA-770-2-A 1.10 Laser Output Power & Wavelength
Audio - Cinch 1.10.1 DVD
Output voltage : 2 Vrms max
Output impedance : < 2kΩ Output power during reading : 1.0mW
Output power during writing : 30mW
1.4.4 Out 2 Wavelength : 650nm
Video - Y/C (Hosiden) 1.10.2 CD
Output voltage Y : 1 Vpp ± 3dB
C : burst 300 mVpp ± 1dB Output power : 1.0mW
Output impedance Y, C : 75 Ω Wavelength : 780nm

Video - Cinch 1.11 Write Speed

Output voltage : 1 Vpp ± 1dB
Output impedance : 75 Ω
Type of Disc (Function) Disc Rotation Speed
Audio - Cinch
Output voltage : 2 Vrms max Read Speed CD 7X CAV (25Hz)
Output impedance : < 1kΩ Read Speed DVD 4X CAV (40Hz)
Write Speed DVD+RW 2.4X ZCAV
1.5 Video Performance DVD
Write Speed DVD+R 2.4X ZCAV
All outputs loaded with 75 Ohm
SNR measurements over full bandwidth without weighting.

1.5.1 All Outputs

SNR : > 48dB

Bandwidth : 4.2 MHz - 3dB
 EN 4 2. 3139 785 3220x Safety Information, General Notes & Lead Free Requirements

2. Safety Information, General Notes & Lead Free Requirements

2.1 Safety Instructions 2.2 Warnings

2.1.1 General Safety 2.2.1 General

Safety regulations require that during a repair: • All ICs and many other semiconductors are susceptible to
• Connect the unit to the mains via an isolation transformer. electrostatic discharges (ESD, ). Careless handling
• Replace safety components, indicated by the symbol , during repair can reduce life drastically. Make sure that,
only by components identical to the original ones. Any during repair, you are at the same potential as the mass
other component substitution (other than original type) of the set by a wristband with resistance. Keep
may increase risk of fire or electrical shock hazard. components and tools at this same potential.
Available ESD protection equipment:
Safety regulations require that after a repair, you must return – Complete kit ESD3 (small tablemat, wristband,
the unit in its original condition. Pay, in particular, attention to connection box, extension cable and earth cable)
the following points: 4822 310 10671.
• Route the wires/cables correctly, and fix them with the – Wristband tester 4822 344 13999.
mounted cable clamps. • Be careful during measurements in the live voltage
• Check the insulation of the mains lead for external section. The primary side of the power supply, including
damage. the heatsink, carries live mains voltage when you
• Check the electrical DC resistance between the mains connect the player to the mains (even when the
plug and the secondary side: player is ‘off’!). It is possible to touch copper tracks and/
1. Unplug the mains cord, and connect a wire between or components in this unshielded primary area, when
the two pins of the mains plug. you service the player. Service personnel must take
2. Set the mains switch to the ‘on’ position (keep the precautions to prevent touching this area or components
mains cord unplugged!). in this area. A ‘lightning stroke’ and a stripe-marked
3. Measure the resistance value between the mains printing on the printed wiring board, indicate the primary
plug and the front panel, controls, and chassis side of the power supply.
bottom. • Never replace modules, or components, while the unit is
4. Repair or correct unit when the resistance ‘on’.
measurement is less than 1 MΩ.
5. Verify this, before you return the unit to the customer/ 2.2.2 Laser
user (ref. UL-standard no. 1492).
6. Switch the unit ‘off’, and remove the wire between the • The use of optical instruments with this product, will
two pins of the mains plug. increase eye hazard.
• Only qualified service personnel may remove the cover or
2.1.2 Laser Safety attempt to service this device, due to possible eye injury.
• Repair handling should take place as much as possible
This unit employs a laser. Only qualified service personnel with a disc loaded inside the player.
may remove the cover, or attempt to service this device (due • Text below is placed inside the unit, on the laser cover
to possible eye injury). shield:

Laser Device Unit CAUTION VISIBLE AND INVISIBLE LASER RADIATION WHEN OPEN AVOID EXPOSURE TO BEAM
Type : Semiconductor laser ADVARSEL SYNLIG OG USYNLIG LASERSTRÅLING VED ÅBNING UNDGÅ UDSÆTTELSE FOR STRÅLING
ADVARSEL SYNLIG OG USYNLIG LASERSTRÅLING NÅR DEKSEL ÅPNES UNNGÅ EKSPONERING FOR STRÅLEN
GaAlAs VARNING SYNLIG OCH OSYNLIG LASERSTRÅLNING NÄR DENNA DEL ÄR ÖPPNAD BETRAKTA EJ STRÅLEN
VARO! AVATTAESSA OLET ALTTIINA NÄKYVÄLLE JA NÄKYMÄTTÖMÄLLE LASER SÄTEILYLLE. ÄLÄ KATSO SÄTEESEEN
Wavelength : 650 nm (DVD) VORSICHT SICHTBARE UND UNSICHTBARE LASERSTRAHLUNG WENN ABDECKUNG GEÖFFNET NICHT DEM STRAHL AUSSETSEN
DANGER VISIBLE AND INVISIBLE LASER RADIATION WHEN OPEN AVOID DIRECT EXPOSURE TO BEAM
: 780 nm (VCD/CD) ATTENTION RAYONNEMENT LASER VISIBLE ET INVISIBLE EN CAS D’OUVERTURE EXPOSITION DANGEREUSE AU FAISCEAU

Output Power : 20 mW
(DVD+RW writing) Figure 2-2
: 0.8 mW
(DVD reading) 2.2.3 Notes
: 0.3 mW
(VCD/CD reading) Dolby
Beam divergence : 60 degree Manufactured under licence from Dolby Laboratories. “Dolby”,
“Pro Logic” and the double-D symbol are trademarks of Dolby
Laboratories. Confidential Unpublished Works.
©1992-1997 Dolby Laboratories, Inc. All rights reserved.
CLASS 1
LASER PRODUCT

Figure 2-3
Figure 2-1
Trusurround
TRUSURROUND, SRS and symbol (fig 2-4) are trademarks
Note: Use of controls or adjustments or performance of
of SRS Labs, Inc. TRUSURROUND technology is
procedure other than those specified herein, may result in
manufactured under licence frm SRS labs, Inc.
hazardous radiation exposure. Avoid direct exposure to beam.

Figure 2-4
 Safety Information, General Notes & Lead Free Requirements 3139 785 3220x 2. EN 5

Video Plus Due to lead-free technology some rules have to be respected by the
“Video Plus+” and “PlusCode” are registered trademarks of workshop during a repair:
the Gemstar Development Corporation. The “Video Plus+”
system is manufactured under licence from the Gemstar • Use only lead-free solder alloy Philips SAC305 with order
Development Corporation. code 0622 149 00106. If lead-free solder-pate is required,
please contact the manufacturer of your solder-equipment.
In general use of solder-paste within workshops should be
avoided because paste is not easy to store and to handle.
• Use only adequate solder tools applicable for lead-free
solder alloy. The solder tool must be able
o To reach at least a solder-temperature of 400°C,
o To stabilize the adjusted temperature at the solder-tip
Figure 2-5 o To exchange solder-tips for different applications.
• Adjust your solder tool so that a temperature around 360°C
– 380°C is reached and stabilized at the solder joint.
Macrovision Heating-time of the solder-joint should not exceed ~ 4 sec.
This product incorporates copyright protection technology that Avoid temperatures above 400°C otherwise wear-out of tips
is protected by method claims of certain U.S. patents and will rise drastically and flux-fluid will be destroyed. To avoid
other intellectual property rights owned by Macrovision wear-out of tips switch off un-used equipment, or reduce
Corporation and other rights owners. heat.
Use of this copyright protection technology must be • Mix of lead-free solder alloy / parts with leaded solder alloy
authorized by Macrovision Corporation, and is intended for / parts is possible but PHILIPS recommends strongly to
home and other limited viewing uses only unless otherwise avoid mixed solder alloy types (leaded and lead-free).
authorized by Macrovision Corporation. Reverse engineering If one cannot avoid or does not know whether product is
or disassembly is prohibited. lead-free, clean carefully the solder-joint from old solder
alloy and re-solder with new solder alloy (SAC305).
2.3 Lead Free Requirement • Use only original spare-parts listed in the Service-Manuals.
Not listed standard-material (commodities) has to be
Information about Lead-free produced sets purchased at external companies.
• Special information for BGA-ICs:
Philips CE is starting production of lead-free sets from - always use the 12nc-recognizable soldering temperature
1.1.2005 onwards. profile of the specific BGA (for de-soldering always use the
lead-free temperature profile, in case of doubt)
INDENTIFICATION: - lead free BGA-ICs will be delivered in so-called ‘dry-
packaging’ (sealed pack including a silica gel pack) to
protect the IC against moisture. After opening, dependent
Regardless of special logo (not always indicated)
of MSL-level seen on indicator-label in the bag, the
BGA-IC possibly still has to be baked dry. (MSL=Moisture
One must treat all sets from 1 Jan 2005 onwards, according
Sensitivity Level). This will be communicated via AYS-
next rules.
website.
Example S/N:
Do not re-use BGAs at all.

• For sets produced before 1.1.2005 (except products of

2004), containing leaded solder-alloy and components,
all needed spare-parts will be available till the end of the
service-period. For repair of such sets nothing changes.

• On our website www.atyourservice.ce.Philips.com you

find more information to:

BGA-de-/soldering (+ baking instructions)

Heating-profiles of BGAs and other ICs used in Philips-sets

Bottom line of typeplate gives a 14-digit S/N. Digit 5&6 is the year, digit 7&8 is You will find this and more technical information within the
the week number, so in this case 1991 wk 18 “magazine”, chapter “workshop news”.

So from 0501 onwards = from 1 Jan 2005 onwards

For additional questions please contact your local repair-helpdesk.
Important note: In fact also products of year 2004 must be treated in this way as long as you
avoid mixing solder-alloys (leaded/ lead-free). So best to always use SAC305 and the higher
temperatures belong to this.
 3.
HDD & DVD Player/ Recorder DVDR3455H

EN 6
Connect
Start with the ‘Basic Connection.’
If you have a VCR, follow the instructions for ‘Connection with a VCR or similar device’.
1 3.

Basic Connection Connection with a VCR

www.p4c.philips.com
Quick Start Guide A Before Connecting or similar device
Unplug the antenna cable that is currently connected
to your TV.
A Before Connecting
Your new Philips recorder replaces the VCR for your
recording needs. First, unplug all the connections from
your VCR.

B Connecting B Connecting
Television (rear)
RL
Directions For Use

R
1 Connect R Television (rear)
3139 785 3220x

2 Set up

3 Enjoy
To AC
Philips recorder power
(rear)
VIDEO (CVBS) VIDEO (CVBS) PR COMPONENT Y
INPUT OUTPUT
EXT 1 DVD RECORDER 22F8 VIDEO
L OUT 1 RP
L L
Philips recorder
TV-OUT R
ANTENNA-IN
LISTED
R Complies with 21 CFR
1040.10 and 1040.11
OUT 2 R R
~
To
MAINS
EXT 2 COAXIAL PB
S-VIDEO (Y/C) AUDIO S-VIDEO (Y/C) (DIGITAL AUDIO) OUT 3 AUDIO
(rear)
antenna VIDEO (CVBS) VIDEO (CVBS)
INPUT OUTPUT PR COMPONENT Y
EXT 1 DVD RECORDER 22F8 VIDEO
L OUT 1 L L
RP
TV-OUT R
or set- ANTENNA-IN
LISTED
R Complies with 21 CFR OUT 2 R R
1040.10 and 1040.11
EXT 2 COAXIAL PB
What’s in the box? To antenna top box S-VIDEO (Y/C) AUDIO S-VIDEO (Y/C) (DIGITAL AUDIO) OUT 3 AUDIO

or set-top box
OUTPUT VIDEO (CVBS) PR COMPONENT Y To AC
VIDEO
OUT 1 L power
VIDEO
OUT
OUT 2 L
The following except of the Quick Use Guide serves as an introduction to the set.

R AUDIO
OUT R

S-VIDEO (Y/C) COAXIAL PB

AUDIO
Directions For Use

(DIGITAL AUDIO) OUT 3

VCR or similar device

(rear)
HDD & DVD Player/ Recorder

A Connect the antenna cable to the A Follow the steps 1 to 5 of ‘Connecting’ under
ANTENNA-IN jack on the recorder. ‘Basic Connections’ to connect the recorder
B Use the supplied RF coaxial cable to connect the before you proceed to step 2 below.
TV-OUT jack on this recorder to the B Use a yellow video cable (not supplied) to
Antenna In jack on the TV. connect the VIDEO (CVBS) EXT 1 jack on
C Use the supplied audio/video cable (yellow plug) this recorder to the yellow VIDEO OUT jack on
to connect the VIDEO (CVBS) – OUT1 the VCR.
User jack on this recorder to the VIDEO IN jack on C Use another red and white audio cable (not
Manual the TV. supplied) to connect the AUDIO L/R INPUT
D Use the supplied audio/video cable (red/ white jacks on this recorder to the red and white
plugs) to connect the AUDIO L/R OUTPUT AUDIO OUT jacks on the VCR.
jack on this recorder to the AUDIO IN jacks on D Connect the power cable from your VCR to an
Remote Control Audio/Video Cable the TV. AC power outlet.
RF Coaxial Cable
and 2 batteries E Connect the power cable from the recorder to Note In this setup, the VCR cannot record TV
an AC power outlet. programs.

For additional connection diagrams, see the

accompanying User Manual.
The Complete Direction for the Use can be downloaded in different languages from the internet site of Philips Customer care Center:
 Set up Enjoy
2 3
A Finding the viewing channel B Initial Installation About the Time Shift Buffer Instant Replay
Philips recorder (front panel)
A Press SETUP on the remote control. (TSB) While watching a live TV program, you can press left
W to jump back 10 seconds upon every single press for
SETUP MENU - GENERAL Once you switch on this recorder, the currently instant replay.
selected TV program will be stored in a temporary
Auto Chapter Marker 5min. To return to live broadcast, press and hold right X.
storage called the ‘TSB’ (Time Shift Buffer). The TSB
Record Quality SP can store up to 6 hours of recordings temporarily.
A Press STANDBY-ON on the recorder
Auto Program Search Press DISPLAY once to display the Time
B Turn on the TV. Start Recording
Manual Program Edit Shift video bar.
Note If connected to your VCR, make sure it is
switched off or in standby mode before proceeding. A Before recording to hard disk
(The TSB in playback mode)
Start time Shows TV channel or You can preset the recording quality for content
C Press SETUP . of program video input source recorded to the time shift buffer.
D Press ‘0’ on the TV’s remote control, then press
the Channel Down button repeatedly until you see B Setup and install TV channels. CH003 A Press SETUP on the remote control.
the { SETUP MENU - GENERAL } page. This is Highlight and press right X . B Highlight and press right X .
the correct viewing channel for the recorder. Press down T repeatedly until you highlight Press down T repeatedly until you highlight
{ Auto Program - Search } and press OK . { Record Quality } and press right X.
SETUP MENU - GENERAL A warning message will appear.
Auto Chapter Marker 5min.
C Use up S / down T keys to select the preferred
Record Quality SP
Select OK OK and press OK to proceed. mode of recording quality and press OK to
Auto Program Search
Manual Program Edit 03:15:36 AM 09:15:36 AM confirm.
Highlight { Tuner Input Source }, press
08:30:45 AM
Record Quality Hours of Recording
right X and select a suitable setting: that can be stored
To exit, press [SETUP].
160GB Hard Disk
{ Cable } – if the recorder is connected via a HQ High Quality 34
SP Standard Play 68
cable/satellite box. Program stored TSB Time of current SPP Standard Play Plus 85
{ Air } – if the recorder is connected directly in TSB status icon screen playback LP Long Play 102
to the antenna wall outlet. in playback EP Extended Play 136
Note You may press the AV or SELECT button on SLP Super Long Play 200
Current
the TV’s remote control (if available) to select the OK
Select CONTINUE and press OK to start time SEP Super Extended Play 270
correct viewing channel. See your TV’s user manual. Values are estimates only. Parts of the HDD storage will be
automatic TV channel search. reserved for the operations of this recorder and time shifting.
The contents on the time shift buffer will be erased
Note If no channels were found, check the once you press CH + / - or if you switch to
antenna connection and start the channel search Record to hard disk
another mode: SOURCE , B
Directions For Use

again. A Press TUNER to switch to tuner mode.

USB/DV , DVD REC .
C Select the language. B Press CH + / - to go to the TV program
Highlight and press right X . PAUSE LIVE TV channel you wish to record.
– select the System Language C Press DISPLAY to display the time shift
– select the Audio Language for DVD video bar.
disc playback.
Pause ‘live’ TV
– select the Subtitle Language for DVD disc 03:15:36 AM 09:15:36 AM
At times, you may be interrupted while
playback. watching your favourite program. Now you can LIVE
– select the Disc Menu Language for DVD disc PAUSE it, as if you were in control of the
playback. broadcast. Note To record from a connected external device,
D Set the date and time press SOURCE repeatedly to cycle through
Highlight and press right X. A Press PAUSE LIVE TV while video input sources from:
watching any live TV program to suspend it. { CAM 1 } : VIDEO jack on the front
Select { Date (dd/mm/yy) } or { CAM 2 } : S-VIDEO jack on the front
{ Time (hh:mm:ss) } and press OK . B Press PAUSE LIVE TV to continue.
3139 785 3220x

{ EXT 1 } : VIDEO (CVBS) EXT1 jack on the back

Use the numeric keypad 0 - 9 to input the C To return to live broadcast, press and hold { EXT 2 } : S-VIDEO (Y/C) EXT2 jack on the back
date/time, then press OK to confirm. right X. or Press USB/DV to record from a DV
camcorder connected via the DV IN jack on the
E Press SETUP to finish the installation. To jump forward playback, press right X once for recorder.
every 30 seconds.
D Press REC to start recording.
Your Philips recorder is now ready for use! Note Press REC repeatedly to extend 30
3.

minutes increments per single press.

E To stop recording, press STOP .
EN 7
 EN 8
Enjoy Enjoy
3 3 3.

Inserting discs Start playback Copying to a DVD Types of discs used on this
Philips recorder (front panel) A Playback from hard disk recordable disc recorder
You can copy the contents in your hard disk to a DVD
HDD 10 Titles recordable disc.
No Ch. Date Time Title
001 CH001 05/20/06 02.00 PM Nature A Insert a recordable DVD disc.
A Press OPEN/CLOSEç on the front 002 CH003 05/14/06 04.00 PM News 00:20:20
003 CH009 04/25/06 08.30 PM Drama SP NTSC B Press HDD to view the titles on
of the recorder. 004 CH008 04/30/06 03.30 PM Travel 1. Press [SELECT] to the hard disk.
005 CH002 03/28/06 08.30 PM News mark or unmark
006 CH008 04/12/06 11.00 AM Title 3 recordings.
007 CH002 07/04/06 09.30 PM News 2. Press [HDD] to C Use up S or down T keys to select
copy selected
008 CH011 07/23/06 10.30 PM Discover recordings to DVD.
the title.
For other options, press [DVD], [DV], Press [SHUFFLE] to
[TUNER] keys. Press [RIGHT] to go to sort by title. D Press SELECT to mark the PAUSE LIVE TV
PAUSE LIVE TV edit menu.
titles you wish to copy.
A Press HDD to view the titles on the hard E Once you finish your selection, press
3139 785 3220x

disk. HDD to start copying to the

recordable DVD disc.
B Use up S or down T keys to select the title.
Note When copying is in progress, the
C Highlight the title you want and press to start icon will be shown on the screen.
B Get a DVD disc and place in the tray with the label playback.
F During copying, you can continue watching
facing up.
Note To access the edit menu, highlight the title TV programs in tuner mode or select
C Press OPEN/CLOSEç again to close the and press right X. another HDD title for playback.
tray.
D Press HDD to go back to the HDD menu G Once the copying process completes, the icon
anytime. will no longer be shown.
C Record to a DVD recordable disc
A Press TUNER to switch to tuner mode. Playback from a disc
B
B Press CH + / - to go to the TV program A Insert a CD or DVD disc.
channel you wish to record. If the disc menu does not show, press DVD
C Insert a recordable DVD disc. to view the list of titles on the disc.
Press DVD REC to switch to direct record
Directions For Use

mode and display the information bar. 1. Sports

11 / 05 / 2006
12 : 31 : 53 PM
SP 00 : 03 : 00
System State: Stop
Record to Optical Disc As Standard Play 2. Nature
Elapsed Time: 00:00:00 Remaining Time: 02:00:00 09 / 07 / 2006
03 : 30 : 45 PM
SPP 00 : 05 : 59
Note To record from a connected external device, 3. My movie
press SOURCE repeatedly Empty 05 / 08 / 2006
Need help?
09 : 31 : 53 PM
OR press USB/DV to record from a DV SP 00 : 06 : 45
camcorder connected via the DV IN jack on the Onscreen Helptext
recorder. Press DISPLAY on the remote control for onscreen helptext when using your Philips recorder.
B Use up S or down T keys to scroll through the
D Press SELECT repeatedly to select the list of options and/or titles. User Manual
preferred mode of recording quality. C Highlight the title you want and press to start See the user manual that came with your Philips recorder.
Record Quality Hours of Recording Types of discs for recording playback.
that can be stored
4.7 GB Online
DVD±R/±RW disc D To stop, press STOP .
High Quality HQ 1 Go to www.philips.com/support.
Standard Play SP 2 E Press DVD to go back to the disc menu
Standard Play Plus SPP 2.5
Long Play LP 3
anytime.
Extended Play EP 4
Super Long Play SLP 6
Super Extended Play SEP 8
For more recording and playback options, see the
accompanying User Manual. 2006 © Koninklijke Philips N.V.
E Press REC to start recording. All rights reserved.
F To stop the recording, press STOP .
12 NC 3139 245 24611
 Mechanical Instructions 3139 785 3220x 4. EN 9

4. Mechanical Instructions
Note : The position numbers given here refers to the Exploded view
on chapter 9

4.1 Dismantling of the DVD Tray Cover manually 4.2 Dismantling of the Basic Engine (Drive D4.5
open)
1) Insert a screw-driver into the slot provided at the bottom
of the set and push in the direction as shown in Figure 4-1 1) Remove 7 screws to loosen Top cover 240 .
to unlock before sliding the loader 1001 out. 2) Remove 4 screws to loosen the Basic Engine assembly
1001 as shown in Figure 4-3.

Figure 4-1: Slide out Cover Tray

Figure 4-3: Remove Basic Engine
2) Remove the Cover Tray 110 as shown in Figure 4-2.
3) Basic Engine Service position as shown in Figure 4-4.

Insulation
Sheet

Figure 4-2: Remove Cover Tray

Figure 4-4: Basic Engine Service Position
 EN 10 4. 3139 785 3220x Mechanical Instructions

4.3 Dismantling of Frontboard 4.4 Dismantling of the Digital Board

1) Remove Screws as indicated to detach plate front loader 1) Remove 4 screws to loosen the Digital Board 1013 as
182 from Frame assembly 0920 as shown in Figure 4-5 shown in Figure 4-8.
and also secure Front PCB .

Figure 4-5: Detach Front Panel

2) Service Position of Frontboard as shown in Figure 4-6.

Insulation
Sheet

Figure 4-8: Remove Digital Board Mounting screw

2) Service Position for Digital Board is given in Figure 4-9.

Figure 4-6: Frontboard Service Position

Note: When Assembling back the Frontboard ,please remember

to screw the Board ground connector to the chasis ground for
ESD issue as show in Figure 4-7.

Insulation
Sheet

Figure 4-9: Digital Board Service Position

Figure 4-7: FrontBoard ground to Frame Ground

 Mechanical Instructions 3139 785 3220x 4. EN 11

4.5 Dismantling of the Analogue Board 4.6 Dismantling of the PSU Board
1) Remove screws from the rear panel 230 to detach 1) Remove 3 screws to loosen the PSU Board 1002 as
Analogue Board. shown in Figure 4-11.
2) Service Position of Analogue Board is given in Figure 4-10.

Insulation
Sheet

Figure 4-11: Remove mounting screw of PSU

2) Service position for PSU Board is given in Figure 4-12.

Figure 4-10: Analogue Board Service Position

Insulation
Sheet

Figure 4-12: PSU Board Service Position

 EN 12 5. 3139 785 3220x Firmware Upgrading & Diagnostic Software

5. Firmware Upgrading & Diagnostic Software

5.1 Firmware Upgrading
A. Preparation to upgrade firmware:
1. Unzip the zip-archive file
2. Start the CD Burning software and create a new CD project (data disc) with the following settings:
File system: Joliet
Format: MODE 2: CDROM XA
Recording mode: SINGLE SESSION (TRACK-AT-ONCE), FINALIZED CD

Note: Long file name is necessary for the preparation of the upgrade disc

3. Place the content of the zip-archive into the root directory of the new CD project.
4. Burn the data onto a blank CDR or CD-RW

B. Procedure to apply the firmware upgrade:

1. Open the tray and load the Upgrade CDROM.
2. The tray closes and set will display:

“FLASH1”

3. The OSD will display

“Software Upgrade Disc detected. Select OK to start upgrading or CANCEL to exit.”

4. Click on the <OK> button.

5. The set will display:

“Upgrading Software . Please Wait . Do not switch off the power . ”

It will do the Upgrade for the loader and OSD will show .

“Loader Software Upgrade

Loader Software Upgrading . Please Wait .Do not switch off the power.”

The whole process takes less than 5 minutes

Note: Do not press any button or interrupt the mains supply during the upgrading process, otherwise the set may becomes defective

6. When the upgrade is completed the tray will open automatically and the set will display:

“Loader Upgrade process has completed successfully . Press <OK> to reboot system.”

7. The tray open and the set will display:

“DRV OK”

8. Press <OK> and the set goes to standby .

*Note : 1) The content of the HDD(i.e. the video recording(s) and/or mp3 file(s)) will not be erased during the firmware
upgrading process.
 Firmware Upgrading & Diagnostic Software 3139 785 3220x 5. EN 13

5.2 Preparations for new HDD

If the defects is due to a faulty HDD, steps must be taken to replace the set with a new HDD . The
procedure below show the steps taken to prepare a new HDD for use on the set.

1. Replace the Faulty HDD with a new HDD.

2. Before connecting the new HDD on the Digital Board ,the jumper pin at the connector of the HDD is to be removed.
3. Connect the new HDD to the Digital Board.
4. Power up the set . It will open the tray and prompt to load the upgrading disc.(the upgrade disc is
the same disc under firmware upgrading.)
5. The set will display

“Load”.

6. Put the upgrade disc and close the tray and the set will show

“Copy” ……… “Boot”

7. The rest of the procedure follows the software upgrade given in 1B -Procedure to apply the firmware upgrade.

*Note :1) Do not press any button or interrupt the main supply, otherwise the set may become defective.
2) When the HDD formatting is successful, the set will go to standby mode.

5.3 Verification of Firmware

How to read out the firmware version to confirm set has been upgraded:
1. Power up the set
2. Press <setup> <3> <2> <1> in the correct sequence
3. Press <select> button
4. The TV connected to the set will display:

BUILD :B5019V04/Date:May 10 2006

Loader Version : 45.04.05.04
Macrovision Version :
MPEG Chip ID:
Audio DAC:
Region Num:1
Developer:Philips PS3455H 55 R19.04
YesDVD Version :YR.2.1.2.30306

5. Press <Setup> button to exit.

 EN 14 5. 3139 785 3220x Firmware Upgrading & Diagnostic Software

Notes:
 Block Diagrams, Waveforms, Wiring Diagram. 3139 785 3220x 6. EN 15

6. Block Diagrams, Waveforms, Wiring Diagram

Overall Block Diagram of the Set

Front Keyboards 1201

ANALOG BOARD
CONTROL LINES CONTROL AND COMMUNICATION LINES

1300 9
DV-IN AR
7
AL
5
CVBSFIN
4
AUDIO L
3
CONTROL UNIT SLAVE CFIN
2
MICROPROCESSOR 1
YFIN
UPD 16316GB007-8ET
UPD 16316GB-006 AUDIO R
1107
1219 CONTROL LINES SCK,D_FM,D_HOST,RDY_FM,ATN_FM,HOST_RESET
CVBS

1102
ANALOG AUDIO / VIDEO 7
AINFR
S-VIDEO 9
AINFL
11
CVBSFIN
12
13
CFIN
14
1511
15
YFIN

1551
DIGITAL BOARD INPUT/OUTPUT
PROCESSING &
SOURCE
1109
SELECTION
CVBS

2Mbyte
1205
USB (1502) AUDIO L/R IN-EXT
PHY FLASH VOA_CVBS
D_CVBS
12
VOA_SC
D_C
14
D_Y
VOA_SY
16
18
D_VR
VOA_RPR S-VIDEO
1522 20
VOA_GY
VOA_BPb
22

VIA_GY Br
Y
1
VIA_BPb
3
ANALOG VIDEO 5
VIA_RPr Pb
VIA_SC_FR
7
VIA_SY_FR

DVD+RW ENGINE D4.5

9
VIA_CVBS_FR Pr
DIG.VIDEO VIDEO INPUT 10
18
VIA_CVBS_TU OUT1
1600-1 1571 12
VIA_SC_RE

PROCESSING VIA_SY_RE 7203

DOMINO DMN-8652 1536 AUD_BCKI
14
AUDIO L/R
2
MPEG 2, AC3 CODEC 3 AUD_WCKI
ADC
DIGITAL AUDIO 5 AUD_DAT(0)) 1600
7 AUD_MCKI AUDIO ENCODER I2S
TRAY CONTROL IDE BUS IDE BUS DIGITAL AUDIO
40 7206
AUD_BCK0
9
AUD_WCK0
11

SERVO 12 AUD_DAT[0] DAC

14 AUD_MCK0 AUDIO PCM I2S
AUD_MUTE
DISC 18
16 AUD_SPDIF0 POWER_FAIL
LASER I2C
READ 1405
IDE BUS

DDRAM OR CVBS
EEPROM
WRITE
16MbyteX2 2Kbyte A_KILL OUT 2
+12V AUDIO L/R
GND

GND
1671 RS232 1111 VIA_CVBS_TU
S-VIDEO
+5V
SERVICE 12V_STBY
GND_D
5V_STBY
3V3_STBY
GND_D
J1
1402 RF IN - ANTENNA
TUNER
12V_STBY

3V3_STBY
POWER SUPPLY UNIT 5V_STBY BUFFER
HARD DISK
GND_D

GND_D
IDE BUS RF OUT - TV
40 (LOOP THROUGH)
1404

VGN_STBY
VGN_STBY
5N_STBY
DIGITAL AUDIO OUT
5N_STBY J2
GND_A GND_A
IPFAIL IPFAIL
GND_A GND_A
12VA_STBY 12VA_STBY
+12V

GND

GND

+5V

FAN

1406
1112

+12V
+12VH

GND

GND
+5VH

+5V
GND
GND
 Block Diagrams, Waveforms, Wiring Diagram. 3139 785 3220x 6. EN 16

Wiring Diagram

DVDR3455H
Wiring diagram ver 2.0

Analog board PSU

not in layout 8000
FAN1 FAN2 Fan1 Fan2 Mains TBC mm
EH 2.5mm EH 2.5mm (option) VH 7.6mm
1 FAN1P 1 FAN2P 1 MAINS_L
2 FAN1N 2 FAN2N 2 MAINS_N
2p 2p 2p
8013
PSA 180 mm PSA
ANA PH 2mm PH 2mm
1 VGN_STBY 1 VGN_STBY
2 5N_STBY 2 5N_STBY
3 GND_A 3 GND_A
4 IPFAIL 4 IPFAIL
5 GND_A 5 GND_A
6 12VA_STBY 6 12VA_STBY
6p 6p
8012
PS STBY 180mm PS STBY
SDN 3.96mm SDN 3.96mm
1 12V_STBY 1 12V_STBY
2 GND_D 2 GND_D
3 5_STBY 3 5_STBY
4 3V3_STBY 4 3V3_STBY
5 GND_D 5 GND_D
5p 5p

PS DRV
EH 2.5mm
1 12VE
2 GND
3 GND
4 5VE

4p
8006
FAV FCOM COM AIO VIO1 / VIO2 DIG_PS PS HDD 120 mm
FFC 1mm FFC 1mm FFC 1mm FFC 1mm FFC 1mm PH 2mm EH 2.5mm
6 9 FAURIN 14 12Vstby 17 19 GND 18 24 GND 24 30 DB_PB 1 3V3D 1 12VH
5 8 GND 13 VGN_STBY 16 18 SCL0 17 23 ABCK 23 29 GND 2 3V3D 2 GND
4 7 FAULIN 12 PWRFAIL 15 17 SDA0 16 22 AWCK 22 28 DG_Y 3 3V3D 3 GND
3 6 GND 11 PWRCTL 14 16 RDY_FM 15 21 GND 21 27 GND 4 3V3D 4 5VH
2 5 FCVBSIN 10 5VSTBY 13 15 D_FM 14 20 ADA0 20 26 DR_PR 5 GND
1 4 GND 9 RC - NC 12 14 D_HOST 13 19 GND 19 25 GND 6 12VD
3 FCIN 8 HOSTRST 11 13 GND 12 18 AMCK 18 24 DY 7 GND
2 GND 7 ATN_FM 10 12 FPSCK 11 17 GND 17 23 GND 8 GND
1 FYIN 6 RDY_FM 9 11 ATN_FM 10 16 DBCK 16 22 DC 9 5VD
5 GND 8 10 HOSTRST 9 15 GND 15 21 GND 10 HDD_ON
4 D_HOST 7 9 AINSW0 8 14 DWCK 14 20 DCVBS 11 GND
3 D_FM 6 8 AINSW1 7 13 DDA0 13 19 GND 12 GND
2 FPSCK 5 7 FB_SCRT 6 12 GND 12 18 TUCVBS
1 GND 4 6 8SC2_1 5 11 DMCK 11 17 GND
3 5 8SC2_2 4 10 GND 10 16 RCVBSIN
2 4 GND or YUV SW * 3 9 SPDIFO 9 15 GND
1 3 tun_det 2 8 GND 8 14 RYIN
2 HDMI_INT 1 7 AMUTE 7 13 GND
1 fan_on 6 GND 6 12 RCIN
5 DDA3 5 11 GND
4 GND 4 10 FCVBSIN
3 DDA2 3 9 FCIN
2 GND 2 8 GND
1 DDA3 1 7 FYIN
6 GND
24P not in rec 5 AR_PR
layout 4 GND
3 AB_PB
2 GND
1 AG_Y
9p 14p 19p 18p / 24p 24p / 30p 12p 4p

8011 8008 8004 8003 8005 8002

280 mm 280 mm 180 mm 180 mm 140 mm 220mm

Front board Digital board HDD 8007

8010 220 mm
FAV FCOM COM AIO VIO1 / VIO2 DIG_PS HDD_IDE 280 mm HDD_IDE
FFC 1mm FFC 1mm FFC 1mm FFC 1mm FFC 1mm PH 2mm IDE 2.54mm IDE 2.54mm
9 FYIN 1 12V 1 GND 1 GND 1 DB_PB 1 3V3D 1 RSTN 21 DMARQ 1 RSTN 21 DMARQ
8 GND 2 VGNSTBY 2 SCL0 2 ABCK 2 GND 2 3V3D 2 GND 22 GND 2 GND 22 GND
7 FCIN 3 PWRFAIL 3 SDA0 3 AWCK 3 DG_Y 3 3V3D 3 DD[7] 23 DIOWN 3 DD[7] 23 DIOWN
6 GND 4 STBY 4 RDY_FM 4 GND 4 GND 4 3V3D 4 DD[8] 24 GND 4 DD[8] 24 GND
5 FCVBSIN 5 5V 5 D_FM 5 ADA0 5 DR_PR 5 GND 5 DD[6] 25 DIORN 5 DD[6] 25 DIORN
4 GND 6 GND 6 D_HOST 6 GND 6 GND 6 12VD 6 DD[9] 26 GND 6 DD[9] 26 GND
3 FAULIN 7 HOSTRST 7 GND 7 AMCK 7 DY 7 GND 7 DD[5] 27 IORDY 7 DD[5] 27 IORDY
2 GND 8 ATN_MCU 8 FPSCK 8 GND 8 GND 8 GND 8 DD[10] 28 CSEL 8 DD[10] 28 CSEL
1 FAURIN 9 RDY_MCU 9 ATN_FM 9 DBCK 9 DC 9 5VD 9 DD[4] 29 DMACKN 9 DD[4] 29 DMACKN
10 GND 10 HOSTRST 10 GND 10 GND 10 HDD_ON * 10 DD[11] 30 GND 10 DD[11] 30 GND in 3455H IN 3380
11 D_HOST 11 AINSW0 11 DWCK 11 DCVBS 11 GND 11 DD[3] 31 INTRQ 11 DD[3] 31 INTRQ in wiring diag digi bd ana bd
12 D_MCU 12 AINSW1 12 DDA0 12 GND 12 NC 12 DD[12] 32 IOCS16 12 DD[12] 32 IOCS16 DIG_PS DIG_PS DIG_PS
13 SCK 13 FB_SCRT 13 GND 13 TUCVBS 13 DD[2] 33 DA1 13 DD[2] 33 DA1 PH 2mm PH 2mm PH 2mm
14 GND 14 8SC2_1 14 DMCK 14 GND * nc for DVDR3380 14 DD[13] 34 PDIAGN 14 DD[13] 34 PDIAGN 1 3V3D 1 3V3D 1 3V3D
15 8SC2_2 15 GND 15 RCVBSIN 15 DD[1] 35 DA0 15 DD[1] 35 DA0 2 3V3D 2 3V3D 2 3V3D
16 GND or YUV SW * 16 SPDIFO 16 GND 16 DD[14] 36 DA2 16 DD[14] 36 DA2 3 3V3D 3 3V3D 3 3V3D
17 tun_det 17 GND 17 RYIN 17 DD[0] 37 CS0N 17 DD[0] 37 CS0N 4 3V3D 4 3V3D 4 3V3D
18 HDMI_INT 18 AMUTE 18 GND 18 DD[15] 38 CS1N 18 DD[15] 38 CS1N 5 GND 5 GND 5 GND
19 fan_on 19 GND 19 RCIN 19 GND 39 DASPN 19 GND 39 DASPN 6 12VD 6 12VD 6 12VD
20 DDA3 20 GND 20 Keypin 40 GND 20 Keypin 40 GND 7 GND 7 GND 7 GND
21 GND 21 FCVBSIN 8 GND 8 GND 8 GND
* stuffing opt 22 DDA2 22 FCIN 9 5VD 9 5VD 9 5VD
23 GND 23 GND 10 HDD_ON 10 HDD_ON 10 NC
24 DDA3 24 FYIN 11 GND 11 GND 11 GND
25 GND 12 GND 12 NC 12 NC
26 AR_PR
27 GND
28 AB_PB
29 GND
30 AG_Y
9p 14p 19p 18p / 24p 24p / 30p 12p 40p 40p
1401
USB 180 mm USB HDD_PS

FRONT PH 2mm PH 2mm IDE_PSU

1 USB5V 1 USB5V 1 12VH
2 USBP 2 USBP 2 GND
3 USBM 3 USBM 3 GND
4 GND 4 GND 4 5VH
4p 4p 4p

1501
STBY IEEE1394 180 mm IEEE1394
DIPMATE PH 2mm PH 2mm
1 KEY1 1 TPBN 1 TPBN
2 KEY2 2 TPB 2 TPB
3 GND 3 GND
4 TPAN 4 TPAN
5 TPA 5 TPA
6 GND 6 GND

2p 6p 6p DIGI
ODD
8009
8100 ODD_IDE 220 mm ODD_IDE
220 mm IDE 2.54mm IDE 2.54mm
1 RSTN 21 DMARQ 1 RSTN 21 DMARQ
2 GND 22 GND 2 GND 22 GND
3 DD[7] 23 DIOWN 3 DD[7] 23 DIOWN
4 DD[8] 24 GND 4 DD[8] 24 GND
5 DD[6] 25 DIORN 5 DD[6] 25 DIORN
6 DD[9] 26 GND 6 DD[9] 26 GND
7 DD[5] 27 IORDY 7 DD[5] 27 IORDY
8 DD[10] 28 CSEL 8 DD[10] 28 CSEL
9 DD[4] 29 DMACKN 9 DD[4] 29 DMACKN
10 DD[11] 30 GND 10 DD[11] 30 GND
11 DD[3] 31 INTRQ 11 DD[3] 31 INTRQ
12 DD[12] 32 IOCS16 12 DD[12] 32 IOCS16
13 DD[2] 33 DA1 13 DD[2] 33 DA1
14 DD[13] 34 PDIAGN 14 DD[13] 34 PDIAGN
15 DD[1] 35 DA0 15 DD[1] 35 DA0
16 DD[14] 36 DA2 16 DD[14] 36 DA2
17 DD[0] 37 CS0N 17 DD[0] 37 CS0N
18 DD[15] 38 CS1N 18 DD[15] 38 CS1N
19 GND 39 DASPN 19 GND 39 DASPN
20 Keypin 40 GND 20 Keypin 40 GND
40p 40p
Standby board

STBY PS ODD
DIPMATE IDE_PSU
1 KEY1 1 12VE
2 KEY2 2 GND
3 GND
4 5VE
2p 4p
 Block Diagrams, Waveforms, Wiring Diagram. 3139 785 3220x 6. EN 17

Waveforms

Waveforms of Analog Board

I143 Y_OUT I142 C_OUT I144 CVBS_OUT I137 D_C

I138 D_Y I139 D_VR I140 D_YG I141 D_UB

I213 AIA_R_RE1/AIA_R_RE2 I212/I214 I241 ALDAC (PIN 18 7206) I242 (PIN 15 7206)

I150 DIGITAL_OUT 7304MSP XTAL_IN 7304MSP XTAL_OUT

 Block Diagrams, Waveforms, Wiring Diagram. 3139 785 3220x 6. EN 18

Waveforms of Digital Board

AUD_BCKI T537 AUD_BCKO T541 AUD_DAI(0) T539 AUD_DAO(0) T543

AUD_MCKI T540 AUD_MCKO T544 AUD_WCKI T538 AUD_WCKO T542

VOA_BPb T518 VOA_GY T520 VOA_RPr T521 VOA_SY T522

VOA_SC T523 VOA_CVBS T524

 Block Diagrams, Waveforms, Wiring Diagram. 3139 785 3220x 6. EN 19

Test Points Overview for Analog Board

3380_APAC_TPOINT.pdf 2006-05-03
 Block Diagrams, Waveforms, Wiring Diagram. 3139 785 3220x 6. EN 20

Test Points Overview for Digital Board

DVDR3455D_TestPoint.pdf 2006-05-25
 Circuit Diagrams and PWB Layouts 3139 785 3220x 7. EN 21

7. Circuit Diagrams and PWB Layouts

Analog: Video Input/Output

1111-A D2 I126 H6
1 2 3 4 5 6 7 8 9 10 11 12 13 14 1111-B C2 I127 H6
1111-C E2 I128 H6
1112 F2 I129 H6
1113 G2 I130 H7
1114 F2 I131 H7
1121 I6 I132 H7
1122 I6 I133 H7
1131-1 H13 I134 H7

A Video input / output A

1131-2 F13
1132-A C13
1132-B B13
1132-C D13
2101 B4
I135 H7
I136 H7
I137 H7
I138 H8
I139 H8
2102 B4 I140 H8
2103 B6 I141 H8
5V_V 2104 B6 I142 D12
5VN 5VN_V 5V 5V_V 2111 C3 I143 D12
5101 I102 5102 I103 2131 2112 E3 I144 B12
7111 2113 E3 I145 H13
10u 10u BC847BW 100n 2114 E4 I146 F13

10u 16V
10u 16V
GND 2115 I3 I147 H13

2101

2102

10 0n

2103

2104

100n
VOA_CVBS 3121 2116 I3 I148 H13
B 150R 1132-B
B 2117 I3 I149 F2

1%
MSP-801V1-02-01-B NI FE LF 2121 C5 I150 F13
4121 V0_CVBS I144
6 2131 B10 I151 E13
GND GND

160R
2132 C10

3122
CVBS out

330R
3123
7 2133 C11

100p
2134 D11
2132 GND 2135 D11
2121 1u0 VIA_CVBS_TU 2136 E9
Tuner in TUN_CVBS
GND
100n
GND
2137 E9

2151
2138 F11
5VN_V
2139 F11
5V_V
2140 G9
C 1111-B 2133
1132-A
MSP-801V1-02-01-B NI FE LF
C 2141 H9
2142 H11
MSP-801V1-02-01-B NI FE LF I111 RE_CVBS_IN GND
4111 VIA_CVBS_RE 2143 I11
6 100n GND 2151 C12
Rear CVBS in

5
330R
3124
RES 2152 D12
75R 1%
2111
1 00p

7
2153 D12
3111

7112 2134 2
BC857BW 4122 VO_SC I142 2154 G12
VOA_SC 3125
4 C 2155 I12
100n VO_SY I143 Y/C out 2156 I12
150R
3 Y 3111 D4

BZX384-C12

BZX384-C12
160R 1%
GND GND 3112 E4

6122
6121
1

3126
3113 E4
D 2135 D

100p

100p
1111-A 3114 I4
GND
MSP-801V1-02-01-B NI FE LF 3115 I4
100n
GND 3116 I4

BZX384-C12

BZX384-C12
1
3121 B9

2152
2153
5V_V

6123

6124
1132-C
3 I112 RE_SY_IN 4112 VIA_SY_RE GND 5VN_V MSP-801V1-02-01-B NI FE LF 3122 B8
Rear YC in Y I113 RE_SC_IN VIA_SC_RE 7113 2136 GND
3123 B9
4 4115 3124 C11
C BC847BW

8
100n I151 3125 D10
BZX384-C12

BZX384-C12
6111

6112

2 GND
VOA_SY 3127 3126 D10
75R 1%

GND 3127 E9
3112
100p

100p

150R 4123 GND

3128 E8
5

E E 3129 E9
75R 1%
BZX384-C12

BZX384-C12

3113

160R 1%
3130 F10
1u0
2112

2113

3131 F10

330R
6113

6114

3128

3129
1111-C
3132 F11
2114

MSP-801V1-02-01-B NI FE LF 3133 G9
2137 5V_V
GND 3134 H8
100n 3135 H9
8

I149 GND GND GND 7114 2138 1131-2 3136 I10

GND 5VN_V MSD-244V-88 NI FE LF 3137 H10
BC847BW RED_BLACK
100n 6 3138 I11
GND VOA_RPr 3130 GND GND
DIGITAL_AUDIO 4111 C5
I150 5
150R Digital out - Black 4112 D5
F 4124 I146 4
Pr out - Red
F 4113 G5
4114 G5
1114

160R 1%
1112
HLW6S-2D7LF HLW9S-2C7 4115 E5

330R
3131

3132
4116 G5
I114 AIA_R_FR

100p
6 9 4117 H5
5 8 I115 AIA_L_FR 2139 4118 H5
4 7
Front A/V in 3 6
4119 H5
I116 FR_CVBS_IN 4113 VIA_CVBS_FR 100n 4121 B11

2154
2 5 5V_V GND
1 4 GND 4122 D11
I117 FR_SC_IN 4116 VIA_SC_FR 5VN_V
3 4123 E9
2 I118 FR_SY_IN VIA_SY_FR 7115 2140 4124 F11
4114
1 BC847BW 4125 G9
G I119
VOA_GY 3133
100n
GND GND
G 4126 H11
5101 B4
GND 150R 5102 B6
4125 6111 E3
6112 E4
Rear YUV in
160R 1%
1113
LPR6520-P910F 6113 E3

330R
3134

3135
1 6114 E4
VIA_RPr 6121 D12
2 I120 RE_Pr_IN 4117 2141 1131-1 6122 D12
3 RE_Pb_IN 4118 VIA_BPb 5V_V GREEN_BLUE 6123 D11
100n MSD-244V-88 NI FE LF 6124 D12
I123 RE_Y_IN 4119 VIA_GY GND VO_Y I145
H 4
GND 5VN_V 7116
2142
I148
1 Y out - Green H 7111 B9
7112 C10
5 BC847BW VO_Pb
100n 3 Pb out - Blue 7113 E9
6 I121 VOA_BPb 3137 GND I147 7114 F10
150R 2 7115 G9
I124
I125
I126

I127
I128

I129
I13 0
I131
I132

I133
I134

I13 5
I13 6

I137
I138

I139
I140

I1 41
75 R

75 R

75R

100p
100p

100p

100p

7116 H10

100p
4126

160R 1%
I102 B5
GND I103 B7

3136
GND

2155

2156
2115

2116

2117

330R
I111 C2

3138
HLW30S-2C7

GND
3114

3115

3116

I112 D3
1121

2143 I113 E3
I114 F3
I I
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30

100n I115 F3
GND GND I116 G3
GND GND 5VN_V GND
I117 G3
HLW24S-2C7

#0: Not used I118 G3

1122

I119 G3
#4: Used for 3400 I120 H2
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24

I121 H2
#8: Used for 3380 and 3390 from / to Digital Board I123 H2
I124 H2
3139_243_33332_130_1_a2.pdf 2006-03-01
I125 H6

1 2 3 4 5 6 7 8 9 10 11 12 13 14
 Circuit Diagrams and PWB Layouts 3139 785 3220x 7. EN 22

Analog: Audio ADC/DAC

1201 D2 3253 I9
1 2 3 4 5 6 7 8 9 10 11 12 13 1202 C2 3254 I9
1203 F1 3260 I3
1205 E12 3261 H3
2201 D3 3262 I4
2202 D3 3263 I5

Audio ADC / DAC

2203 D3 3264 I5
2204 D3 3265 B11
A A 2205 C4
2206 C4
5201 B2
5202 B3
2207 C4 5203 B5
2208 C4 5211 B11
2209 C4 5212 E5
2210 D4 6201 I7
3V3_A 2211 D4 6202 F9
2212 D4 6203 H9
5V 5V_A 3V3 3V3_A 5VN 5VN_A 2231 B7 6204 F10
2232 C7 6205 G10

5211

100u
5201 I201 5202 I202 5203 I203 2233 D7 7201 C7
10u 10u 10u 2234 D7 7202-1 D8
B B
10 0 n

100n

100n
2235 B9 7202-2 C8

10u 16V

10u 16V

10u 16V
2236 B9 7203 C12

2295
2291

2293

22R
3265
5V_A 3V3_A 2237 C9 7204 F2
22 92 2238 C9 7205 F3

2294

2296
5V_A
2235 47u 6.3V
2241 C9 7206 G5
2231 47u 6.3V
2236 100n
2242 D9 7207 F9
GND GND GND 2232 2243 D10 7208 F10
100n

1m0 6.3V
7201
2244 D10 7209 G9

47K

2247

100n
2245

2246

100n
HEF4052B GND

16
GND 7202-2
2245 C11 7210 G10
10 VDD 8 2246 C11 7211 H7
Audio input analog (AIA) RSA2 0 0

16
1202 9 4X 5 LM833

9
2205 1u0 RSA1 1 3 2241 3213 2247 C12 7212 H8
LPR6520-J440G AIA_R_MSP NULL 7 VDDA VRP VDDD
Φ 2251 F2 7214 H4

3215
C C

3211

1K0
2422 026 05462 6 6
1u0 G4 47u 6.3V 10K 24-BIT AUDIO GND 2252 F3 I201 B2
I211 AIA_L_RE2 AIA_R_RE2 2206
GND GND
5 12
MDX 4 8 ADC 2253 F4 I202 B4
0 SYSCLK
Rear audio in 2 I212 AIA_R_RE2 AIA_R_RE1 2207 1u0 14 13 2254 E4 I203 B5
1 2237 47u 6.3V AID_DAT

Audio input / output digital (AIOD)

4 15 3 13 2255 F4 I204 F4
2 VINR DATAO
I215 AIA_R_FR 2208 1u0 11
6
3 2238 100n 2256 F5 I205 F5
7203
I213 AIA_L_RE1 AIA_L_MSP 2209 1u0 1 2 2257 F5 I206 D11
0 VREF UDA1361TS
2 5
1
3 11 AID_BCK 2258 F6 I211 C2
2210 1u0 GND BCK
I214 AIA_R_RE1 AIA_L_RE2 2
2 5VN_A 2259 F6 I212 C2
1 4 1 2260 F6
3 VINL I213 C2
AIA_L_RE1 2211 1u0 VEE VSS
2261 G6 I214 D2

47u 6.3V
AID_WCK

GN D
3

8
5V_A 6 12
100p

100p

100p

100p

3212

1 K0
2212 1u0 GND
SFOR WS 2262 G3 I215 C2

100n
AIA_L_FR
D 1201
D

100K

100K

100K
100K

100K
100K

100K

100K
7202-1
7 2263 G3 I221 G1
LPR6520-J920G PWON
8 2264 G3 I222 G1
2233 47u 6.3V LM833 I206
2201

2202

2203

2204

2422 026 05383 3 14 2265 G3 I223 G1

2242 3214 MSSEL

3216
1

47K
NULL

2 243

2 244
2234 100n 2266 G4 I224 G1

3217
1 2 VSSA VRN VSSD

1K0
3205

3208
3201

3202

3203

3204

3206

3207
47u 6.3V 10K 2271 F8 I225 G1

15

10
Rear audio in 1
3 4 2272 F8 I226 G1
GND
2273 G8 I227 G1
2 GND GND 5VN_A 2274 G8 I228 G1
GND GND GND GND
5VN_A 2275 F11 I229 G1
GND
AID_MCK 2276 G11 I230 H1
2281 H4 I231 H1
2282 I5 I241 F12
E 12V
3V3_A
E 2283 I6 I242 F12
2284 I8 I243 F12
2291 B2
2292 B2
5212

22u

2293 B3
1205
3224

3K9

2254 100u 6.3V LPR6520-J440G 2294 B4

7205 3249
2271 3241 I241 2295 B5
3V3_A
7204
BC847BW 3
3223
2 BC807-25W

16V 22u 680R 100R

5 Audio-L out 2296 B5
2255 I242 3201 D5
3229

1 100n 5VSTBY
4R7

3221 I204
Audio-R out

2272
1K0

3242
1 4 3202 D5

15K
GND

1n0
2258 47u 16V

100p
3 I243
100n

7207 7208 3203 D5

10K

4K7
100n

2 I205 2256 100n BC857BW BC817-25W 6

3204 D5
F F
47u 16V

3
2259 22n 3246 1 3205 D6
3V3_A 2

2275
3206 D6
3222

2251

2252

2253

2257 GND 6204 1K0

2 1 3207 D6
2260 16V 47u AMUTEC 3245
GND 3208 D6
100n 6202 BAS316
11

17

20

GND 3
5

2K2 3211 C8
1203 VA VA_H VD VL
GND BAS316 GND
HLW18S-2C7 2261 100n 3212 D8
Φ GND
I221 GND
3213 C9
18 3231 22R 192 kHz DAC 2273 3243 3250
I222 AID_BCK AOD_DAT 1 12 3214 D9
17 SDIN VBIAS
I223 3232 22R AID_WCK AOD_BCK 2 13
680R 3215 C10
16 SCLK VQ GND 16V 22u 100R
AOD_WCK 3 19 5VSTBY
15
I224 3233 22R LRCK AMUTEC 3216 D10

3244

2274
AID_DAT AOD_MCK 4 14

15K

1n0
14 MCLK 7206 BMUTEC 3217 D11

100p
10 18 7209
13 RST AOUTA
G I225 3234 22R AID_MCK 8 CS4351 15
G 3221 F1
from/to Digital Board

12 3V3_A 3225 100K DIF0 AOUTB BC857BW

11 SDA DEM
9 7210 3222 F1
33p

33p

33p
33p

I226 3235 22R

3226

AOD_BCK
10K

BC817-25W 3223 F2

2276
10 CDIN AD0 3
7
9
I227 3236 22R DIF1 CS GND 6205 3248 1 3224 E3
3228

AOD_WCK
10K

8 SCL
2263

2264

2265
2262

I228 3237 22R BMUTEC 3247 3225 G4

2266

3227

AOD_DAT
10K
4u7

7 CCLK BAS316 1K0

2K2 2 3226 G4
6 3238 22R GND
I229 AOD_MCK
GND 3227 G4
5 6203
6

16

4 3239 22R GND 3228 G6

I230 AOD_SPDIF 5V_A 5VSTBY
GND
3 GND 3251 3252 BAS316 3229 F5
2 GND GND GND 7212 3231 G2
I231 AIO_MUTE 4K7 22K
1 PDTA124EU 3232 G2
Audio input / output digital (AIOD)

7211 2 3233 G2
H GND
AIO_MUTE PDTC124EU 3
1
H 3234 G2
1 AKILL
3235 G2
5V 3 3236 G2

22K
3261 470R 2281 100n 3237 G2

100K
2

22n
3238 G2
7214 GND
3239 H2
74LVC1G125GW
5

2284

3253
3241 F8

3254
AOD_SPDIF 3260 1K0 2
4 3262 2282 8n2 3263 120R DIGITAL_AUDIO 6201 BAS316 3242 F8
1 POWER_FAIL
3243 G8
EN 75R
150R

5VN_A
390p

GND 3244 G8
3

3245 F9
3246 F10
I I
3264

2283

3247 G9
3248 G10
3249 F11
3250 G11
3139_243_33332_130_2_a2.pdf 2006-03-01 3251 H7
3252 H7

1 2 3 4 5 6 7 8 9 10 11 12 13
 Circuit Diagrams and PWB Layouts 3139 785 3220x 7. EN 23

Analog: Tuner and Multi-Sound Processor (MSP)

1301 G12
1 2 3 4 5 6 7 8 9 10 11 12 13 1302 D1
1303 D1
2301 C3
2302 C3
2303 C4
2304 C4
2310 E2
2311 E2

Tuner and multi sound processor (MSP)

2312 E3
A A 2313 E3
2314 F2
2315 F3
2316 F4
2317 F4
2318 E5
2319 F4
2321 B11
8V 2322 B11
2323 B12
RSA1 2324 B12

16V 10u

47u 16V
10u 16V
2325 B12
B B

100n
RSA2

100n
2326 D13
2327 D13
2328 E12

2321

2322

2323

2324

2325
2329 E13
5V 2330 F12
5V 5V_FV 5V
7304 2331 F13

18

10

42

33

34
5301 I301 MSP3425G 2332 G11
3325 10K

100n

10u
2333 G12

ADR_CL

ADR_SEL

D_CTR_IO1

D_CTR_IO0

TESTEN

VREFTOP

AHVSUP

CAPL_M

4K7
47u

BAS316
10u 16V
2303
2334 G12
220u 10V
2301

2302

100n
3322 100R 12
SCL_5V I2C_CL 2335 D7

2304
3323 100R 13
2336 D7
C SDA_5V I2C_DA
C 3311 E2

6311

3324

5321
11
STBYQ
14 3312 E2
I2S_CL
3313 G3
15 19 3314 G2
I2S_WS DVSUP
16
3315 G3
I2S_DA_OUT 3316 G4
22
RESETQ
3317 E4

16V
17

100n
10u
I2S_DA_IN1
3318 E4
21 3319 F4
I2S_DA_IN2
S1...4 I2SL/R I2SL/R
3320 F4

2326

2327
FM1 DACM_R 26
2335 56p 3 ANA_IN-
LOUDSPEAKER R D/A 3321 E6
FM2 LOUDSPEAKER 3322 C7
D 5V 2336 1u0 2 ANA_IN+
DEMODULATOR NICAM A
NICAM B LOUDSPEAKER L D/A
DACM_L 27 D 3323 C7
3324 C13
1303 1302 I302
5311 6u8 5V_FV
3325 C13
TCSN9082PA26F(H) TCSM0601PD25F(H) 3326 E6
100n

4311 E2
10u 16V

4312 G2
MT 1177
1166

3321
5V_FV

10K
5301 C2
2311

2310

IDENT IDENT 5311 D3

5V_FV 43 MONO_IN DFP
5V_FV

1 3317 4K7 2318 100n 5312 E3

BB+
2 5321 C13
B+

8
3 2312 10u 16V 3318 10K 3 7303-1 36 5322 G11
NC LM393D AGNDC
4 6311 C13

4u7 50V
E NC
5 4311 2 1
TUN_DET0
E

100n
AS HEADPHONE R 7302 G3
TUNER

6 3311 100R 2313 100n 5V_FV A/D SCART-L

4
SCL 100R SCL_5V 7303-1 E5
77 3312
SDA SDA_5V
8 7303-2 E5
AFT_OUT

2328
HEADPHONE L

2329
9 5V_FV 41 SC1_IN_R SCART-R 7304 C8
AUDIO_OUT A/D

3326
10

10K
SIF_OUT I301 D2
8

11 I303 5312 22u 5 7303-2

2u2 50V

VT LM393D I301 C3
2316

330n

2317

12 40 SC1_IN_L SC1_OUT_R 30 AIA_R_MSP

NC TUN_DET1
5V_FV

13 33VSTBY 3319 27K 6 7 SCART-R D/A I303 E3

4u7 50V

VIDEO_OUT
I311 G12
2315
2314

10n

4
MT

3320 10K 38 SC2_IN_R SC1_OUT_L 31 AIA_L_MSP I312 G12

SCART-L
D/A
55
44
11
11

1n0

1n0
37 SC2_IN_L
F SCART Switching Facilities
F

2330

2331
5V_FV

XTAL_OUT
2319

XTAL_IN
AHVSS

AVSUP
VREF2

VREF1

DVSS
AVSS
ASG
NC

TP
100n
3313

2K2

25

29

23

24

28

32
35

39

44

20

6
1
4312 5V I311 I312
7302 5322 1301
BC857BW TUN_CVBS

G 3314 10u 18M432

G

100n

6p8

6p8
100R
3316

75R
3315

100R

2333

2334
2332
H H

I I

3139_243_33332_130_3_a2.pdf 2006-03-01

1 2 3 4 5 6 7 8 9 10 11 12 13
 Circuit Diagrams and PWB Layouts 3139 785 3220x 7. EN 24

Analog: PSU and Interfaces

1401 D1 I408 C6
1 2 3 4 5 6 7 8 9 10 11 12 13 1402 C5 I409 D6
1403 A13 I410 D6
1404 C13 I413 D8
1405 D13 I415 B10
1406 E13 I421 A13
1407 F13 I422 B13
1408 F13 I423 B13
1409 H13 I424 B13
A A 1410 E13 I425 B13

PSU and interfaces

1411 B3 I426 B13
1403
B12P-PH-K
1412 E4 I427 B13
1413 H3 I431 C13
3V3BE I421
1 1414 C6 I432 C13
2

to Digital Board
1415 E7 I433 C13
3
I422
4
2411 B2 I434 D13
5 2412 C3 I435 D13
7419 I423
SI2306DS 12VBE 6 2413 F2 I436 D13
1411 T 500mA I424
12V 7 2414 I2 I441 E13
12VSTBY 8 2415 D6 I442 E13
5VBE I425
9
4413 I426 2416 D7 I450 F13
B 12VBE
12V 3427
7423
BC547B I415
HDD_ON I427
10
11
B 2417 C9 I451 F13
4414
7411 8V 12 2418 E6 I452 F13
2411

330u
SI2306DS 33VSTBY 100R 2419 C6 I464 G13
12VE 2421 G6 I465 G13
12V
GND 2422 H8 I467 G13

47K
3424
33VSTBY

3421

100K

3423

3K3
2423 G8 I471 H13
GND 2431 E11 I479 H13

3428
7420

4K7
BC847BW 7421 3410 C3 I480 H13
PDTC124EU 1404 3411 C3 I481 H13
100K
3411

3413

47K

1u0 50V
B4B-EH-A

220K
3422
3412

2419
3412 C3 I482 I13

3K3

to ODD
I431 3413 C4 I483 I13

BZX384-C8V2
STBYn 12VE 1
C 2
C 3414 D3 I491 G9

2417

100n

6412
7412 I432
3 3415 D3
7413 PDTC124EU 1402 I433
BC847BW
5VE 4 3416 D4
B6B-PH-K
2u2 50V

220K
2412

3410

I406 12V_P 3417 E4

STBYn 6 GND
I407 3418 F3

BAS316
Fr MCU 5

6413
H = On I408
4 POWER_FAIL 7422 GND GND 3419 H3
L = Standby
3 1414 125mA T BC337-25 I413 3420 I3
I409 5VN_P
2 5VN 3421 B6
I410 VGN_P
1401 GND 1
3422 C7
B5P-VH

3425

2416

100n
47K
GND 3423 C7
I401 12V_VH
1 GND 3424 B7

100u
2415
I402 6 6411
2
I403 5V_VH 7414 5 3426 1405 3425 D7
D 3
4
I404 3V3_VH SI3443DV 2
12VH 1K5
12V B4B-EH-A D 3426 D8

to HDD
I405 4 1 BZX384-C6V8 I434 3427 B10
5 12VH 1
3414

47K

2 3428 C9
I435
3 3429 G3
I436
GND 5VH
3

3415 7415 4 3431 F6

BC847BW
GND 3416 12V 3432 G6
3K3 3433 G6
HDD_ON 1415 125mA T
3K3 VGNSTBY 3434 H7
3435 H7

GND
3417

4419
47K

10u 50V
5V 3436 H8

2418
3437 G7

3444

3K3
1406
3438 H9
E B2B-EH-A E 3439 H5

10u 25V
2431
I441
GND 1 3441 F10
I442
2 3442 E10

to FAN
GND

3442

3445

1R0
4K7
3443 F10
1410
3444 E10
5VSTBY B2B-EH-A
1412 T 1000mA 3445 E10
7425
5412 3441 BC327-25 1 3446 F10
4415 7424
BC847BW 2 3451 H10
2413

560u

1m0 68R
4416 7431 3452 H10
MC34063AD 3453 H11
7416 1407 1408
SI2306DS 3431 3454 H11
HLW19S-2C7 HLW17S-2C7

3443

3446
8 DCOL SWC 1

4K7

1K0
F 5V
100R I450
19 17
F 4411 G5
4412 G6
I451
S Q SCL_3V3

Communication to digital board

GND 18 16 4413 B4
SDA_3V3 I452
17 15
RDYFM 4414 B4

BAS316
16 14
R

6421
3418
DFM 15 13 4415 F4
12V

7 IS DHOST 14 12 4416 F4
10K 13 11 4417 I3
SWE 2 SCKFM
IPK 12 10 4418 I3
3433
3432

1R5 FAN
1R5

ATNFM 11 9
7426 TIMC 3 4419 E7
SI2306DS OSC HOSTRST# 10 8
5VBE 5VSTBY
AIN_SEL0 9 7 5411 G6
AIN_SEL1 5412 F7
4411
5411
6 REFERENCE FBS
8 6
VCC REGULATOR 7 5 6411 D8

2423

390p
G 5VE 33u 8SC2_1 6 4
G 6412 C10
100u 10V

8SC2_2 5 3
2421

TUN_DET1 I464
4 2 6413 C10
3429
12V

5 CIN_NEG GND 4 TUN_DET0 I465 6421 F9

3 1
10K HDMI_INT 2 6422 H6
4412

FAN I467
5V 3V3 1 7411 B3
7417 3437 33VSTBY
I491 7412 C4
SI2306DS 1409 7413 C3
5VH 12VSTBY 47K 7441 3453 HLW14S-2C7
3439
BSH103 7414 D3
3434

3451
I471
1K8

4K7
100u 50V
1K0 1 7415 D4

Communication to front board

3438
2422

3436

22K
22K
1K0 SCKFM 2
DFM
7416 F3
BZX384-C8V2

3 7417 G3
SCL_5V SCL_3V3 DHOST 4
12VH

3419
100R
6422

3435

7418 I3
H 10K
7442
BSH103
3454 RDYFM
5
6
H 7419 B7

3452

4K7
ATNFM 7 7420 C7
1K0 HOSTRST# 8 7421 C8
9 7422 C7
5VSTBY I479
3V3BE GND 10
SDA_5V SDA_3V3 STBYn I480
11
7423 B10
1413 2A T POWER_FAIL I481 7424 F11
7418 12
VGNSTBY I482
STS9NF30L 13 7425 E11
4417 12VSTBY I483
3V3 14 7426 G3
7431 F7
2414

560u

4418
7441 H10
7442 H10
3420

18K

I I I401 D1
I402 D1
GND I403 D1
I404 D1
12V I405 D1
I406 C6
3139_243_33332_130_4_a2.pdf 2006-03-01
I407 C6

1 2 3 4 5 6 7 8 9 10 11 12 13
 Circuit Diagrams and PWB Layouts 3139 785 3220x 7. EN 25

Layout: Analog-Main Part (Top View)

3380_APAC_TOPLAYR.pdf 2006-05-25
 Circuit Diagrams and PWB Layouts 3139 785 3220x 7. EN 26

Layout: Analog-Main Part (Bottom View)

TopView_AnalogBd_Hmc_32694.pdf 2005-05-25
 Circuit Diagrams and PWB Layouts 3139 785 3220x 7. EN 27

Front: Front Panel - Display

0010 E3 6108 D10

1 2 3 4 5 6 7 8 9 10 11 12 13 1100 A6 6109 D10
1101 F1 6111 E3
12VSTBY 1100 1102 F2 6112 F3
HUV-08SS65T 1103 F2 6113 F3
3100
1104 F1 6114 G3
VGNSTBY
330R 1105 F2 6115 G3
A 3103
A

330R
3101

2100

3102

10K
47n
1106 F2 6116 H3
2SD1664 10R
7100 1107 E10 6117 H5
3104 3105
1108 F10 7100 A3

P17
P16
P15
P14
P13
P12
P11
P10
F11
F12

F22
F21
5VSTBY F2

NC
8G
7G
6G
5G
4G
3G
2G
1G
P9
P8
P7
P6
P5
P4
P3
P2
P1
BAS316 3106 470R 50V 22u 3107 6101 10R 1109 F13 7101 B2
7101 3108 2100 A4 7102 B3
6100 33R BC847BW 2101 470R BZX384-C6V8 2101 B4 7103 C1
F101

1
2

4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29

32
31
1K0

3109 10R
3111 2102 B5 7105 H13

470R
10R

3110

2102

47n
2103
2104 F100 2103 B1 F100 B6
B 220n
3112 10R B 2104 B5 F101 B9
2105

100n

2SB1132 22u 35V 2105 B1 F102 E13

3113
100u

7102 10R
5100 2106 B1 F103 E13
2106 220n 2107 B2 F104 E13

3127

3128

3129

3130

3131
82K

82K

82K

82K

82K
3114 2107
2108 F10 F105 E13
6K8 1n0 VGNSTBY 2109 F11 F106 F13

F2
2110 F9 F107 F13
3115

1K0

7103
2111 G2 F108 F13
C BC847BW
C 2112 G11
2113 G12
F110 F13
F111 F13

6108 BAS316
2114 G12 F112 F13

6102 BAS316

6104 BAS316

6107 BAS316
6103 BAS316

6105 BAS316
GND

6106 BAS316

6109 BAS316
2115 G12 F113 F13
2116 G13 F114 F13
2117 G2 F115 E9
2118 G2 F117 F10
2119 H10 F119 F10
2120 H3 F120 H5
D 3116 WS0 D 2121 I9 F121 H3
2122 I3 F122 H12
2K7
GND
2123 I3 F123 I12
3117
2124 I12
2K7 3100 A3
0010 3118 3101 A2
WH02D-1 3102 A4
5VLP 2K7
1107 HLW14S-2C7 3103 A10
E 27 1 F115 3 1 GND F102 14 E 3104 A3
1 2
14 Φ VDD SCK F103
F104
13 3105 A10

2
15
0 FIP 51
D_FM
F105
12 3106 A2
5101 1 1 GND D_HOST 11
16 CTRL 3107 A4
2 10
6111
17 DRIVER X 50 1108 RDY_FM F106 9
3108 B10
3 2 100R F117
1101 1102 1103 18 ATN_FM F107 3109 B1
BAS316 4 8
19 2 HOST_RESET F108
5 1 3119 32K768 7 3110 B4
EVQ11L05R EVQ11L05R 20
EVQ11L05R 6112 6 XT 6 3111 B5

2108

2109
21 3 F110

22p

22p
7 2 5VSTBY 5
F 1104 1105 1106 BAS316
22
23
8
4 F119
POWER_FAIL
POWER_CTL F111
F112
4 F 3112 B6
3113 B6
9 RESET 3

3120 47K
EVQ11L05R EVQ11L05R EVQ11L05R 24 VGNSTBY F113 3114 B1
6113 10 GND 2
25 8 F114

1u0
11 SCK SCK
2110
12VSTBY 1 3115 C2
26
BAS316 12 3116 D13
29 FIP 10 1109

100u 16V
10K 6114 13 D_HOST D_HOST
2111 2n2 3121 3117 D13

2113

100n
2112
30
14

2114

100n
2115

100n
2116

100n
BZX384-C6V8
31
15 SCK1
11 3118 E13
2117 2n2 32
6115 GND 16 POWER_FAIL GND 5VLP 3119 F10
33 12
17 POWER_FAIL 3120 F10
G 3123 10K BAS316
34
35
18
13
RC
3122

47K
5VSTBY G 3121 G2
19 IR GND GND 3122 G9
36
2118 2n2 20
KEY_C
37
21 VLOAD
28 3123 G2
38 VGNSTBY
KEY_B 22 3124 H10

270K
3124

2119
39 41

10n
KEY_A 23 1 KEY_A 3125 H2
40 42
3125 10K 24 KEY_R 2 KEY_B 3126 H6
43
F120 3126 3 KEY_C
45 3127 B9
2120 1
46 49 3128 B9
LTL816KETNN

330R 2 IC GND
H 2n2
47
3
LED RC H 3129 B10
6117

48 44
4 POWER_CTL 3130 B10
GND 3131 B10
5 7 5VSTBY 7105
RDY_FM RDY HOST_RESET HOST_RESET
TSOP4836ZC1 5100 B1
6116 F121 F122
5VLP
6
ATN FM VS
5101 E3
5VSTBY ATN_FM
2121

100n

BAT54 COL F123

6100 B1
1m0 6.3V

9
GND D_FM D OUT 6101 A5
2122

2123

2124

100n
10n

VSS 6102 D8
GND
I 52
GND I 6103 D9
6104 D9
GND GND
DC0 GND GND GND 6105 D9
3139_243_33314_130_1_a3.pdf 2006-02-28 6106 D9
6107 D10

1 2 3 4 5 6 7 8 9 10 11 12 13
 Circuit Diagrams and PWB Layouts 3139 785 3220x 7. EN 28

Front: Front Panel - Audio/Video-In

1200 D3
1 2 3 1201 D1
1202 B3
1203-1 B1
IO0 1203-2 B1
1203-3 C1
2211 B3
2212 C3
2213 C1
2214 E2
2215 C1
3211 B2
3212 B2
A A 3213 C1
F203 B1
F204 B1
F205 B1
F206 C1
F209 B3
F211 B3
F212 B3
HLW6R-2C7
F203 AV_GND 6
LPV8529-0100F F209 5 CVBS
2
B YELLOW
1203-1
1
3
AV_GND
F211
4
3 AL
B
AV_GND 2
WHITE 5 F212
F204 3211 2211 1 AR
1203-2 4
6 1202
600R 470p
8
RED F205 3212 AV_GND
7
1203-3
600R 2212
F206

3213

2213

100p
75R
470p
2215 AV_GND

1u0

C GND AV_GND AV_GND

C

D D
I LINK 1394
1201 1200
TPB0-
1 1
TPB0+
2 2
3 TPA0- 3
4 4
TPA0+ 5 6
5
6
CSS5004-7A01E
2214
S6B-PH-K
1u0

E AV_GND GND
E

3139_243_33314_130_2_a4.pdf 2006-02-28

1 2 3
 Circuit Diagrams and PWB Layouts 3139 785 3220x 7. EN 29

Layout: Front Panel (Top Copper Pattern) - SMD + Components

Front_Layout_3139_243_33312_pg1.pdf 2006-05-25

Layout: Front Panel (Bottom Copper Pattern) - Components

Front_Layout_3139_243_33312_pg2.pdf 2006-05-25
 Circuit Diagrams and PWB Layouts 3139 785 3220x 7. EN 30

Front: Standby Layout: Standby (Top View)

1302 C1
1 2 3 4 1303 C4
2301 D2
6300 D2
6301 D2
F300 D2
F301 D2
I300 D3
A A

B B
Front_Layout_3139_243_33312_pg4.pdf 2006-05-25
DC0

C C

1302 1303
F300
1
2 EVQ11L05R

WH02D-1
D F301
D
BZX384-C6V8

BZX384-C6V8
2301

6300

6301
2n2

E GND E

F F

G G

3139_243_33314_130_3_a4.pdf 2006-02-28

1 2 3 4
 Circuit Diagrams and PWB Layouts 3139 785 3220x 7. EN 31

Digital: Back-End Processor

1101 B6 3166 B8 T117 H5

1 2 3 4 5 6 7 8 9 10 11 12 13 1105 E5 3167 B8 T118 H6
1111 D6 3168 F9 T119 I5
2101 B6 3169 F9

Back-end Processor
2102 B6 3171-1 G10
Communication (COM) 3V3BE 2105 E8 3171-2 G10

10K
10K

10K
Video Input Digital (VID) Video Output Analog (VOA) 2106 E5 3171-3 G10
3V3BE
7101-3 2108 G12 3171-4 G10
DMN-8652

1K0
1K0
1K0
1K0
2109 G13 3172-1 G10
Φ

3117
3116

3118
VIDEO DAC 2121 G3 3172-2 G10
B20 A3
Back-end Flash (BEF) VI_E0 DAC1_OUT 2122 G4 3172-3 G10
7101-7 A20
A T106 DMN-8652 VI_E1
A4 A 2123 G4 3172-4 G10

3101

3103
3102

3104
GPIO29 DAC2_OUT
7101-5 TDI A9 Φ AE19 3162 10K A21
PEC
B4
2124 G4
2125 G4
3173-1 G10
3173-2 G10
DMN-8652 T101 TDI SIO_IRRX 3V3BE 0 DAC2_OUTB
TDO B7 C20 VI_VSYNC
T102 TDO GPIO39 1 2126 G4 3173-3 G10
AF8
AE8
0 Φ AF15 BEF_ALE_1 3124 22R
T103
TCK
TRST#
B8
C7
TCK JTAG CS6
AD19
GPIO45 DAC3_OUT
A5
2127 G4 3173-4 G10
AC9
1 HMST HMST_ALE
AD12
T104
TMS D8
TRST SIO_IRTX1
3V3BE A17 A6 2128 G4 3174-1 G10
2 HMST_ADRLO HMST_CS0_8BIT T105 TMS GPIO40 0 DAC4_OUT
AD9 A18 VI_CLK 2129 G5 3174-2 H10
3 CS7 1
AF7 AF16 3137 10K T107 A1 AF20 3166 4K7 B5 2130 G5 3174-3 H10
4 0 3V3BE CLKI SIO_IRTX2 DAC4_OUTB
CLKX MISC
AF17 3138 10K T108 A2 3167 4K7 C19
AD17
1
AF18 3139 10K
1101
C9 AD21 COM_SCL_1 3164 22R B19
0
A7
2131 G5 3174-4 H10
0 2 13M5 XJ RSTO SIO_SCL 1 DAC5_OUT
AE16 HMST_CS AF19 3131 10K D9 AC19 COM_SDA_1 3165 22R B23 2135 I5 3175-1 H10
1 3 EPD SIO_SDA 2
AD15 AE5 3132 10K VIPINT H1 B22 A8 2141 F5 3175-2 H10
2 4 CLK0_DAC 3 DAC6_OUT
AE17 AF5 3133 10K AD18 A22 2142 F5 3175-3 H10
B AC16
3 5
3134 10K H2
GPIO35 SIO_SPI_CLK
AF21 B21
4
VI_D B

18p

18p
4 3163 USB_48MHZ SIO_SPI_CS0 5 2143 F5 3175-4 H10

1
AD16 AD8 C25 A10

Video Output Digital (VOD)

5 0 1M0 GPIO36 GPIO24 6 0 2144 F6 3176-1 H10
AD13 AE14 H4 AE21 B26 B10

2101

2102
6 1 BYPASS_PLL SIO_SPI_CS1 7 1 2145 F6 3176-2 H10
AE15 HMST_GPIO AE10 3V3BE C24 B11
7 2 GPIO25 8 2
AD14 HMST_ADRDATA AE9 AC18 3159 4K7 A26 A11 2146 F6 3176-3 H10
8 3 SIO_SPI_CS2 3V3BE 9 3

BAV99
6101
AE11 C11 3 2147 F6 3176-4 H10

10K
9 CS10 4
AE13 AF13 BEF_OE#_1 3121 22R AD22 B9 C12 2148 F6 3177-1 I10
10 HMST_LDS SIO_SPI_MISO VO_HSYNC 5
AF12 AE22 C8 B12
AC11
11 HMST_OE
AE18 3V3BE
SIO_SPI_MOSI
AE20 C10
VO_VSYNC 6
A12
2149 F6 3177-2 I10
12 HMST_RST SYSRST# SIO_UART1_CTS VO_ACTIVE 7 2151 G1 3177-3 I10
AF11 AC17 A16 VO_D B13

3119
13 HMST_UWE GPIO42 VO_CLK 8
AE12 3123 10K 3158 10K AF23 B15 A13 2152 G1 3177-4 I10

2
14 HMST_UDS 3V3BE SIO_UART1_RTS VO_E 9
AD11 AC10 C13 2153 G1 3178-1 I10
15 HMST_WAIT GPIO41 GPIO30 10
HMST_WR
AF14 BEF_WE#_1 3122 22R SERIAL_IO SIO_UART1_RX
AC20
11
C14 2154 G1 3178-2 H10
MDATA<0:15> AF24 B16 B14
C AE7
AD7
0
LWE
HSMT_DTACK
AD10 3125 10K
3V3BE
SIO_UART1_TX
SIO_UART2_CTS
AC22
AE24
3160 4K7
3V3BE
VIP_SCL
VIP_SDA
C16
D16
0
1
12
13
A14
A15
C 2155 G2
2156 G2
3178-3 H10
3178-4 H10
1 SIO_UART2_RTS VIP_RST# 2 14
AF6 AF9 AF22 B17 C15 2157 G2 3181-1 G13
2 HMST_ADRHI PCMCIA_IOW SIO_UART2_RX 3 15
AC8 C17 2158 G2 3181-2 H13
3 GPIO4 GPIO37 4
AE6 AF10 AE23 D17 VO2_D GPIO<0:15> 2159 G2 3181-3 H13
4 PCMCIA_IOR SIO_UART2_TX 5
VIPINT B18
MADR<1:26>
GPIO5
3135 10K
GPIO38
AD20 C18
6 2160 G2 3181-4 I10
3V3BE SPI_CS3 7 2161 G2 3182-1 I10
3136 10K A19
CS11 8
D18 2162 G3 3182-2 H13
9
1111 2165 I6 3182-3 I10
B4B-PH-SM4-TBT(LF)
2166 G6 3182-4 H13
IEEE1394 Link - Physical (LNK) 5 6 5VBE
3199 3198 2167 G6 3183-1 I10
4 100R 1K0 2171 H5 3183-2 G13
T109
D 3V3BE
3
2
T110
T111
6
3197
3V3BE
3192
D 2172 H6
2173 H6
3183-3 H13
3183-4 G13
1 4K7 10K

2199
7111-1 2

1n0
Audio (AUD) 2174 H6 3184-1 G13
3V3U BC847BS 3
1 3194 2175 H6 3184-2 G13
10K 5 7111-2 3V3BE 2181 I5 3184-3 G13
2K2
2K2
2K2
2K2
2K2
2K2
2K2
2K2

7101-6 3196
BC847BS 2182 I5 3184-4 G13
E4

F4

DMN-8652

3195

3193
4 2183 I6 3185-1 H13

6K8

10K
5V 4K7
Φ 1105

10K
10K
10K
10K
10K
USB_AVDD B4B-PH-SM4-TBT(LF)
2191 I6 3185-2 I13
H3 2106 100n
3141
3143
3145
3147
3149
3151
3153
3155

L1
LINK_ON 1394 E1 7101-4
2192 I6 3185-3 I13
LPS ANA 0 1 5V DMN-8652 2199 D7 3185-4 H13
L2 DMINUS F1 COM_USBM1 3105 22R
LREQ 1 2 USBM1
K1 3106 22R
Φ 3101 A6 3186-1 H13

3111
3112
3113
3114
3115
PHY_CLK 1394 3 USBP1
E2 3107 15K 3102 A6 3186-2 H13
E J4
L3
PHY_CTL0
DPLUS
0
1
F2 COM_USBP1 3108 15K
6
4
5
3V3BE
2105
D25
E23
GPIO34 AUDIO
A2_FSYNC
F25
E 3103 A6 3186-3 H13
PHY_CTL1
G2
100n A2_SCLK AO2_D0 3104 A6 3186-4 H13
0 GPIO31 3105 E5 3187-1 I13
J3 HOST_OC G4 3109 10K 7105 G24
0 1 5V 0
L4 M24C16-RDW6 D26 G23 3106 E5 3187-2 I13

8
1 GPIO44 0 1
M4
Φ E24 AO_D F26 3107 E5 3187-3 I13
2K2
2K2
2K2

2K2
2K2
2K2
2K2
2K2

2 1 AI_D 2
M3 G1 E26 G25 3108 E5 3187-4 H13
3 0 (2Kx8) 2 3
J2 1394_PHY_DATA HOST_PO G3 3110 10K 7
J1
4 1 WC 3168 GPIO<6:7> A23
3109 E5 3188-1 I13
5 GPIO43 EEPROM 22R AO_IEC958 3110 F5 3188-2 I13
K3 1 6 C26 E25
3150
3146
3148

3154
3156
3152
3142
3144

6 0 SCL AI_FSYNC AO_FSYNC

K2 2V5BE 2 A24 A25 3111 E11 3188-3 I13
7 5141 1 ADR AI_MCLKO AO_MCLKO
3 5 D24 F24 3112 E11 3188-4 I13
USB_AGND BLM31 T112 2 SDA AI_SCLK AO_SCLK
3169 B24 B25 3113 E11 3191 H4
2V5S AI_MCLKI AO_MCLKI
E3

F3

4
22R 3114 E11
F GPIO32 GPIO33
F 3192 D9
100n

100n

100n

100n

100n

100n

100n

100n
22u 35V

CS8 CS9 3115 E11 3193 E8

2141

3116 A10 3194 D8

2142

2143

2144

2145

2146

2147

2148

2149

Back-end SDRAM (BES) 3117 A10 3195 E8

3118 A10 3196 D7
7101-1 3119 C10 3197 D8
DMN-8652 2V5S
3121 B4 3198 D7
3V3BE
5165 3171-4 4 5 47R BES_DQ(0)_1 V23
Φ 2108 100n 2109 100n 3122 C4 3199 D7
3V3BE 1V8BE BLM18P T115 3171-3 3 6 47R BES_DQ(1)_1 W24
0 SDRAM 3123 C4 5121 G3
5151 5121 3V3U 1
3171-1 1 8 47R BES_DQ(2)_1 Y25 D22 3124 A4 5135 H5
BLM31 T113 BLM31 T114 2 SDRAM_VREF
100n

100n

3171-2 2 7 47R BES_DQ(3)_1 Y26

3V3P 1V8C
3172-1 1 8 47R BES_DQ(4)_1 V24
3
W23 22R 5 4 3184-4
3125 C4 5141 F5
7101-2 4 CKE
BES_CKE_1
3131 B4 5151 G1
100n
100n

100n

100n

100n

100n

100n

100n

100n

100n

100n

100n

100n

100n

100n

100n

100n

100n

100n

100n

100n

DMN-8652 3172-2 2 7 47R BES_DQ(5)_1 W26 AA25 22R 7 2 3184-2

10u 25V

330u 16V

BES_CAS#_1
2166

2167

G ΦATAPI2
5 CAS
G 3132 B4 5165 G6
2151

2121

3172-3 3 6 47R BES_DQ(6)_1 V25 SDRAM AA26 BES_WE#_1 22R 6 3 3184-3

6 WE
Optical Disc Drive (ODD)

Hard Disk Drive (HDD)

ATAPI 3172-4 4 5 47R BES_DQ(7)_1 V26 Y24 BES_RAS#_1 22R 8 1 3184-1 3133 B4 5166 H6
2154
2152

2153

2155

2156

2157

2158

2159

2160

2161

2162

2122

2123

2124

2125

2126

2127

2128

2129

2130

2131

7 RAS
V4 AC5 3173-1 1 8 47R BES_DQ(8)_1 U25
3134 B4 5171 G5
DMARQ DMARQ 8
3V3BE W2 AF4 3173-2 2 7 47R BES_DQ(9)_1 U26 N23 BES_CLK0_1 22R 7 2 3183-2
5171 R1
INTRQ INTRQ
AE4 3173-3 3 6 47R BES_DQ(10)_1 T25
9
SDRAM_CLK
0
P23 BES_CLK0#_1 22R 5 4 3183-4
3135 C4 5181 I5
BLM18P T116 W3
IORDY IORDY
AD5 3173-4 4 5 47R BES_DQ(11)_1 T26
10 0 3136 D4 6101 B13
3V3A DIOR DIOR 11
T3 AD4 3174-1 1 8 47R BES_DQ(12)_1 R26 R23 BES_CLK1_1 22R 8 1 3181-1 3137 B4 7101-1 F11
DIOW DIOW 12 1
100n

100n

100n

100n

V1 AF3 3174-2 2 7 47R BES_DQ(13)_1 P25 SDRAM_CLK T23 22R 7 2 3181-2 3138 B4 7101-2 G8
10u 25V

BES_CLK1#_1
DMAACK DMAACK 13 1
2171

3V3BE Y1 AD6 3174-3 3 6 47R BES_DQ(14)_1 P26

3139 B4 7101-3 A12
RESET RESET 14
3174-4 4 5 47R BES_DQ(15)_1 N25 U24 BES_DQM(0)_1 22R 6 3 3183-3
2172

2173

2174

2175

Y2 AE2 3175-1 1 8 47R BES_DQ(16)_1 M25

15 0
N26 BES_DQM(1)_1 22R 7 2 3182-2
3141 E1 7101-4 E12
0 0 16 1 3142 F1 7101-5 A2
W1 AD3 3175-2 2 7 47R BES_DQ(17)_1 M24 SDRAM_DQM M26 BES_DQM(2)_1 22R 5 4 3182-4
3161 10K

1K2 1%

1 1 17 2
3143 E1 7101-6 D3
3191

3V3A 3V3A 5VBE 1V8D 3V3V 1V8C 2V5S 3V3P 3V3R 3V3P V3 AC4 3175-3 3 6 47R BES_DQ(18)_1 L26 K23 BES_DQM(3)_1 22R 6 3 3181-3
3
2 ADR ADR 2 18 3
U4 AF2 3175-4 4 5 47R BES_DQ(19)_1 L25 3144 F1 7101-7 A7
H 1V8BE
5135
3V3BE
5166
P1
3
4
3
4
AE3 3176-1
3176-2
1
2
8
7
47R
47R
BES_DQ(20)_1 L23

BES_DQ(21)_1 K26
19
20
SDRAM_DQ
0
AC25
AB23
BES_A(0)_1

BES_A(1)_1
22R
22R
6
8
3
1
3186-3
3186-1
H 3145 E1 7101-8 I3
BLM18P T117 BLM18P T118 21 1 3146 F1 7105 E8
AC21

AC13
AC14
AC15

AC12
AA23
AC7

AC6

M23

U3 Y3 3176-3 3 6 47R BES_DQ(22)_1 K25 AA24 22R 5 4 3185-4

AA4
D21

D10

D11
D12
D13

D23
C22

N24

R24

U23

D14
D15
D19
D20
P24
F23

T24

BES_A(2)_1
1V8D 3V3R 0 0 22 2
D5
D2
D3
D4

D7

C6
D6

N4

R4

D1

C1
B1

K4

P4

3147 E2 7111-1 D7
T4

U1 AA1 3176-4 4 5 47R BES_DQ(23)_1 K24 AC26 BES_A(3)_1 22R 8 1 3185-1

1 1 23 3
100n

100n

3148 F2 7111-2 D9
XTALVDD

BIAS_5V00

BIAS_5V01

DAC_DVDD

RES_VDD

REFVDD

VDDP_08A
VDDP_19A

VREF

T1 Y4 3178-4 4 5 47R BES_DQ(24)_1 H23 AB24 BES_A(4)_1 22R 5 4 3186-4

AVDD DAC_VDD VDD VDD25 VDDP 2 2 24 4
R2
3 3
AA2 3178-3 3 6 47R BES_DQ(25)_1 G26
25 5
AD25 BES_A(5)_1 22R 5 4 3187-4 3149 E2 T101 A6
P3 AB1 3178-2 2 7 47R BES_DQ(26)_1 H25 AD26 BES_A(6)_1 22R 7 2 3186-2 3150 F2 T102 A6
2135

2165

4 4 26 6
N3 AA3 3178-1 1 8 47R BES_DQ(27)_1 H24 AE25 BES_A(7)_1 22R 6 3 3188-3
5 5 27 7 3151 E2 T103 A6
SUPPLY N2
6 6
AB2 3177-3 3 6 47R BES_DQ(28)_1 J24
28 8
AC23 BES_A(8)_1 22R 8 1 3187-1
3152 F2 T104 A6
M2 AC1 3177-2 2 7 47R BES_DQ(29)_1 J25 SDRAM_A AF25 BES_A(9)_1 22R 7 2 3188-2
7 7 29 9
M1 DATA DATA AB3 3177-4 4 5 47R BES_DQ(30)_1 J23 AD24 BES_A(10)_1 22R 6 3 3187-3 3153 E2 T105 A6
DAC_DVSS_1

7101-8 8 8 30 10
DMN-8652 3V3BE 5VBE N1 AC2 3177-1 1 8 47R BES_DQ(31)_1 J26 AE26 BES_A(11)_1 22R 5 4 3188-4 3154 F2 T106 A6
5181 9 9 31 11
XTALVSS

P2 AD1 AC24 BES_A(12)_1 22R 7 2 3187-2 3155 E2 T107 B6

REFVSS

BLM18P T119 R3
10 10
AB4 3183-1 1 8 22R BES_DQS(0)_1 W25
12
AF26
I AGND GND
3V3V
T2
11
12
11
12
AC3 3182-1 1 8 22R BES_DQS(1)_1 R25
0
1
13
14
AD23 BES_A(14)_1 22R 8 1 3188-1 I 3156 F2
3158 C6
T108 B6
T109 D6
100n

100n

100n

100n

U2 AD2 3182-3 3 6 22R BES_DQS(2)_1 L24 SDRAM_DQS AB25 22R 7 2 3185-2

220u 16V

BES_A(15)_1
13 13 2 15
3159 B8 T110 D6
2181
C5
C3
B3
C4

B2

B6

C21
C23
L11
L12
L13
L14
L15
L16
M11
M12
M13
M14
M15
M16
N11
N12
N13
N14
N15
N16
P11
P12
P13
P14
P15
P16
R11
R12
R13
R14
R15
R16
T11
T12
T13
T14
T15
T16

C2

V2 AE1 3181-4 4 5 22R BES_DQS(3)_1 H26 Y23

14 14 3 16
W4 AF1 AB26 BES_CS0#_1 22R 6 3 3185-3 3160 C8 T111 D6
2182

2183

2191

2192

15 15 17
3161 H2 T112 F5
3162 A8 T113 G1
3163 B6 T114 G3
3164 B8 T115 G6
3139_243_34464_130_01_a2.pdf 2006-03-20 3165 B8 T116 G6

1 2 3 4 5 6 7 8 9 10 11 12 13
 Circuit Diagrams and PWB Layouts 3139 785 3220x 7. EN 32

Digital: Memory

2201 D1 3259-3 C11

1 2 3 4 5 6 7 8 9 10 11 12 2202 D1 3259-4 C11
2203 D3 3261-1 C11
2204 D3 3261-2 C11

Memory 2205 D2
2211 A4
2212 B4
2213 B4
3261-3 C11
3261-4 C11
3263-1 C11
3263-2 C11
2214 B4 3263-3 C11
Back-end SDRAM (BES)
2215 A6 3263-4 C11
VTT 2V5D 2216 B6 3265-1 D11
A 2V5D 2V5D A 2217 B6 3265-2 D11
3251-4 4 5 47R 2251 100n 2218 B6 3265-3 D11
3251-3 3 6 47R 2219 B6 3265-4 D11
3251-2 2 7 47R 2252 100n
2220 D3 3267-1 D11
3251-1 1 8 47R
2215 100n 2235 100n 2221 D3 3267-2 D11
2211 2231 3253-4 4 5 47R 2253 100n 2231 A8 3267-3 D11
22u 35V 22u 35V
2216 100n 2236 100n 3253-3 3 6 47R 2232 B8 3267-4 D11
3253-2 2 7 47R 2254 100n 2233 B8 3269-1 E11
2212 100n 2217 100n 2232 100n 2237 100n 3253-1 1 8 47R
2234 B8 3269-2 D11
2213 100n 2218 100n 2233 100n 2238 100n 3255-4 4 5 47R 2255 100n 2235 A9 3269-3 D11
3255-3 3 6 47R 2236 B9 3269-4 D11
2214 100n 2219 100n 2234 100n 2239 100n 3255-2 2 7 47R 2256 100n 2237 B9 3271-1 E11
B 3255-1 1 8 47R B 2238 B9 3271-2 E11
2239 B9 3271-3 E11
3257-4 4 5 47R 2257 100n
2240 D7 3271-4 E11

18

33

15

55

61

18

33

15

55

61
3257-3 3 6 47R

9
2V5BE 14 14 3257-2 2 7 47R 2258 100n 2241 D7 3273-1 E11
VDD VDDQ VDD VDDQ
5201
BLM31 T203
29
30
0 Φ 17
19
29
30
0 Φ 17
19
3257-1 1 8 47R 2251 A12
2252 A12
3273-2 E11
3273-3 E11
2V5D 1 DDR 1 DDR
31 25 31 25 3259-4 4 5 47R 2259 100n
2 SDRAM NC 2 SDRAM NC 2253 A12 3273-4 E11
32 43 32 43 3259-3 3 6 47R
3 3 2254 B12 3275-1 F11
35
4 16Mx16 50 35
4 16Mx16 50 3259-2 2 7 47R 2260 100n
36 53 36 53 3259-1 1 8 47R 2255 B12 3275-2 F11
5 A 5 A
2V5D 37
6
37
6
2256 B12 3275-3 E11
38 2 100R 3231-1 38 2 100R 3239-4 3261-4 4 5 47R 2261 100n 2257 B12 3275-4 E11
7 0 7 0
39 4 39 4 3261-3 3 6 47R
C 40
8
9
1
2
5
100R
100R
3231-2
3231-3 40
8
9
1
2
5
100R
100R
3239-3
3239-2 3261-2 2 7 47R 2262 100n C 2258 B12
2259 C12
3277-1 F11
3277-2 F11
5

7201 28 7 100R 3231-4 28 7 100R 3239-1 3261-1 1 8 47R

10 3 10 3 2260 C12 3277-3 F11
LP2995 41 8 100R 3233-4 41 8 100R 3241-4
11 4 11 4
2261 C12 3277-4 F11
VDDQ

42 10 100R 3233-3 42 10 100R 3241-3 3263-4 4 5 47R 2263 100n

12 5 12 5
VSENSE 3 2V5D AP 7211 11 100R 3233-2 2V5D AP 7231 11 100R 3241-2 3263-3 3 6 47R 2262 C12 3281-1 F11
6 6
7 PVIN 26 13 100R 3233-1 26 13 100R 3241-1 3263-2 2 7 47R 2264 100n
0 D 7 0 D 7 2263 C12 3281-2 F11
27 BA 54 100R 3235-1 27 BA 54 100R 3243-1 3263-1 1 8 47R
1 8 1 8 2264 C12 3281-3 F11
100n

100n
VTT 8 T201 VTT 56 100R 3235-2 56 100R 3243-2
9 9 2265 D12 3281-4 F11
20 57 100R 3235-3 20 57 100R 3243-3 3265-1 1 8 47R 2265 100n
L 10 L 10
6 AVIN 47 DM 59 100R 3235-4 47 DM 59 100R 3243-4 3265-2 2 7 47R 2266 D12 3283 F11
2220

2240
U 11 U 11
60 100R 3237-1 60 100R 3245-1 3265-3 3 6 47R 2266 100n 2267 D12 3284 G11
12 12
100n

VREF 4 T202 49 62 100R 3237-2 49 62 100R 3245-2 3265-4 4 5 47R

22u 35V

VREF 13 VREF 13 2268 D12 3285 G11

GND
2201

63 100R 3237-3 63 100R 3245-3

NC

14 14 2269 D12 3286 G11

100n

100n

100n

100n
46 65 46 65 3267-4 4 5 47R 2267 100n
D 100R 3237-4 100R 3245-4
D
330u 16V
2202

CK 15 CK 15 2270 D12 3294 H8

2203

45 45 3267-3 3 6 47R
CK CK
44 44 3267-2 2 7 47R 2268 100n 2271 E12 3295 I6
2205

2204

2221

2241
2

CKE CKE
24 16 24 16 3267-1 1 8 47R 2272 E12 3296 H8
CS L CS L
23 DQS 51 23 DQS 51
RAS U RAS U 2273 E12 4291 H6
22 22 3269-4 4 5 47R 2269 100n
CAS CAS 2274 E12 4292 H6
21 21 3269-3 3 6 47R
WE WE 2275 E12 4293 H6
3269-2 2 7 47R 2270 100n
VSS VSSQ VSS VSSQ
3269-1 1 8 47R 2276 F12 4294 H8
34

48

66

12

52

58

64

34

48

66

12

52

58

64
2277 F12 5201 B1
3271-4 4 5 47R 2271 100n
2278 F12 5291 F2
3271-3 3 6 47R
3271-2 2 7 47R 2272 100n 2281 F12 7201 C1
3271-1 1 8 47R 2282 F12 7211 C5
2283 F12 7231 C9
E 3273-4 4 5 47R 2273 100n E 2284 G12 7292 F3
3273-3 3 6 47R
2291 G2 7293 H3
3273-2 2 7 47R 2274 100n
3273-1 1 8 47R 2292 F4 7294 H7
2293 H4 T201 D3
3275-4 4 5 47R 2275 100n 2294 F7 T202 D3
3275-3 3 6 47R 3231-1 C6 T203 B2
3275-2 2 7 47R 2276 100n
3231-2 C6 T204 F2
3275-1 1 8 47R
Back-end Flash (BEF) 3231-3 C6
3277-4 4 5 47R 2277 100n 3231-4 C6
3277-3 3 6 47R 3233-1 C6
3277-2 2 7 47R 2278 100n 3233-2 C6
BA{BA(6:21),BEF_HD(0:15)} 3277-1 1 8 47R
F 3V3F F 3233-3 C6
3233-4 C6
3281-4 4 5 47R 2281 100n
2292 100n 3V3F 3281-3 3 6 47R 3235-1 C6
7292 3281-2 2 7 47R 2282 100n 3235-2 D6
20

3V3BE 74LVC573APW 2294 100n 3281-1 1 8 47R 3235-3 D6

5291 1
BLM18P T204 EN 3235-4 D6

37
3V3F 11 3283 47R 2283 100n
C1 3237-1 D6
VDD 3284 47R
2 19 2284 100n 3237-2 D6
10u 25V

1D
2291

3 18 3285 47R 3237-3 D6

4 17 25 29 3286 47R 3237-4 D6
5 16 24
0 [FLASH] 0
31
1 2Mx8/1Mx16 1 3239-1 C10
6 15 23 33
2 2 3239-2 C10
7 14 22 35
G 8 13 21
3
4
3
4
38 G 3239-3 C10
9 12 20
5 5
40 3239-4 C10
19 42 3241-1 C10
6 6
10

18 44
7 7 3241-2 C10
8 D 30
7
8 8
32 3241-3 C10
9 0 9
6 A 34 3241-4 C10
10 2M-1 / 1M-1 10
3V3F 5
11 11
36 3243-1 C10
4 39 3243-2 D10
12 7294 12
2293 100n 3 41
13 M29W160ET70N6F 13 3243-3 D10
7293 2 43
14 14 3243-4 D10
20

74LVC573APW 1 45
15 15 3245-1 D10
1 48
EN 16 A-1
11 17 3245-2 D10
H C1
16
17
18
H 3245-3 D10
2 19 4291 9 3294 4K7
1D 19 3V3F 3245-4 D10
3 18 4292 13
4 17 14 3296 4K7 3251-1 A11
NC SYSRST# 3251-2 A11
5 16 4293 15 10
RB
6 15
SYSRST#
12
RP
3251-3 A11
7 14 11 4294 3251-4 A11
WE
8 13 28
OE 3253-1 B11
9 12 3295 10K 26
3V3F CE 3253-2 B11
47
3V3F BYTE VSS 3253-3 B11
10

3253-4 A11
27

46

3255-1 B11
I I 3255-2 B11
3255-3 B11
3255-4 B11
3257-1 B11
3257-2 B11
3257-3 B11
3257-4 B11
3259-1 C11
3139_243_34464_130_02_a2.pdf 2006-03-20 3259-2 C11

1 2 3 4 5 6 7 8 9 10 11 12
 Circuit Diagrams and PWB Layouts 3139 785 3220x 7. EN 33

Digital: IEEE 1394 Physical Layer

1351 D5
1 2 3 4 5 6 7 8 9 10 11 12 13 14 2301 D6
2302 D6
2303 D6
2304 D6

IEEE1394 Physical Layer

2305 D7
2306 D7
2307 D7
2321 G5
2341 G9
2343 G9
A A 2351 D5
2352 E5
2361 E5
3301 E5
3302 F5
3303 G8
3304 G8
3305 E8
3306 F7
3307 F7
3308 F7
3321 F5
B B 3322 G5
3331 F5
3332 F5
3341 F9
3342 F9
3343 F9
3344 F9
IEEE1394 Link - Physical (LNK) 3345 G9
3351 E5
3360 E5
3361 E5
C C 3362 E5
4361 E5
5301 C6
3V3BE 7301 D6
5301
BLM18P T317 T301 E7
3V3I T302 E7
T303 E7
2301 T304 E7
10u 25V
T305 E7
T306 E7
2302 100n 2305 100n T307 E7
2303 100n 2306 100n
T308 F7
D D T309 E7
T310 F6
2304 100n 2307 100n
T311 F7
T312 E7
1351 7301 T313 E7

35
25

21
44
45

40
2351 33p 24M576 AT-51CD2 TSB41AB1PHP
T314 E7
Φ

PLLVDD
AVDD DVDD
T315 F6
3351
1M0
T351 42 1 T309 3305 22R
XI SYSCLK
T316 F6
2352 33p T352 43 48 T312 T317 C6
XO LREQ
2361 100n 38 2 T313
T321 F6
0 0 T351 E6
39 FILTER CTL 3 T314
1 1
T352 E6
E 3V3I
4361 22
TESTM
1-PORT CABLE
0
4 T301 E
TRANCEIVER 1
5 T302
3V3I
3360 1K0 23
SE ARBITER 2
6 T303
3361 1K0 7 T304
3

IEEE1394 Physical - Transport (PHY)

3362 1K0 24 D 8 T305
SM 4
9 T306
5
3301 1K0 20 10 T307
3V3I CPS 6
11 T308
7
T310 13
LPS
30
TPA+
3302 10K T321 19 29
3V3I ISO TPA-
3331 5K6 1% 33 28
0 TPB+
3332 750R 1% 34 R 27
F 1 TPB-
F

56R 1%

56R 1%

56R 1%

56R 1%
31 16 3306 680R
TPBIAS 0
17 3307 680R

3341

3342

3343

3344
PC 1
T316 12 18 3308 680R
PD 2
3321 100R T315 37 15 T311

GND_HS
PLLGND
RESET C
LKON
100n

3303 10K

5K1 1%
4K7

AGND DGND 3V3I

2341

2343
220p

3345
1u0
26
32
36

14
46
47

41

49

3304 10K
2321

3322

G G

H H

I I

3139_243_34464_130_03_a2.pdf 2006-03-20

1 2 3 4 5 6 7 8 9 10 11 12 13 14
 Circuit Diagrams and PWB Layouts 3139 785 3220x 7. EN 34

Digital: Video Input Processor

1461 D7 T416 C9
1 2 3 4 5 6 7 8 9 10 11 12 13 2401 C9 T421 E6
2402 C9 T422 E6
2403 C9 T423 F7
2404 C9 T431 G10
2411 B9 T432 F10

Video Input Processor 2412 B9

2413 B9
2414 B9
2415 B9
T433 E7
T434 F10
T435 E7
T461 D7
2421 B7 T462 E7
A A 2422 B7
2423 B7
2424 B7
2425 B7
2426 B7
2427 B8
2431 C7
2432 C7
1V8BE 3V3BE 2433 C7
5421 5411
BLM18P T413 BLM18P T415 2434 C7
1V8A2 3V3A2 2435 C7
2453 F6
B B

100n

100n

100n

100n

100n

100n

100n

100n

100n
100n
330u 16V

10u 25V
2461 D7

2421

2411
2462 D7

2422

2423

2425

2426

2412

2413

2414

2415
2424

2427
2471 F5
2472 F5
2473 F5
1V8BE 3V3BE 2474 F5
5431 5401 2475 F5
BLM18P T414 BLM18P T416
1V8D2 3V3D2 2476 F5
2477 G5

100n

100n

100n

100n

100n

100n

100n
10u 25V
10u 25V
2478 G5

2401
2431
2479 G5

2432

2433

2434

2435

2402

2403

2404
C C 2480 G5
2481 G1
2482 G2
2483 G2
2484 G2
2485 G2
3V3D2
2486 G3

1V8D2

3V3D2
1V8A2

1V8A2

3V3A2
2487 G3
2488 G3
2489 G4

3450
2490 G4

10K
2461
33p 3407 E6
D Communication (COM) 4487 T461
D 3408 E6
3423 F4
Communication (COM)

12

76

78
11
14
25

20
21

31
41
55
67

38
48
61
3428 G4

1461
3461
1M0

4
5
3494
7402 REF PLL 1 2 3 4 1 2 3 4 DVDD IOVDD 3430 G4
BC847B 2462 70
100R 33p A18VDD CH CH 0 3450 D5
A18VDD A33VDD 69 3457 2K2
1 3451 G11
T462 66
2 3452 F6
74
1 Φ 3
65
3453 F6
Video Input Digital (VID)

64
XTAL NTSC/PAL/SECAM 4
75
2 C_ 5 63 3454 E7
22R 3482 T411 40
DATACLK VIDEO DECODER 6
60 3455 E6
59
22R 7 3456 F11
T421 3407 28 58
VIP_SCL SCL 8 3457 D11
E VIP_SDA
T422 3408 22R 29
SDA 9
57 E 3461 D7
GPIO
GPIO 3471 H1

Video Input Digital (VID)

T433 35 54 T400 3492-1 1 8 22R 3472 H1
FSS 0
2K2 3454 T435 37 53 T401 3492-2 2 7 22R
GLCO 1 3473 H2
4481 52 T402 3492-3 3 6 22R
100R I2CA 2 3474 H2
3455 T412 30 7401 51 T403 3492-4 4 5 22R
SYSRST# INTREQ 3 3475 H2
10K 3481 3452 10K 33 L2146PFP 50 T404 3488-1 1 8 22R
3V3D2 3V3D2 T423 PWDN 4
2453 100n 34
RESETB Y_ 5 47 T405 3488-2 2 7 22R 3476 H2
Video Input Analog (VIA)

3453 100R 46 T406 3488-3 3 6 22R 3477 H3

VIP_RST# 6
4482 VIA_BPb_2 2471 100n VIA_BPb_3 80 45 T407 3488-4 4 5 22R
A 7 3478 H3
1 44 T408 3486 22R
5402 600R B VI_1 8 3479 H3
VIA_SC_FR_2 2472 100n VIA_SC_FR_3 2 43 T409 3484 22R
C 9 3480 H4
F 3423 270R VIA_CVBS_FR_2 2473 100n VIA_CVBS_FR_3 7
8
A CS
72
F 3481 F5
3482 E7
B VI_2 HS
4483 VIA_GY_2 2474 100n VIA_GY_3 9
C GPIO 3484 F11
5403 600R VBLK T434 3486 F11
VIA_SY_FR_2 2475 100n VIA_SY_FR_3 16 73 4486
A VS 3488-1 F11
17
5404 600R B VI_3 GPIO
VIA_SY_RE_2 2476 100n VIA_SY_RE_3 18 71 T432 3456 2K2 3488-2 F11
C FID
GPIO 3488-3 F11
4484 VIA_RPr_2 2477 100n VIA_RPr_3 23 36 T431 3451 22R
A VI_4 AVID 3488-4 F11
3428 270R GPIO 3492-1 E11
VIA_CVBS_TU_2 2478 100n VIA_CVBS_TU_3 A18GND A33GND
A18GND CH CH 3492-2 E11
5405 600R AGND REF PLL 1 2 3 4 1 2 3 4 DGND IOGND GND_HS
VIA_SC_RE_2 2479 100n VIA_SC_RE_3 3492-3 E11

26

13

77

79
10
15
24

3
6
19
22

27
32
42
56
68

39
49
62

81
3492-4 E11
G 3430 270R VIA_CVBS_RE_2 2480 100n VIA_CVBS_RE_3
G 3494 D5
4481 E5
1%
1%

1%

1%

1%

1%

1%

1%

1%

1%

4482 F4
100p

100p
100p

100p

100p

100p

100p

100p

100p

100p

4483 F4
3472 75R
3471 75R

3473 75R

3474 75R

3475 75R

3476 75R

3477 75R

3478 75R

3479 75R

3480 75R

4484 G4
2482

2489
2481

2483

2484

2485

2486

2487

2488

2490

4486 F11
4487 D5
5401 C8
5402 F4
5403 F4
5404 F4
5405 G4
H H 5411 B8
5421 B6
5431 C6
7401 E9
7402 D5
T400 E10
T401 E10
T402 E10
T403 E10
T404 F10
T405 F10
I I T406 F10
T407 F10
T408 F10
T409 F10
T411 E7
T412 E7
T413 B7
3139_243_34464_130_04_a2.pdf 2006-03-20 T414 C7
T415 B9

1 2 3 4 5 6 7 8 9 10 11 12 13
 Circuit Diagrams and PWB Layouts 3139 785 3220x 7. EN 35

Digital: Interfaces

1501 C1 3572 F2 T516 C8 T672 F3

1 2 3 4 5 6 7 8 9 10 11 12 13 1502 H13 3573-1 G2 T517 A5 T673 F3
1511 A7 3573-2 G2 T518 A9 T674 G3
1512 A7 3573-3 G2 T519 A9 T675 G3
1521 A10 3573-4 G2 T520 A9 T676 G3
1522 A10 3574-1 G2 T521 A9 T677 G3

Interfaces 3V3BE 1536 A13 3574-2 G2 T522 B9 T678 G3

1537 C13 3574-3 G2 T523 B9 T679 G3
1541 F7 3574-4 G2 T524 B9 T680 G3

4K7

IEEE1394 Physical - Transport (PHY)

1551 D13 3575-1 G2 T525 B9 T681 G3
1552 D13 3575-2 G2 T526 B9 T682 G3
5VBE 7595 Video IO
NCP303LSN30 1571 F1 3575-3 G2 T527 B9 T683 G3
Audio IO

3595
1671 F3 3575-4 G2 T528 B9 T684 G3

Video Output Analog (VOA)

2 1536
A 7515
LD29150DT25R
INP
1 T517
IEEE1394
1521
30FMN-BMT-A-TFT
1522
24FMN-BMT-A-TFT 18FMN-BMT-A-TFT A 2502 I12 3576-1 G2 T529 C9 T685 G3

A u d i o (A U D )
OUTP SYSRST#
5 1512 T518 T536 2503 I11 3576-2 G2 T530 C9 T686 G3
T515 CD 1 1 1 1

100n
1 3 NC GND 1511 BM06B-SRSS-TBT T519 3537 22R T537
IN OUT 2V5BE 2 2 2 2 2505 H13 3576-3 H2 T531 C9 T687 G3
T611 T520 3538 22R T538
1 1 3 3 3 3 2506 H13 3576-4 H2 T532 C9 T688 H3
100n

100n
COM 6595 T612

22u 35V

2595

3
BAS316 2 2 4 4 4 4 2507 H13 3577 H2 T533 C9 T689 H3

2515
2596 22p T613 T521 3539 22R T539
3 3 5 5 5 5
T614 2508 H13 3578 H2 T534 C9 T690 H3
2516

2517
2
4 4 6 6 6 6
T615 T522 3540 22R T540 2511 D2 3579-1 H2 T535 C9 T691 H3
HOSTRST# 5 5 7 7 7 7
T616
6 6 8 8 8 8 2512 D2 3579-2 H2 T536 A13 T692 H3
7 T523 3541 22R T541
8 8 9 9 9 9 2513 D2 3579-3 H2 T537 A13 T693 H3
7
10 10 10 10 2515 A2 3579-4 H2 T538 A13 T694 H3
B6B-PH-SM4-TBT(LF) T524 3542 22R T542
11 11 11 11

Video Input Analog (VIA)

12 12
3543 22R T543
12 12
2516 B1 3580 I2 T539 A13 T695 H3
T525
B 13
14
13
14
3544 22R T544
13
14
13
14
B 2517 B2
2518 C2
3581 H2
3582 I2
T540 B13
T541 B13
T696 I3
T697 I3
T526
15 15 15 15 2519 C2 3583 I2 T542 B13 T698 I3
3545 22R T545
16 16 16 16 2520 C2 3584-1 I2 T543 B13 T699 I3
T527
5518 17 17 17 17
BLM31 T702 18 18
3547 22R T546
18 18
2521 C4 3584-2 I2 T544 B13 T700 I3
T528 2522 D3 3584-3 I2 T545 B13 T701 I3
3V3BE 19 19 19 19
3548 22R T547 20
20 20 20 2523 D4 3584-4 I2 T546 B13 T702 B2
100n

100n

T529
220u 16V

BAT760

BAT760

BAT760

BAT760
21 21 21 2525 D7 3585 F6 T547 B13 T703 C2
2518

6501

6502

6505

6506
T530 3549 22R T548
22 22 22 2526 D8 3586 F6 T548 C13 T704 C4
Power supply
2519

2520

23 23 23
1501 T531
24 24
3546 22R T549
24
2527 D6 3587 G6 T549 C13 T705 D7
B12B-PH-SM4-TBT(LF) 2528 D6 3588-1 G6 T551 D13
5VBE 25
T501 T532 24FMN-BMT-A-TFT
1 3521 3523 26 2529 D7 3588-2 G6 T552 D13
T502
C 2
T503
3V3 240R 1% 5K6 1% T533
27 1537
C 2541 C11 3588-3 G6 T553 E13

22p

22p

22p

22p

22p

22p

22p

22p

22p
3 28 2542 C12 3588-4 G6 T554 E13
T504 T534
4 5521 29
T505 T535 2543 C12 3589-1 G6 T555 E13

2541

2542

2543

2544

2545

2547

2548

2549

2546
5 12V BLM31 T704 30
T506 2544 C12 3589-2 G6 T556 E13
6
T507
7 2545 C12 3589-3 H6 T557 E13
100n

100n

T508 5511 330u 16V 7521

8 5V BLM31 T703 L5973D 2546 C13 3589-4 H6 T558 E13
2521

T509 8 6 T516
9
Φ VREF 2547 C12 3590 H6 T559 E13
T510 VCC 5525
2522

2523

HDDSW 10 10u T705

100n

100n

T511 1 2548 C12 3591 H6 T560 E13

220u 16V

11 OUT 1V8BE
2511

3 2549 C12 3592 H6 T561 E13

12 INH
5
2512

2513

FB 2552 F11 3593 H6 T562 E13

SS24
13 14 2
SYNC 2553 F11 3594 H6 T563 E13

100n
4

330u 16V
COMP 2556 F11 3595 A4 T564 E13

2529

2525
D D

22n
220p
GND GND_HS 2557 F11 3596 I6 T565 E13

22n

2526
7522

4523

6521
7 9 BC847B Communication 2558 F12 3597 I6 T566 F13
3529

2527

2528
5VBE 1K0 1551 1552 2559 F12 3671 F4 T567 F13
19FMN-BMT-A-TFT 17FMN-BMT-A-TFT 2561 F12 3672 F4 T568 F13
2562 F11 3673-1 G4 T571 F1

Communication (COM)
12K 1%

4K7 1%
T551
1 1

3522

3528

3530

3531
3552 22R T552 2563 F11 3673-2 G4 T572 F1

1K0

1K0
COM_SCL_2
2 2
3512

3553 22R T553

2K2

COM_SDA_2
3 3 2564 F11 3673-3 G4 T573 G1
3511

T554
2K2

3514 4 4 2565 F12 3673-4 F4 T574 G1

T555
100R 5 5 2566 F12 3674-1 G4 T575 G1
3556 22R COM_DHOST_1 T556
6 6 2567 F12 3674-2 G4 T576 G1
7 7
3557 22R COM_FPSCK_1 T557
8 8
2583 I2 3674-3 G4 T577 G1
BC857B T558
E 7511
HOSTRST#
T559
9
10
9
10
E 2595 A4
2596 A4
3674-4 G4
3675-1 G4
T578 G1
T579 G1
3515

3513

3562 22R T560

1K0

22R

COM_AINSEL0_1

3563 22R COM_AINSEL1_1 T561

11 11 2625 I10 3675-2 G4 T580 G1
12 12 2626 I10 3675-3 G4 T581 G1
3565 22R COM_FBSCRT_1 T562
13 13
3566 22R COM_SBSCRT0_1 T563
14 14
2683 I4 3675-4 G4 T582 G1
3567 22R COM_SBSCRT1_1 T564 3501 H11 3676-1 H4 T583 G1
3558 22R 15 15
T565
16 16 3502 H11 3676-2 G4 T584 G1
3559 22R COM_TUNDET0_1 T566
17 17 3503 I13 3676-3 G4 T585 G1
3561 22R HDMI_INT_1 T567
18 18 19 3504 I13 3676-4 G4 T586 G1
3564 22R COM_FANSW_1 T568
HDMI 3555 22R 19
3505 I13 3677 H4 T587 H1
40FLZ-RSM2-R-TB(LF)(SN) 3506 I13 3678 H4 T588 H1
5VBE

22p

22p

22p

22p

22p
22p

22p

22p

22p

22p

22p

22p

22p
1541 3507 H11 3679-1 H4 T589 H1
F F 3508 H11 3679-2 H4 T590 H1

2562

2563

2564

2565

2566
2552

2553

2556

2557

2567

2559

2561

2558
HDD_IDE 3511 E2 3679-3 H4 T591 H1
Video Output Digital (VOD)
Hard Disc Drive (HDD)

3569
ODD_IDE T620 41 42 3512 E2 3679-4 H4 T592 H1

2K2
1671 3585 33R 40
Optical Disc Drive (ODD)

1571 1-1734160-4 3671 10K T621 3513 E2 3680 I4 T593 H1

3568
2K2
5VBE 39 3560
1-1734160-4 3571 10K T671 HDD_RST#_1 3672 1 2 33R
5VBE 1 3586 33R 38 100R BC857B 3514 E2 3681 H4 T594 H1
T571 ODD_RST#_1 3572 33R T672 T622 7568
1 2 37 3515 E2 3682 H4 T595 I1
T572 T673 HDD_DD(7)_1 3673-4 4 5 33R 33R
2 3 3587 36 3521 C5 3683 I4 T596 I1
T573 ODD_DD(7)_1 3573-1 1 8 33R T674 HDD_DD(8)_1 3673-3 3 6 33R T623
3 4 35

3570
T574 3573-2 2 7 33R T675 3673-1 1 8 33R 3522 D5 3684-1 I4 T597 I1

22R
ODD_DD(8)_1 HDD_DD(6)_1
4 5 34

3551
3588-1 33R

1K0
T575 ODD_DD(6)_1 3573-3 3 6 33R T676 HDD_DD(9)_1 3673-2 2 7 33R T624 3523 C6 3684-2 I4 T598 I1
5 6 33
T576 ODD_DD(9)_1 3573-4 4 5 33R T677 HDD_DD(5)_1 3674-4 4 5 33R
6 7 3588-2 33R 32 3528 D6 3684-3 I4 T599 I1
T577 ODD_DD(5)_1 3574-1 1 8 33R T678 HDD_DD(10)_1 3674-3 3 6 33R T625
7 8 31 3529 D7 3684-4 I4 T600 I1
T578 ODD_DD(10)_1 3574-2 2 7 33R T679 HDD_DD(4)_1 3674-2 2 7 33R
8 9 3588-3 33R 30 3530 D6 4523 D5 T601 I1
T579 3574-3 3 6 33R T680 3674-1 1 8 33R T626
G 9
10
T580
ODD_DD(4)_1

ODD_DD(11)_1 3574-4 4 5 33R

10
11
T681
HDD_DD(11)_1

HDD_DD(3)_1 3675-4 4 5 33R T627

29
28
G 3531 D7 4581 H2 T605 I13
T581 ODD_DD(3)_1 3575-1 1 8 33R T682 HDD_DD(12)_1 3675-3 3 6 33R 3588-4 33R T628 3537 A11 4624 H11 T606 I13
11 12 27
T582 ODD_DD(12)_1 3575-2 2 7 33R T683 HDD_DD(2)_1 3675-2 2 7 33R 5513 BLM31 T629
12 13 5V 26 3538 A11 4681 H4 T607 I13
T583 ODD_DD(2)_1 3575-3 3 6 33R T684 HDD_DD(13)_1 3675-1 1 8 33R 3589-1 33R T630
13 14 25 3539 A11 5511 C2 T608 I13

100n
100n

100n

100n
T584 ODD_DD(13)_1 3575-4 4 5 33R T685 HDD_DD(1)_1 3676-4 4 5 33R 5514 BLM31 T631
14 15 3V3 24 3540 B11 5513 G6 T611 A7
T585 ODD_DD(1)_1 3576-1 1 8 33R T686 HDD_DD(14)_1 3676-3 3 6 33R 3589-2 33R T632
15 16 23
T586 ODD_DD(14)_1 3576-2 2 7 33R T687 HDD_DD(0)_1 3676-2 2 7 33R 3541 B11 5514 G6 T612 A7

2507
2505

2506

2508
16 17 3589-3 33R 22
T587 ODD_DD(0)_1 3576-3 3 6 33R T688 HDD_DD(15)_1 3676-1 1 8 33R T633 3542 B11 5518 B2 T613 A7
17 18 21
T588 ODD_DD(15)_1 3576-4 4 5 33R 3501 10K
18 19 3589-4 33R 20 5V 3543 B11 5521 C3 T614 A7
3677 4K7 T634 3502 10K
19 20 19 3544 B11 5525 D7 T615 B7
3577 4K7 T689 HDD_DMARQ_1 3678 33R 33R 3507 10K CHASSIS1 CHASSIS2 CHASSIS3 CHASSIS4
20 21 3590 18 3545 B11 6501 C7 T616 B7
T589 ODD_DMARQ_1 3578 33R T636 3508 10K
21 22 17
22 23
T690 HDD_DIOW#_1 3679-1 1 8 33R 33R 16
3546 C11 6502 C7 T620 F7
3591
T590 3579-1 1 8 33R 3679-4 4 5 33R T637
H 23
24
ODD_DIOW#_1
ODD_DIOR#_1 3579-2 2 7 33R
24
25
T691
HDD_DIOR#_1
HDD_IORDY_1 3679-3 3 6 33R
3592 33R
15
14
H 3547 B11
3548 B11
6505 C7
6506 C7
T621 F7
T622 F7
T591 ODD_IORDY_1 3579-3 3 6 33R HDD_DMACK#_1 3679-2 2 7 33R T638
25 26 13 3549 C11 6521 D7 T623 G7
ODD_DMACK#_1 3579-4 4 5 33R T692 3681 4K7 33R 7501
26 27 5VBE 3593 12 3551 G10 6595 A5 T624 G7
T592 3581 4K7 T693 4681 T639 TPS2051AD
27 5VBE 28 11

4624
28
T593 4581
29
T694 33R 10 3552 D10 7501 H11 T625 G7
T594 3594 T640
29 30 9 USB 3553 E10 7511 E2 T626 G7
T695 HDD_INTRQ_1 3682 33R 4 6 1502
30 31 3596 33R 8 EN 1 3555 F10 7515 A2 T627 G7
T595 ODD_INTRQ_1 3582 33R 3683 680R T641 B4B-PH-SM4-TBT(LF)
31 32 7 3556 E10 7521 C4 T628 G7
3583 680R T696 2683 22p 33R 2 OUT 2 7 5V_USB T605
32 33 3597 6 5V 1 1 3557 E10 7522 D6 T629 G7
T596 2583 22p HDD_DA(1)_1 3680 33R T642 3503 22R T606
33 34 5 IN 2
34
ODD_DA(1)_1 3580 33R
35
T697 HDD_DA(0)_1 3684-3 3 6 33R
4
3
2 3
8 3504 22R T607
3
3558 E10 7568 F10 T630 G7

100n
T597 3584-1 1 8 33R T698 3684-4 4 5 33R 3505 15K T608 3559 F10 7595 A4 T631 G7

22u 35V
ODD_DA(0)_1 HDD_DA(2)_1
35 36 3 4

100n

100n
2625
T598 ODD_DA(2)_1 3584-4 4 5 33R T699 HDD_CS0#_1 3684-1 1 8 33R 5 3506 15K
36 37 2 OC_ 3560 F9 T501 C1 T632 G7

GND
T599 3584-2 2 7 33R T700 3684-2 2 7 33R 6 5
I ODD_CS0#_1 HDD_CS1#_1
I

2626
37 38 T644 1 3561 F10 T502 C1 T633 H7
T600 ODD_CS1#_1 3584-3 3 6 33R

2503

2502
38 39 3562 E10 T503 C1 T634 H7
T701
39 40
T601 3563 E10 T504 C1 T636 H7

1
40
3564 F10 T505 C1 T637 H7
3565 E10 T506 C1 T638 H7
3566 E10 T507 C1 T639 H7
3567 E10 T508 C1 T640 H7
3568 F10 T509 C1 T641 I7
3569 F10 T510 D1 T642 I7
3139_243_34464_130_05_a2.pdf 2006-03-20 3570 G10 T511 D1 T644 I7
3571 F2 T515 A2 T671 F3

1 2 3 4 5 6 7 8 9 10 11 12 13
 Circuit Diagrams and PWB Layouts 3139 785 3220x 7. EN 36

Layout: Digital-Main Part (Top View)

DVDR3455D_TopView.pdf 2006-05-25
 Circuit Diagrams and PWB Layouts 3139 785 3220x 7. EN 37

Layout: Digital-Main Part (Bottom View)

DVDR3455D_BtmView.pdf 2006-05-25
 Circuit Diagrams and PWB Layouts 3139 785 3220x 7. EN 38

Power Supply Unit: Schematic

3139_247_12862.pdf 2006-05-31
 Circuit Diagrams and PWB Layouts 3139 785 3220x 7. EN 39

Power Supply Unit: Layout

The PSU
Layout is not
available
 Circuit Diagrams and PWB Layouts 3139 785 3220x 7. EN 40

Notes:
 Circuit- and IC description 3139 785 3220x 8. EN 41

8. Circuit- and IC description

8.1. PSU Board The Mains must be disconnected from the Set before
attempting the procedure mentioned below:
8.1.1. General
The PSU is designed with short-circuit protection that
will shutdown the power supply. When this happen,
the voltage stored in capacitor C1 and C40 will prevent
the Power Supply to turn-on, therefore they must be
discharged with a screwdriver with high electrical
isolation handle before the PSU can function normally
again.

Note: During the process of discharging the capacitors,

spark can be observed which is typical of the high
voltage stored in Capacitor C1 and C15.

Figure 8-1 PSU Board Layout

The PSU board provides the following connection to the

rest of the set:

• Connector A: Supply/Signal to Analog Board

Conn. 1401
• Serve as supply to Digital Board

Pin no. Supply / Signal Remarks

1 12V
2 GND
3 5V
4 3.3V
5 GND

• Connector B: Supply/Signal to Analogue Board

Conn. 1402
• Serve as 12VBE to Digital Board,only supplied upon
triggered by STBYn lines from transistor 7421(Analog
Board)

Pin no. Supply / Signal Remarks

1 VGN
2 5N
3 GND
4 IP_FAIL HIGH>4.0v = power good
LOW<4.0v =power fail
5 GND
6 12V
 EN 42 8. 3139 785 3220x Circuit- and IC Description

8.2. Front Board (Panel – Display + Key) 8.3. Analog Board

8.2.1. General 8.3.1. General

The PCBA consist of the following parts:
This board consists of the following parts: • Fan Control
• FIP Control Driver • Tuner Frontend
• Frontend (Audio & Video) • Audio ADC/DAC
• VFD Heater voltage Generator
8.3.2. Tuner Frontend [1100 : TMQZ2]
8.2.2. FIP Control Driver (IC 7105: UPD16316GB)
The Analog board supports 2 possible Tuner Frontend
The core element of the Front Display + Keyboard is unit namely:
the FIP Control Driver. It runs on a 5V supply and is • 1101 – PAL BG,DK and I Broadcast System
responsible for the following functions: • 1100 – NTSC-M Broadcast System
• Interface with the Domino chip on the Digital Board
• Evaluation of the keyboard matrix within Front board It has a RF IN for antenna connection and RF OUT which
• Decoding the remote control commands from the provides a RF loop through for connection to the TV.
infra-red receiver The Frontend ( Tuner & IF-demodulator ) is controlled
• Activation and control of the display by I2C (SCL_5V- and SDA_5V-) lines coming from the
• Timer Wake-up activation Domino Host on the Digital board.
Complete video processing is done in this unit and the
It runs on two clock frequencies namely: video output (CVBS) is taken out from the [VIDEO_OUT]
• 5MHz for normal operation pin 13 via a transistor as CVBS_TV-line to the Video I/O
• 32.768KHz for the real time clock circuitry. The audio-IF component SIF1 is taken out from
the [SIF_OUT] pin 10 for the demodulation by the Multi-
8.2.3. Interface to the Domino chip sound processor (MSP).

It communicates with the Domino Host on the Digital Audio demodulator

board via a 6-wire synchronous serial interface. The The sound demodulation is done by the MSP3425 [7304],
Host is always the master to generate the communication which is also fully controlled via I2C bus by the Domino
clock to the FIP Control Driver irrespective of the Host. The audio signals are available at pin 30 and pin 31
direction of data transfer. and fed as AIA_R_MSP & AIA_L_MSP line to the audio I/O
for further processing.
8.2.4. Evaluation of the keyboard matrix

A key matrix is used on the Front board. The slave μP

does the key scanning with FIP9 - FIP24 (pin 23-26 and
29-40) as output and KEY_A - KEY_C (pin 41-43) as input.
Each key is assigned a key code based on the output
and input ports, and the FIP Control Driver will do the
evaluation by getting the key code.

8.2.5. IR receiver and signal evaluation

The IR receiver on the Front Board contains a selectively

controlled amplifier as well as a photodiode. The photo-
diode changes the received infrared transmission
to electrical pulses, which are then amplified and
demodulated. On the output of the IR receiver, a pulse
sequence with TTL-level, which corresponds to the
envelope curve of the received IF remote control
command can be measured. This pulse sequence is fed
into the FIP Control Driver for further processing via pin
13.

8.2.6. Vacuum Fluorescent Display [1203: HUV-08SS65T]

The VFD is fully controlled and driven by the FIP Control

Driver.

8.2.7. VFD Heater Voltage Generator

The oscillator circuit provided by [5100, 2101, 2102

& 7100] provides the necessary sine wave signal
transistors [7101, 7102 & 7103] to generate the 50% duty-
cycle 48KHz AC square-wave signal for the filament of
the VFD.

8.2.8. Timer Wake-up activation

During the Standby mode, the FIP Control Driver provides

a wakeup service (POWER_CTL-line switches to high),
then the Domino Host (on the Digital Board) starts up and
asks for the wake-up reason.
 8.3.3.

Audio IO
AIA_R_RE2
REAR IN-EXT2
Audio routing

(CVBS / YC)
AIA_L_RE2

MSB/LSB
AFEL LL
HEF4052B
AIA_R_RE1 1 POS:7201
REAR IN-EXT 1 AINFL LH
(YUV) 5
3 H
AIA_L_RE1 3
AIN1L HL L
0dB
2

AIN2L HH
45
UDA1361TS
AFER LL POS:7203
CS4351 12
POS:7206
ALADC
VOR AOUTA 1 A_DATA
D_DATA 16 AINFR LH
14 H ADC
13 ARADC
DAC AIN1R HL 0dB
L 3
15 to FEBE /
from FEBE / AOUTB digital board
digital board 14
VOL AIN2R HH
11
Logic
MSB LSB

AMUTEC BMUTEC 9 10 6 BMUTEC

AKILL
MUTE
MUTE
AOUTA
AR
DKILL IPFAIL REAR OUT2
AKILL
AOUTB (CVBS / YC)
AL
AKILL

MUTE
Circuit- and IC description

MSP3415G

Figure 8-2 Analog Audio IO

AMUTEC
SIF1 AR
2 Demodulator
REAR OUT1
(YUV)
AL
AINFR

40 AIA_R_MSP
SC1_OUT_R
AINFL 30
41 Dig.Audio Out
SC1_OUT_L 31 DA OUT

Source select
ALDAC AIA_L_MSP
37 from digital
Tuner SIF1
DACM_R
26 board
ARDAC AMCO
38
3139 785 3220x

AMCO Q.Peak Det DACM_L 27

Modulator
I2C Control Optical Audio Out (OPTION)

12 13 8 9
SCL_5V RSA2
from CU RSA1
SDA_5V
8.
EN 43
 EN 44 8. 3139 785 3220x Circuit- and IC Description

The sound processing is always done in stereo (that

means separate left- and right- channel) and the complete
switching is realized by using HEF4052, which is a dual
four-to-one multiplexer and MSP3415G, multi-sound
processor.

a) Record path
The complete selection of audio signal for recording is
done by a HEF4052 [7201], which is a dual four-to-one
multiplexer. The input lines for the selector [7301] are
coming either from MSP [7304] (AIA_L_MSP/AIA_R_MSP)
or cinch rear-in Ext AIA_R_RE1/AIA_L_RE1) or the cinch
front-in (AIA_R_FR/AIA_L_FR). The [7201] controlled via
RSA1- and RSA2- signals coming from the MSP [7500].
The MSP acts as a port expander of the FIP Control
Driver. The Op-Amp on the output [7201] is necessary
for performance reasons and acts also as a driver. The
selected signals ALADC* and ARADC* are directly fed to
the Audio-ADC. As there is also a fifth input (DV-in), the
corresponding audio signals (ALDAC*/ARDAC*) from the
Digital board are routed via the MSP [7304] and output as
AIA_R_FR/AIA_L_FR to selector [7201]

b) Cinch out
The Multiplexer (HEF7201) selects signals from a few
sources, namely Rear Cinch In (AIA_R_RE1/AIA_L_RE1),
Front Cinch In (AIA_R_FR/AIA_L_FR) and MSP (AIA_L_
MSP/AIA_R_MSP). The multiplexer is controlled via RSA1
and RSA2 signals coming from the MSP.

c) Digital audio-out path

In addition to the analog output the set is also equipped
with a digital audio output via cinch plug [1131]. The
signal is generated on the digital board and routed
via the audio interface cable and connector [1600] to
the Analog board. Here the DAOUT-line first passes
a 6-fold inverter [7700] being used as a driver and for
performance reasons (noise reduction, jitter,etc).

8.3.4. Audio ADC/DAC

The conversion of analog audio signals (ALADC*/

ARADC*) from the record-selector [7201] is done via
AID_DAT [7203]. This IC can process input signals up
to 2Vrms by using external resistors in series to the
input pins. All required clock signals are generated on
the digital board and only the audio data (AID_DAT)
are routed from the Analog to Digital board for further
processing.

The transformation of digital audio back into analog

domain is done by CS4351 [7206]. All necessary clock
signals are coming from the digital board and digital
audio data (D_DATA0-line) are converted into analog
signals (pin 15 and 18). The output signals from the
audio DAC part (AOUTA/AOUTB) are directly routed to
the rear cinch sockets. To avoid plops and any other
audible noise on the output there is a mute-stage
implemented for each channel. The activation of the mute
function is done via the AMUTEC & BMUTEC (digital
silence mute) from the audio DAC and also the AKILL line
which is a combination of the D_KILL from the Digital
board and POWER_FAIL from power supply.

*Note: ALADC refers to VINL of IC7203

ARADC refers to VINR of IC 7203
 Video IO
8.3.5.

REAR OUT1
OUT
Y U (Pb) V (Pr)

VIA_RPr

VIA_BPb
Video routing

VIA_GY

D_CVBS

VOA_SY
OUT2

From digital board

CVBSR_OUT

VOA_SC
REAR OUT

Y/C
VY_OUT

CVBS
CVBS_REAR
S-CONN

CR_OUT

Y/C WSRO
Y_REAR

REAR IN -EXT2
C_REAR

WSRI
to CU

CVBS
CVBS_REAR
Circuit- and IC description

Y_REAR

Figure 8-3 Analog Video IO

C_REAR

FRONT IN
CVBS_FIN

Y_FIN
C_FIN
A_V
To digital board

A_U
A_Y
CVBS_TV

TUNER
3139 785 3220x

REAR IN-EXT1
IN-1
Y U (Pb) V (Pr)
8.
EN 45
 EN 46 8. 3139 785 3220x Circuit- and IC Description

The switching of the various video input signals is done video encorder, and provides build-in support for non-
by the Video Input Processor on the Digital Board. These simultaneous progressive and interlaced video output.
signals are directly routed to the digital board through A 1394 link layer function is also integrated, requiring
connector 1122 on the Analog Board only a simple external physical layer device. The board
encodes and multiplexes analogue video and digital
8.4. Digital Board uncompressed audio (I2S) into an MPEG2 stream. This
MPEG2 stream is formatted for recording by the DVD+RW
engine. In the playback, the board will decode the MPEG2
The Digital Board is based on the highly integrated LSI
video into analogue video. In addition, a DV stream can
‘Domino’ BGA chip (Ball Grid Array), DMN-8652. This IC
be received via IEEE 1394 (i-Link), and transformed to
has 2 on-chip ATAPI controller and integrates an analog
MPEG2 format.

8.4.1. Record Mode

TO/FROM FRONTEND PART

ATAPI

7401
7101
VIP ITU656
TVP5146

DMN 8652
I2C
1FH VIDEO
(2)
OUT

CLOCK
13.5MHz DIG. AUDIO OUT
7211/7231

DDR SDRAM I2S A UDIO OUT

16M X 16Bit

I2S A UDIO IN

(1)
For DV-in version only 7294 1FH VIDEO IN
7304
1394 FLASH
TSB41AB1 16M Bit

3V3 5V 12V
1512 (1) analogue CVBS / YC and RGB/YUV
(2) analogue CVBS, YC, RGB/YUV
1394 FROM POWER SUPPLY
CONNECTOR

Figure 8-4 Domino block

 Circuit- and IC description 3139 785 3220x 8. EN 47

Video Part Front-end I2S

The digital video input signals from the DV-in on the The Domino chip interfaces directly to the basic Engine
Front board are routed from connector 1521 via the IEEE via ATAPI connector 1571.
1394 PHY IC [7301] to the Domino chip [7101]. It buffers the data streams that are coming from (or going
to) the Basic Engine.
The Video Input Processor encodes the analogue video In the Domino chip, the video MPEG2 stream and the
to digital video stream (CCIR656 format). The output audio AC3 stream are sent to the basic Engine for
stream, named VID_D (0:9), is then routed to the Domino recording through ATAPI bus.
chip. This IC encodes and decodes the digital video
stream into / from MPEG2 format. 8.4.2. Playback mode
During playback, the data from the Basic Engine is going
directly to the Domino chip via ATAPI interface. The
Audio Part Domino chip has the following outputs:
I2S audio is sent from the Analog board to the Domino • Analogue video CVBS, YC and RGB outputs on
chip via connector 1536. connector 1521
The Domino chip compresses the I2S audio data into an • I2S audio (PCM format) on connector 1536
MPEG1-L2 / AC3 audio stream. • SPDIF audio (digital audio output) on connector 1536

8.4.3. Basic Engine Interface

The Digital board is equipped with an IDE bus (ATAPI) for
connecting to the Basic Engine.

8.4.4. Clock Distribution

FRONTEND INTERFACE

14.31818MHz

7401
VIP 7101
TVP5146
7211
150 MHz
SDRAM
DMN 8652

7301 7231

1934 PHY SDRAM

24.576 MHz 13.5 MHz

Figure 8-5 DIMINO_CLOCK

The Domino chip has a complex system, which is needed System clocks:
to support the processes running at different frequencies • DMN-8652 (7101, pin A1 and A2) : 13.5 MHz provided
such as video decoding, audio decoding or peripheral by the x’tal 1101
I/O devices etc. To ensure a synchronous initialization • DMN-8652 1394-LINK (7101, pin K1) : 49.152MHz
of all the registers and state machines, all the PLLs are provided by 1394-PHY
switched to their default frequency 27MHz. • TVP5146 (7401, pin 74 and 75) : 14.31818MHz
Then when the booting control unit is correctly initialized provided by x’tal 1461
and once it has captured all the booting parameters, it • SDRAM (7211 and 7231, pin 45 and 46) : 150MHz
sets the PLLs to its functional frequencies. Thanks to a provided by the DMN-8652
clock blocking mechanism, the frequency switching is • TSB41AB1PHP IEEE 1394 PHY IC (7301, pin 42 and
glitch free. 43) : 24.576MHz provided by x’tal 1351
 EN 48 8. 3139 785 3220x Circuit- and IC Description

8.4.5. Power Supply

The Digital board is not powered in standby mode. The • 2.5V supply for the SDRAM is generated by an ultra
control signal STBY on the analog board will enable the fast low dropout linear regulator [7515]
PSU and power the digital board. • 1.25V DDR termination supply is generated by
• STBY = Low: the digital board is in powered down regulator [7201]
standby mode
• STBY = High: the power supply to the digital board is
enabled. 8.4.6. Memory
The 3V3, +5V and +12V come from the PSU, while the • FLASH IC7294: this memory contains the boot
following voltages are generated in the digital board: parameters and application firmware
• 1.8V core voltage is generated on the board by a 2A
switching step down voltage regulator [7521]

8.4.7. Reset
5V Supply HOSTRST FRONT
MICROPROCESSOR

SYSRST# IDE_RST#_1
DMN 8652 Basic Engine
Delay t1 VAD8041
Delay t2

POWER ON
RESET & LOW
VOLTAGE
DETECTION
NCP303LSN30 VID_RST# VIP (TVP5146)
IC7595 Delay t2
VIP_RST#

LNK_RST# PDI1394P25BD
Delay t2

FLASH MEMORY
RSTn Delay t1

Figure 8-6 DOMINO_RESET

Reset concept Digital board 8.4.8. I/O Connector

The rest circuitry [7595] takes cares that the different
devices on the digital board are boot-up in the correct Audio IO Connector (item 1536)
order. At power on the reset circuitry provides the The Audio In/Out (AIO) connector is used to interchange
following resets (delay τ1): digital audio signals between the Analog and Digital
• SYS_RST# to the Domino chip [7101] and Flash board
Memory [7294]
Video IO Connector (item 1521)
The Domino chip then generates other reset signals The Video In/Out (VIO) Connector is used to interchange
(delay τ2) via its GPIOs: analogue video signals between the Analog and Digital
• VID_RST# to reset the VIP [7401] board
• LNK_RST# to reset the IEEE1394 DV PHY IC [7301]
• IDE_RST#_1 to reset Basic Engine
 Circuit- and IC description 3139 785 3220x 8. EN 49

8.5 IC Description

8.5.1 Analog Board

IC7304 - Multistand Sound Processor Family

BLOCK DIAGRAM

23 24 28 32 33 1 19 34

MSP34x5G

N.C.
N.C.

N.C.
N.C.

AHVSUP

AVSUP

CAPL_M
DVSUP
2 ANA_IN+ DACM_L 27
Loud-
De- Pre- speaker
ADC Modulator processing DAC
3 ANA_IN- sound DACM_R 26
proeessing

17 I2S_DA_IN1 Loud-
Pre- speaker I2S_DA_OUT 16
processing sound
21 I2S_DA_IN2
proeessing
Source
39
ASG select
40 SC1_IN_L

41 SC1_IN_R

SCART
DSP SC1_OUT_L 31
37 SC2_IN_L input
select ADC Prescale DAC
SCART SC1_OUT_R 30
38 SC2_IN_R
Output
select

43 MONO_IN

10 ADR_SEL D_CTR_I/O-0 9
I2C I2S X'tal
12 I2C_CL ADR BUS D_CTR_I/O-1 8
Control Control Oscillator
13 I2C_DA STANDBYQ
VREFTOP

RESETQ

TESTEN
AGNDC
AHVSS
XTAL_OUT

VREF2
VREF1
DVSS
AVSS
XTAL_IN
ADR_CL

I2S_CL

I2S_WS

TP
18 14 5 6 35 36 20 25 42 11 4 7
15 44 29 22

Figure 8-8
 EN 50 8. 3139 785 3220x Circuit- and IC Description

PIN CONFIGURATION
NC

VREF1 DACM_L
SC1_OUT_R DACM_R
SC1_OUT_L VREF2
NC NC
AHVSUP NC

33 32 31 30 29 28 27 26 25 24 23
CAPL_M 34 22 RESETQ
AHVSS 35 21 I2S_DA_IN2
AGNDC 36 20 DVSS
SC2_IN_L 37 19 DVSUP
SC2_IN_R 38 18 ADR_CL
ASG 39 MSP 34x5G 17 I2S_DA_IN1
SC1_IN_L 40 16 I2S_DA_OUT
SC1_IN_R 41 15 I2S_WS
VREFTOP 42 14 I2S_CL
MONO_IN 43 13 I2C_DA
AVSS 44 12 I2C_CL
1 2 3 4 5 6 7 8 9 10 11

AVSUP STANDBYQ
ANA_IN1+ ADR_SEL
ANA_IN− D_CTR_I/O0
TESTEN D_CTR_I/O1
XTAL_IN TP

XTAL_OUT

PMQFP44 package
Figure 8-9

IC7206 - 192KHz Stereo DAC with 2vrms line-out

BLOCK DIAGRAM

1.8 V to 3.3V 3.3 V 9 V to 12 V

Hardware or I 2C/SPI
Control Data

Register/Hardware
Configuration
Reset
Interpolation Multibit Amp
2 Vrms Line Level
Filter with ΔΣ Modulator DAC +
Left Channel Output
Volume Control Filter
Level Translator

PCM
Serial Audio Input Serial
Interface
Interpolation 2 Vrms Line Level
Multibit Amp
Filter with
Volume Control
ΔΣ Modulator DAC + Right Channel
Filter Output

Auto Speed Mode

External
Detect Left and Right
Mute
Internal Voltage Control Mute Controls
Reference

Figure 8-10
 Circuit- and IC description 3139 785 3220x 8. EN 51

PIN DESCRIPTION AND CONFIGURATION

SDIN 1 20 VL
SCLK 2 19 AMUTEC
LRCK 3 18 AOUTA
MCLK 4 17 VA_H
VD 5 16 GND
GND 6 15 AOUTB
DIF1(SCL/CCLK) 7 14 BMUTEC
DIF0(SDA/CDIN) 8 13 VQ
DEM(AD0/CS) 9 12 VBIAS
RST 10 11 VA

Pin Name # Pin Description

SDIN 1 Serial Audio Data Input (Input) - Input for two’s complement serial audio data.
SCLK 2 Serial Clock (Input) - Serial clock for the serial audio interface.
LRCK 3 Left / Right Clock (Input) - Determines which channel, Left or Right, is currently active on the serial
audio data line.
MCLK 4 Master Clock (Input) - Clock source for the delta-sigma modulator and digital filters.
VD 5 Digital Power (Input) - Positive power supply for the digital section.
GND 6 Ground (Input) - Ground reference.
16
RST 10 Reset (Input) - Powers down device and resets all internal resisters to their default settings when
enabled.
VA 11 Low Voltage Analog Power (Input) - Positive power supply for the analog section.
VBIAS 12 Positive Voltage Reference (Output) - Positive reference voltage for the internal DAC.
VQ 13 Quiescent Voltage (Output) - Filter connection for internal quiescent voltage.
VA_H 17 High Voltage Analog Power (Input) - Positive power supply for the analog section.
VL 20 Serial Audio Interface Power (Input) - Positive power for the serial audio interface

BMUTEC Mute Control (Output) - Control signal for optional mute circuit.
14
AMUTEC 19
AOUTB 15 Analog Outputs (Output) - The full scale analog line output level is specified in the Analog Characteris-
AOUTA 18 tics table.
Control Port
Definitions
SCL/CCLK 7 Serial Control Port Clock (Input) - Serial clock for the control port interface.
SDA/CDIN 8 Serial Control Data (Input/Output) - Input/Output for I2C data. Input for SPI data.

AD0/CS 9 Address Bit 0 / Chip Select (Input) - Chip address bit in I2C Mode. Control Port enable in SPI mode.
Stand-Alone
Definitions
DIF0 8 Digital Interface Format (Input) - Defines the required relationship between the Left Right Clock, Serial
DIF1 7 Clock, and Serial Audio Data.
DEM 9 De-emphasis (Input) - Selects the standard 15μs/50μs digital de-emphasis filter response for 44.1 kHz
sample rates
EN 52 8. 3139 785 3220x Circuit- and IC Description

IC7203 - 96KHz Sampling 24-bit stereo audio ADC

BLOCK DIAGRAM

dth VDDA VSSA VRP VRN Vref SYSCLK

16 15 5 4 2 8
9
VDDD
UDA1361TS 10
VSSD

1
VINL ADC
ΣΔ

14
MSSEL
DECIMATION CLOCK
FILTER CONTROL 7
PWON

3
VINR ADC
ΣΔ

13
DATAO
11 DIGITAL DC-CANCELLATION 6
BCK SFOR
12 INTERFACE FILTER
WS

MGT451

Figure 8-11

PIN DESCRIPTION AND CONFIGURATION

SYMBOL PIN DESCRIPTION

VINL 1 left channel input
Vref 2 reference voltage
handbook, halfpage
VINR 3 right channel input VINL 1 16 VDDA

VRN 4 negative reference voltage Vref 2 15 VSSA

VRP 5 positive reference voltage VINR 3 14 MSSEL

SFOR 6 data format selection input VRN 4 13 DATAO
PWON 7 power control input UDA1361TS
VRP 5 12 WS
SYSCLK 8 system clock 256, 384, 512 or 768fs
SFOR 6 11 BCK
VDDD 9 digital supply voltage
PWON 7 10 VSSD
VSSD 10 digital ground
BCK 11 bit clock input/output SYSCLK 8 9 VDDD

WS 12 word select input/output MGT452

DATAO 13 data output

MSSEL 14 master/slave select
VSSA 15 analog ground
VDDA 16 analog supply voltage
 Circuit- and IC description 3139 785 3220x 8. EN 53

8.5.2 Digital Board

IC7301 - IEEE 1394a-2000 one port cable Transceiver/Arbiter

BLOCK DIAGRAM

CPS
LPS Received Data
ISO Decoder/Retimer
Link
CNA† Interface
I/O

SYSCLK
LREQ TPA+
CTL0
TPA–
CTL1
D0
D1
D2
Cable Port
D3
D4 Arbitration TPB+
D5 and Control TPB–
D6 State Machine
D7 Logic

PC0
PC1
PC2
C/LKON

R0 Bias Voltage
R1 and
Current
TPBIAS Generator

Crystal
XI
Oscillator,
Transmit Data XO
PLL System,
PD Encoder FILTER0
and Clock
RESET FILTER1
Generator

† CNA output is only available in the 64-pin PAP package

Figure 8-12
EN 54 8. 3139 785 3220x Circuit- and IC Description

PIN CONFIGURATION

PHP package terminal diagram

PHP PACKAGE
(TOP VIEW)

PLLGND

FILTER1
FILTER0
PLLVDD

RESET
DGND
DGND
DVDD
DVDD
LREQ

XO
XI
48 47 46 45 44 43 42 41 40 39 38 37
SYSCLK 1 36 AGND
CTL0 2 35 AVDD
CTL1 3 34 R1
D0 4 33 R0
D1 5 32 AGND
D2 6 31 TPBIAS
TSB41AB1
D3 7 30 TPA+
D4 8 29 TPA–
D5 9 28 TPB+
D6 10 27 TPB–
D7 11 26 AGND
PD 12 25 AVDD
13 14 15 16 17 18 19 20 21 22 23 24
DV DD
PC0
PC1
PC2

SE
DGND

ISO
CPS
LPS

C/LKON

TESTM

SM

Figure 8-13
 Circuit- and IC description 3139 785 3220x 8. EN 55

PIN DESCRIPTION

TERMINAL
TYPE I/O DESCRIPTION
NAME PHP NO.
AGND 26, 32, 36 Supply – Analog circuit ground terminals. These terminals should be tied together to the
low-impedance circuit board ground plane.
AVDD 25, 35 Supply – Analog circuit power terminals. A combination of high frequency decoupling
capacitors near each terminal is suggested, such as paralleled 0.1 μF and 0.001
μF. Lower frequency 10 μF filtering capacitors are also recommended. These
supply terminals are separated from PLLVDD and DVDD inside the device to provide
noise isolation. They should be tied at a low-impedance point on the circuit board.
C/LKON 15 CMOS I/O Bus manager contender programming input and link-on output. On hardware reset,
this terminal is used to set the default value of the contender status indicated during
self-ID. Programming is done by tying the terminal through a 10-kΩ resistor to a high
(contender) or low (not contender). The resistor allows the link-on output to override
the input. However, it is recommended that this terminal should be programmed
low, and that the contender status be set via the C register bit.
If the TSB41AB1 is used with an LLC that has a dedicated terminal for monitoring
LKON and also setting the contender status, then a 1-kΩ series resistor should be
placed on the LKON line between the PHY and LLC to prevent bus contention.
Following hardware reset, this terminal is the link-on output, which is used to notify
the LLC to power up and become active. The link-on output is a square-wave signal
with a period of approximately 163 ns (8 SYSCLK cycles) when active. The link-on
output is otherwise driven low, except during hardware reset when it is
high-impedance.
The link-on output is activated if the LLC is inactive (LPS inactive or the LCtrl bit
cleared) and when:
a) the PHY receives a link-on PHY packet addressed to this node, or
b) the PEI (port-event interrupt) register bit is 1, or
c) any of the CTOI (configuration-time-out interrupt), CPSI
(cable-power-status interrupt), or STOI (state-time-out
interrupt) register bits are 1 and the RPIE (resuming-port
interrupt enable) register bit is also 1.
Once activated, the link-on output continues active until the LLC becomes active
(both LPS active and the LCtrl bit set). The PHY also deasserts the link-on output
when a bus reset occurs unless the link-on output would otherwise be active
because one of the interrupt bits is set (that is, the link-on output is active due solely
to the reception of a link-on PHY packet).
NOTE: If an interrupt condition exists which would otherwise cause the link-on
output to be activated if the LLC were inactive, the link-on output is activated when
the LLC subsequently becomes inactive.
CNA N/A CMOS O Cable-not-active output. This terminal is asserted high when there is no incoming
bias voltage.
CPS 20 CMOS I Cable power status input. This terminal is normally connected to cable power
through a 400-kΩ resistor. This circuit drives an internal comparator that is used to
detect the presence of cable power. This terminal should be tied directly to DVDD
supply if application does not require it to be used.
CTL0 2 CMOS I/O Control I/Os. These bidirectional signals control communication between the
CTL1 3 TSB41AB1 and the LLC. Bus holders are built into these terminals.
D0 4 CMOS I/O Data I/Os. These are bidirectional data signals between the TSB41AB1 and the
D1 5 LLC. Bus holders are built into these terminals.
D2 6
D3 7
D4 8
D5 9
D6 10
D7 11
EN 56 8. 3139 785 3220x Circuit- and IC Description

TERMINAL
TYPE I/O DESCRIPTION
NAME PHP NO.
DGND 14, 46, 47 Supply – Digital circuit ground terminals. These terminals should be tied together to the
low-impedance circuit board ground plane.
DVDD 21, 44, 45 Supply – Digital circuit power terminals. A combination of high-frequency decoupling
capacitors near each terminal is suggested, such as paralleled 0.1 μF and
0.001 μF. Lower frequency 10 μF filtering capacitors are also recommended.
These supply terminals are separated from PLLVDD and AVDD inside the device to
provide noise isolation. They should be tied at a low-impedance point on the circuit
board.
FILTER0 38 CMOS I/O PLL filter terminals. These terminals are connected to an external capacitor to form
FILTER1 39 a lag-lead filter required for stable operation of the internal frequency multiplier PLL
running from the crystal oscillator. A 0.1 μF ±10% capacitor is the only external
component required to complete this filter.
ISO 19 CMOS I Link interface isolation control input. This terminal controls the operation of output
differentiation logic on the CTL and D terminals. If an optional Annex J type isolation
barrier is implemented between the TSB41AB1 and LLC, the ISO terminal should
be tied low to enable the differentiation logic. If no isolation barrier is implemented
(direct connection), or TI bus holder isolation is implemented, the ISO terminal
should be tied high to disable the differentiation logic. For additional information
refer to TI application note Galvanic Isolation of the IEEE 1394-1995 Serial Bus,
SLLA011.
LPS 13 CMOS I Link power status input. This terminal monitors the active/power status of the link
layer controller and controls the state of the PHY-LLC interface. This terminal
should be connected through a 10-kΩ resistor either to the VDD supplying the LLC,
or to a pulsed output which is active when the LLC is powered (see Figure 9). A
pulsed signal should be used when an isolation barrier exists between the LLC and
PHY. (See Figure 10.)
The LPS input is considered inactive if it is sampled low by the PHY for more than
2.6 μs (128 SYSCLK cycles), and is considered active otherwise (that is, asserted
steady high or an oscillating signal with a low time less than 2.6 μs). The LPS input
must be high for at least 21 ns to guarantee that a high is observed by the PHY.
When the TSB41AB1 detects that LPS is inactive, it places the PHY-LLC interface
into a low-power reset state. In the reset state, the CTL and D outputs are held in
the logic zero state and the LREQ input is ignored; however, the SYSCLK output
remains active. If the LPS input remains low for more than 26 μs (1280 SYSCLK
cycles), the PHY-LLC interface is put into a low-power disabled state in which the
SYSCLK output is also held inactive. The PHY-LLC interface is placed into the
disabled state upon hardware reset.
The LLC is considered active only if both the LPS input is active and the LCtrl
register bit is set to 1, and is considered inactive if either the LPS input is inactive
or the LCtrl register bit is cleared to 0.
LREQ 48 CMOS I LLC request input. The LLC uses this input to initiate a service request to the
TSB41AB1. Bus holder is built into this terminal.
PC0 16 CMOS I Power class programming inputs. On hardware reset, these inputs set the default
PC1 17 value of the power class indicated during self-ID. Programming is done by tying
PC2 18 these terminals high or low. Refer to Table 9 for encoding.
PD 12 CMOS I Power-down input. A high on this terminal turns off all internal circuitry except the
cable-active monitor circuits, which control the CNA output (64-terminal PAP
package only). Asserting the PD input high also activates an internal pulldown on
the RESET terminal to force a reset of the internal control logic. (PD is provided for
legacy compatibility and is not recommended for power management in place of
IEEE 1394a-2000 suspend/resume LPS and C/LKON features.)
 Circuit- and IC description 3139 785 3220x 8. EN 57

TERMINAL
TYPE I/O DESCRIPTION
NAME PHP NO.
PLLGND 41 Supply – PLL circuit ground terminals. These terminals should be tied together to the
low-impedance circuit board ground plane.
PLLVDD 40 Supply – PLL circuit power terminals. A combination of high-frequency decoupling
capacitors near each terminal is suggested, such as paralleled 0.1 μF and 0.001
μF. Lower frequency 10 μF filtering capacitors are also recommended. This supply
terminal is separated from DVDD and AVDD inside the device to provide noise
isolation. It should be tied at a low-impedance point on the circuit board.
R0 33 Bias – Current setting resistor terminals. These terminals are connected through an
R1 34 external resistor to set the internal operating currents and cable driver output
currents. A resistance of 6.34 kΩ ±1.0% is required to meet the IEEE Std
1394-1995 output voltage limits.
RESET 37 CMOS I Logic reset input. Asserting this terminal low resets the internal logic. An internal
pullup resistor to VDD is provided so only an external delay capacitor is required for
proper power-up operation (see power-up reset in the Application Information
section). The RESET terminal also incorporates an internal pulldown which is
activated when the PD input is asserted high. This input is otherwise a standard
logic input, and may also be driven by an open-drain type driver.
SE 23 CMOS I Test control input. This input is used in manufacturing test of the TSB41AB1. For
normal use this terminal may be tied to GND through a 1-kΩ pulldown resistor or
it may be tied to GND directly.
SM 24 CMOS I Test control input. This input is used in manufacturing test of the TSB41AB1. For
normal use this terminal should be tied to GND.
SYSCLK 1 CMOS O System clock output. Provides a 49.152-MHz clock signal, synchronized with data
transfers, to the LLC.
TESTM 22 CMOS I Test control input. This input is used in manufacturing test of the TSB41AB1. For
normal use this terminal should be tied to VDD.
TPA+ 30 Cable I/O Twisted-pair cable A differential signal terminals. Board traces from the pair of
positive and negative differential signal terminals should be kept matched and as
TPA– 29 Cable I/O short as possible to the external load resistors and to the cable connector.
TPB+ 28 Cable I/O Twisted-pair cable B differential signal terminals. Board traces from the pair of
positive and negative differential signal terminals should be kept matched and as
TPB– 27 Cable I/O short as possible to the external load resistors and to the cable connector.
TPBIAS 31 Cable I/O Twisted-pair bias output. This provides the 1.86 V nominal bias voltage needed for
proper operation of the twisted-pair cable drivers and receivers, and for signaling
to the remote nodes that there is an active cable connection.
XI 42 Crystal – Crystal oscillator inputs. These terminals connect to a 24.576-MHz parallel
XO 43 resonant fundamental mode crystal. The optimum values for the external shunt
capacitors are dependent on the specifications of the crystal used (see crystal
selection in the Application Information section). When an external clock source is
used, XI should be the input and XO should be left open, and the clock must be
supplied before the device is powered on.
EN 58 8. 3139 785 3220x Circuit- and IC Description

IC7401 - 4x10bit DigitalVideo Decoder with microvision

BLOCK DIAGRAM

Copy VBI
CVBS/Y/G
Protection Data
Detector Slicer

Analog Front End

VI_1_A Composite and S-Video Processor

CVBS/ VI_1_B ADC1
Pb/B/C Y/C
VI_1_C CVBS/Y Y Luma
Separation
Processing YCbCr
5-line
VI_2_A C C Chroma Y[9:0]
CVBS/ Adaptive
VI_2_B ADC2 Processing
Y/G Comb C[9:0]
VI_2_C Output
M
Formatter
U FSS
VI_3_A X
CVBS/ Y/G Component
VI_3_B ADC3
Pr/R/C Processor
VI_3_C Pb/B YCbCr
Color
Gain/Offset Space
Pr/R Conversion
CVBS/Y VI_4_A ADC4

GPIO
Sampling
Clock Timing Processor
Host
with Sync Detector
Interface
XTAL1
XTAL2

VS/VBLK
AVID

GLCO

DG
DR

DB
FSO

SCL

SDA
PWDN

HS/CS
DATACLK

FID
RESETB

Figure 8-14

PIN CONFIGURATION
PFP PACKAGE
(TOP VIEW)
VS/VBLK/GPIO
CH1_A18GND
CH1_A18VDD
PLL_A18GND
PLL_A18VDD

HS/CS/GPIO

C_0/GPIO
C_1/GPIO

C_2/GPIO
C_3/GPIO
C_4/GPIO
C_5/GPIO
FID/GPIO
VI_1_A

IOGND
IOVDD
XTAL2
XTAL1

DGND
DVDD

80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61
VI_1_B 1 60 C_6/GPIO/RED
VI_1_C 2 59 C_7/GPIO/GREEN
CH1_A33GND 3 58 C_8/GPIO/BLUE
CH1_A33VDD 4 57 C_9/GPIO/FSO
CH2_A33VDD 5 56 DGND
CH2_A33GND 6 55 DVDD
VI_2_A 7 54 Y_0
VI_2_B 8 53 Y_1
VI_2_C 9 52 Y_2
CH2_A18GND 10 51 Y_3
CH2_A18VDD 11 50 Y_4
A18VDD_REF 12 49 IOGND
A18GND_REF 13 48 IOVDD
CH3_A18VDD 14 47 Y_5
CH3_A18GND 15 46 Y_6
VI_3_A 16 45 Y_7
VI_3_B 17 44 Y_8
VI_3_C 18 43 Y_9
CH3_A33GND 19 42 DGND
CH3_A33VDD 20 41 DVDD
21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40
VI_4_A

SCL
SDA
AGND

DVDD
CH4_A33VDD

CH4_A18VDD

DGND

DGND

DATACLK
CH4_A33GND

CH4_A18GND

INTREQ

PWDN
RESETB
FSS/GPIO
AVID/GPIO
GLCO/I2CA
IOVDD
IOGND

Figure 8-15
 Circuit- and IC description 3139 785 3220x 8. EN 59

PIN DESCRIPTION

TERMINAL
I/O DESCRIPTION
NAME NUMBER
Analog Video
VI_1_A 80
VI_1_B 1 VI_1_x: Analog video input for CVBS/Pb/B/C

VI_1_C 2 VI_2_x: Analog video input for CVBS/Y/G

VI_2_A 7 VI_3_x: Analog video input for CVBS/Pr/R/C

VI_2_B 8 VI_4_A: Analog video input for CVBS/Y

I Up to 10 composite, 4 S-video, and 2 composite or 3 component video inputs (or a combination thereof)
VI_2_C 9
can be supported.
VI_3_A 16
The inputs must be ac-coupled. The recommended coupling capacitor is 0.1 μF.
VI_3_B 17
The possible input configurations are listed in the input select register at I2C subaddress 00h (see
VI_3_C 18 Section 2.11.1).
VI_4_A 23
Clock Signals
DATACLK 40 O Line-locked data output clock.
External clock reference input. It may be connected to an external oscillator with a 1.8-V compatible clock
XTAL1 74 I
signal or a 14.31818-MHz crystal oscillator.
XTAL2 75 O External clock reference output. Not connected if XTAL1 is driven by an external single-ended oscillator.
Digital Video
57, 58,
59, 60, Digital video output of CbCr, C[9] is MSB and C[0] is LSB. Unused outputs can be left unconnected. Also,
C[9:0]/ these terminals can be programmable general-purpose I/O.
63, 64, O
GPIO[9:0]
65, 66, For the 8-bit mode, the two LSBs are ignored.
69, 70
D_BLUE 58 I Digital BLUE input from overlay device
D_GREEN 59 I Digital GREEN input from overlay device
D_RED 60 I Digital RED input from overlay device
FSO 57 I Fast-switch overlay between digital RGB and any video
43, 44,
45, 46, Digital video output of Y/YCbCr, Y[9] is MSB and Y[0] is LSB.
Y[9:0] 47, 50, O
51, 52, For the 8-bit mode, the two LSBs are ignored. Unused outputs can be left unconnected.
53, 54
Miscellaneous Signals
Fast-switch (blanking) input. Switching signal between the synchronous component video (YPbPr/RGB)
FSS/GPIO 35 I/O and the composite video input.
Programmable general-purpose I/O
Genlock control output (GLCO). Two Genlock data formats are available: TI format and real time control
GLCO/I2CA 37 I/O (RTC) format.
During reset, this terminal is an input used to program the I2C address LSB.
INTREQ 30 O Interrupt request
Power down input:
PWDN 33 I 1 = Power down
0 = Normal mode
RESETB 34 I Reset input, active low
EN 60 8. 3139 785 3220x Circuit- and IC Description

TERMINAL
I/O DESCRIPTION
NAME NUMBER
Host Interface
SCL 28 I I2C clock input
SDA 29 I/O I2C data bus
Power Supplies
AGND 26 I Analog ground. Connect to analog ground.
A18GND_REF 13 I Analog 1.8-V return
A18VDD_REF 12 I Analog power for reference 1.8 V
CH1_A18GND 79
CH2_A18GND 10
I Analog 1.8-V return
CH3_A18GND 15
CH4_A18GND 24
CH1_A18VDD 78
CH2_A18VDD 11
I Analog power. Connect to 1.8 V.
CH3_A18VDD 14
CH4_A18VDD 25
CH1_A33GND 3
CH2_A33GND 6
I Analog 3.3-V return
CH3_A33GND 19
CH4_A33GND 22
CH1_A33VDD 4
CH2_A33VDD 5
I Analog power. Connect to 3.3 V.
CH3_A33VDD 20
CH4_A33VDD 21
27, 32, 42,
DGND I Digital return
56, 68
31, 41, 55,
DVDD I Digital power. Connect to 1.8 V.
67
IOGND 39, 49, 62 I Digital power return
IOVDD 38, 48, 61 I Digital power. Connect to 3.3 V or less for reduced noise.
PLL_A18GND 77 I Analog power return
PLL_A18VDD 76 I Analog power. Connect to 1.8 V.
Sync Signals
Horizontal sync output or digital composite sync output
HS/CS/GPIO 72 I/O
Programmable general-purpose I/O
Vertical sync output (for modes with dedicated VSYNC) or VBLK output
VS/VBLK/GPIO 73 I/O
Programmable general-purpose I/O
Odd/even field indicator output. This terminal needs a pulldown resistor.
FID/GPIO 71 I/O
Programmable general-purpose I/O
Active video indicator output
AVID/GPIO 36 I/O
Programmable general-purpose I/O
 Circuit- and IC description 3139 785 3220x 8. EN 61

IC7595 - Voltage Detector Series with Programmable Delay

BLOCK DIAGRAM
NCP303LSNxxT1
Open Drain Output Configuration
2 Input 1 Reset Output

RD

Vref

3 Gnd 5 CD

Figure 8-18

PIN DESCRIPTION AND CONFIGURATION

PIN CONNECTIONS AND

MARKING DIAGRAM

Reset
1 5 CD
Output
xxxYW

Input 2

Ground 3 4 N.C.

xxx = 302 or 303

Y = Year
W = Work Week
(Top View)

Figure 8-19
EN 62 9. 3139 785 3220x Exploded View & Spare Parts List

Exploded View of DVDR3455H/55/97/75

2006-05-31
3139_249_36541_110_1_a1.pdf
P002

P001

Figure 9-1
 Exploded View & Spare Parts List 3139 785 3220x 9. EN 63

MISCELLANEOUS-SET & ACCESSORY

P001 3141 079 39691 FRONT CAB. ASSY DVDR3455H /55
P001 3141 079 39701 FRONT CAB. ASSY DVDR3455H APAC
/75/96/97
P002 3141 079 36761 FRAME ASSY DVDR3455H
0110 3139 244 10561 COVER TRAY DVDR3455H
0131 3139 241 25081 CLIP ESD DVDR3380

0179 3139 241 25041 SPRING EMC DVDR3400

0180 3139 241 24361 SPRING AV DVDR3400
0184 4822 532 60948 BUSH
0189 2822 031 00051 FAN 12VDC 0.6W 3000RPM B
0230 3139 241 24101 PLATE REAR DVDR3455H NAFTA

0240 3139 241 24231 COVER TOP DVDR3455H

0269 2522 200 98475 SCR PAN TORX ST BK #6-32X6
0341 2422 549 00971 REMOTE CONTR DVDR3455H/NAFTA
B
0345 2422 070 00026 MAINS CORD BRZ 10A 1M85 VH B /55
0345 4822 321 11499 MAINSCORD 2.0M - EU /97

0345 2422 070 98233 MAINSCORD AUS 7A5 1M8 VH BK B/75

0345 2422 070 00093 MAINSCORD TWN 7A 1M8 VH BK B /96
0346 3139 128 73010 MAINS PLUG ADAPTER /55
0350 2422 076 00718 CBLE CINCH 1M5 CINCH RDYEWH B
0487 4822 320 50377 CONNECT. CABLE PAL

1001 3139 248 88731 PCBAS DVDR3455H DIGI BOARD LA

/55
1001 3139 248 51321 PCBAS DVDR3455H DIGI BOARD/75/75
1001 3139 248 88721 PCBSA DVDR3455H DIGI BOARD/97/97
1001 3139 248 51311 PCBAS DVDR3455H DIGI BOARD /96
1002 3139 248 88701 PCBAS DVDR3455H ANA BOARD NA
/55/96

1002 3139 248 88691 PCBAS DVDR3455H ANA BOARD AP

/75/97
1003 3139 248 89111 PCBAS DVDR3455H FRONT COMBI
1004 3139 247 12862 PSU 06H85 WR AC7012X LF PIE
1005 3139 248 00221 DRIVE D5.1 CLOSED
1006 2822 062 00142 HDD 3.5”” 160GB WD1600BB-55GUC0

8003 3139 241 02541 FFC FOIL 18P/180/18P AD 1MMP

8004 3139 241 02551 FFC FOIL 19P/180/19P AD 1MMP
8005 3139 241 02531 FFC FOIL 24P/140/24P AD 1MMP
8006 3139 241 02061 CBLE HR 04P/120/04P LC UL
8007 3139 241 02361 CBLE EH 04P/220/04P F6001 UL

8008 3139 241 02181 FFC FOIL 14P/280/14P BD 1MMP

8009 3139 241 02161 CBLE IDE 40P/220/40P IDE UL SP
8010 3139 241 00921 CBLE IDE 40P/280/40P IDE UL
8011 3139 241 01521 FFC FOIL 09P/280/09P BD 1MMP
8013 3139 241 02241 CBLE VH 05P/180/05P VH 22ST BK

Note: Only the parts mentioned in this list are normal service
spare parts.
 EN 64 10. 3139 785 3220x Revision List

10. REVISION LIST

Version 1.0
* Initial Release

Version 1.1
* Addition of DVDR3455H/96
* Update service parts list