Stick a fork in It:

Applications for SystemVerilog

Dynamic Processes

Doug Smith and David Long

Doulos
Processes
Fine-grained process control
Foreign code adapters
Creating stimulus
Summary

APPLICATIONS FOR
SYSTEMVERILOG
DYNAMIC PROCESSES
 What is a “process”?

• A process is a thread of execution

• Static process – has a defined end to the execution

– assign, initial, always, always_comb, etc.
– fork..join

• Dynamic process – undefined end of execution

– fork..join_any and fork..join_none
– wait fork, disable fork and std::process for
process control

• Useful in system modelling (including testbenches)

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 Static processes

module Design( input clk, ... );

// Combinational process modules
always @*
processes
begin
...
end

// Synchronous process
always_ff @( posedge clk )
begin
...
end

SubBlock b1 ( .* ); // Instantiations signals

endmodule : Design
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 Static and dynamic processes

fork … join fork … join_any fork … join_none

• all branches complete • first branch completes • invoking code

proceeds immediately
• invoking code • invoking code then
proceeds when all proceeds • all branches run to
branches finish completion in parallel
with invoking code

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 fork .. join

• fork .. join blocks until all forked processes have completed

initial
begin Two processes
fork
task1; 1

begin 2
task2; task2 and task3 run in sequence
task1 runs in parallel with these
task3;
end
join
$display("All tasks have completed");
end
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 fork .. join_none

• fork .. join_none spawns “background” processes

initial
begin Two processes
fork
task1; 1

begin 2
task2;
task3;
end
processes start when parent blocks
join_none
#0 $display("All tasks have started");
end
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 fork .. join_any

• fork .. join_any also spawns “background” processes

initial
begin Two processes
fork
task1; 1

begin 2
task2;
task3;
end
join_any The other is still running

$display("One process has finished");

end
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 wait fork

• How do I know when processes have completed?

This is the parent process
initial
begin
fork
...
join_none
...
wait fork; Blocks (waits) until all spawned
processes have finished
end

• Useful to stop tests from exiting before testbench is done

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 disable kill

• How can I “kill” sub-processes?

initial
begin
fork
...
Blocks (waits) until one spawned
join_any
process has finished ...
disable fork;
end ... then kills the rest

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 Identifying processes
• It is sometimes useful to give processes a unique identifier
initial
begin
for (int i; i<3; i++) Spawns 3 processes

fork
automatic int id = i;
... Local copy of id for each process
join_none
...
end

• But how do I wait / kill a specific process – e.g., id 2?

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 Fine-grain process control
• Class std::process provides fine-grain process control

class process;
Blocking kill() or disable fork
enum state {
FINISHED, RUNNING, WAITING, SUSPENDED, KILLED };
static function process self();
function state status(); Returns handle to
current process
function void kill();
task await();
function void suspend();
task resume();
endclass

• Objects of type process are created automatically

(cannot call new)
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 Sample applications

• Resolution functions in SystemVerilog

• Creation of independent testbench threads
• Foreign code adapters
• Better generation of stimulus
• Hardware modeling
• Timeouts
• TLI (Transaction Level Interface)
• Architectural modeling

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Processes
Fine-grained process control
Foreign code adapters
Creating stimulus
Summary

APPLICATIONS FOR
SYSTEMVERILOG
DYNAMIC PROCESSES
 Verilog net resolution
“Higher” strength wins

• Each driver onto a net has a strength 0 St0

a
assign (strong0, weak1) w = a; St0
w
1
assign (pull0, pull1) w = b; b
Pu1

Level Keyword Context

7 supply0 supply1 primitive/assign
Default 6 strong0 strong1 primitive/assign
5 pull0 pull1 primitive/assign
4 large trireg
3 weak0 weak1 primitive/assign
2 medium trireg
1 small trireg
0 highz0 highz1 primitive/assign
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 Custom resolution function?

• wand (wired-and) / wor (wired-or)

• What about mixed-signal behavior?
Amplitude

driver
filters
Not in Verilog!

Resolution bus
time Function

real
analog

+ real driver

real
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 Mixed-signal resolution function

• Possible in VHDL using resolved type ...

package a_pack is
type real_vec is array (natural range <>) of real;
function resolve (s: real_vec) return real;
subtype a_type is resolve real;
end package;

package body a_pack is

function resolve (s: real_vec) return real is
variable sum: real := 0.0;
begin
for i in s'range loop real
sum := sum + s(i);
end loop; + real

return sum; real

end function resolve;
end package body;
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 SV Interface resolution function

interface analog_if();
real driver_vals[process];
real result;

function void resolve();

// Sum all values
result = 0.0;
foreach ( driver_vals[proc] )
result += driver_vals[proc];
endfunction: resolve
real

function void write (real val);

process this_proc;
+ real

this_proc = process::self; real

driver_vals[this_proc] = val;
resolve();
endfunction: write
endinterface: analog_if
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 Example

module driver #(real low=0.0, high=0.0,

time delay=1ns)(analog_if aif);
initial begin
aif.write(low);
#delay aif.write(high);
#delay aif.write(low);
end aif
D1
endmodule: driver
+
D2
module top;
analog_if aif1();
driver #(0.0,2.50,10ns) D1(aif1);
driver #(0.0,1.25,12ns) D2(aif1);
...
endmodule: top

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Processes
Fine-grained process control
Foreign code adapters
Creating stimulus
Summary

APPLICATIONS FOR
SYSTEMVERILOG
DYNAMIC PROCESSES
 Foreign Code Adapters

SystemVerilog

Adapter

Foreign Code
(C / SystemC /
C++ / etc. )

Independent thread of execution

(dynamic process)

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 Example

SystemVerilog

Adapter

Perl Unix
Script Filter

DPI

Pipe

Pipe

Operating System
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 DPI Code (1)
#!perl # stimgen.pl
@all_ops = ( @operate_ops, @branch_ops, ... ); Adapter
for ( $i = 0; $i< 100; $i++ ) {
my $index = rand @all_ops; Perl
print $all_ops[$index], "\n"; Script
} DPI
#include <stdio.h>
#include <stdlib.h>
#define PERLCMD "./stimgen.pl” // Script
#define MAXLINE 256 Pipe

FILE *fpin;
char line[MAXLINE];

int open_pipe() {
// Open the pipe to the Perl script
if ( (fpin = popen( PERLCMD, "r" )) == NULL )
// Print error if null
...
}
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 DPI Code (2)

char *get_stimulus(){ Adapter

Perl
// Open pipe if not yet created Script
if ( fpin == NULL ) DPI
if ( open_pipe())
return NULL;
Pipe
// Read in the stimulus
if ( fgets( line, MAXLINE, fpin ) != NULL )
return line; // Send to the DPI

return NULL;
}

// Define Unix filtering functions here ...

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 Adaptor code (1)
import "DPI-C" function string get_stimulus();
import "DPI-C" function void filter(input string line);

task run();
fork
begin
1 string op, in;
while (( in = get_stimulus()) != "" )
begin
assert( $sscanf( in, "%s", op ));
tr = new ( op ); SystemVerilog
Adapter
Perl Unix
// Send transaction Script Filter
DPI
...
end
Pipe
end
Pipe
... Operating System
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 Adaptor code (2)
SystemVerilog
task run(); Adapter
... Perl Unix
Script Filter
fork DPI
begin
// Process perl input Pipe
1 ... Pipe
end Operating System

begin
forever begin
@( /* named event */ );
2 // Call DPI function to send to pipe
filter( tr.sprint() );
end
end
join_any
disable fork;
endtask
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Processes
Fine-grained process control
Foreign code adapters
Creating stimulus
Summary

APPLICATIONS FOR
SYSTEMVERILOG
DYNAMIC PROCESSES
 Layered sequential stimulus

Tests enumerate possible

top-level sequences

Virtual or layered
seq1 seq2 seq2
sequences

Constrained random
sequence of transactions tx1 tx2 tx3

Randomized transactions are not enough

Drive transactions into DUT tx1 Driver DUT

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 Virtual sequences

uvm_env

uvm_sequencer

uvm_agent uvm_agent

uvm_sequencer uvm_sequencer

uvm_driver uvm_driver

dut_if dut_if

DUT

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 Forking sequences
class my_virtual_sequence extends uvm_sequence;

...

virtual task body();

fork
p_sequencer.sequencer0.start(iseq_inst0);
p_sequencer.sequencer1.start(iseq_inst1);
join_none
#0; // Wait allows threads to start

... // Do other work here

wait fork;

`uvm_do_on(eseq_inst0, p_sequencer.sequencer0)
`uvm_do_on(esqe_inst1, p_sequencer.sequencer1)
endtask: body

endclass: my_virtual_sequence

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Processes
Fine-grained process control
Foreign code adapters
Creating stimulus
Summary

APPLICATIONS FOR
SYSTEMVERILOG
DYNAMIC PROCESSES
 Summary

• Dynamic processes and process control enables:

– Resolution functions in SystemVerilog!
– Foreign code adapters
– Better generation of stimulus

• See paper ...

– Creation of independent testbench threads
– Hardware modeling
– Timeouts
– TLI (Transaction Level Interface)
– Architectural modeling

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 Any Questions?

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