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Digital Integrated Circuits

A Design Perspective

Performance Issues

187

Fan-In Considerations

Propagation delay deteriorates rapidly as a function of fan-in – quadratically in the worst case.

A 3 B 3 C 3 D 3

A 4 CL
B 4 C3
C 4 C2
D 4 C1

tpHL = 0.69 Reqn(C1+2C2+3C3+4CL)

188

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Fast Complex Gates: Design Technique 1

Transistor sizing
as long as fan-out capacitance dominates
Progressive sizing

InN MN CL Distributed RC line

 M1 > M2 > M3 > … > MN
(the FET closest to the output is the smallest)
In3 M3 C3
 Can reduce delay by more than 20%;
In2 M2 C2 decreasing gains as technology shrinks
In1 M1 C1

189

Fast Complex Gates: Design Technique 2

Transistor ordering

critical path critical path

charged 01 charged

In3 1 M3 CL In1 M3 CL

In2 1 M2 C2 charged In2 1 M2 C2 discharged

In1 M1 C1 charged In3 1 M1 C1 discharged
01

delay determined by time to discharge CL, C1 and C2 delay determined by time to discharge CL

190

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Fast Complex Gates: Design Technique 3

Alternative logic structures

F = ABCDEFGH

191

Fast Complex Gates: Design Technique 4

Isolating fan-in from fan-out using buffer insertion

CL CL

192

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Static CMOS Combinational Circuit

VDD VDD

M1 M2

Out Out

A
A PDN1 PDN2
B
B

VSS VSS

Differential Cascode Voltage Switch Logic (DCVSL)

193

DCVSL Example
XOR & XNOR

194

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Digital Integrated Circuits

A Design Perspective

Pass-Transistor &
Transmission Gate

195

Pass-Transistor Logic
 N transistors
 No Static Consumption

Switch Out A
Out
Inputs

Network B
B

196

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Example: AND Gate

A
B
F = AB

197

Complementary Pass Transistor Logic

A
Pass-Transistor
A F
B Network
B

A Inverse
A Pass-Transistor F
B
B Network

B B B B B B

A A A

B F=AB B F=A+B A F=AÝ

A A A

B F=AB B F=A+B A F=A Ý

AND/NAND OR/NOR EXOR/NEXOR

198

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Transmission Gate

C
C

A B A B

C
C

C = 2.5 V
A = 2.5 V
B
CL

C=0V

199

Resistance of Transmission Gate

30

2. 5 V
Rn Rn
Rp
Resistance, ohms

20
2.5 V Vou t

Rp
0V
10
R n || Rp

0
0.0 1.0 2.0
Vou t , V

200

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Transmission Gate: Multiplexer

V DD
S

A
M2

S F

M1

201

Transmission Gate: XOR

B
M2

M3/M4 A
A
F

M1
B

202

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Transmission Gate: Full Adder

 Similar delays for sum and carry
P
VDD
VDD Ci
A
P S Sum Generation
A A P Ci

A P VDD
B B
VDD A
P
P Co Carry Generation
Ci Ci Ci
A
Setup P

203

Digital Integrated Circuits

A Design Perspective

Dynamic Logic

204

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Dynamic CMOS
In static circuits at every point in time (except when switching) the output is
connected to either GND or VDD via a low resistance path.
fan-in of n inputs requires 2n (n NMOS + n PMOS) devices

Dynamic circuits rely on the temporary storage of signal values on the

capacitance of high impedance nodes.
only requires n + 2 (n+1 NMOS + 1 PMOS) transistors

205

Dynamic Gate

Clk Mp Clk Mp
Out Out
In1 CL
A
In2 PDN
C
In3
B
Clk Me
Clk Me

Two phase operation

Precharge (Clk = 0)
Evaluate (Clk = 1)

206

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Dynamic Gate

off
Clk Mp Clk Mp on
1
Out Out
In1 CL (AB+C)
A
In2 PDN
C
In3
B
Clk Me
off
Clk Me on

Two phase operation

Precharge (Clk = 0)
Evaluate (Clk = 1)

207

Conditions on Output
Once the output of a dynamic gate is discharged, it cannot be charged again until the next
precharge operation.
Inputs to the gate can make at most one transition during evaluation.
Output can be in the high impedance state during and after evaluation (PDN off), state is
stored on CL

208

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Properties of Dynamic Gates

Logic function is implemented by the PDN only
number of transistors is N + 2 (versus 2N for static complementary CMOS)
Full swing outputs (VOL = GND and VOH = VDD)
Non-ratioed - sizing of the devices does not affect the logic levels
Faster switching speeds
reduced load capacitance due to lower input capacitance (Cin)
reduced load capacitance due to smaller output loading (Cout)
no Isc, so all the current provided by PDN goes into discharging CL

209

Properties of Dynamic Gates Cont’d

Overall power dissipation usually higher than static CMOS
no static current path ever exists between VDD and GND (including Psc)
no glitching
higher transition probabilities
extra load on Clk
PDN starts to work as soon as the input signals exceed VTn, so VM, VIH and VIL
equal to VTn
low noise margin (NML)
Needs a precharge/evaluate clock

210

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Issues in Dynamic Design 1: Charge Leakage

CLK
Clk Mp
Out

A CL

VOut Evaluate
Clk Me
Precharge

Leakage sources

Dominant component is subthreshold current

211

Solution to Charge Leakage

Keeper

Clk Mp Mkp

A Out
CL
B

Clk Me

Same approach as level restorer for pass-transistor logic

212

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Issues in Dynamic Design 2: Charge Sharing

Charge stored originally on CL is redistributed (shared) over CL and CA leading to

reduced robustness

Clk Mp
Out
A CL

B=0 CA

Clk Me CB

213

Charge Sharing

VDD
case 1) if V out < VTn

Clk Mp

Out C L VDD = C L Vout  t  + Ca  VDD – V Tn  V X  

or
CL
A Ma Ca
V out = Vout  t  – V DD = – --------  V DD – V Tn  V X  
X C
L
Ca
B= 0 Mb case 2) if V out > VTn

 Ca 
Cb Vout = –V DD  ---------------------- 
Clk Me  Ca + CL 

214

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Solution to Charge Redistribution

Precharge internal nodes using a clock-driven transistor (at the cost of increased area
and power)

Clk Mp Mkp Clk

Out
A

Clk Me

215

Issues in Dynamic Design 4: Clock Feedthrough

Coupling between Out and Clk input of the precharge device due to the gate to drain
capacitance. So voltage of Out can rise above VDD. The fast rising (and falling edges)
of the clock couple to Out.

Clk Mp
Out
A CL

Clk Me

216

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Clock Feedthrough

Clock feedthrough
Clk 2.5
Out
In1
1.5
In2
0.5
In3 In &
Clk
-0.5
In4 Out
0 0.5 1
Clk
Time, ns
Clock feedthrough

217

Other Effects
Capacitive coupling
Substrate coupling
Minority charge injection
Supply noise (ground bounce)

218

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