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Arithmetic

The document discusses binary number representation and arithmetic operations in computers. It covers unsigned and two's complement representation, how to design a 32-bit ALU from 1-bit ALUs, handling subtraction and comparison, and algorithms for unsigned and signed multiplication like Booth's algorithm. Signed multiplication maps the problem to unsigned multiplication using Booth's encoding technique.

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0% found this document useful (0 votes)
12 views

Arithmetic

The document discusses binary number representation and arithmetic operations in computers. It covers unsigned and two's complement representation, how to design a 32-bit ALU from 1-bit ALUs, handling subtraction and comparison, and algorithms for unsigned and signed multiplication like Booth's algorithm. Signed multiplication maps the problem to unsigned multiplication using Booth's encoding technique.

Uploaded by

singh258963147
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
Available Formats
Download as PDF, TXT or read online on Scribd
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20-02-2024

Arithmetic for Computers

Binary Representation
Unsigned :
• The binary number

01011000 00010101 00101110 11100111


MSB LSB

represents the quantity 0 × 2 +1×2 + ⋯+ 1 × 2

• A 32-bit word can represent 232 numbers between 0 and 2 − 1 Numbers


are always positive

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Binary Representation
2’s Complement:
32 bits can only represent 232 numbers – if we wish to also Each number represents the quantity
represent negative numbers, we can represent 231 positive -231 x31 + x30 230 + x29 229 + … + x1 21 + x0 20
numbers (incl zero) and 231 negative numbers
Why is this representation favorable?
0000 0000 0000 0000 0000 0000 0000 0000two = 0ten Consider the sum of 1 and -2 …. we get -1
0000 0000 0000 0000 0000 0000 0000 0001two = 1ten Consider the sum of 2 and -1 …. we get +1
… This format can directly undergo addition
0111 1111 1111 1111 1111 1111 1111 1111two = 231-1 without any conversions!

1000 0000 0000 0000 0000 0000 0000 0000two = -231


1000 0000 0000 0000 0000 0000 0000 0001two = -(231 – 1)
1000 0000 0000 0000 0000 0000 0000 0010two = -(231 – 2)

1111 1111 1111 1111 1111 1111 1111 1110two = -2
1111 1111 1111 1111 1111 1111 1111 1111two = -1

Binary Representation
2’s Complement: 0000 0000 0000 0000 0000 0000 0000 0000two = 0ten
0000 0000 0000 0000 0000 0000 0000 0001two = 1ten

0111 1111 1111 1111 1111 1111 1111 1111two = 231-1

1000 0000 0000 0000 0000 0000 0000 0000two = -231


1000 0000 0000 0000 0000 0000 0000 0001two = -(231 – 1)
1000 0000 0000 0000 0000 0000 0000 0010two = -(231 – 2)

1111 1111 1111 1111 1111 1111 1111 1110two = -2
1111 1111 1111 1111 1111 1111 1111 1111two = -1

Note that the sum of a number x and its inverted representation x’ always equals a string of 1s (-1)
x + x’ = -1
x’ + 1 = -x … hence, can compute the negative of a number by
-x = x’ + 1 inverting all bits and adding 1

Similarly, the sum of x and -x gives us all zeroes, with a carry of 1


In reality, x + (-x) = 2n … hence the name 2’s complement

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ALU Design
1bit ALU: Q. How to do subtraction?

Q. How to design 32-bit ALU


from 1-bit ALU?

Tailoring the 32-bit ALU to MIPS


slt rd, rs, rt -- if (rs < rt) rd = 1; else rd = 0 Idea: (a-b) < 0 → a < b

ALU 31
ALU 0 – ALU 30

Problem: Overflow e.g., rs = (1001)2 = -7 and rt = (0110)2= 6

How to modify the 1-bit ALU to handle slt correctly?

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Tailoring the 32-bit ALU to MIPS


Supporting conditional branch: beq rs, rt, L1 -- if (rs == rt) branch to instruction labeled L1
Idea: (a-b) = 0 → a = b

ALU 0 – ALU 30

ALU control lines Function


000 and
001 or
010 add
110 subtract
111 Set on less than
ALU 31

Unsigned Multiplication (Combinational)


1 1 0 1 Multiplicand (13)
1 0 1 1 Multiplier (11)
--------- Ripple-carry array
1101
1101
0000
1101
-----------------
1 0 0 0 1 1 1 1 Product (143)

Carry-save array

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Unsigned Multiplication (Sequential)

1 1 0 1 Multiplicand (13)
1 0 1 1 Multiplier (11)
---------
1101
1101
0000
1101
-----------------
1 0 0 0 1 1 1 1 Product (143)

Unsigned Multiplication
Unsigned multiplication:
M
1101
C Q
0 0000 1011 Initialization
A

0 1101 1011 q0 = 1 → Add


0 0110 1101 Shift right

1 0011 1101 q0 = 1 → Add


0 1001 1110 Shift right
1 1 0 1 Multiplicand (13)
1 0 1 1 Multiplier (11)
0 1001 1110 q0 = 0 → No Add ---------
0 0100 1111 Shift right 1101
1101
1 0001 1111 q0 = 1 → Add 0000
1101
0 1000 1111 Shift right -----------------
1 0 0 0 1 1 1 1 Product (143)

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Signed Multiplication

• Recall grade school trick


Booth’s encoding:
• When multiplying by 9: Current Bit to Explanation Example Operation
• Multiply by 10 (shift digits left) bit right
• Subtract once 1 0 Begins run of ‘1’ 0000111100 Subtract
• E.g., 12345 x 9 = 12345 x (10 - 1) 1 1 Middle of run of ‘1’ 0000111100 Nothing
= 123450 - 12345 0 1 End of a run of ‘1’ 0000111100 Add
• Booth’s algorithm applies same principle 0 0 Middle of a run of ‘0’ 0000111100 Nothing
• Except no ‘9’ in binary, just ‘1’ and ‘0’
• Search for a run of ‘1’ bits in the multiplier
• E.g. ‘0110’ has a run of 2 ‘1’ bits in the middle
• Multiplying by ‘0110’ (6 in decimal) is equivalent to multiplying by 8 and subtracting twice,
since 6 x m = (8 – 2) x m = 8m – 2m

Booth’s Algorithm
Example: 2 x -3 = -6, or 0010 x 1101 = 1111 1010

M
0010 Q-1
Q
0000 1101 0 Initialization Current bit Bit to right Operation
A
1 0 Subtract

1110 1101 0 Q0Q-1 = 10 → Subtract 1 1 Nothing


0 1 Add
1111 0110 1 Arithmetic right shift
0 0 Nothing

0001 0110 1 Q0Q-1 = 01 → Add


0000 1011 0 Arithmetic right shift

1110 1011 0 Q0Q-1 = 10 → Subtract 1111 0101 1 Q0Q-1 = 11 → Nothing

1111 0101 1 Arithmetic right shift 1111 1010 1 Arithmetic right shift

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Why Booth’s Algorithm Works?


𝒂𝒊 𝒂𝒊 𝟏 Operation
Assume 𝑎 be the multiplier and 𝑏 be the multiplicand
1 0 Subtract
1 1 Nothing
Booth’s algorithm can be written as
0 1 Add
𝑎 −𝑎 ×𝑏×2 0 0 Nothing
+ 𝑎 −𝑎 ×𝑏×2
+ 𝑎 −𝑎 ×𝑏×2 Note: −𝑎 × 2 + 𝑎 × 2 = 𝑎 × 2 and 𝑎 =0 𝑎 − 𝑎 = 0 Nothing
… … 𝑎 − 𝑎 = 1 Add
𝑎 − 𝑎 = −1 Subtract
+ 𝑎 −𝑎 ×𝑏×2
+ 𝑎 −𝑎 ×𝑏×2

Factoring out 𝑏 from each term: 𝑏 × 𝑎 × −2 + 𝑎 ×2 +⋯+ 𝑎 × 2 + 𝑎 ×2

2’s complement of 𝑎

Unsigned Division

1101 100010010 Dividend


Divisor 1101
10000
1101
1110
1101
1 Remainder

Restoring division:
Do the following 𝒏 times
1. Shift 𝐴 and 𝑄 left one bit
2. 𝐴 ← 𝐴 − 𝑀
3. If the sign of 𝐴 is 1 i.e., 𝑎 = 1
𝑞 ←0
𝐴 ← 𝐴 + 𝑀 //Restore After division 𝑛-bit quotient is in 𝑄 and the remainder is in 𝐴
else
𝑞 ←1

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Unsigned Division (Restoring)


Example: Divisor: 11 Dividend: 1000
A Q M
00000 1000 00011 Initialization
00001 000? Shift left 𝐴𝑄
11101 000? Subtract 𝐴 ← 𝐴 − 𝑀
00001 0000 𝑞 ← 0, 𝐴 ← 𝐴 + 𝑀

00010 000? Shift left 𝐴𝑄


11111 000? Subtract 𝐴 ← 𝐴 − 𝑀
00010 0000 𝑞 ← 0, 𝐴 ← 𝐴 + 𝑀
00100 000? Shift left 𝐴𝑄
Do the following 𝒏 times
00001 000? Subtract 𝐴 ← 𝐴 − 𝑀 1. Shift 𝐴 and 𝑄 left one bit
00001 0001 𝑞 ←1 2. 𝐴 ← 𝐴 − 𝑀
3. If the sign of 𝐴 is 1 i.e., 𝑎 = 1
00010 001? Shift left 𝐴𝑄 𝑞 ←0
𝐴 ← 𝐴 + 𝑀 //Restore
11111 001? Subtract 𝐴 ← 𝐴 − 𝑀
else
00010 0010 𝑞 ← 0, 𝐴 ← 𝐴 + 𝑀 𝑞 ←1
Remainder Quotient

Unsigned Division (Non-restoring)

In restoring division after subtraction what we do?

If A is positive – Shift left AQ and subtract M


 2A - M
If A is negative – First we restore A by adding M,
then we shift left AQ and subtract M
 2(A + M) – M = 2A + M

Summary: Restore operation is eliminated


In each step, we need to shift and then Add/Subtract
Restoring Division
Non-restoring division Do the following 𝒏 times
Step 1: Do the following 𝑛 times 1. Shift 𝐴 and 𝑄 left one bit
1. If the sign of A is 0, Shift left AQ by one bit, and subtract M from A 2. 𝐴 ← 𝐴 − 𝑀
otherwise, Shift left AQ by one bit and add M from A 3. If the sign of 𝐴 is 1 i.e., 𝑎 = 1
2. Now, if the sign of A is 0, set 𝑞 to 1; otherwise set 𝑞 to 0 𝑞 ←0
𝐴 ← 𝐴 + 𝑀 //Restore
Step 2 [Sign correction of reminder]: If the sign of A is 1, add M to A else
𝑞 ←1

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Unsigned Division (Non-restoring)


Example: Divisor: 11 Dividend: 1000
A Q M
00000 1000 00011 Initialization
00001 000? Shift left 𝐴𝑄
11110 000? Subtract 𝐴 ← 𝐴 − 𝑀
11110 0000 𝑞 ← 0 (A is –ve)

11100 000? Shift left 𝐴𝑄


11111 000? Add 𝐴 ← 𝐴 + 𝑀
11111 0000 𝑞 ← 0 (A is –ve) Non-restoring division
Step 1: Do the following 𝑛 times
11110 000? Shift left 𝐴𝑄 1. If the sign of A is 0, Shift left AQ by one bit, and subtract
00001 000? Add 𝐴 ← 𝐴 + 𝑀 M from A
otherwise, Shift left AQ by one bit and add M from A
00001 0001 𝑞 ← 1 (A is +ve) 2. Now, if the sign of A is 0, set 𝑞 to 1; otherwise set 𝑞 to 0
00010 001? Shift left 𝐴𝑄 Step 2 [Sign correction of reminder]:
If the sign of A is 1, add M to A
11111 001? Subtract 𝐴 ← 𝐴 − 𝑀
11111 0010 𝑞 ← 0 (A is –ve)
Remainder(?) Quotient After sign correction, reminder is 00010

Signed Division
Simplest solution: Use unsigned division and negate the quotient if signs of divisor and dividend disagree.

Q. What should be the sign of remainder?

Note: The equation 𝐷𝑖𝑣𝑖𝑑𝑒𝑛𝑑 = 𝑄𝑢𝑜𝑡𝑖𝑒𝑛𝑡 × 𝐷𝑖𝑣𝑖𝑠𝑜𝑟 + 𝑅𝑒𝑚𝑎𝑖𝑛𝑑𝑒𝑟 must always hold

Example: −7 ÷ 2: 𝑄𝑢𝑜𝑡𝑖𝑒𝑛𝑡 = −3,


𝑅𝑒𝑚𝑎𝑖𝑛𝑑𝑒𝑟 = 𝐷𝑖𝑣𝑖𝑑𝑒𝑛𝑑 − 𝑄𝑢𝑜𝑡𝑖𝑒𝑛𝑡 × 𝐷𝑖𝑣𝑖𝑠𝑜𝑟 = −7 − −3 × 2 = −1

Note: −4 as quotient also satisfies the formula i.e., 𝑅𝑒𝑚𝑎𝑖𝑛𝑑𝑒𝑟 = −7 − −4 × 2 = 1.


However, the absolute value of the quotient would change depending on the sign of the
divisor and the dividend. Here, − 𝑥 ÷ 𝑦 ≠ −𝑥 ÷ 𝑦, which is problematic!
Example: 7 ÷ −2: 𝑄𝑢𝑜𝑡𝑖𝑒𝑛𝑡 = −3,
𝑅𝑒𝑚𝑎𝑖𝑛𝑑𝑒𝑟 = 𝐷𝑖𝑣𝑖𝑑𝑒𝑛𝑑 − 𝑄𝑢𝑜𝑡𝑖𝑒𝑛𝑡 × 𝐷𝑖𝑣𝑖𝑠𝑜𝑟 = 7 − −3 × −2 = 1

Example: −7 ÷ −2: 𝑄𝑢𝑜𝑡𝑖𝑒𝑛𝑡 = 3,


𝑅𝑒𝑚𝑎𝑖𝑛𝑑𝑒𝑟 = 𝐷𝑖𝑣𝑖𝑑𝑒𝑛𝑑 − 𝑄𝑢𝑜𝑡𝑖𝑒𝑛𝑡 × 𝐷𝑖𝑣𝑖𝑠𝑜𝑟 = −7 − 3 × −2 = −1
Rule: Negate the quotient if the sign of divisor and dividend are opposite.
Sign of non-zero remainder matches the dividend.

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MIPS Multiplication and Division


Multiplication: Division:
• Two 32-bit registers for product • Use HI/LO registers for result
• HI: most-significant 32 bits • HI: 32-bit remainder
• LO: least-significant 32-bits • LO: 32-bit quotient
• Instructions • Instructions
• mult rs, rt / multu rs, rt • div rs, rt / divu rs, rt
• 64-bit product in HI/LO • No overflow or divide-by-0 checking
• mfhi rd / mflo rd • If divisor is 0, result is unpredictable
• Move from HI/LO to rd • Software must perform checks if required
• Can test HI value to see if product • Use mfhi, mflo to access result
overflows 32 bits

Floating Point Numbers


Normalized scientific notation: single non-zero digit to the left of the decimal (binary) point
– example: 3.5 x 109

Floating-point standard:
• Defined by IEEE Std 754-1985
• Developed in response to divergence of representations
• Portability issues for scientific code
• Now almost universally adopted
• Two representations
• Single precision (32-bit)
• Double precision (64-bit)

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IEEE Floating Point Format


single: 8 bits single: 23 bits
double: 11 bits double: 52 bits
S Exponent Fraction

x  ( 1)S  (1 Fraction)  2(Exponent Bias)

• S: sign bit (0  non-negative, 1  negative)


• Normalize significand: 1.0 ≤ |significand| < 2.0
• Always has a leading pre-binary-point 1 bit, so no need to represent it explicitly (hidden bit)
• Significand is Fraction with the “1.” restored
• Exponent: excess representation: actual exponent + Bias
• Ensures exponent is unsigned
• Single: Bias = 127; Double: Bias = 1203 Q. Why excess-127 representation
for exponent is used?

Note: More exponent bits → wider range of numbers


More fraction bits → higher precision

Example
• Represent 0.75 • What number is represented by the single-
• 0.75 = 1.12 × 2–1 precision float
• S=0 11000000101000…00
• Fraction = 1000…002 • S=1
• Exponent = –1 + Bias • Fraction = 01000…002
• Single: –1 + 127 = 126 = 011111102 • Exponent = 100000012 = 129
• Single: 0011111101000…00
• x = (–1)1 × (1 + 012) × 2(129 – 127)
Q. Represent 0.5 = (–1) × 1.25 × 22
= –5.0
Q. How to represent 0 ?
A. Exponent 00…0, Fraction: 00…0

±Infinity: Exponent = 111...1, Fraction = 000...0


NAN: Exponent = 111...1, Fraction ≠ 000...0
Indicates illegal or undefined result e.g., 0.0/0.0

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Floating Point Numbers


Single Precision Range: Double Precision Range:
• Exponents 00000000 and 11111111 reserved • Exponents 0000…00 and 1111…11 reserved
• Smallest value
Smallest value
• Exponent: 00000000001
Exponent: 00000001
 actual exponent = 1 – 1023 = –1022
 actual exponent = 1 – 127 = –126
• Fraction: 000…00  significand = 1.0
Fraction: 000…00  significand = 1.0
±1.0 × 2–126 ≈ ±1.2 × 10–38 • ±1.0 × 2–1022 ≈ ±2.2 × 10–308
• Largest value
Largest value • Exponent: 11111111110
exponent: 11111110  actual exponent = 2046 – 1023 = +1023
 actual exponent = 254 – 127 = +127 • Fraction: 111…11  significand ≈ 2.0
Fraction: 111…11  significand ≈ 2.0 • ±2.0 × 2+1023 ≈ ±1.8 × 10+308
±2.0 × 2+127 ≈ ±3.4 × 10+38

Summary
Value inf 2 special cases up top that use the 0 255 00…0
Value NAN reserved exponent field of 255 0 255 xx….x
Highest Norm ~2 x 2127 0 254 11….1

Value 1 0 127 00…0


Exponent field < 127, i.e., after
subtracting bias, they are negative
exponents, representing numbers < 1
Smallest Norm ~1x 2-126 0 0..01 00…0
Largest Denorm ~1 x 2-126 Special case with exponent field 0, used to 0 0..00 11…1
Smallest Denorm ~2-149 represent denorms, that help us gradually approach 0 0 0..00 00…1
Value 0 0 0..00 00…0
Same rules as above, but the sign bit is 1
Same magnitudes as above, but negative numbers

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Floating Point Addition


• Consider a 4-digit binary example (0.5 + –0.4375)
• 1.0002 × 2–1 + –1.1102 × 2–2

1. Align binary points


Shift number with smaller exponent
1.0002 × 2–1 + –0.1112 × 2–1
2. Add significands
1.0002 × 2–1 + –0.1112 × 2–1 = 0.0012 × 2–1

3. Normalize result & check for over/underflow


1.0002 × 2–4, with no over/underflow
4. Round and renormalize if necessary
1.0002 × 2–4 (no change) = 0.0625 Assumptions of associativity may fail
(x+y)+z x+(y+z)
x -1.50E+38 -1.50E+38
y 1.50E+38 0.00E+00
z 1.0 1.0 1.50E+38
1.00E+00 0.00E+00

Floating Point Multiplication


• Consider a 4-digit binary example
• 1.0002 × 2–1 × –1.1102 × 2–2 (0.5 × –0.4375)
• 1. Add exponents
• Unbiased: –1 + –2 = –3
• Biased: (–1 + 127) + (–2 + 127) = –3 + 254 – 127 = –3 + 127
• 2. Multiply significands
• 1.0002 × 1.1102 = 1.1102  1.1102 × 2–3
• 3. Normalize result & check for over/underflow
• 1.1102 × 2–3 (no change) with no over/underflow
• 4. Round and renormalize if necessary
• 1.1102 × 2–3 (no change)
• 5. Determine sign: +ve × –ve  –ve
• –1.1102 × 2–3 = –0.21875

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