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COSS - Contact Session - 4 - With Annotaton

The hit ratio is 11/13 = 84.6%

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notes.chandan
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51 views

COSS - Contact Session - 4 - With Annotaton

The hit ratio is 11/13 = 84.6%

Uploaded by

notes.chandan
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
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Computer Organization and

Software Systems

Contact Session 4 Dr. Lucy J. Gudino


The Bottom Line
• How much?
• Capacity
• How fast?
• Time is money
• How expensive?

•Faster access time , ------------ cost per bit


•Greater capacity, --------------- cost per bit
•Greater capacity, ---------------access time
Memory Hierarchy
• Registers
• In CPU
• Internal or Main memory
• May include one or more levels of cache
• “RAM”
• External memory
• Backing store
Performance enhancement -Motivation
Performance enhancement -Motivation

Locality of Reference
During the course of the execution of a
program, memory references tend to
cluster
• Temporal locality: Locality in time
• If an item is referenced, it will tend
to be referenced again soon
• Spatial locality: Locality in space
• If an item is referenced, items
whose addresses are close by will
tend to be referenced soon.
Example

product = 1;
for ( i = 0; i < n-1; i++)
product = product * a[i] ;

•Data :
• Access array elements in succession – spatial locality
• Reference to “product” “i” and “n” in each iteration –
Temporal locality
•Instructions :
• Reference instructions in sequence : Spatial locality
• Looping through : Temporal locality
Performance enhancement -Motivation
Cache
Cache

• Small, fast memory


• Sits between normal main memory and CPU
• May be located on CPU chip or separate module
Cache and Main Memory Structure
START
Cache Read Operation
Receive address (RA)
From CPU

Is block Access main memory


containing RA for block containing
word in Cache? RA word

Fetch RA word and Allocate cache line


deliver to CPU for main memory
block

Load main memory Deliver RA word to


block in to cache line CPU
DONE
Performance of cache
• Hit ratio : Number of Hits / total references
to memory
• Hit
• Miss
Read Hit
Read Miss
Write hit
Write miss
Mapping Function
• How memory blocks are mapped to cache lines
• Three types
-Direct mapping
-Associative mapping
-Set Associative mapping
Direct Mapped Cache

• 16 Bytes main memory


• How many address bits are
required?
• Memory block size is 4 bytes
• Cache of 8 Byte
• How many cache lines?
• cache contains 2 lines ( 4
bytes per Line)
Direct Mapped Cache
• Each block of main memory maps to only one cache line
• i.e. if a block is in cache, it must be in one specific place
• i = j modulo m
where i = cache line number
j = main memory block no.
m = no.of lines in the
cache
Direct Mapped Cache
i = j modulo m

• Address is split in three parts:


• Tag
• Line
• Word
Direct Mapped Cache Organization
Direct mapped cache- Summary
• Address length = (s+w) bits
• Number of addressable units = 2s+w words or bytes
• Block size = line size = 2w words or bytes
• Number of blocks in main memory = 2s+w / 2w = 2s
• Number of lines in cache = m = 2r
• Size of tag =(s-r) bits
Direct mapped cache- Summary

1 1 2

Tag s-r Line or Slot r Word w


Direct mapped cache-pros & cons

• Simple
• Inexpensive
• Fixed location for given block
- If a program accesses 2 blocks that map to the same line repeatedly,
cache misses are very high
Problem 1 : Direct Mapped Cache

•Given :
• Cache of 64KByte, Cache block of 4 bytes
• 16MBytes main memory
•Find out
a) Number of bits required to address the main memory
b) Number of blocks in main memory
c) Number of cache lines
d) Number of bits required to identify a word (byte) in a block
e) Number of bits to identify a block
f) Tag, Line, Word
Solution 1
•Given :
• Cache of 64kByte, Cache block of 4 bytes
• 16MBytes main memory

•Find out
a) Number of bits required to address the main memory

•b) Number of blocks in main memory

•c) Number of cache lines


Solution 1
•Given :
• Cache of 64kByte, Cache block of 4 bytes
• 16MBytes main memory

•Find out
•d) Number of bits required to identify a word (byte) in a block?

•e) Number of bits required to identify a block

•f) Tag, Line, Word


Tag s-r Line r Word w

8 14 2
Problem 2
Solution 2
Solution 2
Solution 2
Problem 3
• Consider a direct-mapped cache with 64
cache lines and a block size of 16 bytes and
main memory of 8K (Byte addressable
memory) . To what line number does byte
address 1200H map?
Problem 4
• The system uses a L1 cache with
direct mapping and 32-bit address
format is as follows:
• bits 0 - 3 = offset (word)
• bits 4 - 14 = index bits (Line)
• bits15 - 31 = tag
a) What is the size of cache line?
b) How many Cache lines are there?
c) How much space is required to
store the tags in the L1 cache?
d) What is the total Capacity of
cache including tag storage?
Problem 5

• 16 Bytes main memory, Memory block


size is 4 bytes, Cache of 8 Byte
(cache is 2 lines of 4 bytes each )
• Block access sequence :

•0 2 0 2 2 0 0 2 0 0 0 2 1

• Find out hit ratio.


Problem 5 – Direct Mapped Cache

• 16 Bytes main memory, Memory block


size is 4 bytes, Cache of 8 Byte
(cache is 2 lines of 4 bytes each )
Block access sequence :
0 2 0 2 2 0 0 2 0 0 0 2 1
Find out hit ratio.

0 2 0 2 2 0 0 2 0 0 0 2 1
Problem 6
• Suppose a 1024-byte cache has an access time of 0.1 microseconds and the main memory stores
1 Mbytes with an access time of 1 microsecond. A referenced memory block that is not in cache
must be loaded into cache .
• Answer the following questions:
a) What is the number of bits needed to address the main memory?

a) If the cache hit ratio is 95%, what is the average access time for a memory reference?

Avg access time = hit ratio * cache access + (1- hit ratio) * (cache access + memory access)
Associative Mapping

• A main memory block can load into any line of cache


• Memory address is interpreted as tag and word
• Tag uniquely identifies block of memory
• Every line’s tag is examined for a match
• Cache searching gets expensive
Associative Cache Organization
Associative Mapping Summary

• Address length = (s + w) bits


• Number of addressable units = 2s+w words or bytes
• Block size = line size = 2w words or bytes
• Number of blocks in main memory = 2s+ w/2w = 2s
• Number of lines in cache = undetermined
• Size of tag = s bits
Problem 7

•Given :
• Cache of 128KByte, Cache block of 8 bytes
• 32 MBytes main memory
•Find out
a) Number of bits required to address the memory

b) Number of blocks in main memory

c) Number of cache lines

d) Number of bits required to identify a word (byte) in a block?

e) Tag, Word
Problem 8
•Cache of 64KByte, Cache block of 4 bytes , 16 M Bytes main memory and
associative mapping.
Fill in the blanks:

Number of bits in main memory address = _____

Number of lines in the cache memory = ______

Word bits = _________

Tag bits = ________


Problem 9

• 16 Bytes main memory, Memory block size is 4 bytes, Cache of 8


Byte (cache is 2 lines of 4 bytes each ) and associative mapping.
Block access sequence :
0 2 0 2 2 0 0 2 0 0 0 2 1
Find out hit ratio.

0 2 0 2 2 0 0 2 0 0 0 2 1

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