TMS320F2838x Real-Time

Microcontrollers With Connectivity

Manager

Technical Reference Manual

Literature Number: SPRUII0E

MAY 2019 – REVISED SEPTEMBER 2023
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Table of Contents

Read This First.......................................................................................................................................................................131

About This Manual............................................................................................................................................................... 131
Notational Conventions........................................................................................................................................................ 131
Glossary............................................................................................................................................................................... 131
Related Documentation From Texas Instruments................................................................................................................ 131
Support Resources.............................................................................................................................................................. 131
Trademarks.......................................................................................................................................................................... 132
1 ► C28x SYSTEM RESOURCES......................................................................................................................................... 133
1.1 Technical Reference Manual Overview..........................................................................................................................133
2 C2000™ Microcontrollers Software Support................................................................................................................... 135
2.1 Introduction.................................................................................................................................................................... 136
2.2 C2000Ware Structure.....................................................................................................................................................136
2.3 Documentation............................................................................................................................................................... 136
2.4 Devices.......................................................................................................................................................................... 136
2.5 Libraries......................................................................................................................................................................... 136
2.6 Code Composer Studio™ Integrated Development Environment (IDE)........................................................................ 136
2.7 SysConfig and PinMUX Tool.......................................................................................................................................... 137
3 C28x System Control and Interrupts................................................................................................................................ 139
3.1 C28x System Control Introduction................................................................................................................................. 140
3.1.1 SYSCTL Related Collateral..................................................................................................................................... 140
3.2 System Control Functional Description.......................................................................................................................... 141
3.2.1 Device Identification................................................................................................................................................ 141
3.2.2 Device Configuration Registers............................................................................................................................... 141
3.3 Resets............................................................................................................................................................................ 142
3.3.1 Reset Sources......................................................................................................................................................... 142
3.3.2 External Reset (XRSn)............................................................................................................................................ 143
3.3.3 Simulate External Reset.......................................................................................................................................... 143
3.3.4 Power-On Reset (POR)...........................................................................................................................................143
3.3.5 Debugger Reset (SYSRS).......................................................................................................................................143
3.3.6 Simulate CPU1 Reset..............................................................................................................................................143
3.3.7 Watchdog Reset (WDRS)........................................................................................................................................144
3.3.8 NMI Watchdog Reset (NMIWDRS)..........................................................................................................................144
3.3.9 Secure Code Copy Reset (SCCRESET).................................................................................................................144
3.3.10 ESC Reset Output................................................................................................................................................. 144
3.3.11 Test Reset (TRST)................................................................................................................................................. 144
3.4 Peripheral Interrupts.......................................................................................................................................................145
3.4.1 Interrupt Concepts................................................................................................................................................... 145
3.4.2 Interrupt Architecture............................................................................................................................................... 145
3.4.3 Interrupt Entry Sequence.........................................................................................................................................147
3.4.4 Configuring and Using Interrupts.............................................................................................................................148
3.4.5 PIE Channel Mapping..............................................................................................................................................150
3.4.6 System Error and CM Status Interrupts...................................................................................................................151
3.4.7 Vector Tables........................................................................................................................................................... 153
3.5 Exceptions and Non-Maskable Interrupts...................................................................................................................... 159
3.5.1 Configuring and Using NMIs....................................................................................................................................159
3.5.2 Emulation Considerations........................................................................................................................................159
3.5.3 NMI Sources............................................................................................................................................................159
3.5.4 Illegal Instruction Trap (ITRAP)............................................................................................................................... 160
3.6 Safety Features..............................................................................................................................................................161
3.6.1 Write Protection on Registers.................................................................................................................................. 161

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3.6.2 CPU1 and CPU2 ePIE Vector Address Validity Check............................................................................................162

3.6.3 NMIWDs.................................................................................................................................................................. 162
3.6.4 ECC and Parity Enabled RAMs, Shared RAMs Protection..................................................................................... 162
3.6.5 ECC Enabled Flash Memory................................................................................................................................... 162
3.6.6 ERRORSTS Pin...................................................................................................................................................... 163
3.7 Clocking......................................................................................................................................................................... 163
3.7.1 Clock Sources......................................................................................................................................................... 165
3.7.2 Derived Clocks........................................................................................................................................................ 167
3.7.3 Device Clock Domains............................................................................................................................................ 168
3.7.4 External Clock Output (XCLKOUT)......................................................................................................................... 169
3.7.5 Clock Connectivity................................................................................................................................................... 169
3.7.6 PLL/AUXPLL........................................................................................................................................................... 171
3.7.7 Clock (OSCCLK) Failure Detection......................................................................................................................... 174
3.8 Clock Configuration Semaphore.................................................................................................................................... 176
3.9 32-Bit CPU Timers 0/1/2................................................................................................................................................ 177
3.10 Watchdog Timers......................................................................................................................................................... 178
3.10.1 Servicing the Watchdog Timer...............................................................................................................................179
3.10.2 Minimum Window Check....................................................................................................................................... 179
3.10.3 Watchdog Reset or Watchdog Interrupt Mode.......................................................................................................180
3.10.4 Watchdog Operation in Low Power Modes........................................................................................................... 180
3.10.5 Emulation Considerations......................................................................................................................................180
3.11 Low Power Modes........................................................................................................................................................ 181
3.11.1 IDLE.......................................................................................................................................................................181
3.11.2 STANDBY.............................................................................................................................................................. 181
3.12 Memory Controller Module...........................................................................................................................................182
3.12.1 Functional Description........................................................................................................................................... 183
3.13 JTAG............................................................................................................................................................................ 192
3.13.1 JTAG Noise and TAP_STATUS............................................................................................................................. 192
3.14 System Control Register Configuration Restrictions.................................................................................................... 193
3.15 Software....................................................................................................................................................................... 194
3.15.1 SYSCTL Examples................................................................................................................................................194
3.15.2 MEMCFG Examples..............................................................................................................................................194
3.15.3 NMI Examples....................................................................................................................................................... 197
3.15.4 TIMER Examples...................................................................................................................................................198
3.15.5 WATCHDOG Examples.........................................................................................................................................198
3.16 System Control Registers............................................................................................................................................ 200
3.16.1 SYSCTRL Base Address Table (C28)................................................................................................................... 200
3.16.2 ACCESS_PROTECTION_REGS Registers..........................................................................................................201
3.16.3 CLK_CFG_REGS Registers..................................................................................................................................225
3.16.4 CM_CONF_REGS Registers................................................................................................................................ 256
3.16.5 CPU_SYS_REGS Registers................................................................................................................................. 263
3.16.6 CPU_ID_REGS Registers..................................................................................................................................... 311
3.16.7 CPU1_PERIPH_AC_REGS Registers.................................................................................................................. 313
3.16.8 CPUTIMER_REGS Registers............................................................................................................................... 392
3.16.9 DEV_CFG_REGS Registers................................................................................................................................. 399
3.16.10 DMA_CLA_SRC_SEL_REGS Registers.............................................................................................................457
3.16.11 MEM_CFG_REGS Registers...............................................................................................................................464
3.16.12 MEMORY_ERROR_REGS Registers................................................................................................................. 539
3.16.13 NMI_INTRUPT_REGS Registers........................................................................................................................ 559
3.16.14 PIE_CTRL_REGS Registers............................................................................................................................... 579
3.16.15 ROM_PREFETCH_REGS Registers.................................................................................................................. 619
3.16.16 ROM_WAIT_STATE_REGS Registers................................................................................................................ 621
3.16.17 SYNC_SOC_REGS Registers............................................................................................................................ 623
3.16.18 SYS_STATUS_REGS Registers......................................................................................................................... 630
3.16.19 TEST_ERROR_REGS Registers........................................................................................................................ 643
3.16.20 UID_REGS Registers.......................................................................................................................................... 647
3.16.21 WD_REGS Registers.......................................................................................................................................... 656
3.16.22 XINT_REGS Registers........................................................................................................................................ 663
3.16.23 Register to Driverlib Function Mapping............................................................................................................... 672
4 C28x Processor...................................................................................................................................................................697
4.1 Introduction.................................................................................................................................................................... 698

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4.2 C28X Related Collateral.................................................................................................................................................698

4.3 Features......................................................................................................................................................................... 698
4.4 Floating-Point Unit..........................................................................................................................................................698
4.5 Trigonometric Math Unit (TMU)......................................................................................................................................699
4.6 VCRC Unit......................................................................................................................................................................699
5 ROM Code and Peripheral Booting...................................................................................................................................701
5.1 Introduction.................................................................................................................................................................... 702
5.1.1 ROM Related Collateral...........................................................................................................................................702
5.2 Device Boot Sequence...................................................................................................................................................703
5.3 Device Boot Modes........................................................................................................................................................ 704
5.4 Device Boot Configurations............................................................................................................................................705
5.4.1 Configuring Boot Mode Pins for CPU1.................................................................................................................... 706
5.4.2 Configuring Boot Mode Table Options for CPU1..................................................................................................... 708
5.4.3 Boot Mode Example Use Cases..............................................................................................................................709
5.5 Device Boot Flow Diagrams........................................................................................................................................... 711
5.5.1 CPU1 Boot Flow...................................................................................................................................................... 711
5.5.2 CPU2 Boot Flow...................................................................................................................................................... 714
5.5.3 Connectivity Manager (CM) Boot Flow....................................................................................................................715
5.6 Device Reset and Exception Handling...........................................................................................................................716
5.6.1 Reset Causes and Handling....................................................................................................................................716
5.6.2 Exceptions and Interrupts Handling.........................................................................................................................716
5.7 Boot ROM Description................................................................................................................................................... 718
5.7.1 CPU1 Boot ROM Configuration Registers...............................................................................................................718
5.7.2 Booting CPU2 and CM............................................................................................................................................ 720
5.7.3 Entry Points............................................................................................................................................................. 724
5.7.4 Wait Points...............................................................................................................................................................725
5.7.5 Memory Maps..........................................................................................................................................................726
5.7.6 ROM Tables.............................................................................................................................................................728
5.7.7 Boot Modes and Loaders........................................................................................................................................ 729
5.7.8 GPIO Assignments for CPU1.................................................................................................................................. 747
5.7.9 Secure ROM Function APIs.................................................................................................................................... 750
5.7.10 Clock Initializations................................................................................................................................................ 753
5.7.11 Boot Status information..........................................................................................................................................753
5.7.12 ROM Version......................................................................................................................................................... 757
5.8 Application Notes for Using the Bootloaders..................................................................................................................758
5.8.1 Boot Data Stream Structure.................................................................................................................................... 758
5.8.2 The C2000 Hex Utility..............................................................................................................................................760
5.9 Software......................................................................................................................................................................... 762
5.9.1 BOOT Examples......................................................................................................................................................762
6 Dual Code Security Module (DCSM)................................................................................................................................. 765
6.1 Introduction.................................................................................................................................................................... 766
6.1.1 DCSM Related Collateral........................................................................................................................................ 766
6.2 Functional Description....................................................................................................................................................766
6.2.1 CSM Passwords...................................................................................................................................................... 768
6.2.2 Emulation Code Security Logic (ECSL)...................................................................................................................770
6.2.3 CPU Secure Logic................................................................................................................................................... 770
6.2.4 Execute-Only Protection..........................................................................................................................................770
6.2.5 Password Lock........................................................................................................................................................ 770
6.2.6 JTAGLOCK.............................................................................................................................................................. 771
6.2.7 Link Pointer and Zone Select.................................................................................................................................. 771
6.2.8 C Code Example to Get Zone Select Block Addr for Zone1....................................................................................774
6.3 Flash and OTP Erase/Program......................................................................................................................................774
6.4 Secure Copy Code.........................................................................................................................................................774
6.5 SecureCRC.................................................................................................................................................................... 775
6.6 CSM Impact on Other On-Chip Resources....................................................................................................................775
6.7 Incorporating Code Security in User Applications..........................................................................................................777
6.7.1 Environments That Require Security Unlocking...................................................................................................... 777
6.7.2 CSM Password Match Flow.................................................................................................................................... 778
6.7.3 C Code Example to Unsecure C28x Zone1............................................................................................................ 779
6.7.4 C Code Example to Resecure C28x Zone1............................................................................................................ 779
6.7.5 Environments That Require ECSL Unlocking..........................................................................................................779

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6.7.6 ECSL Password Match Flow................................................................................................................................... 780

6.7.7 ECSL Disable Considerations for any Zone............................................................................................................ 781
6.7.8 Device Unique ID.....................................................................................................................................................781
6.8 Software......................................................................................................................................................................... 782
6.8.1 DCSM Examples..................................................................................................................................................... 782
6.9 DCSM Registers............................................................................................................................................................ 784
6.9.1 DCSM Base Address Table (C28)........................................................................................................................... 784
6.9.2 CM DCSM Base Address Table (CM)..................................................................................................................... 784
6.9.3 DCSM_Z1_REGS Registers................................................................................................................................... 785
6.9.4 DCSM_Z2_REGS Registers................................................................................................................................... 835
6.9.5 DCSM_COMMON_REGS Registers.......................................................................................................................876
6.9.6 DCSM_Z1_OTP Registers...................................................................................................................................... 897
6.9.7 DCSM_Z2_OTP Registers...................................................................................................................................... 914
7 Background CRC-32 (BGCRC).......................................................................................................................................... 925
7.1 Introduction.................................................................................................................................................................... 926
7.1.1 BGCRC Related Collateral...................................................................................................................................... 926
7.1.2 Features.................................................................................................................................................................. 926
7.1.3 Block Diagram......................................................................................................................................................... 926
7.1.4 Memory Wait States and Memory Map................................................................................................................... 927
7.2 Functional Description....................................................................................................................................................928
7.2.1 Data Read Unit........................................................................................................................................................ 928
7.2.2 CRC-32 Compute Unit.............................................................................................................................................928
7.2.3 CRC Notification Unit...............................................................................................................................................929
7.2.4 Operating Modes..................................................................................................................................................... 930
7.2.5 BGCRC Watchdog...................................................................................................................................................930
7.2.6 Hardware and Software Faults Protection...............................................................................................................930
7.3 Application of the BGCRC..............................................................................................................................................930
7.3.1 Software Configuration............................................................................................................................................ 931
7.3.2 Decision on Error Response Severity......................................................................................................................932
7.3.3 Decision of Controller for CLA_CRC....................................................................................................................... 932
7.3.4 Execution of Time Critical Code from Wait-Stated Memories..................................................................................932
7.3.5 BGCRC Execution...................................................................................................................................................932
7.3.6 Debug/Error Response for BGCRC Errors..............................................................................................................933
7.3.7 BGCRC Golden CRC-32 Value Computation..........................................................................................................934
7.4 Software......................................................................................................................................................................... 935
7.4.1 BGCRC Examples...................................................................................................................................................935
7.5 BGCRC Registers.......................................................................................................................................................... 936
7.5.1 BGCRC Base Address Table (C28).........................................................................................................................936
7.5.2 BGCRC_REGS Registers....................................................................................................................................... 937
7.5.3 BGCRC Registers to Driverlib Functions.................................................................................................................963
8 Control Law Accelerator (CLA)..........................................................................................................................................965
8.1 Introduction.................................................................................................................................................................... 966
8.1.1 Features.................................................................................................................................................................. 966
8.1.2 CLA Related Collateral............................................................................................................................................ 966
8.1.3 Block Diagram......................................................................................................................................................... 967
8.2 CLA Interface................................................................................................................................................................. 968
8.2.1 CLA Memory............................................................................................................................................................968
8.2.2 CLA Memory Bus.................................................................................................................................................... 969
8.2.3 Shared Peripherals and EALLOW Protection..........................................................................................................969
8.2.4 CLA Tasks and Interrupt Vectors............................................................................................................................. 970
8.2.5 CLA Software Interrupt to CPU............................................................................................................................... 975
8.3 CLA, DMA, and CPU Arbitration.................................................................................................................................... 975
8.3.1 CLA Message RAM................................................................................................................................................. 976
8.3.2 Peripheral Registers (ePWM, HRPWM, Comparator).............................................................................................976
8.4 CLA Configuration and Debug....................................................................................................................................... 977
8.4.1 Building a CLA Application...................................................................................................................................... 977
8.4.2 Typical CLA Initialization Sequence........................................................................................................................ 977
8.4.3 Debugging CLA Code..............................................................................................................................................979
8.4.4 CLA Illegal Opcode Behavior.................................................................................................................................. 981
8.4.5 Resetting the CLA................................................................................................................................................... 982
8.5 Pipeline.......................................................................................................................................................................... 982

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8.5.1 Pipeline Overview....................................................................................................................................................982

8.5.2 CLA Pipeline Alignment...........................................................................................................................................983
8.5.3 Parallel Instructions................................................................................................................................................. 988
8.5.4 CLA Task Execution Latency...................................................................................................................................988
8.6 Software......................................................................................................................................................................... 989
8.6.1 CLA Examples.........................................................................................................................................................989
8.7 Instruction Set................................................................................................................................................................ 994
8.7.1 Instruction Descriptions........................................................................................................................................... 994
8.7.2 Addressing Modes and Encoding............................................................................................................................995
8.7.3 Instructions.............................................................................................................................................................. 998
8.8 CLA Registers...............................................................................................................................................................1116
8.8.1 CLA Base Address Table (C28)............................................................................................................................. 1116
8.8.2 CLA_ONLY_REGS Registers................................................................................................................................ 1117
8.8.3 CLA_SOFTINT_REGS Registers.......................................................................................................................... 1125
8.8.4 CLA_REGS Registers............................................................................................................................................1129
8.8.5 CLA Registers to Driverlib Functions..................................................................................................................... 1176
9 Configurable Logic Block (CLB)......................................................................................................................................1179
9.1 Introduction...................................................................................................................................................................1180
9.1.1 CLB Related Collateral.......................................................................................................................................... 1180
9.2 Description....................................................................................................................................................................1180
9.2.1 CLB Clock.............................................................................................................................................................. 1182
9.3 CLB Input/Output Connection.......................................................................................................................................1184
9.3.1 Overview................................................................................................................................................................ 1184
9.3.2 CLB Input Selection............................................................................................................................................... 1184
9.3.3 CLB Output Selection............................................................................................................................................ 1198
9.3.4 CLB Output Signal Multiplexer.............................................................................................................................. 1200
9.4 CLB Tile........................................................................................................................................................................1203
9.4.1 Static Switch Block................................................................................................................................................ 1204
9.4.2 Counter Block........................................................................................................................................................ 1206
9.4.3 FSM Block............................................................................................................................................................. 1210
9.4.4 LUT4 Block............................................................................................................................................................ 1212
9.4.5 Output LUT Block.................................................................................................................................................. 1212
9.4.6 Asynchronous Output Conditioning (AOC) Block.................................................................................................. 1213
9.4.7 High Level Controller (HLC).................................................................................................................................. 1216
9.5 CPU Interface...............................................................................................................................................................1221
9.5.1 Register Description.............................................................................................................................................. 1221
9.5.2 Non-Memory Mapped Registers............................................................................................................................1222
9.6 DMA Access.................................................................................................................................................................1222
9.7 CLB Data Export Through SPI RX Buffer.....................................................................................................................1223
9.8 CLB Pipeline Mode...................................................................................................................................................... 1224
9.9 Software....................................................................................................................................................................... 1225
9.9.1 CLB Examples.......................................................................................................................................................1225
9.10 CLB Registers............................................................................................................................................................ 1230
9.10.1 CLB Base Address Table (C28)...........................................................................................................................1230
9.10.2 CLB_LOGIC_CONFIG_REGS Registers............................................................................................................ 1232
9.10.3 CLB_LOGIC_CONTROL_REGS Registers........................................................................................................ 1284
9.10.4 CLB_DATA_EXCHANGE_REGS Registers........................................................................................................ 1316
9.10.5 CLB Registers to Driverlib Functions...................................................................................................................1318
10 Dual-Clock Comparator (DCC).......................................................................................................................................1323
10.1 Introduction................................................................................................................................................................ 1324
10.1.1 Features.............................................................................................................................................................. 1324
10.1.2 Block Diagram..................................................................................................................................................... 1324
10.2 Module Operation.......................................................................................................................................................1325
10.2.1 Configuring DCC Counters..................................................................................................................................1326
10.2.2 Single-Shot Measurement Mode......................................................................................................................... 1327
10.2.3 Continuous Monitoring Mode...............................................................................................................................1328
10.2.4 Error Conditions...................................................................................................................................................1329
10.3 Interrupts.................................................................................................................................................................... 1331
10.4 Software..................................................................................................................................................................... 1332
10.4.1 DCC Examples.................................................................................................................................................... 1332
10.5 DCC Registers........................................................................................................................................................... 1334

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10.5.1 DCC Base Address Table (C28)..........................................................................................................................1334

10.5.2 DCC_REGS Registers........................................................................................................................................ 1335
10.5.3 DCC Registers to Driverlib Functions..................................................................................................................1345
11 Direct Memory Access (DMA)........................................................................................................................................1347
11.1 Introduction.................................................................................................................................................................1348
11.1.1 Features...............................................................................................................................................................1348
11.1.2 Block Diagram......................................................................................................................................................1349
11.2 Architecture................................................................................................................................................................ 1350
11.2.1 Peripheral Interrupt Event Trigger Sources......................................................................................................... 1350
11.2.2 DMA Bus..............................................................................................................................................................1355
11.3 Address Pointer and Transfer Control........................................................................................................................ 1355
11.4 Pipeline Timing and Throughput.................................................................................................................................1361
11.5 CPU and CLA Arbitration............................................................................................................................................1362
11.6 Channel Priority.......................................................................................................................................................... 1363
11.6.1 Round-Robin Mode..............................................................................................................................................1363
11.6.2 Channel 1 High-Priority Mode..............................................................................................................................1364
11.7 Overrun Detection Feature......................................................................................................................................... 1364
11.8 Software..................................................................................................................................................................... 1365
11.8.1 DMA Examples.................................................................................................................................................... 1365
11.9 DMA Registers........................................................................................................................................................... 1366
11.9.1 DMA Base Address Table (C28).......................................................................................................................... 1366
11.9.2 DMA_REGS Registers.........................................................................................................................................1367
11.9.3 DMA_CH_REGS Registers................................................................................................................................. 1372
11.9.4 DMA Registers to Driverlib Functions.................................................................................................................. 1399
12 External Memory Interface (EMIF).................................................................................................................................1403
12.1 Introduction................................................................................................................................................................ 1404
12.1.1 EMIF Related Collateral...................................................................................................................................... 1405
12.1.2 Purpose of the Peripheral....................................................................................................................................1405
12.1.3 Features.............................................................................................................................................................. 1405
12.1.4 Functional Block Diagram....................................................................................................................................1406
12.1.5 Configuring Device Pins...................................................................................................................................... 1407
12.2 EMIF Module Architecture..........................................................................................................................................1407
12.2.1 EMIF Clock Control............................................................................................................................................. 1407
12.2.2 EMIF Requests....................................................................................................................................................1407
12.2.3 EMIF Signal Descriptions.................................................................................................................................... 1408
12.2.4 EMIF Signal Multiplexing Control........................................................................................................................ 1409
12.2.5 SDRAM Controller and Interface......................................................................................................................... 1409
12.2.6 Asynchronous Controller and Interface............................................................................................................... 1422
12.2.7 Data Bus Parking.................................................................................................................................................1433
12.2.8 Reset and Initialization Considerations............................................................................................................... 1434
12.2.9 Interrupt Support..................................................................................................................................................1434
12.2.10 DMA Event Support...........................................................................................................................................1435
12.2.11 EMIF Signal Multiplexing................................................................................................................................... 1435
12.2.12 Memory Map......................................................................................................................................................1435
12.2.13 Priority and Arbitration....................................................................................................................................... 1436
12.2.14 System Considerations......................................................................................................................................1436
12.2.15 Power Management.......................................................................................................................................... 1437
12.2.16 Emulation Considerations..................................................................................................................................1437
12.3 Example Configuration...............................................................................................................................................1438
12.3.1 Hardware Interface.............................................................................................................................................. 1438
12.3.2 Software Configuration........................................................................................................................................ 1438
12.4 Software..................................................................................................................................................................... 1447
12.4.1 EMIF Examples................................................................................................................................................... 1447
12.5 EMIF Registers.......................................................................................................................................................... 1450
12.5.1 EMIF Base Address Table (C28)......................................................................................................................... 1450
12.5.2 EMIF_REGS Registers........................................................................................................................................1451
12.5.3 EMIF1_CONFIG_REGS Registers......................................................................................................................1472
12.5.4 EMIF2_CONFIG_REGS Registers......................................................................................................................1477
12.5.5 EMIF Registers to Driverlib Functions................................................................................................................. 1480
13 Flash Module...................................................................................................................................................................1483
13.1 Introduction to Flash and OTP Memory..................................................................................................................... 1484

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13.1.1 FLASH Related Collateral................................................................................................................................... 1484

13.1.2 Features.............................................................................................................................................................. 1484
13.1.3 Flash Tools.......................................................................................................................................................... 1485
13.1.4 Default Flash Configuration................................................................................................................................. 1485
13.2 Flash Bank, OTP, and Pump...................................................................................................................................... 1485
13.3 Flash Module Controller (FMC)..................................................................................................................................1486
13.4 Flash and OTP Memory Power-Down Modes and Wakeup.......................................................................................1487
13.5 Active Grace Period................................................................................................................................................... 1489
13.6 Flash and OTP Memory Performance....................................................................................................................... 1489
13.7 Flash Read Interface..................................................................................................................................................1490
13.7.1 C28x-FMC (CPU1-FMC and CPU2-FMC) Flash Read Interface........................................................................ 1490
13.7.2 M4-FMC (CM-FMC) Flash Read Interface.......................................................................................................... 1492
13.8 Flash Erase and Program.......................................................................................................................................... 1495
13.8.1 Erase................................................................................................................................................................... 1495
13.8.2 Program...............................................................................................................................................................1495
13.8.3 Verify....................................................................................................................................................................1495
13.9 Error Correction Code (ECC) Protection....................................................................................................................1496
13.9.1 Single-Bit Data Error............................................................................................................................................1497
13.9.2 Uncorrectable Error............................................................................................................................................. 1498
13.9.3 SECDED Logic Correctness Check.................................................................................................................... 1499
13.10 Reserved Locations Within Flash and OTP Memory............................................................................................... 1500
13.11 Migrating an Application from RAM to Flash............................................................................................................ 1500
13.12 Procedure to Change the Flash Control Registers.................................................................................................. 1501
13.13 Flash Pump Ownership Semaphore........................................................................................................................ 1501
13.14 Software................................................................................................................................................................... 1503
13.14.1 FLASH Examples.............................................................................................................................................. 1503
13.15 Flash Registers........................................................................................................................................................ 1504
13.15.1 FLASH Base Address Table (C28).................................................................................................................... 1504
13.15.2 CM FLASH Base Address Table (CM).............................................................................................................. 1504
13.15.3 FLASH_CTRL_REGS Registers....................................................................................................................... 1505
13.15.4 FLASH_ECC_REGS Registers......................................................................................................................... 1514
13.15.5 CM_FLASH_CTRL_REGS Registers................................................................................................................1537
13.15.6 CM_FLASH_ECC_REGS Registers................................................................................................................. 1547
13.15.7 FLASH_PUMP_SEMAPHORE_REGS Registers............................................................................................. 1571
13.15.8 FLASH Registers to Driverlib Functions............................................................................................................ 1572
14 Embedded Real-time Analysis and Diagnostic (ERAD).............................................................................................. 1575
14.1 Introduction................................................................................................................................................................ 1576
14.1.1 ERAD Related Collateral..................................................................................................................................... 1577
14.2 Enhanced Bus Comparator Unit................................................................................................................................ 1577
14.2.1 Enhanced Bus Comparator Unit Operations....................................................................................................... 1577
14.2.2 Event Masking and Exporting..............................................................................................................................1578
14.3 System Event Counter Unit........................................................................................................................................1579
14.3.1 System Event Counter Modes.............................................................................................................................1579
14.3.2 Reset on Event.................................................................................................................................................... 1584
14.3.3 Operation Conditions...........................................................................................................................................1584
14.4 ERAD Ownership, Initialization and Reset.................................................................................................................1584
14.5 ERAD Programming Sequence................................................................................................................................. 1585
14.5.1 Hardware Breakpoint and Hardware Watch Point Programming Sequence....................................................... 1585
14.5.2 Timer and Counter Programming Sequence....................................................................................................... 1586
14.6 Cyclic Redundancy Check Unit..................................................................................................................................1586
14.6.1 CRC Unit Qualifier............................................................................................................................................... 1587
14.6.2 CRC Unit Programming Sequence......................................................................................................................1588
14.7 Program Counter Trace..............................................................................................................................................1589
14.7.1 Functional Block Diagram....................................................................................................................................1590
14.7.2 Trace Qualification Modes................................................................................................................................... 1591
14.7.3 Trace Memory......................................................................................................................................................1591
14.7.4 Trace Input Signal Conditioning...........................................................................................................................1592
14.7.5 PC Trace Software Operation..............................................................................................................................1593
14.7.6 Trace Operation in Debug Mode......................................................................................................................... 1593
14.8 Software..................................................................................................................................................................... 1594
14.8.1 ERAD Examples..................................................................................................................................................1594

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14.9 ERAD Registers......................................................................................................................................................... 1601

14.9.1 ERAD Base Address Table (C28)........................................................................................................................1601
14.9.2 ERAD_GLOBAL_REGS Registers......................................................................................................................1603
14.9.3 ERAD_HWBP_REGS Registers......................................................................................................................... 1624
14.9.4 ERAD_COUNTER_REGS Registers.................................................................................................................. 1631
14.9.5 ERAD_CRC_GLOBAL_REGS Registers............................................................................................................ 1642
14.9.6 ERAD_CRC_REGS Registers............................................................................................................................ 1645
14.9.7 ERAD Registers to Driverlib Functions................................................................................................................1648
15 General-Purpose Input/Output (GPIO)..........................................................................................................................1651
15.1 Introduction................................................................................................................................................................ 1652
15.1.1 GPIO Related Collateral...................................................................................................................................... 1654
15.2 Configuration Overview..............................................................................................................................................1654
15.3 Digital General-Purpose I/O Control.......................................................................................................................... 1655
15.4 Input Qualification...................................................................................................................................................... 1657
15.4.1 No Synchronization (Asynchronous Input).......................................................................................................... 1657
15.4.2 Synchronization to SYSCLKOUT Only................................................................................................................1657
15.4.3 Qualification Using a Sampling Window..............................................................................................................1657
15.5 USB Signals............................................................................................................................................................... 1661
15.6 SPI Signals.................................................................................................................................................................1661
15.7 GPIO and Peripheral Muxing..................................................................................................................................... 1662
15.7.1 GPIO Muxing....................................................................................................................................................... 1662
15.7.2 Peripheral Muxing................................................................................................................................................1669
15.8 Internal Pullup Configuration Requirements.............................................................................................................. 1670
15.9 Software..................................................................................................................................................................... 1671
15.9.1 GPIO Examples...................................................................................................................................................1671
15.9.2 LED Examples.....................................................................................................................................................1671
15.10 GPIO Registers........................................................................................................................................................ 1672
15.10.1 GPIO Base Address Table (C28).......................................................................................................................1672
15.10.2 CM GPIO Base Address Table (CM)................................................................................................................. 1672
15.10.3 GPIO_CTRL_REGS Registers..........................................................................................................................1674
15.10.4 GPIO_DATA_REGS Registers.......................................................................................................................... 1827
15.10.5 GPIO_DATA_READ_REGS Registers.............................................................................................................. 1877
15.10.6 CM_GPIO_DATA_REGS Registers...................................................................................................................1884
15.10.7 CM_GPIO_DATA_READ_REGS Registers.......................................................................................................1934
15.10.8 GPIO Registers to Driverlib Functions...............................................................................................................1942
16 Interprocessor Communication (IPC)........................................................................................................................... 1949
16.1 Introduction................................................................................................................................................................ 1950
16.2 Message RAMs..........................................................................................................................................................1950
16.3 IPC Flags and Interrupts............................................................................................................................................ 1953
16.4 IPC Command Registers........................................................................................................................................... 1953
16.5 Free-Running Counter............................................................................................................................................... 1953
16.6 IPC Communication Protocol..................................................................................................................................... 1954
16.7 Software..................................................................................................................................................................... 1955
16.7.1 IPC Examples......................................................................................................................................................1955
16.8 IPC Registers............................................................................................................................................................. 1958
16.8.1 IPC Base Address Table (C28)............................................................................................................................1958
16.8.2 CM IPC Base Address Table (CM)...................................................................................................................... 1958
16.8.3 CPU1TOCPU2_IPC_REGS_CPU1VIEW Registers........................................................................................... 1959
16.8.4 CPU1TOCPU2_IPC_REGS_CPU2VIEW Registers........................................................................................... 1993
16.8.5 CPU1TOCM_IPC_REGS_CPU1VIEW Registers............................................................................................... 2027
16.8.6 CPU1TOCM_IPC_REGS_CMVIEW Registers................................................................................................... 2060
16.8.7 CPU2TOCM_IPC_REGS_CPU2VIEW Registers............................................................................................... 2094
16.8.8 CPU2TOCM_IPC_REGS_CMVIEW Registers................................................................................................... 2125
16.8.9 IPC Registers to Driverlib Functions....................................................................................................................2155
17 Crossbar (X-BAR)........................................................................................................................................................... 2161
17.1 Input X-BAR and CLB Input X-BAR .......................................................................................................................... 2162
17.1.1 CLB Input X-BAR.................................................................................................................................................2165
17.2 ePWM, CLB, and GPIO Output X-BAR......................................................................................................................2166
17.2.1 ePWM X-BAR......................................................................................................................................................2166
17.2.2 CLB X-BAR..........................................................................................................................................................2168
17.2.3 GPIO Output X-BAR............................................................................................................................................2171

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17.2.4 CLB Output X-BAR..............................................................................................................................................2173

17.2.5 X-BAR Flags........................................................................................................................................................2174
17.3 XBAR Registers......................................................................................................................................................... 2176
17.3.1 XBAR Base Address Table (C28)........................................................................................................................2176
17.3.2 INPUT_XBAR_REGS Registers..........................................................................................................................2177
17.3.3 XBAR_REGS Registers...................................................................................................................................... 2197
17.3.4 EPWM_XBAR_REGS Registers......................................................................................................................... 2230
17.3.5 CLB_XBAR_REGS Registers............................................................................................................................. 2323
17.3.6 OUTPUT_XBAR_REGS Registers......................................................................................................................2416
17.3.7 Register to Driverlib Function Mapping............................................................................................................... 2517
18 ► ANALOG PERIPHERALS........................................................................................................................................... 2523
18.1 Technical Reference Manual Overview......................................................................................................................2523
19 Analog Subsystem......................................................................................................................................................... 2525
19.1 Introduction................................................................................................................................................................ 2526
19.1.1 Features.............................................................................................................................................................. 2526
19.1.2 Block Diagram..................................................................................................................................................... 2526
19.2 Optimizing Power-Up Time........................................................................................................................................ 2529
19.3 Analog Subsystem Registers..................................................................................................................................... 2530
19.3.1 ASBSYS Base Address Table (C28)................................................................................................................... 2530
19.3.2 ANALOG_SUBSYS_REGS Registers.................................................................................................................2531
20 Analog-to-Digital Converter (ADC)................................................................................................................................2541
20.1 Introduction................................................................................................................................................................ 2542
20.1.1 ADC Related Collateral....................................................................................................................................... 2542
20.1.2 Features.............................................................................................................................................................. 2543
20.1.3 Block Diagram..................................................................................................................................................... 2544
20.2 ADC Configurability....................................................................................................................................................2545
20.2.1 Clock Configuration............................................................................................................................................. 2545
20.2.2 Resolution............................................................................................................................................................2545
20.2.3 Voltage Reference............................................................................................................................................... 2546
20.2.4 Signal Mode.........................................................................................................................................................2546
20.2.5 Expected Conversion Results............................................................................................................................. 2547
20.2.6 Interpreting Conversion Results.......................................................................................................................... 2548
20.3 SOC Principle of Operation........................................................................................................................................2549
20.3.1 SOC Configuration.............................................................................................................................................. 2550
20.3.2 Trigger Operation.................................................................................................................................................2550
20.3.3 ADC Acquisition (Sample and Hold) Window......................................................................................................2550
20.3.4 ADC Input Models............................................................................................................................................... 2551
20.3.5 Channel Selection............................................................................................................................................... 2552
20.4 SOC Configuration Examples.................................................................................................................................... 2553
20.4.1 Single Conversion from ePWM Trigger............................................................................................................... 2553
20.4.2 Oversampled Conversion from ePWM Trigger....................................................................................................2553
20.4.3 Multiple Conversions from CPU Timer Trigger.................................................................................................... 2554
20.4.4 Software Triggering of SOCs...............................................................................................................................2555
20.5 ADC Conversion Priority............................................................................................................................................ 2555
20.6 Burst Mode.................................................................................................................................................................2558
20.6.1 Burst Mode Example........................................................................................................................................... 2558
20.6.2 Burst Mode Priority Example............................................................................................................................... 2559
20.7 EOC and Interrupt Operation..................................................................................................................................... 2560
20.7.1 Interrupt Overflow................................................................................................................................................ 2561
20.7.2 Continue to Interrupt Mode..................................................................................................................................2561
20.7.3 Early Interrupt Configuration Mode......................................................................................................................2562
20.8 Post-Processing Blocks............................................................................................................................................. 2563
20.8.1 PPB Offset Correction......................................................................................................................................... 2564
20.8.2 PPB Error Calculation..........................................................................................................................................2564
20.8.3 PPB Limit Detection and Zero-Crossing Detection..............................................................................................2564
20.8.4 PPB Sample Delay Capture................................................................................................................................ 2566
20.9 Opens/Shorts Detection Circuit (OSDETECT)...........................................................................................................2567
20.9.1 Implementation.................................................................................................................................................... 2568
20.9.2 Detecting an Open Input Pin............................................................................................................................... 2568
20.9.3 Detecting a Shorted Input Pin..............................................................................................................................2568
20.10 Power-Up Sequence................................................................................................................................................ 2569

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20.11 ADC Calibration........................................................................................................................................................2569

20.11.1 ADC Zero Offset Calibration.............................................................................................................................. 2570
20.11.2 ADC Calibration Routines in OTP Memory........................................................................................................2570
20.12 ADC Timings............................................................................................................................................................ 2571
20.12.1 ADC Timing Diagrams....................................................................................................................................... 2571
20.13 Additional Information.............................................................................................................................................. 2577
20.13.1 Ensuring Synchronous Operation......................................................................................................................2577
20.13.2 Choosing an Acquisition Window Duration........................................................................................................2581
20.13.3 Achieving Simultaneous Sampling.................................................................................................................... 2583
20.13.4 Result Register Mapping................................................................................................................................... 2583
20.13.5 Internal Temperature Sensor............................................................................................................................. 2583
20.13.6 Designing an External Reference Circuit...........................................................................................................2584
20.14 Software................................................................................................................................................................... 2586
20.14.1 ADC Examples.................................................................................................................................................. 2586
20.15 ADC Registers......................................................................................................................................................... 2593
20.15.1 ADC Base Address Table (C28)........................................................................................................................ 2593
20.15.2 ADC_REGS Registers.......................................................................................................................................2594
20.15.3 ADC_RESULT_REGS Registers.......................................................................................................................2728
20.15.4 ADC Registers to Driverlib Functions................................................................................................................ 2749
21 Buffered Digital-to-Analog Converter (DAC)................................................................................................................2755
21.1 Introduction................................................................................................................................................................ 2756
21.1.1 DAC Related Collateral....................................................................................................................................... 2756
21.1.2 Features.............................................................................................................................................................. 2756
21.1.3 Block Diagram..................................................................................................................................................... 2756
21.2 Using the DAC........................................................................................................................................................... 2757
21.2.1 Initialization Sequence.........................................................................................................................................2757
21.2.2 DAC Offset Adjustment........................................................................................................................................2758
21.2.3 EPWMSYNCPER Signal..................................................................................................................................... 2758
21.3 Lock Registers........................................................................................................................................................... 2758
21.4 Software..................................................................................................................................................................... 2759
21.4.1 DAC Examples.................................................................................................................................................... 2759
21.5 DAC Registers........................................................................................................................................................... 2760
21.5.1 DAC Base Address Table (C28).......................................................................................................................... 2760
21.5.2 DAC_REGS Registers.........................................................................................................................................2761
21.5.3 DAC Registers to Driverlib Functions.................................................................................................................. 2768
22 Comparator Subsystem (CMPSS)................................................................................................................................. 2769
22.1 Introduction................................................................................................................................................................ 2770
22.1.1 CMPSS Related Collateral.................................................................................................................................. 2770
22.1.2 Features.............................................................................................................................................................. 2770
22.1.3 Block Diagram..................................................................................................................................................... 2771
22.2 Comparator................................................................................................................................................................ 2771
22.3 Reference DAC.......................................................................................................................................................... 2772
22.4 Ramp Generator........................................................................................................................................................ 2773
22.4.1 Ramp Generator Overview..................................................................................................................................2773
22.4.2 Ramp Generator Behavior...................................................................................................................................2774
22.4.3 Ramp Generator Behavior at Corner Cases....................................................................................................... 2775
22.5 Digital Filter................................................................................................................................................................ 2776
22.5.1 Filter Initialization Sequence................................................................................................................................2777
22.6 Using the CMPSS...................................................................................................................................................... 2777
22.6.1 LATCHCLR, EPWMSYNCPER and EPWMBLANK Signals ...............................................................................2777
22.6.2 Synchronizer, Digital Filter, and Latch Delays..................................................................................................... 2777
22.6.3 Calibrating the CMPSS .......................................................................................................................................2778
22.6.4 Enabling and Disabling the CMPSS Clock.......................................................................................................... 2778
22.7 Software..................................................................................................................................................................... 2779
22.7.1 CMPSS Examples............................................................................................................................................... 2779
22.8 CMPSS Registers...................................................................................................................................................... 2780
22.8.1 CMPSS Base Address Table (C28).....................................................................................................................2780
22.8.2 CMPSS_REGS Registers................................................................................................................................... 2781
22.8.3 CMPSS Registers to Driverlib Functions.............................................................................................................2805
23 ► CONTROL PERIPHERALS.........................................................................................................................................2809
23.1 Technical Reference Manual Overview......................................................................................................................2809

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24 Enhanced Capture (eCAP)............................................................................................................................................. 2811

24.1 Introduction................................................................................................................................................................ 2812
24.1.1 Features.............................................................................................................................................................. 2812
24.1.2 ECAP Related Collateral..................................................................................................................................... 2812
24.2 Description................................................................................................................................................................. 2813
24.3 Configuring Device Pins for the eCAP....................................................................................................................... 2813
24.4 Capture and APWM Operating Mode........................................................................................................................ 2819
24.5 Capture Mode Description......................................................................................................................................... 2821
24.5.1 Event Prescaler................................................................................................................................................... 2822
24.5.2 Edge Polarity Select and Qualifier.......................................................................................................................2823
24.5.3 Continuous/One-Shot Control............................................................................................................................. 2823
24.5.4 32-Bit Counter and Phase Control.......................................................................................................................2824
24.5.5 CAP1-CAP4 Registers........................................................................................................................................ 2824
24.5.6 eCAP Synchronization.........................................................................................................................................2825
24.5.7 Interrupt Control...................................................................................................................................................2826
24.5.8 DMA Interrupt...................................................................................................................................................... 2828
24.5.9 Shadow Load and Lockout Control..................................................................................................................... 2828
24.5.10 APWM Mode Operation.....................................................................................................................................2828
24.6 Application of the eCAP Module................................................................................................................................ 2830
24.6.1 Example 1 - Absolute Time-Stamp Operation Rising-Edge Trigger.................................................................... 2830
24.6.2 Example 2 - Absolute Time-Stamp Operation Rising- and Falling-Edge Trigger.................................................2831
24.6.3 Example 3 - Time Difference (Delta) Operation Rising-Edge Trigger..................................................................2832
24.6.4 Example 4 - Time Difference (Delta) Operation Rising- and Falling-Edge Trigger.............................................. 2833
24.7 Application of the APWM Mode................................................................................................................................. 2834
24.7.1 Example 1 - Simple PWM Generation (Independent Channels)......................................................................... 2834
24.8 Software..................................................................................................................................................................... 2835
24.8.1 ECAP Examples.................................................................................................................................................. 2835
24.9 eCAP Registers..........................................................................................................................................................2836
24.9.1 ECAP Base Address Table (C28)........................................................................................................................2836
24.9.2 ECAP_REGS Registers...................................................................................................................................... 2837
24.9.3 ECAP Registers to Driverlib Functions................................................................................................................2855
25 High Resolution Capture (HRCAP)................................................................................................................................2859
25.1 Introduction................................................................................................................................................................ 2860
25.1.1 HRCAP Related Collateral.................................................................................................................................. 2860
25.1.2 Features.............................................................................................................................................................. 2860
25.1.3 Description...........................................................................................................................................................2860
25.2 Operational Details.....................................................................................................................................................2861
25.2.1 HRCAP Clocking................................................................................................................................................. 2863
25.2.2 HRCAP Initialization Sequence........................................................................................................................... 2863
25.2.3 HRCAP Interrupts................................................................................................................................................2863
25.2.4 HRCAP Calibration..............................................................................................................................................2864
25.3 Known Exceptions......................................................................................................................................................2865
25.4 Software..................................................................................................................................................................... 2866
25.4.1 HRCAP Examples............................................................................................................................................... 2866
25.5 HRCAP Registers...................................................................................................................................................... 2866
25.5.1 HRCAP Base Address Table (C28)..................................................................................................................... 2866
25.5.2 HRCAP_REGS Registers....................................................................................................................................2867
25.5.3 HRCAP Registers to Driverlib Functions............................................................................................................. 2877
26 Enhanced Pulse Width Modulator (ePWM)...................................................................................................................2879
26.1 Introduction................................................................................................................................................................ 2880
26.1.1 EPWM Related Collateral....................................................................................................................................2881
26.1.2 Submodule Overview.......................................................................................................................................... 2882
26.2 Configuring Device Pins.............................................................................................................................................2887
26.3 ePWM Modules Overview..........................................................................................................................................2887
26.4 Time-Base (TB) Submodule.......................................................................................................................................2889
26.4.1 Purpose of the Time-Base Submodule................................................................................................................2889
26.4.2 Controlling and Monitoring the Time-Base Submodule....................................................................................... 2890
26.4.3 Calculating PWM Period and Frequency.............................................................................................................2892
26.4.4 Phase Locking the Time-Base Clocks of Multiple ePWM Modules..................................................................... 2897
26.4.5 Simultaneous Writes to TBPRD and CMPx Registers Between ePWM Modules............................................... 2897
26.4.6 Time-Base Counter Modes and Timing Waveforms............................................................................................ 2898

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26.4.7 Global Load......................................................................................................................................................... 2901

26.5 Counter-Compare (CC) Submodule...........................................................................................................................2903
26.5.1 Purpose of the Counter-Compare Submodule.................................................................................................... 2903
26.5.2 Controlling and Monitoring the Counter-Compare Submodule............................................................................2904
26.5.3 Operational Highlights for the Counter-Compare Submodule............................................................................. 2905
26.5.4 Count Mode Timing Waveforms.......................................................................................................................... 2906
26.6 Action-Qualifier (AQ) Submodule...............................................................................................................................2909
26.6.1 Purpose of the Action-Qualifier Submodule........................................................................................................ 2909
26.6.2 Action-Qualifier Submodule Control and Status Register Definitions..................................................................2910
26.6.3 Action-Qualifier Event Priority..............................................................................................................................2912
26.6.4 AQCTLA and AQCTLB Shadow Mode Operations............................................................................................. 2913
26.6.5 Configuration Requirements for Common Waveforms........................................................................................ 2915
26.7 Dead-Band Generator (DB) Submodule.................................................................................................................... 2922
26.7.1 Purpose of the Dead-Band Submodule...............................................................................................................2922
26.7.2 Dead-band Submodule Additional Operating Modes.......................................................................................... 2923
26.7.3 Operational Highlights for the Dead-Band Submodule........................................................................................2925
26.8 PWM Chopper (PC) Submodule................................................................................................................................ 2929
26.8.1 Purpose of the PWM Chopper Submodule......................................................................................................... 2929
26.8.2 Operational Highlights for the PWM Chopper Submodule.................................................................................. 2929
26.8.3 Waveforms...........................................................................................................................................................2930
26.9 Trip-Zone (TZ) Submodule.........................................................................................................................................2933
26.9.1 Purpose of the Trip-Zone Submodule..................................................................................................................2933
26.9.2 Operational Highlights for the Trip-Zone Submodule.......................................................................................... 2934
26.9.3 Generating Trip Event Interrupts......................................................................................................................... 2937
26.10 Event-Trigger (ET) Submodule................................................................................................................................ 2939
26.10.1 Operational Overview of the ePWM Event-Trigger Submodule........................................................................ 2940
26.11 Digital Compare (DC) Submodule............................................................................................................................ 2944
26.11.1 Purpose of the Digital Compare Submodule......................................................................................................2946
26.11.2 Enhanced Trip Action Using CMPSS.................................................................................................................2946
26.11.3 Using CMPSS to Trip the ePWM on a Cycle-by-Cycle Basis............................................................................ 2946
26.11.4 Operation Highlights of the Digital Compare Submodule.................................................................................. 2947
26.12 ePWM Crossbar (X-BAR)........................................................................................................................................ 2954
26.13 Applications to Power Topologies............................................................................................................................ 2955
26.13.1 Overview of Multiple Modules............................................................................................................................2955
26.13.2 Key Configuration Capabilities.......................................................................................................................... 2956
26.13.3 Controlling Multiple Buck Converters With Independent Frequencies.............................................................. 2957
26.13.4 Controlling Multiple Buck Converters With Same Frequencies......................................................................... 2959
26.13.5 Controlling Multiple Half H-Bridge (HHB) Converters........................................................................................2961
26.13.6 Controlling Dual 3-Phase Inverters for Motors (ACI and PMSM)...................................................................... 2963
26.13.7 Practical Applications Using Phase Control Between PWM Modules............................................................... 2965
26.13.8 Controlling a 3-Phase Interleaved DC/DC Converter........................................................................................ 2966
26.13.9 Controlling Zero Voltage Switched Full Bridge (ZVSFB) Converter.................................................................. 2969
26.13.10 Controlling a Peak Current Mode Controlled Buck Module............................................................................. 2971
26.13.11 Controlling H-Bridge LLC Resonant Converter................................................................................................2972
26.14 Register Lock Protection.......................................................................................................................................... 2973
26.15 High-Resolution Pulse Width Modulator (HRPWM)................................................................................................. 2974
26.15.1 Operational Description of HRPWM.................................................................................................................. 2976
26.15.2 SFO Library Software - SFO_TI_Build_V8.lib................................................................................................... 2997
26.16 Software................................................................................................................................................................... 3000
26.16.1 EPWM Examples...............................................................................................................................................3000
26.16.2 HRPWM Examples............................................................................................................................................3004
26.17 ePWM Registers...................................................................................................................................................... 3007
26.17.1 EPWM Base Address Table (C28).................................................................................................................... 3007
26.17.2 EPWM_REGS Registers................................................................................................................................... 3008
26.17.3 SYNC_SOC_REGS Registers.......................................................................................................................... 3129
26.17.4 Register to Driverlib Function Mapping............................................................................................................. 3136
27 Enhanced Quadrature Encoder Pulse (eQEP)............................................................................................................. 3149
27.1 Introduction................................................................................................................................................................ 3150
27.1.1 EQEP Related Collateral..................................................................................................................................... 3152
27.2 Configuring Device Pins.............................................................................................................................................3152
27.3 Description................................................................................................................................................................. 3153

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27.3.1 EQEP Inputs........................................................................................................................................................3153

27.3.2 Functional Description......................................................................................................................................... 3156
27.3.3 eQEP Memory Map............................................................................................................................................. 3157
27.4 Quadrature Decoder Unit (QDU)................................................................................................................................3158
27.4.1 Position Counter Input Modes............................................................................................................................. 3158
27.4.2 eQEP Input Polarity Selection............................................................................................................................. 3161
27.4.3 Position-Compare Sync Output........................................................................................................................... 3161
27.5 Position Counter and Control Unit (PCCU)................................................................................................................ 3161
27.5.1 Position Counter Operating Modes..................................................................................................................... 3161
27.5.2 Position Counter Latch........................................................................................................................................ 3164
27.5.3 Position Counter Initialization.............................................................................................................................. 3166
27.5.4 eQEP Position-compare Unit...............................................................................................................................3167
27.6 eQEP Edge Capture Unit........................................................................................................................................... 3169
27.7 eQEP Watchdog.........................................................................................................................................................3173
27.8 eQEP Unit Timer Base............................................................................................................................................... 3173
27.9 QMA Module.............................................................................................................................................................. 3174
27.9.1 Modes of Operation............................................................................................................................................. 3175
27.9.2 Interrupt and Error Generation............................................................................................................................ 3176
27.10 eQEP Interrupt Structure..........................................................................................................................................3177
27.11 Software................................................................................................................................................................... 3178
27.11.1 EQEP Examples................................................................................................................................................ 3178
27.12 eQEP Registers....................................................................................................................................................... 3181
27.12.1 EQEP Base Address Table (C28)......................................................................................................................3181
27.12.2 EQEP_REGS Registers.................................................................................................................................... 3182
27.12.3 EQEP Registers to Driverlib Functions..............................................................................................................3218
28 Sigma Delta Filter Module (SDFM)................................................................................................................................ 3221
28.1 Introduction................................................................................................................................................................ 3222
28.1.1 SDFM Related Collateral.....................................................................................................................................3222
28.1.2 Features.............................................................................................................................................................. 3223
28.1.3 Block Diagram..................................................................................................................................................... 3224
28.2 Configuring Device Pins.............................................................................................................................................3226
28.3 Input Qualification...................................................................................................................................................... 3227
28.4 Input Control Unit....................................................................................................................................................... 3228
28.5 SDFM Clock Control.................................................................................................................................................. 3228
28.6 Sinc Filter................................................................................................................................................................... 3229
28.6.1 Data Rate and Latency of the Sinc Filter.............................................................................................................3231
28.7 Data (Primary) Filter Unit........................................................................................................................................... 3232
28.7.1 32-bit or 16-bit Data Filter Output Representation...............................................................................................3233
28.7.2 Data FIFO............................................................................................................................................................3233
28.7.3 SDSYNC Event................................................................................................................................................... 3235
28.8 Comparator (Secondary) Filter Unit........................................................................................................................... 3237
28.8.1 Higher Threshold (HLT) Comparators ................................................................................................................ 3239
28.8.2 Lower Threshold (LLT) Comparators ..................................................................................................................3239
28.8.3 Digital Filter..........................................................................................................................................................3240
28.9 Theoretical SDFM Filter Output................................................................................................................................. 3241
28.10 Interrupt Unit............................................................................................................................................................ 3243
28.10.1 SDFM (SDyERR) Interrupt Sources ................................................................................................................. 3243
28.10.2 Data Ready (DRINT) Interrupt Sources.............................................................................................................3244
28.11 Software................................................................................................................................................................... 3246
28.11.1 SDFM Examples................................................................................................................................................ 3246
28.12 SDFM Registers.......................................................................................................................................................3250
28.12.1 SDFM Base Address Table (C28)..................................................................................................................... 3250
28.12.2 SDFM_REGS Registers.................................................................................................................................... 3251
28.12.3 SDFM Registers to Driverlib Functions............................................................................................................. 3345
29 ► COMMUNICATION PERIPHERALS............................................................................................................................3351
29.1 Technical Reference Manual Overview......................................................................................................................3351
30 Controller Area Network (CAN)..................................................................................................................................... 3353
30.1 Introduction................................................................................................................................................................ 3354
30.1.1 DCAN Related Collateral.....................................................................................................................................3354
30.1.2 Features.............................................................................................................................................................. 3354
30.1.3 Block Diagram..................................................................................................................................................... 3355

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30.2 Functional Description................................................................................................................................................3357

30.2.1 Configuring Device Pins...................................................................................................................................... 3357
30.2.2 Address/Data Bus Bridge.................................................................................................................................... 3358
30.3 Operating Modes........................................................................................................................................................3359
30.3.1 Initialization..........................................................................................................................................................3359
30.3.2 CAN Message Transfer (Normal Operation)....................................................................................................... 3360
30.3.3 Test Modes.......................................................................................................................................................... 3361
30.4 Multiple Clock Source................................................................................................................................................ 3365
30.5 Interrupt Functionality.................................................................................................................................................3366
30.5.1 Message Object Interrupts.................................................................................................................................. 3366
30.5.2 Status Change Interrupts.....................................................................................................................................3366
30.5.3 Error Interrupts.................................................................................................................................................... 3366
30.5.4 Peripheral Interrupt Expansion (PIE) Module Nomenclature for DCAN Interrupts.............................................. 3366
30.5.5 Interrupt Topologies............................................................................................................................................. 3367
30.6 DMA Functionality...................................................................................................................................................... 3368
30.7 Parity Check Mechanism........................................................................................................................................... 3368
30.7.1 Behavior on Parity Error...................................................................................................................................... 3368
30.8 Debug Mode...............................................................................................................................................................3369
30.9 Module Initialization....................................................................................................................................................3369
30.10 Configuration of Message Objects........................................................................................................................... 3370
30.10.1 Configuration of a Transmit Object for Data Frames......................................................................................... 3370
30.10.2 Configuration of a Transmit Object for Remote Frames.................................................................................... 3370
30.10.3 Configuration of a Single Receive Object for Data Frames...............................................................................3370
30.10.4 Configuration of a Single Receive Object for Remote Frames..........................................................................3371
30.10.5 Configuration of a FIFO Buffer...........................................................................................................................3371
30.11 Message Handling....................................................................................................................................................3371
30.11.1 Message Handler Overview...............................................................................................................................3372
30.11.2 Receive/Transmit Priority...................................................................................................................................3372
30.11.3 Transmission of Messages in Event Driven CAN Communication.................................................................... 3372
30.11.4 Updating a Transmit Object............................................................................................................................... 3373
30.11.5 Changing a Transmit Object.............................................................................................................................. 3373
30.11.6 Acceptance Filtering of Received Messages..................................................................................................... 3374
30.11.7 Reception of Data Frames................................................................................................................................. 3374
30.11.8 Reception of Remote Frames............................................................................................................................ 3374
30.11.9 Reading Received Messages............................................................................................................................ 3374
30.11.10 Requesting New Data for a Receive Object.................................................................................................... 3375
30.11.11 Storing Received Messages in FIFO Buffers................................................................................................... 3375
30.11.12 Reading from a FIFO Buffer.............................................................................................................................3375
30.12 CAN Bit Timing.........................................................................................................................................................3377
30.12.1 Bit Time and Bit Rate.........................................................................................................................................3377
30.12.2 Configuration of the CAN Bit Timing..................................................................................................................3382
30.13 Message Interface Register Sets............................................................................................................................. 3386
30.13.1 Message Interface Register Sets 1 and 2 (IF1 and IF2)....................................................................................3386
30.13.2 Message Interface Register Set 3 (IF3).............................................................................................................3387
30.14 Message RAM..........................................................................................................................................................3388
30.14.1 Structure of Message Objects........................................................................................................................... 3388
30.14.2 Addressing Message Objects in RAM............................................................................................................... 3391
30.14.3 Message RAM Representation in Debug Mode................................................................................................ 3392
30.15 Software................................................................................................................................................................... 3393
30.15.1 CAN Examples.................................................................................................................................................. 3393
30.16 CAN Registers......................................................................................................................................................... 3398
30.16.1 CAN Base Address Table (C28)........................................................................................................................ 3398
30.16.2 CM CAN Base Address Table (CM).................................................................................................................. 3398
30.16.3 CAN_REGS Registers.......................................................................................................................................3399
30.16.4 CAN Registers to Driverlib Functions................................................................................................................ 3455
31 EtherCAT® Slave Controller (ESC)................................................................................................................................ 3459
31.1 Introduction................................................................................................................................................................ 3460
31.1.1 ECAT Related Collateral......................................................................................................................................3460
31.1.2 ESC Features...................................................................................................................................................... 3461
31.1.3 ESC Subsystem Integrated Features.................................................................................................................. 3461
31.1.4 F2838x ESC versus Beckhoff ET1100................................................................................................................ 3462

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31.1.5 EtherCAT IP Block Diagram................................................................................................................................ 3462

31.1.6 ESC Functional Blocks........................................................................................................................................ 3463
31.1.7 EtherCAT Physical Layer.....................................................................................................................................3466
31.1.8 EtherCAT Protocol............................................................................................................................................... 3469
31.1.9 EtherCAT State Machine (ESM).......................................................................................................................... 3469
31.1.10 More Information on EtherCAT.......................................................................................................................... 3470
31.1.11 Beckhoff® Automation EtherCAT IP Errata........................................................................................................ 3470
31.2 ESC and ESCSS Description.....................................................................................................................................3470
31.2.1 ESC RAM Parity and Memory Address Maps..................................................................................................... 3472
31.2.2 Local Host Communication..................................................................................................................................3473
31.2.3 Debug Emulation Mode Operation...................................................................................................................... 3474
31.2.4 ESC SubSystem..................................................................................................................................................3474
31.2.5 Interrupts and Interrupt Mapping......................................................................................................................... 3476
31.2.6 Power, Clocks, and Resets..................................................................................................................................3476
31.2.7 LED Controls....................................................................................................................................................... 3478
31.2.8 Slave Node Configuration and EEPROM............................................................................................................ 3480
31.2.9 General-Purpose Inputs and Outputs..................................................................................................................3480
31.2.10 Distributed Clocks – Sync and Latch.................................................................................................................3482
31.3 Software Initialization Sequence and Allocating Ownership...................................................................................... 3491
31.4 ESC Configuration Constants.................................................................................................................................... 3492
31.5 EtherCAT IP Registers............................................................................................................................................... 3493
31.5.1 ECAT Base Address Table (C28)........................................................................................................................ 3493
31.5.2 ESCSS_REGS Registers.................................................................................................................................... 3494
31.5.3 ESCSS_CONFIG_REGS Registers.................................................................................................................... 3520
31.5.4 ESC_SS Registers to Driverlib Functions........................................................................................................... 3532
32 Fast Serial Interface (FSI)...............................................................................................................................................3537
32.1 Introduction................................................................................................................................................................ 3538
32.1.1 FSI Related Collateral......................................................................................................................................... 3538
32.1.2 FSI Features........................................................................................................................................................3538
32.2 System-level Integration.............................................................................................................................................3539
32.2.1 CPU Interface...................................................................................................................................................... 3539
32.2.2 Signal Description................................................................................................................................................3541
32.2.3 FSI Interrupts.......................................................................................................................................................3542
32.2.4 CLA Task Triggering............................................................................................................................................ 3544
32.2.5 DMA Interface......................................................................................................................................................3544
32.2.6 External Frame Trigger Mux................................................................................................................................ 3544
32.3 FSI Functional Description......................................................................................................................................... 3546
32.3.1 Introduction to Operation .................................................................................................................................... 3546
32.3.2 FSI Transmitter Module....................................................................................................................................... 3547
32.3.3 FSI Receiver Module........................................................................................................................................... 3553
32.3.4 Frame Format......................................................................................................................................................3559
32.3.5 Flush Sequence...................................................................................................................................................3563
32.3.6 Internal Loopback................................................................................................................................................ 3563
32.3.7 CRC Generation.................................................................................................................................................. 3564
32.3.8 ECC Module........................................................................................................................................................ 3565
32.3.9 Tag Matching....................................................................................................................................................... 3566
32.3.10 TDM Configurations...........................................................................................................................................3566
32.3.11 FSI Trigger Generation...................................................................................................................................... 3569
32.3.12 FSI-SPI Compatibility Mode.............................................................................................................................. 3571
32.4 FSI Programing Guide............................................................................................................................................... 3575
32.4.1 Establishing the Communication Link..................................................................................................................3575
32.4.2 Register Protection.............................................................................................................................................. 3577
32.4.3 Emulation Mode...................................................................................................................................................3577
32.5 Software..................................................................................................................................................................... 3578
32.5.1 FSI Examples...................................................................................................................................................... 3578
32.6 FSI Registers............................................................................................................................................................. 3588
32.6.1 FSI Base Address Table (C28)............................................................................................................................ 3588
32.6.2 FSI_TX_REGS Registers.................................................................................................................................... 3589
32.6.3 FSI_RX_REGS Registers....................................................................................................................................3615
32.6.4 FSI Registers to Driverlib Functions.................................................................................................................... 3655
33 Inter-Integrated Circuit Module (I2C).............................................................................................................................3661

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33.1 Introduction................................................................................................................................................................ 3662

33.1.1 I2C Related Collateral......................................................................................................................................... 3662
33.1.2 Features.............................................................................................................................................................. 3663
33.1.3 Features Not Supported...................................................................................................................................... 3663
33.1.4 Functional Overview............................................................................................................................................ 3664
33.1.5 Clock Generation.................................................................................................................................................3665
33.1.6 I2C Clock Divider Registers (I2CCLKL and I2CCLKH)....................................................................................... 3666
33.2 Configuring Device Pins.............................................................................................................................................3667
33.3 I2C Module Operational Details................................................................................................................................. 3667
33.3.1 Input and Output Voltage Levels......................................................................................................................... 3667
33.3.2 Data Validity.........................................................................................................................................................3667
33.3.3 Operating Modes................................................................................................................................................. 3667
33.3.4 I2C Module START and STOP Conditions.......................................................................................................... 3671
33.3.5 Non-repeat Mode versus Repeat Mode.............................................................................................................. 3672
33.3.6 Serial Data Formats.............................................................................................................................................3672
33.3.7 Clock Synchronization......................................................................................................................................... 3675
33.3.8 Arbitration............................................................................................................................................................ 3676
33.3.9 Digital Loopback Mode........................................................................................................................................ 3677
33.3.10 NACK Bit Generation.........................................................................................................................................3678
33.4 Interrupt Requests Generated by the I2C Module..................................................................................................... 3679
33.4.1 Basic I2C Interrupt Requests...............................................................................................................................3679
33.4.2 I2C FIFO Interrupts..............................................................................................................................................3682
33.5 Resetting or Disabling the I2C Module.......................................................................................................................3682
33.6 Software..................................................................................................................................................................... 3683
33.6.1 I2C Examples...................................................................................................................................................... 3683
33.7 I2C Registers............................................................................................................................................................. 3685
33.7.1 I2C Base Address Table (C28)............................................................................................................................ 3685
33.7.2 I2C_REGS Registers...........................................................................................................................................3686
33.7.3 I2C Registers to Driverlib Functions.................................................................................................................... 3709
34 Multichannel Buffered Serial Port (McBSP)..................................................................................................................3711
34.1 Introduction................................................................................................................................................................ 3712
34.1.1 MCBSP Related Collateral.................................................................................................................................. 3712
34.1.2 Features of the McBSPs......................................................................................................................................3712
34.1.3 McBSP Pins/Signals............................................................................................................................................3713
34.2 Configuring Device Pins.............................................................................................................................................3713
34.3 McBSP Operation...................................................................................................................................................... 3714
34.3.1 Data Transfer Process of McBSPs...................................................................................................................... 3714
34.3.2 Companding (Compressing and Expanding) Data.............................................................................................. 3715
34.3.3 Clocking and Framing Data................................................................................................................................. 3717
34.3.4 Frame Phases..................................................................................................................................................... 3719
34.3.5 McBSP Reception............................................................................................................................................... 3722
34.3.6 McBSP Transmission.......................................................................................................................................... 3723
34.3.7 Interrupts and DMA Events Generated by a McBSP...........................................................................................3724
34.4 McBSP Sample Rate Generator................................................................................................................................ 3724
34.4.1 Block Diagram..................................................................................................................................................... 3725
34.4.2 Frame Synchronization Generation in the Sample Rate Generator.................................................................... 3728
34.4.3 Synchronizing Sample Rate Generator Outputs to an External Clock................................................................ 3728
34.4.4 Reset and Initialization Procedure for the Sample Rate Generator.....................................................................3730
34.5 McBSP Exception/Error Conditions........................................................................................................................... 3731
34.5.1 Types of Errors.................................................................................................................................................... 3731
34.5.2 Overrun in the Receiver.......................................................................................................................................3732
34.5.3 Unexpected Receive Frame-Synchronization Pulse........................................................................................... 3733
34.5.4 Overwrite in the Transmitter................................................................................................................................ 3735
34.5.5 Underflow in the Transmitter................................................................................................................................3736
34.5.6 Unexpected Transmit Frame-Synchronization Pulse.......................................................................................... 3737
34.6 Multichannel Selection Modes................................................................................................................................... 3740
34.6.1 Channels, Blocks, and Partitions.........................................................................................................................3740
34.6.2 Multichannel Selection.........................................................................................................................................3741
34.6.3 Configuring a Frame for Multichannel Selection..................................................................................................3741
34.6.4 Using Two Partitions............................................................................................................................................3741
34.6.5 Using Eight Partitions.......................................................................................................................................... 3743

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34.6.6 Receive Multichannel Selection Mode.................................................................................................................3744

34.6.7 Transmit Multichannel Selection Modes.............................................................................................................. 3745
34.6.8 Using Interrupts Between Block Transfers.......................................................................................................... 3746
34.7 SPI Operation Using the Clock Stop Mode................................................................................................................ 3747
34.7.1 SPI Protocol.........................................................................................................................................................3747
34.7.2 Clock Stop Mode................................................................................................................................................. 3748
34.7.3 Enable and Configure the Clock Stop Mode....................................................................................................... 3748
34.7.4 Clock Stop Mode Timing Diagrams..................................................................................................................... 3749
34.7.5 Procedure for Configuring a McBSP for SPI Operation.......................................................................................3751
34.7.6 McBSP as the SPI Master .................................................................................................................................. 3751
34.7.7 McBSP as an SPI Slave ..................................................................................................................................... 3753
34.8 Receiver Configuration...............................................................................................................................................3754
34.8.1 Programming the McBSP Registers for the Desired Receiver Operation........................................................... 3754
34.8.2 Resetting and Enabling the Receiver.................................................................................................................. 3755
34.8.3 Set the Receiver Pins to Operate as McBSP Pins.............................................................................................. 3755
34.8.4 Digital Loopback Mode........................................................................................................................................ 3756
34.8.5 Clock Stop Mode................................................................................................................................................. 3756
34.8.6 Receive Multichannel Selection Mode.................................................................................................................3757
34.8.7 Receive Frame Phases....................................................................................................................................... 3757
34.8.8 Receive Word Lengths........................................................................................................................................ 3758
34.8.9 Receive Frame Length........................................................................................................................................ 3759
34.8.10 Receive Frame-Synchronization Ignore Function............................................................................................. 3760
34.8.11 Receive Companding Mode...............................................................................................................................3761
34.8.12 Receive Data Delay...........................................................................................................................................3763
34.8.13 Receive Sign-Extension and Justification Mode................................................................................................3765
34.8.14 Receive Interrupt Mode..................................................................................................................................... 3766
34.8.15 Receive Frame-Synchronization Mode............................................................................................................. 3766
34.8.16 Receive Frame-Synchronization Polarity.......................................................................................................... 3768
34.8.17 Receive Clock Mode..........................................................................................................................................3771
34.8.18 Receive Clock Polarity.......................................................................................................................................3772
34.8.19 SRG Clock Divide-Down Value..........................................................................................................................3774
34.8.20 SRG Clock Synchronization Mode.................................................................................................................... 3774
34.8.21 SRG Clock Mode (Choose an Input Clock)....................................................................................................... 3775
34.8.22 SRG Input Clock Polarity...................................................................................................................................3775
34.9 Transmitter Configuration...........................................................................................................................................3776
34.9.1 Programming the McBSP Registers for the Desired Transmitter Operation....................................................... 3776
34.9.2 Resetting and Enabling the Transmitter.............................................................................................................. 3777
34.9.3 Set the Transmitter Pins to Operate as McBSP Pins.......................................................................................... 3777
34.9.4 Digital Loopback Mode........................................................................................................................................ 3778
34.9.5 Clock Stop Mode................................................................................................................................................. 3778
34.9.6 Transmit Multichannel Selection Mode................................................................................................................3779
34.9.7 XCERs Used in the Transmit Multichannel Selection Mode................................................................................3780
34.9.8 Transmit Frame Phases...................................................................................................................................... 3782
34.9.9 Transmit Word Lengths....................................................................................................................................... 3782
34.9.10 Transmit Frame Length..................................................................................................................................... 3783
34.9.11 Enable/Disable the Transmit Frame-Synchronization Ignore Function..............................................................3784
34.9.12 Transmit Companding Mode............................................................................................................................. 3785
34.9.13 Transmit Data Delay.......................................................................................................................................... 3786
34.9.14 Transmit DXENA Mode..................................................................................................................................... 3788
34.9.15 Transmit Interrupt Mode.................................................................................................................................... 3788
34.9.16 Transmit Frame-Synchronization Mode.............................................................................................................3789
34.9.17 Transmit Frame-Synchronization Polarity..........................................................................................................3790
34.9.18 SRG Frame-Synchronization Period and Pulse Width...................................................................................... 3791
34.9.19 Transmit Clock Mode.........................................................................................................................................3792
34.9.20 Transmit Clock Polarity......................................................................................................................................3792
34.10 Emulation and Reset Considerations.......................................................................................................................3793
34.10.1 McBSP Emulation Mode....................................................................................................................................3794
34.10.2 Resetting and Initializing McBSPs.....................................................................................................................3794
34.11 Data Packing Examples........................................................................................................................................... 3796
34.11.1 Data Packing Using Frame Length and Word Length....................................................................................... 3796
34.11.2 Data Packing Using Word Length and the Frame-Synchronization Ignore Function.........................................3798

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34.12 Interrupt Generation................................................................................................................................................. 3799

34.12.1 McBSP Receive Interrupt Generation............................................................................................................... 3799
34.12.2 McBSP Transmit Interrupt Generation...............................................................................................................3800
34.12.3 Error Flags.........................................................................................................................................................3800
34.13 McBSP Modes......................................................................................................................................................... 3801
34.14 Special Case: External Device is the Transmit Frame Master ................................................................................ 3801
34.15 Software................................................................................................................................................................... 3803
34.15.1 MCBSP Examples............................................................................................................................................. 3803
34.16 McBSP Registers..................................................................................................................................................... 3806
34.16.1 MCBSP Base Address Table (C28)...................................................................................................................3806
34.16.2 McBSP_REGS Registers.................................................................................................................................. 3807
34.16.3 MCBSP Registers to Driverlib Functions...........................................................................................................3851
35 Power Management Bus Module (PMBus)................................................................................................................... 3855
35.1 Introduction................................................................................................................................................................ 3856
35.1.1 PMBUS Related Collateral.................................................................................................................................. 3856
35.1.2 Features.............................................................................................................................................................. 3856
35.1.3 Block Diagram..................................................................................................................................................... 3857
35.2 Configuring Device Pins.............................................................................................................................................3857
35.3 Slave Mode Operation............................................................................................................................................... 3858
35.3.1 Configuration....................................................................................................................................................... 3858
35.3.2 Message Handling...............................................................................................................................................3858
35.4 Master Mode Operation............................................................................................................................................. 3868
35.4.1 Configuration....................................................................................................................................................... 3868
35.4.2 Message Handling...............................................................................................................................................3868
35.5 PMBus Registers....................................................................................................................................................... 3879
35.5.1 PMBUS Base Address Table (C28).....................................................................................................................3879
35.5.2 PMBUS_REGS Registers................................................................................................................................... 3880
35.5.3 PMBUS Registers to Driverlib Functions.............................................................................................................3899
36 Serial Communications Interface (SCI)........................................................................................................................ 3901
36.1 Introduction................................................................................................................................................................ 3902
36.1.1 Features.............................................................................................................................................................. 3902
36.1.2 SCI Related Collateral......................................................................................................................................... 3903
36.1.3 Block Diagram..................................................................................................................................................... 3903
36.2 Architecture................................................................................................................................................................ 3903
36.3 SCI Module Signal Summary..................................................................................................................................... 3903
36.4 Configuring Device Pins.............................................................................................................................................3905
36.5 Multiprocessor and Asynchronous Communication Modes....................................................................................... 3905
36.6 SCI Programmable Data Format................................................................................................................................3906
36.7 SCI Multiprocessor Communication...........................................................................................................................3907
36.7.1 Recognizing the Address Byte............................................................................................................................ 3907
36.7.2 Controlling the SCI TX and RX Features.............................................................................................................3907
36.7.3 Receipt Sequence............................................................................................................................................... 3907
36.8 Idle-Line Multiprocessor Mode................................................................................................................................... 3908
36.8.1 Idle-Line Mode Steps...........................................................................................................................................3908
36.8.2 Block Start Signal................................................................................................................................................ 3909
36.8.3 Wake-Up Temporary (WUT) Flag........................................................................................................................ 3909
36.8.4 Receiver Operation..............................................................................................................................................3909
36.9 Address-Bit Multiprocessor Mode.............................................................................................................................. 3910
36.9.1 Sending an Address............................................................................................................................................ 3910
36.10 SCI Communication Format..................................................................................................................................... 3911
36.10.1 Receiver Signals in Communication Modes...................................................................................................... 3911
36.10.2 Transmitter Signals in Communication Modes.................................................................................................. 3912
36.11 SCI Port Interrupts....................................................................................................................................................3913
36.12 SCI Baud Rate Calculations.....................................................................................................................................3913
36.13 SCI Enhanced Features...........................................................................................................................................3914
36.13.1 SCI FIFO Description........................................................................................................................................ 3914
36.13.2 SCI Auto-Baud...................................................................................................................................................3916
36.13.3 Autobaud-Detect Sequence.............................................................................................................................. 3916
36.14 Software................................................................................................................................................................... 3917
36.14.1 SCI Examples....................................................................................................................................................3917
36.15 SCI Registers........................................................................................................................................................... 3919

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36.15.1 SCI Base Address Table (C28)..........................................................................................................................3919

36.15.2 SCI_REGS Registers........................................................................................................................................ 3920
36.15.3 SCI Registers to Driverlib Functions..................................................................................................................3939
37 Serial Peripheral Interface (SPI).................................................................................................................................... 3943
37.1 Introduction................................................................................................................................................................ 3944
37.1.1 Features.............................................................................................................................................................. 3944
37.1.2 SPI Related Collateral......................................................................................................................................... 3944
37.1.3 Block Diagram..................................................................................................................................................... 3945
37.2 System-Level Integration........................................................................................................................................... 3946
37.2.1 SPI Module Signals............................................................................................................................................. 3946
37.2.2 Configuring Device Pins...................................................................................................................................... 3947
37.2.3 SPI Interrupts.......................................................................................................................................................3947
37.2.4 DMA Support....................................................................................................................................................... 3949
37.3 SPI Operation.............................................................................................................................................................3950
37.3.1 Introduction to Operation..................................................................................................................................... 3950
37.3.2 Master Mode........................................................................................................................................................3951
37.3.3 Slave Mode..........................................................................................................................................................3952
37.3.4 Data Format.........................................................................................................................................................3954
37.3.5 Baud Rate Selection............................................................................................................................................3955
37.3.6 SPI Clocking Schemes........................................................................................................................................ 3956
37.3.7 SPI FIFO Description...........................................................................................................................................3957
37.3.8 SPI DMA Transfers..............................................................................................................................................3958
37.3.9 SPI High-Speed Mode.........................................................................................................................................3959
37.3.10 SPI 3-Wire Mode Description............................................................................................................................ 3959
37.4 Programming Procedure............................................................................................................................................ 3961
37.4.1 Initialization Upon Reset......................................................................................................................................3961
37.4.2 Configuring the SPI............................................................................................................................................. 3961
37.4.3 Configuring the SPI for High-Speed Mode.......................................................................................................... 3962
37.4.4 Data Transfer Example........................................................................................................................................3963
37.4.5 SPI 3-Wire Mode Code Examples.......................................................................................................................3964
37.4.6 SPI STEINV Bit in Digital Audio Transfers...........................................................................................................3966
37.5 Software..................................................................................................................................................................... 3967
37.5.1 SPI Examples...................................................................................................................................................... 3967
37.6 SPI Registers............................................................................................................................................................. 3969
37.6.1 SPI Base Address Table (C28)............................................................................................................................3969
37.6.2 SPI_REGS Registers.......................................................................................................................................... 3970
37.6.3 SPI Registers to Driverlib Functions....................................................................................................................3988
38 Universal Serial Bus (USB) Controller..........................................................................................................................3991
38.1 Introduction................................................................................................................................................................ 3992
38.1.1 Features.............................................................................................................................................................. 3992
38.1.2 USB Related Collateral........................................................................................................................................3992
38.1.3 Block Diagram..................................................................................................................................................... 3993
38.2 Functional Description................................................................................................................................................3995
38.2.1 Operation as a Device......................................................................................................................................... 3995
38.2.2 Operation as a Host.............................................................................................................................................3999
38.2.3 DMA Operation....................................................................................................................................................4003
38.2.4 Address/Data Bus Bridge.................................................................................................................................... 4003
38.3 Initialization and Configuration................................................................................................................................... 4005
38.3.1 Pin Configuration................................................................................................................................................. 4005
38.3.2 Endpoint Configuration........................................................................................................................................ 4006
38.4 USB Global Interrupts................................................................................................................................................ 4006
38.5 Software..................................................................................................................................................................... 4007
38.5.1 USB Examples.................................................................................................................................................... 4007
38.6 USB Registers............................................................................................................................................................4012
38.6.1 USB Base Address Table (C28).......................................................................................................................... 4012
38.6.2 USB_REGS Registers.........................................................................................................................................4013
38.6.3 USB Registers to Driverlib Functions.................................................................................................................. 4157
39 ► CONNECTIVITY MANAGER (CM).............................................................................................................................. 4175
39.1 Technical Reference Manual Overview......................................................................................................................4175
40 Connectivity Manager Subsystem................................................................................................................................ 4177
40.1 Connectivity Manager Overview................................................................................................................................ 4178

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40.2 Connectivity Manager Functional Block Diagram...................................................................................................... 4179

40.3 Arm® Cortex®-M4 Processor Core Overview.............................................................................................................4180
41 Connectivity Manager System Control and Interrupts................................................................................................4181
41.1 Introduction................................................................................................................................................................ 4182
41.2 Reset..........................................................................................................................................................................4182
41.2.1 CPU1 SYSRS .....................................................................................................................................................4182
41.2.2 System Reset Request (CMSYSRESETREQ)....................................................................................................4182
41.2.3 CM NMI Watchdog Reset (CMNMIWDRSTn)..................................................................................................... 4182
41.2.4 CM Secure Code Copy Reset (CMSCCRESETn)...............................................................................................4182
41.3 CM Clocking...............................................................................................................................................................4183
41.3.1 CM Clock Sources...............................................................................................................................................4183
41.3.2 CM Derived Clocks..............................................................................................................................................4183
41.3.3 CM Device Clock Domains..................................................................................................................................4183
41.3.4 CM Clock Connectivity........................................................................................................................................ 4185
41.4 SysTick.......................................................................................................................................................................4185
41.5 Watchdog Timer......................................................................................................................................................... 4186
41.6 Exceptions and NMI................................................................................................................................................... 4186
41.6.1 CM Subsystem Nested Vectored Interrupt Controller..........................................................................................4186
41.6.2 CM Subsystem Exceptions Handling.................................................................................................................. 4187
41.6.3 CM Subsystem Non-Maskable Interrupt (CMNMI) Module................................................................................. 4189
41.6.4 CM Interrupts/NMI to CPU1/CPU2...................................................................................................................... 4191
41.7 Nested Vectored Interrupt Controller (NVIC)..............................................................................................................4191
41.7.1 Level-Sensitive and Pulse Interrupts................................................................................................................... 4194
41.7.2 Hardware and Software Control of Interrupts...................................................................................................... 4194
41.7.3 NVIC Registers Access....................................................................................................................................... 4194
41.8 32-Bit CM CPU Timers 0/1/2......................................................................................................................................4195
41.9 Memory Controller Module.........................................................................................................................................4196
41.9.1 Functional Description......................................................................................................................................... 4196
41.10 Memory Protection Unit (MPU)................................................................................................................................ 4202
41.10.1 Functional Description....................................................................................................................................... 4203
41.10.2 Overlapping Regions......................................................................................................................................... 4203
41.10.3 Sub-Regions......................................................................................................................................................4204
41.10.4 Programmers Model.......................................................................................................................................... 4204
41.11 Debug and Trace......................................................................................................................................................4205
41.11.1 Trace Port Interface Unit....................................................................................................................................4205
41.12 CM-SysCtrl Registers...............................................................................................................................................4206
41.12.1 CM System Control Base Addresses................................................................................................................ 4206
41.12.2 CM_MEMCFG_REGS Registers.......................................................................................................................4207
41.12.3 CM_MEMORYDIAGERROR_REGS Registers.................................................................................................4228
41.12.4 CM_MEMORYERROR_REGS Registers..........................................................................................................4233
41.12.5 CMSYSCTL_REGS Registers...........................................................................................................................4261
41.12.6 CM_CPUTIMER_REGS Registers....................................................................................................................4286
41.12.7 MPU_REGS Registers...................................................................................................................................... 4292
41.12.8 CM_NMI_INTRUPT_REGS Registers.............................................................................................................. 4324
41.12.9 NVIC Registers..................................................................................................................................................4336
41.12.10 SCB Registers................................................................................................................................................. 4406
41.12.11 CSFR Registers............................................................................................................................................... 4433
41.12.12 SYSTICK Registers......................................................................................................................................... 4440
41.12.13 MPU Registers................................................................................................................................................ 4445
41.12.14 CM_WD_REGS Registers...............................................................................................................................4469
42 Advanced Encryption Standard (AES) Accelerator.....................................................................................................4477
42.1 Introduction................................................................................................................................................................ 4478
42.1.1 AES Block Diagram............................................................................................................................................. 4478
42.1.2 AES Algorithm..................................................................................................................................................... 4481
42.2 AES Operating Modes............................................................................................................................................... 4482
42.2.1 GCM Operation................................................................................................................................................... 4482
42.2.2 CCM Operation....................................................................................................................................................4483
42.2.3 XTS Operation.....................................................................................................................................................4484
42.2.4 ECB Feedback Mode.......................................................................................................................................... 4485
42.2.5 CBC Feedback Mode.......................................................................................................................................... 4486
42.2.6 CTR and ICM Feedback Modes.......................................................................................................................... 4487

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42.2.7 CFB Mode........................................................................................................................................................... 4488

42.2.8 F8 Mode.............................................................................................................................................................. 4489
42.2.9 F9 Operation........................................................................................................................................................4490
42.2.10 CBC-MAC Operation......................................................................................................................................... 4491
42.3 Extended and Combined Modes of Operations......................................................................................................... 4492
42.3.1 GCM Protocol Operation..................................................................................................................................... 4492
42.3.2 CCM Protocol Operation..................................................................................................................................... 4492
42.3.3 Hardware Requests.............................................................................................................................................4492
42.4 AES Module Programming Guide.............................................................................................................................. 4493
42.4.1 AES Low-Level Programming Models.................................................................................................................4493
42.5 Software..................................................................................................................................................................... 4498
42.5.1 AES Examples.....................................................................................................................................................4498
42.6 AES Registers............................................................................................................................................................4499
42.6.1 AES Base Addresses.......................................................................................................................................... 4499
42.6.2 AES_SS_REGS Registers.................................................................................................................................. 4500
42.6.3 AES_REGS Registers......................................................................................................................................... 4504
43 Ethernet Media Access Controller (EMAC).................................................................................................................. 4549
43.1 Introduction................................................................................................................................................................ 4550
43.1.1 Standard Compliance.......................................................................................................................................... 4550
43.1.2 MAC Features..................................................................................................................................................... 4550
43.2 System Level Integration............................................................................................................................................4552
43.2.1 Ethernet Signal Connection and Description.......................................................................................................4552
43.2.2 Configuring Device Pins...................................................................................................................................... 4557
43.2.3 MAC Interface Selection......................................................................................................................................4557
43.2.4 Clocks for Ethernet Module................................................................................................................................. 4557
43.2.5 RMII Mode Clocking............................................................................................................................................ 4558
43.2.6 RevMII Mode Clocking........................................................................................................................................ 4558
43.2.7 Configuring Trigger Sources for Time Stamping..................................................................................................4559
43.2.8 Ethernet Interrupts...............................................................................................................................................4560
43.3 Features..................................................................................................................................................................... 4562
43.3.1 Multiple Channels and Queues Support..............................................................................................................4562
43.3.2 IEEE 1588 Timestamp Support........................................................................................................................... 4566
43.3.3 Packet Filtering....................................................................................................................................................4580
43.3.4 VLAN Support......................................................................................................................................................4588
43.3.5 TCP/IP Offloading Features.................................................................................................................................4590
43.3.6 Loopback Mode................................................................................................................................................... 4606
43.3.7 Reverse Media Independent Interface (RevMII)..................................................................................................4607
43.4 Descriptors................................................................................................................................................................. 4613
43.4.1 Descriptor Structure.............................................................................................................................................4613
43.4.2 Transmit Descriptor............................................................................................................................................. 4615
43.4.3 Receive Descriptor.............................................................................................................................................. 4627
43.5 Programming..............................................................................................................................................................4639
43.5.1 Initializing DMA....................................................................................................................................................4639
43.5.2 Initializing MTL Registers.................................................................................................................................... 4640
43.5.3 Initializing MAC....................................................................................................................................................4640
43.5.4 Performing Normal Receive and Transmit Operation..........................................................................................4641
43.5.5 Stopping and Starting Transmission....................................................................................................................4641
43.5.6 Programming Guidelines for Multi-Channel Multi-Queuing................................................................................. 4641
43.6 Software..................................................................................................................................................................... 4649
43.6.1 ETHERNET Examples........................................................................................................................................ 4649
43.7 Ethernet Registers..................................................................................................................................................... 4654
43.7.1 Ethernet Base Addresses....................................................................................................................................4654
43.7.2 ETHERNETSS_REGS Registers........................................................................................................................ 4655
43.7.3 EMAC_REGS Registers......................................................................................................................................4671
44 Generic Cyclic Redundancy Check (GCRC)................................................................................................................ 5075
44.1 Generic CRC Overview..............................................................................................................................................5076
44.1.1 GCRC Features...................................................................................................................................................5076
44.1.2 GCRC Block Diagram..........................................................................................................................................5076
44.2 GCRC Functional Description.................................................................................................................................... 5077
44.2.1 GCRC Polynomials..............................................................................................................................................5077
44.2.2 Fixed Polynomial................................................................................................................................................. 5077

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44.2.3 GCRC Data Input................................................................................................................................................ 5077

44.2.4 GCRC Execution Sequence Flow....................................................................................................................... 5078
44.2.5 GCRC Transformations....................................................................................................................................... 5079
44.3 Software..................................................................................................................................................................... 5081
44.3.1 GCRC Examples................................................................................................................................................. 5081
44.4 GCRC Registers........................................................................................................................................................ 5081
44.4.1 GCRC Base Addresses.......................................................................................................................................5081
44.4.2 GCRC_REGS Registers......................................................................................................................................5082
45 Modular Controller Area Network (MCAN)................................................................................................................... 5089
45.1 MCAN Introduction.....................................................................................................................................................5090
45.1.1 MCAN Related Collateral.................................................................................................................................... 5090
45.1.2 MCAN Features...................................................................................................................................................5091
45.2 MCAN Environment................................................................................................................................................... 5091
45.3 CAN Network Basics..................................................................................................................................................5092
45.4 MCAN Integration.......................................................................................................................................................5093
45.5 MCAN Functional Description.................................................................................................................................... 5095
45.5.1 Module Clocking Requirements...........................................................................................................................5096
45.5.2 Interrupt Requests............................................................................................................................................... 5096
45.5.3 Operating Modes................................................................................................................................................. 5097
45.5.4 Transmitter Delay Compensation........................................................................................................................ 5100
45.5.5 Restricted Operation Mode..................................................................................................................................5102
45.5.6 Bus Monitoring Mode...........................................................................................................................................5102
45.5.7 Disabled Automatic Retransmission (DAR) Mode...............................................................................................5103
45.5.8 Clock Stop Mode................................................................................................................................................. 5103
45.5.9 Test Modes.......................................................................................................................................................... 5106
45.5.10 Timestamp Generation...................................................................................................................................... 5107
45.5.11 Timeout Counter................................................................................................................................................ 5109
45.5.12 Safety................................................................................................................................................................ 5109
45.5.13 Rx Handling........................................................................................................................................................5111
45.5.14 Tx Handling........................................................................................................................................................5117
45.5.15 FIFO Acknowledge Handling.............................................................................................................................5121
45.5.16 Message RAM................................................................................................................................................... 5121
45.6 Software..................................................................................................................................................................... 5132
45.6.1 MCAN Examples................................................................................................................................................. 5132
45.7 MCAN Registers........................................................................................................................................................ 5135
45.7.1 MCAN Base Address Table (C28)....................................................................................................................... 5135
45.7.2 CM MCAN Base Address Table (CM)................................................................................................................. 5135
45.7.3 MCANSS_REGS Registers.................................................................................................................................5136
45.7.4 MCAN_REGS Registers......................................................................................................................................5149
45.7.5 MCAN_ERROR_REGS Registers.......................................................................................................................5226
46 Connectivity Manager Inter-Integrated Circuit (I2C) Module...................................................................................... 5253
46.1 Introduction................................................................................................................................................................ 5254
46.1.1 Features.............................................................................................................................................................. 5254
46.1.2 Block Diagram..................................................................................................................................................... 5255
46.2 Functional Description................................................................................................................................................5255
46.2.1 I2C Bus Functional Overview.............................................................................................................................. 5256
46.2.2 Available Speed Modes.......................................................................................................................................5261
46.2.3 Interrupts............................................................................................................................................................. 5263
46.2.4 Loopback Operation............................................................................................................................................ 5263
46.2.5 FIFO and µDMA Operation..................................................................................................................................5264
46.2.6 Command Sequence Flow Charts.......................................................................................................................5266
46.3 Initialization and Configuration................................................................................................................................... 5273
46.3.1 Configure the I2C Module to Transmit a Single Byte as a Master ......................................................................5273
46.3.2 Configure the I2C Master to High-Speed Mode.................................................................................................. 5274
46.4 CM I2C Registers.......................................................................................................................................................5274
46.4.1 CM I2C Base Addresses..................................................................................................................................... 5274
46.4.2 CM_I2C_REGS Registers................................................................................................................................... 5275
46.4.3 CM_I2C_WRITE_REGS Registers..................................................................................................................... 5317
47 Synchronous Serial Interface (SSI)...............................................................................................................................5323
47.1 Introduction................................................................................................................................................................ 5324
47.1.1 Features.............................................................................................................................................................. 5324

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47.1.2 Block Diagram..................................................................................................................................................... 5324

47.2 Functional Description................................................................................................................................................5326
47.2.1 Bit Rate Generation............................................................................................................................................. 5326
47.2.2 FIFO Operation....................................................................................................................................................5326
47.2.3 SSInFSS Function............................................................................................................................................... 5327
47.2.4 Interrupts............................................................................................................................................................. 5327
47.2.5 Frame Formats.................................................................................................................................................... 5328
47.2.6 DMA Operation....................................................................................................................................................5333
47.3 Initialization and Configuration................................................................................................................................... 5334
47.4 Software..................................................................................................................................................................... 5335
47.4.1 SSI Examples...................................................................................................................................................... 5335
47.5 SSI Registers............................................................................................................................................................. 5335
47.5.1 SSI Base Addresses............................................................................................................................................5335
47.5.2 SSI_REGS Registers.......................................................................................................................................... 5336
48 Universal Asynchronous Receiver/Transmitter (UART)............................................................................................. 5369
48.1 Introduction................................................................................................................................................................ 5370
48.1.1 Features.............................................................................................................................................................. 5370
48.1.2 Block Diagram..................................................................................................................................................... 5370
48.2 Functional Description................................................................................................................................................5370
48.2.1 Transmit and Receive Logic................................................................................................................................ 5371
48.2.2 Baud-Rate Generation.........................................................................................................................................5372
48.2.3 Data Transmission...............................................................................................................................................5373
48.2.4 Serial IR (SIR)..................................................................................................................................................... 5373
48.2.5 9-Bit UART Mode.................................................................................................................................................5374
48.2.6 FIFO Operation....................................................................................................................................................5375
48.2.7 Interrupts............................................................................................................................................................. 5375
48.2.8 Loopback Operation............................................................................................................................................ 5376
48.2.9 DMA Operation....................................................................................................................................................5376
48.3 Initialization and Configuration................................................................................................................................... 5377
48.4 Software..................................................................................................................................................................... 5378
48.4.1 UART Examples.................................................................................................................................................. 5378
48.5 UART Registers......................................................................................................................................................... 5379
48.5.1 UART Base Addresses........................................................................................................................................5379
48.5.2 UART_REGS Registers.......................................................................................................................................5380
48.5.3 UART_REGS_WRITE Registers......................................................................................................................... 5420
49 Micro Direct Memory Access (µDMA)........................................................................................................................... 5423
49.1 Introduction................................................................................................................................................................ 5424
49.1.1 Features.............................................................................................................................................................. 5424
49.1.2 Block Diagram..................................................................................................................................................... 5425
49.2 Functional Description................................................................................................................................................5425
49.2.1 Channel Assignments..........................................................................................................................................5426
49.2.2 Priority................................................................................................................................................................. 5427
49.2.3 Arbitration Size.................................................................................................................................................... 5427
49.2.4 Request Types.....................................................................................................................................................5427
49.2.5 Channel Configuration.........................................................................................................................................5428
49.2.6 Transfer Modes....................................................................................................................................................5430
49.2.7 Transfer Size and Increment............................................................................................................................... 5438
49.2.8 Peripheral Interface............................................................................................................................................. 5438
49.2.9 Software Request................................................................................................................................................ 5439
49.2.10 Interrupts and Errors..........................................................................................................................................5439
49.3 Initialization and Configuration................................................................................................................................... 5439
49.3.1 Module Initialization............................................................................................................................................. 5439
49.3.2 Configuring a Memory-to-Memory Transfer.........................................................................................................5439
49.3.3 Configuring a Peripheral for Simple Transmit......................................................................................................5441
49.3.4 Configuring a Peripheral for Ping-Pong Receive.................................................................................................5443
49.3.5 Configuring Channel Assignments...................................................................................................................... 5445
49.4 Software..................................................................................................................................................................... 5446
49.4.1 UDMA Examples................................................................................................................................................. 5446
49.5 µDMA Registers......................................................................................................................................................... 5446
49.5.1 µDMA Base Addresses....................................................................................................................................... 5446
49.5.2 UDMAREGS Registers........................................................................................................................................5447

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49.5.3 UDMACHDES Registers..................................................................................................................................... 5478

50 Revision History............................................................................................................................................................. 5484

List of Figures
Figure 1-1. F2838x Block Diagram.......................................................................................................................................... 134
Figure 3-1. Device Interrupt Architecture.................................................................................................................................146
Figure 3-2. Interrupt Propagation Path.................................................................................................................................... 147
Figure 3-3. System Error and CM Status Interrupt Sources.................................................................................................... 152
Figure 3-4. ERRORSTS Pin Diagram......................................................................................................................................163
Figure 3-5. Clocking System....................................................................................................................................................164
Figure 3-6. Single-ended 3.3V External Clock.........................................................................................................................165
Figure 3-7. External Crystal..................................................................................................................................................... 166
Figure 3-8. External Resonator................................................................................................................................................166
Figure 3-9. AUXCLKIN............................................................................................................................................................ 167
Figure 3-10. PLL/AUXPLL....................................................................................................................................................... 171
Figure 3-11. Missing Clock Detection Logic.............................................................................................................................175
Figure 3-12. Clock Configuration Semaphore (CLKSEM) State Transitions........................................................................... 176
Figure 3-13. CPU-Timers.........................................................................................................................................................177
Figure 3-14. CPU-Timer Interrupts Signals and Output Signal................................................................................................177
Figure 3-15. CPU Watchdog Timer Module............................................................................................................................. 178
Figure 3-16. Memory Architecture........................................................................................................................................... 182
Figure 3-17. Arbitration Scheme on Global Shared Memories................................................................................................ 185
Figure 3-18. Arbitration Scheme on Local Shared Memories..................................................................................................185
Figure 3-19. ROM Parity Checking Logic................................................................................................................................ 191
Figure 3-20. NMAVFLG Register............................................................................................................................................. 203
Figure 3-21. NMAVSET Register............................................................................................................................................. 205
Figure 3-22. NMAVCLR Register.............................................................................................................................................207
Figure 3-23. NMAVINTEN Register......................................................................................................................................... 209
Figure 3-24. NMCPURDAVADDR Register............................................................................................................................. 210
Figure 3-25. NMCPUWRAVADDR Register.............................................................................................................................211
Figure 3-26. NMCPUFAVADDR Register................................................................................................................................ 212
Figure 3-27. NMDMAWRAVADDR Register............................................................................................................................ 213
Figure 3-28. NMCLA1RDAVADDR Register............................................................................................................................214
Figure 3-29. NMCLA1WRAVADDR Register........................................................................................................................... 215
Figure 3-30. NMCLA1FAVADDR Register............................................................................................................................... 216
Figure 3-31. NMDMARDAVADDR Register.............................................................................................................................217
Figure 3-32. MAVFLG Register................................................................................................................................................218
Figure 3-33. MAVSET Register................................................................................................................................................219
Figure 3-34. MAVCLR Register............................................................................................................................................... 220
Figure 3-35. MAVINTEN Register............................................................................................................................................221
Figure 3-36. MCPUFAVADDR Register................................................................................................................................... 222
Figure 3-37. MCPUWRAVADDR Register............................................................................................................................... 223
Figure 3-38. MDMAWRAVADDR Register...............................................................................................................................224
Figure 3-39. CLKSEM Register............................................................................................................................................... 227
Figure 3-40. CLKCFGLOCK1 Register....................................................................................................................................228
Figure 3-41. CLKSRCCTL1 Register.......................................................................................................................................231
Figure 3-42. CLKSRCCTL2 Register.......................................................................................................................................233
Figure 3-43. CLKSRCCTL3 Register.......................................................................................................................................235
Figure 3-44. SYSPLLCTL1 Register........................................................................................................................................236
Figure 3-45. SYSPLLMULT Register....................................................................................................................................... 237
Figure 3-46. SYSPLLSTS Register......................................................................................................................................... 239
Figure 3-47. AUXPLLCTL1 Register....................................................................................................................................... 240
Figure 3-48. AUXPLLMULT Register.......................................................................................................................................241
Figure 3-49. AUXPLLSTS Register......................................................................................................................................... 243
Figure 3-50. SYSCLKDIVSEL Register................................................................................................................................... 244
Figure 3-51. AUXCLKDIVSEL Register...................................................................................................................................245
Figure 3-52. PERCLKDIVSEL Register...................................................................................................................................246
Figure 3-53. XCLKOUTDIVSEL Register................................................................................................................................ 247
Figure 3-54. CLBCLKCTL Register......................................................................................................................................... 248
Figure 3-55. LOSPCP Register............................................................................................................................................... 250
Figure 3-56. MCDCR Register.................................................................................................................................................251

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Figure 3-57. X1CNT Register.................................................................................................................................................. 252

Figure 3-58. XTALCR Register................................................................................................................................................ 253
Figure 3-59. ETHERCATCLKCTL Register............................................................................................................................. 254
Figure 3-60. CMCLKCTL Register...........................................................................................................................................255
Figure 3-61. CMRESCTL Register.......................................................................................................................................... 257
Figure 3-62. CMTOCPU1NMICTL Register.............................................................................................................................258
Figure 3-63. CMTOCPU1INTCTL Register............................................................................................................................. 259
Figure 3-64. PALLOCATE0 Register....................................................................................................................................... 260
Figure 3-65. CM_CONF_REGS_LOCK Register.................................................................................................................... 262
Figure 3-66. CPUSYSLOCK1 Register................................................................................................................................... 265
Figure 3-67. CPUSYSLOCK2 Register................................................................................................................................... 268
Figure 3-68. PIEVERRADDR Register.................................................................................................................................... 269
Figure 3-69. PCLKCR0 Register............................................................................................................................................. 270
Figure 3-70. PCLKCR1 Register............................................................................................................................................. 272
Figure 3-71. PCLKCR2 Register............................................................................................................................................. 273
Figure 3-72. PCLKCR3 Register............................................................................................................................................. 275
Figure 3-73. PCLKCR4 Register............................................................................................................................................. 277
Figure 3-74. PCLKCR6 Register............................................................................................................................................. 278
Figure 3-75. PCLKCR7 Register............................................................................................................................................. 279
Figure 3-76. PCLKCR8 Register............................................................................................................................................. 280
Figure 3-77. PCLKCR9 Register............................................................................................................................................. 281
Figure 3-78. PCLKCR10 Register........................................................................................................................................... 282
Figure 3-79. PCLKCR11 Register............................................................................................................................................283
Figure 3-80. PCLKCR13 Register........................................................................................................................................... 284
Figure 3-81. PCLKCR14 Register........................................................................................................................................... 285
Figure 3-82. PCLKCR16 Register........................................................................................................................................... 287
Figure 3-83. PCLKCR17 Register........................................................................................................................................... 288
Figure 3-84. PCLKCR18 Register........................................................................................................................................... 290
Figure 3-85. PCLKCR20 Register........................................................................................................................................... 292
Figure 3-86. PCLKCR21 Register........................................................................................................................................... 293
Figure 3-87. PCLKCR22 Register........................................................................................................................................... 294
Figure 3-88. PCLKCR23 Register........................................................................................................................................... 295
Figure 3-89. SIMRESET Register............................................................................................................................................296
Figure 3-90. LPMCR Register................................................................................................................................................. 297
Figure 3-91. GPIOLPMSEL0 Register.....................................................................................................................................298
Figure 3-92. GPIOLPMSEL1 Register.....................................................................................................................................301
Figure 3-93. TMR2CLKCTL Register...................................................................................................................................... 304
Figure 3-94. RESCCLR Register.............................................................................................................................................305
Figure 3-95. RESC Register.................................................................................................................................................... 307
Figure 3-96. MCANWAKESTATUS Register........................................................................................................................... 309
Figure 3-97. MCANWAKESTATUSCLR Register.................................................................................................................... 310
Figure 3-98. CPUID Register...................................................................................................................................................312
Figure 3-99. ADCA_AC Register............................................................................................................................................. 316
Figure 3-100. ADCB_AC Register........................................................................................................................................... 317
Figure 3-101. ADCC_AC Register...........................................................................................................................................318
Figure 3-102. ADCD_AC Register...........................................................................................................................................319
Figure 3-103. CMPSS1_AC Register...................................................................................................................................... 320
Figure 3-104. CMPSS2_AC Register...................................................................................................................................... 321
Figure 3-105. CMPSS3_AC Register...................................................................................................................................... 322
Figure 3-106. CMPSS4_AC Register...................................................................................................................................... 323
Figure 3-107. CMPSS5_AC Register...................................................................................................................................... 324
Figure 3-108. CMPSS6_AC Register...................................................................................................................................... 325
Figure 3-109. CMPSS7_AC Register...................................................................................................................................... 326
Figure 3-110. CMPSS8_AC Register.......................................................................................................................................327
Figure 3-111. DACA_AC Register............................................................................................................................................328
Figure 3-112. DACB_AC Register........................................................................................................................................... 329
Figure 3-113. DACC_AC Register........................................................................................................................................... 330
Figure 3-114. EPWM1_AC Register........................................................................................................................................ 331
Figure 3-115. EPWM2_AC Register........................................................................................................................................ 332
Figure 3-116. EPWM3_AC Register........................................................................................................................................ 333
Figure 3-117. EPWM4_AC Register........................................................................................................................................ 334

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Figure 3-118. EPWM5_AC Register........................................................................................................................................ 335

Figure 3-119. EPWM6_AC Register........................................................................................................................................ 336
Figure 3-120. EPWM7_AC Register........................................................................................................................................337
Figure 3-121. EPWM8_AC Register........................................................................................................................................338
Figure 3-122. EPWM9_AC Register........................................................................................................................................339
Figure 3-123. EPWM10_AC Register......................................................................................................................................340
Figure 3-124. EPWM11_AC Register...................................................................................................................................... 341
Figure 3-125. EPWM12_AC Register......................................................................................................................................342
Figure 3-126. EPWM13_AC Register......................................................................................................................................343
Figure 3-127. EPWM14_AC Register......................................................................................................................................344
Figure 3-128. EPWM15_AC Register......................................................................................................................................345
Figure 3-129. EPWM16_AC Register......................................................................................................................................346
Figure 3-130. EQEP1_AC Register......................................................................................................................................... 347
Figure 3-131. EQEP2_AC Register......................................................................................................................................... 348
Figure 3-132. EQEP3_AC Register......................................................................................................................................... 349
Figure 3-133. ECAP1_AC Register......................................................................................................................................... 350
Figure 3-134. ECAP2_AC Register......................................................................................................................................... 351
Figure 3-135. ECAP3_AC Register......................................................................................................................................... 352
Figure 3-136. ECAP4_AC Register......................................................................................................................................... 353
Figure 3-137. ECAP5_AC Register......................................................................................................................................... 354
Figure 3-138. ECAP6_AC Register......................................................................................................................................... 355
Figure 3-139. ECAP7_AC Register......................................................................................................................................... 356
Figure 3-140. SDFM1_AC Register.........................................................................................................................................357
Figure 3-141. SDFM2_AC Register.........................................................................................................................................358
Figure 3-142. CLB1_AC Register............................................................................................................................................ 359
Figure 3-143. CLB2_AC Register............................................................................................................................................ 360
Figure 3-144. CLB3_AC Register............................................................................................................................................ 361
Figure 3-145. CLB4_AC Register............................................................................................................................................ 362
Figure 3-146. CLB5_AC Register............................................................................................................................................ 363
Figure 3-147. CLB6_AC Register............................................................................................................................................ 364
Figure 3-148. CLB7_AC Register............................................................................................................................................ 365
Figure 3-149. CLB8_AC Register............................................................................................................................................ 366
Figure 3-150. SPIA_AC Register.............................................................................................................................................367
Figure 3-151. SPIB_AC Register.............................................................................................................................................368
Figure 3-152. SPIC_AC Register.............................................................................................................................................369
Figure 3-153. SPID_AC Register.............................................................................................................................................370
Figure 3-154. PMBUS_A_AC Register....................................................................................................................................371
Figure 3-155. CAN_A_AC Register......................................................................................................................................... 372
Figure 3-156. CAN_B_AC Register......................................................................................................................................... 373
Figure 3-157. MCBSPA_AC Register...................................................................................................................................... 374
Figure 3-158. MCBSPB_AC Register......................................................................................................................................375
Figure 3-159. USBA_AC Register........................................................................................................................................... 376
Figure 3-160. HRPWM_AC Register....................................................................................................................................... 377
Figure 3-161. ETHERCAT_AC Register.................................................................................................................................. 379
Figure 3-162. FSIATX_AC Register.........................................................................................................................................380
Figure 3-163. FSIARX_AC Register........................................................................................................................................ 381
Figure 3-164. FSIBTX_AC Register........................................................................................................................................ 382
Figure 3-165. FSIBRX_AC Register........................................................................................................................................ 383
Figure 3-166. FSICRX_AC Register........................................................................................................................................384
Figure 3-167. FSIDRX_AC Register........................................................................................................................................385
Figure 3-168. FSIERX_AC Register........................................................................................................................................ 386
Figure 3-169. FSIFRX_AC Register........................................................................................................................................ 387
Figure 3-170. FSIGRX_AC Register........................................................................................................................................388
Figure 3-171. FSIHRX_AC Register........................................................................................................................................389
Figure 3-172. MCANA_AC Register........................................................................................................................................ 390
Figure 3-173. PERIPH_AC_LOCK Register............................................................................................................................391
Figure 3-174. TIM Register......................................................................................................................................................393
Figure 3-175. PRD Register.................................................................................................................................................... 394
Figure 3-176. TCR Register.....................................................................................................................................................395
Figure 3-177. TPR Register.....................................................................................................................................................397
Figure 3-178. TPRH Register.................................................................................................................................................. 398

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Figure 3-179. DEVCFGLOCK1 Register................................................................................................................................. 401

Figure 3-180. DEVCFGLOCK2 Register................................................................................................................................. 403
Figure 3-181. PARTIDL Register............................................................................................................................................. 404
Figure 3-182. PARTIDH Register.............................................................................................................................................406
Figure 3-183. REVID Register................................................................................................................................................. 407
Figure 3-184. PERCNF1 Register........................................................................................................................................... 408
Figure 3-185. FUSEERR Register...........................................................................................................................................409
Figure 3-186. SOFTPRES0 Register.......................................................................................................................................410
Figure 3-187. SOFTPRES1 Register.......................................................................................................................................412
Figure 3-188. SOFTPRES2 Register.......................................................................................................................................413
Figure 3-189. SOFTPRES3 Register.......................................................................................................................................415
Figure 3-190. SOFTPRES4 Register.......................................................................................................................................416
Figure 3-191. SOFTPRES6 Register.......................................................................................................................................417
Figure 3-192. SOFTPRES7 Register.......................................................................................................................................418
Figure 3-193. SOFTPRES8 Register.......................................................................................................................................419
Figure 3-194. SOFTPRES9 Register.......................................................................................................................................420
Figure 3-195. SOFTPRES10 Register.....................................................................................................................................421
Figure 3-196. SOFTPRES11 Register..................................................................................................................................... 422
Figure 3-197. SOFTPRES13 Register.....................................................................................................................................423
Figure 3-198. SOFTPRES14 Register.....................................................................................................................................424
Figure 3-199. SOFTPRES16 Register.....................................................................................................................................425
Figure 3-200. SOFTPRES17 Register.....................................................................................................................................426
Figure 3-201. SOFTPRES18 Register.....................................................................................................................................427
Figure 3-202. SOFTPRES20 Register.....................................................................................................................................429
Figure 3-203. SOFTPRES21 Register.....................................................................................................................................430
Figure 3-204. SOFTPRES23 Register.....................................................................................................................................431
Figure 3-205. CPUSEL0 Register............................................................................................................................................432
Figure 3-206. CPUSEL1 Register............................................................................................................................................434
Figure 3-207. CPUSEL2 Register............................................................................................................................................435
Figure 3-208. CPUSEL4 Register............................................................................................................................................436
Figure 3-209. CPUSEL5 Register............................................................................................................................................437
Figure 3-210. CPUSEL6 Register............................................................................................................................................438
Figure 3-211. CPUSEL7 Register............................................................................................................................................ 439
Figure 3-212. CPUSEL8 Register............................................................................................................................................440
Figure 3-213. CPUSEL9 Register............................................................................................................................................441
Figure 3-214. CPUSEL11 Register.......................................................................................................................................... 442
Figure 3-215. CPUSEL12 Register..........................................................................................................................................443
Figure 3-216. CPUSEL14 Register..........................................................................................................................................444
Figure 3-217. CPUSEL15 Register..........................................................................................................................................445
Figure 3-218. CPUSEL16 Register..........................................................................................................................................446
Figure 3-219. CPUSEL18 Register..........................................................................................................................................448
Figure 3-220. CPUSEL25 Register..........................................................................................................................................449
Figure 3-221. CPU2RESCTL Register.................................................................................................................................... 450
Figure 3-222. RSTSTAT Register............................................................................................................................................ 451
Figure 3-223. LPMSTAT Register............................................................................................................................................ 452
Figure 3-224. USBTYPE Register........................................................................................................................................... 453
Figure 3-225. ECAPTYPE Register.........................................................................................................................................454
Figure 3-226. SDFMTYPE Register........................................................................................................................................ 455
Figure 3-227. MEMMAPTYPE Register.................................................................................................................................. 456
Figure 3-228. CLA1TASKSRCSELLOCK Register..................................................................................................................458
Figure 3-229. DMACHSRCSELLOCK Register.......................................................................................................................459
Figure 3-230. CLA1TASKSRCSEL1 Register..........................................................................................................................460
Figure 3-231. CLA1TASKSRCSEL2 Register..........................................................................................................................461
Figure 3-232. DMACHSRCSEL1 Register.............................................................................................................................. 462
Figure 3-233. DMACHSRCSEL2 Register.............................................................................................................................. 463
Figure 3-234. DxLOCK Register..............................................................................................................................................466
Figure 3-235. DxCOMMIT Register......................................................................................................................................... 467
Figure 3-236. DxACCPROT0 Register.................................................................................................................................... 468
Figure 3-237. DxTEST Register.............................................................................................................................................. 470
Figure 3-238. DxINIT Register.................................................................................................................................................471
Figure 3-239. DxINITDONE Register...................................................................................................................................... 472

SPRUII0E – MAY 2019 – REVISED SEPTEMBER 2023 TMS320F2838x Real-Time Microcontrollers With Connectivity Manager 29
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Figure 3-240. DxRAMTEST_LOCK Register...........................................................................................................................473

Figure 3-241. LSxLOCK Register............................................................................................................................................ 474
Figure 3-242. LSxCOMMIT Register....................................................................................................................................... 476
Figure 3-243. LSxMSEL Register............................................................................................................................................ 478
Figure 3-244. LSxCLAPGM Register.......................................................................................................................................480
Figure 3-245. LSxACCPROT0 Register.................................................................................................................................. 482
Figure 3-246. LSxACCPROT1 Register.................................................................................................................................. 484
Figure 3-247. LSxTEST Register.............................................................................................................................................486
Figure 3-248. LSxINIT Register............................................................................................................................................... 488
Figure 3-249. LSxINITDONE Register.....................................................................................................................................490
Figure 3-250. LSxRAMTEST_LOCK Register.........................................................................................................................492
Figure 3-251. GSxLOCK Register........................................................................................................................................... 493
Figure 3-252. GSxCOMMIT Register...................................................................................................................................... 495
Figure 3-253. GSxMSEL Register........................................................................................................................................... 498
Figure 3-254. GSxACCPROT0 Register................................................................................................................................. 500
Figure 3-255. GSxACCPROT1 Register................................................................................................................................. 502
Figure 3-256. GSxACCPROT2 Register................................................................................................................................. 504
Figure 3-257. GSxACCPROT3 Register................................................................................................................................. 506
Figure 3-258. GSxTEST Register............................................................................................................................................508
Figure 3-259. GSxINIT Register.............................................................................................................................................. 512
Figure 3-260. GSxINITDONE Register....................................................................................................................................514
Figure 3-261. GSxRAMTEST_LOCK Register........................................................................................................................ 516
Figure 3-262. MSGxLOCK Register........................................................................................................................................ 518
Figure 3-263. MSGxCOMMIT Register................................................................................................................................... 520
Figure 3-264. MSGxACCPROT0 Register.............................................................................................................................. 522
Figure 3-265. MSGxACCPROT1 Register.............................................................................................................................. 523
Figure 3-266. MSGxACCPROT2 Register.............................................................................................................................. 524
Figure 3-267. MSGxTEST Register.........................................................................................................................................526
Figure 3-268. MSGxINIT Register........................................................................................................................................... 528
Figure 3-269. MSGxINITDONE Register.................................................................................................................................530
Figure 3-270. MSGxRAMTEST_LOCK Register..................................................................................................................... 532
Figure 3-271. ROM_LOCK Register........................................................................................................................................534
Figure 3-272. ROM_TEST Register........................................................................................................................................ 535
Figure 3-273. ROM_FORCE_ERROR Register...................................................................................................................... 536
Figure 3-274. PERI_MEM_TEST_LOCK Register.................................................................................................................. 537
Figure 3-275. PERI_MEM_TEST_CONTROL Register.......................................................................................................... 538
Figure 3-276. UCERRFLG Register........................................................................................................................................ 541
Figure 3-277. UCERRSET Register........................................................................................................................................ 542
Figure 3-278. UCERRCLR Register........................................................................................................................................ 543
Figure 3-279. UCCPUREADDR Register................................................................................................................................ 544
Figure 3-280. UCDMAREADDR Register................................................................................................................................545
Figure 3-281. UCCLA1READDR Register...............................................................................................................................546
Figure 3-282. UCECATRAMADDR Register........................................................................................................................... 547
Figure 3-283. CERRFLG Register...........................................................................................................................................548
Figure 3-284. CERRSET Register...........................................................................................................................................549
Figure 3-285. CERRCLR Register...........................................................................................................................................550
Figure 3-286. CCPUREADDR Register...................................................................................................................................551
Figure 3-287. CCLA1READDR Register................................................................................................................................. 552
Figure 3-288. CERRCNT Register.......................................................................................................................................... 553
Figure 3-289. CERRTHRES Register......................................................................................................................................554
Figure 3-290. CEINTFLG Register.......................................................................................................................................... 555
Figure 3-291. CEINTCLR Register.......................................................................................................................................... 556
Figure 3-292. CEINTSET Register.......................................................................................................................................... 557
Figure 3-293. CEINTEN Register............................................................................................................................................ 558
Figure 3-294. NMICFG Register..............................................................................................................................................560
Figure 3-295. NMIFLG Register.............................................................................................................................................. 561
Figure 3-296. NMIFLGCLR Register....................................................................................................................................... 564
Figure 3-297. NMIFLGFRC Register....................................................................................................................................... 567
Figure 3-298. NMIWDCNT Register........................................................................................................................................ 569
Figure 3-299. NMIWDPRD Register........................................................................................................................................570
Figure 3-300. NMISHDFLG Register.......................................................................................................................................571

30 TMS320F2838x Real-Time Microcontrollers With Connectivity Manager SPRUII0E – MAY 2019 – REVISED SEPTEMBER 2023
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Figure 3-301. ERRORSTS Register........................................................................................................................................ 574

Figure 3-302. ERRORSTSCLR Register.................................................................................................................................575
Figure 3-303. ERRORSTSFRC Register.................................................................................................................................576
Figure 3-304. ERRORCTL Register........................................................................................................................................ 577
Figure 3-305. ERRORLOCK Register..................................................................................................................................... 578
Figure 3-306. PIECTRL Register.............................................................................................................................................581
Figure 3-307. PIEACK Register...............................................................................................................................................582
Figure 3-308. PIEIER1 Register.............................................................................................................................................. 583
Figure 3-309. PIEIFR1 Register.............................................................................................................................................. 584
Figure 3-310. PIEIER2 Register.............................................................................................................................................. 586
Figure 3-311. PIEIFR2 Register...............................................................................................................................................587
Figure 3-312. PIEIER3 Register.............................................................................................................................................. 589
Figure 3-313. PIEIFR3 Register.............................................................................................................................................. 590
Figure 3-314. PIEIER4 Register.............................................................................................................................................. 592
Figure 3-315. PIEIFR4 Register.............................................................................................................................................. 593
Figure 3-316. PIEIER5 Register.............................................................................................................................................. 595
Figure 3-317. PIEIFR5 Register.............................................................................................................................................. 596
Figure 3-318. PIEIER6 Register.............................................................................................................................................. 598
Figure 3-319. PIEIFR6 Register.............................................................................................................................................. 599
Figure 3-320. PIEIER7 Register.............................................................................................................................................. 601
Figure 3-321. PIEIFR7 Register.............................................................................................................................................. 602
Figure 3-322. PIEIER8 Register.............................................................................................................................................. 604
Figure 3-323. PIEIFR8 Register.............................................................................................................................................. 605
Figure 3-324. PIEIER9 Register.............................................................................................................................................. 607
Figure 3-325. PIEIFR9 Register.............................................................................................................................................. 608
Figure 3-326. PIEIER10 Register............................................................................................................................................ 610
Figure 3-327. PIEIFR10 Register.............................................................................................................................................611
Figure 3-328. PIEIER11 Register.............................................................................................................................................613
Figure 3-329. PIEIFR11 Register.............................................................................................................................................614
Figure 3-330. PIEIER12 Register............................................................................................................................................ 616
Figure 3-331. PIEIFR12 Register............................................................................................................................................ 617
Figure 3-332. ROMPREFETCH Register................................................................................................................................ 620
Figure 3-333. ROMWAITSTATE Register................................................................................................................................622
Figure 3-334. SYNCSELECT Register.................................................................................................................................... 624
Figure 3-335. ADCSOCOUTSELECT Register....................................................................................................................... 626
Figure 3-336. SYNCSOCLOCK Register................................................................................................................................ 629
Figure 3-337. CM_STATUS_INT_FLG Register...................................................................................................................... 631
Figure 3-338. CM_STATUS_INT_CLR Register......................................................................................................................632
Figure 3-339. CM_STATUS_INT_SET Register...................................................................................................................... 633
Figure 3-340. CM_STATUS_MASK Register...........................................................................................................................634
Figure 3-341. SYS_ERR_INT_FLG Register.......................................................................................................................... 635
Figure 3-342. SYS_ERR_INT_CLR Register.......................................................................................................................... 637
Figure 3-343. SYS_ERR_INT_SET Register.......................................................................................................................... 639
Figure 3-344. SYS_ERR_MASK Register............................................................................................................................... 641
Figure 3-345. CPU_RAM_TEST_ERROR_STS Register....................................................................................................... 644
Figure 3-346. CPU_RAM_TEST_ERROR_STS_CLR Register.............................................................................................. 645
Figure 3-347. CPU_RAM_TEST_ERROR_ADDR Register.................................................................................................... 646
Figure 3-348. UID_PSRAND0 Register...................................................................................................................................648
Figure 3-349. UID_PSRAND1 Register...................................................................................................................................649
Figure 3-350. UID_PSRAND2 Register...................................................................................................................................650
Figure 3-351. UID_PSRAND3 Register...................................................................................................................................651
Figure 3-352. UID_PSRAND4 Register...................................................................................................................................652
Figure 3-353. UID_PSRAND5 Register...................................................................................................................................653
Figure 3-354. UID_UNIQUE Register......................................................................................................................................654
Figure 3-355. UID_CHECKSUM Register............................................................................................................................... 655
Figure 3-356. SCSR Register.................................................................................................................................................. 657
Figure 3-357. WDCNTR Register............................................................................................................................................ 658
Figure 3-358. WDKEY Register...............................................................................................................................................659
Figure 3-359. WDCR Register.................................................................................................................................................660
Figure 3-360. WDWCR Register............................................................................................................................................. 662
Figure 3-361. XINT1CR Register.............................................................................................................................................664

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Figure 3-362. XINT2CR Register.............................................................................................................................................665

Figure 3-363. XINT3CR Register.............................................................................................................................................666
Figure 3-364. XINT4CR Register.............................................................................................................................................667
Figure 3-365. XINT5CR Register.............................................................................................................................................668
Figure 3-366. XINT1CTR Register.......................................................................................................................................... 669
Figure 3-367. XINT2CTR Register.......................................................................................................................................... 670
Figure 3-368. XINT3CTR Register.......................................................................................................................................... 671
Figure 5-1. CPU1 Device Boot Flow........................................................................................................................................ 711
Figure 5-2. CPU1 Emulation Boot Flow...................................................................................................................................712
Figure 5-3. CPU1 Standalone Boot Flow.................................................................................................................................713
Figure 5-4. CPU2 Boot Flow....................................................................................................................................................714
Figure 5-5. CM Boot Flow........................................................................................................................................................715
Figure 5-6. Overview of SCI Bootloader Operation................................................................................................................. 732
Figure 5-7. Overview of SCI Boot Function............................................................................................................................. 733
Figure 5-8. SPI Loader............................................................................................................................................................ 734
Figure 5-9. Data Transfer From EEPROM Flow...................................................................................................................... 735
Figure 5-10. EEPROM Device at Address 0x50......................................................................................................................736
Figure 5-11. Overview of I2C Boot Function............................................................................................................................ 737
Figure 5-12. Random Read..................................................................................................................................................... 738
Figure 5-13. Sequential Read..................................................................................................................................................738
Figure 5-14. Overview of Parallel GPIO Bootloader Operation............................................................................................... 739
Figure 5-15. Parallel GPIO Bootloader Handshake Protocol...................................................................................................740
Figure 5-16. Parallel GPIO Mode Overview............................................................................................................................ 741
Figure 5-17. Parallel GPIO Mode - Host Transfer Flow........................................................................................................... 741
Figure 5-18. 8-Bit Parallel GetWord Function.......................................................................................................................... 742
Figure 5-19. Overview of CAN-A Bootloader Operation.......................................................................................................... 743
Figure 5-20. USB Boot Flow.................................................................................................................................................... 745
Figure 6-1. Storage of Zone-Select Bits in OTP...................................................................................................................... 772
Figure 6-2. Location of Zone-Select Block Based on Link-Pointer.......................................................................................... 773
Figure 6-3. CSM Password Match Flow (PMF)....................................................................................................................... 778
Figure 6-4. ECSL Password Match Flow (PMF)......................................................................................................................780
Figure 6-5. Z1_LINKPOINTER Register..................................................................................................................................787
Figure 6-6. Z1_OTPSECLOCK Register................................................................................................................................. 788
Figure 6-7. Z1_JLM_ENABLE Register...................................................................................................................................789
Figure 6-8. Z1_LINKPOINTERERR Register.......................................................................................................................... 790
Figure 6-9. Z1_GPREG1 Register...........................................................................................................................................791
Figure 6-10. Z1_GPREG2 Register.........................................................................................................................................792
Figure 6-11. Z1_GPREG3 Register......................................................................................................................................... 793
Figure 6-12. Z1_GPREG4 Register.........................................................................................................................................794
Figure 6-13. Z1_CSMKEY0 Register.......................................................................................................................................795
Figure 6-14. Z1_CSMKEY1 Register.......................................................................................................................................796
Figure 6-15. Z1_CSMKEY2 Register.......................................................................................................................................797
Figure 6-16. Z1_CSMKEY3 Register.......................................................................................................................................798
Figure 6-17. Z1_CR Register...................................................................................................................................................799
Figure 6-18. Z1_GRABSECT1R Register............................................................................................................................... 800
Figure 6-19. Z1_GRABSECT2R Register............................................................................................................................... 803
Figure 6-20. Z1_GRABSECT3R Register............................................................................................................................... 806
Figure 6-21. Z1_GRABRAM1R Register................................................................................................................................. 809
Figure 6-22. Z1_GRABRAM2R Register................................................................................................................................. 811
Figure 6-23. Z1_GRABRAM3R Register................................................................................................................................. 814
Figure 6-24. Z1_EXEONLYSECT1R Register......................................................................................................................... 816
Figure 6-25. Z1_EXEONLYSECT2R Register......................................................................................................................... 820
Figure 6-26. Z1_EXEONLYRAM1R Register...........................................................................................................................823
Figure 6-27. Z1_JTAGKEY0 Register......................................................................................................................................827
Figure 6-28. Z1_JTAGKEY1 Register......................................................................................................................................828
Figure 6-29. Z1_JTAGKEY2 Register......................................................................................................................................829
Figure 6-30. Z1_JTAGKEY3 Register......................................................................................................................................830
Figure 6-31. Z1_CMACKEY0 Register.................................................................................................................................... 831
Figure 6-32. Z1_CMACKEY1 Register.................................................................................................................................... 832
Figure 6-33. Z1_CMACKEY2 Register.................................................................................................................................... 833
Figure 6-34. Z1_CMACKEY3 Register.................................................................................................................................... 834

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Figure 6-35. Z2_LINKPOINTER Register................................................................................................................................837

Figure 6-36. Z2_OTPSECLOCK Register............................................................................................................................... 838
Figure 6-37. Z2_LINKPOINTERERR Register........................................................................................................................ 839
Figure 6-38. Z2_GPREG1 Register.........................................................................................................................................840
Figure 6-39. Z2_GPREG2 Register.........................................................................................................................................841
Figure 6-40. Z2_GPREG3 Register.........................................................................................................................................842
Figure 6-41. Z2_GPREG4 Register.........................................................................................................................................843
Figure 6-42. Z2_CSMKEY0 Register.......................................................................................................................................844
Figure 6-43. Z2_CSMKEY1 Register.......................................................................................................................................845
Figure 6-44. Z2_CSMKEY2 Register.......................................................................................................................................846
Figure 6-45. Z2_CSMKEY3 Register.......................................................................................................................................847
Figure 6-46. Z2_CR Register...................................................................................................................................................848
Figure 6-47. Z2_GRABSECT1R Register............................................................................................................................... 849
Figure 6-48. Z2_GRABSECT2R Register............................................................................................................................... 852
Figure 6-49. Z2_GRABSECT3R Register............................................................................................................................... 855
Figure 6-50. Z2_GRABRAM1R Register................................................................................................................................. 858
Figure 6-51. Z2_GRABRAM2R Register................................................................................................................................. 860
Figure 6-52. Z2_GRABRAM3R Register................................................................................................................................. 863
Figure 6-53. Z2_EXEONLYSECT1R Register......................................................................................................................... 865
Figure 6-54. Z2_EXEONLYSECT2R Register......................................................................................................................... 869
Figure 6-55. Z2_EXEONLYRAM1R Register...........................................................................................................................872
Figure 6-56. FLSEM Register.................................................................................................................................................. 877
Figure 6-57. SECTSTAT1 Register..........................................................................................................................................878
Figure 6-58. SECTSTAT2 Register..........................................................................................................................................881
Figure 6-59. SECTSTAT3 Register..........................................................................................................................................884
Figure 6-60. RAMSTAT1 Register........................................................................................................................................... 887
Figure 6-61. RAMSTAT2 Register........................................................................................................................................... 889
Figure 6-62. RAMSTAT3 Register........................................................................................................................................... 892
Figure 6-63. SECERRSTAT Register...................................................................................................................................... 894
Figure 6-64. SECERRCLR Register........................................................................................................................................895
Figure 6-65. SECERRFRC Register........................................................................................................................................896
Figure 6-66. Z1OTP_LINKPOINTER1 Register...................................................................................................................... 898
Figure 6-67. Z1OTP_LINKPOINTER2 Register...................................................................................................................... 899
Figure 6-68. Z1OTP_LINKPOINTER3 Register...................................................................................................................... 900
Figure 6-69. Z1OTP_JLM_ENABLE Register......................................................................................................................... 901
Figure 6-70. Z1OTP_GPREG1 Register................................................................................................................................. 902
Figure 6-71. Z1OTP_GPREG2 Register................................................................................................................................. 903
Figure 6-72. Z1OTP_GPREG3 Register................................................................................................................................. 904
Figure 6-73. Z1OTP_GPREG4 Register................................................................................................................................. 905
Figure 6-74. Z1OTP_PSWDLOCK Register............................................................................................................................906
Figure 6-75. Z1OTP_CRCLOCK Register...............................................................................................................................907
Figure 6-76. Z1OTP_JTAGPSWDH0 Register........................................................................................................................ 908
Figure 6-77. Z1OTP_JTAGPSWDH1 Register........................................................................................................................ 909
Figure 6-78. Z1OTP_CMACKEY0 Register.............................................................................................................................910
Figure 6-79. Z1OTP_CMACKEY1 Register............................................................................................................................. 911
Figure 6-80. Z1OTP_CMACKEY2 Register.............................................................................................................................912
Figure 6-81. Z1OTP_CMACKEY3 Register.............................................................................................................................913
Figure 6-82. Z2OTP_LINKPOINTER1 Register...................................................................................................................... 915
Figure 6-83. Z2OTP_LINKPOINTER2 Register...................................................................................................................... 916
Figure 6-84. Z2OTP_LINKPOINTER3 Register...................................................................................................................... 917
Figure 6-85. Z2OTP_GPREG1 Register................................................................................................................................. 918
Figure 6-86. Z2OTP_GPREG2 Register................................................................................................................................. 919
Figure 6-87. Z2OTP_GPREG3 Register................................................................................................................................. 920
Figure 6-88. Z2OTP_GPREG4 Register................................................................................................................................. 921
Figure 6-89. Z2OTP_PSWDLOCK Register............................................................................................................................922
Figure 6-90. Z2OTP_CRCLOCK Register...............................................................................................................................923
Figure 7-1. BGCRC Block Diagram......................................................................................................................................... 926
Figure 7-2. BGCRC Memory Map........................................................................................................................................... 927
Figure 7-3. BGCRC NMI..........................................................................................................................................................929
Figure 7-4. BGCRC Interrupt................................................................................................................................................... 929
Figure 7-5. BGCRC Execution Sequence Flow.......................................................................................................................931

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Figure 7-6. BGCRC Execution Sequence Example................................................................................................................ 933

Figure 7-7. BGCRC_EN Register............................................................................................................................................ 939
Figure 7-8. BGCRC_CTRL1 Register......................................................................................................................................940
Figure 7-9. BGCRC_CTRL2 Register......................................................................................................................................941
Figure 7-10. BGCRC_START_ADDR Register....................................................................................................................... 942
Figure 7-11. BGCRC_SEED Register......................................................................................................................................943
Figure 7-12. BGCRC_GOLDEN Register................................................................................................................................944
Figure 7-13. BGCRC_RESULT Register................................................................................................................................. 945
Figure 7-14. BGCRC_CURR_ADDR Register........................................................................................................................ 946
Figure 7-15. BGCRC_WD_CFG Register............................................................................................................................... 947
Figure 7-16. BGCRC_WD_MIN Register................................................................................................................................ 948
Figure 7-17. BGCRC_WD_MAX Register............................................................................................................................... 949
Figure 7-18. BGCRC_WD_CNT Register................................................................................................................................950
Figure 7-19. BGCRC_NMIFLG Register................................................................................................................................. 951
Figure 7-20. BGCRC_NMICLR Register................................................................................................................................. 952
Figure 7-21. BGCRC_NMIFRC Register................................................................................................................................. 953
Figure 7-22. BGCRC_INTEN Register.................................................................................................................................... 954
Figure 7-23. BGCRC_INTFLG Register.................................................................................................................................. 955
Figure 7-24. BGCRC_INTCLR Register.................................................................................................................................. 957
Figure 7-25. BGCRC_INTFRC Register..................................................................................................................................958
Figure 7-26. BGCRC_LOCK Register..................................................................................................................................... 959
Figure 7-27. BGCRC_COMMIT Register................................................................................................................................ 961
Figure 8-1. CLA (Type 2) Block Diagram.................................................................................................................................967
Figure 8-2. _MVECTBGRNDACTIVE Register...................................................................................................................... 1118
Figure 8-3. _MPSACTL Register............................................................................................................................................1119
Figure 8-4. _MPSA1 Register................................................................................................................................................ 1120
Figure 8-5. _MPSA2 Register................................................................................................................................................ 1121
Figure 8-6. SOFTINTEN Register.......................................................................................................................................... 1122
Figure 8-7. SOFTINTFRC Register........................................................................................................................................1124
Figure 8-8. SOFTINTEN Register.......................................................................................................................................... 1126
Figure 8-9. SOFTINTFRC Register........................................................................................................................................1128
Figure 8-10. MVECT1 Register..............................................................................................................................................1131
Figure 8-11. MVECT2 Register.............................................................................................................................................. 1132
Figure 8-12. MVECT3 Register..............................................................................................................................................1133
Figure 8-13. MVECT4 Register..............................................................................................................................................1134
Figure 8-14. MVECT5 Register..............................................................................................................................................1135
Figure 8-15. MVECT6 Register..............................................................................................................................................1136
Figure 8-16. MVECT7 Register..............................................................................................................................................1137
Figure 8-17. MVECT8 Register..............................................................................................................................................1138
Figure 8-18. MCTL Register...................................................................................................................................................1139
Figure 8-19. _MVECTBGRNDACTIVE Register....................................................................................................................1140
Figure 8-20. SOFTINTEN Register........................................................................................................................................ 1141
Figure 8-21. _MSTSBGRND Register................................................................................................................................... 1143
Figure 8-22. _MCTLBGRND Register....................................................................................................................................1144
Figure 8-23. _MVECTBGRND Register.................................................................................................................................1145
Figure 8-24. MIFR Register....................................................................................................................................................1146
Figure 8-25. MIOVF Register................................................................................................................................................. 1150
Figure 8-26. MIFRC Register................................................................................................................................................. 1153
Figure 8-27. MICLR Register................................................................................................................................................. 1155
Figure 8-28. MICLROVF Register..........................................................................................................................................1157
Figure 8-29. MIER Register................................................................................................................................................... 1159
Figure 8-30. MIRUN Register.................................................................................................................................................1162
Figure 8-31. _MPC Register.................................................................................................................................................. 1164
Figure 8-32. _MAR0 Register................................................................................................................................................ 1165
Figure 8-33. _MAR1 Register................................................................................................................................................ 1166
Figure 8-34. _MSTF Register.................................................................................................................................................1167
Figure 8-35. _MR0 Register...................................................................................................................................................1170
Figure 8-36. _MR1 Register...................................................................................................................................................1171
Figure 8-37. _MR2 Register...................................................................................................................................................1172
Figure 8-38. _MR3 Register...................................................................................................................................................1173
Figure 8-39. _MPSACTL Register......................................................................................................................................... 1174

34 TMS320F2838x Real-Time Microcontrollers With Connectivity Manager SPRUII0E – MAY 2019 – REVISED SEPTEMBER 2023
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Figure 8-40. _MPSA1 Register.............................................................................................................................................. 1175

Figure 8-41. _MPSA2 Register.............................................................................................................................................. 1176
Figure 9-1. Block Diagram of the CLB Subsystem in the Device...........................................................................................1181
Figure 9-2. Block Diagram of a CLB Tile and CPU Interface................................................................................................. 1181
Figure 9-3. CLB Clocking....................................................................................................................................................... 1182
Figure 9-4. CLB Clock Prescalar............................................................................................................................................1183
Figure 9-5. GPIO to CLB Tile Connections............................................................................................................................ 1184
Figure 9-6. CLB Input Mux and Filter..................................................................................................................................... 1185
Figure 9-7. CLB Input Synchronization Example................................................................................................................... 1185
Figure 9-8. CLB Input Pipelining Example............................................................................................................................. 1186
Figure 9-9. CLB Outputs........................................................................................................................................................ 1199
Figure 9-10. CLB Output Signal Multiplexer.......................................................................................................................... 1200
Figure 9-11. CLB Tile Submodules........................................................................................................................................ 1203
Figure 9-12. Counter Block....................................................................................................................................................1206
Figure 9-13. LFSR Modes..................................................................................................................................................... 1209
Figure 9-14. FSM Block......................................................................................................................................................... 1210
Figure 9-15. FSM LUT Block..................................................................................................................................................1211
Figure 9-16. LUT4 Block........................................................................................................................................................1212
Figure 9-17. Output LUT Block.............................................................................................................................................. 1212
Figure 9-18. AOC Block.........................................................................................................................................................1214
Figure 9-19. AOC Block and The CLB TILE.......................................................................................................................... 1215
Figure 9-20. High Level Controller Block............................................................................................................................... 1216
Figure 9-21. CLB Control of SPI RX Buffer............................................................................................................................1224
Figure 9-22. CLB_COUNT_RESET Register........................................................................................................................ 1234
Figure 9-23. CLB_COUNT_MODE_1 Register..................................................................................................................... 1235
Figure 9-24. CLB_COUNT_MODE_0 Register..................................................................................................................... 1236
Figure 9-25. CLB_COUNT_EVENT Register........................................................................................................................ 1237
Figure 9-26. CLB_FSM_EXTRA_IN0 Register......................................................................................................................1238
Figure 9-27. CLB_FSM_EXTERNAL_IN0 Register...............................................................................................................1239
Figure 9-28. CLB_FSM_EXTERNAL_IN1 Register...............................................................................................................1240
Figure 9-29. CLB_FSM_EXTRA_IN1 Register......................................................................................................................1241
Figure 9-30. CLB_LUT4_IN0 Register...................................................................................................................................1242
Figure 9-31. CLB_LUT4_IN1 Register...................................................................................................................................1243
Figure 9-32. CLB_LUT4_IN2 Register...................................................................................................................................1244
Figure 9-33. CLB_LUT4_IN3 Register...................................................................................................................................1245
Figure 9-34. CLB_FSM_LUT_FN1_0 Register......................................................................................................................1246
Figure 9-35. CLB_FSM_LUT_FN2 Register..........................................................................................................................1247
Figure 9-36. CLB_LUT4_FN1_0 Register............................................................................................................................. 1248
Figure 9-37. CLB_LUT4_FN2 Register................................................................................................................................. 1249
Figure 9-38. CLB_FSM_NEXT_STATE_0 Register...............................................................................................................1250
Figure 9-39. CLB_FSM_NEXT_STATE_1 Register...............................................................................................................1251
Figure 9-40. CLB_FSM_NEXT_STATE_2 Register...............................................................................................................1252
Figure 9-41. CLB_MISC_CONTROL Register...................................................................................................................... 1253
Figure 9-42. CLB_OUTPUT_LUT_0 Register....................................................................................................................... 1256
Figure 9-43. CLB_OUTPUT_LUT_1 Register....................................................................................................................... 1257
Figure 9-44. CLB_OUTPUT_LUT_2 Register....................................................................................................................... 1258
Figure 9-45. CLB_OUTPUT_LUT_3 Register....................................................................................................................... 1259
Figure 9-46. CLB_OUTPUT_LUT_4 Register....................................................................................................................... 1260
Figure 9-47. CLB_OUTPUT_LUT_5 Register....................................................................................................................... 1261
Figure 9-48. CLB_OUTPUT_LUT_6 Register....................................................................................................................... 1262
Figure 9-49. CLB_OUTPUT_LUT_7 Register....................................................................................................................... 1263
Figure 9-50. CLB_HLC_EVENT_SEL Register..................................................................................................................... 1264
Figure 9-51. CLB_COUNT_MATCH_TAP_SEL Register...................................................................................................... 1265
Figure 9-52. CLB_OUTPUT_COND_CTRL_0 Register........................................................................................................ 1266
Figure 9-53. CLB_OUTPUT_COND_CTRL_1 Register........................................................................................................ 1268
Figure 9-54. CLB_OUTPUT_COND_CTRL_2 Register........................................................................................................ 1270
Figure 9-55. CLB_OUTPUT_COND_CTRL_3 Register........................................................................................................ 1272
Figure 9-56. CLB_OUTPUT_COND_CTRL_4 Register........................................................................................................ 1274
Figure 9-57. CLB_OUTPUT_COND_CTRL_5 Register........................................................................................................ 1276
Figure 9-58. CLB_OUTPUT_COND_CTRL_6 Register........................................................................................................ 1278
Figure 9-59. CLB_OUTPUT_COND_CTRL_7 Register........................................................................................................ 1280

SPRUII0E – MAY 2019 – REVISED SEPTEMBER 2023 TMS320F2838x Real-Time Microcontrollers With Connectivity Manager 35
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Figure 9-60. CLB_MISC_ACCESS_CTRL Register..............................................................................................................1282

Figure 9-61. CLB_SPI_DATA_CTRL_HI Register................................................................................................................. 1283
Figure 9-62. CLB_LOAD_EN Register.................................................................................................................................. 1286
Figure 9-63. CLB_LOAD_ADDR Register............................................................................................................................. 1287
Figure 9-64. CLB_LOAD_DATA Register.............................................................................................................................. 1288
Figure 9-65. CLB_INPUT_FILTER Register.......................................................................................................................... 1289
Figure 9-66. CLB_IN_MUX_SEL_0 Register.........................................................................................................................1291
Figure 9-67. CLB_LCL_MUX_SEL_1 Register......................................................................................................................1293
Figure 9-68. CLB_LCL_MUX_SEL_2 Register......................................................................................................................1294
Figure 9-69. CLB_BUF_PTR Register...................................................................................................................................1295
Figure 9-70. CLB_GP_REG Register.................................................................................................................................... 1296
Figure 9-71. CLB_OUT_EN Register.................................................................................................................................... 1298
Figure 9-72. CLB_GLBL_MUX_SEL_1 Register................................................................................................................... 1299
Figure 9-73. CLB_GLBL_MUX_SEL_2 Register................................................................................................................... 1300
Figure 9-74. CLB_PRESCALE_CTRL Register.................................................................................................................... 1301
Figure 9-75. CLB_INTR_TAG_REG Register........................................................................................................................1302
Figure 9-76. CLB_LOCK Register......................................................................................................................................... 1303
Figure 9-77. CLB_HLC_INSTR_READ_PTR Register..........................................................................................................1304
Figure 9-78. CLB_HLC_INSTR_VALUE Register..................................................................................................................1305
Figure 9-79. CLB_DBG_OUT_2 Register..............................................................................................................................1306
Figure 9-80. CLB_DBG_R0 Register.....................................................................................................................................1307
Figure 9-81. CLB_DBG_R1 Register.....................................................................................................................................1308
Figure 9-82. CLB_DBG_R2 Register.....................................................................................................................................1309
Figure 9-83. CLB_DBG_R3 Register.....................................................................................................................................1310
Figure 9-84. CLB_DBG_C0 Register..................................................................................................................................... 1311
Figure 9-85. CLB_DBG_C1 Register.....................................................................................................................................1312
Figure 9-86. CLB_DBG_C2 Register.....................................................................................................................................1313
Figure 9-87. CLB_DBG_OUT Register..................................................................................................................................1314
Figure 9-88. CLB_PUSH Register......................................................................................................................................... 1317
Figure 9-89. CLB_PULL Register.......................................................................................................................................... 1318
Figure 10-1. DCC Module Overview......................................................................................................................................1324
Figure 10-2. DCC Operation..................................................................................................................................................1325
Figure 10-3. Counter Relationship.........................................................................................................................................1329
Figure 10-4. Clock1 Slower Than Clock0 - Results in an Error and Stops Counting.............................................................1329
Figure 10-5. Clock1 Faster Than Clock0 - Results in an Error and Stops Counting............................................................. 1330
Figure 10-6. Clock1 Not Present - Results in an Error and Stops Counting..........................................................................1330
Figure 10-7. Clock0 Not Present - Results in an Error and Stops Counting..........................................................................1331
Figure 10-8. DCCGCTRL Register........................................................................................................................................ 1336
Figure 10-9. DCCCNTSEED0 Register................................................................................................................................. 1337
Figure 10-10. DCCVALIDSEED0 Register............................................................................................................................ 1338
Figure 10-11. DCCCNTSEED1 Register............................................................................................................................... 1339
Figure 10-12. DCCSTATUS Register.....................................................................................................................................1340
Figure 10-13. DCCCNT0 Register.........................................................................................................................................1341
Figure 10-14. DCCVALID0 Register...................................................................................................................................... 1342
Figure 10-15. DCCCNT1 Register.........................................................................................................................................1343
Figure 10-16. DCCCLKSRC1 Register..................................................................................................................................1344
Figure 10-17. DCCCLKSRC0 Register..................................................................................................................................1345
Figure 11-1. DMA Block Diagram.......................................................................................................................................... 1349
Figure 11-2. DMA Trigger Architecture.................................................................................................................................. 1351
Figure 11-3. Peripheral Interrupt Trigger Input Diagram........................................................................................................ 1352
Figure 11-4. DMA State Diagram...........................................................................................................................................1360
Figure 11-5. 3-Stage Pipeline DMA Transfer......................................................................................................................... 1361
Figure 11-6. 3-stage Pipeline with One Read Stall................................................................................................................ 1361
Figure 11-7. Overrun Detection Logic.................................................................................................................................... 1364
Figure 11-8. DMACTRL Register........................................................................................................................................... 1368
Figure 11-9. DEBUGCTRL Register...................................................................................................................................... 1369
Figure 11-10. PRIORITYCTRL1 Register.............................................................................................................................. 1370
Figure 11-11. PRIORITYSTAT Register................................................................................................................................. 1371
Figure 11-12. MODE Register................................................................................................................................................1374
Figure 11-13. CONTROL Register.........................................................................................................................................1376
Figure 11-14. BURST_SIZE Register.................................................................................................................................... 1378

36 TMS320F2838x Real-Time Microcontrollers With Connectivity Manager SPRUII0E – MAY 2019 – REVISED SEPTEMBER 2023
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Figure 11-15. BURST_COUNT Register............................................................................................................................... 1379

Figure 11-16. SRC_BURST_STEP Register......................................................................................................................... 1380
Figure 11-17. DST_BURST_STEP Register..........................................................................................................................1381
Figure 11-18. TRANSFER_SIZE Register............................................................................................................................. 1382
Figure 11-19. TRANSFER_COUNT Register........................................................................................................................ 1383
Figure 11-20. SRC_TRANSFER_STEP Register.................................................................................................................. 1384
Figure 11-21. DST_TRANSFER_STEP Register.................................................................................................................. 1385
Figure 11-22. SRC_WRAP_SIZE Register............................................................................................................................ 1386
Figure 11-23. SRC_WRAP_COUNT Register....................................................................................................................... 1387
Figure 11-24. SRC_WRAP_STEP Register...........................................................................................................................1388
Figure 11-25. DST_WRAP_SIZE Register............................................................................................................................ 1389
Figure 11-26. DST_WRAP_COUNT Register........................................................................................................................1390
Figure 11-27. DST_WRAP_STEP Register........................................................................................................................... 1391
Figure 11-28. SRC_BEG_ADDR_SHADOW Register...........................................................................................................1392
Figure 11-29. SRC_ADDR_SHADOW Register.................................................................................................................... 1393
Figure 11-30. SRC_BEG_ADDR_ACTIVE Register.............................................................................................................. 1394
Figure 11-31. SRC_ADDR_ACTIVE Register........................................................................................................................1395
Figure 11-32. DST_BEG_ADDR_SHADOW Register........................................................................................................... 1396
Figure 11-33. DST_ADDR_SHADOW Register.....................................................................................................................1397
Figure 11-34. DST_BEG_ADDR_ACTIVE Register.............................................................................................................. 1398
Figure 11-35. DST_ADDR_ACTIVE Register........................................................................................................................ 1399
Figure 12-1. EMIF Module Overview..................................................................................................................................... 1404
Figure 12-2. EMIF Functional Block Diagram........................................................................................................................1406
Figure 12-3. Timing Waveform of SDRAM PRE Command...................................................................................................1410
Figure 12-4. EMIF to 2M × 16 × 4 Bank SDRAM Interface....................................................................................................1411
Figure 12-5. EMIF to 512K × 16 × 2 Bank SDRAM Interface................................................................................................ 1411
Figure 12-6. Timing Waveform for Basic SDRAM Read Operation....................................................................................... 1419
Figure 12-7. Timing Waveform for Basic SDRAM Write Operation....................................................................................... 1420
Figure 12-8. EMIF Asynchronous Interface........................................................................................................................... 1422
Figure 12-9. EMIF to 8-bit/16-bit Memory Interface...............................................................................................................1423
Figure 12-10. Common Asynchronous Interface................................................................................................................... 1423
Figure 12-11. Timing Waveform of an Asynchronous Read Cycle in Normal Mode.............................................................. 1427
Figure 12-12. Timing Waveform of an Asynchronous Write Cycle in Normal Mode.............................................................. 1429
Figure 12-13. Timing Waveform of an Asynchronous Read Cycle in Select Strobe Mode....................................................1431
Figure 12-14. Timing Waveform of an Asynchronous Write Cycle in Select Strobe Mode.................................................... 1433
Figure 12-15. Example Configuration Interface..................................................................................................................... 1439
Figure 12-16. SDRAM Timing Register (SDRAM_TR).......................................................................................................... 1440
Figure 12-17. SDRAM Self Refresh Exit Timing Register (SDR_EXT_TMNG)..................................................................... 1441
Figure 12-18. SDRAM Refresh Control Register (SDRAM_RCR).........................................................................................1441
Figure 12-19. SDRAM Configuration Register (SDRAM_CR)............................................................................................... 1442
Figure 12-20. LH28F800BJE-PTTL90 to EMIF Read Timing Waveforms............................................................................. 1443
Figure 12-21. LH28F800BJE-PTTL90 to EMIF Write Timing Waveforms............................................................................. 1444
Figure 12-22. Asynchronous m Configuration Register (m = 1, 2) (ASYNC_CSn_CR(n = 2, 3))..........................................1446
Figure 12-23. RCSR Register................................................................................................................................................1453
Figure 12-24. ASYNC_WCCR Register................................................................................................................................ 1454
Figure 12-25. SDRAM_CR Register......................................................................................................................................1455
Figure 12-26. SDRAM_RCR Register................................................................................................................................... 1457
Figure 12-27. ASYNC_CS2_CR Register............................................................................................................................. 1458
Figure 12-28. ASYNC_CS3_CR Register............................................................................................................................. 1460
Figure 12-29. ASYNC_CS4_CR Register............................................................................................................................. 1462
Figure 12-30. SDRAM_TR Register...................................................................................................................................... 1464
Figure 12-31. TOTAL_SDRAM_AR Register.........................................................................................................................1465
Figure 12-32. TOTAL_SDRAM_ACTR Register.................................................................................................................... 1466
Figure 12-33. SDR_EXT_TMNG Register.............................................................................................................................1467
Figure 12-34. INT_RAW Register.......................................................................................................................................... 1468
Figure 12-35. INT_MSK Register.......................................................................................................................................... 1469
Figure 12-36. INT_MSK_SET Register................................................................................................................................. 1470
Figure 12-37. INT_MSK_CLR Register................................................................................................................................. 1471
Figure 12-38. EMIF1LOCK Register......................................................................................................................................1473
Figure 12-39. EMIF1COMMIT Register.................................................................................................................................1474
Figure 12-40. EMIF1MSEL Register......................................................................................................................................1475

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Figure 12-41. EMIF1ACCPROT0 Register............................................................................................................................1476

Figure 12-42. EMIF2LOCK Register......................................................................................................................................1478
Figure 12-43. EMIF2COMMIT Register.................................................................................................................................1479
Figure 12-44. EMIF2ACCPROT0 Register............................................................................................................................1480
Figure 13-1. FMC Interface with Core, Bank, and Pump.......................................................................................................1486
Figure 13-2. Flash Prefetch Mode......................................................................................................................................... 1491
Figure 13-3. Flash Cache Mode............................................................................................................................................ 1493
Figure 13-4. ECC Logic Inputs and Outputs..........................................................................................................................1496
Figure 13-5. Flash Pump Semaphore (PUMPREQUEST) States and State Transitions...................................................... 1502
Figure 13-6. FRDCNTL Register........................................................................................................................................... 1506
Figure 13-7. FBAC Register.................................................................................................................................................. 1507
Figure 13-8. FBFALLBACK Register..................................................................................................................................... 1508
Figure 13-9. FBPRDY Register............................................................................................................................................. 1509
Figure 13-10. FPAC1 Register...............................................................................................................................................1510
Figure 13-11. FMSTAT Register.............................................................................................................................................1511
Figure 13-12. FRD_INTF_CTRL Register............................................................................................................................. 1513
Figure 13-13. ECC_ENABLE Register.................................................................................................................................. 1516
Figure 13-14. SINGLE_ERR_ADDR_LOW Register.............................................................................................................1517
Figure 13-15. SINGLE_ERR_ADDR_HIGH Register............................................................................................................ 1518
Figure 13-16. UNC_ERR_ADDR_LOW Register.................................................................................................................. 1519
Figure 13-17. UNC_ERR_ADDR_HIGH Register................................................................................................................. 1520
Figure 13-18. ERR_STATUS Register...................................................................................................................................1521
Figure 13-19. ERR_POS Register.........................................................................................................................................1523
Figure 13-20. ERR_STATUS_CLR Register..........................................................................................................................1524
Figure 13-21. ERR_CNT Register......................................................................................................................................... 1525
Figure 13-22. ERR_THRESHOLD Register.......................................................................................................................... 1526
Figure 13-23. ERR_INTFLG Register....................................................................................................................................1527
Figure 13-24. ERR_INTCLR Register................................................................................................................................... 1528
Figure 13-25. FDATAH_TEST Register................................................................................................................................. 1529
Figure 13-26. FDATAL_TEST Register..................................................................................................................................1530
Figure 13-27. FADDR_TEST Register...................................................................................................................................1531
Figure 13-28. FECC_TEST Register..................................................................................................................................... 1532
Figure 13-29. FECC_CTRL Register.....................................................................................................................................1533
Figure 13-30. FOUTH_TEST Register.................................................................................................................................. 1534
Figure 13-31. FOUTL_TEST Register................................................................................................................................... 1535
Figure 13-32. FECC_STATUS Register.................................................................................................................................1536
Figure 13-33. FRDCNTL Register......................................................................................................................................... 1538
Figure 13-34. FBAC Register................................................................................................................................................ 1539
Figure 13-35. FBFALLBACK Register................................................................................................................................... 1540
Figure 13-36. FBPRDY Register........................................................................................................................................... 1541
Figure 13-37. FPAC1 Register...............................................................................................................................................1542
Figure 13-38. FMSTAT Register............................................................................................................................................ 1543
Figure 13-39. FRD_INTF_CTRL_LOCK Register................................................................................................................. 1545
Figure 13-40. FRD_INTF_CTRL Register............................................................................................................................. 1546
Figure 13-41. ECC_ENABLE Register.................................................................................................................................. 1549
Figure 13-42. SINGLE_ERR_ADDR_LOW Register.............................................................................................................1550
Figure 13-43. SINGLE_ERR_ADDR_HIGH Register............................................................................................................ 1551
Figure 13-44. UNC_ERR_ADDR_LOW Register.................................................................................................................. 1552
Figure 13-45. UNC_ERR_ADDR_HIGH Register................................................................................................................. 1553
Figure 13-46. ERR_STATUS Register...................................................................................................................................1554
Figure 13-47. ERR_POS Register.........................................................................................................................................1556
Figure 13-48. ERR_STATUS_CLR Register..........................................................................................................................1557
Figure 13-49. ERR_CNT Register......................................................................................................................................... 1558
Figure 13-50. ERR_THRESHOLD Register.......................................................................................................................... 1559
Figure 13-51. ERR_INTFLG Register....................................................................................................................................1560
Figure 13-52. ERR_INTCLR Register................................................................................................................................... 1561
Figure 13-53. FDATAH_TEST Register................................................................................................................................. 1562
Figure 13-54. FDATAL_TEST Register..................................................................................................................................1563
Figure 13-55. FADDR_TEST Register...................................................................................................................................1564
Figure 13-56. FECC_TEST Register..................................................................................................................................... 1565
Figure 13-57. FECC_CTRL Register.....................................................................................................................................1566

38 TMS320F2838x Real-Time Microcontrollers With Connectivity Manager SPRUII0E – MAY 2019 – REVISED SEPTEMBER 2023
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Figure 13-58. FOUTH_TEST Register.................................................................................................................................. 1567

Figure 13-59. FOUTL_TEST Register................................................................................................................................... 1568
Figure 13-60. FECC_STATUS Register.................................................................................................................................1569
Figure 13-61. FLASH_ECC_REGS_LOCK Register.............................................................................................................1570
Figure 13-62. PUMPREQUEST Register.............................................................................................................................. 1572
Figure 14-1. ERAD Overview................................................................................................................................................ 1576
Figure 14-2. EBC Units Event Masking................................................................................................................................. 1578
Figure 14-3. System Event Counter Inputs............................................................................................................................1580
Figure 14-4. Event Masking and Exporting for CRC Qualifiers............................................................................................. 1587
Figure 14-5. PC Trace Operation...........................................................................................................................................1589
Figure 14-6. PC Trace Block Diagram................................................................................................................................... 1590
Figure 14-7. Trace Qualifier Input Conditioning Circuit..........................................................................................................1592
Figure 14-8. GLBL_EVENT_STAT Register.......................................................................................................................... 1604
Figure 14-9. GLBL_HALT_STAT Register............................................................................................................................. 1606
Figure 14-10. GLBL_ENABLE Register.................................................................................................................................1608
Figure 14-11. GLBL_CTM_RESET Register......................................................................................................................... 1610
Figure 14-12. GLBL_NMI_CTL Register................................................................................................................................1611
Figure 14-13. GLBL_OWNER Register................................................................................................................................. 1613
Figure 14-14. GLBL_EVENT_AND_MASK Register............................................................................................................. 1614
Figure 14-15. GLBL_EVENT_OR_MASK Register............................................................................................................... 1618
Figure 14-16. GLBL_AND_EVENT_INT_MASK Register..................................................................................................... 1622
Figure 14-17. GLBL_OR_EVENT_INT_MASK Register....................................................................................................... 1623
Figure 14-18. HWBP_MASK Register................................................................................................................................... 1625
Figure 14-19. HWBP_REF Register...................................................................................................................................... 1626
Figure 14-20. HWBP_CLEAR Register................................................................................................................................. 1627
Figure 14-21. HWBP_CNTL Register....................................................................................................................................1628
Figure 14-22. HWBP_STATUS Register................................................................................................................................1630
Figure 14-23. CTM_CNTL Register.......................................................................................................................................1632
Figure 14-24. CTM_STATUS Register...................................................................................................................................1634
Figure 14-25. CTM_REF Register......................................................................................................................................... 1635
Figure 14-26. CTM_COUNT Register................................................................................................................................... 1636
Figure 14-27. CTM_MAX_COUNT Register..........................................................................................................................1637
Figure 14-28. CTM_INPUT_SEL Register.............................................................................................................................1638
Figure 14-29. CTM_CLEAR Register.................................................................................................................................... 1639
Figure 14-30. CTM_INPUT_SEL_2 Register.........................................................................................................................1640
Figure 14-31. CTM_INPUT_COND Register.........................................................................................................................1641
Figure 14-32. CRC_GLOBAL_CTRL Register...................................................................................................................... 1643
Figure 14-33. CRC_CURRENT Register...............................................................................................................................1646
Figure 14-34. CRC_SEED Register...................................................................................................................................... 1647
Figure 14-35. CRC_QUALIFIER Register............................................................................................................................. 1648
Figure 15-1. GPIO Logic for a Single Pin.............................................................................................................................. 1653
Figure 15-2. Input Qualification Using a Sampling Window...................................................................................................1657
Figure 15-3. Input Qualifier Clock Cycles.............................................................................................................................. 1660
Figure 15-4. GPACTRL Register........................................................................................................................................... 1678
Figure 15-5. GPAQSEL1 Register......................................................................................................................................... 1679
Figure 15-6. GPAQSEL2 Register......................................................................................................................................... 1680
Figure 15-7. GPAMUX1 Register...........................................................................................................................................1681
Figure 15-8. GPAMUX2 Register...........................................................................................................................................1682
Figure 15-9. GPADIR Register...............................................................................................................................................1683
Figure 15-10. GPAPUD Register........................................................................................................................................... 1685
Figure 15-11. GPAINV Register............................................................................................................................................. 1687
Figure 15-12. GPAODR Register...........................................................................................................................................1689
Figure 15-13. GPAGMUX1 Register...................................................................................................................................... 1691
Figure 15-14. GPAGMUX2 Register...................................................................................................................................... 1692
Figure 15-15. GPACSEL1 Register....................................................................................................................................... 1693
Figure 15-16. GPACSEL2 Register....................................................................................................................................... 1694
Figure 15-17. GPACSEL3 Register....................................................................................................................................... 1695
Figure 15-18. GPACSEL4 Register....................................................................................................................................... 1696
Figure 15-19. GPALOCK Register......................................................................................................................................... 1697
Figure 15-20. GPACR Register..............................................................................................................................................1699
Figure 15-21. GPBCTRL Register......................................................................................................................................... 1701

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Figure 15-22. GPBQSEL1 Register.......................................................................................................................................1702

Figure 15-23. GPBQSEL2 Register.......................................................................................................................................1703
Figure 15-24. GPBMUX1 Register........................................................................................................................................ 1704
Figure 15-25. GPBMUX2 Register........................................................................................................................................ 1705
Figure 15-26. GPBDIR Register............................................................................................................................................ 1706
Figure 15-27. GPBPUD Register...........................................................................................................................................1708
Figure 15-28. GPBINV Register............................................................................................................................................ 1710
Figure 15-29. GPBODR Register.......................................................................................................................................... 1712
Figure 15-30. GPBAMSEL Register...................................................................................................................................... 1714
Figure 15-31. GPBGMUX1 Register......................................................................................................................................1716
Figure 15-32. GPBGMUX2 Register......................................................................................................................................1717
Figure 15-33. GPBCSEL1 Register....................................................................................................................................... 1718
Figure 15-34. GPBCSEL2 Register....................................................................................................................................... 1719
Figure 15-35. GPBCSEL3 Register....................................................................................................................................... 1720
Figure 15-36. GPBCSEL4 Register....................................................................................................................................... 1721
Figure 15-37. GPBLOCK Register.........................................................................................................................................1722
Figure 15-38. GPBCR Register............................................................................................................................................. 1724
Figure 15-39. GPCCTRL Register.........................................................................................................................................1726
Figure 15-40. GPCQSEL1 Register.......................................................................................................................................1727
Figure 15-41. GPCQSEL2 Register.......................................................................................................................................1728
Figure 15-42. GPCMUX1 Register........................................................................................................................................ 1729
Figure 15-43. GPCMUX2 Register........................................................................................................................................ 1730
Figure 15-44. GPCDIR Register............................................................................................................................................ 1731
Figure 15-45. GPCPUD Register...........................................................................................................................................1733
Figure 15-46. GPCINV Register............................................................................................................................................ 1735
Figure 15-47. GPCODR Register.......................................................................................................................................... 1737
Figure 15-48. GPCGMUX1 Register..................................................................................................................................... 1739
Figure 15-49. GPCGMUX2 Register..................................................................................................................................... 1740
Figure 15-50. GPCCSEL1 Register.......................................................................................................................................1741
Figure 15-51. GPCCSEL2 Register.......................................................................................................................................1742
Figure 15-52. GPCCSEL3 Register.......................................................................................................................................1743
Figure 15-53. GPCCSEL4 Register.......................................................................................................................................1744
Figure 15-54. GPCLOCK Register........................................................................................................................................ 1745
Figure 15-55. GPCCR Register............................................................................................................................................. 1747
Figure 15-56. GPDCTRL Register.........................................................................................................................................1749
Figure 15-57. GPDQSEL1 Register.......................................................................................................................................1750
Figure 15-58. GPDQSEL2 Register.......................................................................................................................................1752
Figure 15-59. GPDMUX1 Register........................................................................................................................................ 1754
Figure 15-60. GPDMUX2 Register........................................................................................................................................ 1756
Figure 15-61. GPDDIR Register............................................................................................................................................ 1758
Figure 15-62. GPDPUD Register...........................................................................................................................................1760
Figure 15-63. GPDINV Register............................................................................................................................................ 1762
Figure 15-64. GPDODR Register.......................................................................................................................................... 1764
Figure 15-65. GPDGMUX1 Register..................................................................................................................................... 1766
Figure 15-66. GPDGMUX2 Register..................................................................................................................................... 1768
Figure 15-67. GPDCSEL1 Register.......................................................................................................................................1770
Figure 15-68. GPDCSEL2 Register.......................................................................................................................................1771
Figure 15-69. GPDCSEL3 Register.......................................................................................................................................1772
Figure 15-70. GPDCSEL4 Register.......................................................................................................................................1773
Figure 15-71. GPDLOCK Register........................................................................................................................................ 1774
Figure 15-72. GPDCR Register............................................................................................................................................. 1776
Figure 15-73. GPECTRL Register......................................................................................................................................... 1778
Figure 15-74. GPEQSEL1 Register.......................................................................................................................................1779
Figure 15-75. GPEQSEL2 Register.......................................................................................................................................1781
Figure 15-76. GPEMUX1 Register........................................................................................................................................ 1783
Figure 15-77. GPEMUX2 Register........................................................................................................................................ 1785
Figure 15-78. GPEDIR Register............................................................................................................................................ 1787
Figure 15-79. GPEPUD Register...........................................................................................................................................1789
Figure 15-80. GPEINV Register............................................................................................................................................ 1791
Figure 15-81. GPEODR Register.......................................................................................................................................... 1793
Figure 15-82. GPEGMUX1 Register......................................................................................................................................1795

40 TMS320F2838x Real-Time Microcontrollers With Connectivity Manager SPRUII0E – MAY 2019 – REVISED SEPTEMBER 2023
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Figure 15-83. GPEGMUX2 Register......................................................................................................................................1797

Figure 15-84. GPECSEL1 Register....................................................................................................................................... 1799
Figure 15-85. GPECSEL2 Register....................................................................................................................................... 1800
Figure 15-86. GPECSEL3 Register....................................................................................................................................... 1801
Figure 15-87. GPECSEL4 Register....................................................................................................................................... 1802
Figure 15-88. GPELOCK Register.........................................................................................................................................1803
Figure 15-89. GPECR Register............................................................................................................................................. 1805
Figure 15-90. GPFCTRL Register......................................................................................................................................... 1807
Figure 15-91. GPFQSEL1 Register....................................................................................................................................... 1808
Figure 15-92. GPFMUX1 Register.........................................................................................................................................1810
Figure 15-93. GPFDIR Register............................................................................................................................................ 1812
Figure 15-94. GPFPUD Register........................................................................................................................................... 1814
Figure 15-95. GPFINV Register.............................................................................................................................................1816
Figure 15-96. GPFODR Register...........................................................................................................................................1818
Figure 15-97. GPFGMUX1 Register......................................................................................................................................1820
Figure 15-98. GPFCSEL1 Register....................................................................................................................................... 1821
Figure 15-99. GPFCSEL2 Register....................................................................................................................................... 1822
Figure 15-100. GPFLOCK Register.......................................................................................................................................1823
Figure 15-101. GPFCR Register........................................................................................................................................... 1825
Figure 15-102. GPADAT Register..........................................................................................................................................1829
Figure 15-103. GPASET Register..........................................................................................................................................1831
Figure 15-104. GPACLEAR Register.....................................................................................................................................1833
Figure 15-105. GPATOGGLE Register.................................................................................................................................. 1835
Figure 15-106. GPBDAT Register..........................................................................................................................................1837
Figure 15-107. GPBSET Register......................................................................................................................................... 1839
Figure 15-108. GPBCLEAR Register.................................................................................................................................... 1841
Figure 15-109. GPBTOGGLE Register..................................................................................................................................1843
Figure 15-110. GPCDAT Register..........................................................................................................................................1845
Figure 15-111. GPCSET Register..........................................................................................................................................1847
Figure 15-112. GPCCLEAR Register.....................................................................................................................................1849
Figure 15-113. GPCTOGGLE Register..................................................................................................................................1851
Figure 15-114. GPDDAT Register..........................................................................................................................................1853
Figure 15-115. GPDSET Register..........................................................................................................................................1855
Figure 15-116. GPDCLEAR Register.....................................................................................................................................1857
Figure 15-117. GPDTOGGLE Register..................................................................................................................................1859
Figure 15-118. GPEDAT Register..........................................................................................................................................1861
Figure 15-119. GPESET Register..........................................................................................................................................1863
Figure 15-120. GPECLEAR Register.................................................................................................................................... 1865
Figure 15-121. GPETOGGLE Register..................................................................................................................................1867
Figure 15-122. GPFDAT Register..........................................................................................................................................1869
Figure 15-123. GPFSET Register..........................................................................................................................................1871
Figure 15-124. GPFCLEAR Register.....................................................................................................................................1873
Figure 15-125. GPFTOGGLE Register..................................................................................................................................1875
Figure 15-126. GPADAT_R Register..................................................................................................................................... 1878
Figure 15-127. GPBDAT_R Register..................................................................................................................................... 1879
Figure 15-128. GPCDAT_R Register.....................................................................................................................................1880
Figure 15-129. GPDDAT_R Register.....................................................................................................................................1881
Figure 15-130. GPEDAT_R Register..................................................................................................................................... 1882
Figure 15-131. GPFDAT_R Register..................................................................................................................................... 1883
Figure 15-132. GPADAT Register..........................................................................................................................................1886
Figure 15-133. GPASET Register..........................................................................................................................................1888
Figure 15-134. GPACLEAR Register.....................................................................................................................................1890
Figure 15-135. GPATOGGLE Register.................................................................................................................................. 1892
Figure 15-136. GPBDAT Register..........................................................................................................................................1894
Figure 15-137. GPBSET Register......................................................................................................................................... 1896
Figure 15-138. GPBCLEAR Register.................................................................................................................................... 1898
Figure 15-139. GPBTOGGLE Register..................................................................................................................................1900
Figure 15-140. GPCDAT Register......................................................................................................................................... 1902
Figure 15-141. GPCSET Register......................................................................................................................................... 1904
Figure 15-142. GPCCLEAR Register.................................................................................................................................... 1906
Figure 15-143. GPCTOGGLE Register................................................................................................................................. 1908

SPRUII0E – MAY 2019 – REVISED SEPTEMBER 2023 TMS320F2838x Real-Time Microcontrollers With Connectivity Manager 41
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Figure 15-144. GPDDAT Register......................................................................................................................................... 1910

Figure 15-145. GPDSET Register......................................................................................................................................... 1912
Figure 15-146. GPDCLEAR Register.................................................................................................................................... 1914
Figure 15-147. GPDTOGGLE Register................................................................................................................................. 1916
Figure 15-148. GPEDAT Register..........................................................................................................................................1918
Figure 15-149. GPESET Register......................................................................................................................................... 1920
Figure 15-150. GPECLEAR Register.................................................................................................................................... 1922
Figure 15-151. GPETOGGLE Register..................................................................................................................................1924
Figure 15-152. GPFDAT Register..........................................................................................................................................1926
Figure 15-153. GPFSET Register..........................................................................................................................................1928
Figure 15-154. GPFCLEAR Register.....................................................................................................................................1930
Figure 15-155. GPFTOGGLE Register..................................................................................................................................1932
Figure 15-156. GPADAT_R Register..................................................................................................................................... 1935
Figure 15-157. GPBDAT_R Register..................................................................................................................................... 1936
Figure 15-158. GPCDAT_R Register.....................................................................................................................................1937
Figure 15-159. GPDDAT_R Register.....................................................................................................................................1938
Figure 15-160. GPEDAT_R Register..................................................................................................................................... 1939
Figure 15-161. GPFDAT_R Register..................................................................................................................................... 1940
Figure 15-162. GPGDAT_R Register.....................................................................................................................................1941
Figure 15-163. GPHDAT_R Register.....................................................................................................................................1942
Figure 16-1. CPU1_TO_CPU2 IPC Module...........................................................................................................................1951
Figure 16-2. CPUx_to_CM IPC Module.................................................................................................................................1952
Figure 16-3. CPU1TOCPU2IPCACK Register.......................................................................................................................1961
Figure 16-4. CPU2TOCPU1IPCSTS Register....................................................................................................................... 1963
Figure 16-5. CPU1TOCPU2IPCSET Register....................................................................................................................... 1968
Figure 16-6. CPU1TOCPU2IPCCLR Register.......................................................................................................................1972
Figure 16-7. CPU1TOCPU2IPCFLG Register....................................................................................................................... 1976
Figure 16-8. IPCCOUNTERL Register.................................................................................................................................. 1980
Figure 16-9. IPCCOUNTERH Register..................................................................................................................................1981
Figure 16-10. CPU1TOCPU2IPCSENDCOM Register..........................................................................................................1982
Figure 16-11. CPU1TOCPU2IPCSENDADDR Register........................................................................................................ 1983
Figure 16-12. CPU1TOCPU2IPCSENDDATA Register.........................................................................................................1984
Figure 16-13. CPU2TOCPU1IPCREPLY Register................................................................................................................ 1985
Figure 16-14. CPU2TOCPU1IPCRECVCOM Register..........................................................................................................1986
Figure 16-15. CPU2TOCPU1IPCRECVADDR Register........................................................................................................ 1987
Figure 16-16. CPU2TOCPU1IPCRECVDATA Register.........................................................................................................1988
Figure 16-17. CPU1TOCPU2IPCREPLY Register................................................................................................................ 1989
Figure 16-18. CPU2TOCPU1IPCBOOTSTS Register...........................................................................................................1990
Figure 16-19. CPU1TOCPU2IPCBOOTMODE Register....................................................................................................... 1991
Figure 16-20. PUMPREQUEST Register.............................................................................................................................. 1992
Figure 16-21. CPU2TOCPU1IPCACK Register.....................................................................................................................1995
Figure 16-22. CPU1TOCPU2IPCSTS Register..................................................................................................................... 1997
Figure 16-23. CPU2TOCPU1IPCSET Register..................................................................................................................... 2002
Figure 16-24. CPU2TOCPU1IPCCLR Register.....................................................................................................................2006
Figure 16-25. CPU2TOCPU1IPCFLG Register..................................................................................................................... 2010
Figure 16-26. IPCCOUNTERL Register................................................................................................................................ 2014
Figure 16-27. IPCCOUNTERH Register................................................................................................................................2015
Figure 16-28. CPU1TOCPU2IPCRECVCOM Register..........................................................................................................2016
Figure 16-29. CPU1TOCPU2IPCRECVADDR Register........................................................................................................ 2017
Figure 16-30. CPU1TOCPU2IPCRECVDATA Register.........................................................................................................2018
Figure 16-31. CPU2TOCPU1IPCREPLY Register................................................................................................................ 2019
Figure 16-32. CPU2TOCPU1IPCSENDCOM Register..........................................................................................................2020
Figure 16-33. CPU2TOCPU1IPCSENDADDR Register........................................................................................................2021
Figure 16-34. CPU2TOCPU1IPCSENDDATA Register.........................................................................................................2022
Figure 16-35. CPU1TOCPU2IPCREPLY Register................................................................................................................ 2023
Figure 16-36. CPU2TOCPU1IPCBOOTSTS Register...........................................................................................................2024
Figure 16-37. CPU1TOCPU2IPCBOOTMODE Register....................................................................................................... 2025
Figure 16-38. PUMPREQUEST Register.............................................................................................................................. 2026
Figure 16-39. CPU1TOCMIPCACK Register.........................................................................................................................2029
Figure 16-40. CMTOCPU1IPCSTS Register......................................................................................................................... 2031
Figure 16-41. CPU1TOCMIPCSET Register......................................................................................................................... 2036

42 TMS320F2838x Real-Time Microcontrollers With Connectivity Manager SPRUII0E – MAY 2019 – REVISED SEPTEMBER 2023
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Figure 16-42. CPU1TOCMIPCCLR Register.........................................................................................................................2040

Figure 16-43. CPU1TOCMIPCFLG Register......................................................................................................................... 2044
Figure 16-44. IPCCOUNTERL Register................................................................................................................................ 2048
Figure 16-45. IPCCOUNTERH Register................................................................................................................................2049
Figure 16-46. CPU1TOCMIPCSENDCOM Register..............................................................................................................2050
Figure 16-47. CPU1TOCMIPCSENDADDR Register............................................................................................................2051
Figure 16-48. CPU1TOCMIPCSENDDATA Register.............................................................................................................2052
Figure 16-49. CMTOCPU1IPCREPLY Register.................................................................................................................... 2053
Figure 16-50. CMTOCPU1IPCRECVCOM Register..............................................................................................................2054
Figure 16-51. CMTOCPU1IPCRECVADDR Register............................................................................................................ 2055
Figure 16-52. CMTOCPU1IPCRECVDATA Register.............................................................................................................2056
Figure 16-53. CPU1TOCMIPCREPLY Register.................................................................................................................... 2057
Figure 16-54. CMTOCPU1IPCBOOTSTS Register...............................................................................................................2058
Figure 16-55. CPU1TOCMIPCBOOTMODE Register........................................................................................................... 2059
Figure 16-56. CMTOCPU1IPCACK Register.........................................................................................................................2062
Figure 16-57. CPU1TOCMIPCSTS Register......................................................................................................................... 2064
Figure 16-58. CMTOCPU1IPCSET Register......................................................................................................................... 2069
Figure 16-59. CMTOCPU1IPCCLR Register.........................................................................................................................2073
Figure 16-60. CMTOCPU1IPCFLG Register......................................................................................................................... 2077
Figure 16-61. IPCCOUNTERL Register................................................................................................................................ 2081
Figure 16-62. IPCCOUNTERH Register................................................................................................................................2082
Figure 16-63. CPU1TOCMIPCRECVCOM Register..............................................................................................................2083
Figure 16-64. CPU1TOCMIPCRECVADDR Register............................................................................................................ 2084
Figure 16-65. CPU1TOCMIPCRECVDATA Register.............................................................................................................2085
Figure 16-66. CMTOCPU1IPCREPLY Register.................................................................................................................... 2086
Figure 16-67. CMTOCPU1IPCSENDCOM Register..............................................................................................................2087
Figure 16-68. CMTOCPU1IPCSENDADDR Register............................................................................................................2088
Figure 16-69. CMTOCPU1IPCSENDDATA Register.............................................................................................................2089
Figure 16-70. CPU1TOCMIPCREPLY Register.................................................................................................................... 2090
Figure 16-71. CMTOCPU1IPCBOOTSTS Register...............................................................................................................2091
Figure 16-72. CPU1TOCMIPCBOOTMODE Register........................................................................................................... 2092
Figure 16-73. PUMPREQUEST Register.............................................................................................................................. 2093
Figure 16-74. CPU2TOCMIPCACK Register.........................................................................................................................2096
Figure 16-75. CMTOCPU2IPCSTS Register......................................................................................................................... 2098
Figure 16-76. CPU2TOCMIPCSET Register......................................................................................................................... 2103
Figure 16-77. CPU2TOCMIPCCLR Register.........................................................................................................................2107
Figure 16-78. CPU2TOCMIPCFLG Register......................................................................................................................... 2111
Figure 16-79. IPCCOUNTERL Register.................................................................................................................................2115
Figure 16-80. IPCCOUNTERH Register................................................................................................................................ 2116
Figure 16-81. CPU2TOCMIPCSENDCOM Register..............................................................................................................2117
Figure 16-82. CPU2TOCMIPCSENDADDR Register............................................................................................................ 2118
Figure 16-83. CPU2TOCMIPCSENDDATA Register............................................................................................................. 2119
Figure 16-84. CMTOCPU2IPCREPLY Register.................................................................................................................... 2120
Figure 16-85. CMTOCPU2IPCRECVCOM Register..............................................................................................................2121
Figure 16-86. CMTOCPU2IPCRECVADDR Register............................................................................................................ 2122
Figure 16-87. CMTOCPU2IPCRECVDATA Register.............................................................................................................2123
Figure 16-88. CPU2TOCMIPCREPLY Register.................................................................................................................... 2124
Figure 16-89. CMTOCPU2IPCACK Register.........................................................................................................................2127
Figure 16-90. CPU2TOCMIPCSTS Register......................................................................................................................... 2129
Figure 16-91. CMTOCPU2IPCSET Register......................................................................................................................... 2134
Figure 16-92. CMTOCPU2IPCCLR Register.........................................................................................................................2138
Figure 16-93. CMTOCPU2IPCFLG Register......................................................................................................................... 2142
Figure 16-94. IPCCOUNTERL Register................................................................................................................................ 2146
Figure 16-95. IPCCOUNTERH Register................................................................................................................................2147
Figure 16-96. CPU2TOCMIPCRECVCOM Register..............................................................................................................2148
Figure 16-97. CPU2TOCMIPCRECVADDR Register............................................................................................................ 2149
Figure 16-98. CPU2TOCMIPCRECVDATA Register.............................................................................................................2150
Figure 16-99. CMTOCPU2IPCREPLY Register.................................................................................................................... 2151
Figure 16-100. CMTOCPU2IPCSENDCOM Register............................................................................................................2152
Figure 16-101. CMTOCPU2IPCSENDADDR Register..........................................................................................................2153
Figure 16-102. CMTOCPU2IPCSENDDATA Register...........................................................................................................2154

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Figure 16-103. CPU2TOCMIPCREPLY Register.................................................................................................................. 2155

Figure 17-1. Input X-BAR...................................................................................................................................................... 2163
Figure 17-2. ePWM X-BAR Architecture - Single Output...................................................................................................... 2166
Figure 17-3. CLB X-BAR Architecture - Single Output.......................................................................................................... 2168
Figure 17-4. GPIO to CLB Tile Connections..........................................................................................................................2169
Figure 17-5. GPIO Output X-BAR Architecture..................................................................................................................... 2171
Figure 17-6. X-BAR Input Sources........................................................................................................................................ 2175
Figure 17-7. INPUT1SELECT Register................................................................................................................................. 2179
Figure 17-8. INPUT2SELECT Register................................................................................................................................. 2180
Figure 17-9. INPUT3SELECT Register................................................................................................................................. 2181
Figure 17-10. INPUT4SELECT Register............................................................................................................................... 2182
Figure 17-11. INPUT5SELECT Register................................................................................................................................2183
Figure 17-12. INPUT6SELECT Register............................................................................................................................... 2184
Figure 17-13. INPUT7SELECT Register............................................................................................................................... 2185
Figure 17-14. INPUT8SELECT Register............................................................................................................................... 2186
Figure 17-15. INPUT9SELECT Register............................................................................................................................... 2187
Figure 17-16. INPUT10SELECT Register............................................................................................................................. 2188
Figure 17-17. INPUT11SELECT Register..............................................................................................................................2189
Figure 17-18. INPUT12SELECT Register............................................................................................................................. 2190
Figure 17-19. INPUT13SELECT Register............................................................................................................................. 2191
Figure 17-20. INPUT14SELECT Register............................................................................................................................. 2192
Figure 17-21. INPUT15SELECT Register............................................................................................................................. 2193
Figure 17-22. INPUT16SELECT Register............................................................................................................................. 2194
Figure 17-23. INPUTSELECTLOCK Register....................................................................................................................... 2195
Figure 17-24. XBARFLG1 Register....................................................................................................................................... 2198
Figure 17-25. XBARFLG2 Register....................................................................................................................................... 2203
Figure 17-26. XBARFLG3 Register....................................................................................................................................... 2208
Figure 17-27. XBARFLG4 Register....................................................................................................................................... 2213
Figure 17-28. XBARCLR1 Register....................................................................................................................................... 2218
Figure 17-29. XBARCLR2 Register....................................................................................................................................... 2221
Figure 17-30. XBARCLR3 Register....................................................................................................................................... 2224
Figure 17-31. XBARCLR4 Register....................................................................................................................................... 2227
Figure 17-32. TRIP4MUX0TO15CFG Register..................................................................................................................... 2232
Figure 17-33. TRIP4MUX16TO31CFG Register................................................................................................................... 2235
Figure 17-34. TRIP5MUX0TO15CFG Register..................................................................................................................... 2238
Figure 17-35. TRIP5MUX16TO31CFG Register................................................................................................................... 2241
Figure 17-36. TRIP7MUX0TO15CFG Register..................................................................................................................... 2244
Figure 17-37. TRIP7MUX16TO31CFG Register................................................................................................................... 2247
Figure 17-38. TRIP8MUX0TO15CFG Register..................................................................................................................... 2250
Figure 17-39. TRIP8MUX16TO31CFG Register................................................................................................................... 2253
Figure 17-40. TRIP9MUX0TO15CFG Register..................................................................................................................... 2256
Figure 17-41. TRIP9MUX16TO31CFG Register................................................................................................................... 2259
Figure 17-42. TRIP10MUX0TO15CFG Register................................................................................................................... 2262
Figure 17-43. TRIP10MUX16TO31CFG Register................................................................................................................. 2265
Figure 17-44. TRIP11MUX0TO15CFG Register....................................................................................................................2268
Figure 17-45. TRIP11MUX16TO31CFG Register..................................................................................................................2271
Figure 17-46. TRIP12MUX0TO15CFG Register................................................................................................................... 2274
Figure 17-47. TRIP12MUX16TO31CFG Register................................................................................................................. 2277
Figure 17-48. TRIP4MUXENABLE Register..........................................................................................................................2280
Figure 17-49. TRIP5MUXENABLE Register..........................................................................................................................2285
Figure 17-50. TRIP7MUXENABLE Register..........................................................................................................................2290
Figure 17-51. TRIP8MUXENABLE Register..........................................................................................................................2295
Figure 17-52. TRIP9MUXENABLE Register..........................................................................................................................2300
Figure 17-53. TRIP10MUXENABLE Register........................................................................................................................2305
Figure 17-54. TRIP11MUXENABLE Register........................................................................................................................ 2310
Figure 17-55. TRIP12MUXENABLE Register........................................................................................................................2315
Figure 17-56. TRIPOUTINV Register.................................................................................................................................... 2320
Figure 17-57. TRIPLOCK Register........................................................................................................................................ 2322
Figure 17-58. AUXSIG0MUX0TO15CFG Register................................................................................................................ 2325
Figure 17-59. AUXSIG0MUX16TO31CFG Register.............................................................................................................. 2328
Figure 17-60. AUXSIG1MUX0TO15CFG Register................................................................................................................ 2331

44 TMS320F2838x Real-Time Microcontrollers With Connectivity Manager SPRUII0E – MAY 2019 – REVISED SEPTEMBER 2023
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Figure 17-61. AUXSIG1MUX16TO31CFG Register.............................................................................................................. 2334

Figure 17-62. AUXSIG2MUX0TO15CFG Register................................................................................................................ 2337
Figure 17-63. AUXSIG2MUX16TO31CFG Register.............................................................................................................. 2340
Figure 17-64. AUXSIG3MUX0TO15CFG Register................................................................................................................ 2343
Figure 17-65. AUXSIG3MUX16TO31CFG Register.............................................................................................................. 2346
Figure 17-66. AUXSIG4MUX0TO15CFG Register................................................................................................................ 2349
Figure 17-67. AUXSIG4MUX16TO31CFG Register.............................................................................................................. 2352
Figure 17-68. AUXSIG5MUX0TO15CFG Register................................................................................................................ 2355
Figure 17-69. AUXSIG5MUX16TO31CFG Register.............................................................................................................. 2358
Figure 17-70. AUXSIG6MUX0TO15CFG Register................................................................................................................ 2361
Figure 17-71. AUXSIG6MUX16TO31CFG Register.............................................................................................................. 2364
Figure 17-72. AUXSIG7MUX0TO15CFG Register................................................................................................................ 2367
Figure 17-73. AUXSIG7MUX16TO31CFG Register.............................................................................................................. 2370
Figure 17-74. AUXSIG0MUXENABLE Register.................................................................................................................... 2373
Figure 17-75. AUXSIG1MUXENABLE Register.................................................................................................................... 2378
Figure 17-76. AUXSIG2MUXENABLE Register.................................................................................................................... 2383
Figure 17-77. AUXSIG3MUXENABLE Register.................................................................................................................... 2388
Figure 17-78. AUXSIG4MUXENABLE Register.................................................................................................................... 2393
Figure 17-79. AUXSIG5MUXENABLE Register.................................................................................................................... 2398
Figure 17-80. AUXSIG6MUXENABLE Register.................................................................................................................... 2403
Figure 17-81. AUXSIG7MUXENABLE Register.................................................................................................................... 2408
Figure 17-82. AUXSIGOUTINV Register...............................................................................................................................2413
Figure 17-83. AUXSIGLOCK Register...................................................................................................................................2415
Figure 17-84. OUTPUT1MUX0TO15CFG Register...............................................................................................................2418
Figure 17-85. OUTPUT1MUX16TO31CFG Register.............................................................................................................2421
Figure 17-86. OUTPUT2MUX0TO15CFG Register...............................................................................................................2424
Figure 17-87. OUTPUT2MUX16TO31CFG Register.............................................................................................................2427
Figure 17-88. OUTPUT3MUX0TO15CFG Register...............................................................................................................2430
Figure 17-89. OUTPUT3MUX16TO31CFG Register.............................................................................................................2433
Figure 17-90. OUTPUT4MUX0TO15CFG Register...............................................................................................................2436
Figure 17-91. OUTPUT4MUX16TO31CFG Register.............................................................................................................2439
Figure 17-92. OUTPUT5MUX0TO15CFG Register...............................................................................................................2442
Figure 17-93. OUTPUT5MUX16TO31CFG Register.............................................................................................................2445
Figure 17-94. OUTPUT6MUX0TO15CFG Register...............................................................................................................2448
Figure 17-95. OUTPUT6MUX16TO31CFG Register.............................................................................................................2451
Figure 17-96. OUTPUT7MUX0TO15CFG Register...............................................................................................................2454
Figure 17-97. OUTPUT7MUX16TO31CFG Register.............................................................................................................2457
Figure 17-98. OUTPUT8MUX0TO15CFG Register...............................................................................................................2460
Figure 17-99. OUTPUT8MUX16TO31CFG Register.............................................................................................................2463
Figure 17-100. OUTPUT1MUXENABLE Register................................................................................................................. 2466
Figure 17-101. OUTPUT2MUXENABLE Register................................................................................................................. 2471
Figure 17-102. OUTPUT3MUXENABLE Register................................................................................................................. 2476
Figure 17-103. OUTPUT4MUXENABLE Register................................................................................................................. 2481
Figure 17-104. OUTPUT5MUXENABLE Register................................................................................................................. 2486
Figure 17-105. OUTPUT6MUXENABLE Register................................................................................................................. 2491
Figure 17-106. OUTPUT7MUXENABLE Register................................................................................................................. 2496
Figure 17-107. OUTPUT8MUXENABLE Register................................................................................................................. 2501
Figure 17-108. OUTPUTLATCH Register..............................................................................................................................2506
Figure 17-109. OUTPUTLATCHCLR Register.......................................................................................................................2508
Figure 17-110. OUTPUTLATCHFRC Register.......................................................................................................................2510
Figure 17-111. OUTPUTLATCHENABLE Register................................................................................................................ 2512
Figure 17-112. OUTPUTINV Register....................................................................................................................................2514
Figure 17-113. OUTPUTLOCK Register................................................................................................................................2516
Figure 18-1. F2838x Block Diagram...................................................................................................................................... 2524
Figure 19-1. Analog Subsystem Block Diagram (337-Ball ZWT)...........................................................................................2527
Figure 19-2. Analog Subsystem Block Diagram (176-Pin PTP)............................................................................................ 2528
Figure 19-3. INTOSC1TRIM Register....................................................................................................................................2532
Figure 19-4. INTOSC2TRIM Register....................................................................................................................................2533
Figure 19-5. TSNSCTL Register............................................................................................................................................2534
Figure 19-6. LOCK Register.................................................................................................................................................. 2535
Figure 19-7. ANAREFTRIMA Register.................................................................................................................................. 2536

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Figure 19-8. ANAREFTRIMB Register.................................................................................................................................. 2537

Figure 19-9. ANAREFTRIMC Register.................................................................................................................................. 2538
Figure 19-10. ANAREFTRIMD Register................................................................................................................................ 2539
Figure 20-1. ADC Module Block Diagram..............................................................................................................................2544
Figure 20-2. SOC Block Diagram.......................................................................................................................................... 2549
Figure 20-3. Single-Ended Input Model................................................................................................................................. 2551
Figure 20-4. Differential Input Model......................................................................................................................................2551
Figure 20-5. Round Robin Priority Example.......................................................................................................................... 2556
Figure 20-6. High Priority Example........................................................................................................................................2557
Figure 20-7. Burst Priority Example.......................................................................................................................................2559
Figure 20-8. ADC EOC Interrupts..........................................................................................................................................2560
Figure 20-9. ADC PPB Block Diagram.................................................................................................................................. 2563
Figure 20-10. ADC PPB Interrupt Event................................................................................................................................ 2565
Figure 20-11. Opens/Shorts Detection Circuit....................................................................................................................... 2567
Figure 20-12. Input Circuit Equivalent with OSDETECT Enabled......................................................................................... 2568
Figure 20-13. ADC Timings for 12-bit Mode in Early Interrupt Mode.....................................................................................2572
Figure 20-14. ADC Timings for 12-bit Mode in Late Interrupt Mode...................................................................................... 2573
Figure 20-15. ADC Timings for 16-bit Mode in Early Interrupt Mode.....................................................................................2574
Figure 20-16. ADC Timings for 16-bit Mode in Late Interrupt Mode (SYSCLK Cycles).........................................................2575
Figure 20-17. Example: Basic Synchronous Operation.........................................................................................................2577
Figure 20-18. Example: Synchronous Operation with Multiple Trigger Sources................................................................... 2578
Figure 20-19. Example: Synchronous Operation with Uneven SOC Numbers..................................................................... 2579
Figure 20-20. Example: Asynchronous Operation with Uneven SOC Numbers – Trigger Overflow..................................... 2579
Figure 20-21. Example: Asynchronous Operation with Different Resolutions....................................................................... 2580
Figure 20-22. Example: Synchronous Operation with Different Resolutions......................................................................... 2580
Figure 20-23. Example: Synchronous Equivalent Operation with Non-Overlapping Conversions........................................ 2581
Figure 20-24. ADC Reference System.................................................................................................................................. 2584
Figure 20-25. ADC Shared Reference System......................................................................................................................2585
Figure 20-26. ADCCTL1 Register..........................................................................................................................................2597
Figure 20-27. ADCCTL2 Register..........................................................................................................................................2599
Figure 20-28. ADCBURSTCTL Register............................................................................................................................... 2600
Figure 20-29. ADCINTFLG Register......................................................................................................................................2602
Figure 20-30. ADCINTFLGCLR Register.............................................................................................................................. 2604
Figure 20-31. ADCINTOVF Register..................................................................................................................................... 2605
Figure 20-32. ADCINTOVFCLR Register.............................................................................................................................. 2606
Figure 20-33. ADCINTSEL1N2 Register............................................................................................................................... 2607
Figure 20-34. ADCINTSEL3N4 Register............................................................................................................................... 2609
Figure 20-35. ADCSOCPRICTL Register.............................................................................................................................. 2611
Figure 20-36. ADCINTSOCSEL1 Register............................................................................................................................ 2613
Figure 20-37. ADCINTSOCSEL2 Register............................................................................................................................ 2615
Figure 20-38. ADCSOCFLG1 Register..................................................................................................................................2617
Figure 20-39. ADCSOCFRC1 Register................................................................................................................................. 2621
Figure 20-40. ADCSOCOVF1 Register................................................................................................................................. 2626
Figure 20-41. ADCSOCOVFCLR1 Register.......................................................................................................................... 2629
Figure 20-42. ADCSOC0CTL Register..................................................................................................................................2632
Figure 20-43. ADCSOC1CTL Register..................................................................................................................................2635
Figure 20-44. ADCSOC2CTL Register..................................................................................................................................2638
Figure 20-45. ADCSOC3CTL Register..................................................................................................................................2641
Figure 20-46. ADCSOC4CTL Register..................................................................................................................................2644
Figure 20-47. ADCSOC5CTL Register..................................................................................................................................2647
Figure 20-48. ADCSOC6CTL Register..................................................................................................................................2650
Figure 20-49. ADCSOC7CTL Register..................................................................................................................................2653
Figure 20-50. ADCSOC8CTL Register..................................................................................................................................2656
Figure 20-51. ADCSOC9CTL Register..................................................................................................................................2659
Figure 20-52. ADCSOC10CTL Register................................................................................................................................2662
Figure 20-53. ADCSOC11CTL Register................................................................................................................................ 2665
Figure 20-54. ADCSOC12CTL Register................................................................................................................................2668
Figure 20-55. ADCSOC13CTL Register................................................................................................................................2671
Figure 20-56. ADCSOC14CTL Register................................................................................................................................2674
Figure 20-57. ADCSOC15CTL Register................................................................................................................................2677
Figure 20-58. ADCEVTSTAT Register...................................................................................................................................2680

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Figure 20-59. ADCEVTCLR Register.................................................................................................................................... 2683

Figure 20-60. ADCEVTSEL Register.....................................................................................................................................2685
Figure 20-61. ADCEVTINTSEL Register...............................................................................................................................2687
Figure 20-62. ADCOSDETECT Register...............................................................................................................................2689
Figure 20-63. ADCCOUNTER Register.................................................................................................................................2690
Figure 20-64. ADCREV Register........................................................................................................................................... 2691
Figure 20-65. ADCOFFTRIM Register.................................................................................................................................. 2692
Figure 20-66. ADCPPB1CONFIG Register........................................................................................................................... 2693
Figure 20-67. ADCPPB1STAMP Register............................................................................................................................. 2695
Figure 20-68. ADCPPB1OFFCAL Register........................................................................................................................... 2696
Figure 20-69. ADCPPB1OFFREF Register...........................................................................................................................2697
Figure 20-70. ADCPPB1TRIPHI Register............................................................................................................................. 2698
Figure 20-71. ADCPPB1TRIPLO Register............................................................................................................................ 2699
Figure 20-72. ADCPPB2CONFIG Register........................................................................................................................... 2700
Figure 20-73. ADCPPB2STAMP Register............................................................................................................................. 2702
Figure 20-74. ADCPPB2OFFCAL Register........................................................................................................................... 2703
Figure 20-75. ADCPPB2OFFREF Register...........................................................................................................................2704
Figure 20-76. ADCPPB2TRIPHI Register............................................................................................................................. 2705
Figure 20-77. ADCPPB2TRIPLO Register............................................................................................................................ 2706
Figure 20-78. ADCPPB3CONFIG Register........................................................................................................................... 2707
Figure 20-79. ADCPPB3STAMP Register............................................................................................................................. 2709
Figure 20-80. ADCPPB3OFFCAL Register........................................................................................................................... 2710
Figure 20-81. ADCPPB3OFFREF Register........................................................................................................................... 2711
Figure 20-82. ADCPPB3TRIPHI Register............................................................................................................................. 2712
Figure 20-83. ADCPPB3TRIPLO Register............................................................................................................................ 2713
Figure 20-84. ADCPPB4CONFIG Register........................................................................................................................... 2714
Figure 20-85. ADCPPB4STAMP Register............................................................................................................................. 2716
Figure 20-86. ADCPPB4OFFCAL Register........................................................................................................................... 2717
Figure 20-87. ADCPPB4OFFREF Register...........................................................................................................................2718
Figure 20-88. ADCPPB4TRIPHI Register............................................................................................................................. 2719
Figure 20-89. ADCPPB4TRIPLO Register............................................................................................................................ 2720
Figure 20-90. ADCINTCYCLE Register.................................................................................................................................2721
Figure 20-91. ADCINLTRIM1 Register.................................................................................................................................. 2722
Figure 20-92. ADCINLTRIM2 Register.................................................................................................................................. 2723
Figure 20-93. ADCINLTRIM3 Register.................................................................................................................................. 2724
Figure 20-94. ADCINLTRIM4 Register.................................................................................................................................. 2725
Figure 20-95. ADCINLTRIM5 Register.................................................................................................................................. 2726
Figure 20-96. ADCINLTRIM6 Register.................................................................................................................................. 2727
Figure 20-97. ADCRESULT0 Register...................................................................................................................................2730
Figure 20-98. ADCRESULT1 Register...................................................................................................................................2731
Figure 20-99. ADCRESULT2 Register...................................................................................................................................2732
Figure 20-100. ADCRESULT3 Register.................................................................................................................................2733
Figure 20-101. ADCRESULT4 Register.................................................................................................................................2734
Figure 20-102. ADCRESULT5 Register.................................................................................................................................2735
Figure 20-103. ADCRESULT6 Register.................................................................................................................................2736
Figure 20-104. ADCRESULT7 Register.................................................................................................................................2737
Figure 20-105. ADCRESULT8 Register.................................................................................................................................2738
Figure 20-106. ADCRESULT9 Register.................................................................................................................................2739
Figure 20-107. ADCRESULT10 Register...............................................................................................................................2740
Figure 20-108. ADCRESULT11 Register...............................................................................................................................2741
Figure 20-109. ADCRESULT12 Register...............................................................................................................................2742
Figure 20-110. ADCRESULT13 Register...............................................................................................................................2743
Figure 20-111. ADCRESULT14 Register............................................................................................................................... 2744
Figure 20-112. ADCRESULT15 Register...............................................................................................................................2745
Figure 20-113. ADCPPB1RESULT Register..........................................................................................................................2746
Figure 20-114. ADCPPB2RESULT Register..........................................................................................................................2747
Figure 20-115. ADCPPB3RESULT Register..........................................................................................................................2748
Figure 20-116. ADCPPB4RESULT Register..........................................................................................................................2749
Figure 21-1. DAC Module Block Diagram..............................................................................................................................2757
Figure 21-2. DACREV Register............................................................................................................................................. 2762
Figure 21-3. DACCTL Register..............................................................................................................................................2763

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Figure 21-4. DACVALA Register............................................................................................................................................2764

Figure 21-5. DACVALS Register............................................................................................................................................2765
Figure 21-6. DACOUTEN Register........................................................................................................................................2766
Figure 21-7. DACLOCK Register...........................................................................................................................................2767
Figure 21-8. DACTRIM Register............................................................................................................................................2768
Figure 22-1. CMPSS Module Block Diagram........................................................................................................................ 2771
Figure 22-2. Comparator Block Diagram............................................................................................................................... 2771
Figure 22-3. Reference DAC Block Diagram.........................................................................................................................2772
Figure 22-4. Ramp Generator Block Diagram....................................................................................................................... 2774
Figure 22-5. Ramp Generator Behavior................................................................................................................................ 2775
Figure 22-6. Digital Filter Behavior........................................................................................................................................ 2776
Figure 22-7. COMPCTL Register.......................................................................................................................................... 2783
Figure 22-8. COMPHYSCTL Register................................................................................................................................... 2785
Figure 22-9. COMPSTS Register.......................................................................................................................................... 2786
Figure 22-10. COMPSTSCLR Register................................................................................................................................. 2787
Figure 22-11. COMPDACCTL Register................................................................................................................................. 2788
Figure 22-12. DACHVALS Register....................................................................................................................................... 2790
Figure 22-13. DACHVALA Register....................................................................................................................................... 2791
Figure 22-14. RAMPMAXREFA Register.............................................................................................................................. 2792
Figure 22-15. RAMPMAXREFS Register.............................................................................................................................. 2793
Figure 22-16. RAMPDECVALA Register............................................................................................................................... 2794
Figure 22-17. RAMPDECVALS Register............................................................................................................................... 2795
Figure 22-18. RAMPSTS Register.........................................................................................................................................2796
Figure 22-19. DACLVALS Register........................................................................................................................................2797
Figure 22-20. DACLVALA Register........................................................................................................................................2798
Figure 22-21. RAMPDLYA Register.......................................................................................................................................2799
Figure 22-22. RAMPDLYS Register.......................................................................................................................................2800
Figure 22-23. CTRIPLFILCTL Register................................................................................................................................. 2801
Figure 22-24. CTRIPLFILCLKCTL Register.......................................................................................................................... 2802
Figure 22-25. CTRIPHFILCTL Register.................................................................................................................................2803
Figure 22-26. CTRIPHFILCLKCTL Register..........................................................................................................................2804
Figure 22-27. COMPLOCK Register..................................................................................................................................... 2805
Figure 23-1. F2838x Block Diagram...................................................................................................................................... 2810
Figure 24-1. Capture and APWM Modes of Operation..........................................................................................................2819
Figure 24-2. Counter Compare and PRD Effects on the eCAP Output in APWM Mode....................................................... 2820
Figure 24-3. eCAP Block Diagram.........................................................................................................................................2821
Figure 24-4. Event Prescale Control......................................................................................................................................2822
Figure 24-5. Prescale Function Waveforms...........................................................................................................................2822
Figure 24-6. Details of the Continuous/One-shot Block.........................................................................................................2824
Figure 24-7. Details of the Counter and Synchronization Block............................................................................................ 2825
Figure 24-8. eCAP Synchronization Scheme........................................................................................................................ 2825
Figure 24-9. Interrupts in eCAP Module................................................................................................................................ 2827
Figure 24-10. PWM Waveform Details Of APWM Mode Operation.......................................................................................2828
Figure 24-11. Time-Base Frequency and Period Calculation................................................................................................ 2829
Figure 24-12. Capture Sequence for Absolute Time-stamp and Rising-Edge Detect........................................................... 2830
Figure 24-13. Capture Sequence for Absolute Time-stamp with Rising- and Falling-Edge Detect....................................... 2831
Figure 24-14. Capture Sequence for Delta Mode Time-stamp and Rising Edge Detect....................................................... 2832
Figure 24-15. Capture Sequence for Delta Mode Time-stamp with Rising- and Falling-Edge Detect...................................2833
Figure 24-16. PWM Waveform Details of APWM Mode Operation....................................................................................... 2834
Figure 24-17. TSCTR Register.............................................................................................................................................. 2839
Figure 24-18. CTRPHS Register........................................................................................................................................... 2840
Figure 24-19. CAP1 Register.................................................................................................................................................2841
Figure 24-20. CAP2 Register.................................................................................................................................................2842
Figure 24-21. CAP3 Register.................................................................................................................................................2843
Figure 24-22. CAP4 Register.................................................................................................................................................2844
Figure 24-23. ECCTL0 Register............................................................................................................................................ 2845
Figure 24-24. ECCTL1 Register............................................................................................................................................ 2846
Figure 24-25. ECCTL2 Register............................................................................................................................................ 2848
Figure 24-26. ECEINT Register.............................................................................................................................................2850
Figure 24-27. ECFLG Register.............................................................................................................................................. 2852
Figure 24-28. ECCLR Register..............................................................................................................................................2853

48 TMS320F2838x Real-Time Microcontrollers With Connectivity Manager SPRUII0E – MAY 2019 – REVISED SEPTEMBER 2023
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Figure 24-29. ECFRC Register..............................................................................................................................................2854

Figure 24-30. ECAPSYNCINSEL Register............................................................................................................................2855
Figure 25-1. HRCAP Operations Block Diagram...................................................................................................................2862
Figure 25-2. HRCAP Calibration............................................................................................................................................2863
Figure 25-3. HRCTL Register................................................................................................................................................ 2868
Figure 25-4. HRINTEN Register............................................................................................................................................ 2869
Figure 25-5. HRFLG Register................................................................................................................................................2870
Figure 25-6. HRCLR Register................................................................................................................................................2871
Figure 25-7. HRFRC Register............................................................................................................................................... 2872
Figure 25-8. HRCALPRD Register........................................................................................................................................ 2873
Figure 25-9. HRSYSCLKCTR Register................................................................................................................................. 2874
Figure 25-10. HRSYSCLKCAP Register............................................................................................................................... 2875
Figure 25-11. HRCLKCTR Register.......................................................................................................................................2876
Figure 25-12. HRCLKCAP Register...................................................................................................................................... 2877
Figure 26-1. Multiple ePWM Modules....................................................................................................................................2883
Figure 26-2. Submodules and Signal Connections for an ePWM Module.............................................................................2884
Figure 26-3. ePWM Modules and Critical Internal Signal Interconnects............................................................................... 2886
Figure 26-4. Time-Base Submodule...................................................................................................................................... 2889
Figure 26-5. Time-Base Submodule Signals and Registers.................................................................................................. 2890
Figure 26-6. Time-Base Frequency and Period.....................................................................................................................2892
Figure 26-7. Time-Base Counter Synchronization Scheme...................................................................................................2894
Figure 26-8. ePWM External SYNC Output...........................................................................................................................2895
Figure 26-9. Time-Base Up-Count Mode Waveforms............................................................................................................2898
Figure 26-10. Time-Base Down-Count Mode Waveforms..................................................................................................... 2899
Figure 26-11. Time-Base Up-Down-Count Waveforms, TBCTL[PHSDIR = 0] Count Down On Synchronization Event....... 2899
Figure 26-12. Time-Base Up-Down Count Waveforms, TBCTL[PHSDIR = 1] Count Up On Synchronization Event............2900
Figure 26-13. Global Load: Signals and Registers................................................................................................................ 2901
Figure 26-14. One-Shot Sync Mode...................................................................................................................................... 2902
Figure 26-15. Counter-Compare Submodule........................................................................................................................ 2903
Figure 26-16. Detailed View of the Counter-Compare Submodule........................................................................................2904
Figure 26-17. Counter-Compare Event Waveforms in Up-Count Mode................................................................................ 2907
Figure 26-18. Counter-Compare Events in Down-Count Mode.............................................................................................2907
Figure 26-19. Counter-Compare Events In Up-Down-Count Mode, TBCTL[PHSDIR = 0] Count Down On
Synchronization Event....................................................................................................................................................... 2908
Figure 26-20. Counter-Compare Events In Up-Down-Count Mode, TBCTL[PHSDIR = 1] Count Up On Synchronization
Event.................................................................................................................................................................................. 2908
Figure 26-21. Action-Qualifier Submodule.............................................................................................................................2909
Figure 26-22. Action-Qualifier Submodule Inputs and Outputs............................................................................................. 2910
Figure 26-23. Possible Action-Qualifier Actions for EPWMxA and EPWMxB Outputs.......................................................... 2911
Figure 26-24. AQCTL[SHDWAQAMODE]............................................................................................................................. 2914
Figure 26-25. AQCTL[SHDWAQBMODE]............................................................................................................................. 2914
Figure 26-26. Up-Down Count Mode Symmetrical Waveform...............................................................................................2916
Figure 26-27. Up, Single Edge Asymmetric Waveform, with Independent Modulation on EPWMxA and EPWMxB—
Active High......................................................................................................................................................................... 2917
Figure 26-28. Up, Single Edge Asymmetric Waveform with Independent Modulation on EPWMxA and EPWMxB—
Active Low..........................................................................................................................................................................2918
Figure 26-29. Up-Count, Pulse Placement Asymmetric Waveform With Independent Modulation on EPWMxA..................2919
Figure 26-30. Up-Down Count, Dual-Edge Symmetric Waveform, with Independent Modulation on EPWMxA and
EPWMxB — Active Low.....................................................................................................................................................2919
Figure 26-31. Up-Down Count, Dual-Edge Symmetric Waveform, with Independent Modulation on EPWMxA and
EPWMxB — Complementary.............................................................................................................................................2920
Figure 26-32. Up-Down Count, Dual-Edge Asymmetric Waveform, with Independent Modulation on EPWMxA—Active
Low.....................................................................................................................................................................................2920
Figure 26-33. Up-Down Count, PWM Waveform Generation Utilizing T1 and T2 Events..................................................... 2921
Figure 26-34. Dead_Band Submodule.................................................................................................................................. 2922
Figure 26-35. Configuration Options for the Dead-Band Submodule.................................................................................... 2925
Figure 26-36. Dead-Band Waveforms for Typical Cases (0% < Duty < 100%)..................................................................... 2927
Figure 26-37. PWM Chopper Submodule..............................................................................................................................2929
Figure 26-38. PWM Chopper Submodule Operational Details.............................................................................................. 2930
Figure 26-39. Simple PWM Chopper Submodule Waveforms Showing Chopping Action Only............................................ 2930
Figure 26-40. PWM Chopper Submodule Waveforms Showing the First Pulse and Subsequent Sustaining Pulses........... 2931

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Figure 26-41. PWM Chopper Submodule Waveforms Showing the Pulse Width (Duty Cycle) Control of Sustaining Pulses 2932
Figure 26-42. Trip-Zone Submodule......................................................................................................................................2933
Figure 26-43. Trip-Zone Submodule Mode Control Logic......................................................................................................2937
Figure 26-44. Trip-Zone Submodule Interrupt Logic..............................................................................................................2938
Figure 26-45. Event-Trigger Submodule................................................................................................................................2939
Figure 26-46. Event-Trigger Submodule Showing Event Inputs and Prescaled Outputs...................................................... 2940
Figure 26-47. Event-Trigger Interrupt Generator................................................................................................................... 2942
Figure 26-48. Event-Trigger SOCA Pulse Generator............................................................................................................ 2943
Figure 26-49. Event-Trigger SOCB Pulse Generator............................................................................................................ 2943
Figure 26-50. Digital-Compare Submodule High-Level Block Diagram.................................................................................2944
Figure 26-51. GPIO MUX-to-Trip Input Connectivity............................................................................................................. 2945
Figure 26-52. DCxEVT1 Event Triggering............................................................................................................................. 2948
Figure 26-53. DCxEVT2 Event Triggering............................................................................................................................. 2949
Figure 26-54. Event Filtering................................................................................................................................................. 2950
Figure 26-55. Blanking Window Timing Diagram...................................................................................................................2951
Figure 26-56. Valley Switching...............................................................................................................................................2953
Figure 26-57. ePWM X-BAR..................................................................................................................................................2954
Figure 26-58. Simplified ePWM Module................................................................................................................................ 2955
Figure 26-59. EPWM1 Configured as a Typical Master, EPWM2 Configured as a Slave .................................................... 2956
Figure 26-60. Control of Four Buck Stages. Here FPWM1≠ FPWM2≠ FPWM3≠ FPWM4 ............................................................. 2957
Figure 26-61. Buck Waveforms for Control of Four Buck Stages (Note: Only three bucks shown here).............................. 2958
Figure 26-62. Control of Four Buck Stages. (Note: FPWM2 = N x FPWM1).............................................................................. 2959
Figure 26-63. Buck Waveforms for Control of Four Buck Stages (Note: FPWM2 = FPWM1).................................................... 2960
Figure 26-64. Control of Two Half-H Bridge Stages (FPWM2 = N x FPWM1)............................................................................ 2961
Figure 26-65. Half-H Bridge Waveforms for Control of Two Half-H Bridge Stages (Note: Here FPWM2 = FPWM1)................. 2962
Figure 26-66. Control of Dual 3-Phase Inverter Stages as Is Commonly Used in Motor Control..........................................2963
Figure 26-67. 3-Phase Inverter Waveforms for Control of Dual 3-Phase Inverter Stages (Only One Inverter Shown)......... 2964
Figure 26-68. Configuring Two PWM Modules for Phase Control......................................................................................... 2965
Figure 26-69. Timing Waveforms Associated with Phase Control Between Two Modules....................................................2966
Figure 26-70. Control of 3-Phase Interleaved DC/DC Converter.......................................................................................... 2967
Figure 26-71. 3-Phase Interleaved DC/DC Converter Waveforms for Control of 3-Phase Interleaved DC/DC Converter....2968
Figure 26-72. Control of Full-H Bridge Stage (FPWM2 = FPWM1)............................................................................................ 2969
Figure 26-73. ZVS Full-H Bridge Waveforms........................................................................................................................ 2970
Figure 26-74. Peak Current Mode Control of Buck Converter...............................................................................................2971
Figure 26-75. Peak Current Mode Control Waveforms for Control of Buck Converter.......................................................... 2971
Figure 26-76. Control of Two Resonant Converter Stages....................................................................................................2972
Figure 26-77. H-Bridge LLC Resonant Converter PWM Waveforms.....................................................................................2972
Figure 26-78. HRPWM Block Diagram.................................................................................................................................. 2974
Figure 26-79. Resolution Calculations for Conventionally Generated PWM......................................................................... 2975
Figure 26-80. Operating Logic Using MEP............................................................................................................................ 2976
Figure 26-81. HRPWM Extension Registers and Memory Configuration.............................................................................. 2977
Figure 26-82. HRPWM System Interface.............................................................................................................................. 2978
Figure 26-83. HRPWM and HRCAL Source Clock................................................................................................................2979
Figure 26-84. Required PWM Waveform for a Requested Duty = 40.5%..............................................................................2982
Figure 26-85. Low % Duty Cycle Range Limitation Example (HRPCTL[HRPE] = 0)............................................................ 2985
Figure 26-86. High % Duty Cycle Range Limitation Example (HRPCTL[HRPE] = 0)............................................................2986
Figure 26-87. Up-Count Duty Cycle Range Limitation Example (HRPCTL[HRPE]=1)..........................................................2986
Figure 26-88. Up-Down Count Duty Cycle Range Limitation Example (HRPCTL[HRPE]=1)................................................2986
Figure 26-89. Simple Buck Controlled Converter Using a Single PWM................................................................................ 2993
Figure 26-90. PWM Waveform Generated for Simple Buck Controlled Converter................................................................ 2993
Figure 26-91. Simple Reconstruction Filter for a PWM-based DAC......................................................................................2995
Figure 26-92. PWM Waveform Generated for the PWM DAC Function................................................................................ 2995
Figure 26-93. TBCTL Register............................................................................................................................................... 3011
Figure 26-94. TBCTL2 Register.............................................................................................................................................3013
Figure 26-95. EPWMSYNCINSEL Register.......................................................................................................................... 3014
Figure 26-96. TBCTR Register.............................................................................................................................................. 3015
Figure 26-97. TBSTS Register.............................................................................................................................................. 3016
Figure 26-98. EPWMSYNCOUTEN Register........................................................................................................................ 3017
Figure 26-99. TBCTL3 Register.............................................................................................................................................3019
Figure 26-100. CMPCTL Register......................................................................................................................................... 3020
Figure 26-101. CMPCTL2 Register....................................................................................................................................... 3022

50 TMS320F2838x Real-Time Microcontrollers With Connectivity Manager SPRUII0E – MAY 2019 – REVISED SEPTEMBER 2023
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Figure 26-102. DBCTL Register............................................................................................................................................ 3024

Figure 26-103. DBCTL2 Register.......................................................................................................................................... 3027
Figure 26-104. AQCTL Register............................................................................................................................................ 3028
Figure 26-105. AQTSRCSEL Register.................................................................................................................................. 3030
Figure 26-106. PCCTL Register............................................................................................................................................ 3031
Figure 26-107. VCAPCTL Register....................................................................................................................................... 3032
Figure 26-108. VCNTCFG Register.......................................................................................................................................3034
Figure 26-109. HRCNFG Register.........................................................................................................................................3036
Figure 26-110. HRPWR Register...........................................................................................................................................3038
Figure 26-111. HRMSTEP Register....................................................................................................................................... 3039
Figure 26-112. HRCNFG2 Register....................................................................................................................................... 3040
Figure 26-113. HRPCTL Register.......................................................................................................................................... 3041
Figure 26-114. TRREM Register............................................................................................................................................3043
Figure 26-115. GLDCTL Register.......................................................................................................................................... 3044
Figure 26-116. GLDCFG Register......................................................................................................................................... 3046
Figure 26-117. EPWMXLINK Register...................................................................................................................................3048
Figure 26-118. AQCTLA Register.......................................................................................................................................... 3050
Figure 26-119. AQCTLA2 Register........................................................................................................................................ 3052
Figure 26-120. AQCTLB Register..........................................................................................................................................3053
Figure 26-121. AQCTLB2 Register........................................................................................................................................3055
Figure 26-122. AQSFRC Register......................................................................................................................................... 3056
Figure 26-123. AQCSFRC Register...................................................................................................................................... 3057
Figure 26-124. DBREDHR Register...................................................................................................................................... 3058
Figure 26-125. DBRED Register........................................................................................................................................... 3059
Figure 26-126. DBFEDHR Register.......................................................................................................................................3060
Figure 26-127. DBFED Register............................................................................................................................................3061
Figure 26-128. TBPHS Register............................................................................................................................................ 3062
Figure 26-129. TBPRDHR Register.......................................................................................................................................3063
Figure 26-130. TBPRD Register............................................................................................................................................3064
Figure 26-131. CMPA Register.............................................................................................................................................. 3065
Figure 26-132. CMPB Register..............................................................................................................................................3066
Figure 26-133. CMPC Register............................................................................................................................................. 3067
Figure 26-134. CMPD Register............................................................................................................................................. 3068
Figure 26-135. GLDCTL2 Register........................................................................................................................................3069
Figure 26-136. SWVDELVAL Register...................................................................................................................................3070
Figure 26-137. TZSEL Register.............................................................................................................................................3071
Figure 26-138. TZDCSEL Register........................................................................................................................................3073
Figure 26-139. TZCTL Register.............................................................................................................................................3074
Figure 26-140. TZCTL2 Register...........................................................................................................................................3075
Figure 26-141. TZCTLDCA Register..................................................................................................................................... 3077
Figure 26-142. TZCTLDCB Register..................................................................................................................................... 3079
Figure 26-143. TZEINT Register........................................................................................................................................... 3081
Figure 26-144. TZFLG Register.............................................................................................................................................3082
Figure 26-145. TZCBCFLG Register..................................................................................................................................... 3084
Figure 26-146. TZOSTFLG Register..................................................................................................................................... 3085
Figure 26-147. TZCLR Register............................................................................................................................................ 3086
Figure 26-148. TZCBCCLR Register.....................................................................................................................................3087
Figure 26-149. TZOSTCLR Register..................................................................................................................................... 3088
Figure 26-150. TZFRC Register............................................................................................................................................ 3089
Figure 26-151. ETSEL Register.............................................................................................................................................3090
Figure 26-152. ETPS Register...............................................................................................................................................3093
Figure 26-153. ETFLG Register............................................................................................................................................ 3096
Figure 26-154. ETCLR Register............................................................................................................................................ 3097
Figure 26-155. ETFRC Register............................................................................................................................................ 3098
Figure 26-156. ETINTPS Register.........................................................................................................................................3099
Figure 26-157. ETSOCPS Register.......................................................................................................................................3100
Figure 26-158. ETCNTINITCTL Register.............................................................................................................................. 3101
Figure 26-159. ETCNTINIT Register..................................................................................................................................... 3102
Figure 26-160. DCTRIPSEL Register....................................................................................................................................3103
Figure 26-161. DCACTL Register..........................................................................................................................................3105
Figure 26-162. DCBCTL Register..........................................................................................................................................3107

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Figure 26-163. DCFCTL Register..........................................................................................................................................3109

Figure 26-164. DCCAPCTL Register..................................................................................................................................... 3111
Figure 26-165. DCFOFFSET Register...................................................................................................................................3113
Figure 26-166. DCFOFFSETCNT Register........................................................................................................................... 3114
Figure 26-167. DCFWINDOW Register................................................................................................................................. 3115
Figure 26-168. DCFWINDOWCNT Register..........................................................................................................................3116
Figure 26-169. DCCAP Register............................................................................................................................................3117
Figure 26-170. DCAHTRIPSEL Register............................................................................................................................... 3118
Figure 26-171. DCALTRIPSEL Register................................................................................................................................3120
Figure 26-172. DCBHTRIPSEL Register...............................................................................................................................3122
Figure 26-173. DCBLTRIPSEL Register................................................................................................................................3124
Figure 26-174. EPWMLOCK Register................................................................................................................................... 3126
Figure 26-175. HWVDELVAL Register.................................................................................................................................. 3127
Figure 26-176. VCNTVAL Register........................................................................................................................................3128
Figure 26-177. SYNCSELECT Register................................................................................................................................ 3130
Figure 26-178. ADCSOCOUTSELECT Register................................................................................................................... 3132
Figure 26-179. SYNCSOCLOCK Register............................................................................................................................ 3135
Figure 27-1. Optical Encoder Disk.........................................................................................................................................3150
Figure 27-2. QEP Encoder Output Signal for Forward/Reverse Movement.......................................................................... 3150
Figure 27-3. Index Pulse Example.........................................................................................................................................3151
Figure 27-4. Using eQEP to Decode Signals from SinCos Transducer.................................................................................3154
Figure 27-5. Functional Block Diagram of the eQEP Peripheral........................................................................................... 3156
Figure 27-6. Functional Block Diagram of Decoder Unit....................................................................................................... 3158
Figure 27-7. Quadrature Decoder State Machine..................................................................................................................3159
Figure 27-8. Quadrature-clock and Direction Decoding........................................................................................................ 3160
Figure 27-9. Position Counter Reset by Index Pulse for 1000-Line Encoder (QPOSMAX = 3999 or 0xF9F)....................... 3162
Figure 27-10. Position Counter Underflow/Overflow (QPOSMAX = 4)..................................................................................3163
Figure 27-11. Software Index Marker for 1000-line Encoder (QEPCTL[IEL] = 1)..................................................................3165
Figure 27-12. Strobe Event Latch (QEPCTL[SEL] = 1)......................................................................................................... 3165
Figure 27-13. Latching Position Counter on ADCSOCA/ADCSOCB Event.......................................................................... 3166
Figure 27-14. eQEP Position-compare Unit.......................................................................................................................... 3167
Figure 27-15. eQEP Position-compare Event Generation Points..........................................................................................3168
Figure 27-16. eQEP Position-compare Sync Output Pulse Stretcher................................................................................... 3168
Figure 27-17. eQEP Edge Capture Unit................................................................................................................................ 3170
Figure 27-18. Unit Position Event for Low Speed Measurement (QCAPCTL[UPPS] = 0010)...............................................3171
Figure 27-19. eQEP Edge Capture Unit - Timing Details...................................................................................................... 3171
Figure 27-20. eQEP Watchdog Timer....................................................................................................................................3173
Figure 27-21. eQEP Unit Timer Base.................................................................................................................................... 3173
Figure 27-22. QMA Module Block Diagram........................................................................................................................... 3174
Figure 27-23. QMA Mode-1................................................................................................................................................... 3175
Figure 27-24. QMA Mode-2................................................................................................................................................... 3176
Figure 27-25. eQEP Interrupt Generation..............................................................................................................................3177
Figure 27-26. QPOSCNT Register........................................................................................................................................ 3184
Figure 27-27. QPOSINIT Register.........................................................................................................................................3185
Figure 27-28. QPOSMAX Register........................................................................................................................................3186
Figure 27-29. QPOSCMP Register........................................................................................................................................3187
Figure 27-30. QPOSILAT Register........................................................................................................................................ 3188
Figure 27-31. QPOSSLAT Register....................................................................................................................................... 3189
Figure 27-32. QPOSLAT Register......................................................................................................................................... 3190
Figure 27-33. QUTMR Register.............................................................................................................................................3191
Figure 27-34. QUPRD Register............................................................................................................................................. 3192
Figure 27-35. QWDTMR Register......................................................................................................................................... 3193
Figure 27-36. QWDPRD Register..........................................................................................................................................3194
Figure 27-37. QDECCTL Register.........................................................................................................................................3195
Figure 27-38. QEPCTL Register............................................................................................................................................3197
Figure 27-39. QCAPCTL Register......................................................................................................................................... 3199
Figure 27-40. QPOSCTL Register.........................................................................................................................................3200
Figure 27-41. QEINT Register............................................................................................................................................... 3201
Figure 27-42. QFLG Register................................................................................................................................................ 3203
Figure 27-43. QCLR Register................................................................................................................................................ 3205
Figure 27-44. QFRC Register................................................................................................................................................3207

52 TMS320F2838x Real-Time Microcontrollers With Connectivity Manager SPRUII0E – MAY 2019 – REVISED SEPTEMBER 2023
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Figure 27-45. QEPSTS Register........................................................................................................................................... 3209

Figure 27-46. QCTMR Register.............................................................................................................................................3210
Figure 27-47. QCPRD Register............................................................................................................................................. 3211
Figure 27-48. QCTMRLAT Register.......................................................................................................................................3212
Figure 27-49. QCPRDLAT Register.......................................................................................................................................3213
Figure 27-50. REV Register...................................................................................................................................................3214
Figure 27-51. QEPSTROBESEL Register.............................................................................................................................3215
Figure 27-52. QMACTRL Register........................................................................................................................................ 3216
Figure 27-53. QEPSRCSEL Register.................................................................................................................................... 3217
Figure 28-1. Sigma Delta Filter Module (SDFM) CPU Interface............................................................................................3222
Figure 28-2. Sigma Delta Filter Module (SDFM) Block Diagram........................................................................................... 3224
Figure 28-3. Block Diagram of One Filter Module................................................................................................................. 3225
Figure 28-4. Input Qualification on SD-Cx and SD-Dx.......................................................................................................... 3227
Figure 28-5. Different Modulator Modes Supported...............................................................................................................3228
Figure 28-6. SDFM Clock Control..........................................................................................................................................3229
Figure 28-7. Simplified Sinc Filter Architecture......................................................................................................................3229
Figure 28-8. Z-Transform of Sinc Filter of Order N................................................................................................................ 3230
Figure 28-9. Frequency Response of Different Sinc Filters................................................................................................... 3230
Figure 28-10. SDSYNC Event............................................................................................................................................... 3236
Figure 28-11. Comparator Unit Structure...............................................................................................................................3238
Figure 28-12. Digital Filter..................................................................................................................................................... 3240
Figure 28-13. SDFM Error (SD_ERR) Interrupt Sources.......................................................................................................3243
Figure 28-14. SDFM Data Ready (SDy_DRINTx) Interrupt...................................................................................................3244
Figure 28-15. SDIFLG Register............................................................................................................................................. 3254
Figure 28-16. SDIFLGCLR Register......................................................................................................................................3257
Figure 28-17. SDCTL Register.............................................................................................................................................. 3259
Figure 28-18. SDMFILEN Register........................................................................................................................................3260
Figure 28-19. SDSTATUS Register....................................................................................................................................... 3261
Figure 28-20. SDCTLPARM1 Register.................................................................................................................................. 3262
Figure 28-21. SDDFPARM1 Register.................................................................................................................................... 3263
Figure 28-22. SDDPARM1 Register...................................................................................................................................... 3264
Figure 28-23. SDFLT1CMPH1 Register................................................................................................................................ 3265
Figure 28-24. SDFLT1CMPL1 Register................................................................................................................................. 3266
Figure 28-25. SDCPARM1 Register...................................................................................................................................... 3267
Figure 28-26. SDDATA1 Register.......................................................................................................................................... 3269
Figure 28-27. SDDATFIFO1 Register.................................................................................................................................... 3270
Figure 28-28. SDCDATA1 Register....................................................................................................................................... 3271
Figure 28-29. SDFLT1CMPH2 Register................................................................................................................................ 3272
Figure 28-30. SDFLT1CMPHZ Register................................................................................................................................ 3273
Figure 28-31. SDFIFOCTL1 Register.................................................................................................................................... 3274
Figure 28-32. SDSYNC1 Register......................................................................................................................................... 3275
Figure 28-33. SDFLT1CMPL2 Register................................................................................................................................. 3276
Figure 28-34. SDCTLPARM2 Register.................................................................................................................................. 3277
Figure 28-35. SDDFPARM2 Register.................................................................................................................................... 3278
Figure 28-36. SDDPARM2 Register...................................................................................................................................... 3279
Figure 28-37. SDFLT2CMPH1 Register................................................................................................................................ 3280
Figure 28-38. SDFLT2CMPL1 Register................................................................................................................................. 3281
Figure 28-39. SDCPARM2 Register...................................................................................................................................... 3282
Figure 28-40. SDDATA2 Register.......................................................................................................................................... 3284
Figure 28-41. SDDATFIFO2 Register.................................................................................................................................... 3285
Figure 28-42. SDCDATA2 Register....................................................................................................................................... 3286
Figure 28-43. SDFLT2CMPH2 Register................................................................................................................................ 3287
Figure 28-44. SDFLT2CMPHZ Register................................................................................................................................ 3288
Figure 28-45. SDFIFOCTL2 Register.................................................................................................................................... 3289
Figure 28-46. SDSYNC2 Register......................................................................................................................................... 3290
Figure 28-47. SDFLT2CMPL2 Register................................................................................................................................. 3291
Figure 28-48. SDCTLPARM3 Register.................................................................................................................................. 3292
Figure 28-49. SDDFPARM3 Register.................................................................................................................................... 3293
Figure 28-50. SDDPARM3 Register...................................................................................................................................... 3294
Figure 28-51. SDFLT3CMPH1 Register................................................................................................................................ 3295
Figure 28-52. SDFLT3CMPL1 Register................................................................................................................................. 3296

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Figure 28-53. SDCPARM3 Register...................................................................................................................................... 3297

Figure 28-54. SDDATA3 Register.......................................................................................................................................... 3299
Figure 28-55. SDDATFIFO3 Register.................................................................................................................................... 3300
Figure 28-56. SDCDATA3 Register....................................................................................................................................... 3301
Figure 28-57. SDFLT3CMPH2 Register................................................................................................................................ 3302
Figure 28-58. SDFLT3CMPHZ Register................................................................................................................................ 3303
Figure 28-59. SDFIFOCTL3 Register.................................................................................................................................... 3304
Figure 28-60. SDSYNC3 Register......................................................................................................................................... 3305
Figure 28-61. SDFLT3CMPL2 Register................................................................................................................................. 3306
Figure 28-62. SDCTLPARM4 Register.................................................................................................................................. 3307
Figure 28-63. SDDFPARM4 Register.................................................................................................................................... 3308
Figure 28-64. SDDPARM4 Register...................................................................................................................................... 3309
Figure 28-65. SDFLT4CMPH1 Register................................................................................................................................ 3310
Figure 28-66. SDFLT4CMPL1 Register................................................................................................................................. 3311
Figure 28-67. SDCPARM4 Register...................................................................................................................................... 3312
Figure 28-68. SDDATA4 Register.......................................................................................................................................... 3314
Figure 28-69. SDDATFIFO4 Register.................................................................................................................................... 3315
Figure 28-70. SDCDATA4 Register....................................................................................................................................... 3316
Figure 28-71. SDFLT4CMPH2 Register................................................................................................................................ 3317
Figure 28-72. SDFLT4CMPHZ Register................................................................................................................................ 3318
Figure 28-73. SDFIFOCTL4 Register.................................................................................................................................... 3319
Figure 28-74. SDSYNC4 Register......................................................................................................................................... 3320
Figure 28-75. SDFLT4CMPL2 Register................................................................................................................................. 3321
Figure 28-76. SDCOMP1CTL Register................................................................................................................................. 3322
Figure 28-77. SDCOMP1EVT2FLTCTL Register.................................................................................................................. 3323
Figure 28-78. SDCOMP1EVT2FLTCLKCTL Register........................................................................................................... 3324
Figure 28-79. SDCOMP1EVT1FLTCTL Register.................................................................................................................. 3325
Figure 28-80. SDCOMP1EVT1FLTCLKCTL Register........................................................................................................... 3326
Figure 28-81. SDCOMP1LOCK Register.............................................................................................................................. 3327
Figure 28-82. SDCOMP2CTL Register................................................................................................................................. 3328
Figure 28-83. SDCOMP2EVT2FLTCTL Register.................................................................................................................. 3329
Figure 28-84. SDCOMP2EVT2FLTCLKCTL Register........................................................................................................... 3330
Figure 28-85. SDCOMP2EVT1FLTCTL Register.................................................................................................................. 3331
Figure 28-86. SDCOMP2EVT1FLTCLKCTL Register........................................................................................................... 3332
Figure 28-87. SDCOMP2LOCK Register.............................................................................................................................. 3333
Figure 28-88. SDCOMP3CTL Register................................................................................................................................. 3334
Figure 28-89. SDCOMP3EVT2FLTCTL Register.................................................................................................................. 3335
Figure 28-90. SDCOMP3EVT2FLTCLKCTL Register........................................................................................................... 3336
Figure 28-91. SDCOMP3EVT1FLTCTL Register.................................................................................................................. 3337
Figure 28-92. SDCOMP3EVT1FLTCLKCTL Register........................................................................................................... 3338
Figure 28-93. SDCOMP3LOCK Register.............................................................................................................................. 3339
Figure 28-94. SDCOMP4CTL Register................................................................................................................................. 3340
Figure 28-95. SDCOMP4EVT2FLTCTL Register.................................................................................................................. 3341
Figure 28-96. SDCOMP4EVT2FLTCLKCTL Register........................................................................................................... 3342
Figure 28-97. SDCOMP4EVT1FLTCTL Register.................................................................................................................. 3343
Figure 28-98. SDCOMP4EVT1FLTCLKCTL Register........................................................................................................... 3344
Figure 28-99. SDCOMP4LOCK Register.............................................................................................................................. 3345
Figure 29-1. F2838x Block Diagram...................................................................................................................................... 3352
Figure 30-1. CAN Block Diagram.......................................................................................................................................... 3355
Figure 30-2. Accessing Message Objects Through IFx Registers.........................................................................................3356
Figure 30-3. CAN_MUX.........................................................................................................................................................3361
Figure 30-4. CAN Core in Silent Mode.................................................................................................................................. 3362
Figure 30-5. CAN Core in Loopback Mode............................................................................................................................3363
Figure 30-6. CAN Core in External Loopback Mode............................................................................................................. 3364
Figure 30-7. CAN Core in Loopback Combined with Silent Mode.........................................................................................3365
Figure 30-8. CAN Interrupt Topology 1.................................................................................................................................. 3367
Figure 30-9. CAN Interrupt Topology 2.................................................................................................................................. 3367
Figure 30-10. Initialization of a Transmit Object.................................................................................................................... 3370
Figure 30-11. Initialization of a Single Receive Object for Data Frames................................................................................3370
Figure 30-12. Initialization of a Single Receive Object for Remote Frames.......................................................................... 3371
Figure 30-13. CPU Handling of a FIFO Buffer (Interrupt Driven)...........................................................................................3376

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Figure 30-14. Bit Timing.........................................................................................................................................................3377

Figure 30-15. Propagation Time Segment.............................................................................................................................3378
Figure 30-16. Synchronization on Late and Early Edges...................................................................................................... 3380
Figure 30-17. Filtering of Short Dominant Spikes..................................................................................................................3381
Figure 30-18. Structure of the CAN Core's CAN Protocol Controller.....................................................................................3383
Figure 30-19. Data Transfer Between IF1 / IF2 Registers and Message RAM..................................................................... 3387
Figure 30-20. Structure of a Message Object........................................................................................................................3388
Figure 30-21. Message RAM Representation in Debug Mode.............................................................................................. 3392
Figure 30-22. CAN_CTL Register..........................................................................................................................................3401
Figure 30-23. CAN_ES Register............................................................................................................................................3404
Figure 30-24. CAN_ERRC Register...................................................................................................................................... 3406
Figure 30-25. CAN_BTR Register......................................................................................................................................... 3407
Figure 30-26. CAN_INT Register...........................................................................................................................................3409
Figure 30-27. CAN_TEST Register....................................................................................................................................... 3410
Figure 30-28. CAN_PERR Register...................................................................................................................................... 3412
Figure 30-29. CAN_RAM_INIT Register................................................................................................................................3413
Figure 30-30. CAN_GLB_INT_EN Register.......................................................................................................................... 3414
Figure 30-31. CAN_GLB_INT_FLG Register........................................................................................................................ 3415
Figure 30-32. CAN_GLB_INT_CLR Register........................................................................................................................ 3416
Figure 30-33. CAN_ABOTR Register.................................................................................................................................... 3417
Figure 30-34. CAN_TXRQ_X Register.................................................................................................................................. 3418
Figure 30-35. CAN_TXRQ_21 Register................................................................................................................................ 3419
Figure 30-36. CAN_NDAT_X Register...................................................................................................................................3420
Figure 30-37. CAN_NDAT_21 Register................................................................................................................................. 3421
Figure 30-38. CAN_IPEN_X Register....................................................................................................................................3422
Figure 30-39. CAN_IPEN_21 Register.................................................................................................................................. 3423
Figure 30-40. CAN_MVAL_X Register...................................................................................................................................3424
Figure 30-41. CAN_MVAL_21 Register................................................................................................................................. 3425
Figure 30-42. CAN_IP_MUX21 Register............................................................................................................................... 3426
Figure 30-43. CAN_IF1CMD Register................................................................................................................................... 3427
Figure 30-44. CAN_IF1MSK Register................................................................................................................................... 3430
Figure 30-45. CAN_IF1ARB Register....................................................................................................................................3431
Figure 30-46. CAN_IF1MCTL Register................................................................................................................................. 3433
Figure 30-47. CAN_IF1DATA Register.................................................................................................................................. 3435
Figure 30-48. CAN_IF1DATB Register.................................................................................................................................. 3436
Figure 30-49. CAN_IF2CMD Register................................................................................................................................... 3437
Figure 30-50. CAN_IF2MSK Register................................................................................................................................... 3440
Figure 30-51. CAN_IF2ARB Register....................................................................................................................................3441
Figure 30-52. CAN_IF2MCTL Register................................................................................................................................. 3443
Figure 30-53. CAN_IF2DATA Register.................................................................................................................................. 3445
Figure 30-54. CAN_IF2DATB Register.................................................................................................................................. 3446
Figure 30-55. CAN_IF3OBS Register....................................................................................................................................3447
Figure 30-56. CAN_IF3MSK Register................................................................................................................................... 3449
Figure 30-57. CAN_IF3ARB Register....................................................................................................................................3450
Figure 30-58. CAN_IF3MCTL Register................................................................................................................................. 3451
Figure 30-59. CAN_IF3DATA Register.................................................................................................................................. 3453
Figure 30-60. CAN_IF3DATB Register.................................................................................................................................. 3454
Figure 30-61. CAN_IF3UPD Register....................................................................................................................................3455
Figure 31-1. EtherCAT IP Block Diagram.............................................................................................................................. 3462
Figure 31-2. Two-port ESC Description................................................................................................................................. 3464
Figure 31-3. Two-port Block Diagram in EtherCAT Topology................................................................................................ 3464
Figure 31-4. ESC PHY Interface Diagram............................................................................................................................. 3467
Figure 31-5. PHY Management Interface Connectivity......................................................................................................... 3468
Figure 31-6. EtherCAT State Machine................................................................................................................................... 3470
Figure 31-7. ESC Integration on MCU...................................................................................................................................3471
Figure 31-8. Interaction of ESCSS with the CPU Subsystem................................................................................................3473
Figure 31-9. ESCSS Wrapper................................................................................................................................................3475
Figure 31-10. Clocking of ESC.............................................................................................................................................. 3477
Figure 31-11. ESCSS General-Purpose Inputs Integration................................................................................................... 3481
Figure 31-12. ESCSS General-Purpose Output Integration.................................................................................................. 3482
Figure 31-13. ESC SYNC and LATCH...................................................................................................................................3482

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Figure 31-14. SYNC0 Signal Modes......................................................................................................................................3484

Figure 31-15. SYNC Integration for the HOST Intervention.................................................................................................. 3485
Figure 31-16. SYNC Event Muxing for Different Host DMA Triggers.................................................................................... 3486
Figure 31-17. ESC Latch Input Integration............................................................................................................................ 3487
Figure 31-18. SYNC Integration for Control Functions - PWM SYNC................................................................................... 3490
Figure 31-19. SYNC Integration for Control Functions – ECAP............................................................................................ 3490
Figure 31-20. SYNC Integration for Signal Conditioning – CLB............................................................................................ 3491
Figure 31-21. ESCSS_IPREVNUM Register.........................................................................................................................3496
Figure 31-22. ESCSS_INTR_RIS Register........................................................................................................................... 3497
Figure 31-23. ESCSS_INTR_MASK Register....................................................................................................................... 3499
Figure 31-24. ESCSS_INTR_MIS Register........................................................................................................................... 3501
Figure 31-25. ESCSS_INTR_CLR Register.......................................................................................................................... 3503
Figure 31-26. ESCSS_INTR_SET Register.......................................................................................................................... 3504
Figure 31-27. ESCSS_LATCH_SEL Register........................................................................................................................3506
Figure 31-28. ESCSS_ACCESS_CTRL Register..................................................................................................................3507
Figure 31-29. ESCSS_GPIN_DAT Register.......................................................................................................................... 3508
Figure 31-30. ESCSS_GPIN_PIPE Register.........................................................................................................................3509
Figure 31-31. ESCSS_GPIN_GRP_CAP_SEL Register....................................................................................................... 3510
Figure 31-32. ESCSS_GPOUT_DAT Register...................................................................................................................... 3512
Figure 31-33. ESCSS_GPOUT_PIPE Register.....................................................................................................................3513
Figure 31-34. ESCSS_GPOUT_GRP_CAP_SEL Register................................................................................................... 3514
Figure 31-35. ESCSS_MEM_TEST Register........................................................................................................................ 3515
Figure 31-36. ESCSS_RESET_DEST_CONFIG Register.................................................................................................... 3516
Figure 31-37. ESCSS_SYNC0_CONFIG Register................................................................................................................3518
Figure 31-38. ESCSS_SYNC1_CONFIG Register................................................................................................................3519
Figure 31-39. ESCSS_CONFIG_LOCK Register.................................................................................................................. 3521
Figure 31-40. ESCSS_MISC_IO_CONFIG Register............................................................................................................. 3522
Figure 31-41. ESCSS_PHY_IO_CONFIG Register...............................................................................................................3523
Figure 31-42. ESCSS_SYNC_IO_CONFIG Register............................................................................................................ 3524
Figure 31-43. ESCSS_LATCH_IO_CONFIG Register...........................................................................................................3525
Figure 31-44. ESCSS_GPIN_SEL Register.......................................................................................................................... 3526
Figure 31-45. ESCSS_GPIN_IOPAD_SEL Register............................................................................................................. 3527
Figure 31-46. ESCSS_GPOUT_SEL Register...................................................................................................................... 3528
Figure 31-47. ESCSS_GPOUT_IOPAD_SEL Register......................................................................................................... 3529
Figure 31-48. ESCSS_LED_CONFIG Register.....................................................................................................................3530
Figure 31-49. ESCSS_MISC_CONFIG Register...................................................................................................................3532
Figure 32-1. FSI Transmitter (FSITX) CPU Interface.............................................................................................................3539
Figure 32-2. FSI Receiver (FSIRX) CPU Interface with CLB.................................................................................................3540
Figure 32-3. FSI Transmitter Block Diagram......................................................................................................................... 3547
Figure 32-4. FSI Transmitter Core Block Diagram.................................................................................................................3548
Figure 32-5. FSI Receiver Block Diagram............................................................................................................................. 3553
Figure 32-6. FSI Receiver Core Block Diagram.................................................................................................................... 3554
Figure 32-7. Delay Line Control Circuit..................................................................................................................................3557
Figure 32-8. Flush Sequence Signals....................................................................................................................................3563
Figure 32-9. FSI with Internal Loopback................................................................................................................................3564
Figure 32-10. FSI Multi-Slave TDM Configuration.................................................................................................................3567
Figure 32-11. FSI Transmitter Multi-Slave TDM Multiplexing................................................................................................ 3567
Figure 32-12. Generated Signals for FSI Multi-Slave TDM Configuration.............................................................................3568
Figure 32-13. FSI and CLB Multi-Slave TDM Connections................................................................................................... 3569
Figure 32-14. RX_TRIGx FSI Trigger.................................................................................................................................... 3570
Figure 32-15. FSITX as SPI Master, Transmit Only.............................................................................................................. 3572
Figure 32-16. FSIRX as SPI Slave, Receive Only.................................................................................................................3573
Figure 32-17. FSITX and FSIRX as SPI Master, Full Duplex................................................................................................ 3574
Figure 32-18. Point to Point Connection................................................................................................................................3575
Figure 32-19. TX_MASTER_CTRL Register......................................................................................................................... 3591
Figure 32-20. TX_CLK_CTRL Register................................................................................................................................. 3592
Figure 32-21. TX_OPER_CTRL_LO Register....................................................................................................................... 3593
Figure 32-22. TX_OPER_CTRL_HI Register........................................................................................................................ 3595
Figure 32-23. TX_FRAME_CTRL Register........................................................................................................................... 3596
Figure 32-24. TX_FRAME_TAG_UDATA Register................................................................................................................ 3597
Figure 32-25. TX_BUF_PTR_LOAD Register....................................................................................................................... 3598

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Figure 32-26. TX_BUF_PTR_STS Register.......................................................................................................................... 3599

Figure 32-27. TX_PING_CTRL Register............................................................................................................................... 3600
Figure 32-28. TX_PING_TAG Register..................................................................................................................................3601
Figure 32-29. TX_PING_TO_REF Register...........................................................................................................................3602
Figure 32-30. TX_PING_TO_CNT Register.......................................................................................................................... 3603
Figure 32-31. TX_INT_CTRL Register.................................................................................................................................. 3604
Figure 32-32. TX_DMA_CTRL Register................................................................................................................................ 3606
Figure 32-33. TX_LOCK_CTRL Register.............................................................................................................................. 3607
Figure 32-34. TX_EVT_STS Register................................................................................................................................... 3608
Figure 32-35. TX_EVT_CLR Register................................................................................................................................... 3609
Figure 32-36. TX_EVT_FRC Register................................................................................................................................... 3610
Figure 32-37. TX_USER_CRC Register................................................................................................................................ 3611
Figure 32-38. TX_ECC_DATA Register.................................................................................................................................3612
Figure 32-39. TX_ECC_VAL Register................................................................................................................................... 3613
Figure 32-40. TX_BUF_BASE_y Register.............................................................................................................................3614
Figure 32-41. RX_MASTER_CTRL Register.........................................................................................................................3617
Figure 32-42. RX_OPER_CTRL Register............................................................................................................................. 3618
Figure 32-43. RX_FRAME_INFO Register............................................................................................................................3619
Figure 32-44. RX_FRAME_TAG_UDATA Register................................................................................................................3620
Figure 32-45. RX_DMA_CTRL Register................................................................................................................................3621
Figure 32-46. RX_EVT_STS Register................................................................................................................................... 3622
Figure 32-47. RX_CRC_INFO Register.................................................................................................................................3625
Figure 32-48. RX_EVT_CLR Register...................................................................................................................................3626
Figure 32-49. RX_EVT_FRC Register...................................................................................................................................3628
Figure 32-50. RX_BUF_PTR_LOAD Register.......................................................................................................................3631
Figure 32-51. RX_BUF_PTR_STS Register..........................................................................................................................3632
Figure 32-52. RX_FRAME_WD_CTRL Register................................................................................................................... 3633
Figure 32-53. RX_FRAME_WD_REF Register..................................................................................................................... 3634
Figure 32-54. RX_FRAME_WD_CNT Register..................................................................................................................... 3635
Figure 32-55. RX_PING_WD_CTRL Register.......................................................................................................................3636
Figure 32-56. RX_PING_TAG Register................................................................................................................................. 3637
Figure 32-57. RX_PING_WD_REF Register......................................................................................................................... 3638
Figure 32-58. RX_PING_WD_CNT Register.........................................................................................................................3639
Figure 32-59. RX_INT1_CTRL Register................................................................................................................................3640
Figure 32-60. RX_INT2_CTRL Register................................................................................................................................3643
Figure 32-61. RX_LOCK_CTRL Register..............................................................................................................................3646
Figure 32-62. RX_ECC_DATA Register................................................................................................................................ 3647
Figure 32-63. RX_ECC_VAL Register................................................................................................................................... 3648
Figure 32-64. RX_ECC_SEC_DATA Register....................................................................................................................... 3649
Figure 32-65. RX_ECC_LOG Register..................................................................................................................................3650
Figure 32-66. RX_FRAME_TAG_CMP Register................................................................................................................... 3651
Figure 32-67. RX_PING_TAG_CMP Register....................................................................................................................... 3652
Figure 32-68. RX_DLYLINE_CTRL Register......................................................................................................................... 3653
Figure 32-69. RX_VIS_1 Register......................................................................................................................................... 3654
Figure 32-70. RX_BUF_BASE_y Register............................................................................................................................ 3655
Figure 33-1. Multiple I2C Modules Connected...................................................................................................................... 3662
Figure 33-2. I2C Module Conceptual Block Diagram............................................................................................................ 3665
Figure 33-3. Clocking Diagram for the I2C Module............................................................................................................... 3665
Figure 33-4. Roles of the Clock Divide-Down Values (ICCL and ICCH)................................................................................3666
Figure 33-5. Bit Transfer on the I2C bus................................................................................................................................3667
Figure 33-6. I2C Slave TX / RX Flowchart.............................................................................................................................3669
Figure 33-7. I2C Master TX / RX Flowchart...........................................................................................................................3670
Figure 33-8. I2C Module START and STOP Conditions........................................................................................................3671
Figure 33-9. I2C Module Data Transfer (7-Bit Addressing with 8-bit Data Configuration Shown)......................................... 3672
Figure 33-10. I2C Module 7-Bit Addressing Format (FDF = 0, XA = 0 in I2CMDR).............................................................. 3673
Figure 33-11. I2C Module 10-Bit Addressing Format (FDF = 0, XA = 1 in I2CMDR).............................................................3673
Figure 33-12. I2C Module Free Data Format (FDF = 1 in I2CMDR)......................................................................................3674
Figure 33-13. Repeated START Condition (in This Case, 7-Bit Addressing Format)............................................................ 3674
Figure 33-14. Synchronization of Two I2C Clock Generators During Arbitration...................................................................3675
Figure 33-15. Arbitration Procedure Between Two Master-Transmitters...............................................................................3676
Figure 33-16. Pin Diagram Showing the Effects of the Digital Loopback Mode (DLB) Bit.....................................................3677

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Figure 33-17. Enable Paths of the I2C Interrupt Requests....................................................................................................3680

Figure 33-18. Backwards Compatibility Mode and Forward Compatibility Bit, Slave Transmitter......................................... 3681
Figure 33-19. I2C FIFO Interrupt........................................................................................................................................... 3682
Figure 33-20. I2COAR Register.............................................................................................................................................3688
Figure 33-21. I2CIER Register.............................................................................................................................................. 3689
Figure 33-22. I2CSTR Register............................................................................................................................................. 3690
Figure 33-23. I2CCLKL Register........................................................................................................................................... 3694
Figure 33-24. I2CCLKH Register...........................................................................................................................................3695
Figure 33-25. I2CCNT Register............................................................................................................................................. 3696
Figure 33-26. I2CDRR Register.............................................................................................................................................3697
Figure 33-27. I2CSAR Register............................................................................................................................................. 3698
Figure 33-28. I2CDXR Register.............................................................................................................................................3699
Figure 33-29. I2CMDR Register............................................................................................................................................ 3700
Figure 33-30. I2CISRC Register............................................................................................................................................3703
Figure 33-31. I2CEMDR Register..........................................................................................................................................3704
Figure 33-32. I2CPSC Register............................................................................................................................................. 3705
Figure 33-33. I2CFFTX Register........................................................................................................................................... 3706
Figure 33-34. I2CFFRX Register........................................................................................................................................... 3708
Figure 34-1. Conceptual Block Diagram of the McBSP.........................................................................................................3714
Figure 34-2. McBSP Data Transfer Paths............................................................................................................................. 3715
Figure 34-3. Companding Processes.................................................................................................................................... 3716
Figure 34-4. μ-Law Transmit Data Companding Format....................................................................................................... 3716
Figure 34-5. A-Law Transmit Data Companding Format....................................................................................................... 3716
Figure 34-6. Two Methods by Which the McBSP Can Compand Internal Data.................................................................... 3717
Figure 34-7. Example - Clock Signal Control of Bit Transfer Timing......................................................................................3717
Figure 34-8. McBSP Operating at Maximum Packet Frequency........................................................................................... 3719
Figure 34-9. Single-Phase Frame for a McBSP Data Transfer..............................................................................................3720
Figure 34-10. Dual-Phase Frame for a McBSP Data Transfer.............................................................................................. 3720
Figure 34-11. Implementing the AC97 Standard With a Dual-Phase Frame......................................................................... 3721
Figure 34-12. Timing of an AC97-Standard Data Transfer Near Frame Synchronization..................................................... 3721
Figure 34-13. McBSP Reception Physical Data Path............................................................................................................3722
Figure 34-14. McBSP Reception Signal Activity....................................................................................................................3722
Figure 34-15. McBSP Transmission Physical Data Path.......................................................................................................3723
Figure 34-16. McBSP Transmission Signal Activity...............................................................................................................3723
Figure 34-17. Conceptual Block Diagram of the Sample Rate Generator.............................................................................3725
Figure 34-18. Possible Inputs to the Sample Rate Generator and the Polarity Bits.............................................................. 3727
Figure 34-19. CLKG Synchronization and FSG Generation When GSYNC = 1 and CLKGDV = 1.......................................3729
Figure 34-20. CLKG Synchronization and FSG Generation When GSYNC = 1 and CLKGDV = 3.......................................3730
Figure 34-21. Overrun in the McBSP Receiver..................................................................................................................... 3732
Figure 34-22. Overrun Prevented in the McBSP Receiver.................................................................................................... 3733
Figure 34-23. Possible Responses to Receive Frame-Synchronization Pulses....................................................................3733
Figure 34-24. An Unexpected Frame-Synchronization Pulse During a McBSP Reception...................................................3734
Figure 34-25. Proper Positioning of Frame-Synchronization Pulses..................................................................................... 3735
Figure 34-26. Data in the McBSP Transmitter Overwritten and Thus Not Transmitted......................................................... 3735
Figure 34-27. Underflow During McBSP Transmission......................................................................................................... 3736
Figure 34-28. Underflow Prevented in the McBSP Transmitter............................................................................................. 3737
Figure 34-29. Possible Responses to Transmit Frame-Synchronization Pulses................................................................... 3737
Figure 34-30. An Unexpected Frame-Synchronization Pulse During a McBSP Transmission..............................................3738
Figure 34-31. Proper Positioning of Frame-Synchronization Pulses..................................................................................... 3739
Figure 34-32. Alternating Between the Channels of Partition A and the Channels of Partition B..........................................3742
Figure 34-33. Reassigning Channel Blocks Throughout a McBSP Data Transfer................................................................ 3742
Figure 34-34. McBSP Data Transfer in the 8-Partition Mode................................................................................................ 3743
Figure 34-35. Activity on McBSP Pins for the Possible Values of XMCM..............................................................................3747
Figure 34-36. Typical SPI Interface....................................................................................................................................... 3748
Figure 34-37. SPI Transfer with CLKSTP = 10b (No Clock Delay), CLKXP = 0, and CLKRP = 0.........................................3750
Figure 34-38. SPI Transfer with CLKSTP = 11b (Clock Delay), CLKXP = 0, CLKRP = 1......................................................3750
Figure 34-39. SPI Transfer with CLKSTP = 10b (No Clock Delay), CLKXP = 1, and CLKRP = 0.........................................3750
Figure 34-40. SPI Transfer with CLKSTP = 11b (Clock Delay), CLKXP = 1, CLKRP = 1......................................................3751
Figure 34-41. SPI Interface with McBSP Used as Master .................................................................................................... 3752
Figure 34-42. SPI Interface With McBSP Used as Slave ..................................................................................................... 3753
Figure 34-43. Unexpected Frame-Synchronization Pulse With (R/X)FIG = 0....................................................................... 3761

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Figure 34-44. Unexpected Frame-Synchronization Pulse With (R/X)FIG = 1....................................................................... 3761

Figure 34-45. Companding Processes for Reception and for Transmission......................................................................... 3762
Figure 34-46. Range of Programmable Data Delay.............................................................................................................. 3763
Figure 34-47. 2-Bit Data Delay Used to Skip a Framing Bit.................................................................................................. 3764
Figure 34-48. Data Clocked Externally Using a Rising Edge and Sampled by the McBSP Receiver on a Falling Edge...... 3769
Figure 34-49. Frame of Period 16 CLKG Periods and Active Width of 2 CLKG Periods.......................................................3770
Figure 34-50. Data Clocked Externally Using a Rising Edge and Sampled by the McBSP Receiver on a Falling Edge...... 3773
Figure 34-51. Unexpected Frame-Synchronization Pulse With (R/X) FIG = 0...................................................................... 3784
Figure 34-52. Unexpected Frame-Synchronization Pulse With (R/X) FIG = 1...................................................................... 3784
Figure 34-53. Companding Processes for Reception and for Transmission......................................................................... 3785
Figure 34-54. μ-Law Transmit Data Companding Format..................................................................................................... 3786
Figure 34-55. A-Law Transmit Data Companding Format..................................................................................................... 3786
Figure 34-56. Range of Programmable Data Delay.............................................................................................................. 3787
Figure 34-57. 2-Bit Data Delay Used to Skip a Framing Bit.................................................................................................. 3787
Figure 34-58. Data Clocked Externally Using a Rising Edge and Sampled by the McBSP Receiver on a Falling Edge...... 3791
Figure 34-59. Frame of Period 16 CLKG Periods and Active Width of 2 CLKG Periods.......................................................3791
Figure 34-60. Data Clocked Externally Using a Rising Edge and Sampled by the McBSP Receiver on a Falling Edge...... 3793
Figure 34-61. Four 8-Bit Data Words Transferred To/From the McBSP................................................................................ 3796
Figure 34-62. One 32-Bit Data Word Transferred To/From the McBSP................................................................................ 3797
Figure 34-63. 8-Bit Data Words Transferred at Maximum Packet Frequency....................................................................... 3798
Figure 34-64. Configuring the Data Stream of Figure 34-63 as a Continuous 32-Bit Word...................................................3798
Figure 34-65. Receive Interrupt Generation.......................................................................................................................... 3799
Figure 34-66. Transmit Interrupt Generation......................................................................................................................... 3800
Figure 34-67. DRR2 Register................................................................................................................................................ 3809
Figure 34-68. DRR1 Register................................................................................................................................................ 3810
Figure 34-69. DXR2 Register.................................................................................................................................................3811
Figure 34-70. DXR1 Register................................................................................................................................................ 3812
Figure 34-71. SPCR2 Register.............................................................................................................................................. 3813
Figure 34-72. SPCR1 Register.............................................................................................................................................. 3816
Figure 34-73. RCR2 Register................................................................................................................................................ 3819
Figure 34-74. RCR1 Register................................................................................................................................................ 3821
Figure 34-75. XCR2 Register................................................................................................................................................ 3822
Figure 34-76. XCR1 Register................................................................................................................................................ 3824
Figure 34-77. SRGR2 Register..............................................................................................................................................3825
Figure 34-78. SRGR1 Register..............................................................................................................................................3827
Figure 34-79. MCR2 Register................................................................................................................................................3828
Figure 34-80. MCR1 Register................................................................................................................................................3830
Figure 34-81. RCERA Register............................................................................................................................................. 3832
Figure 34-82. RCERB Register............................................................................................................................................. 3833
Figure 34-83. XCERA Register..............................................................................................................................................3834
Figure 34-84. XCERB Register..............................................................................................................................................3835
Figure 34-85. PCR Register.................................................................................................................................................. 3836
Figure 34-86. RCERC Register............................................................................................................................................. 3839
Figure 34-87. RCERD Register............................................................................................................................................. 3840
Figure 34-88. XCERC Register............................................................................................................................................. 3841
Figure 34-89. XCERD Register............................................................................................................................................. 3842
Figure 34-90. RCERE Register............................................................................................................................................. 3843
Figure 34-91. RCERF Register..............................................................................................................................................3844
Figure 34-92. XCERE Register..............................................................................................................................................3845
Figure 34-93. XCERF Register..............................................................................................................................................3846
Figure 34-94. RCERG Register............................................................................................................................................. 3847
Figure 34-95. RCERH Register............................................................................................................................................. 3848
Figure 34-96. XCERG Register............................................................................................................................................. 3849
Figure 34-97. XCERH Register............................................................................................................................................. 3850
Figure 34-98. MFFINT Register.............................................................................................................................................3851
Figure 35-1. PMBus Module Block Diagram..........................................................................................................................3857
Figure 35-2. Quick Command Message................................................................................................................................ 3859
Figure 35-3. Send Byte Message With and Without PEC..................................................................................................... 3859
Figure 35-4. Receive Byte Message With and Without PEC.................................................................................................3860
Figure 35-5. Write Byte and Write Word Messages With and Without PEC..........................................................................3860
Figure 35-6. Read Byte and Read Word Messages With and Without PEC......................................................................... 3861

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Figure 35-7. Process Call Message With and Without PEC..................................................................................................3862

Figure 35-8. Block Write Message With and Without PEC.................................................................................................... 3862
Figure 35-9. Block Read Message With and Without PEC....................................................................................................3863
Figure 35-10. Block Write-Block Read Process Call Message With and Without PEC......................................................... 3864
Figure 35-11. Alert Response Message.................................................................................................................................3864
Figure 35-12. Extended Command Write Byte and Write Word Messages With and Without PEC...................................... 3865
Figure 35-13. Extended Command Read Byte and Read Word Messages With and Without PEC......................................3866
Figure 35-14. Group Command Message With and Without PEC........................................................................................ 3867
Figure 35-15. Quick Command Message.............................................................................................................................. 3868
Figure 35-16. Send Byte Message With and Without PEC................................................................................................... 3869
Figure 35-17. Receive Byte Message With and Without PEC...............................................................................................3869
Figure 35-18. Write Byte and Write Word Messages With and Without PEC........................................................................3870
Figure 35-19. Read Byte and Read Word Messages With and Without PEC....................................................................... 3871
Figure 35-20. Process Call Message With and Without PEC................................................................................................3872
Figure 35-21. Block Write Message With and Without PEC.................................................................................................. 3873
Figure 35-22. Block Read Message With and Without PEC..................................................................................................3874
Figure 35-23. Block Write-Block Read Process Call Message With and Without PEC......................................................... 3875
Figure 35-24. Alert Response Message................................................................................................................................ 3875
Figure 35-25. Extended Command Write Byte and Write Word Messages With and Without PEC...................................... 3876
Figure 35-26. Extended Command Read Byte and Read Word Messages With and Without PEC......................................3877
Figure 35-27. Group Command Message With and Without PEC........................................................................................ 3878
Figure 35-28. PMBMC Register.............................................................................................................................................3881
Figure 35-29. PMBTXBUF Register...................................................................................................................................... 3882
Figure 35-30. PMBRXBUF Register...................................................................................................................................... 3883
Figure 35-31. PMBACK Register...........................................................................................................................................3884
Figure 35-32. PMBSTS Register........................................................................................................................................... 3885
Figure 35-33. PMBINTM Register......................................................................................................................................... 3887
Figure 35-34. PMBSC Register............................................................................................................................................. 3889
Figure 35-35. PMBHSA Register...........................................................................................................................................3891
Figure 35-36. PMBCTRL Register.........................................................................................................................................3892
Figure 35-37. PMBTIMCTL Register..................................................................................................................................... 3894
Figure 35-38. PMBTIMCLK Register..................................................................................................................................... 3895
Figure 35-39. PMBTIMSTSETUP Register........................................................................................................................... 3896
Figure 35-40. PMBTIMBIDLE Register..................................................................................................................................3897
Figure 35-41. PMBTIMLOWTIMOUT Register...................................................................................................................... 3898
Figure 35-42. PMBTIMHIGHTIMOUT Register..................................................................................................................... 3899
Figure 36-1. SCI CPU Interface.............................................................................................................................................3902
Figure 36-2. Serial Communications Interface (SCI) Module Block Diagram........................................................................3904
Figure 36-3. Typical SCI Data Frame Formats...................................................................................................................... 3906
Figure 36-4. Idle-Line Multiprocessor Communication Format..............................................................................................3908
Figure 36-5. Double-Buffered WUT and TXSHF................................................................................................................... 3909
Figure 36-6. Address-Bit Multiprocessor Communication Format......................................................................................... 3910
Figure 36-7. SCI Asynchronous Communications Format.....................................................................................................3911
Figure 36-8. SCI RX Signals in Communication Modes........................................................................................................ 3911
Figure 36-9. SCI TX Signals in Communications Mode........................................................................................................ 3912
Figure 36-10. SCI FIFO Interrupt Flags and Enable Logic.................................................................................................... 3915
Figure 36-11. SCICCR Register.............................................................................................................................................3921
Figure 36-12. SCICTL1 Register........................................................................................................................................... 3923
Figure 36-13. SCIHBAUD Register....................................................................................................................................... 3925
Figure 36-14. SCILBAUD Register........................................................................................................................................ 3926
Figure 36-15. SCICTL2 Register........................................................................................................................................... 3927
Figure 36-16. SCIRXST Register.......................................................................................................................................... 3929
Figure 36-17. SCIRXEMU Register....................................................................................................................................... 3931
Figure 36-18. SCIRXBUF Register........................................................................................................................................3932
Figure 36-19. SCITXBUF Register........................................................................................................................................ 3933
Figure 36-20. SCIFFTX Register........................................................................................................................................... 3934
Figure 36-21. SCIFFRX Register...........................................................................................................................................3936
Figure 36-22. SCIFFCT Register...........................................................................................................................................3938
Figure 36-23. SCIPRI Register.............................................................................................................................................. 3939
Figure 37-1. SPI CPU Interface............................................................................................................................................. 3945
Figure 37-2. SPI Interrupt Flags and Enable Logic Generation.............................................................................................3948

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Figure 37-3. SPI DMA Trigger Diagram.................................................................................................................................3949

Figure 37-4. SPI Master/Slave Connection........................................................................................................................... 3950
Figure 37-5. SPI Module Master Configuration..................................................................................................................... 3952
Figure 37-6. SPI Module Slave Configuration....................................................................................................................... 3953
Figure 37-7. SPICLK Signal Options..................................................................................................................................... 3956
Figure 37-8. SPI: SPICLK-LSPCLK Characteristic when (BRR + 1) is Odd, BRR > 3, and CLKPOLARITY = 1.................. 3957
Figure 37-9. SPI 3-wire Master Mode....................................................................................................................................3959
Figure 37-10. SPI 3-wire Slave Mode....................................................................................................................................3960
Figure 37-11. Five Bits per Character.................................................................................................................................... 3963
Figure 37-12. SPI Digital Audio Receiver Configuration Using Two SPIs............................................................................. 3966
Figure 37-13. Standard Right-Justified Digital Audio Data Format........................................................................................3966
Figure 37-14. SPICCR Register............................................................................................................................................ 3971
Figure 37-15. SPICTL Register............................................................................................................................................. 3973
Figure 37-16. SPISTS Register............................................................................................................................................. 3975
Figure 37-17. SPIBRR Register.............................................................................................................................................3977
Figure 37-18. SPIRXEMU Register....................................................................................................................................... 3978
Figure 37-19. SPIRXBUF Register........................................................................................................................................ 3979
Figure 37-20. SPITXBUF Register........................................................................................................................................ 3980
Figure 37-21. SPIDAT Register............................................................................................................................................. 3981
Figure 37-22. SPIFFTX Register........................................................................................................................................... 3982
Figure 37-23. SPIFFRX Register...........................................................................................................................................3984
Figure 37-24. SPIFFCT Register........................................................................................................................................... 3986
Figure 37-25. SPIPRI Register.............................................................................................................................................. 3987
Figure 38-1. USB Block Diagram...........................................................................................................................................3993
Figure 38-2. USB Scheme.....................................................................................................................................................3994
Figure 38-3. USBFADDR Register........................................................................................................................................ 4017
Figure 38-4. USBPOWER Register....................................................................................................................................... 4018
Figure 38-5. USBTXIS Register.............................................................................................................................................4019
Figure 38-6. USBRXIS Register............................................................................................................................................ 4020
Figure 38-7. USBTXIE Register.............................................................................................................................................4021
Figure 38-8. USBRXIE Register............................................................................................................................................ 4022
Figure 38-9. USBIS Register................................................................................................................................................. 4023
Figure 38-10. USBIE Register............................................................................................................................................... 4024
Figure 38-11. USBFRAME Register...................................................................................................................................... 4025
Figure 38-12. USBEPIDX Register........................................................................................................................................4026
Figure 38-13. USBTEST Register......................................................................................................................................... 4027
Figure 38-14. USBFIFO0 Register........................................................................................................................................ 4028
Figure 38-15. USBFIFO1 Register........................................................................................................................................ 4029
Figure 38-16. USBFIFO2 Register........................................................................................................................................ 4030
Figure 38-17. USBFIFO3 Register........................................................................................................................................ 4031
Figure 38-18. USBDEVCTL Register.................................................................................................................................... 4032
Figure 38-19. USBTXFIFOSZ Register................................................................................................................................. 4034
Figure 38-20. USBRXFIFOSZ Register.................................................................................................................................4035
Figure 38-21. USBTXFIFOADD Register.............................................................................................................................. 4036
Figure 38-22. USBRXFIFOADD Register..............................................................................................................................4045
Figure 38-23. USBCONTIM Register.................................................................................................................................... 4054
Figure 38-24. USBFSEOF Register.......................................................................................................................................4055
Figure 38-25. USBLSEOF Register.......................................................................................................................................4056
Figure 38-26. USBTXFUNCADDR0 Register........................................................................................................................4057
Figure 38-27. USBTXHUBADDR0 Register.......................................................................................................................... 4058
Figure 38-28. USBTXHUBPORT0 Register...........................................................................................................................4059
Figure 38-29. USBTXFUNCADDR1 Register........................................................................................................................4060
Figure 38-30. USBTXHUBADDR1 Register.......................................................................................................................... 4061
Figure 38-31. USBTXHUBPORT1 Register...........................................................................................................................4062
Figure 38-32. USBRXFUNCADDR1 Register....................................................................................................................... 4063
Figure 38-33. USBRXHUBADDR1 Register..........................................................................................................................4064
Figure 38-34. USBRXHUBPORT1 Register.......................................................................................................................... 4065
Figure 38-35. USBTXFUNCADDR2 Register........................................................................................................................4066
Figure 38-36. USBTXHUBADDR2 Register.......................................................................................................................... 4067
Figure 38-37. USBTXHUBPORT2 Register...........................................................................................................................4068
Figure 38-38. USBRXFUNCADDR2 Register....................................................................................................................... 4069

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Figure 38-39. USBRXHUBADDR2 Register..........................................................................................................................4070

Figure 38-40. USBRXHUBPORT2 Register.......................................................................................................................... 4071
Figure 38-41. USBTXFUNCADDR3 Register........................................................................................................................4072
Figure 38-42. USBTXHUBADDR3 Register.......................................................................................................................... 4073
Figure 38-43. USBTXHUBPORT3 Register...........................................................................................................................4074
Figure 38-44. USBRXFUNCADDR3 Register....................................................................................................................... 4075
Figure 38-45. USBRXHUBADDR3 Register..........................................................................................................................4076
Figure 38-46. USBRXHUBPORT3 Register.......................................................................................................................... 4077
Figure 38-47. USBCSRL0 Register....................................................................................................................................... 4078
Figure 38-48. USBCSRH0 Register...................................................................................................................................... 4080
Figure 38-49. USBCOUNT0 Register....................................................................................................................................4081
Figure 38-50. USBTYPE0 Register....................................................................................................................................... 4082
Figure 38-51. USBNAKLMT Register.................................................................................................................................... 4083
Figure 38-52. USBTXMAXP1 Register..................................................................................................................................4084
Figure 38-53. USBTXCSRL1 Register.................................................................................................................................. 4085
Figure 38-54. USBTXCSRH1 Register..................................................................................................................................4087
Figure 38-55. USBRXMAXP1 Register................................................................................................................................. 4089
Figure 38-56. USBRXCSRL1 Register.................................................................................................................................. 4090
Figure 38-57. USBRXCSRH1 Register................................................................................................................................. 4092
Figure 38-58. USBRXCOUNT1 Register...............................................................................................................................4094
Figure 38-59. USBTXTYPE1 Register...................................................................................................................................4095
Figure 38-60. USBTXINTERVAL1 Register...........................................................................................................................4096
Figure 38-61. USBRXTYPE1 Register.................................................................................................................................. 4097
Figure 38-62. USBRXINTERVAL1 Register.......................................................................................................................... 4098
Figure 38-63. USBTXMAXP2 Register..................................................................................................................................4099
Figure 38-64. USBTXCSRL2 Register.................................................................................................................................. 4100
Figure 38-65. USBTXCSRH2 Register..................................................................................................................................4102
Figure 38-66. USBRXMAXP2 Register................................................................................................................................. 4104
Figure 38-67. USBRXCSRL2 Register.................................................................................................................................. 4105
Figure 38-68. USBRXCSRH2 Register................................................................................................................................. 4107
Figure 38-69. USBRXCOUNT2 Register...............................................................................................................................4109
Figure 38-70. USBTXTYPE2 Register................................................................................................................................... 4110
Figure 38-71. USBTXINTERVAL2 Register........................................................................................................................... 4111
Figure 38-72. USBRXTYPE2 Register...................................................................................................................................4112
Figure 38-73. USBRXINTERVAL2 Register...........................................................................................................................4113
Figure 38-74. USBTXMAXP3 Register.................................................................................................................................. 4114
Figure 38-75. USBTXCSRL3 Register...................................................................................................................................4115
Figure 38-76. USBTXCSRH3 Register.................................................................................................................................. 4117
Figure 38-77. USBRXMAXP3 Register..................................................................................................................................4119
Figure 38-78. USBRXCSRL3 Register.................................................................................................................................. 4120
Figure 38-79. USBRXCSRH3 Register................................................................................................................................. 4122
Figure 38-80. USBRXCOUNT3 Register...............................................................................................................................4124
Figure 38-81. USBTXTYPE3 Register...................................................................................................................................4125
Figure 38-82. USBTXINTERVAL3 Register...........................................................................................................................4126
Figure 38-83. USBRXTYPE3 Register.................................................................................................................................. 4127
Figure 38-84. USBRXINTERVAL3 Register.......................................................................................................................... 4128
Figure 38-85. USBRQPKTCOUNT1 Register....................................................................................................................... 4129
Figure 38-86. USBRQPKTCOUNT2 Register....................................................................................................................... 4130
Figure 38-87. USBRQPKTCOUNT3 Register....................................................................................................................... 4131
Figure 38-88. USBRXDPKTBUFDIS Register.......................................................................................................................4132
Figure 38-89. USBTXDPKTBUFDIS Register....................................................................................................................... 4133
Figure 38-90. USBEPC Register........................................................................................................................................... 4134
Figure 38-91. USBEPCRIS Register..................................................................................................................................... 4136
Figure 38-92. USBEPCIM Register....................................................................................................................................... 4137
Figure 38-93. USBEPCISC Register..................................................................................................................................... 4138
Figure 38-94. USBDRRIS Register....................................................................................................................................... 4139
Figure 38-95. USBDRIM Register......................................................................................................................................... 4140
Figure 38-96. USBDRISC Register....................................................................................................................................... 4141
Figure 38-97. USBGPCS Register........................................................................................................................................ 4142
Figure 38-98. USBVDC Register........................................................................................................................................... 4143
Figure 38-99. USBVDCRIS Register..................................................................................................................................... 4144

62 TMS320F2838x Real-Time Microcontrollers With Connectivity Manager SPRUII0E – MAY 2019 – REVISED SEPTEMBER 2023
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Figure 38-100. USBVDCIM Register..................................................................................................................................... 4145

Figure 38-101. USBVDCISC Register................................................................................................................................... 4146
Figure 38-102. USBIDVRIS Register.....................................................................................................................................4147
Figure 38-103. USBIDVIM Register.......................................................................................................................................4148
Figure 38-104. USBIDVISC Register.....................................................................................................................................4149
Figure 38-105. USBDMASEL Register..................................................................................................................................4150
Figure 38-106. USB_GLB_INT_EN Register.........................................................................................................................4151
Figure 38-107. USB_GLB_INT_FLG Register.......................................................................................................................4152
Figure 38-108. USB_GLB_INT_FLG_CLR Register............................................................................................................. 4153
Figure 38-109. USBDMARIS Register...................................................................................................................................4154
Figure 38-110. USBDMAIM Register..................................................................................................................................... 4155
Figure 38-111. USBDMAISC Register................................................................................................................................... 4156
Figure 39-1. F2838x Block Diagram...................................................................................................................................... 4176
Figure 40-1. Connectivity Manager Block Diagram............................................................................................................... 4179
Figure 41-1. CM Clocking System......................................................................................................................................... 4184
Figure 41-2. CM Subsystem NMI Sources and NMIWD........................................................................................................4189
Figure 41-3. CM CPU-Timers................................................................................................................................................ 4195
Figure 41-4. CM CPU-Timers Interrupt Signals..................................................................................................................... 4195
Figure 41-5. CM Memory Block Diagram.............................................................................................................................. 4196
Figure 41-6. Mem allocate logic.............................................................................................................................................4197
Figure 41-7. Interleaving........................................................................................................................................................4198
Figure 41-8. Content of Each Memory Location for ECC Memories..................................................................................... 4199
Figure 41-9. Content of Each Memory Location for Parity Memories....................................................................................4199
Figure 41-10. ROM Parity Checking Logic............................................................................................................................ 4201
Figure 41-11. CM Block Diagram...........................................................................................................................................4202
Figure 41-12. Unaligned Start Address................................................................................................................................. 4203
Figure 41-13. Overlapping Regions.......................................................................................................................................4203
Figure 41-14. Sub-Regions....................................................................................................................................................4204
Figure 41-15. Programmers Model Memory Map..................................................................................................................4204
Figure 41-16. Debug Trace....................................................................................................................................................4205
Figure 41-17. CxLOCK Register............................................................................................................................................4209
Figure 41-18. CxTEST Register............................................................................................................................................ 4210
Figure 41-19. CxINIT Register............................................................................................................................................... 4211
Figure 41-20. CxINITDONE Register.................................................................................................................................... 4212
Figure 41-21. CMMSGxLOCK Register.................................................................................................................................4213
Figure 41-22. CMMSGxTEST Register................................................................................................................................. 4214
Figure 41-23. CMMSGxINIT Register....................................................................................................................................4216
Figure 41-24. CMMSGxINITDONE Register......................................................................................................................... 4217
Figure 41-25. SxGROUP1_LOCK Register...........................................................................................................................4218
Figure 41-26. SxGROUP1_TEST Register........................................................................................................................... 4219
Figure 41-27. SxGROUP1_INIT Register..............................................................................................................................4221
Figure 41-28. SxGROUP1_INITDONE Register................................................................................................................... 4222
Figure 41-29. ROM_LOCK Register......................................................................................................................................4223
Figure 41-30. ROM_TEST Register...................................................................................................................................... 4224
Figure 41-31. ROM_FORCE_ERROR Register.................................................................................................................... 4225
Figure 41-32. PERI_MEM_TEST_LOCK Register................................................................................................................ 4226
Figure 41-33. PERI_MEM_TEST_CONTROL Register........................................................................................................ 4227
Figure 41-34. DIAGERRFLG Register...................................................................................................................................4229
Figure 41-35. DIAGERRCLR Register.................................................................................................................................. 4231
Figure 41-36. DIAGERRADDR Register............................................................................................................................... 4232
Figure 41-37. UCERRFLG Register...................................................................................................................................... 4235
Figure 41-38. UCERRSET Register...................................................................................................................................... 4237
Figure 41-39. UCERRCLR Register...................................................................................................................................... 4238
Figure 41-40. UCM4EADDR Register................................................................................................................................... 4239
Figure 41-41. UCEMACEADDR Register..............................................................................................................................4240
Figure 41-42. UCuDMAEADDR Register.............................................................................................................................. 4241
Figure 41-43. UCEtherCATMEMREADDR Register..............................................................................................................4242
Figure 41-44. UCEMACMEMREADDR Register...................................................................................................................4243
Figure 41-45. BUSFAULTFLG Register.................................................................................................................................4244
Figure 41-46. BUSFAULTCLR Register.................................................................................................................................4245
Figure 41-47. M4BUSFAULTADDR Register.........................................................................................................................4246

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Figure 41-48. uDMABUSFAULTADDR Register....................................................................................................................4247

Figure 41-49. EMACBUSFAULTADDR Register................................................................................................................... 4248
Figure 41-50. CERRFLG Register.........................................................................................................................................4249
Figure 41-51. CERRSET Register.........................................................................................................................................4250
Figure 41-52. CERRCLR Register.........................................................................................................................................4251
Figure 41-53. CM4EADDR Register......................................................................................................................................4252
Figure 41-54. CEMACEADDR Register................................................................................................................................ 4253
Figure 41-55. CuDMAEADDR Register.................................................................................................................................4254
Figure 41-56. CERRCNT Register........................................................................................................................................ 4255
Figure 41-57. CERRTHRES Register....................................................................................................................................4256
Figure 41-58. CEINTFLG Register........................................................................................................................................ 4257
Figure 41-59. CEINTSET Register........................................................................................................................................ 4258
Figure 41-60. CEINTCLR Register........................................................................................................................................ 4259
Figure 41-61. CEINTEN Register.......................................................................................................................................... 4260
Figure 41-62. CMPCLKCR0 Register....................................................................................................................................4263
Figure 41-63. CMPCLKCR1 Register....................................................................................................................................4264
Figure 41-64. CMPCLKCR2 Register....................................................................................................................................4266
Figure 41-65. CMSOFTPRESET0 Register.......................................................................................................................... 4268
Figure 41-66. CMSOFTPRESET1 Register.......................................................................................................................... 4269
Figure 41-67. CMSOFTPRESET2 Register.......................................................................................................................... 4271
Figure 41-68. CMCLKSTOPREQ0 Register.......................................................................................................................... 4272
Figure 41-69. CMCLKSTOPREQ1 Register.......................................................................................................................... 4273
Figure 41-70. CMCLKSTOPREQ2 Register.......................................................................................................................... 4274
Figure 41-71. CMCLKSTOPACK0 Register...........................................................................................................................4275
Figure 41-72. CMCLKSTOPACK1 Register...........................................................................................................................4276
Figure 41-73. CMCLKSTOPACK2 Register...........................................................................................................................4277
Figure 41-74. MCANWAKESTATUS Register....................................................................................................................... 4278
Figure 41-75. MCANWAKESTATUSCLR Register................................................................................................................ 4279
Figure 41-76. PALLOCATESTS Register.............................................................................................................................. 4280
Figure 41-77. CMRESCCLR Register................................................................................................................................... 4281
Figure 41-78. CMRESC Register.......................................................................................................................................... 4283
Figure 41-79. CMSYSCTLLOCK Register.............................................................................................................................4285
Figure 41-80. TIM Register....................................................................................................................................................4287
Figure 41-81. PRD Register.................................................................................................................................................. 4288
Figure 41-82. TCR Register...................................................................................................................................................4289
Figure 41-83. TPR Register...................................................................................................................................................4291
Figure 41-84. MPU_CONTROL_REG Register.....................................................................................................................4294
Figure 41-85. ACC_VIO_INTEN Register............................................................................................................................. 4295
Figure 41-86. ACC_VIO_FLAGS Register............................................................................................................................ 4296
Figure 41-87. ACC_VIO_FLAGS_SET Register................................................................................................................... 4297
Figure 41-88. ACC_VIO_FLAGS_CLR Register................................................................................................................... 4298
Figure 41-89. ACC_VIO_ADDR_REG Register.................................................................................................................... 4299
Figure 41-90. REGION0_STARTADDRESSS Register.........................................................................................................4300
Figure 41-91. REGION0_CONFIG Register..........................................................................................................................4301
Figure 41-92. REGION1_STARTADDRESSS Register.........................................................................................................4303
Figure 41-93. REGION1_CONFIG Register..........................................................................................................................4304
Figure 41-94. REGION2_STARTADDRESSS Register.........................................................................................................4306
Figure 41-95. REGION2_CONFIG Register..........................................................................................................................4307
Figure 41-96. REGION3_STARTADDRESSS Register.........................................................................................................4309
Figure 41-97. REGION3_CONFIG Register..........................................................................................................................4310
Figure 41-98. REGION4_STARTADDRESSS Register.........................................................................................................4312
Figure 41-99. REGION4_CONFIG Register..........................................................................................................................4313
Figure 41-100. REGION5_STARTADDRESSS Register.......................................................................................................4315
Figure 41-101. REGION5_CONFIG Register........................................................................................................................4316
Figure 41-102. REGION6_STARTADDRESSS Register.......................................................................................................4318
Figure 41-103. REGION6_CONFIG Register........................................................................................................................4319
Figure 41-104. REGION7_STARTADDRESSS Register.......................................................................................................4321
Figure 41-105. REGION7_CONFIG Register........................................................................................................................4322
Figure 41-106. CMNMICFG Register.................................................................................................................................... 4325
Figure 41-107. CMNMIFLG Register.....................................................................................................................................4326
Figure 41-108. CMNMIFLGCLR Register..............................................................................................................................4328

64 TMS320F2838x Real-Time Microcontrollers With Connectivity Manager SPRUII0E – MAY 2019 – REVISED SEPTEMBER 2023
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Figure 41-109. CMNMIFLGFRC Register............................................................................................................................. 4330

Figure 41-110. CMNMIWDCNT Register...............................................................................................................................4332
Figure 41-111. CMNMIWDPRD Register...............................................................................................................................4333
Figure 41-112. CMNMISHDWFLG Register.......................................................................................................................... 4334
Figure 41-113. NVIC_ISER0 Register................................................................................................................................... 4338
Figure 41-114. NVIC_ISER1 Register................................................................................................................................... 4343
Figure 41-115. NVIC_ICER0 Register................................................................................................................................... 4348
Figure 41-116. NVIC_ICER1 Register................................................................................................................................... 4353
Figure 41-117. NVIC_ISPR0 Register................................................................................................................................... 4358
Figure 41-118. NVIC_ISPR1 Register................................................................................................................................... 4363
Figure 41-119. NVIC_ISPR2 Register................................................................................................................................... 4368
Figure 41-120. NVIC_ICPR0 Register...................................................................................................................................4373
Figure 41-121. NVIC_ICPR1 Register...................................................................................................................................4378
Figure 41-122. NVIC_IABR0 Register................................................................................................................................... 4383
Figure 41-123. NVIC_IABR1 Register................................................................................................................................... 4386
Figure 41-124. NVIC_IPR0 Register..................................................................................................................................... 4389
Figure 41-125. NVIC_IPR1 Register..................................................................................................................................... 4390
Figure 41-126. NVIC_IPR2 Register..................................................................................................................................... 4391
Figure 41-127. NVIC_IPR3 Register..................................................................................................................................... 4392
Figure 41-128. NVIC_IPR4 Register..................................................................................................................................... 4393
Figure 41-129. NVIC_IPR5 Register..................................................................................................................................... 4394
Figure 41-130. NVIC_IPR6 Register..................................................................................................................................... 4395
Figure 41-131. NVIC_IPR7 Register..................................................................................................................................... 4396
Figure 41-132. NVIC_IPR8 Register..................................................................................................................................... 4397
Figure 41-133. NVIC_IPR9 Register..................................................................................................................................... 4398
Figure 41-134. NVIC_IPR10 Register................................................................................................................................... 4399
Figure 41-135. NVIC_IPR11 Register....................................................................................................................................4400
Figure 41-136. NVIC_IPR12 Register................................................................................................................................... 4401
Figure 41-137. NVIC_IPR13 Register................................................................................................................................... 4402
Figure 41-138. NVIC_IPR14 Register................................................................................................................................... 4403
Figure 41-139. NVIC_IPR15 Register................................................................................................................................... 4404
Figure 41-140. STIR Register................................................................................................................................................4405
Figure 41-141. ACTLR Register............................................................................................................................................ 4408
Figure 41-142. CPUID Register.............................................................................................................................................4409
Figure 41-143. ICSR Register............................................................................................................................................... 4410
Figure 41-144. VTOR Register.............................................................................................................................................. 4412
Figure 41-145. AIRCR Register.............................................................................................................................................4413
Figure 41-146. SCR Register................................................................................................................................................ 4415
Figure 41-147. CCR Register................................................................................................................................................ 4416
Figure 41-148. SHPR1 Register............................................................................................................................................ 4418
Figure 41-149. SHPR2 Register............................................................................................................................................ 4419
Figure 41-150. SHPR3 Register............................................................................................................................................ 4420
Figure 41-151. SHCSRS Register......................................................................................................................................... 4421
Figure 41-152. CFSR Register.............................................................................................................................................. 4425
Figure 41-153. HFSR Register.............................................................................................................................................. 4429
Figure 41-154. MMFAR Register........................................................................................................................................... 4430
Figure 41-155. BFAR Register...............................................................................................................................................4431
Figure 41-156. AFSR Register.............................................................................................................................................. 4432
Figure 41-157. MMSR Register............................................................................................................................................. 4434
Figure 41-158. BFSR Register.............................................................................................................................................. 4436
Figure 41-159. UFSR Register.............................................................................................................................................. 4438
Figure 41-160. SYST_CSR Register..................................................................................................................................... 4441
Figure 41-161. SYST_RVR Register..................................................................................................................................... 4442
Figure 41-162. SYST_CVR Register..................................................................................................................................... 4443
Figure 41-163. SYST_CALIB Register.................................................................................................................................. 4444
Figure 41-164. MPU_TYPE Register.....................................................................................................................................4446
Figure 41-165. MPU_CTRL Register.....................................................................................................................................4447
Figure 41-166. MPU_RNR Register...................................................................................................................................... 4448
Figure 41-167. MPU_RBAR Register.................................................................................................................................... 4449
Figure 41-168. MPU_RASR Register.................................................................................................................................... 4450
Figure 41-169. MPU_RBAR_A1 Register..............................................................................................................................4454

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Figure 41-170. MPU_RASR_A1 Register..............................................................................................................................4455

Figure 41-171. MPU_RBAR_A2 Register..............................................................................................................................4459
Figure 41-172. MPU_RASR_A2 Register..............................................................................................................................4460
Figure 41-173. MPU_RBAR_A3 Register..............................................................................................................................4464
Figure 41-174. MPU_RASR_A3 Register..............................................................................................................................4465
Figure 41-175. SCSR Register.............................................................................................................................................. 4470
Figure 41-176. WDCNTR Register........................................................................................................................................ 4471
Figure 41-177. WDKEY Register...........................................................................................................................................4472
Figure 41-178. WDCR Register.............................................................................................................................................4473
Figure 41-179. WDWCR Register......................................................................................................................................... 4475
Figure 42-1. AES Block Diagram...........................................................................................................................................4478
Figure 42-2. AES - GCM Operation.......................................................................................................................................4482
Figure 42-3. AES - CCM Operation....................................................................................................................................... 4483
Figure 42-4. AES - XTS Operation........................................................................................................................................ 4484
Figure 42-5. AES - ECB Feedback Mode..............................................................................................................................4485
Figure 42-6. AES - CBC Feedback Mode..............................................................................................................................4486
Figure 42-7. AES Encryption With CTR/ICM Mode............................................................................................................... 4487
Figure 42-8. AES - CFB Feedback Mode.............................................................................................................................. 4488
Figure 42-9. AES - F8 Mode..................................................................................................................................................4489
Figure 42-10. AES - F9 Operation......................................................................................................................................... 4490
Figure 42-11. AES - CBC-MAC Authentication Mode............................................................................................................4491
Figure 42-12. AES Polling Mode........................................................................................................................................... 4495
Figure 42-13. AES Interrupt Service......................................................................................................................................4497
Figure 42-14. AESDMAINTEN Register................................................................................................................................ 4501
Figure 42-15. AESDMASTATUS Register............................................................................................................................. 4502
Figure 42-16. AESDMASTATUSCLR Register...................................................................................................................... 4503
Figure 42-17. AES_KEY2_6 Register....................................................................................................................................4506
Figure 42-18. AES_KEY2_7 Register....................................................................................................................................4507
Figure 42-19. AES_KEY2_4 Register....................................................................................................................................4508
Figure 42-20. AES_KEY2_5 Register....................................................................................................................................4509
Figure 42-21. AES_KEY2_2 Register....................................................................................................................................4510
Figure 42-22. AES_KEY2_3 Register.................................................................................................................................... 4511
Figure 42-23. AES_KEY2_0 Register....................................................................................................................................4512
Figure 42-24. AES_KEY2_1 Register....................................................................................................................................4513
Figure 42-25. AES_KEY1_6 Register....................................................................................................................................4514
Figure 42-26. AES_KEY1_7 Register....................................................................................................................................4515
Figure 42-27. AES_KEY1_4 Register....................................................................................................................................4516
Figure 42-28. AES_KEY1_5 Register....................................................................................................................................4517
Figure 42-29. AES_KEY1_2 Register....................................................................................................................................4518
Figure 42-30. AES_KEY1_3 Register....................................................................................................................................4519
Figure 42-31. AES_KEY1_0 Register....................................................................................................................................4520
Figure 42-32. AES_KEY1_1 Register....................................................................................................................................4521
Figure 42-33. AES_IV_IN_OUT_0 Register.......................................................................................................................... 4522
Figure 42-34. AES_IV_IN_OUT_1 Register.......................................................................................................................... 4523
Figure 42-35. AES_IV_IN_OUT_2 Register.......................................................................................................................... 4524
Figure 42-36. AES_IV_IN_OUT_3 Register.......................................................................................................................... 4525
Figure 42-37. AES_CTRL Register....................................................................................................................................... 4526
Figure 42-38. AES_C_LENGTH_0 Register..........................................................................................................................4530
Figure 42-39. AES_C_LENGTH_1 Register..........................................................................................................................4531
Figure 42-40. AES_AUTH_LENGTH Register...................................................................................................................... 4532
Figure 42-41. AES_DATA_IN_OUT_0 Register.....................................................................................................................4533
Figure 42-42. AES_DATA_IN_OUT_1 Register.....................................................................................................................4534
Figure 42-43. AES_DATA_IN_OUT_2 Register.....................................................................................................................4535
Figure 42-44. AES_DATA_IN_OUT_3 Register.....................................................................................................................4536
Figure 42-45. AES_TAG_OUT_0 Register............................................................................................................................ 4537
Figure 42-46. AES_TAG_OUT_1 Register............................................................................................................................ 4538
Figure 42-47. AES_TAG_OUT_2 Register............................................................................................................................ 4539
Figure 42-48. AES_TAG_OUT_3 Register............................................................................................................................ 4540
Figure 42-49. AES_REV Register......................................................................................................................................... 4541
Figure 42-50. AES_SYSCONFIG Register............................................................................................................................4542
Figure 42-51. AES_SYSSTATUS Register............................................................................................................................ 4544

66 TMS320F2838x Real-Time Microcontrollers With Connectivity Manager SPRUII0E – MAY 2019 – REVISED SEPTEMBER 2023
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Figure 42-52. AES_IRQSTATUS Register.............................................................................................................................4545

Figure 42-53. AES_IRQENABLE Register............................................................................................................................ 4546
Figure 42-54. AES_DIRTY_BITS Register............................................................................................................................ 4547
Figure 43-1. MII Mode Signals...............................................................................................................................................4553
Figure 43-2. RMII Mode Signals............................................................................................................................................ 4554
Figure 43-3. RevMII Mode Signals........................................................................................................................................ 4556
Figure 43-4. Ethernet Clocking.............................................................................................................................................. 4557
Figure 43-5. RMII Clocking.................................................................................................................................................... 4558
Figure 43-6. RevMII Clocking................................................................................................................................................ 4558
Figure 43-7. Trigger Sources for Auxiliary Timestamping......................................................................................................4559
Figure 43-8. MAC Interrupt Sources......................................................................................................................................4560
Figure 43-9. Combined SBD_Intr Sources............................................................................................................................ 4561
Figure 43-10. Networked Time Synchronization....................................................................................................................4568
Figure 43-11. Propagation Delay Calculation in Clocks Supporting Peer-to-Peer Path Correction.......................................4569
Figure 43-12. System Time Update Using Fine Method........................................................................................................4578
Figure 43-13. Packet Filtering................................................................................................................................................4581
Figure 43-14. TCP Segmentation Overview.......................................................................................................................... 4594
Figure 43-15. Header and Payload Fields of Segmented Packets........................................................................................4597
Figure 43-16. Wakeup Filter Register Layout........................................................................................................................ 4600
Figure 43-17. LPI Transitions on Transmit.............................................................................................................................4603
Figure 43-18. LPI Transitions on Receive..............................................................................................................................4605
Figure 43-19. Descriptor Ring Structure................................................................................................................................ 4613
Figure 43-20. DMA Descriptor Ring.......................................................................................................................................4614
Figure 43-21. Transmit Normal Descriptor Read Format.......................................................................................................4615
Figure 43-22. Transmit Write Back Format............................................................................................................................4620
Figure 43-23. Transmit Context Descriptor Format............................................................................................................... 4624
Figure 43-24. Receive Normal Descriptor Read Format....................................................................................................... 4627
Figure 43-25. Receive Normal Write Back Format................................................................................................................ 4630
Figure 43-26. Receive Context Descriptor Format................................................................................................................ 4637
Figure 43-27. ETHERNETSS_IPREVNUM Register.............................................................................................................4657
Figure 43-28. ETHERNETSS_CTRLSTS Register............................................................................................................... 4658
Figure 43-29. ETHERNETSS_PTPTSTRIGSEL0 Register...................................................................................................4660
Figure 43-30. ETHERNETSS_PTPTSTRIGSEL1 Register...................................................................................................4661
Figure 43-31. ETHERNETSS_PTPTSSWTRIG0 Register....................................................................................................4662
Figure 43-32. ETHERNETSS_PTPTSSWTRIG1 Register....................................................................................................4663
Figure 43-33. ETHERNETSS_PTPPPSR0 Register............................................................................................................. 4664
Figure 43-34. ETHERNETSS_PTPPPSR1 Register............................................................................................................. 4665
Figure 43-35. ETHERNETSS_PTP_TSRL Register..............................................................................................................4666
Figure 43-36. ETHERNETSS_PTP_TSRH Register............................................................................................................. 4667
Figure 43-37. ETHERNETSS_PTP_TSWL Register.............................................................................................................4668
Figure 43-38. ETHERNETSS_PTP_TSWH Register............................................................................................................ 4669
Figure 43-39. ETHERNETSS_REVMII_CTRL Register........................................................................................................ 4670
Figure 43-40. MAC_Configuration Register...........................................................................................................................4697
Figure 43-41. MAC_Ext_Configuration Register................................................................................................................... 4703
Figure 43-42. MAC_Packet_Filter Register........................................................................................................................... 4705
Figure 43-43. MAC_Watchdog_Timeout Register................................................................................................................. 4708
Figure 43-44. MAC_Hash_Table_Reg0 Register.................................................................................................................. 4709
Figure 43-45. MAC_Hash_Table_Reg1 Register.................................................................................................................. 4710
Figure 43-46. MAC_VLAN_Tag_Ctrl Register........................................................................................................................4711
Figure 43-47. MAC_VLAN_Tag_Data Register..................................................................................................................... 4713
Figure 43-48. MAC_VLAN_Hash_Table Register..................................................................................................................4715
Figure 43-49. MAC_VLAN_Incl Register............................................................................................................................... 4716
Figure 43-50. MAC_Inner_VLAN_Incl Register.....................................................................................................................4718
Figure 43-51. MAC_Q0_Tx_Flow_Ctrl Register.................................................................................................................... 4720
Figure 43-52. MAC_Rx_Flow_Ctrl Register.......................................................................................................................... 4722
Figure 43-53. MAC_RxQ_Ctrl4 Register............................................................................................................................... 4723
Figure 43-54. MAC_RxQ_Ctrl0 Register............................................................................................................................... 4725
Figure 43-55. MAC_RxQ_Ctrl1 Register............................................................................................................................... 4726
Figure 43-56. MAC_RxQ_Ctrl2 Register............................................................................................................................... 4728
Figure 43-57. MAC_Interrupt_Status Register...................................................................................................................... 4729
Figure 43-58. MAC_Interrupt_Enable Register..................................................................................................................... 4732

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Figure 43-59. MAC_Rx_Tx_Status Register......................................................................................................................... 4734

Figure 43-60. MAC_PMT_Control_Status Register...............................................................................................................4736
Figure 43-61. MAC_RWK_Packet_Filter Register.................................................................................................................4740
Figure 43-62. MAC_LPI_Control_Status Register.................................................................................................................4741
Figure 43-63. MAC_LPI_Timers_Control Register................................................................................................................ 4744
Figure 43-64. MAC_LPI_Entry_Timer Register..................................................................................................................... 4745
Figure 43-65. MAC_1US_Tic_Counter Register....................................................................................................................4746
Figure 43-66. MAC_Version Register.................................................................................................................................... 4747
Figure 43-67. MAC_Debug Register..................................................................................................................................... 4748
Figure 43-68. MAC_HW_Feature0 Register..........................................................................................................................4749
Figure 43-69. MAC_HW_Feature1 Register..........................................................................................................................4752
Figure 43-70. MAC_HW_Feature2 Register..........................................................................................................................4755
Figure 43-71. MAC_HW_Feature3 Register..........................................................................................................................4757
Figure 43-72. MAC_MDIO_Address Register....................................................................................................................... 4759
Figure 43-73. MAC_MDIO_Data Register............................................................................................................................. 4762
Figure 43-74. MAC_ARP_Address Register......................................................................................................................... 4763
Figure 43-75. MAC_CSR_SW_Ctrl Register......................................................................................................................... 4764
Figure 43-76. MAC_Ext_Cfg1 Register................................................................................................................................. 4765
Figure 43-77. MAC_Address0_High Register....................................................................................................................... 4766
Figure 43-78. MAC_Address0_Low Register........................................................................................................................ 4767
Figure 43-79. MAC_Address1_High Register....................................................................................................................... 4768
Figure 43-80. MAC_Address1_Low Register........................................................................................................................ 4769
Figure 43-81. MAC_Address2_High Register....................................................................................................................... 4770
Figure 43-82. MAC_Address2_Low Register........................................................................................................................ 4771
Figure 43-83. MAC_Address3_High Register....................................................................................................................... 4772
Figure 43-84. MAC_Address3_Low Register........................................................................................................................ 4773
Figure 43-85. MAC_Address4_High Register....................................................................................................................... 4774
Figure 43-86. MAC_Address4_Low Register........................................................................................................................ 4775
Figure 43-87. MAC_Address5_High Register....................................................................................................................... 4776
Figure 43-88. MAC_Address5_Low Register........................................................................................................................ 4777
Figure 43-89. MAC_Address6_High Register....................................................................................................................... 4778
Figure 43-90. MAC_Address6_Low Register........................................................................................................................ 4779
Figure 43-91. MAC_Address7_High Register....................................................................................................................... 4780
Figure 43-92. MAC_Address7_Low Register........................................................................................................................ 4781
Figure 43-93. MMC_Control Register....................................................................................................................................4782
Figure 43-94. MMC_Rx_Interrupt Register............................................................................................................................4784
Figure 43-95. MMC_Tx_Interrupt Register............................................................................................................................ 4790
Figure 43-96. MMC_Rx_Interrupt_Mask Register................................................................................................................. 4796
Figure 43-97. MMC_Tx_Interrupt_Mask Register................................................................................................................. 4801
Figure 43-98. Tx_Octet_Count_Good_Bad Register.............................................................................................................4805
Figure 43-99. Tx_Packet_Count_Good_Bad Register.......................................................................................................... 4806
Figure 43-100. Tx_Broadcast_Packets_Good Register........................................................................................................ 4807
Figure 43-101. Tx_Multicast_Packets_Good Register.......................................................................................................... 4808
Figure 43-102. Tx_64Octets_Packets_Good_Bad Register..................................................................................................4809
Figure 43-103. Tx_65To127Octets_Packets_Good_Bad Register........................................................................................4810
Figure 43-104. Tx_128To255Octets_Packets_Good_Bad Register...................................................................................... 4811
Figure 43-105. Tx_256To511Octets_Packets_Good_Bad Register...................................................................................... 4812
Figure 43-106. Tx_512To1023Octets_Packets_Good_Bad Register....................................................................................4813
Figure 43-107. Tx_1024ToMaxOctets_Packets_Good_Bad Register................................................................................... 4814
Figure 43-108. Tx_Unicast_Packets_Good_Bad Register.................................................................................................... 4815
Figure 43-109. Tx_Multicast_Packets_Good_Bad Register..................................................................................................4816
Figure 43-110. Tx_Broadcast_Packets_Good_Bad Register................................................................................................ 4817
Figure 43-111. Tx_Underflow_Error_Packets Register..........................................................................................................4818
Figure 43-112. Tx_Single_Collision_Good_Packets Register............................................................................................... 4819
Figure 43-113. Tx_Multiple_Collision_Good_Packets Register.............................................................................................4820
Figure 43-114. Tx_Deferred_Packets Register......................................................................................................................4821
Figure 43-115. Tx_Late_Collision_Packets Register............................................................................................................. 4822
Figure 43-116. Tx_Excessive_Collision_Packets Register....................................................................................................4823
Figure 43-117. Tx_Carrier_Error_Packets Register...............................................................................................................4824
Figure 43-118. Tx_Octet_Count_Good Register................................................................................................................... 4825
Figure 43-119. Tx_Packet_Count_Good Register................................................................................................................. 4826

68 TMS320F2838x Real-Time Microcontrollers With Connectivity Manager SPRUII0E – MAY 2019 – REVISED SEPTEMBER 2023
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Figure 43-120. Tx_Excessive_Deferral_Error Register......................................................................................................... 4827

Figure 43-121. Tx_Pause_Packets Register......................................................................................................................... 4828
Figure 43-122. Tx_VLAN_Packets_Good Register............................................................................................................... 4829
Figure 43-123. Tx_OSize_Packets_Good Register...............................................................................................................4830
Figure 43-124. Rx_Packets_Count_Good_Bad Register...................................................................................................... 4831
Figure 43-125. Rx_Octet_Count_Good_Bad Register.......................................................................................................... 4832
Figure 43-126. Rx_Octet_Count_Good Register...................................................................................................................4833
Figure 43-127. Rx_Broadcast_Packets_Good Register........................................................................................................4834
Figure 43-128. Rx_Multicast_Packets_Good Register..........................................................................................................4835
Figure 43-129. Rx_CRC_Error_Packets Register................................................................................................................. 4836
Figure 43-130. Rx_Alignment_Error_Packets Register.........................................................................................................4837
Figure 43-131. Rx_Runt_Error_Packets Register................................................................................................................. 4838
Figure 43-132. Rx_Jabber_Error_Packets Register..............................................................................................................4839
Figure 43-133. Rx_Undersize_Packets_Good Register........................................................................................................4840
Figure 43-134. Rx_Oversize_Packets_Good Register..........................................................................................................4841
Figure 43-135. Rx_64Octets_Packets_Good_Bad Register................................................................................................. 4842
Figure 43-136. Rx_65To127Octets_Packets_Good_Bad Register....................................................................................... 4843
Figure 43-137. Rx_128To255Octets_Packets_Good_Bad Register..................................................................................... 4844
Figure 43-138. Rx_256To511Octets_Packets_Good_Bad Register......................................................................................4845
Figure 43-139. Rx_512To1023Octets_Packets_Good_Bad Register................................................................................... 4846
Figure 43-140. Rx_1024ToMaxOctets_Packets_Good_Bad Register...................................................................................4847
Figure 43-141. Rx_Unicast_Packets_Good Register............................................................................................................ 4848
Figure 43-142. Rx_Length_Error_Packets Register..............................................................................................................4849
Figure 43-143. Rx_Out_Of_Range_Type_Packets Register.................................................................................................4850
Figure 43-144. Rx_Pause_Packets Register.........................................................................................................................4851
Figure 43-145. Rx_FIFO_Overflow_Packets Register.......................................................................................................... 4852
Figure 43-146. Rx_VLAN_Packets_Good_Bad Register...................................................................................................... 4853
Figure 43-147. Rx_Watchdog_Error_Packets Register.........................................................................................................4854
Figure 43-148. Rx_Receive_Error_Packets Register............................................................................................................4855
Figure 43-149. Rx_Control_Packets_Good Register............................................................................................................ 4856
Figure 43-150. Tx_LPI_USEC_Cntr Register........................................................................................................................4857
Figure 43-151. Tx_LPI_Tran_Cntr Register...........................................................................................................................4858
Figure 43-152. Rx_LPI_USEC_Cntr Register....................................................................................................................... 4859
Figure 43-153. Rx_LPI_Tran_Cntr Register.......................................................................................................................... 4860
Figure 43-154. MMC_IPC_Rx_Interrupt_Mask Register....................................................................................................... 4861
Figure 43-155. MMC_IPC_Rx_Interrupt Register..................................................................................................................4865
Figure 43-156. RxIPv4_Good_Packets Register...................................................................................................................4870
Figure 43-157. RxIPv4_Header_Error_Packets Register......................................................................................................4871
Figure 43-158. RxIPv4_No_Payload_Packets Register........................................................................................................ 4872
Figure 43-159. RxIPv4_Fragmented_Packets Register........................................................................................................ 4873
Figure 43-160. RxIPv4_UDP_Checksum_Disabled_Packets Register................................................................................. 4874
Figure 43-161. RxIPv6_Good_Packets Register...................................................................................................................4875
Figure 43-162. RxIPv6_Header_Error_Packets Register......................................................................................................4876
Figure 43-163. RxIPv6_No_Payload_Packets Register........................................................................................................ 4877
Figure 43-164. RxUDP_Good_Packets Register.................................................................................................................. 4878
Figure 43-165. RxUDP_Error_Packets Register................................................................................................................... 4879
Figure 43-166. RxTCP_Good_Packets Register...................................................................................................................4880
Figure 43-167. RxTCP_Error_Packets Register....................................................................................................................4881
Figure 43-168. RxICMP_Good_Packets Register................................................................................................................. 4882
Figure 43-169. RxICMP_Error_Packets Register..................................................................................................................4883
Figure 43-170. RxIPv4_Good_Octets Register..................................................................................................................... 4884
Figure 43-171. RxIPv4_Header_Error_Octets Register........................................................................................................ 4885
Figure 43-172. RxIPv4_No_Payload_Octets Register.......................................................................................................... 4886
Figure 43-173. RxIPv4_Fragmented_Octets Register...........................................................................................................4887
Figure 43-174. RxIPv4_UDP_Checksum_Disable_Octets Register..................................................................................... 4888
Figure 43-175. RxIPv6_Good_Octets Register..................................................................................................................... 4889
Figure 43-176. RxIPv6_Header_Error_Octets Register........................................................................................................ 4890
Figure 43-177. RxIPv6_No_Payload_Octets Register.......................................................................................................... 4891
Figure 43-178. RxUDP_Good_Octets Register.....................................................................................................................4892
Figure 43-179. RxUDP_Error_Octets Register......................................................................................................................4893
Figure 43-180. RxTCP_Good_Octets Register..................................................................................................................... 4894

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Figure 43-181. RxTCP_Error_Octets Register...................................................................................................................... 4895

Figure 43-182. RxICMP_Good_Octets Register................................................................................................................... 4896
Figure 43-183. RxICMP_Error_Octets Register.................................................................................................................... 4897
Figure 43-184. MAC_L3_L4_Control0 Register.................................................................................................................... 4898
Figure 43-185. MAC_Layer4_Address0 Register..................................................................................................................4901
Figure 43-186. MAC_Layer3_Addr0_Reg0 Register.............................................................................................................4902
Figure 43-187. MAC_Layer3_Addr1_Reg0 Register.............................................................................................................4903
Figure 43-188. MAC_Layer3_Addr2_Reg0 Register.............................................................................................................4904
Figure 43-189. MAC_Layer3_Addr3_Reg0 Register.............................................................................................................4905
Figure 43-190. MAC_L3_L4_Control1 Register.................................................................................................................... 4906
Figure 43-191. MAC_Layer4_Address1 Register..................................................................................................................4909
Figure 43-192. MAC_Layer3_Addr0_Reg1 Register.............................................................................................................4910
Figure 43-193. MAC_Layer3_Addr1_Reg1 Register............................................................................................................. 4911
Figure 43-194. MAC_Layer3_Addr2_Reg1 Register.............................................................................................................4912
Figure 43-195. MAC_Layer3_Addr3_Reg1 Register.............................................................................................................4913
Figure 43-196. MAC_L3_L4_Control2 Register.................................................................................................................... 4914
Figure 43-197. MAC_Layer4_Address2 Register..................................................................................................................4917
Figure 43-198. MAC_Layer3_Addr0_Reg2 Register.............................................................................................................4918
Figure 43-199. MAC_Layer3_Addr1_Reg2 Register.............................................................................................................4919
Figure 43-200. MAC_Layer3_Addr2_Reg2 Register.............................................................................................................4920
Figure 43-201. MAC_Layer3_Addr3_Reg2 Register.............................................................................................................4921
Figure 43-202. MAC_L3_L4_Control3 Register.................................................................................................................... 4922
Figure 43-203. MAC_Layer4_Address3 Register..................................................................................................................4925
Figure 43-204. MAC_Layer3_Addr0_Reg3 Register.............................................................................................................4926
Figure 43-205. MAC_Layer3_Addr1_Reg3 Register.............................................................................................................4927
Figure 43-206. MAC_Layer3_Addr2_Reg3 Register.............................................................................................................4928
Figure 43-207. MAC_Layer3_Addr3_Reg3 Register.............................................................................................................4929
Figure 43-208. MAC_Timestamp_Control Register...............................................................................................................4930
Figure 43-209. MAC_Sub_Second_Increment Register....................................................................................................... 4934
Figure 43-210. MAC_System_Time_Seconds Register........................................................................................................ 4935
Figure 43-211. MAC_System_Time_Nanoseconds Register................................................................................................ 4936
Figure 43-212. MAC_System_Time_Seconds_Update Register...........................................................................................4937
Figure 43-213. MAC_System_Time_Nanoseconds_Update Register...................................................................................4938
Figure 43-214. MAC_Timestamp_Addend Register.............................................................................................................. 4939
Figure 43-215. MAC_System_Time_Higher_Word_Seconds Register................................................................................. 4940
Figure 43-216. MAC_Timestamp_Status Register................................................................................................................ 4941
Figure 43-217. MAC_Tx_Timestamp_Status_Nanoseconds Register.................................................................................. 4944
Figure 43-218. MAC_Tx_Timestamp_Status_Seconds Register.......................................................................................... 4945
Figure 43-219. MAC_Auxiliary_Control Register...................................................................................................................4946
Figure 43-220. MAC_Auxiliary_Timestamp_Nanoseconds Register.....................................................................................4947
Figure 43-221. MAC_Auxiliary_Timestamp_Seconds Register.............................................................................................4948
Figure 43-222. MAC_Timestamp_Ingress_Asym_Corr Register...........................................................................................4949
Figure 43-223. MAC_Timestamp_Egress_Asym_Corr Register........................................................................................... 4950
Figure 43-224. MAC_Timestamp_Ingress_Corr_Nanosecond Register............................................................................... 4951
Figure 43-225. MAC_Timestamp_Egress_Corr_Nanosecond Register................................................................................ 4952
Figure 43-226. MAC_Timestamp_Ingress_Corr_Subnanosec Register................................................................................4953
Figure 43-227. MAC_Timestamp_Egress_Corr_Subnanosec Register................................................................................ 4954
Figure 43-228. MAC_PPS_Control Register......................................................................................................................... 4955
Figure 43-229. MAC_PPS0_Target_Time_Seconds Register............................................................................................... 4959
Figure 43-230. MAC_PPS0_Target_Time_Nanoseconds Register....................................................................................... 4960
Figure 43-231. MAC_PPS0_Interval Register....................................................................................................................... 4961
Figure 43-232. MAC_PPS0_Width Register..........................................................................................................................4962
Figure 43-233. MAC_PPS1_Target_Time_Seconds Register............................................................................................... 4963
Figure 43-234. MAC_PPS1_Target_Time_Nanoseconds Register....................................................................................... 4964
Figure 43-235. MAC_PPS1_Interval Register....................................................................................................................... 4965
Figure 43-236. MAC_PPS1_Width Register..........................................................................................................................4966
Figure 43-237. MAC_PTO_Control Register......................................................................................................................... 4967
Figure 43-238. MAC_Source_Port_Identity0 Register.......................................................................................................... 4969
Figure 43-239. MAC_Source_Port_Identity1 Register.......................................................................................................... 4970
Figure 43-240. MAC_Source_Port_Identity2 Register.......................................................................................................... 4971
Figure 43-241. MAC_Log_Message_Interval Register..........................................................................................................4972

70 TMS320F2838x Real-Time Microcontrollers With Connectivity Manager SPRUII0E – MAY 2019 – REVISED SEPTEMBER 2023
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Figure 43-242. MTL_Operation_Mode Register.................................................................................................................... 4973

Figure 43-243. MTL_DBG_CTL Register.............................................................................................................................. 4975
Figure 43-244. MTL_DBG_STS Register.............................................................................................................................. 4978
Figure 43-245. MTL_FIFO_Debug_Data Register................................................................................................................ 4980
Figure 43-246. MTL_Interrupt_Status Register..................................................................................................................... 4981
Figure 43-247. MTL_RxQ_DMA_Map0 Register...................................................................................................................4983
Figure 43-248. MTL_TxQ0_Operation_Mode Register......................................................................................................... 4985
Figure 43-249. MTL_TxQ0_Underflow Register....................................................................................................................4987
Figure 43-250. MTL_TxQ0_Debug Register......................................................................................................................... 4988
Figure 43-251. MTL_TxQ0_ETS_Status Register.................................................................................................................4990
Figure 43-252. MTL_TxQ0_Quantum_Weight Register........................................................................................................ 4991
Figure 43-253. MTL_Q0_Interrupt_Control_Status Register.................................................................................................4992
Figure 43-254. MTL_RxQ0_Operation_Mode Register.........................................................................................................4994
Figure 43-255. MTL_RxQ0_Missed_Packet_Overflow_Cnt Register................................................................................... 4997
Figure 43-256. MTL_RxQ0_Debug Register......................................................................................................................... 4999
Figure 43-257. MTL_RxQ0_Control Register........................................................................................................................ 5000
Figure 43-258. MTL_TxQ1_Operation_Mode Register......................................................................................................... 5001
Figure 43-259. MTL_TxQ1_Underflow Register....................................................................................................................5003
Figure 43-260. MTL_TxQ1_Debug Register......................................................................................................................... 5004
Figure 43-261. MTL_TxQ1_ETS_Status Register.................................................................................................................5006
Figure 43-262. MTL_TxQ1_Quantum_Weight Register........................................................................................................ 5007
Figure 43-263. MTL_Q1_Interrupt_Control_Status Register.................................................................................................5008
Figure 43-264. MTL_RxQ1_Operation_Mode Register.........................................................................................................5010
Figure 43-265. MTL_RxQ1_Missed_Packet_Overflow_Cnt Register................................................................................... 5013
Figure 43-266. MTL_RxQ1_Debug Register......................................................................................................................... 5015
Figure 43-267. MTL_RxQ1_Control Register........................................................................................................................ 5016
Figure 43-268. DMA_Mode Register..................................................................................................................................... 5017
Figure 43-269. DMA_SysBus_Mode Register.......................................................................................................................5019
Figure 43-270. DMA_Interrupt_Status Register.................................................................................................................... 5021
Figure 43-271. DMA_Debug_Status0 Register..................................................................................................................... 5023
Figure 43-272. DMA_CH0_Control Register......................................................................................................................... 5025
Figure 43-273. DMA_CH0_Tx_Control Register................................................................................................................... 5027
Figure 43-274. DMA_CH0_Rx_Control Register...................................................................................................................5029
Figure 43-275. DMA_CH0_TxDesc_List_Address Register..................................................................................................5031
Figure 43-276. DMA_CH0_RxDesc_List_Address Register................................................................................................. 5032
Figure 43-277. DMA_CH0_TxDesc_Tail_Pointer Register....................................................................................................5033
Figure 43-278. DMA_CH0_RxDesc_Tail_Pointer Register................................................................................................... 5034
Figure 43-279. DMA_CH0_TxDesc_Ring_Length Register.................................................................................................. 5035
Figure 43-280. DMA_CH0_RxDesc_Ring_Length Register..................................................................................................5036
Figure 43-281. DMA_CH0_Interrupt_Enable Register.......................................................................................................... 5037
Figure 43-282. DMA_CH0_Rx_Interrupt_Watchdog_Timer Register.................................................................................... 5039
Figure 43-283. DMA_CH0_Current_App_TxDesc Register.................................................................................................. 5040
Figure 43-284. DMA_CH0_Current_App_RxDesc Register..................................................................................................5041
Figure 43-285. DMA_CH0_Current_App_TxBuffer Register................................................................................................. 5042
Figure 43-286. DMA_CH0_Current_App_RxBuffer Register.................................................................................................5043
Figure 43-287. DMA_CH0_Status Register...........................................................................................................................5044
Figure 43-288. DMA_CH0_Miss_Frame_Cnt Register......................................................................................................... 5048
Figure 43-289. DMA_CH0_RX_ERI_Cnt Register................................................................................................................ 5049
Figure 43-290. DMA_CH1_Control Register......................................................................................................................... 5050
Figure 43-291. DMA_CH1_Tx_Control Register................................................................................................................... 5052
Figure 43-292. DMA_CH1_Rx_Control Register...................................................................................................................5054
Figure 43-293. DMA_CH1_TxDesc_List_Address Register..................................................................................................5056
Figure 43-294. DMA_CH1_RxDesc_List_Address Register................................................................................................. 5057
Figure 43-295. DMA_CH1_TxDesc_Tail_Pointer Register....................................................................................................5058
Figure 43-296. DMA_CH1_RxDesc_Tail_Pointer Register................................................................................................... 5059
Figure 43-297. DMA_CH1_TxDesc_Ring_Length Register.................................................................................................. 5060
Figure 43-298. DMA_CH1_RxDesc_Ring_Length Register..................................................................................................5061
Figure 43-299. DMA_CH1_Interrupt_Enable Register.......................................................................................................... 5062
Figure 43-300. DMA_CH1_Rx_Interrupt_Watchdog_Timer Register.................................................................................... 5064
Figure 43-301. DMA_CH1_Current_App_TxDesc Register.................................................................................................. 5065
Figure 43-302. DMA_CH1_Current_App_RxDesc Register..................................................................................................5066

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Figure 43-303. DMA_CH1_Current_App_TxBuffer Register................................................................................................. 5067

Figure 43-304. DMA_CH1_Current_App_RxBuffer Register.................................................................................................5068
Figure 43-305. DMA_CH1_Status Register...........................................................................................................................5069
Figure 43-306. DMA_CH1_Miss_Frame_Cnt Register......................................................................................................... 5073
Figure 43-307. DMA_CH1_RX_ERI_Cnt Register................................................................................................................ 5074
Figure 44-1. GCRC Block Diagram....................................................................................................................................... 5076
Figure 44-2. CRC Sequence Flow.........................................................................................................................................5078
Figure 44-3. CRCCTRL Register...........................................................................................................................................5083
Figure 44-4. CRCPOLY Register........................................................................................................................................... 5084
Figure 44-5. CRCDATAMASK Register................................................................................................................................. 5085
Figure 44-6. CRCDATAIN Register........................................................................................................................................5086
Figure 44-7. CRCDATAOUT Register....................................................................................................................................5087
Figure 44-8. CRCDATATRANS Register............................................................................................................................... 5088
Figure 45-1. MCAN Module Overview................................................................................................................................... 5090
Figure 45-2. MCAN Typical Bus Wiring................................................................................................................................. 5091
Figure 45-3. MCAN Integration..............................................................................................................................................5093
Figure 45-4. MCAN Block Diagram....................................................................................................................................... 5095
Figure 45-5. CAN FD Frame..................................................................................................................................................5098
Figure 45-6. CAN Bit Timing.................................................................................................................................................. 5100
Figure 45-7. Transmitter Delay Measurement....................................................................................................................... 5101
Figure 45-8. Connection of Signals in Bus Monitoring Mode.................................................................................................5102
Figure 45-9. Auto Wakeup Enabled Exit from Power Down.................................................................................................. 5105
Figure 45-10. External Loop Back Mode............................................................................................................................... 5106
Figure 45-11. Internal Loop Back Mode.................................................................................................................................5107
Figure 45-12. External Timestamp Counter Interrupt............................................................................................................ 5108
Figure 45-13. Standard Message ID Filter Path.....................................................................................................................5113
Figure 45-14. Extended Message ID Filter Path.................................................................................................................... 5114
Figure 45-15. Rx FIFO Status................................................................................................................................................ 5115
Figure 45-16. Rx FIFO Overflow Handling.............................................................................................................................5116
Figure 45-17. Mixed Dedicated Tx Buffers /Tx FIFO (example)............................................................................................ 5120
Figure 45-18. Mixed Dedicated Tx Buffers /Tx Queue (example)..........................................................................................5120
Figure 45-19. Message RAM Configuration.......................................................................................................................... 5122
Figure 45-20. Rx Buffer/Rx FIFO Element Structure............................................................................................................. 5123
Figure 45-21. Tx Buffer Element Structure............................................................................................................................ 5125
Figure 45-22. Tx Event FIFO Element Structure................................................................................................................... 5127
Figure 45-23. Standard Message ID Filter Element Structure...............................................................................................5128
Figure 45-24. Extended Message ID Filter Element Structure.............................................................................................. 5130
Figure 45-25. MCANSS_PID Register...................................................................................................................................5138
Figure 45-26. MCANSS_CTRL Register............................................................................................................................... 5139
Figure 45-27. MCANSS_STAT Register................................................................................................................................ 5140
Figure 45-28. MCANSS_ICS Register...................................................................................................................................5141
Figure 45-29. MCANSS_IRS Register...................................................................................................................................5142
Figure 45-30. MCANSS_IECS Register................................................................................................................................ 5143
Figure 45-31. MCANSS_IE Register..................................................................................................................................... 5144
Figure 45-32. MCANSS_IES Register...................................................................................................................................5145
Figure 45-33. MCANSS_EOI Register.................................................................................................................................. 5146
Figure 45-34. MCANSS_EXT_TS_PRESCALER Register................................................................................................... 5147
Figure 45-35. MCANSS_EXT_TS_UNSERVICED_INTR_CNTR Register........................................................................... 5148
Figure 45-36. MCAN_CREL Register....................................................................................................................................5151
Figure 45-37. MCAN_ENDN Register................................................................................................................................... 5152
Figure 45-38. MCAN_DBTP Register....................................................................................................................................5153
Figure 45-39. MCAN_TEST Register.................................................................................................................................... 5155
Figure 45-40. MCAN_RWD Register..................................................................................................................................... 5156
Figure 45-41. MCAN_CCCR Register................................................................................................................................... 5157
Figure 45-42. MCAN_NBTP Register....................................................................................................................................5160
Figure 45-43. MCAN_TSCC Register....................................................................................................................................5162
Figure 45-44. MCAN_TSCV Register....................................................................................................................................5163
Figure 45-45. MCAN_TOCC Register................................................................................................................................... 5164
Figure 45-46. MCAN_TOCV Register....................................................................................................................................5165
Figure 45-47. MCAN_ECR Register......................................................................................................................................5166
Figure 45-48. MCAN_PSR Register...................................................................................................................................... 5167

72 TMS320F2838x Real-Time Microcontrollers With Connectivity Manager SPRUII0E – MAY 2019 – REVISED SEPTEMBER 2023
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Figure 45-49. MCAN_TDCR Register................................................................................................................................... 5170

Figure 45-50. MCAN_IR Register..........................................................................................................................................5171
Figure 45-51. MCAN_IE Register.......................................................................................................................................... 5174
Figure 45-52. MCAN_ILS Register........................................................................................................................................ 5176
Figure 45-53. MCAN_ILE Register........................................................................................................................................ 5179
Figure 45-54. MCAN_GFC Register......................................................................................................................................5180
Figure 45-55. MCAN_SIDFC Register...................................................................................................................................5181
Figure 45-56. MCAN_XIDFC Register...................................................................................................................................5182
Figure 45-57. MCAN_XIDAM Register.................................................................................................................................. 5183
Figure 45-58. MCAN_HPMS Register................................................................................................................................... 5184
Figure 45-59. MCAN_NDAT1 Register.................................................................................................................................. 5185
Figure 45-60. MCAN_NDAT2 Register.................................................................................................................................. 5188
Figure 45-61. MCAN_RXF0C Register..................................................................................................................................5191
Figure 45-62. MCAN_RXF0S Register..................................................................................................................................5192
Figure 45-63. MCAN_RXF0A Register..................................................................................................................................5193
Figure 45-64. MCAN_RXBC Register................................................................................................................................... 5194
Figure 45-65. MCAN_RXF1C Register..................................................................................................................................5195
Figure 45-66. MCAN_RXF1S Register..................................................................................................................................5196
Figure 45-67. MCAN_RXF1A Register..................................................................................................................................5197
Figure 45-68. MCAN_RXESC Register................................................................................................................................. 5198
Figure 45-69. MCAN_TXBC Register....................................................................................................................................5200
Figure 45-70. MCAN_TXFQS Register................................................................................................................................. 5202
Figure 45-71. MCAN_TXESC Register................................................................................................................................. 5203
Figure 45-72. MCAN_TXBRP Register................................................................................................................................. 5204
Figure 45-73. MCAN_TXBAR Register................................................................................................................................. 5207
Figure 45-74. MCAN_TXBCR Register................................................................................................................................. 5209
Figure 45-75. MCAN_TXBTO Register..................................................................................................................................5211
Figure 45-76. MCAN_TXBCF Register..................................................................................................................................5213
Figure 45-77. MCAN_TXBTIE Register.................................................................................................................................5215
Figure 45-78. MCAN_TXBCIE Register................................................................................................................................ 5219
Figure 45-79. MCAN_TXEFC Register..................................................................................................................................5223
Figure 45-80. MCAN_TXEFS Register..................................................................................................................................5224
Figure 45-81. MCAN_TXEFA Register.................................................................................................................................. 5225
Figure 45-82. MCANERR_REV Register.............................................................................................................................. 5228
Figure 45-83. MCANERR_VECTOR Register....................................................................................................................... 5229
Figure 45-84. MCANERR_STAT Register............................................................................................................................. 5230
Figure 45-85. MCANERR_WRAP_REV Register..................................................................................................................5231
Figure 45-86. MCANERR_CTRL Register............................................................................................................................ 5232
Figure 45-87. MCANERR_ERR_CTRL1 Register.................................................................................................................5234
Figure 45-88. MCANERR_ERR_CTRL2 Register.................................................................................................................5235
Figure 45-89. MCANERR_ERR_STAT1 Register..................................................................................................................5236
Figure 45-90. MCANERR_ERR_STAT2 Register..................................................................................................................5238
Figure 45-91. MCANERR_ERR_STAT3 Register..................................................................................................................5239
Figure 45-92. MCANERR_SEC_EOI Register...................................................................................................................... 5240
Figure 45-93. MCANERR_SEC_STATUS Register...............................................................................................................5241
Figure 45-94. MCANERR_SEC_ENABLE_SET Register..................................................................................................... 5242
Figure 45-95. MCANERR_SEC_ENABLE_CLR Register..................................................................................................... 5243
Figure 45-96. MCANERR_DED_EOI Register...................................................................................................................... 5244
Figure 45-97. MCANERR_DED_STATUS Register...............................................................................................................5245
Figure 45-98. MCANERR_DED_ENABLE_SET Register..................................................................................................... 5246
Figure 45-99. MCANERR_DED_ENABLE_CLR Register.....................................................................................................5247
Figure 45-100. MCANERR_AGGR_ENABLE_SET Register................................................................................................ 5248
Figure 45-101. MCANERR_AGGR_ENABLE_CLR Register................................................................................................5249
Figure 45-102. MCANERR_AGGR_STATUS_SET Register.................................................................................................5250
Figure 45-103. MCANERR_AGGR_STATUS_CLR Register................................................................................................ 5251
Figure 46-1. I2C Block Diagram............................................................................................................................................ 5255
Figure 46-2. I2C Bus Configuration....................................................................................................................................... 5256
Figure 46-3. START and STOP Conditions........................................................................................................................... 5256
Figure 46-4. Complete Data Transfer With a 7-Bit Address.................................................................................................. 5257
Figure 46-5. R/S Bit in First Byte........................................................................................................................................... 5257
Figure 46-6. Data Validity During Bit Transfer on the I2C Bus...............................................................................................5257

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Figure 46-7. High-Speed Data Format.................................................................................................................................. 5262

Figure 46-8. Master Single Transmit......................................................................................................................................5266
Figure 46-9. Master Single Receive...................................................................................................................................... 5267
Figure 46-10. Master Transmit of Multiple Data Bytes...........................................................................................................5268
Figure 46-11. Master Receive of Multiple Data Bytes............................................................................................................5269
Figure 46-12. Master Receive With Repeated START After Master Transmit.......................................................................5270
Figure 46-13. Master Transmit With Repeated START After Master Receive.......................................................................5270
Figure 46-14. Standard High-Speed Mode Master Transmit................................................................................................. 5271
Figure 46-15. Slave Command Sequence.............................................................................................................................5272
Figure 46-16. I2CMSA Register.............................................................................................................................................5277
Figure 46-17. I2CMCS Register............................................................................................................................................ 5278
Figure 46-18. I2CMDR Register............................................................................................................................................ 5280
Figure 46-19. I2CMTPR Register.......................................................................................................................................... 5281
Figure 46-20. I2CMIMR Register...........................................................................................................................................5282
Figure 46-21. I2CMRIS Register........................................................................................................................................... 5284
Figure 46-22. I2CMMIS Register........................................................................................................................................... 5287
Figure 46-23. I2CMICR Register........................................................................................................................................... 5289
Figure 46-24. I2CMCR Register............................................................................................................................................ 5291
Figure 46-25. I2CMCLKOCNT Register................................................................................................................................ 5292
Figure 46-26. I2CMBMON Register.......................................................................................................................................5293
Figure 46-27. I2CMBLEN Register........................................................................................................................................ 5294
Figure 46-28. I2CMBCNT Register........................................................................................................................................5295
Figure 46-29. I2CSOAR Register.......................................................................................................................................... 5296
Figure 46-30. I2CSCSR Register.......................................................................................................................................... 5297
Figure 46-31. I2CSDR Register.............................................................................................................................................5299
Figure 46-32. I2CSIMR Register........................................................................................................................................... 5300
Figure 46-33. I2CSRIS Register............................................................................................................................................ 5302
Figure 46-34. I2CSMIS Register............................................................................................................................................5304
Figure 46-35. I2CSICR Register............................................................................................................................................5306
Figure 46-36. I2CSOAR2 Register........................................................................................................................................ 5308
Figure 46-37. I2CSACKCTL Register....................................................................................................................................5309
Figure 46-38. I2CFIFODATARX Register.............................................................................................................................. 5310
Figure 46-39. I2CFIFOCTL Register......................................................................................................................................5311
Figure 46-40. I2CFIFOSTATUS Register...............................................................................................................................5313
Figure 46-41. I2CPP Register................................................................................................................................................5315
Figure 46-42. I2CPC Register............................................................................................................................................... 5316
Figure 46-43. I2CMCS_WRITE Register...............................................................................................................................5318
Figure 46-44. I2CSCSR_WRITE Register.............................................................................................................................5320
Figure 46-45. I2CFIFODATATX Register...............................................................................................................................5321
Figure 47-1. SSI Block Diagram............................................................................................................................................ 5325
Figure 47-2. TI Synchronous Serial Frame Format (Single Transfer)....................................................................................5328
Figure 47-3. TI Synchronous Serial Frame Format (Continuous Transfer)........................................................................... 5328
Figure 47-4. Freescale SPI Format (Single Transfer) with SPO=0 and SPH=0................................................................... 5330
Figure 47-5. Freescale SPI Format (Continuous Transfer) with SPO=0 and SPH=0............................................................ 5330
Figure 47-6. Freescale SPI Frame Format with SPO =0 and SPH=1................................................................................... 5331
Figure 47-7. Freescale SPI Frame Format (Single Transfer) with SPO=1 and SPH=0.........................................................5332
Figure 47-8. Freescale SPI Frame Format (Continuous Transfer) with SPO=1 and SPH=0.................................................5332
Figure 47-9. Freescale SPI Frame Format with SPO =1 and SPH =1.................................................................................. 5333
Figure 47-10. SSICR0 Register............................................................................................................................................. 5338
Figure 47-11. SSICR1 Register............................................................................................................................................. 5340
Figure 47-12. SSIDR Register............................................................................................................................................... 5342
Figure 47-13. SSISR Register............................................................................................................................................... 5343
Figure 47-14. SSICPSR Register.......................................................................................................................................... 5344
Figure 47-15. SSIIM Register................................................................................................................................................ 5345
Figure 47-16. SSIRIS Register.............................................................................................................................................. 5347
Figure 47-17. SSIMIS Register..............................................................................................................................................5349
Figure 47-18. SSIICR Register.............................................................................................................................................. 5351
Figure 47-19. SSIDMACTL Register..................................................................................................................................... 5352
Figure 47-20. SSIPV Register............................................................................................................................................... 5353
Figure 47-21. SSIPP Register............................................................................................................................................... 5354
Figure 47-22. SSIPC Register............................................................................................................................................... 5355

74 TMS320F2838x Real-Time Microcontrollers With Connectivity Manager SPRUII0E – MAY 2019 – REVISED SEPTEMBER 2023
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Figure 47-23. SSIPeriphID4 Register.................................................................................................................................... 5356

Figure 47-24. SSIPeriphID5 Register.................................................................................................................................... 5357
Figure 47-25. SSIPeriphID6 Register.................................................................................................................................... 5358
Figure 47-26. SSIPeriphID7 Register.................................................................................................................................... 5359
Figure 47-27. SSIPeriphID0 Register.................................................................................................................................... 5360
Figure 47-28. SSIPeriphID1 Register.................................................................................................................................... 5361
Figure 47-29. SSIPeriphID2 Register.................................................................................................................................... 5362
Figure 47-30. SSIPeriphID3 Register.................................................................................................................................... 5363
Figure 47-31. SSIPCellID0 Register...................................................................................................................................... 5364
Figure 47-32. SSIPCellID1 Register...................................................................................................................................... 5365
Figure 47-33. SSIPCellID2 Register...................................................................................................................................... 5366
Figure 47-34. SSIPCellID3 Register...................................................................................................................................... 5367
Figure 48-1. UART Module Block Diagram............................................................................................................................5371
Figure 48-2. UART Character Frame.....................................................................................................................................5371
Figure 48-3. IrDA Data Modulation........................................................................................................................................ 5374
Figure 48-4. UARTDR Register............................................................................................................................................. 5382
Figure 48-5. UARTRSR Register...........................................................................................................................................5384
Figure 48-6. UARTFR Register..............................................................................................................................................5386
Figure 48-7. UARTILPR Register.......................................................................................................................................... 5388
Figure 48-8. UARTIBRD Register..........................................................................................................................................5389
Figure 48-9. UARTFBRD Register.........................................................................................................................................5390
Figure 48-10. UARTLCRH Register.......................................................................................................................................5391
Figure 48-11. UARTCTL Register..........................................................................................................................................5393
Figure 48-12. UARTIFLS Register.........................................................................................................................................5395
Figure 48-13. UARTIM Register............................................................................................................................................ 5396
Figure 48-14. UARTRIS Register.......................................................................................................................................... 5398
Figure 48-15. UARTMIS Register.......................................................................................................................................... 5400
Figure 48-16. UARTICR Register.......................................................................................................................................... 5402
Figure 48-17. UARTDMACTL Register..................................................................................................................................5404
Figure 48-18. UART9BITADDR Register...............................................................................................................................5405
Figure 48-19. UART9BITAMASK Register............................................................................................................................ 5406
Figure 48-20. UARTPP Register............................................................................................................................................5407
Figure 48-21. UARTPeriphID4 Register................................................................................................................................ 5408
Figure 48-22. UARTPeriphID5 Register................................................................................................................................ 5409
Figure 48-23. UARTPeriphID6 Register................................................................................................................................ 5410
Figure 48-24. UARTPeriphID7 Register.................................................................................................................................5411
Figure 48-25. UARTPeriphID0 Register................................................................................................................................ 5412
Figure 48-26. UARTPeriphID1 Register................................................................................................................................ 5413
Figure 48-27. UARTPeriphID2 Register................................................................................................................................ 5414
Figure 48-28. UARTPeriphID3 Register................................................................................................................................ 5415
Figure 48-29. UARTPCellID0 Register.................................................................................................................................. 5416
Figure 48-30. UARTPCellID1 Register.................................................................................................................................. 5417
Figure 48-31. UARTPCellID2 Register.................................................................................................................................. 5418
Figure 48-32. UARTPCellID3 Register.................................................................................................................................. 5419
Figure 48-33. UARTECR Register.........................................................................................................................................5421
Figure 49-1. µDMA Block Diagram........................................................................................................................................ 5425
Figure 49-2. Example of Ping-Pong µDMA Transaction........................................................................................................ 5431
Figure 49-3. Memory Scatter-Gather, Setup and Configuration............................................................................................ 5433
Figure 49-4. Memory Scatter-Gather, µDMA Copy Sequence.............................................................................................. 5434
Figure 49-5. Peripheral Scatter-Gather, Setup and Configuration.........................................................................................5436
Figure 49-6. Peripheral Scatter-Gather, µDMA Copy Sequence........................................................................................... 5437
Figure 49-7. DMASTAT Register........................................................................................................................................... 5449
Figure 49-8. DMACFG Register............................................................................................................................................ 5450
Figure 49-9. DMACTLBASE Register....................................................................................................................................5451
Figure 49-10. DMAALTBASE Register.................................................................................................................................. 5452
Figure 49-11. DMASWREQ Register.....................................................................................................................................5453
Figure 49-12. DMAUSEBURSTSET Register....................................................................................................................... 5454
Figure 49-13. DMAUSEBURSTCLR Register....................................................................................................................... 5455
Figure 49-14. DMAREQMASKSET Register......................................................................................................................... 5456
Figure 49-15. DMAREQMASKCLR Register.........................................................................................................................5457
Figure 49-16. DMAENASET Register....................................................................................................................................5458

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Figure 49-17. DMAENACLR Register................................................................................................................................... 5459

Figure 49-18. DMAALTSET Register.....................................................................................................................................5460
Figure 49-19. DMAALTCLR Register.....................................................................................................................................5461
Figure 49-20. DMAPRIOSET Register.................................................................................................................................. 5462
Figure 49-21. DMAPRIOCLR Register.................................................................................................................................. 5463
Figure 49-22. DMAERRCLR Register................................................................................................................................... 5464
Figure 49-23. DMACHMAP0 Register................................................................................................................................... 5465
Figure 49-24. DMACHMAP1 Register................................................................................................................................... 5466
Figure 49-25. DMACHMAP2 Register................................................................................................................................... 5467
Figure 49-26. DMACHMAP3 Register................................................................................................................................... 5468
Figure 49-27. DMAPeriphID4 Register.................................................................................................................................. 5469
Figure 49-28. DMAPeriphID0 Register.................................................................................................................................. 5470
Figure 49-29. DMAPeriphID1 Register.................................................................................................................................. 5471
Figure 49-30. DMAPeriphID2 Register.................................................................................................................................. 5472
Figure 49-31. DMAPeriphID3 Register.................................................................................................................................. 5473
Figure 49-32. DMAPCellID0 Register....................................................................................................................................5474
Figure 49-33. DMAPCellID1 Register....................................................................................................................................5475
Figure 49-34. DMAPCellID2 Register....................................................................................................................................5476
Figure 49-35. DMAPCellID3 Register....................................................................................................................................5477
Figure 49-36. DMASRCENDP Register................................................................................................................................ 5479
Figure 49-37. DMADSTENDP Register.................................................................................................................................5480
Figure 49-38. DMACHCTL Register...................................................................................................................................... 5481

List of Tables
Table 2-1. C2000Ware Root Directories.................................................................................................................................. 136
Table 3-1. Reset Signals..........................................................................................................................................................142
Table 3-2. PIE Channel Mapping............................................................................................................................................. 150
Table 3-3. CPU Interrupt Vectors............................................................................................................................................. 153
Table 3-4. PIE Interrupt Vectors...............................................................................................................................................154
Table 3-5. Access to EALLOW-Protected Registers................................................................................................................161
Table 3-6. Clock Connections Sorted by Clock Domain.......................................................................................................... 169
Table 3-7. Clock Source (OSCCLK) Failure Detection............................................................................................................ 174
Table 3-8. Example Watchdog Key Sequences.......................................................................................................................179
Table 3-9. Local Shared RAM..................................................................................................................................................183
Table 3-10. Global Shared RAM.............................................................................................................................................. 183
Table 3-11. Error Handling in Different Scenarios....................................................................................................................189
Table 3-12. Mapping of ECC Bits in Read Data from ECC/Parity Address Map..................................................................... 190
Table 3-13. Mapping of Parity Bits in Read Data from ECC/Parity Address Map....................................................................190
Table 3-14. System Control Registers Impacted..................................................................................................................... 193
Table 3-15. SYSCTRL Base Address Table (C28).................................................................................................................. 200
Table 3-16. ACCESS_PROTECTION_REGS Registers......................................................................................................... 201
Table 3-17. ACCESS_PROTECTION_REGS Access Type Codes.........................................................................................201
Table 3-18. NMAVFLG Register Field Descriptions................................................................................................................. 203
Table 3-19. NMAVSET Register Field Descriptions................................................................................................................. 205
Table 3-20. NMAVCLR Register Field Descriptions.................................................................................................................207
Table 3-21. NMAVINTEN Register Field Descriptions............................................................................................................. 209
Table 3-22. NMCPURDAVADDR Register Field Descriptions................................................................................................. 210
Table 3-23. NMCPUWRAVADDR Register Field Descriptions.................................................................................................211
Table 3-24. NMCPUFAVADDR Register Field Descriptions.................................................................................................... 212
Table 3-25. NMDMAWRAVADDR Register Field Descriptions................................................................................................ 213
Table 3-26. NMCLA1RDAVADDR Register Field Descriptions................................................................................................214
Table 3-27. NMCLA1WRAVADDR Register Field Descriptions............................................................................................... 215
Table 3-28. NMCLA1FAVADDR Register Field Descriptions................................................................................................... 216
Table 3-29. NMDMARDAVADDR Register Field Descriptions.................................................................................................217
Table 3-30. MAVFLG Register Field Descriptions....................................................................................................................218
Table 3-31. MAVSET Register Field Descriptions....................................................................................................................219
Table 3-32. MAVCLR Register Field Descriptions................................................................................................................... 220
Table 3-33. MAVINTEN Register Field Descriptions................................................................................................................221
Table 3-34. MCPUFAVADDR Register Field Descriptions....................................................................................................... 222
Table 3-35. MCPUWRAVADDR Register Field Descriptions................................................................................................... 223
Table 3-36. MDMAWRAVADDR Register Field Descriptions...................................................................................................224

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Table 3-37. CLK_CFG_REGS Registers................................................................................................................................. 225

Table 3-38. CLK_CFG_REGS Access Type Codes................................................................................................................ 225
Table 3-39. CLKSEM Register Field Descriptions................................................................................................................... 227
Table 3-40. CLKCFGLOCK1 Register Field Descriptions........................................................................................................228
Table 3-41. CLKSRCCTL1 Register Field Descriptions...........................................................................................................231
Table 3-42. CLKSRCCTL2 Register Field Descriptions...........................................................................................................233
Table 3-43. CLKSRCCTL3 Register Field Descriptions...........................................................................................................235
Table 3-44. SYSPLLCTL1 Register Field Descriptions............................................................................................................236
Table 3-45. SYSPLLMULT Register Field Descriptions........................................................................................................... 237
Table 3-46. SYSPLLSTS Register Field Descriptions............................................................................................................. 239
Table 3-47. AUXPLLCTL1 Register Field Descriptions........................................................................................................... 240
Table 3-48. AUXPLLMULT Register Field Descriptions...........................................................................................................241
Table 3-49. AUXPLLSTS Register Field Descriptions............................................................................................................. 243
Table 3-50. SYSCLKDIVSEL Register Field Descriptions....................................................................................................... 244
Table 3-51. AUXCLKDIVSEL Register Field Descriptions.......................................................................................................245
Table 3-52. PERCLKDIVSEL Register Field Descriptions.......................................................................................................246
Table 3-53. XCLKOUTDIVSEL Register Field Descriptions.................................................................................................... 247
Table 3-54. CLBCLKCTL Register Field Descriptions............................................................................................................. 248
Table 3-55. LOSPCP Register Field Descriptions................................................................................................................... 250
Table 3-56. MCDCR Register Field Descriptions.....................................................................................................................251
Table 3-57. X1CNT Register Field Descriptions...................................................................................................................... 252
Table 3-58. XTALCR Register Field Descriptions.................................................................................................................... 253
Table 3-59. ETHERCATCLKCTL Register Field Descriptions................................................................................................. 254
Table 3-60. CMCLKCTL Register Field Descriptions...............................................................................................................255
Table 3-61. CM_CONF_REGS Registers................................................................................................................................256
Table 3-62. CM_CONF_REGS Access Type Codes............................................................................................................... 256
Table 3-63. CMRESCTL Register Field Descriptions.............................................................................................................. 257
Table 3-64. CMTOCPU1NMICTL Register Field Descriptions.................................................................................................258
Table 3-65. CMTOCPU1INTCTL Register Field Descriptions................................................................................................. 259
Table 3-66. PALLOCATE0 Register Field Descriptions........................................................................................................... 260
Table 3-67. CM_CONF_REGS_LOCK Register Field Descriptions........................................................................................ 262
Table 3-68. CPU_SYS_REGS Registers.................................................................................................................................263
Table 3-69. CPU_SYS_REGS Access Type Codes................................................................................................................ 263
Table 3-70. CPUSYSLOCK1 Register Field Descriptions....................................................................................................... 265
Table 3-71. CPUSYSLOCK2 Register Field Descriptions....................................................................................................... 268
Table 3-72. PIEVERRADDR Register Field Descriptions........................................................................................................ 269
Table 3-73. PCLKCR0 Register Field Descriptions................................................................................................................. 270
Table 3-74. PCLKCR1 Register Field Descriptions................................................................................................................. 272
Table 3-75. PCLKCR2 Register Field Descriptions................................................................................................................. 273
Table 3-76. PCLKCR3 Register Field Descriptions................................................................................................................. 275
Table 3-77. PCLKCR4 Register Field Descriptions................................................................................................................. 277
Table 3-78. PCLKCR6 Register Field Descriptions................................................................................................................. 278
Table 3-79. PCLKCR7 Register Field Descriptions................................................................................................................. 279
Table 3-80. PCLKCR8 Register Field Descriptions................................................................................................................. 280
Table 3-81. PCLKCR9 Register Field Descriptions................................................................................................................. 281
Table 3-82. PCLKCR10 Register Field Descriptions............................................................................................................... 282
Table 3-83. PCLKCR11 Register Field Descriptions................................................................................................................283
Table 3-84. PCLKCR13 Register Field Descriptions............................................................................................................... 284
Table 3-85. PCLKCR14 Register Field Descriptions............................................................................................................... 285
Table 3-86. PCLKCR16 Register Field Descriptions............................................................................................................... 287
Table 3-87. PCLKCR17 Register Field Descriptions............................................................................................................... 288
Table 3-88. PCLKCR18 Register Field Descriptions............................................................................................................... 290
Table 3-89. PCLKCR20 Register Field Descriptions............................................................................................................... 292
Table 3-90. PCLKCR21 Register Field Descriptions............................................................................................................... 293
Table 3-91. PCLKCR22 Register Field Descriptions............................................................................................................... 294
Table 3-92. PCLKCR23 Register Field Descriptions............................................................................................................... 295
Table 3-93. SIMRESET Register Field Descriptions................................................................................................................296
Table 3-94. LPMCR Register Field Descriptions..................................................................................................................... 297
Table 3-95. GPIOLPMSEL0 Register Field Descriptions.........................................................................................................298
Table 3-96. GPIOLPMSEL1 Register Field Descriptions.........................................................................................................301
Table 3-97. TMR2CLKCTL Register Field Descriptions.......................................................................................................... 304

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Table 3-98. RESCCLR Register Field Descriptions.................................................................................................................305

Table 3-99. RESC Register Field Descriptions........................................................................................................................ 307
Table 3-100. MCANWAKESTATUS Register Field Descriptions............................................................................................. 309
Table 3-101. MCANWAKESTATUSCLR Register Field Descriptions...................................................................................... 310
Table 3-102. CPU_ID_REGS Registers...................................................................................................................................311
Table 3-103. CPU_ID_REGS Access Type Codes.................................................................................................................. 311
Table 3-104. CPUID Register Field Descriptions.....................................................................................................................312
Table 3-105. CPU1_PERIPH_AC_REGS Registers................................................................................................................313
Table 3-106. CPU1_PERIPH_AC_REGS Access Type Codes............................................................................................... 314
Table 3-107. ADCA_AC Register Field Descriptions............................................................................................................... 316
Table 3-108. ADCB_AC Register Field Descriptions............................................................................................................... 317
Table 3-109. ADCC_AC Register Field Descriptions...............................................................................................................318
Table 3-110. ADCD_AC Register Field Descriptions............................................................................................................... 319
Table 3-111. CMPSS1_AC Register Field Descriptions...........................................................................................................320
Table 3-112. CMPSS2_AC Register Field Descriptions...........................................................................................................321
Table 3-113. CMPSS3_AC Register Field Descriptions...........................................................................................................322
Table 3-114. CMPSS4_AC Register Field Descriptions...........................................................................................................323
Table 3-115. CMPSS5_AC Register Field Descriptions...........................................................................................................324
Table 3-116. CMPSS6_AC Register Field Descriptions...........................................................................................................325
Table 3-117. CMPSS7_AC Register Field Descriptions...........................................................................................................326
Table 3-118. CMPSS8_AC Register Field Descriptions...........................................................................................................327
Table 3-119. DACA_AC Register Field Descriptions............................................................................................................... 328
Table 3-120. DACB_AC Register Field Descriptions............................................................................................................... 329
Table 3-121. DACC_AC Register Field Descriptions...............................................................................................................330
Table 3-122. EPWM1_AC Register Field Descriptions............................................................................................................331
Table 3-123. EPWM2_AC Register Field Descriptions............................................................................................................332
Table 3-124. EPWM3_AC Register Field Descriptions............................................................................................................333
Table 3-125. EPWM4_AC Register Field Descriptions............................................................................................................334
Table 3-126. EPWM5_AC Register Field Descriptions............................................................................................................335
Table 3-127. EPWM6_AC Register Field Descriptions............................................................................................................336
Table 3-128. EPWM7_AC Register Field Descriptions............................................................................................................337
Table 3-129. EPWM8_AC Register Field Descriptions............................................................................................................338
Table 3-130. EPWM9_AC Register Field Descriptions............................................................................................................339
Table 3-131. EPWM10_AC Register Field Descriptions..........................................................................................................340
Table 3-132. EPWM11_AC Register Field Descriptions.......................................................................................................... 341
Table 3-133. EPWM12_AC Register Field Descriptions..........................................................................................................342
Table 3-134. EPWM13_AC Register Field Descriptions..........................................................................................................343
Table 3-135. EPWM14_AC Register Field Descriptions..........................................................................................................344
Table 3-136. EPWM15_AC Register Field Descriptions..........................................................................................................345
Table 3-137. EPWM16_AC Register Field Descriptions..........................................................................................................346
Table 3-138. EQEP1_AC Register Field Descriptions............................................................................................................. 347
Table 3-139. EQEP2_AC Register Field Descriptions............................................................................................................. 348
Table 3-140. EQEP3_AC Register Field Descriptions............................................................................................................. 349
Table 3-141. ECAP1_AC Register Field Descriptions............................................................................................................. 350
Table 3-142. ECAP2_AC Register Field Descriptions............................................................................................................. 351
Table 3-143. ECAP3_AC Register Field Descriptions............................................................................................................. 352
Table 3-144. ECAP4_AC Register Field Descriptions............................................................................................................. 353
Table 3-145. ECAP5_AC Register Field Descriptions............................................................................................................. 354
Table 3-146. ECAP6_AC Register Field Descriptions............................................................................................................. 355
Table 3-147. ECAP7_AC Register Field Descriptions............................................................................................................. 356
Table 3-148. SDFM1_AC Register Field Descriptions.............................................................................................................357
Table 3-149. SDFM2_AC Register Field Descriptions.............................................................................................................358
Table 3-150. CLB1_AC Register Field Descriptions................................................................................................................ 359
Table 3-151. CLB2_AC Register Field Descriptions................................................................................................................ 360
Table 3-152. CLB3_AC Register Field Descriptions................................................................................................................ 361
Table 3-153. CLB4_AC Register Field Descriptions................................................................................................................ 362
Table 3-154. CLB5_AC Register Field Descriptions................................................................................................................ 363
Table 3-155. CLB6_AC Register Field Descriptions................................................................................................................ 364
Table 3-156. CLB7_AC Register Field Descriptions................................................................................................................ 365
Table 3-157. CLB8_AC Register Field Descriptions................................................................................................................ 366
Table 3-158. SPIA_AC Register Field Descriptions.................................................................................................................367

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Table 3-159. SPIB_AC Register Field Descriptions.................................................................................................................368

Table 3-160. SPIC_AC Register Field Descriptions.................................................................................................................369
Table 3-161. SPID_AC Register Field Descriptions.................................................................................................................370
Table 3-162. PMBUS_A_AC Register Field Descriptions........................................................................................................371
Table 3-163. CAN_A_AC Register Field Descriptions............................................................................................................. 372
Table 3-164. CAN_B_AC Register Field Descriptions............................................................................................................. 373
Table 3-165. MCBSPA_AC Register Field Descriptions.......................................................................................................... 374
Table 3-166. MCBSPB_AC Register Field Descriptions..........................................................................................................375
Table 3-167. USBA_AC Register Field Descriptions............................................................................................................... 376
Table 3-168. HRPWM_AC Register Field Descriptions........................................................................................................... 377
Table 3-169. ETHERCAT_AC Register Field Descriptions...................................................................................................... 379
Table 3-170. FSIATX_AC Register Field Descriptions.............................................................................................................380
Table 3-171. FSIARX_AC Register Field Descriptions............................................................................................................ 381
Table 3-172. FSIBTX_AC Register Field Descriptions............................................................................................................ 382
Table 3-173. FSIBRX_AC Register Field Descriptions............................................................................................................ 383
Table 3-174. FSICRX_AC Register Field Descriptions............................................................................................................384
Table 3-175. FSIDRX_AC Register Field Descriptions............................................................................................................385
Table 3-176. FSIERX_AC Register Field Descriptions............................................................................................................ 386
Table 3-177. FSIFRX_AC Register Field Descriptions............................................................................................................ 387
Table 3-178. FSIGRX_AC Register Field Descriptions............................................................................................................388
Table 3-179. FSIHRX_AC Register Field Descriptions............................................................................................................389
Table 3-180. MCANA_AC Register Field Descriptions............................................................................................................ 390
Table 3-181. PERIPH_AC_LOCK Register Field Descriptions................................................................................................391
Table 3-182. CPUTIMER_REGS Registers.............................................................................................................................392
Table 3-183. CPUTIMER_REGS Access Type Codes............................................................................................................ 392
Table 3-184. TIM Register Field Descriptions..........................................................................................................................393
Table 3-185. PRD Register Field Descriptions........................................................................................................................ 394
Table 3-186. TCR Register Field Descriptions.........................................................................................................................395
Table 3-187. TPR Register Field Descriptions.........................................................................................................................397
Table 3-188. TPRH Register Field Descriptions...................................................................................................................... 398
Table 3-189. DEV_CFG_REGS Registers...............................................................................................................................399
Table 3-190. DEV_CFG_REGS Access Type Codes.............................................................................................................. 400
Table 3-191. DEVCFGLOCK1 Register Field Descriptions..................................................................................................... 401
Table 3-192. DEVCFGLOCK2 Register Field Descriptions..................................................................................................... 403
Table 3-193. PARTIDL Register Field Descriptions................................................................................................................. 404
Table 3-194. PARTIDH Register Field Descriptions.................................................................................................................406
Table 3-195. REVID Register Field Descriptions..................................................................................................................... 407
Table 3-196. PERCNF1 Register Field Descriptions............................................................................................................... 408
Table 3-197. FUSEERR Register Field Descriptions...............................................................................................................409
Table 3-198. SOFTPRES0 Register Field Descriptions...........................................................................................................410
Table 3-199. SOFTPRES1 Register Field Descriptions...........................................................................................................412
Table 3-200. SOFTPRES2 Register Field Descriptions...........................................................................................................413
Table 3-201. SOFTPRES3 Register Field Descriptions...........................................................................................................415
Table 3-202. SOFTPRES4 Register Field Descriptions...........................................................................................................416
Table 3-203. SOFTPRES6 Register Field Descriptions...........................................................................................................417
Table 3-204. SOFTPRES7 Register Field Descriptions...........................................................................................................418
Table 3-205. SOFTPRES8 Register Field Descriptions...........................................................................................................419
Table 3-206. SOFTPRES9 Register Field Descriptions...........................................................................................................420
Table 3-207. SOFTPRES10 Register Field Descriptions.........................................................................................................421
Table 3-208. SOFTPRES11 Register Field Descriptions......................................................................................................... 422
Table 3-209. SOFTPRES13 Register Field Descriptions.........................................................................................................423
Table 3-210. SOFTPRES14 Register Field Descriptions.........................................................................................................424
Table 3-211. SOFTPRES16 Register Field Descriptions......................................................................................................... 425
Table 3-212. SOFTPRES17 Register Field Descriptions.........................................................................................................426
Table 3-213. SOFTPRES18 Register Field Descriptions.........................................................................................................427
Table 3-214. SOFTPRES20 Register Field Descriptions.........................................................................................................429
Table 3-215. SOFTPRES21 Register Field Descriptions.........................................................................................................430
Table 3-216. SOFTPRES23 Register Field Descriptions.........................................................................................................431
Table 3-217. CPUSEL0 Register Field Descriptions................................................................................................................432
Table 3-218. CPUSEL1 Register Field Descriptions................................................................................................................434
Table 3-219. CPUSEL2 Register Field Descriptions................................................................................................................435

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Table 3-220. CPUSEL4 Register Field Descriptions................................................................................................................436

Table 3-221. CPUSEL5 Register Field Descriptions................................................................................................................437
Table 3-222. CPUSEL6 Register Field Descriptions................................................................................................................438
Table 3-223. CPUSEL7 Register Field Descriptions................................................................................................................439
Table 3-224. CPUSEL8 Register Field Descriptions................................................................................................................440
Table 3-225. CPUSEL9 Register Field Descriptions................................................................................................................441
Table 3-226. CPUSEL11 Register Field Descriptions.............................................................................................................. 442
Table 3-227. CPUSEL12 Register Field Descriptions..............................................................................................................443
Table 3-228. CPUSEL14 Register Field Descriptions..............................................................................................................444
Table 3-229. CPUSEL15 Register Field Descriptions..............................................................................................................445
Table 3-230. CPUSEL16 Register Field Descriptions..............................................................................................................446
Table 3-231. CPUSEL18 Register Field Descriptions..............................................................................................................448
Table 3-232. CPUSEL25 Register Field Descriptions..............................................................................................................449
Table 3-233. CPU2RESCTL Register Field Descriptions........................................................................................................ 450
Table 3-234. RSTSTAT Register Field Descriptions................................................................................................................ 451
Table 3-235. LPMSTAT Register Field Descriptions................................................................................................................ 452
Table 3-236. USBTYPE Register Field Descriptions............................................................................................................... 453
Table 3-237. ECAPTYPE Register Field Descriptions.............................................................................................................454
Table 3-238. SDFMTYPE Register Field Descriptions............................................................................................................ 455
Table 3-239. MEMMAPTYPE Register Field Descriptions...................................................................................................... 456
Table 3-240. DMA_CLA_SRC_SEL_REGS Registers............................................................................................................ 457
Table 3-241. DMA_CLA_SRC_SEL_REGS Access Type Codes............................................................................................457
Table 3-242. CLA1TASKSRCSELLOCK Register Field Descriptions......................................................................................458
Table 3-243. DMACHSRCSELLOCK Register Field Descriptions...........................................................................................459
Table 3-244. CLA1TASKSRCSEL1 Register Field Descriptions..............................................................................................460
Table 3-245. CLA1TASKSRCSEL2 Register Field Descriptions..............................................................................................461
Table 3-246. DMACHSRCSEL1 Register Field Descriptions.................................................................................................. 462
Table 3-247. DMACHSRCSEL2 Register Field Descriptions.................................................................................................. 463
Table 3-248. MEM_CFG_REGS Registers..............................................................................................................................464
Table 3-249. MEM_CFG_REGS Access Type Codes............................................................................................................. 465
Table 3-250. DxLOCK Register Field Descriptions..................................................................................................................466
Table 3-251. DxCOMMIT Register Field Descriptions............................................................................................................. 467
Table 3-252. DxACCPROT0 Register Field Descriptions........................................................................................................ 468
Table 3-253. DxTEST Register Field Descriptions.................................................................................................................. 470
Table 3-254. DxINIT Register Field Descriptions.....................................................................................................................471
Table 3-255. DxINITDONE Register Field Descriptions.......................................................................................................... 472
Table 3-256. DxRAMTEST_LOCK Register Field Descriptions...............................................................................................473
Table 3-257. LSxLOCK Register Field Descriptions................................................................................................................ 474
Table 3-258. LSxCOMMIT Register Field Descriptions........................................................................................................... 476
Table 3-259. LSxMSEL Register Field Descriptions................................................................................................................ 478
Table 3-260. LSxCLAPGM Register Field Descriptions...........................................................................................................480
Table 3-261. LSxACCPROT0 Register Field Descriptions...................................................................................................... 482
Table 3-262. LSxACCPROT1 Register Field Descriptions...................................................................................................... 484
Table 3-263. LSxTEST Register Field Descriptions.................................................................................................................486
Table 3-264. LSxINIT Register Field Descriptions................................................................................................................... 488
Table 3-265. LSxINITDONE Register Field Descriptions.........................................................................................................490
Table 3-266. LSxRAMTEST_LOCK Register Field Descriptions.............................................................................................492
Table 3-267. GSxLOCK Register Field Descriptions............................................................................................................... 493
Table 3-268. GSxCOMMIT Register Field Descriptions.......................................................................................................... 495
Table 3-269. GSxMSEL Register Field Descriptions............................................................................................................... 498
Table 3-270. GSxACCPROT0 Register Field Descriptions..................................................................................................... 500
Table 3-271. GSxACCPROT1 Register Field Descriptions..................................................................................................... 502
Table 3-272. GSxACCPROT2 Register Field Descriptions..................................................................................................... 504
Table 3-273. GSxACCPROT3 Register Field Descriptions..................................................................................................... 506
Table 3-274. GSxTEST Register Field Descriptions................................................................................................................508
Table 3-275. GSxINIT Register Field Descriptions.................................................................................................................. 512
Table 3-276. GSxINITDONE Register Field Descriptions........................................................................................................514
Table 3-277. GSxRAMTEST_LOCK Register Field Descriptions............................................................................................ 516
Table 3-278. MSGxLOCK Register Field Descriptions............................................................................................................ 518
Table 3-279. MSGxCOMMIT Register Field Descriptions....................................................................................................... 520
Table 3-280. MSGxACCPROT0 Register Field Descriptions.................................................................................................. 522

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Table 3-281. MSGxACCPROT1 Register Field Descriptions.................................................................................................. 523

Table 3-282. MSGxACCPROT2 Register Field Descriptions.................................................................................................. 524
Table 3-283. MSGxTEST Register Field Descriptions.............................................................................................................526
Table 3-284. MSGxINIT Register Field Descriptions............................................................................................................... 528
Table 3-285. MSGxINITDONE Register Field Descriptions.....................................................................................................530
Table 3-286. MSGxRAMTEST_LOCK Register Field Descriptions......................................................................................... 532
Table 3-287. ROM_LOCK Register Field Descriptions............................................................................................................534
Table 3-288. ROM_TEST Register Field Descriptions............................................................................................................ 535
Table 3-289. ROM_FORCE_ERROR Register Field Descriptions.......................................................................................... 536
Table 3-290. PERI_MEM_TEST_LOCK Register Field Descriptions...................................................................................... 537
Table 3-291. PERI_MEM_TEST_CONTROL Register Field Descriptions.............................................................................. 538
Table 3-292. MEMORY_ERROR_REGS Registers.................................................................................................................539
Table 3-293. MEMORY_ERROR_REGS Access Type Codes................................................................................................ 539
Table 3-294. UCERRFLG Register Field Descriptions............................................................................................................ 541
Table 3-295. UCERRSET Register Field Descriptions............................................................................................................ 542
Table 3-296. UCERRCLR Register Field Descriptions............................................................................................................ 543
Table 3-297. UCCPUREADDR Register Field Descriptions.................................................................................................... 544
Table 3-298. UCDMAREADDR Register Field Descriptions....................................................................................................545
Table 3-299. UCCLA1READDR Register Field Descriptions...................................................................................................546
Table 3-300. UCECATRAMADDR Register Field Descriptions............................................................................................... 547
Table 3-301. CERRFLG Register Field Descriptions...............................................................................................................548
Table 3-302. CERRSET Register Field Descriptions...............................................................................................................549
Table 3-303. CERRCLR Register Field Descriptions...............................................................................................................550
Table 3-304. CCPUREADDR Register Field Descriptions.......................................................................................................551
Table 3-305. CCLA1READDR Register Field Descriptions..................................................................................................... 552
Table 3-306. CERRCNT Register Field Descriptions.............................................................................................................. 553
Table 3-307. CERRTHRES Register Field Descriptions..........................................................................................................554
Table 3-308. CEINTFLG Register Field Descriptions.............................................................................................................. 555
Table 3-309. CEINTCLR Register Field Descriptions.............................................................................................................. 556
Table 3-310. CEINTSET Register Field Descriptions.............................................................................................................. 557
Table 3-311. CEINTEN Register Field Descriptions.................................................................................................................558
Table 3-312. NMI_INTRUPT_REGS Registers....................................................................................................................... 559
Table 3-313. NMI_INTRUPT_REGS Access Type Codes.......................................................................................................559
Table 3-314. NMICFG Register Field Descriptions..................................................................................................................560
Table 3-315. NMIFLG Register Field Descriptions.................................................................................................................. 561
Table 3-316. NMIFLGCLR Register Field Descriptions........................................................................................................... 564
Table 3-317. NMIFLGFRC Register Field Descriptions........................................................................................................... 567
Table 3-318. NMIWDCNT Register Field Descriptions............................................................................................................ 569
Table 3-319. NMIWDPRD Register Field Descriptions............................................................................................................570
Table 3-320. NMISHDFLG Register Field Descriptions...........................................................................................................571
Table 3-321. ERRORSTS Register Field Descriptions............................................................................................................ 574
Table 3-322. ERRORSTSCLR Register Field Descriptions.....................................................................................................575
Table 3-323. ERRORSTSFRC Register Field Descriptions.....................................................................................................576
Table 3-324. ERRORCTL Register Field Descriptions............................................................................................................ 577
Table 3-325. ERRORLOCK Register Field Descriptions......................................................................................................... 578
Table 3-326. PIE_CTRL_REGS Registers.............................................................................................................................. 579
Table 3-327. PIE_CTRL_REGS Access Type Codes..............................................................................................................579
Table 3-328. PIECTRL Register Field Descriptions.................................................................................................................581
Table 3-329. PIEACK Register Field Descriptions...................................................................................................................582
Table 3-330. PIEIER1 Register Field Descriptions.................................................................................................................. 583
Table 3-331. PIEIFR1 Register Field Descriptions.................................................................................................................. 584
Table 3-332. PIEIER2 Register Field Descriptions.................................................................................................................. 586
Table 3-333. PIEIFR2 Register Field Descriptions.................................................................................................................. 587
Table 3-334. PIEIER3 Register Field Descriptions.................................................................................................................. 589
Table 3-335. PIEIFR3 Register Field Descriptions.................................................................................................................. 590
Table 3-336. PIEIER4 Register Field Descriptions.................................................................................................................. 592
Table 3-337. PIEIFR4 Register Field Descriptions.................................................................................................................. 593
Table 3-338. PIEIER5 Register Field Descriptions.................................................................................................................. 595
Table 3-339. PIEIFR5 Register Field Descriptions.................................................................................................................. 596
Table 3-340. PIEIER6 Register Field Descriptions.................................................................................................................. 598
Table 3-341. PIEIFR6 Register Field Descriptions.................................................................................................................. 599

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Table 3-342. PIEIER7 Register Field Descriptions.................................................................................................................. 601

Table 3-343. PIEIFR7 Register Field Descriptions.................................................................................................................. 602
Table 3-344. PIEIER8 Register Field Descriptions.................................................................................................................. 604
Table 3-345. PIEIFR8 Register Field Descriptions.................................................................................................................. 605
Table 3-346. PIEIER9 Register Field Descriptions.................................................................................................................. 607
Table 3-347. PIEIFR9 Register Field Descriptions.................................................................................................................. 608
Table 3-348. PIEIER10 Register Field Descriptions................................................................................................................ 610
Table 3-349. PIEIFR10 Register Field Descriptions.................................................................................................................611
Table 3-350. PIEIER11 Register Field Descriptions.................................................................................................................613
Table 3-351. PIEIFR11 Register Field Descriptions.................................................................................................................614
Table 3-352. PIEIER12 Register Field Descriptions................................................................................................................ 616
Table 3-353. PIEIFR12 Register Field Descriptions................................................................................................................ 617
Table 3-354. ROM_PREFETCH_REGS Registers..................................................................................................................619
Table 3-355. ROM_PREFETCH_REGS Access Type Codes................................................................................................. 619
Table 3-356. ROMPREFETCH Register Field Descriptions.................................................................................................... 620
Table 3-357. ROM_WAIT_STATE_REGS Registers............................................................................................................... 621
Table 3-358. ROM_WAIT_STATE_REGS Access Type Codes...............................................................................................621
Table 3-359. ROMWAITSTATE Register Field Descriptions....................................................................................................622
Table 3-360. SYNC_SOC_REGS Registers............................................................................................................................623
Table 3-361. SYNC_SOC_REGS Access Type Codes........................................................................................................... 623
Table 3-362. SYNCSELECT Register Field Descriptions........................................................................................................ 624
Table 3-363. ADCSOCOUTSELECT Register Field Descriptions........................................................................................... 626
Table 3-364. SYNCSOCLOCK Register Field Descriptions.................................................................................................... 629
Table 3-365. SYS_STATUS_REGS Registers.........................................................................................................................630
Table 3-366. SYS_STATUS_REGS Access Type Codes........................................................................................................ 630
Table 3-367. CM_STATUS_INT_FLG Register Field Descriptions.......................................................................................... 631
Table 3-368. CM_STATUS_INT_CLR Register Field Descriptions..........................................................................................632
Table 3-369. CM_STATUS_INT_SET Register Field Descriptions.......................................................................................... 633
Table 3-370. CM_STATUS_MASK Register Field Descriptions...............................................................................................634
Table 3-371. SYS_ERR_INT_FLG Register Field Descriptions.............................................................................................. 635
Table 3-372. SYS_ERR_INT_CLR Register Field Descriptions.............................................................................................. 637
Table 3-373. SYS_ERR_INT_SET Register Field Descriptions.............................................................................................. 639
Table 3-374. SYS_ERR_MASK Register Field Descriptions................................................................................................... 641
Table 3-375. TEST_ERROR_REGS Registers....................................................................................................................... 643
Table 3-376. TEST_ERROR_REGS Access Type Codes.......................................................................................................643
Table 3-377. CPU_RAM_TEST_ERROR_STS Register Field Descriptions........................................................................... 644
Table 3-378. CPU_RAM_TEST_ERROR_STS_CLR Register Field Descriptions.................................................................. 645
Table 3-379. CPU_RAM_TEST_ERROR_ADDR Register Field Descriptions........................................................................ 646
Table 3-380. UID_REGS Registers......................................................................................................................................... 647
Table 3-381. UID_REGS Access Type Codes.........................................................................................................................647
Table 3-382. UID_PSRAND0 Register Field Descriptions.......................................................................................................648
Table 3-383. UID_PSRAND1 Register Field Descriptions.......................................................................................................649
Table 3-384. UID_PSRAND2 Register Field Descriptions.......................................................................................................650
Table 3-385. UID_PSRAND3 Register Field Descriptions.......................................................................................................651
Table 3-386. UID_PSRAND4 Register Field Descriptions.......................................................................................................652
Table 3-387. UID_PSRAND5 Register Field Descriptions.......................................................................................................653
Table 3-388. UID_UNIQUE Register Field Descriptions..........................................................................................................654
Table 3-389. UID_CHECKSUM Register Field Descriptions................................................................................................... 655
Table 3-390. WD_REGS Registers..........................................................................................................................................656
Table 3-391. WD_REGS Access Type Codes......................................................................................................................... 656
Table 3-392. SCSR Register Field Descriptions...................................................................................................................... 657
Table 3-393. WDCNTR Register Field Descriptions................................................................................................................ 658
Table 3-394. WDKEY Register Field Descriptions...................................................................................................................659
Table 3-395. WDCR Register Field Descriptions.....................................................................................................................660
Table 3-396. WDWCR Register Field Descriptions................................................................................................................. 662
Table 3-397. XINT_REGS Registers....................................................................................................................................... 663
Table 3-398. XINT_REGS Access Type Codes.......................................................................................................................663
Table 3-399. XINT1CR Register Field Descriptions.................................................................................................................664
Table 3-400. XINT2CR Register Field Descriptions.................................................................................................................665
Table 3-401. XINT3CR Register Field Descriptions.................................................................................................................666
Table 3-402. XINT4CR Register Field Descriptions.................................................................................................................667

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Table 3-403. XINT5CR Register Field Descriptions.................................................................................................................668

Table 3-404. XINT1CTR Register Field Descriptions.............................................................................................................. 669
Table 3-405. XINT2CTR Register Field Descriptions.............................................................................................................. 670
Table 3-406. XINT3CTR Register Field Descriptions.............................................................................................................. 671
Table 3-407. ASYSCTL Registers to Driverlib Functions.........................................................................................................672
Table 3-408. CPUTIMER Registers to Driverlib Functions...................................................................................................... 672
Table 3-409. DCSM Registers to Driverlib Functions.............................................................................................................. 673
Table 3-410. MEMCFG Registers to Driverlib Functions......................................................................................................... 677
Table 3-411. NMI Registers to Driverlib Functions...................................................................................................................682
Table 3-412. PIE Registers to Driverlib Functions................................................................................................................... 682
Table 3-413. SYSCTL Registers to Driverlib Functions........................................................................................................... 684
Table 3-414. WWD Registers to Driverlib Functions................................................................................................................694
Table 3-415. XINT Registers to Driverlib Functions.................................................................................................................695
Table 4-1. TMU Supported Instructions................................................................................................................................... 699
Table 5-1. Boot System Overview............................................................................................................................................702
Table 5-2. ROM Memory..........................................................................................................................................................702
Table 5-3. CPU1 Boot ROM Sequence................................................................................................................................... 703
Table 5-4. CPU2 Boot ROM Sequence................................................................................................................................... 703
Table 5-5. CM Boot ROM Sequence....................................................................................................................................... 704
Table 5-6. Device Default Boot Modes for CPU1.....................................................................................................................704
Table 5-7. CPU1 Flash-to-USB Boot Decision Table............................................................................................................... 704
Table 5-8. All Available Boot Modes........................................................................................................................................ 705
Table 5-9. CPU1 BOOTPINCONFIG Bit Fields....................................................................................................................... 706
Table 5-10. CPU1 Standalone Boot Mode Select Pin Decoding............................................................................................. 707
Table 5-11. CPU1 BOOTDEF Bit Fields...................................................................................................................................708
Table 5-12. Zero Boot Pin Boot Table Result...........................................................................................................................709
Table 5-13. One Boot Pin Boot Table Result........................................................................................................................... 709
Table 5-14. Three Boot Pins Boot Table Result....................................................................................................................... 710
Table 5-15. Boot ROM Reset Causes and Actions..................................................................................................................716
Table 5-16. Boot ROM Exceptions and Actions.......................................................................................................................717
Table 5-17. CPU1 Boot ROM Registers.................................................................................................................................. 718
Table 5-18. CPU1 DCSM Z1/Z2 GPREG2 Bit Fields...............................................................................................................719
Table 5-19. CPU2 Boot Procedure.......................................................................................................................................... 720
Table 5-20. CM Boot Procedure.............................................................................................................................................. 720
Table 5-21. CPU1TOCPU2IPCBOOTMODE Register Details.................................................................................................721
Table 5-22. CPU1TOCMIPCBOOTMODE Register Details.....................................................................................................722
Table 5-23. CPU2 to CPU1 Error IPC Commands.................................................................................................................. 723
Table 5-24. CM to CPU1 Error IPC Commands...................................................................................................................... 723
Table 5-25. Entry Point Addresses for CPU1...........................................................................................................................724
Table 5-26. Entry Point Addresses for CPU2...........................................................................................................................724
Table 5-27. Entry Point Addresses for CM...............................................................................................................................724
Table 5-28. Wait Point Addresses for CPU1............................................................................................................................ 725
Table 5-29. Wait Point Addresses for CPU2............................................................................................................................ 725
Table 5-30. Wait Point Addresses for CM................................................................................................................................ 725
Table 5-31. CPU1 Boot ROM Memory Map.............................................................................................................................726
Table 5-32. CPU2 Boot ROM Memory Map.............................................................................................................................726
Table 5-33. CM Boot ROM Memory Map.................................................................................................................................727
Table 5-34. CPU1 CLA Data ROM Memory Map.................................................................................................................... 727
Table 5-35. CPU2 CLA Data ROM Memory Map.................................................................................................................... 727
Table 5-36. CPU1 Reserved RAM Memory Map..................................................................................................................... 728
Table 5-37. CPU2 Reserved RAM Memory Map..................................................................................................................... 728
Table 5-38. CM Reserved RAM Memory Map......................................................................................................................... 728
Table 5-39. ROM Symbol Tables............................................................................................................................................. 728
Table 5-40. Boot Mode Availability...........................................................................................................................................729
Table 5-41. Reasons for Entering Wait Boot............................................................................................................................729
Table 5-42. Secure Flash Tag and Key Details........................................................................................................................730
Table 5-43. Secure Flash Authentication Failure Actions........................................................................................................ 731
Table 5-44. Secure Flash on all CPUs Recommended Flow...................................................................................................731
Table 5-45. IPC Message Copy Steps.....................................................................................................................................732
Table 5-46. IPC Message Copy Destination Address..............................................................................................................732
Table 5-47. SPI 8-Bit Data Stream...........................................................................................................................................734

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Table 5-48. I2C 8-Bit Data Stream...........................................................................................................................................738

Table 5-49. Parallel GPIO Boot 8-Bit Data Stream.................................................................................................................. 739
Table 5-50. Bit-Rate Value for Internal Oscillators................................................................................................................... 743
Table 5-51. CAN 8-Bit Data Stream.........................................................................................................................................744
Table 5-52. USB 8-Bit Data Stream......................................................................................................................................... 746
Table 5-53. SCI Boot Options.................................................................................................................................................. 747
Table 5-54. CAN Boot Options.................................................................................................................................................747
Table 5-55. I2C Boot Options...................................................................................................................................................747
Table 5-56. USB Boot Options.................................................................................................................................................747
Table 5-57. RAM Boot Options................................................................................................................................................ 748
Table 5-58. Flash Boot Options............................................................................................................................................... 748
Table 5-59. Secure Flash Boot Options................................................................................................................................... 748
Table 5-60. Wait Boot Options................................................................................................................................................. 748
Table 5-61. SPI Boot Options.................................................................................................................................................. 748
Table 5-62. Parallel Boot Options............................................................................................................................................ 749
Table 5-63. Secure Copy Code Function.................................................................................................................................750
Table 5-64. Secure CRC Calculation Function........................................................................................................................ 750
Table 5-65. Secure Flash CMAC Calculation Function............................................................................................................751
Table 5-66. CPU1 Boot Clock Sources....................................................................................................................................753
Table 5-67. CPU1 Clock State After Boot................................................................................................................................ 753
Table 5-68. CPU1 Boot Status Address...................................................................................................................................754
Table 5-69. CPU1 Boot Status Bit Fields................................................................................................................................. 754
Table 5-70. CPU2 Boot ROM Status Address......................................................................................................................... 755
Table 5-71. CPU2 Boot Status Bit Fields................................................................................................................................. 755
Table 5-72. CM Boot ROM Status Address............................................................................................................................. 756
Table 5-73. CM Boot Status Bit Fields..................................................................................................................................... 756
Table 5-74. Boot Mode and MPOST Status Addresses...........................................................................................................757
Table 5-75. Boot ROM Version Information for CPU1............................................................................................................. 757
Table 5-76. Boot ROM Version Information for CPU2............................................................................................................. 757
Table 5-77. Boot ROM Version Information for CM................................................................................................................. 757
Table 5-78. LSB/MSB Loading Sequence in 8-Bit Data Stream.............................................................................................. 759
Table 5-79. Boot Loader Options............................................................................................................................................. 761
Table 6-1. RAM/Flash Status................................................................................................................................................... 767
Table 6-2. Security Levels........................................................................................................................................................767
Table 6-3. Default Value of ZxOTP (Programmed by TI)......................................................................................................... 769
Table 6-4. DCSM Base Address Table (C28).......................................................................................................................... 784
Table 6-5. CM DCSM Base Address Table (CM).....................................................................................................................784
Table 6-6. DCSM_Z1_REGS Registers...................................................................................................................................785
Table 6-7. DCSM_Z1_REGS Access Type Codes.................................................................................................................. 785
Table 6-8. Z1_LINKPOINTER Register Field Descriptions......................................................................................................787
Table 6-9. Z1_OTPSECLOCK Register Field Descriptions..................................................................................................... 788
Table 6-10. Z1_JLM_ENABLE Register Field Descriptions.....................................................................................................789
Table 6-11. Z1_LINKPOINTERERR Register Field Descriptions.............................................................................................790
Table 6-12. Z1_GPREG1 Register Field Descriptions.............................................................................................................791
Table 6-13. Z1_GPREG2 Register Field Descriptions.............................................................................................................792
Table 6-14. Z1_GPREG3 Register Field Descriptions.............................................................................................................793
Table 6-15. Z1_GPREG4 Register Field Descriptions.............................................................................................................794
Table 6-16. Z1_CSMKEY0 Register Field Descriptions...........................................................................................................795
Table 6-17. Z1_CSMKEY1 Register Field Descriptions...........................................................................................................796
Table 6-18. Z1_CSMKEY2 Register Field Descriptions...........................................................................................................797
Table 6-19. Z1_CSMKEY3 Register Field Descriptions...........................................................................................................798
Table 6-20. Z1_CR Register Field Descriptions.......................................................................................................................799
Table 6-21. Z1_GRABSECT1R Register Field Descriptions................................................................................................... 800
Table 6-22. Z1_GRABSECT2R Register Field Descriptions................................................................................................... 803
Table 6-23. Z1_GRABSECT3R Register Field Descriptions................................................................................................... 806
Table 6-24. Z1_GRABRAM1R Register Field Descriptions..................................................................................................... 809
Table 6-25. Z1_GRABRAM2R Register Field Descriptions..................................................................................................... 811
Table 6-26. Z1_GRABRAM3R Register Field Descriptions..................................................................................................... 814
Table 6-27. Z1_EXEONLYSECT1R Register Field Descriptions............................................................................................. 816
Table 6-28. Z1_EXEONLYSECT2R Register Field Descriptions............................................................................................. 820
Table 6-29. Z1_EXEONLYRAM1R Register Field Descriptions...............................................................................................823

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Table 6-30. Z1_JTAGKEY0 Register Field Descriptions..........................................................................................................827

Table 6-31. Z1_JTAGKEY1 Register Field Descriptions..........................................................................................................828
Table 6-32. Z1_JTAGKEY2 Register Field Descriptions..........................................................................................................829
Table 6-33. Z1_JTAGKEY3 Register Field Descriptions..........................................................................................................830
Table 6-34. Z1_CMACKEY0 Register Field Descriptions........................................................................................................ 831
Table 6-35. Z1_CMACKEY1 Register Field Descriptions........................................................................................................ 832
Table 6-36. Z1_CMACKEY2 Register Field Descriptions........................................................................................................ 833
Table 6-37. Z1_CMACKEY3 Register Field Descriptions........................................................................................................ 834
Table 6-38. DCSM_Z2_REGS Registers.................................................................................................................................835
Table 6-39. DCSM_Z2_REGS Access Type Codes................................................................................................................ 835
Table 6-40. Z2_LINKPOINTER Register Field Descriptions....................................................................................................837
Table 6-41. Z2_OTPSECLOCK Register Field Descriptions................................................................................................... 838
Table 6-42. Z2_LINKPOINTERERR Register Field Descriptions............................................................................................ 839
Table 6-43. Z2_GPREG1 Register Field Descriptions.............................................................................................................840
Table 6-44. Z2_GPREG2 Register Field Descriptions.............................................................................................................841
Table 6-45. Z2_GPREG3 Register Field Descriptions.............................................................................................................842
Table 6-46. Z2_GPREG4 Register Field Descriptions.............................................................................................................843
Table 6-47. Z2_CSMKEY0 Register Field Descriptions...........................................................................................................844
Table 6-48. Z2_CSMKEY1 Register Field Descriptions...........................................................................................................845
Table 6-49. Z2_CSMKEY2 Register Field Descriptions...........................................................................................................846
Table 6-50. Z2_CSMKEY3 Register Field Descriptions...........................................................................................................847
Table 6-51. Z2_CR Register Field Descriptions.......................................................................................................................848
Table 6-52. Z2_GRABSECT1R Register Field Descriptions................................................................................................... 849
Table 6-53. Z2_GRABSECT2R Register Field Descriptions................................................................................................... 852
Table 6-54. Z2_GRABSECT3R Register Field Descriptions................................................................................................... 855
Table 6-55. Z2_GRABRAM1R Register Field Descriptions..................................................................................................... 858
Table 6-56. Z2_GRABRAM2R Register Field Descriptions..................................................................................................... 860
Table 6-57. Z2_GRABRAM3R Register Field Descriptions..................................................................................................... 863
Table 6-58. Z2_EXEONLYSECT1R Register Field Descriptions............................................................................................. 865
Table 6-59. Z2_EXEONLYSECT2R Register Field Descriptions............................................................................................. 869
Table 6-60. Z2_EXEONLYRAM1R Register Field Descriptions...............................................................................................872
Table 6-61. DCSM_COMMON_REGS Registers.................................................................................................................... 876
Table 6-62. DCSM_COMMON_REGS Access Type Codes....................................................................................................876
Table 6-63. FLSEM Register Field Descriptions...................................................................................................................... 877
Table 6-64. SECTSTAT1 Register Field Descriptions..............................................................................................................878
Table 6-65. SECTSTAT2 Register Field Descriptions..............................................................................................................881
Table 6-66. SECTSTAT3 Register Field Descriptions..............................................................................................................884
Table 6-67. RAMSTAT1 Register Field Descriptions............................................................................................................... 887
Table 6-68. RAMSTAT2 Register Field Descriptions............................................................................................................... 889
Table 6-69. RAMSTAT3 Register Field Descriptions............................................................................................................... 892
Table 6-70. SECERRSTAT Register Field Descriptions.......................................................................................................... 894
Table 6-71. SECERRCLR Register Field Descriptions............................................................................................................895
Table 6-72. SECERRFRC Register Field Descriptions............................................................................................................896
Table 6-73. DCSM_Z1_OTP Registers....................................................................................................................................897
Table 6-74. DCSM_Z1_OTP Access Type Codes................................................................................................................... 897
Table 6-75. Z1OTP_LINKPOINTER1 Register Field Descriptions.......................................................................................... 898
Table 6-76. Z1OTP_LINKPOINTER2 Register Field Descriptions.......................................................................................... 899
Table 6-77. Z1OTP_LINKPOINTER3 Register Field Descriptions.......................................................................................... 900
Table 6-78. Z1OTP_JLM_ENABLE Register Field Descriptions............................................................................................. 901
Table 6-79. Z1OTP_GPREG1 Register Field Descriptions..................................................................................................... 902
Table 6-80. Z1OTP_GPREG2 Register Field Descriptions..................................................................................................... 903
Table 6-81. Z1OTP_GPREG3 Register Field Descriptions..................................................................................................... 904
Table 6-82. Z1OTP_GPREG4 Register Field Descriptions..................................................................................................... 905
Table 6-83. Z1OTP_PSWDLOCK Register Field Descriptions................................................................................................906
Table 6-84. Z1OTP_CRCLOCK Register Field Descriptions...................................................................................................907
Table 6-85. Z1OTP_JTAGPSWDH0 Register Field Descriptions............................................................................................ 908
Table 6-86. Z1OTP_JTAGPSWDH1 Register Field Descriptions............................................................................................ 909
Table 6-87. Z1OTP_CMACKEY0 Register Field Descriptions.................................................................................................910
Table 6-88. Z1OTP_CMACKEY1 Register Field Descriptions................................................................................................. 911
Table 6-89. Z1OTP_CMACKEY2 Register Field Descriptions.................................................................................................912
Table 6-90. Z1OTP_CMACKEY3 Register Field Descriptions.................................................................................................913

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Table 6-91. DCSM_Z2_OTP Registers....................................................................................................................................914

Table 6-92. DCSM_Z2_OTP Access Type Codes................................................................................................................... 914
Table 6-93. Z2OTP_LINKPOINTER1 Register Field Descriptions.......................................................................................... 915
Table 6-94. Z2OTP_LINKPOINTER2 Register Field Descriptions.......................................................................................... 916
Table 6-95. Z2OTP_LINKPOINTER3 Register Field Descriptions.......................................................................................... 917
Table 6-96. Z2OTP_GPREG1 Register Field Descriptions..................................................................................................... 918
Table 6-97. Z2OTP_GPREG2 Register Field Descriptions..................................................................................................... 919
Table 6-98. Z2OTP_GPREG3 Register Field Descriptions..................................................................................................... 920
Table 6-99. Z2OTP_GPREG4 Register Field Descriptions..................................................................................................... 921
Table 6-100. Z2OTP_PSWDLOCK Register Field Descriptions..............................................................................................922
Table 6-101. Z2OTP_CRCLOCK Register Field Descriptions.................................................................................................923
Table 7-1. BGCRC Register Groups........................................................................................................................................931
Table 7-2. Data Address Location Example 1..........................................................................................................................934
Table 7-3. Data Address Location Example 2..........................................................................................................................934
Table 7-4. Data Address Location Example 3..........................................................................................................................934
Table 7-5. BGCRC Base Address Table (C28)........................................................................................................................ 936
Table 7-6. BGCRC_REGS Registers.......................................................................................................................................937
Table 7-7. BGCRC_REGS Access Type Codes...................................................................................................................... 937
Table 7-8. BGCRC_EN Register Field Descriptions................................................................................................................ 939
Table 7-9. BGCRC_CTRL1 Register Field Descriptions..........................................................................................................940
Table 7-10. BGCRC_CTRL2 Register Field Descriptions........................................................................................................941
Table 7-11. BGCRC_START_ADDR Register Field Descriptions............................................................................................942
Table 7-12. BGCRC_SEED Register Field Descriptions......................................................................................................... 943
Table 7-13. BGCRC_GOLDEN Register Field Descriptions....................................................................................................944
Table 7-14. BGCRC_RESULT Register Field Descriptions..................................................................................................... 945
Table 7-15. BGCRC_CURR_ADDR Register Field Descriptions............................................................................................ 946
Table 7-16. BGCRC_WD_CFG Register Field Descriptions................................................................................................... 947
Table 7-17. BGCRC_WD_MIN Register Field Descriptions.................................................................................................... 948
Table 7-18. BGCRC_WD_MAX Register Field Descriptions................................................................................................... 949
Table 7-19. BGCRC_WD_CNT Register Field Descriptions....................................................................................................950
Table 7-20. BGCRC_NMIFLG Register Field Descriptions..................................................................................................... 951
Table 7-21. BGCRC_NMICLR Register Field Descriptions..................................................................................................... 952
Table 7-22. BGCRC_NMIFRC Register Field Descriptions..................................................................................................... 953
Table 7-23. BGCRC_INTEN Register Field Descriptions........................................................................................................ 954
Table 7-24. BGCRC_INTFLG Register Field Descriptions...................................................................................................... 955
Table 7-25. BGCRC_INTCLR Register Field Descriptions...................................................................................................... 957
Table 7-26. BGCRC_INTFRC Register Field Descriptions......................................................................................................958
Table 7-27. BGCRC_LOCK Register Field Descriptions......................................................................................................... 959
Table 7-28. BGCRC_COMMIT Register Field Descriptions.................................................................................................... 961
Table 7-29. BGCRC Registers to Driverlib Functions.............................................................................................................. 963
Table 8-1. Configuration Options............................................................................................................................................. 970
Table 8-2. Pipeline Behavior of the MDEBUGSTOP1 Instruction............................................................................................ 979
Table 8-3. Write Followed by Read - Read Occurs First..........................................................................................................983
Table 8-4. Write Followed by Read - Write Occurs First.......................................................................................................... 983
Table 8-5. ADC to CLA Early Interrupt Response....................................................................................................................987
Table 8-6. Operand Nomenclature...........................................................................................................................................994
Table 8-7. INSTRUCTION dest, source1, source2 Short Description..................................................................................... 995
Table 8-8. Addressing Modes.................................................................................................................................................. 996
Table 8-9. Shift Field Encoding................................................................................................................................................ 996
Table 8-10. Operand Encoding................................................................................................................................................ 997
Table 8-11. Condition Field Encoding...................................................................................................................................... 997
Table 8-12. Pipeline Activity for MBCNDD, Branch Not Taken.............................................................................................. 1013
Table 8-13. Pipeline Activity for MBCNDD, Branch Taken.....................................................................................................1013
Table 8-14. Pipeline Activity for MCCNDD, Call Not Taken................................................................................................... 1018
Table 8-15. Pipeline Activity for MCCNDD, Call Taken..........................................................................................................1019
Table 8-16. Pipeline Activity for MMOV16 MARx, MRa , #16I............................................................................................... 1055
Table 8-17. Pipeline Activity for MMOV16 MAR0/MAR1, mem16......................................................................................... 1058
Table 8-18. Pipeline Activity for MMOVI16 MAR0/MAR1, #16I............................................................................................. 1074
Table 8-19. Pipeline Activity for MRCNDD, Return Not Taken...............................................................................................1097
Table 8-20. Pipeline Activity for MRCNDD, Return Taken..................................................................................................... 1097
Table 8-21. Pipeline Activity for MSTOP................................................................................................................................ 1101

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Table 8-22. CLA Base Address Table (C28)...........................................................................................................................1116

Table 8-23. CLA_ONLY_REGS Registers..............................................................................................................................1117
Table 8-24. CLA_ONLY_REGS Access Type Codes............................................................................................................. 1117
Table 8-25. _MVECTBGRNDACTIVE Register Field Descriptions........................................................................................ 1118
Table 8-26. _MPSACTL Register Field Descriptions..............................................................................................................1119
Table 8-27. _MPSA1 Register Field Descriptions.................................................................................................................. 1120
Table 8-28. _MPSA2 Register Field Descriptions.................................................................................................................. 1121
Table 8-29. SOFTINTEN Register Field Descriptions............................................................................................................ 1122
Table 8-30. SOFTINTFRC Register Field Descriptions..........................................................................................................1124
Table 8-31. CLA_SOFTINT_REGS Registers........................................................................................................................1125
Table 8-32. CLA_SOFTINT_REGS Access Type Codes....................................................................................................... 1125
Table 8-33. SOFTINTEN Register Field Descriptions............................................................................................................ 1126
Table 8-34. SOFTINTFRC Register Field Descriptions..........................................................................................................1128
Table 8-35. CLA_REGS Registers......................................................................................................................................... 1129
Table 8-36. CLA_REGS Access Type Codes........................................................................................................................ 1129
Table 8-37. MVECT1 Register Field Descriptions..................................................................................................................1131
Table 8-38. MVECT2 Register Field Descriptions..................................................................................................................1132
Table 8-39. MVECT3 Register Field Descriptions..................................................................................................................1133
Table 8-40. MVECT4 Register Field Descriptions..................................................................................................................1134
Table 8-41. MVECT5 Register Field Descriptions..................................................................................................................1135
Table 8-42. MVECT6 Register Field Descriptions..................................................................................................................1136
Table 8-43. MVECT7 Register Field Descriptions..................................................................................................................1137
Table 8-44. MVECT8 Register Field Descriptions..................................................................................................................1138
Table 8-45. MCTL Register Field Descriptions.......................................................................................................................1139
Table 8-46. _MVECTBGRNDACTIVE Register Field Descriptions........................................................................................1140
Table 8-47. SOFTINTEN Register Field Descriptions............................................................................................................ 1141
Table 8-48. _MSTSBGRND Register Field Descriptions....................................................................................................... 1143
Table 8-49. _MCTLBGRND Register Field Descriptions........................................................................................................1144
Table 8-50. _MVECTBGRND Register Field Descriptions.....................................................................................................1145
Table 8-51. MIFR Register Field Descriptions........................................................................................................................1146
Table 8-52. MIOVF Register Field Descriptions..................................................................................................................... 1150
Table 8-53. MIFRC Register Field Descriptions..................................................................................................................... 1153
Table 8-54. MICLR Register Field Descriptions..................................................................................................................... 1155
Table 8-55. MICLROVF Register Field Descriptions..............................................................................................................1157
Table 8-56. MIER Register Field Descriptions....................................................................................................................... 1159
Table 8-57. MIRUN Register Field Descriptions.....................................................................................................................1162
Table 8-58. _MPC Register Field Descriptions...................................................................................................................... 1164
Table 8-59. _MAR0 Register Field Descriptions.................................................................................................................... 1165
Table 8-60. _MAR1 Register Field Descriptions.................................................................................................................... 1166
Table 8-61. _MSTF Register Field Descriptions.....................................................................................................................1167
Table 8-62. _MR0 Register Field Descriptions.......................................................................................................................1170
Table 8-63. _MR1 Register Field Descriptions.......................................................................................................................1171
Table 8-64. _MR2 Register Field Descriptions.......................................................................................................................1172
Table 8-65. _MR3 Register Field Descriptions.......................................................................................................................1173
Table 8-66. _MPSACTL Register Field Descriptions............................................................................................................. 1174
Table 8-67. _MPSA1 Register Field Descriptions.................................................................................................................. 1175
Table 8-68. _MPSA2 Register Field Descriptions.................................................................................................................. 1176
Table 8-69. CLA Registers to Driverlib Functions.................................................................................................................. 1176
Table 9-1. Example CLB Clocking Configuration................................................................................................................... 1182
Table 9-2. Global Signals and Mux Selection.........................................................................................................................1186
Table 9-3. Global Signals and Mux Selection.........................................................................................................................1190
Table 9-4. Local Signals and Mux Selection.......................................................................................................................... 1194
Table 9-5. Local Signals and Mux Selection.......................................................................................................................... 1196
Table 9-6. CLB Output Signal Multiplexer Table.................................................................................................................... 1200
Table 9-7. CLB Output Signal Multiplexer Table.................................................................................................................... 1201
Table 9-8. Output Table..........................................................................................................................................................1204
Table 9-9. Input Table............................................................................................................................................................ 1205
Table 9-10. Ports Tied Off to Prevent Combinatorial Loops...................................................................................................1205
Table 9-11. Counter Block Operating Modes......................................................................................................................... 1208
Table 9-12. HLC Event List.................................................................................................................................................... 1217
Table 9-13. HLC ALT Event List.............................................................................................................................................1218

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Table 9-14. HLC Instruction Address Ranges........................................................................................................................1219

Table 9-15. HLC Instruction Format.......................................................................................................................................1219
Table 9-16. HLC Instruction Description................................................................................................................................ 1219
Table 9-17. HLC Register Encoding...................................................................................................................................... 1220
Table 9-18. Non-Memory Mapped Register Addresses.........................................................................................................1222
Table 9-19. CLB to SPI RX Access........................................................................................................................................1223
Table 9-20. CLB Base Address Table (C28).......................................................................................................................... 1230
Table 9-21. CLB_LOGIC_CONFIG_REGS Registers........................................................................................................... 1232
Table 9-22. CLB_LOGIC_CONFIG_REGS Access Type Codes...........................................................................................1233
Table 9-23. CLB_COUNT_RESET Register Field Descriptions............................................................................................ 1234
Table 9-24. CLB_COUNT_MODE_1 Register Field Descriptions......................................................................................... 1235
Table 9-25. CLB_COUNT_MODE_0 Register Field Descriptions......................................................................................... 1236
Table 9-26. CLB_COUNT_EVENT Register Field Descriptions............................................................................................ 1237
Table 9-27. CLB_FSM_EXTRA_IN0 Register Field Descriptions..........................................................................................1238
Table 9-28. CLB_FSM_EXTERNAL_IN0 Register Field Descriptions...................................................................................1239
Table 9-29. CLB_FSM_EXTERNAL_IN1 Register Field Descriptions...................................................................................1240
Table 9-30. CLB_FSM_EXTRA_IN1 Register Field Descriptions..........................................................................................1241
Table 9-31. CLB_LUT4_IN0 Register Field Descriptions.......................................................................................................1242
Table 9-32. CLB_LUT4_IN1 Register Field Descriptions.......................................................................................................1243
Table 9-33. CLB_LUT4_IN2 Register Field Descriptions.......................................................................................................1244
Table 9-34. CLB_LUT4_IN3 Register Field Descriptions.......................................................................................................1245
Table 9-35. CLB_FSM_LUT_FN1_0 Register Field Descriptions..........................................................................................1246
Table 9-36. CLB_FSM_LUT_FN2 Register Field Descriptions..............................................................................................1247
Table 9-37. CLB_LUT4_FN1_0 Register Field Descriptions................................................................................................. 1248
Table 9-38. CLB_LUT4_FN2 Register Field Descriptions..................................................................................................... 1249
Table 9-39. CLB_FSM_NEXT_STATE_0 Register Field Descriptions...................................................................................1250
Table 9-40. CLB_FSM_NEXT_STATE_1 Register Field Descriptions...................................................................................1251
Table 9-41. CLB_FSM_NEXT_STATE_2 Register Field Descriptions...................................................................................1252
Table 9-42. CLB_MISC_CONTROL Register Field Descriptions.......................................................................................... 1253
Table 9-43. CLB_OUTPUT_LUT_0 Register Field Descriptions........................................................................................... 1256
Table 9-44. CLB_OUTPUT_LUT_1 Register Field Descriptions........................................................................................... 1257
Table 9-45. CLB_OUTPUT_LUT_2 Register Field Descriptions........................................................................................... 1258
Table 9-46. CLB_OUTPUT_LUT_3 Register Field Descriptions........................................................................................... 1259
Table 9-47. CLB_OUTPUT_LUT_4 Register Field Descriptions........................................................................................... 1260
Table 9-48. CLB_OUTPUT_LUT_5 Register Field Descriptions........................................................................................... 1261
Table 9-49. CLB_OUTPUT_LUT_6 Register Field Descriptions........................................................................................... 1262
Table 9-50. CLB_OUTPUT_LUT_7 Register Field Descriptions........................................................................................... 1263
Table 9-51. CLB_HLC_EVENT_SEL Register Field Descriptions......................................................................................... 1264
Table 9-52. CLB_COUNT_MATCH_TAP_SEL Register Field Descriptions.......................................................................... 1265
Table 9-53. CLB_OUTPUT_COND_CTRL_0 Register Field Descriptions............................................................................ 1266
Table 9-54. CLB_OUTPUT_COND_CTRL_1 Register Field Descriptions............................................................................ 1268
Table 9-55. CLB_OUTPUT_COND_CTRL_2 Register Field Descriptions............................................................................ 1270
Table 9-56. CLB_OUTPUT_COND_CTRL_3 Register Field Descriptions............................................................................ 1272
Table 9-57. CLB_OUTPUT_COND_CTRL_4 Register Field Descriptions............................................................................ 1274
Table 9-58. CLB_OUTPUT_COND_CTRL_5 Register Field Descriptions............................................................................ 1276
Table 9-59. CLB_OUTPUT_COND_CTRL_6 Register Field Descriptions............................................................................ 1278
Table 9-60. CLB_OUTPUT_COND_CTRL_7 Register Field Descriptions............................................................................ 1280
Table 9-61. CLB_MISC_ACCESS_CTRL Register Field Descriptions..................................................................................1282
Table 9-62. CLB_SPI_DATA_CTRL_HI Register Field Descriptions..................................................................................... 1283
Table 9-63. CLB_LOGIC_CONTROL_REGS Registers........................................................................................................1284
Table 9-64. CLB_LOGIC_CONTROL_REGS Access Type Codes....................................................................................... 1284
Table 9-65. CLB_LOAD_EN Register Field Descriptions...................................................................................................... 1286
Table 9-66. CLB_LOAD_ADDR Register Field Descriptions................................................................................................. 1287
Table 9-67. CLB_LOAD_DATA Register Field Descriptions.................................................................................................. 1288
Table 9-68. CLB_INPUT_FILTER Register Field Descriptions.............................................................................................. 1289
Table 9-69. CLB_IN_MUX_SEL_0 Register Field Descriptions.............................................................................................1291
Table 9-70. CLB_LCL_MUX_SEL_1 Register Field Descriptions..........................................................................................1293
Table 9-71. CLB_LCL_MUX_SEL_2 Register Field Descriptions..........................................................................................1294
Table 9-72. CLB_BUF_PTR Register Field Descriptions.......................................................................................................1295
Table 9-73. CLB_GP_REG Register Field Descriptions........................................................................................................ 1296
Table 9-74. CLB_OUT_EN Register Field Descriptions........................................................................................................ 1298

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Table 9-75. CLB_GLBL_MUX_SEL_1 Register Field Descriptions....................................................................................... 1299

Table 9-76. CLB_GLBL_MUX_SEL_2 Register Field Descriptions....................................................................................... 1300
Table 9-77. CLB_PRESCALE_CTRL Register Field Descriptions........................................................................................ 1301
Table 9-78. CLB_INTR_TAG_REG Register Field Descriptions............................................................................................1302
Table 9-79. CLB_LOCK Register Field Descriptions............................................................................................................. 1303
Table 9-80. CLB_HLC_INSTR_READ_PTR Register Field Descriptions..............................................................................1304
Table 9-81. CLB_HLC_INSTR_VALUE Register Field Descriptions......................................................................................1305
Table 9-82. CLB_DBG_OUT_2 Register Field Descriptions..................................................................................................1306
Table 9-83. CLB_DBG_R0 Register Field Descriptions.........................................................................................................1307
Table 9-84. CLB_DBG_R1 Register Field Descriptions.........................................................................................................1308
Table 9-85. CLB_DBG_R2 Register Field Descriptions.........................................................................................................1309
Table 9-86. CLB_DBG_R3 Register Field Descriptions.........................................................................................................1310
Table 9-87. CLB_DBG_C0 Register Field Descriptions......................................................................................................... 1311
Table 9-88. CLB_DBG_C1 Register Field Descriptions.........................................................................................................1312
Table 9-89. CLB_DBG_C2 Register Field Descriptions.........................................................................................................1313
Table 9-90. CLB_DBG_OUT Register Field Descriptions......................................................................................................1314
Table 9-91. CLB_DATA_EXCHANGE_REGS Registers....................................................................................................... 1316
Table 9-92. CLB_DATA_EXCHANGE_REGS Access Type Codes.......................................................................................1316
Table 9-93. CLB_PUSH Register Field Descriptions............................................................................................................. 1317
Table 9-94. CLB_PULL Register Field Descriptions.............................................................................................................. 1318
Table 9-95. CLB Registers to Driverlib Functions.................................................................................................................. 1318
Table 10-1. DCC Base Address Table (C28)......................................................................................................................... 1334
Table 10-2. DCC_REGS Registers........................................................................................................................................1335
Table 10-3. DCC_REGS Access Type Codes....................................................................................................................... 1335
Table 10-4. DCCGCTRL Register Field Descriptions............................................................................................................ 1336
Table 10-5. DCCCNTSEED0 Register Field Descriptions..................................................................................................... 1337
Table 10-6. DCCVALIDSEED0 Register Field Descriptions.................................................................................................. 1338
Table 10-7. DCCCNTSEED1 Register Field Descriptions..................................................................................................... 1339
Table 10-8. DCCSTATUS Register Field Descriptions...........................................................................................................1340
Table 10-9. DCCCNT0 Register Field Descriptions...............................................................................................................1341
Table 10-10. DCCVALID0 Register Field Descriptions.......................................................................................................... 1342
Table 10-11. DCCCNT1 Register Field Descriptions............................................................................................................. 1343
Table 10-12. DCCCLKSRC1 Register Field Descriptions......................................................................................................1344
Table 10-13. DCCCLKSRC0 Register Field Descriptions......................................................................................................1345
Table 10-14. DCC Registers to Driverlib Functions............................................................................................................... 1345
Table 11-1. DMA Trigger Source Options.............................................................................................................................. 1352
Table 11-2. BURSTSIZE versus DATASIZE Behavior........................................................................................................... 1357
Table 11-3. DMA Base Address Table (C28)......................................................................................................................... 1366
Table 11-4. DMA_REGS Registers........................................................................................................................................ 1367
Table 11-5. DMA_REGS Access Type Codes....................................................................................................................... 1367
Table 11-6. DMACTRL Register Field Descriptions............................................................................................................... 1368
Table 11-7. DEBUGCTRL Register Field Descriptions.......................................................................................................... 1369
Table 11-8. PRIORITYCTRL1 Register Field Descriptions.................................................................................................... 1370
Table 11-9. PRIORITYSTAT Register Field Descriptions.......................................................................................................1371
Table 11-10. DMA_CH_REGS Registers...............................................................................................................................1372
Table 11-11. DMA_CH_REGS Access Type Codes.............................................................................................................. 1372
Table 11-12. MODE Register Field Descriptions....................................................................................................................1374
Table 11-13. CONTROL Register Field Descriptions.............................................................................................................1376
Table 11-14. BURST_SIZE Register Field Descriptions........................................................................................................ 1378
Table 11-15. BURST_COUNT Register Field Descriptions................................................................................................... 1379
Table 11-16. SRC_BURST_STEP Register Field Descriptions............................................................................................. 1380
Table 11-17. DST_BURST_STEP Register Field Descriptions..............................................................................................1381
Table 11-18. TRANSFER_SIZE Register Field Descriptions................................................................................................. 1382
Table 11-19. TRANSFER_COUNT Register Field Descriptions............................................................................................ 1383
Table 11-20. SRC_TRANSFER_STEP Register Field Descriptions...................................................................................... 1384
Table 11-21. DST_TRANSFER_STEP Register Field Descriptions...................................................................................... 1385
Table 11-22. SRC_WRAP_SIZE Register Field Descriptions................................................................................................ 1386
Table 11-23. SRC_WRAP_COUNT Register Field Descriptions........................................................................................... 1387
Table 11-24. SRC_WRAP_STEP Register Field Descriptions...............................................................................................1388
Table 11-25. DST_WRAP_SIZE Register Field Descriptions................................................................................................ 1389
Table 11-26. DST_WRAP_COUNT Register Field Descriptions............................................................................................1390

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Table 11-27. DST_WRAP_STEP Register Field Descriptions............................................................................................... 1391

Table 11-28. SRC_BEG_ADDR_SHADOW Register Field Descriptions...............................................................................1392
Table 11-29. SRC_ADDR_SHADOW Register Field Descriptions........................................................................................ 1393
Table 11-30. SRC_BEG_ADDR_ACTIVE Register Field Descriptions.................................................................................. 1394
Table 11-31. SRC_ADDR_ACTIVE Register Field Descriptions............................................................................................1395
Table 11-32. DST_BEG_ADDR_SHADOW Register Field Descriptions............................................................................... 1396
Table 11-33. DST_ADDR_SHADOW Register Field Descriptions.........................................................................................1397
Table 11-34. DST_BEG_ADDR_ACTIVE Register Field Descriptions.................................................................................. 1398
Table 11-35. DST_ADDR_ACTIVE Register Field Descriptions............................................................................................ 1399
Table 11-36. DMA Registers to Driverlib Functions............................................................................................................... 1399
Table 12-1. Configuration for EMIF1 and EMIF2 Modules.....................................................................................................1404
Table 12-2. EMIF Pins Used to Access Both SDRAM and Asynchronous Memories........................................................... 1408
Table 12-3. EMIF Pins Specific to SDRAM............................................................................................................................1408
Table 12-4. EMIF Pins Specific to Asynchronous Memory.................................................................................................... 1409
Table 12-5. EMIF SDRAM Commands.................................................................................................................................. 1409
Table 12-6. Truth Table for SDRAM Commands....................................................................................................................1410
Table 12-7. 16-bit EMIF Address Pin Connections................................................................................................................ 1412
Table 12-8. Description of the SDRAM Configuration Register (SDRAM_CR)......................................................................1413
Table 12-9. Description of the SDRAM Refresh Control Register (SDRAM_RCR)............................................................... 1413
Table 12-10. Description of the SDRAM Timing Register (SDRAM_TR)...............................................................................1413
Table 12-11. Description of the SDRAM Self Refresh Exit Timing Register (SDR_EXT_TMNG)..........................................1414
Table 12-12. SDRAM LOAD MODE REGISTER Command................................................................................................. 1414
Table 12-13. Refresh Urgency Levels....................................................................................................................................1416
Table 12-14. Mapping from Logical Address to EMIF Pins for 32-bit SDRAM.......................................................................1421
Table 12-15. Mapping from Logical Address to EMIF Pins for 16-bit SDRAM.......................................................................1421
Table 12-16. Normal Mode vs. Select Strobe Mode.............................................................................................................. 1422
Table 12-17. Description of the Asynchronous m Configuration Register (ASYNC_CSn_CR)............................................. 1424
Table 12-18. Description of the Asynchronous Wait Cycle Configuration Register (ASYNC_WCCR).................................. 1425
Table 12-19. Description of EMIF Interrupt Mask Set Register (INT_MSK_SET)..................................................................1425
Table 12-20. Description of EMIF Interrupt Mast Clear Register (INT_MSK_CLR)............................................................... 1426
Table 12-21. Asynchronous Read Operation in Normal Mode.............................................................................................. 1426
Table 12-22. Asynchronous Write Operation in Normal Mode...............................................................................................1428
Table 12-23. Asynchronous Read Operation in Select Strobe Mode.................................................................................... 1430
Table 12-24. Asynchronous Write Operation in Select Strobe Mode.....................................................................................1432
Table 12-25. Interrupt Monitor and Control Bit Fields............................................................................................................ 1435
Table 12-26. SR Field Value For EMIF to K4S641632H-TC(L)70 Interface...........................................................................1438
Table 12-27. SDRAM_TR Field Calculations for EMIF to K4S641632H-TC(L)70 Interface.................................................. 1440
Table 12-28. RR Calculation for EMIF to K4S641632H-TC(L)70 Interface........................................................................... 1441
Table 12-29. RR Calculation for EMIF to K4S641632H-TC(L)70 Interface........................................................................... 1441
Table 12-30. SDRAM_CR Field Values For EMIF to K4S641632H-TC(L)70 Interface..........................................................1442
Table 12-31. AC Characteristics for a Read Access..............................................................................................................1443
Table 12-32. AC Characteristics for a Write Access.............................................................................................................. 1443
Table 12-33. EMIF Base Address Table (C28)...................................................................................................................... 1450
Table 12-34. EMIF_REGS Registers..................................................................................................................................... 1451
Table 12-35. EMIF_REGS Access Type Codes.................................................................................................................... 1451
Table 12-36. RCSR Register Field Descriptions....................................................................................................................1453
Table 12-37. ASYNC_WCCR Register Field Descriptions.................................................................................................... 1454
Table 12-38. SDRAM_CR Register Field Descriptions..........................................................................................................1455
Table 12-39. SDRAM_RCR Register Field Descriptions....................................................................................................... 1457
Table 12-40. ASYNC_CS2_CR Register Field Descriptions................................................................................................. 1458
Table 12-41. ASYNC_CS3_CR Register Field Descriptions................................................................................................. 1460
Table 12-42. ASYNC_CS4_CR Register Field Descriptions................................................................................................. 1462
Table 12-43. SDRAM_TR Register Field Descriptions.......................................................................................................... 1464
Table 12-44. TOTAL_SDRAM_AR Register Field Descriptions.............................................................................................1465
Table 12-45. TOTAL_SDRAM_ACTR Register Field Descriptions........................................................................................ 1466
Table 12-46. SDR_EXT_TMNG Register Field Descriptions.................................................................................................1467
Table 12-47. INT_RAW Register Field Descriptions.............................................................................................................. 1468
Table 12-48. INT_MSK Register Field Descriptions.............................................................................................................. 1469
Table 12-49. INT_MSK_SET Register Field Descriptions..................................................................................................... 1470
Table 12-50. INT_MSK_CLR Register Field Descriptions..................................................................................................... 1471
Table 12-51. EMIF1_CONFIG_REGS Registers................................................................................................................... 1472

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Table 12-52. EMIF1_CONFIG_REGS Access Type Codes.................................................................................................. 1472

Table 12-53. EMIF1LOCK Register Field Descriptions..........................................................................................................1473
Table 12-54. EMIF1COMMIT Register Field Descriptions.....................................................................................................1474
Table 12-55. EMIF1MSEL Register Field Descriptions..........................................................................................................1475
Table 12-56. EMIF1ACCPROT0 Register Field Descriptions................................................................................................1476
Table 12-57. EMIF2_CONFIG_REGS Registers................................................................................................................... 1477
Table 12-58. EMIF2_CONFIG_REGS Access Type Codes.................................................................................................. 1477
Table 12-59. EMIF2LOCK Register Field Descriptions..........................................................................................................1478
Table 12-60. EMIF2COMMIT Register Field Descriptions.....................................................................................................1479
Table 12-61. EMIF2ACCPROT0 Register Field Descriptions................................................................................................1480
Table 12-62. EMIF Registers to Driverlib Functions.............................................................................................................. 1480
Table 13-1. FLASH Base Address Table (C28)..................................................................................................................... 1504
Table 13-2. CM FLASH Base Address Table (CM)................................................................................................................1504
Table 13-3. FLASH_CTRL_REGS Registers.........................................................................................................................1505
Table 13-4. FLASH_CTRL_REGS Access Type Codes........................................................................................................ 1505
Table 13-5. FRDCNTL Register Field Descriptions............................................................................................................... 1506
Table 13-6. FBAC Register Field Descriptions...................................................................................................................... 1507
Table 13-7. FBFALLBACK Register Field Descriptions......................................................................................................... 1508
Table 13-8. FBPRDY Register Field Descriptions................................................................................................................. 1509
Table 13-9. FPAC1 Register Field Descriptions.....................................................................................................................1510
Table 13-10. FMSTAT Register Field Descriptions................................................................................................................ 1511
Table 13-11. FRD_INTF_CTRL Register Field Descriptions..................................................................................................1513
Table 13-12. FLASH_ECC_REGS Registers........................................................................................................................ 1514
Table 13-13. FLASH_ECC_REGS Access Type Codes........................................................................................................1514
Table 13-14. ECC_ENABLE Register Field Descriptions...................................................................................................... 1516
Table 13-15. SINGLE_ERR_ADDR_LOW Register Field Descriptions.................................................................................1517
Table 13-16. SINGLE_ERR_ADDR_HIGH Register Field Descriptions................................................................................ 1518
Table 13-17. UNC_ERR_ADDR_LOW Register Field Descriptions...................................................................................... 1519
Table 13-18. UNC_ERR_ADDR_HIGH Register Field Descriptions..................................................................................... 1520
Table 13-19. ERR_STATUS Register Field Descriptions.......................................................................................................1521
Table 13-20. ERR_POS Register Field Descriptions.............................................................................................................1523
Table 13-21. ERR_STATUS_CLR Register Field Descriptions..............................................................................................1524
Table 13-22. ERR_CNT Register Field Descriptions............................................................................................................. 1525
Table 13-23. ERR_THRESHOLD Register Field Descriptions.............................................................................................. 1526
Table 13-24. ERR_INTFLG Register Field Descriptions........................................................................................................1527
Table 13-25. ERR_INTCLR Register Field Descriptions....................................................................................................... 1528
Table 13-26. FDATAH_TEST Register Field Descriptions..................................................................................................... 1529
Table 13-27. FDATAL_TEST Register Field Descriptions......................................................................................................1530
Table 13-28. FADDR_TEST Register Field Descriptions.......................................................................................................1531
Table 13-29. FECC_TEST Register Field Descriptions......................................................................................................... 1532
Table 13-30. FECC_CTRL Register Field Descriptions.........................................................................................................1533
Table 13-31. FOUTH_TEST Register Field Descriptions...................................................................................................... 1534
Table 13-32. FOUTL_TEST Register Field Descriptions....................................................................................................... 1535
Table 13-33. FECC_STATUS Register Field Descriptions.....................................................................................................1536
Table 13-34. CM_FLASH_CTRL_REGS Registers............................................................................................................... 1537
Table 13-35. CM_FLASH_CTRL_REGS Access Type Codes.............................................................................................. 1537
Table 13-36. FRDCNTL Register Field Descriptions............................................................................................................. 1538
Table 13-37. FBAC Register Field Descriptions.................................................................................................................... 1539
Table 13-38. FBFALLBACK Register Field Descriptions....................................................................................................... 1540
Table 13-39. FBPRDY Register Field Descriptions............................................................................................................... 1541
Table 13-40. FPAC1 Register Field Descriptions...................................................................................................................1542
Table 13-41. FMSTAT Register Field Descriptions................................................................................................................ 1543
Table 13-42. FRD_INTF_CTRL_LOCK Register Field Descriptions..................................................................................... 1545
Table 13-43. FRD_INTF_CTRL Register Field Descriptions................................................................................................. 1546
Table 13-44. CM_FLASH_ECC_REGS Registers.................................................................................................................1547
Table 13-45. CM_FLASH_ECC_REGS Access Type Codes................................................................................................ 1547
Table 13-46. ECC_ENABLE Register Field Descriptions...................................................................................................... 1549
Table 13-47. SINGLE_ERR_ADDR_LOW Register Field Descriptions.................................................................................1550
Table 13-48. SINGLE_ERR_ADDR_HIGH Register Field Descriptions................................................................................ 1551
Table 13-49. UNC_ERR_ADDR_LOW Register Field Descriptions...................................................................................... 1552
Table 13-50. UNC_ERR_ADDR_HIGH Register Field Descriptions..................................................................................... 1553

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Table 13-51. ERR_STATUS Register Field Descriptions.......................................................................................................1554

Table 13-52. ERR_POS Register Field Descriptions.............................................................................................................1556
Table 13-53. ERR_STATUS_CLR Register Field Descriptions..............................................................................................1557
Table 13-54. ERR_CNT Register Field Descriptions............................................................................................................. 1558
Table 13-55. ERR_THRESHOLD Register Field Descriptions.............................................................................................. 1559
Table 13-56. ERR_INTFLG Register Field Descriptions........................................................................................................1560
Table 13-57. ERR_INTCLR Register Field Descriptions....................................................................................................... 1561
Table 13-58. FDATAH_TEST Register Field Descriptions..................................................................................................... 1562
Table 13-59. FDATAL_TEST Register Field Descriptions......................................................................................................1563
Table 13-60. FADDR_TEST Register Field Descriptions.......................................................................................................1564
Table 13-61. FECC_TEST Register Field Descriptions......................................................................................................... 1565
Table 13-62. FECC_CTRL Register Field Descriptions.........................................................................................................1566
Table 13-63. FOUTH_TEST Register Field Descriptions...................................................................................................... 1567
Table 13-64. FOUTL_TEST Register Field Descriptions....................................................................................................... 1568
Table 13-65. FECC_STATUS Register Field Descriptions.....................................................................................................1569
Table 13-66. FLASH_ECC_REGS_LOCK Register Field Descriptions.................................................................................1570
Table 13-67. FLASH_PUMP_SEMAPHORE_REGS Registers.............................................................................................1571
Table 13-68. FLASH_PUMP_SEMAPHORE_REGS Access Type Codes............................................................................ 1571
Table 13-69. PUMPREQUEST Register Field Descriptions.................................................................................................. 1572
Table 13-70. FLASH Registers to Driverlib Functions........................................................................................................... 1572
Table 14-1. Event Selector Mux Signals................................................................................................................................ 1581
Table 14-2. CPU Interfaces Monitored by CRC Units............................................................................................................1587
Table 14-3. Trace Memory Entry Bit Fields............................................................................................................................1591
Table 14-4. ERAD Base Address Table (C28)....................................................................................................................... 1601
Table 14-5. ERAD_GLOBAL_REGS Registers..................................................................................................................... 1603
Table 14-6. ERAD_GLOBAL_REGS Access Type Codes.....................................................................................................1603
Table 14-7. GLBL_EVENT_STAT Register Field Descriptions.............................................................................................. 1604
Table 14-8. GLBL_HALT_STAT Register Field Descriptions................................................................................................. 1606
Table 14-9. GLBL_ENABLE Register Field Descriptions.......................................................................................................1608
Table 14-10. GLBL_CTM_RESET Register Field Descriptions............................................................................................. 1610
Table 14-11. GLBL_NMI_CTL Register Field Descriptions.................................................................................................... 1611
Table 14-12. GLBL_OWNER Register Field Descriptions..................................................................................................... 1613
Table 14-13. GLBL_EVENT_AND_MASK Register Field Descriptions................................................................................. 1614
Table 14-14. GLBL_EVENT_OR_MASK Register Field Descriptions................................................................................... 1618
Table 14-15. GLBL_AND_EVENT_INT_MASK Register Field Descriptions......................................................................... 1622
Table 14-16. GLBL_OR_EVENT_INT_MASK Register Field Descriptions........................................................................... 1623
Table 14-17. ERAD_HWBP_REGS Registers.......................................................................................................................1624
Table 14-18. ERAD_HWBP_REGS Access Type Codes...................................................................................................... 1624
Table 14-19. HWBP_MASK Register Field Descriptions....................................................................................................... 1625
Table 14-20. HWBP_REF Register Field Descriptions.......................................................................................................... 1626
Table 14-21. HWBP_CLEAR Register Field Descriptions..................................................................................................... 1627
Table 14-22. HWBP_CNTL Register Field Descriptions........................................................................................................1628
Table 14-23. HWBP_STATUS Register Field Descriptions....................................................................................................1630
Table 14-24. ERAD_COUNTER_REGS Registers................................................................................................................1631
Table 14-25. ERAD_COUNTER_REGS Access Type Codes............................................................................................... 1631
Table 14-26. CTM_CNTL Register Field Descriptions...........................................................................................................1632
Table 14-27. CTM_STATUS Register Field Descriptions.......................................................................................................1634
Table 14-28. CTM_REF Register Field Descriptions............................................................................................................. 1635
Table 14-29. CTM_COUNT Register Field Descriptions....................................................................................................... 1636
Table 14-30. CTM_MAX_COUNT Register Field Descriptions..............................................................................................1637
Table 14-31. CTM_INPUT_SEL Register Field Descriptions.................................................................................................1638
Table 14-32. CTM_CLEAR Register Field Descriptions........................................................................................................ 1639
Table 14-33. CTM_INPUT_SEL_2 Register Field Descriptions.............................................................................................1640
Table 14-34. CTM_INPUT_COND Register Field Descriptions.............................................................................................1641
Table 14-35. ERAD_CRC_GLOBAL_REGS Registers......................................................................................................... 1642
Table 14-36. ERAD_CRC_GLOBAL_REGS Access Type Codes.........................................................................................1642
Table 14-37. CRC_GLOBAL_CTRL Register Field Descriptions.......................................................................................... 1643
Table 14-38. ERAD_CRC_REGS Registers..........................................................................................................................1645
Table 14-39. ERAD_CRC_REGS Access Type Codes......................................................................................................... 1645
Table 14-40. CRC_CURRENT Register Field Descriptions...................................................................................................1646
Table 14-41. CRC_SEED Register Field Descriptions.......................................................................................................... 1647

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Table 14-42. CRC_QUALIFIER Register Field Descriptions................................................................................................. 1648

Table 14-43. ERAD Registers to Driverlib Functions............................................................................................................. 1648
Table 15-1. GPIO access by different controllers...................................................................................................................1653
Table 15-2. Sampling Period..................................................................................................................................................1658
Table 15-3. Sampling Frequency........................................................................................................................................... 1658
Table 15-4. Case 1: Three-Sample Sampling Window Width................................................................................................1659
Table 15-5. Case 2: Six-Sample Sampling Window Width.................................................................................................... 1659
Table 15-6. USB I/O Signal Muxing....................................................................................................................................... 1661
Table 15-7. GPIO Configuration for High-Speed SPI.............................................................................................................1661
Table 15-8. GPIO Muxed Pins............................................................................................................................................... 1662
Table 15-9. GPIO and Peripheral Muxing.............................................................................................................................. 1669
Table 15-10. Peripheral Muxing (Multiple Pins Assigned)..................................................................................................... 1670
Table 15-11. GPIO Base Address Table (C28)...................................................................................................................... 1672
Table 15-12. CM GPIO Base Address Table (CM)................................................................................................................ 1672
Table 15-13. GPIO_CTRL_REGS Registers......................................................................................................................... 1674
Table 15-14. GPIO_CTRL_REGS Access Type Codes.........................................................................................................1676
Table 15-15. GPACTRL Register Field Descriptions............................................................................................................. 1678
Table 15-16. GPAQSEL1 Register Field Descriptions........................................................................................................... 1679
Table 15-17. GPAQSEL2 Register Field Descriptions........................................................................................................... 1680
Table 15-18. GPAMUX1 Register Field Descriptions.............................................................................................................1681
Table 15-19. GPAMUX2 Register Field Descriptions.............................................................................................................1682
Table 15-20. GPADIR Register Field Descriptions.................................................................................................................1683
Table 15-21. GPAPUD Register Field Descriptions............................................................................................................... 1685
Table 15-22. GPAINV Register Field Descriptions.................................................................................................................1687
Table 15-23. GPAODR Register Field Descriptions...............................................................................................................1689
Table 15-24. GPAGMUX1 Register Field Descriptions.......................................................................................................... 1691
Table 15-25. GPAGMUX2 Register Field Descriptions.......................................................................................................... 1692
Table 15-26. GPACSEL1 Register Field Descriptions........................................................................................................... 1693
Table 15-27. GPACSEL2 Register Field Descriptions........................................................................................................... 1694
Table 15-28. GPACSEL3 Register Field Descriptions........................................................................................................... 1695
Table 15-29. GPACSEL4 Register Field Descriptions........................................................................................................... 1696
Table 15-30. GPALOCK Register Field Descriptions............................................................................................................. 1697
Table 15-31. GPACR Register Field Descriptions..................................................................................................................1699
Table 15-32. GPBCTRL Register Field Descriptions............................................................................................................. 1701
Table 15-33. GPBQSEL1 Register Field Descriptions...........................................................................................................1702
Table 15-34. GPBQSEL2 Register Field Descriptions...........................................................................................................1703
Table 15-35. GPBMUX1 Register Field Descriptions............................................................................................................ 1704
Table 15-36. GPBMUX2 Register Field Descriptions............................................................................................................ 1705
Table 15-37. GPBDIR Register Field Descriptions................................................................................................................ 1706
Table 15-38. GPBPUD Register Field Descriptions...............................................................................................................1708
Table 15-39. GPBINV Register Field Descriptions................................................................................................................ 1710
Table 15-40. GPBODR Register Field Descriptions.............................................................................................................. 1712
Table 15-41. GPBAMSEL Register Field Descriptions.......................................................................................................... 1714
Table 15-42. GPBGMUX1 Register Field Descriptions..........................................................................................................1716
Table 15-43. GPBGMUX2 Register Field Descriptions..........................................................................................................1717
Table 15-44. GPBCSEL1 Register Field Descriptions........................................................................................................... 1718
Table 15-45. GPBCSEL2 Register Field Descriptions........................................................................................................... 1719
Table 15-46. GPBCSEL3 Register Field Descriptions........................................................................................................... 1720
Table 15-47. GPBCSEL4 Register Field Descriptions........................................................................................................... 1721
Table 15-48. GPBLOCK Register Field Descriptions.............................................................................................................1722
Table 15-49. GPBCR Register Field Descriptions................................................................................................................. 1724
Table 15-50. GPCCTRL Register Field Descriptions.............................................................................................................1726
Table 15-51. GPCQSEL1 Register Field Descriptions...........................................................................................................1727
Table 15-52. GPCQSEL2 Register Field Descriptions...........................................................................................................1728
Table 15-53. GPCMUX1 Register Field Descriptions............................................................................................................ 1729
Table 15-54. GPCMUX2 Register Field Descriptions............................................................................................................ 1730
Table 15-55. GPCDIR Register Field Descriptions................................................................................................................ 1731
Table 15-56. GPCPUD Register Field Descriptions...............................................................................................................1733
Table 15-57. GPCINV Register Field Descriptions................................................................................................................ 1735
Table 15-58. GPCODR Register Field Descriptions.............................................................................................................. 1737
Table 15-59. GPCGMUX1 Register Field Descriptions......................................................................................................... 1739

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Table 15-60. GPCGMUX2 Register Field Descriptions......................................................................................................... 1740

Table 15-61. GPCCSEL1 Register Field Descriptions...........................................................................................................1741
Table 15-62. GPCCSEL2 Register Field Descriptions...........................................................................................................1742
Table 15-63. GPCCSEL3 Register Field Descriptions...........................................................................................................1743
Table 15-64. GPCCSEL4 Register Field Descriptions...........................................................................................................1744
Table 15-65. GPCLOCK Register Field Descriptions............................................................................................................ 1745
Table 15-66. GPCCR Register Field Descriptions................................................................................................................. 1747
Table 15-67. GPDCTRL Register Field Descriptions.............................................................................................................1749
Table 15-68. GPDQSEL1 Register Field Descriptions...........................................................................................................1750
Table 15-69. GPDQSEL2 Register Field Descriptions...........................................................................................................1752
Table 15-70. GPDMUX1 Register Field Descriptions............................................................................................................ 1754
Table 15-71. GPDMUX2 Register Field Descriptions............................................................................................................ 1756
Table 15-72. GPDDIR Register Field Descriptions................................................................................................................ 1758
Table 15-73. GPDPUD Register Field Descriptions...............................................................................................................1760
Table 15-74. GPDINV Register Field Descriptions................................................................................................................ 1762
Table 15-75. GPDODR Register Field Descriptions.............................................................................................................. 1764
Table 15-76. GPDGMUX1 Register Field Descriptions......................................................................................................... 1766
Table 15-77. GPDGMUX2 Register Field Descriptions......................................................................................................... 1768
Table 15-78. GPDCSEL1 Register Field Descriptions...........................................................................................................1770
Table 15-79. GPDCSEL2 Register Field Descriptions...........................................................................................................1771
Table 15-80. GPDCSEL3 Register Field Descriptions...........................................................................................................1772
Table 15-81. GPDCSEL4 Register Field Descriptions...........................................................................................................1773
Table 15-82. GPDLOCK Register Field Descriptions............................................................................................................ 1774
Table 15-83. GPDCR Register Field Descriptions................................................................................................................. 1776
Table 15-84. GPECTRL Register Field Descriptions............................................................................................................. 1778
Table 15-85. GPEQSEL1 Register Field Descriptions...........................................................................................................1779
Table 15-86. GPEQSEL2 Register Field Descriptions...........................................................................................................1781
Table 15-87. GPEMUX1 Register Field Descriptions............................................................................................................ 1783
Table 15-88. GPEMUX2 Register Field Descriptions............................................................................................................ 1785
Table 15-89. GPEDIR Register Field Descriptions................................................................................................................ 1787
Table 15-90. GPEPUD Register Field Descriptions...............................................................................................................1789
Table 15-91. GPEINV Register Field Descriptions................................................................................................................ 1791
Table 15-92. GPEODR Register Field Descriptions.............................................................................................................. 1793
Table 15-93. GPEGMUX1 Register Field Descriptions..........................................................................................................1795
Table 15-94. GPEGMUX2 Register Field Descriptions..........................................................................................................1797
Table 15-95. GPECSEL1 Register Field Descriptions........................................................................................................... 1799
Table 15-96. GPECSEL2 Register Field Descriptions........................................................................................................... 1800
Table 15-97. GPECSEL3 Register Field Descriptions........................................................................................................... 1801
Table 15-98. GPECSEL4 Register Field Descriptions........................................................................................................... 1802
Table 15-99. GPELOCK Register Field Descriptions.............................................................................................................1803
Table 15-100. GPECR Register Field Descriptions............................................................................................................... 1805
Table 15-101. GPFCTRL Register Field Descriptions........................................................................................................... 1807
Table 15-102. GPFQSEL1 Register Field Descriptions......................................................................................................... 1808
Table 15-103. GPFMUX1 Register Field Descriptions...........................................................................................................1810
Table 15-104. GPFDIR Register Field Descriptions.............................................................................................................. 1812
Table 15-105. GPFPUD Register Field Descriptions............................................................................................................. 1814
Table 15-106. GPFINV Register Field Descriptions...............................................................................................................1816
Table 15-107. GPFODR Register Field Descriptions.............................................................................................................1818
Table 15-108. GPFGMUX1 Register Field Descriptions........................................................................................................1820
Table 15-109. GPFCSEL1 Register Field Descriptions......................................................................................................... 1821
Table 15-110. GPFCSEL2 Register Field Descriptions..........................................................................................................1822
Table 15-111. GPFLOCK Register Field Descriptions........................................................................................................... 1823
Table 15-112. GPFCR Register Field Descriptions................................................................................................................1825
Table 15-113. GPIO_DATA_REGS Registers........................................................................................................................1827
Table 15-114. GPIO_DATA_REGS Access Type Codes....................................................................................................... 1827
Table 15-115. GPADAT Register Field Descriptions.............................................................................................................. 1829
Table 15-116. GPASET Register Field Descriptions.............................................................................................................. 1831
Table 15-117. GPACLEAR Register Field Descriptions......................................................................................................... 1833
Table 15-118. GPATOGGLE Register Field Descriptions...................................................................................................... 1835
Table 15-119. GPBDAT Register Field Descriptions..............................................................................................................1837
Table 15-120. GPBSET Register Field Descriptions............................................................................................................. 1839

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Table 15-121. GPBCLEAR Register Field Descriptions........................................................................................................ 1841

Table 15-122. GPBTOGGLE Register Field Descriptions......................................................................................................1843
Table 15-123. GPCDAT Register Field Descriptions............................................................................................................. 1845
Table 15-124. GPCSET Register Field Descriptions............................................................................................................. 1847
Table 15-125. GPCCLEAR Register Field Descriptions........................................................................................................ 1849
Table 15-126. GPCTOGGLE Register Field Descriptions..................................................................................................... 1851
Table 15-127. GPDDAT Register Field Descriptions............................................................................................................. 1853
Table 15-128. GPDSET Register Field Descriptions............................................................................................................. 1855
Table 15-129. GPDCLEAR Register Field Descriptions........................................................................................................ 1857
Table 15-130. GPDTOGGLE Register Field Descriptions..................................................................................................... 1859
Table 15-131. GPEDAT Register Field Descriptions..............................................................................................................1861
Table 15-132. GPESET Register Field Descriptions............................................................................................................. 1863
Table 15-133. GPECLEAR Register Field Descriptions........................................................................................................ 1865
Table 15-134. GPETOGGLE Register Field Descriptions......................................................................................................1867
Table 15-135. GPFDAT Register Field Descriptions..............................................................................................................1869
Table 15-136. GPFSET Register Field Descriptions..............................................................................................................1871
Table 15-137. GPFCLEAR Register Field Descriptions.........................................................................................................1873
Table 15-138. GPFTOGGLE Register Field Descriptions......................................................................................................1875
Table 15-139. GPIO_DATA_READ_REGS Registers............................................................................................................1877
Table 15-140. GPIO_DATA_READ_REGS Access Type Codes........................................................................................... 1877
Table 15-141. GPADAT_R Register Field Descriptions......................................................................................................... 1878
Table 15-142. GPBDAT_R Register Field Descriptions......................................................................................................... 1879
Table 15-143. GPCDAT_R Register Field Descriptions.........................................................................................................1880
Table 15-144. GPDDAT_R Register Field Descriptions.........................................................................................................1881
Table 15-145. GPEDAT_R Register Field Descriptions......................................................................................................... 1882
Table 15-146. GPFDAT_R Register Field Descriptions......................................................................................................... 1883
Table 15-147. CM_GPIO_DATA_REGS Registers................................................................................................................ 1884
Table 15-148. CM_GPIO_DATA_REGS Access Type Codes............................................................................................... 1884
Table 15-149. GPADAT Register Field Descriptions..............................................................................................................1886
Table 15-150. GPASET Register Field Descriptions..............................................................................................................1888
Table 15-151. GPACLEAR Register Field Descriptions.........................................................................................................1890
Table 15-152. GPATOGGLE Register Field Descriptions...................................................................................................... 1892
Table 15-153. GPBDAT Register Field Descriptions..............................................................................................................1894
Table 15-154. GPBSET Register Field Descriptions............................................................................................................. 1896
Table 15-155. GPBCLEAR Register Field Descriptions........................................................................................................ 1898
Table 15-156. GPBTOGGLE Register Field Descriptions......................................................................................................1900
Table 15-157. GPCDAT Register Field Descriptions............................................................................................................. 1902
Table 15-158. GPCSET Register Field Descriptions............................................................................................................. 1904
Table 15-159. GPCCLEAR Register Field Descriptions........................................................................................................ 1906
Table 15-160. GPCTOGGLE Register Field Descriptions..................................................................................................... 1908
Table 15-161. GPDDAT Register Field Descriptions............................................................................................................. 1910
Table 15-162. GPDSET Register Field Descriptions............................................................................................................. 1912
Table 15-163. GPDCLEAR Register Field Descriptions........................................................................................................ 1914
Table 15-164. GPDTOGGLE Register Field Descriptions..................................................................................................... 1916
Table 15-165. GPEDAT Register Field Descriptions..............................................................................................................1918
Table 15-166. GPESET Register Field Descriptions............................................................................................................. 1920
Table 15-167. GPECLEAR Register Field Descriptions........................................................................................................ 1922
Table 15-168. GPETOGGLE Register Field Descriptions......................................................................................................1924
Table 15-169. GPFDAT Register Field Descriptions..............................................................................................................1926
Table 15-170. GPFSET Register Field Descriptions..............................................................................................................1928
Table 15-171. GPFCLEAR Register Field Descriptions.........................................................................................................1930
Table 15-172. GPFTOGGLE Register Field Descriptions......................................................................................................1932
Table 15-173. CM_GPIO_DATA_READ_REGS Registers.................................................................................................... 1934
Table 15-174. CM_GPIO_DATA_READ_REGS Access Type Codes................................................................................... 1934
Table 15-175. GPADAT_R Register Field Descriptions......................................................................................................... 1935
Table 15-176. GPBDAT_R Register Field Descriptions......................................................................................................... 1936
Table 15-177. GPCDAT_R Register Field Descriptions.........................................................................................................1937
Table 15-178. GPDDAT_R Register Field Descriptions.........................................................................................................1938
Table 15-179. GPEDAT_R Register Field Descriptions......................................................................................................... 1939
Table 15-180. GPFDAT_R Register Field Descriptions......................................................................................................... 1940
Table 15-181. GPGDAT_R Register Field Descriptions.........................................................................................................1941

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Table 15-182. GPHDAT_R Register Field Descriptions.........................................................................................................1942

Table 15-183. GPIO Registers to Driverlib Functions............................................................................................................ 1942
Table 16-1. CPU1-CM IPC Message RAM Read / Write Access...........................................................................................1950
Table 16-2. CPU2-CM IPC Message RAM Read / Write Access...........................................................................................1950
Table 16-3. CPU1-CPU2 IPC Message RAM Read / Write Access.......................................................................................1950
Table 16-4. IPC Command Registers.................................................................................................................................... 1953
Table 16-5. IPC Base Address Table (C28)........................................................................................................................... 1958
Table 16-6. CM IPC Base Address Table (CM)..................................................................................................................... 1958
Table 16-7. CPU1TOCPU2_IPC_REGS_CPU1VIEW Registers...........................................................................................1959
Table 16-8. CPU1TOCPU2_IPC_REGS_CPU1VIEW Access Type Codes.......................................................................... 1959
Table 16-9. CPU1TOCPU2IPCACK Register Field Descriptions...........................................................................................1961
Table 16-10. CPU2TOCPU1IPCSTS Register Field Descriptions......................................................................................... 1963
Table 16-11. CPU1TOCPU2IPCSET Register Field Descriptions......................................................................................... 1968
Table 16-12. CPU1TOCPU2IPCCLR Register Field Descriptions.........................................................................................1972
Table 16-13. CPU1TOCPU2IPCFLG Register Field Descriptions......................................................................................... 1976
Table 16-14. IPCCOUNTERL Register Field Descriptions.................................................................................................... 1980
Table 16-15. IPCCOUNTERH Register Field Descriptions....................................................................................................1981
Table 16-16. CPU1TOCPU2IPCSENDCOM Register Field Descriptions..............................................................................1982
Table 16-17. CPU1TOCPU2IPCSENDADDR Register Field Descriptions............................................................................1983
Table 16-18. CPU1TOCPU2IPCSENDDATA Register Field Descriptions.............................................................................1984
Table 16-19. CPU2TOCPU1IPCREPLY Register Field Descriptions.................................................................................... 1985
Table 16-20. CPU2TOCPU1IPCRECVCOM Register Field Descriptions..............................................................................1986
Table 16-21. CPU2TOCPU1IPCRECVADDR Register Field Descriptions............................................................................ 1987
Table 16-22. CPU2TOCPU1IPCRECVDATA Register Field Descriptions.............................................................................1988
Table 16-23. CPU1TOCPU2IPCREPLY Register Field Descriptions.................................................................................... 1989
Table 16-24. CPU2TOCPU1IPCBOOTSTS Register Field Descriptions...............................................................................1990
Table 16-25. CPU1TOCPU2IPCBOOTMODE Register Field Descriptions........................................................................... 1991
Table 16-26. PUMPREQUEST Register Field Descriptions.................................................................................................. 1992
Table 16-27. CPU1TOCPU2_IPC_REGS_CPU2VIEW Registers.........................................................................................1993
Table 16-28. CPU1TOCPU2_IPC_REGS_CPU2VIEW Access Type Codes........................................................................ 1993
Table 16-29. CPU2TOCPU1IPCACK Register Field Descriptions.........................................................................................1995
Table 16-30. CPU1TOCPU2IPCSTS Register Field Descriptions......................................................................................... 1997
Table 16-31. CPU2TOCPU1IPCSET Register Field Descriptions......................................................................................... 2002
Table 16-32. CPU2TOCPU1IPCCLR Register Field Descriptions.........................................................................................2006
Table 16-33. CPU2TOCPU1IPCFLG Register Field Descriptions......................................................................................... 2010
Table 16-34. IPCCOUNTERL Register Field Descriptions.................................................................................................... 2014
Table 16-35. IPCCOUNTERH Register Field Descriptions....................................................................................................2015
Table 16-36. CPU1TOCPU2IPCRECVCOM Register Field Descriptions..............................................................................2016
Table 16-37. CPU1TOCPU2IPCRECVADDR Register Field Descriptions............................................................................ 2017
Table 16-38. CPU1TOCPU2IPCRECVDATA Register Field Descriptions.............................................................................2018
Table 16-39. CPU2TOCPU1IPCREPLY Register Field Descriptions.................................................................................... 2019
Table 16-40. CPU2TOCPU1IPCSENDCOM Register Field Descriptions..............................................................................2020
Table 16-41. CPU2TOCPU1IPCSENDADDR Register Field Descriptions............................................................................2021
Table 16-42. CPU2TOCPU1IPCSENDDATA Register Field Descriptions.............................................................................2022
Table 16-43. CPU1TOCPU2IPCREPLY Register Field Descriptions.................................................................................... 2023
Table 16-44. CPU2TOCPU1IPCBOOTSTS Register Field Descriptions...............................................................................2024
Table 16-45. CPU1TOCPU2IPCBOOTMODE Register Field Descriptions........................................................................... 2025
Table 16-46. PUMPREQUEST Register Field Descriptions.................................................................................................. 2026
Table 16-47. CPU1TOCM_IPC_REGS_CPU1VIEW Registers.............................................................................................2027
Table 16-48. CPU1TOCM_IPC_REGS_CPU1VIEW Access Type Codes............................................................................ 2027
Table 16-49. CPU1TOCMIPCACK Register Field Descriptions.............................................................................................2029
Table 16-50. CMTOCPU1IPCSTS Register Field Descriptions............................................................................................. 2031
Table 16-51. CPU1TOCMIPCSET Register Field Descriptions............................................................................................. 2036
Table 16-52. CPU1TOCMIPCCLR Register Field Descriptions.............................................................................................2040
Table 16-53. CPU1TOCMIPCFLG Register Field Descriptions............................................................................................. 2044
Table 16-54. IPCCOUNTERL Register Field Descriptions.................................................................................................... 2048
Table 16-55. IPCCOUNTERH Register Field Descriptions....................................................................................................2049
Table 16-56. CPU1TOCMIPCSENDCOM Register Field Descriptions..................................................................................2050
Table 16-57. CPU1TOCMIPCSENDADDR Register Field Descriptions................................................................................2051
Table 16-58. CPU1TOCMIPCSENDDATA Register Field Descriptions.................................................................................2052
Table 16-59. CMTOCPU1IPCREPLY Register Field Descriptions........................................................................................ 2053

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Table 16-60. CMTOCPU1IPCRECVCOM Register Field Descriptions..................................................................................2054

Table 16-61. CMTOCPU1IPCRECVADDR Register Field Descriptions................................................................................ 2055
Table 16-62. CMTOCPU1IPCRECVDATA Register Field Descriptions.................................................................................2056
Table 16-63. CPU1TOCMIPCREPLY Register Field Descriptions........................................................................................ 2057
Table 16-64. CMTOCPU1IPCBOOTSTS Register Field Descriptions...................................................................................2058
Table 16-65. CPU1TOCMIPCBOOTMODE Register Field Descriptions............................................................................... 2059
Table 16-66. CPU1TOCM_IPC_REGS_CMVIEW Registers.................................................................................................2060
Table 16-67. CPU1TOCM_IPC_REGS_CMVIEW Access Type Codes................................................................................ 2060
Table 16-68. CMTOCPU1IPCACK Register Field Descriptions.............................................................................................2062
Table 16-69. CPU1TOCMIPCSTS Register Field Descriptions............................................................................................. 2064
Table 16-70. CMTOCPU1IPCSET Register Field Descriptions............................................................................................. 2069
Table 16-71. CMTOCPU1IPCCLR Register Field Descriptions.............................................................................................2073
Table 16-72. CMTOCPU1IPCFLG Register Field Descriptions............................................................................................. 2077
Table 16-73. IPCCOUNTERL Register Field Descriptions.................................................................................................... 2081
Table 16-74. IPCCOUNTERH Register Field Descriptions....................................................................................................2082
Table 16-75. CPU1TOCMIPCRECVCOM Register Field Descriptions..................................................................................2083
Table 16-76. CPU1TOCMIPCRECVADDR Register Field Descriptions................................................................................ 2084
Table 16-77. CPU1TOCMIPCRECVDATA Register Field Descriptions.................................................................................2085
Table 16-78. CMTOCPU1IPCREPLY Register Field Descriptions........................................................................................ 2086
Table 16-79. CMTOCPU1IPCSENDCOM Register Field Descriptions..................................................................................2087
Table 16-80. CMTOCPU1IPCSENDADDR Register Field Descriptions................................................................................2088
Table 16-81. CMTOCPU1IPCSENDDATA Register Field Descriptions.................................................................................2089
Table 16-82. CPU1TOCMIPCREPLY Register Field Descriptions........................................................................................ 2090
Table 16-83. CMTOCPU1IPCBOOTSTS Register Field Descriptions...................................................................................2091
Table 16-84. CPU1TOCMIPCBOOTMODE Register Field Descriptions............................................................................... 2092
Table 16-85. PUMPREQUEST Register Field Descriptions.................................................................................................. 2093
Table 16-86. CPU2TOCM_IPC_REGS_CPU2VIEW Registers.............................................................................................2094
Table 16-87. CPU2TOCM_IPC_REGS_CPU2VIEW Access Type Codes............................................................................ 2094
Table 16-88. CPU2TOCMIPCACK Register Field Descriptions.............................................................................................2096
Table 16-89. CMTOCPU2IPCSTS Register Field Descriptions............................................................................................. 2098
Table 16-90. CPU2TOCMIPCSET Register Field Descriptions............................................................................................. 2103
Table 16-91. CPU2TOCMIPCCLR Register Field Descriptions.............................................................................................2107
Table 16-92. CPU2TOCMIPCFLG Register Field Descriptions............................................................................................. 2111
Table 16-93. IPCCOUNTERL Register Field Descriptions.....................................................................................................2115
Table 16-94. IPCCOUNTERH Register Field Descriptions.................................................................................................... 2116
Table 16-95. CPU2TOCMIPCSENDCOM Register Field Descriptions..................................................................................2117
Table 16-96. CPU2TOCMIPCSENDADDR Register Field Descriptions................................................................................ 2118
Table 16-97. CPU2TOCMIPCSENDDATA Register Field Descriptions................................................................................. 2119
Table 16-98. CMTOCPU2IPCREPLY Register Field Descriptions........................................................................................ 2120
Table 16-99. CMTOCPU2IPCRECVCOM Register Field Descriptions..................................................................................2121
Table 16-100. CMTOCPU2IPCRECVADDR Register Field Descriptions.............................................................................. 2122
Table 16-101. CMTOCPU2IPCRECVDATA Register Field Descriptions...............................................................................2123
Table 16-102. CPU2TOCMIPCREPLY Register Field Descriptions...................................................................................... 2124
Table 16-103. CPU2TOCM_IPC_REGS_CMVIEW Registers...............................................................................................2125
Table 16-104. CPU2TOCM_IPC_REGS_CMVIEW Access Type Codes.............................................................................. 2125
Table 16-105. CMTOCPU2IPCACK Register Field Descriptions...........................................................................................2127
Table 16-106. CPU2TOCMIPCSTS Register Field Descriptions........................................................................................... 2129
Table 16-107. CMTOCPU2IPCSET Register Field Descriptions........................................................................................... 2134
Table 16-108. CMTOCPU2IPCCLR Register Field Descriptions...........................................................................................2138
Table 16-109. CMTOCPU2IPCFLG Register Field Descriptions........................................................................................... 2142
Table 16-110. IPCCOUNTERL Register Field Descriptions...................................................................................................2146
Table 16-111. IPCCOUNTERH Register Field Descriptions.................................................................................................. 2147
Table 16-112. CPU2TOCMIPCRECVCOM Register Field Descriptions................................................................................2148
Table 16-113. CPU2TOCMIPCRECVADDR Register Field Descriptions.............................................................................. 2149
Table 16-114. CPU2TOCMIPCRECVDATA Register Field Descriptions............................................................................... 2150
Table 16-115. CMTOCPU2IPCREPLY Register Field Descriptions.......................................................................................2151
Table 16-116. CMTOCPU2IPCSENDCOM Register Field Descriptions................................................................................2152
Table 16-117. CMTOCPU2IPCSENDADDR Register Field Descriptions.............................................................................. 2153
Table 16-118. CMTOCPU2IPCSENDDATA Register Field Descriptions............................................................................... 2154
Table 16-119. CPU2TOCMIPCREPLY Register Field Descriptions.......................................................................................2155
Table 16-120. IPC Registers to Driverlib Functions............................................................................................................... 2155

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Table 17-1. Input X-BAR Destinations................................................................................................................................... 2164

Table 17-2. CLB Input X-BAR Destinations........................................................................................................................... 2165
Table 17-3. EPWM X-BAR Mux Configuration Table............................................................................................................. 2167
Table 17-4. CLB X-BAR Mux Configuration Table................................................................................................................. 2170
Table 17-5. Output X-BAR Mux Configuration Table............................................................................................................. 2172
Table 17-6. CLB Output X-BAR Mux Configuration Table..................................................................................................... 2173
Table 17-7. XBAR Base Address Table (C28)....................................................................................................................... 2176
Table 17-8. INPUT_XBAR_REGS Registers......................................................................................................................... 2177
Table 17-9. INPUT_XBAR_REGS Access Type Codes........................................................................................................ 2177
Table 17-10. INPUT1SELECT Register Field Descriptions................................................................................................... 2179
Table 17-11. INPUT2SELECT Register Field Descriptions....................................................................................................2180
Table 17-12. INPUT3SELECT Register Field Descriptions................................................................................................... 2181
Table 17-13. INPUT4SELECT Register Field Descriptions................................................................................................... 2182
Table 17-14. INPUT5SELECT Register Field Descriptions................................................................................................... 2183
Table 17-15. INPUT6SELECT Register Field Descriptions................................................................................................... 2184
Table 17-16. INPUT7SELECT Register Field Descriptions................................................................................................... 2185
Table 17-17. INPUT8SELECT Register Field Descriptions................................................................................................... 2186
Table 17-18. INPUT9SELECT Register Field Descriptions................................................................................................... 2187
Table 17-19. INPUT10SELECT Register Field Descriptions................................................................................................. 2188
Table 17-20. INPUT11SELECT Register Field Descriptions..................................................................................................2189
Table 17-21. INPUT12SELECT Register Field Descriptions................................................................................................. 2190
Table 17-22. INPUT13SELECT Register Field Descriptions................................................................................................. 2191
Table 17-23. INPUT14SELECT Register Field Descriptions................................................................................................. 2192
Table 17-24. INPUT15SELECT Register Field Descriptions................................................................................................. 2193
Table 17-25. INPUT16SELECT Register Field Descriptions................................................................................................. 2194
Table 17-26. INPUTSELECTLOCK Register Field Descriptions........................................................................................... 2195
Table 17-27. XBAR_REGS Registers....................................................................................................................................2197
Table 17-28. XBAR_REGS Access Type Codes................................................................................................................... 2197
Table 17-29. XBARFLG1 Register Field Descriptions........................................................................................................... 2198
Table 17-30. XBARFLG2 Register Field Descriptions........................................................................................................... 2203
Table 17-31. XBARFLG3 Register Field Descriptions........................................................................................................... 2208
Table 17-32. XBARFLG4 Register Field Descriptions........................................................................................................... 2213
Table 17-33. XBARCLR1 Register Field Descriptions........................................................................................................... 2218
Table 17-34. XBARCLR2 Register Field Descriptions........................................................................................................... 2221
Table 17-35. XBARCLR3 Register Field Descriptions........................................................................................................... 2224
Table 17-36. XBARCLR4 Register Field Descriptions........................................................................................................... 2227
Table 17-37. EPWM_XBAR_REGS Registers.......................................................................................................................2230
Table 17-38. EPWM_XBAR_REGS Access Type Codes...................................................................................................... 2230
Table 17-39. TRIP4MUX0TO15CFG Register Field Descriptions......................................................................................... 2232
Table 17-40. TRIP4MUX16TO31CFG Register Field Descriptions....................................................................................... 2235
Table 17-41. TRIP5MUX0TO15CFG Register Field Descriptions......................................................................................... 2238
Table 17-42. TRIP5MUX16TO31CFG Register Field Descriptions....................................................................................... 2241
Table 17-43. TRIP7MUX0TO15CFG Register Field Descriptions......................................................................................... 2244
Table 17-44. TRIP7MUX16TO31CFG Register Field Descriptions....................................................................................... 2247
Table 17-45. TRIP8MUX0TO15CFG Register Field Descriptions......................................................................................... 2250
Table 17-46. TRIP8MUX16TO31CFG Register Field Descriptions....................................................................................... 2253
Table 17-47. TRIP9MUX0TO15CFG Register Field Descriptions......................................................................................... 2256
Table 17-48. TRIP9MUX16TO31CFG Register Field Descriptions....................................................................................... 2259
Table 17-49. TRIP10MUX0TO15CFG Register Field Descriptions....................................................................................... 2262
Table 17-50. TRIP10MUX16TO31CFG Register Field Descriptions..................................................................................... 2265
Table 17-51. TRIP11MUX0TO15CFG Register Field Descriptions........................................................................................2268
Table 17-52. TRIP11MUX16TO31CFG Register Field Descriptions......................................................................................2271
Table 17-53. TRIP12MUX0TO15CFG Register Field Descriptions....................................................................................... 2274
Table 17-54. TRIP12MUX16TO31CFG Register Field Descriptions..................................................................................... 2277
Table 17-55. TRIP4MUXENABLE Register Field Descriptions..............................................................................................2280
Table 17-56. TRIP5MUXENABLE Register Field Descriptions..............................................................................................2285
Table 17-57. TRIP7MUXENABLE Register Field Descriptions..............................................................................................2290
Table 17-58. TRIP8MUXENABLE Register Field Descriptions..............................................................................................2295
Table 17-59. TRIP9MUXENABLE Register Field Descriptions..............................................................................................2300
Table 17-60. TRIP10MUXENABLE Register Field Descriptions............................................................................................2305
Table 17-61. TRIP11MUXENABLE Register Field Descriptions............................................................................................ 2310

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Table 17-62. TRIP12MUXENABLE Register Field Descriptions............................................................................................2315

Table 17-63. TRIPOUTINV Register Field Descriptions........................................................................................................ 2320
Table 17-64. TRIPLOCK Register Field Descriptions............................................................................................................ 2322
Table 17-65. CLB_XBAR_REGS Registers...........................................................................................................................2323
Table 17-66. CLB_XBAR_REGS Access Type Codes.......................................................................................................... 2323
Table 17-67. AUXSIG0MUX0TO15CFG Register Field Descriptions.................................................................................... 2325
Table 17-68. AUXSIG0MUX16TO31CFG Register Field Descriptions.................................................................................. 2328
Table 17-69. AUXSIG1MUX0TO15CFG Register Field Descriptions.................................................................................... 2331
Table 17-70. AUXSIG1MUX16TO31CFG Register Field Descriptions.................................................................................. 2334
Table 17-71. AUXSIG2MUX0TO15CFG Register Field Descriptions.................................................................................... 2337
Table 17-72. AUXSIG2MUX16TO31CFG Register Field Descriptions.................................................................................. 2340
Table 17-73. AUXSIG3MUX0TO15CFG Register Field Descriptions.................................................................................... 2343
Table 17-74. AUXSIG3MUX16TO31CFG Register Field Descriptions.................................................................................. 2346
Table 17-75. AUXSIG4MUX0TO15CFG Register Field Descriptions.................................................................................... 2349
Table 17-76. AUXSIG4MUX16TO31CFG Register Field Descriptions.................................................................................. 2352
Table 17-77. AUXSIG5MUX0TO15CFG Register Field Descriptions.................................................................................... 2355
Table 17-78. AUXSIG5MUX16TO31CFG Register Field Descriptions.................................................................................. 2358
Table 17-79. AUXSIG6MUX0TO15CFG Register Field Descriptions.................................................................................... 2361
Table 17-80. AUXSIG6MUX16TO31CFG Register Field Descriptions.................................................................................. 2364
Table 17-81. AUXSIG7MUX0TO15CFG Register Field Descriptions.................................................................................... 2367
Table 17-82. AUXSIG7MUX16TO31CFG Register Field Descriptions.................................................................................. 2370
Table 17-83. AUXSIG0MUXENABLE Register Field Descriptions........................................................................................ 2373
Table 17-84. AUXSIG1MUXENABLE Register Field Descriptions........................................................................................ 2378
Table 17-85. AUXSIG2MUXENABLE Register Field Descriptions........................................................................................ 2383
Table 17-86. AUXSIG3MUXENABLE Register Field Descriptions........................................................................................ 2388
Table 17-87. AUXSIG4MUXENABLE Register Field Descriptions........................................................................................ 2393
Table 17-88. AUXSIG5MUXENABLE Register Field Descriptions........................................................................................ 2398
Table 17-89. AUXSIG6MUXENABLE Register Field Descriptions........................................................................................ 2403
Table 17-90. AUXSIG7MUXENABLE Register Field Descriptions........................................................................................ 2408
Table 17-91. AUXSIGOUTINV Register Field Descriptions...................................................................................................2413
Table 17-92. AUXSIGLOCK Register Field Descriptions.......................................................................................................2415
Table 17-93. OUTPUT_XBAR_REGS Registers................................................................................................................... 2416
Table 17-94. OUTPUT_XBAR_REGS Access Type Codes.................................................................................................. 2416
Table 17-95. OUTPUT1MUX0TO15CFG Register Field Descriptions...................................................................................2418
Table 17-96. OUTPUT1MUX16TO31CFG Register Field Descriptions.................................................................................2421
Table 17-97. OUTPUT2MUX0TO15CFG Register Field Descriptions...................................................................................2424
Table 17-98. OUTPUT2MUX16TO31CFG Register Field Descriptions.................................................................................2427
Table 17-99. OUTPUT3MUX0TO15CFG Register Field Descriptions...................................................................................2430
Table 17-100. OUTPUT3MUX16TO31CFG Register Field Descriptions...............................................................................2433
Table 17-101. OUTPUT4MUX0TO15CFG Register Field Descriptions.................................................................................2436
Table 17-102. OUTPUT4MUX16TO31CFG Register Field Descriptions...............................................................................2439
Table 17-103. OUTPUT5MUX0TO15CFG Register Field Descriptions.................................................................................2442
Table 17-104. OUTPUT5MUX16TO31CFG Register Field Descriptions...............................................................................2445
Table 17-105. OUTPUT6MUX0TO15CFG Register Field Descriptions.................................................................................2448
Table 17-106. OUTPUT6MUX16TO31CFG Register Field Descriptions...............................................................................2451
Table 17-107. OUTPUT7MUX0TO15CFG Register Field Descriptions.................................................................................2454
Table 17-108. OUTPUT7MUX16TO31CFG Register Field Descriptions...............................................................................2457
Table 17-109. OUTPUT8MUX0TO15CFG Register Field Descriptions.................................................................................2460
Table 17-110. OUTPUT8MUX16TO31CFG Register Field Descriptions............................................................................... 2463
Table 17-111. OUTPUT1MUXENABLE Register Field Descriptions......................................................................................2466
Table 17-112. OUTPUT2MUXENABLE Register Field Descriptions..................................................................................... 2471
Table 17-113. OUTPUT3MUXENABLE Register Field Descriptions..................................................................................... 2476
Table 17-114. OUTPUT4MUXENABLE Register Field Descriptions..................................................................................... 2481
Table 17-115. OUTPUT5MUXENABLE Register Field Descriptions..................................................................................... 2486
Table 17-116. OUTPUT6MUXENABLE Register Field Descriptions..................................................................................... 2491
Table 17-117. OUTPUT7MUXENABLE Register Field Descriptions..................................................................................... 2496
Table 17-118. OUTPUT8MUXENABLE Register Field Descriptions..................................................................................... 2501
Table 17-119. OUTPUTLATCH Register Field Descriptions.................................................................................................. 2506
Table 17-120. OUTPUTLATCHCLR Register Field Descriptions...........................................................................................2508
Table 17-121. OUTPUTLATCHFRC Register Field Descriptions.......................................................................................... 2510
Table 17-122. OUTPUTLATCHENABLE Register Field Descriptions....................................................................................2512

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Table 17-123. OUTPUTINV Register Field Descriptions....................................................................................................... 2514

Table 17-124. OUTPUTLOCK Register Field Descriptions................................................................................................... 2516
Table 17-125. INPUTXBAR Registers to Driverlib Functions................................................................................................ 2517
Table 17-126. XBAR Registers to Driverlib Functions........................................................................................................... 2517
Table 17-127. EPWMXBAR Registers to Driverlib Functions................................................................................................ 2518
Table 17-128. CLBXBAR Registers to Driverlib Functions.................................................................................................... 2519
Table 17-129. OUTPUTXBAR Registers to Driverlib Functions............................................................................................ 2520
Table 19-1. Analog Signal Descriptions................................................................................................................................. 2529
Table 19-2. Reference Summary........................................................................................................................................... 2529
Table 19-3. ASBSYS Base Address Table (C28)...................................................................................................................2530
Table 19-4. ANALOG_SUBSYS_REGS Registers................................................................................................................ 2531
Table 19-5. ANALOG_SUBSYS_REGS Access Type Codes............................................................................................... 2531
Table 19-6. INTOSC1TRIM Register Field Descriptions........................................................................................................2532
Table 19-7. INTOSC2TRIM Register Field Descriptions........................................................................................................2533
Table 19-8. TSNSCTL Register Field Descriptions................................................................................................................2534
Table 19-9. LOCK Register Field Descriptions...................................................................................................................... 2535
Table 19-10. ANAREFTRIMA Register Field Descriptions.................................................................................................... 2536
Table 19-11. ANAREFTRIMB Register Field Descriptions.....................................................................................................2537
Table 19-12. ANAREFTRIMC Register Field Descriptions.................................................................................................... 2538
Table 19-13. ANAREFTRIMD Register Field Descriptions.................................................................................................... 2539
Table 20-1. ADC Options and Configuration Levels.............................................................................................................. 2545
Table 20-2. Analog to 12-bit Digital Formulas........................................................................................................................2547
Table 20-3. Analog to 16-bit Digital Formulas........................................................................................................................2547
Table 20-4. 12-Bit Digital-to-Analog Formulas....................................................................................................................... 2548
Table 20-5. 16-Bit Digital-to-Analog Formulas....................................................................................................................... 2548
Table 20-6. Channel Selection of Input Pins..........................................................................................................................2552
Table 20-7. Example Requirements for Multiple Signal Sampling......................................................................................... 2554
Table 20-8. Example Connections for Multiple Signal Sampling........................................................................................... 2554
Table 20-9. DETECTCFG Settings........................................................................................................................................ 2567
Table 20-10. ADC Timing Parameter Descriptions................................................................................................................ 2571
Table 20-11. ADC Timings in 12-bit Mode............................................................................................................................. 2576
Table 20-12. ADC Timings in 16-bit Mode............................................................................................................................. 2576
Table 20-13. ADC Base Address Table (C28)....................................................................................................................... 2593
Table 20-14. ADC_REGS Registers...................................................................................................................................... 2594
Table 20-15. ADC_REGS Access Type Codes..................................................................................................................... 2595
Table 20-16. ADCCTL1 Register Field Descriptions..............................................................................................................2597
Table 20-17. ADCCTL2 Register Field Descriptions..............................................................................................................2599
Table 20-18. ADCBURSTCTL Register Field Descriptions................................................................................................... 2600
Table 20-19. ADCINTFLG Register Field Descriptions..........................................................................................................2602
Table 20-20. ADCINTFLGCLR Register Field Descriptions.................................................................................................. 2604
Table 20-21. ADCINTOVF Register Field Descriptions......................................................................................................... 2605
Table 20-22. ADCINTOVFCLR Register Field Descriptions.................................................................................................. 2606
Table 20-23. ADCINTSEL1N2 Register Field Descriptions................................................................................................... 2607
Table 20-24. ADCINTSEL3N4 Register Field Descriptions................................................................................................... 2609
Table 20-25. ADCSOCPRICTL Register Field Descriptions.................................................................................................. 2611
Table 20-26. ADCINTSOCSEL1 Register Field Descriptions................................................................................................ 2613
Table 20-27. ADCINTSOCSEL2 Register Field Descriptions................................................................................................ 2615
Table 20-28. ADCSOCFLG1 Register Field Descriptions......................................................................................................2617
Table 20-29. ADCSOCFRC1 Register Field Descriptions..................................................................................................... 2621
Table 20-30. ADCSOCOVF1 Register Field Descriptions..................................................................................................... 2626
Table 20-31. ADCSOCOVFCLR1 Register Field Descriptions.............................................................................................. 2629
Table 20-32. ADCSOC0CTL Register Field Descriptions......................................................................................................2632
Table 20-33. ADCSOC1CTL Register Field Descriptions......................................................................................................2635
Table 20-34. ADCSOC2CTL Register Field Descriptions......................................................................................................2638
Table 20-35. ADCSOC3CTL Register Field Descriptions......................................................................................................2641
Table 20-36. ADCSOC4CTL Register Field Descriptions......................................................................................................2644
Table 20-37. ADCSOC5CTL Register Field Descriptions......................................................................................................2647
Table 20-38. ADCSOC6CTL Register Field Descriptions......................................................................................................2650
Table 20-39. ADCSOC7CTL Register Field Descriptions......................................................................................................2653
Table 20-40. ADCSOC8CTL Register Field Descriptions......................................................................................................2656
Table 20-41. ADCSOC9CTL Register Field Descriptions......................................................................................................2659

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Table 20-42. ADCSOC10CTL Register Field Descriptions....................................................................................................2662

Table 20-43. ADCSOC11CTL Register Field Descriptions.................................................................................................... 2665
Table 20-44. ADCSOC12CTL Register Field Descriptions....................................................................................................2668
Table 20-45. ADCSOC13CTL Register Field Descriptions....................................................................................................2671
Table 20-46. ADCSOC14CTL Register Field Descriptions....................................................................................................2674
Table 20-47. ADCSOC15CTL Register Field Descriptions....................................................................................................2677
Table 20-48. ADCEVTSTAT Register Field Descriptions.......................................................................................................2680
Table 20-49. ADCEVTCLR Register Field Descriptions........................................................................................................ 2683
Table 20-50. ADCEVTSEL Register Field Descriptions.........................................................................................................2685
Table 20-51. ADCEVTINTSEL Register Field Descriptions...................................................................................................2687
Table 20-52. ADCOSDETECT Register Field Descriptions...................................................................................................2689
Table 20-53. ADCCOUNTER Register Field Descriptions.....................................................................................................2690
Table 20-54. ADCREV Register Field Descriptions............................................................................................................... 2691
Table 20-55. ADCOFFTRIM Register Field Descriptions...................................................................................................... 2692
Table 20-56. ADCPPB1CONFIG Register Field Descriptions............................................................................................... 2693
Table 20-57. ADCPPB1STAMP Register Field Descriptions................................................................................................. 2695
Table 20-58. ADCPPB1OFFCAL Register Field Descriptions............................................................................................... 2696
Table 20-59. ADCPPB1OFFREF Register Field Descriptions...............................................................................................2697
Table 20-60. ADCPPB1TRIPHI Register Field Descriptions................................................................................................. 2698
Table 20-61. ADCPPB1TRIPLO Register Field Descriptions................................................................................................ 2699
Table 20-62. ADCPPB2CONFIG Register Field Descriptions............................................................................................... 2700
Table 20-63. ADCPPB2STAMP Register Field Descriptions................................................................................................. 2702
Table 20-64. ADCPPB2OFFCAL Register Field Descriptions............................................................................................... 2703
Table 20-65. ADCPPB2OFFREF Register Field Descriptions...............................................................................................2704
Table 20-66. ADCPPB2TRIPHI Register Field Descriptions................................................................................................. 2705
Table 20-67. ADCPPB2TRIPLO Register Field Descriptions................................................................................................ 2706
Table 20-68. ADCPPB3CONFIG Register Field Descriptions............................................................................................... 2707
Table 20-69. ADCPPB3STAMP Register Field Descriptions................................................................................................. 2709
Table 20-70. ADCPPB3OFFCAL Register Field Descriptions............................................................................................... 2710
Table 20-71. ADCPPB3OFFREF Register Field Descriptions............................................................................................... 2711
Table 20-72. ADCPPB3TRIPHI Register Field Descriptions................................................................................................. 2712
Table 20-73. ADCPPB3TRIPLO Register Field Descriptions................................................................................................ 2713
Table 20-74. ADCPPB4CONFIG Register Field Descriptions............................................................................................... 2714
Table 20-75. ADCPPB4STAMP Register Field Descriptions................................................................................................. 2716
Table 20-76. ADCPPB4OFFCAL Register Field Descriptions............................................................................................... 2717
Table 20-77. ADCPPB4OFFREF Register Field Descriptions...............................................................................................2718
Table 20-78. ADCPPB4TRIPHI Register Field Descriptions................................................................................................. 2719
Table 20-79. ADCPPB4TRIPLO Register Field Descriptions................................................................................................ 2720
Table 20-80. ADCINTCYCLE Register Field Descriptions.....................................................................................................2721
Table 20-81. ADCINLTRIM1 Register Field Descriptions...................................................................................................... 2722
Table 20-82. ADCINLTRIM2 Register Field Descriptions...................................................................................................... 2723
Table 20-83. ADCINLTRIM3 Register Field Descriptions...................................................................................................... 2724
Table 20-84. ADCINLTRIM4 Register Field Descriptions...................................................................................................... 2725
Table 20-85. ADCINLTRIM5 Register Field Descriptions...................................................................................................... 2726
Table 20-86. ADCINLTRIM6 Register Field Descriptions...................................................................................................... 2727
Table 20-87. ADC_RESULT_REGS Registers...................................................................................................................... 2728
Table 20-88. ADC_RESULT_REGS Access Type Codes......................................................................................................2728
Table 20-89. ADCRESULT0 Register Field Descriptions.......................................................................................................2730
Table 20-90. ADCRESULT1 Register Field Descriptions.......................................................................................................2731
Table 20-91. ADCRESULT2 Register Field Descriptions.......................................................................................................2732
Table 20-92. ADCRESULT3 Register Field Descriptions.......................................................................................................2733
Table 20-93. ADCRESULT4 Register Field Descriptions.......................................................................................................2734
Table 20-94. ADCRESULT5 Register Field Descriptions.......................................................................................................2735
Table 20-95. ADCRESULT6 Register Field Descriptions.......................................................................................................2736
Table 20-96. ADCRESULT7 Register Field Descriptions.......................................................................................................2737
Table 20-97. ADCRESULT8 Register Field Descriptions.......................................................................................................2738
Table 20-98. ADCRESULT9 Register Field Descriptions.......................................................................................................2739
Table 20-99. ADCRESULT10 Register Field Descriptions.....................................................................................................2740
Table 20-100. ADCRESULT11 Register Field Descriptions...................................................................................................2741
Table 20-101. ADCRESULT12 Register Field Descriptions...................................................................................................2742
Table 20-102. ADCRESULT13 Register Field Descriptions...................................................................................................2743

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Table 20-103. ADCRESULT14 Register Field Descriptions...................................................................................................2744

Table 20-104. ADCRESULT15 Register Field Descriptions...................................................................................................2745
Table 20-105. ADCPPB1RESULT Register Field Descriptions............................................................................................. 2746
Table 20-106. ADCPPB2RESULT Register Field Descriptions............................................................................................. 2747
Table 20-107. ADCPPB3RESULT Register Field Descriptions............................................................................................. 2748
Table 20-108. ADCPPB4RESULT Register Field Descriptions............................................................................................. 2749
Table 20-109. ADC Registers to Driverlib Functions............................................................................................................. 2749
Table 21-1. DAC Base Address Table (C28)......................................................................................................................... 2760
Table 21-2. DAC_REGS Registers........................................................................................................................................ 2761
Table 21-3. DAC_REGS Access Type Codes....................................................................................................................... 2761
Table 21-4. DACREV Register Field Descriptions................................................................................................................. 2762
Table 21-5. DACCTL Register Field Descriptions..................................................................................................................2763
Table 21-6. DACVALA Register Field Descriptions................................................................................................................2764
Table 21-7. DACVALS Register Field Descriptions................................................................................................................2765
Table 21-8. DACOUTEN Register Field Descriptions............................................................................................................2766
Table 21-9. DACLOCK Register Field Descriptions...............................................................................................................2767
Table 21-10. DACTRIM Register Field Descriptions..............................................................................................................2768
Table 21-11. DAC Registers to Driverlib Functions................................................................................................................2768
Table 22-1. CMPSS Base Address Table (C28).................................................................................................................... 2780
Table 22-2. CMPSS_REGS Registers...................................................................................................................................2781
Table 22-3. CMPSS_REGS Access Type Codes.................................................................................................................. 2781
Table 22-4. COMPCTL Register Field Descriptions.............................................................................................................. 2783
Table 22-5. COMPHYSCTL Register Field Descriptions....................................................................................................... 2785
Table 22-6. COMPSTS Register Field Descriptions.............................................................................................................. 2786
Table 22-7. COMPSTSCLR Register Field Descriptions....................................................................................................... 2787
Table 22-8. COMPDACCTL Register Field Descriptions.......................................................................................................2788
Table 22-9. DACHVALS Register Field Descriptions............................................................................................................. 2790
Table 22-10. DACHVALA Register Field Descriptions........................................................................................................... 2791
Table 22-11. RAMPMAXREFA Register Field Descriptions...................................................................................................2792
Table 22-12. RAMPMAXREFS Register Field Descriptions.................................................................................................. 2793
Table 22-13. RAMPDECVALA Register Field Descriptions................................................................................................... 2794
Table 22-14. RAMPDECVALS Register Field Descriptions................................................................................................... 2795
Table 22-15. RAMPSTS Register Field Descriptions.............................................................................................................2796
Table 22-16. DACLVALS Register Field Descriptions............................................................................................................2797
Table 22-17. DACLVALA Register Field Descriptions............................................................................................................2798
Table 22-18. RAMPDLYA Register Field Descriptions...........................................................................................................2799
Table 22-19. RAMPDLYS Register Field Descriptions...........................................................................................................2800
Table 22-20. CTRIPLFILCTL Register Field Descriptions..................................................................................................... 2801
Table 22-21. CTRIPLFILCLKCTL Register Field Descriptions.............................................................................................. 2802
Table 22-22. CTRIPHFILCTL Register Field Descriptions.....................................................................................................2803
Table 22-23. CTRIPHFILCLKCTL Register Field Descriptions..............................................................................................2804
Table 22-24. COMPLOCK Register Field Descriptions......................................................................................................... 2805
Table 22-25. CMPSS Registers to Driverlib Functions.......................................................................................................... 2805
Table 24-1. eCAP Input Selection..........................................................................................................................................2813
Table 24-2. ECAP Base Address Table (C28)....................................................................................................................... 2836
Table 24-3. ECAP_REGS Registers......................................................................................................................................2837
Table 24-4. ECAP_REGS Access Type Codes..................................................................................................................... 2837
Table 24-5. TSCTR Register Field Descriptions.................................................................................................................... 2839
Table 24-6. CTRPHS Register Field Descriptions................................................................................................................. 2840
Table 24-7. CAP1 Register Field Descriptions.......................................................................................................................2841
Table 24-8. CAP2 Register Field Descriptions.......................................................................................................................2842
Table 24-9. CAP3 Register Field Descriptions.......................................................................................................................2843
Table 24-10. CAP4 Register Field Descriptions.....................................................................................................................2844
Table 24-11. ECCTL0 Register Field Descriptions.................................................................................................................2845
Table 24-12. ECCTL1 Register Field Descriptions................................................................................................................ 2846
Table 24-13. ECCTL2 Register Field Descriptions................................................................................................................ 2848
Table 24-14. ECEINT Register Field Descriptions.................................................................................................................2850
Table 24-15. ECFLG Register Field Descriptions.................................................................................................................. 2852
Table 24-16. ECCLR Register Field Descriptions..................................................................................................................2853
Table 24-17. ECFRC Register Field Descriptions..................................................................................................................2854
Table 24-18. ECAPSYNCINSEL Register Field Descriptions................................................................................................2855

102 TMS320F2838x Real-Time Microcontrollers With Connectivity Manager SPRUII0E – MAY 2019 – REVISED SEPTEMBER 2023
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Table 24-19. ECAP Registers to Driverlib Functions............................................................................................................. 2855

Table 25-1. Scale Factor........................................................................................................................................................2865
Table 25-2. HRCAP Base Address Table (C28).................................................................................................................... 2866
Table 25-3. HRCAP_REGS Registers................................................................................................................................... 2867
Table 25-4. HRCAP_REGS Access Type Codes.................................................................................................................. 2867
Table 25-5. HRCTL Register Field Descriptions.................................................................................................................... 2868
Table 25-6. HRINTEN Register Field Descriptions................................................................................................................ 2869
Table 25-7. HRFLG Register Field Descriptions....................................................................................................................2870
Table 25-8. HRCLR Register Field Descriptions....................................................................................................................2871
Table 25-9. HRFRC Register Field Descriptions................................................................................................................... 2872
Table 25-10. HRCALPRD Register Field Descriptions.......................................................................................................... 2873
Table 25-11. HRSYSCLKCTR Register Field Descriptions....................................................................................................2874
Table 25-12. HRSYSCLKCAP Register Field Descriptions................................................................................................... 2875
Table 25-13. HRCLKCTR Register Field Descriptions.......................................................................................................... 2876
Table 25-14. HRCLKCAP Register Field Descriptions.......................................................................................................... 2877
Table 25-15. HRCAP Registers to Driverlib Functions.......................................................................................................... 2877
Table 26-1. Submodule Configuration Parameters................................................................................................................2887
Table 26-2. Key Time-Base Signals.......................................................................................................................................2891
Table 26-3. ePWM SYNC Selection...................................................................................................................................... 2896
Table 26-4. Action-Qualifier Submodule Possible Input Events.............................................................................................2910
Table 26-5. Action-Qualifier Event Priority for Up-Down-Count Mode................................................................................... 2912
Table 26-6. Action-Qualifier Event Priority for Up-Count Mode............................................................................................. 2912
Table 26-7. Action-Qualifier Event Priority for Down-Count Mode.........................................................................................2912
Table 26-8. Behavior if CMPA/CMPB is Greater than the Period.......................................................................................... 2913
Table 26-9. Classical Dead-Band Operating Modes..............................................................................................................2926
Table 26-10. Additional Dead-Band Operating Modes.......................................................................................................... 2926
Table 26-11. Dead-Band Delay Values in μS as a Function of DBFED and DBRED.............................................................2928
Table 26-12. Possible Pulse Width Values for EPWMCLK = 80 MHz....................................................................................2931
Table 26-13. Possible Actions On a Trip Event......................................................................................................................2935
Table 26-14. Lock Bits and Corresponding Registers............................................................................................................2973
Table 26-15. Resolution for PWM and HRPWM.................................................................................................................... 2975
Table 26-16. Relationship Between MEP Steps, PWM Frequency, and Resolution..............................................................2981
Table 26-17. CMPA versus Duty (left), and [CMPA:CMPAHR] versus Duty (right)................................................................2982
Table 26-18. Duty Cycle Range Limitation for Three EPWMCLK/TBCLK Cycles................................................................. 2985
Table 26-19. SFO Library Features....................................................................................................................................... 2997
Table 26-20. Factor Values.................................................................................................................................................... 2998
Table 26-21. EPWM Base Address Table (C28)....................................................................................................................3007
Table 26-22. EPWM_REGS Registers.................................................................................................................................. 3008
Table 26-23. EPWM_REGS Access Type Codes..................................................................................................................3010
Table 26-24. TBCTL Register Field Descriptions................................................................................................................... 3011
Table 26-25. TBCTL2 Register Field Descriptions.................................................................................................................3013
Table 26-26. EPWMSYNCINSEL Register Field Descriptions.............................................................................................. 3014
Table 26-27. TBCTR Register Field Descriptions.................................................................................................................. 3015
Table 26-28. TBSTS Register Field Descriptions.................................................................................................................. 3016
Table 26-29. EPWMSYNCOUTEN Register Field Descriptions............................................................................................ 3017
Table 26-30. TBCTL3 Register Field Descriptions.................................................................................................................3019
Table 26-31. CMPCTL Register Field Descriptions............................................................................................................... 3020
Table 26-32. CMPCTL2 Register Field Descriptions............................................................................................................. 3022
Table 26-33. DBCTL Register Field Descriptions.................................................................................................................. 3024
Table 26-34. DBCTL2 Register Field Descriptions................................................................................................................ 3027
Table 26-35. AQCTL Register Field Descriptions.................................................................................................................. 3028
Table 26-36. AQTSRCSEL Register Field Descriptions........................................................................................................ 3030
Table 26-37. PCCTL Register Field Descriptions.................................................................................................................. 3031
Table 26-38. VCAPCTL Register Field Descriptions............................................................................................................. 3032
Table 26-39. VCNTCFG Register Field Descriptions.............................................................................................................3034
Table 26-40. HRCNFG Register Field Descriptions...............................................................................................................3036
Table 26-41. HRPWR Register Field Descriptions................................................................................................................ 3038
Table 26-42. HRMSTEP Register Field Descriptions............................................................................................................ 3039
Table 26-43. HRCNFG2 Register Field Descriptions.............................................................................................................3040
Table 26-44. HRPCTL Register Field Descriptions................................................................................................................3041
Table 26-45. TRREM Register Field Descriptions................................................................................................................. 3043

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Table 26-46. GLDCTL Register Field Descriptions................................................................................................................3044

Table 26-47. GLDCFG Register Field Descriptions............................................................................................................... 3046
Table 26-48. EPWMXLINK Register Field Descriptions........................................................................................................ 3048
Table 26-49. AQCTLA Register Field Descriptions................................................................................................................3050
Table 26-50. AQCTLA2 Register Field Descriptions..............................................................................................................3052
Table 26-51. AQCTLB Register Field Descriptions................................................................................................................3053
Table 26-52. AQCTLB2 Register Field Descriptions..............................................................................................................3055
Table 26-53. AQSFRC Register Field Descriptions............................................................................................................... 3056
Table 26-54. AQCSFRC Register Field Descriptions............................................................................................................ 3057
Table 26-55. DBREDHR Register Field Descriptions............................................................................................................ 3058
Table 26-56. DBRED Register Field Descriptions................................................................................................................. 3059
Table 26-57. DBFEDHR Register Field Descriptions.............................................................................................................3060
Table 26-58. DBFED Register Field Descriptions..................................................................................................................3061
Table 26-59. TBPHS Register Field Descriptions.................................................................................................................. 3062
Table 26-60. TBPRDHR Register Field Descriptions.............................................................................................................3063
Table 26-61. TBPRD Register Field Descriptions..................................................................................................................3064
Table 26-62. CMPA Register Field Descriptions.................................................................................................................... 3065
Table 26-63. CMPB Register Field Descriptions....................................................................................................................3066
Table 26-64. CMPC Register Field Descriptions................................................................................................................... 3067
Table 26-65. CMPD Register Field Descriptions................................................................................................................... 3068
Table 26-66. GLDCTL2 Register Field Descriptions..............................................................................................................3069
Table 26-67. SWVDELVAL Register Field Descriptions.........................................................................................................3070
Table 26-68. TZSEL Register Field Descriptions...................................................................................................................3071
Table 26-69. TZDCSEL Register Field Descriptions..............................................................................................................3073
Table 26-70. TZCTL Register Field Descriptions...................................................................................................................3074
Table 26-71. TZCTL2 Register Field Descriptions.................................................................................................................3075
Table 26-72. TZCTLDCA Register Field Descriptions........................................................................................................... 3077
Table 26-73. TZCTLDCB Register Field Descriptions........................................................................................................... 3079
Table 26-74. TZEINT Register Field Descriptions................................................................................................................. 3081
Table 26-75. TZFLG Register Field Descriptions...................................................................................................................3082
Table 26-76. TZCBCFLG Register Field Descriptions........................................................................................................... 3084
Table 26-77. TZOSTFLG Register Field Descriptions........................................................................................................... 3085
Table 26-78. TZCLR Register Field Descriptions.................................................................................................................. 3086
Table 26-79. TZCBCCLR Register Field Descriptions...........................................................................................................3087
Table 26-80. TZOSTCLR Register Field Descriptions........................................................................................................... 3088
Table 26-81. TZFRC Register Field Descriptions.................................................................................................................. 3089
Table 26-82. ETSEL Register Field Descriptions...................................................................................................................3090
Table 26-83. ETPS Register Field Descriptions.....................................................................................................................3093
Table 26-84. ETFLG Register Field Descriptions.................................................................................................................. 3096
Table 26-85. ETCLR Register Field Descriptions.................................................................................................................. 3097
Table 26-86. ETFRC Register Field Descriptions.................................................................................................................. 3098
Table 26-87. ETINTPS Register Field Descriptions...............................................................................................................3099
Table 26-88. ETSOCPS Register Field Descriptions.............................................................................................................3100
Table 26-89. ETCNTINITCTL Register Field Descriptions.................................................................................................... 3101
Table 26-90. ETCNTINIT Register Field Descriptions........................................................................................................... 3102
Table 26-91. DCTRIPSEL Register Field Descriptions..........................................................................................................3103
Table 26-92. DCACTL Register Field Descriptions................................................................................................................3105
Table 26-93. DCBCTL Register Field Descriptions................................................................................................................3107
Table 26-94. DCFCTL Register Field Descriptions................................................................................................................3109
Table 26-95. DCCAPCTL Register Field Descriptions........................................................................................................... 3111
Table 26-96. DCFOFFSET Register Field Descriptions.........................................................................................................3113
Table 26-97. DCFOFFSETCNT Register Field Descriptions................................................................................................. 3114
Table 26-98. DCFWINDOW Register Field Descriptions....................................................................................................... 3115
Table 26-99. DCFWINDOWCNT Register Field Descriptions................................................................................................3116
Table 26-100. DCCAP Register Field Descriptions................................................................................................................3117
Table 26-101. DCAHTRIPSEL Register Field Descriptions................................................................................................... 3118
Table 26-102. DCALTRIPSEL Register Field Descriptions....................................................................................................3120
Table 26-103. DCBHTRIPSEL Register Field Descriptions...................................................................................................3122
Table 26-104. DCBLTRIPSEL Register Field Descriptions....................................................................................................3124
Table 26-105. EPWMLOCK Register Field Descriptions....................................................................................................... 3126
Table 26-106. HWVDELVAL Register Field Descriptions...................................................................................................... 3127

104 TMS320F2838x Real-Time Microcontrollers With Connectivity Manager SPRUII0E – MAY 2019 – REVISED SEPTEMBER 2023
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Table 26-107. VCNTVAL Register Field Descriptions............................................................................................................3128

Table 26-108. SYNC_SOC_REGS Registers........................................................................................................................3129
Table 26-109. SYNC_SOC_REGS Access Type Codes....................................................................................................... 3129
Table 26-110. SYNCSELECT Register Field Descriptions.................................................................................................... 3130
Table 26-111. ADCSOCOUTSELECT Register Field Descriptions........................................................................................3132
Table 26-112. SYNCSOCLOCK Register Field Descriptions.................................................................................................3135
Table 26-113. EPWM Registers to Driverlib Functions.......................................................................................................... 3136
Table 26-114. HRPWM Registers to Driverlib Functions....................................................................................................... 3142
Table 27-1. eQEP Input Source Select Table........................................................................................................................ 3155
Table 27-2. EQEP Memory Map............................................................................................................................................ 3157
Table 27-3. Quadrature Decoder Truth Table........................................................................................................................ 3159
Table 27-4. EQEP Base Address Table (C28)....................................................................................................................... 3181
Table 27-5. EQEP_REGS Registers......................................................................................................................................3182
Table 27-6. EQEP_REGS Access Type Codes..................................................................................................................... 3182
Table 27-7. QPOSCNT Register Field Descriptions.............................................................................................................. 3184
Table 27-8. QPOSINIT Register Field Descriptions...............................................................................................................3185
Table 27-9. QPOSMAX Register Field Descriptions..............................................................................................................3186
Table 27-10. QPOSCMP Register Field Descriptions............................................................................................................3187
Table 27-11. QPOSILAT Register Field Descriptions.............................................................................................................3188
Table 27-12. QPOSSLAT Register Field Descriptions........................................................................................................... 3189
Table 27-13. QPOSLAT Register Field Descriptions............................................................................................................. 3190
Table 27-14. QUTMR Register Field Descriptions.................................................................................................................3191
Table 27-15. QUPRD Register Field Descriptions................................................................................................................. 3192
Table 27-16. QWDTMR Register Field Descriptions............................................................................................................. 3193
Table 27-17. QWDPRD Register Field Descriptions..............................................................................................................3194
Table 27-18. QDECCTL Register Field Descriptions.............................................................................................................3195
Table 27-19. QEPCTL Register Field Descriptions................................................................................................................3197
Table 27-20. QCAPCTL Register Field Descriptions............................................................................................................. 3199
Table 27-21. QPOSCTL Register Field Descriptions.............................................................................................................3200
Table 27-22. QEINT Register Field Descriptions................................................................................................................... 3201
Table 27-23. QFLG Register Field Descriptions.................................................................................................................... 3203
Table 27-24. QCLR Register Field Descriptions.................................................................................................................... 3205
Table 27-25. QFRC Register Field Descriptions....................................................................................................................3207
Table 27-26. QEPSTS Register Field Descriptions............................................................................................................... 3209
Table 27-27. QCTMR Register Field Descriptions.................................................................................................................3210
Table 27-28. QCPRD Register Field Descriptions................................................................................................................. 3211
Table 27-29. QCTMRLAT Register Field Descriptions...........................................................................................................3212
Table 27-30. QCPRDLAT Register Field Descriptions...........................................................................................................3213
Table 27-31. REV Register Field Descriptions.......................................................................................................................3214
Table 27-32. QEPSTROBESEL Register Field Descriptions.................................................................................................3215
Table 27-33. QMACTRL Register Field Descriptions............................................................................................................ 3216
Table 27-34. QEPSRCSEL Register Field Descriptions........................................................................................................ 3217
Table 27-35. EQEP Registers to Driverlib Functions............................................................................................................. 3218
Table 28-1. Modulator Clock Modes...................................................................................................................................... 3228
Table 28-2. Order of Sinc Filter..............................................................................................................................................3231
Table 28-3. Peak Data Values for Different DOSR/Filter Combinations................................................................................ 3232
Table 28-4. Shift Control Bit Configuration Settings...............................................................................................................3233
Table 28-5. SDSYNCx.SYNCSEL......................................................................................................................................... 3235
Table 28-6. Number of Incorrect Samples Tabulated.............................................................................................................3236
Table 28-7. Peak Data Values for Different OSR/Filter Combinations................................................................................... 3237
Table 28-8. SDFM Data-Ready Interrupt (SDy_DRINTx) Output Selection...........................................................................3245
Table 28-9. SDFM Base Address Table (C28).......................................................................................................................3250
Table 28-10. SDFM_REGS Registers................................................................................................................................... 3251
Table 28-11. SDFM_REGS Access Type Codes................................................................................................................... 3253
Table 28-12. SDIFLG Register Field Descriptions................................................................................................................. 3254
Table 28-13. SDIFLGCLR Register Field Descriptions..........................................................................................................3257
Table 28-14. SDCTL Register Field Descriptions.................................................................................................................. 3259
Table 28-15. SDMFILEN Register Field Descriptions............................................................................................................3260
Table 28-16. SDSTATUS Register Field Descriptions........................................................................................................... 3261
Table 28-17. SDCTLPARM1 Register Field Descriptions...................................................................................................... 3262
Table 28-18. SDDFPARM1 Register Field Descriptions........................................................................................................ 3263

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Table 28-19. SDDPARM1 Register Field Descriptions.......................................................................................................... 3264

Table 28-20. SDFLT1CMPH1 Register Field Descriptions.................................................................................................... 3265
Table 28-21. SDFLT1CMPL1 Register Field Descriptions..................................................................................................... 3266
Table 28-22. SDCPARM1 Register Field Descriptions.......................................................................................................... 3267
Table 28-23. SDDATA1 Register Field Descriptions.............................................................................................................. 3269
Table 28-24. SDDATFIFO1 Register Field Descriptions........................................................................................................ 3270
Table 28-25. SDCDATA1 Register Field Descriptions........................................................................................................... 3271
Table 28-26. SDFLT1CMPH2 Register Field Descriptions.................................................................................................... 3272
Table 28-27. SDFLT1CMPHZ Register Field Descriptions.................................................................................................... 3273
Table 28-28. SDFIFOCTL1 Register Field Descriptions........................................................................................................ 3274
Table 28-29. SDSYNC1 Register Field Descriptions............................................................................................................. 3275
Table 28-30. SDFLT1CMPL2 Register Field Descriptions..................................................................................................... 3276
Table 28-31. SDCTLPARM2 Register Field Descriptions...................................................................................................... 3277
Table 28-32. SDDFPARM2 Register Field Descriptions........................................................................................................ 3278
Table 28-33. SDDPARM2 Register Field Descriptions.......................................................................................................... 3279
Table 28-34. SDFLT2CMPH1 Register Field Descriptions.................................................................................................... 3280
Table 28-35. SDFLT2CMPL1 Register Field Descriptions..................................................................................................... 3281
Table 28-36. SDCPARM2 Register Field Descriptions.......................................................................................................... 3282
Table 28-37. SDDATA2 Register Field Descriptions.............................................................................................................. 3284
Table 28-38. SDDATFIFO2 Register Field Descriptions........................................................................................................ 3285
Table 28-39. SDCDATA2 Register Field Descriptions........................................................................................................... 3286
Table 28-40. SDFLT2CMPH2 Register Field Descriptions.................................................................................................... 3287
Table 28-41. SDFLT2CMPHZ Register Field Descriptions.................................................................................................... 3288
Table 28-42. SDFIFOCTL2 Register Field Descriptions........................................................................................................ 3289
Table 28-43. SDSYNC2 Register Field Descriptions............................................................................................................. 3290
Table 28-44. SDFLT2CMPL2 Register Field Descriptions..................................................................................................... 3291
Table 28-45. SDCTLPARM3 Register Field Descriptions...................................................................................................... 3292
Table 28-46. SDDFPARM3 Register Field Descriptions........................................................................................................ 3293
Table 28-47. SDDPARM3 Register Field Descriptions.......................................................................................................... 3294
Table 28-48. SDFLT3CMPH1 Register Field Descriptions.................................................................................................... 3295
Table 28-49. SDFLT3CMPL1 Register Field Descriptions..................................................................................................... 3296
Table 28-50. SDCPARM3 Register Field Descriptions.......................................................................................................... 3297
Table 28-51. SDDATA3 Register Field Descriptions.............................................................................................................. 3299
Table 28-52. SDDATFIFO3 Register Field Descriptions........................................................................................................ 3300
Table 28-53. SDCDATA3 Register Field Descriptions........................................................................................................... 3301
Table 28-54. SDFLT3CMPH2 Register Field Descriptions.................................................................................................... 3302
Table 28-55. SDFLT3CMPHZ Register Field Descriptions.................................................................................................... 3303
Table 28-56. SDFIFOCTL3 Register Field Descriptions........................................................................................................ 3304
Table 28-57. SDSYNC3 Register Field Descriptions............................................................................................................. 3305
Table 28-58. SDFLT3CMPL2 Register Field Descriptions..................................................................................................... 3306
Table 28-59. SDCTLPARM4 Register Field Descriptions...................................................................................................... 3307
Table 28-60. SDDFPARM4 Register Field Descriptions........................................................................................................ 3308
Table 28-61. SDDPARM4 Register Field Descriptions.......................................................................................................... 3309
Table 28-62. SDFLT4CMPH1 Register Field Descriptions.................................................................................................... 3310
Table 28-63. SDFLT4CMPL1 Register Field Descriptions..................................................................................................... 3311
Table 28-64. SDCPARM4 Register Field Descriptions.......................................................................................................... 3312
Table 28-65. SDDATA4 Register Field Descriptions.............................................................................................................. 3314
Table 28-66. SDDATFIFO4 Register Field Descriptions........................................................................................................ 3315
Table 28-67. SDCDATA4 Register Field Descriptions........................................................................................................... 3316
Table 28-68. SDFLT4CMPH2 Register Field Descriptions.................................................................................................... 3317
Table 28-69. SDFLT4CMPHZ Register Field Descriptions.................................................................................................... 3318
Table 28-70. SDFIFOCTL4 Register Field Descriptions........................................................................................................ 3319
Table 28-71. SDSYNC4 Register Field Descriptions............................................................................................................. 3320
Table 28-72. SDFLT4CMPL2 Register Field Descriptions..................................................................................................... 3321
Table 28-73. SDCOMP1CTL Register Field Descriptions..................................................................................................... 3322
Table 28-74. SDCOMP1EVT2FLTCTL Register Field Descriptions...................................................................................... 3323
Table 28-75. SDCOMP1EVT2FLTCLKCTL Register Field Descriptions............................................................................... 3324
Table 28-76. SDCOMP1EVT1FLTCTL Register Field Descriptions...................................................................................... 3325
Table 28-77. SDCOMP1EVT1FLTCLKCTL Register Field Descriptions............................................................................... 3326
Table 28-78. SDCOMP1LOCK Register Field Descriptions.................................................................................................. 3327
Table 28-79. SDCOMP2CTL Register Field Descriptions..................................................................................................... 3328

106 TMS320F2838x Real-Time Microcontrollers With Connectivity Manager SPRUII0E – MAY 2019 – REVISED SEPTEMBER 2023
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Table 28-80. SDCOMP2EVT2FLTCTL Register Field Descriptions...................................................................................... 3329

Table 28-81. SDCOMP2EVT2FLTCLKCTL Register Field Descriptions............................................................................... 3330
Table 28-82. SDCOMP2EVT1FLTCTL Register Field Descriptions...................................................................................... 3331
Table 28-83. SDCOMP2EVT1FLTCLKCTL Register Field Descriptions............................................................................... 3332
Table 28-84. SDCOMP2LOCK Register Field Descriptions.................................................................................................. 3333
Table 28-85. SDCOMP3CTL Register Field Descriptions..................................................................................................... 3334
Table 28-86. SDCOMP3EVT2FLTCTL Register Field Descriptions...................................................................................... 3335
Table 28-87. SDCOMP3EVT2FLTCLKCTL Register Field Descriptions............................................................................... 3336
Table 28-88. SDCOMP3EVT1FLTCTL Register Field Descriptions...................................................................................... 3337
Table 28-89. SDCOMP3EVT1FLTCLKCTL Register Field Descriptions............................................................................... 3338
Table 28-90. SDCOMP3LOCK Register Field Descriptions.................................................................................................. 3339
Table 28-91. SDCOMP4CTL Register Field Descriptions..................................................................................................... 3340
Table 28-92. SDCOMP4EVT2FLTCTL Register Field Descriptions...................................................................................... 3341
Table 28-93. SDCOMP4EVT2FLTCLKCTL Register Field Descriptions............................................................................... 3342
Table 28-94. SDCOMP4EVT1FLTCTL Register Field Descriptions...................................................................................... 3343
Table 28-95. SDCOMP4EVT1FLTCLKCTL Register Field Descriptions............................................................................... 3344
Table 28-96. SDCOMP4LOCK Register Field Descriptions.................................................................................................. 3345
Table 28-97. SDFM Registers to Driverlib Functions.............................................................................................................3345
Table 30-1. CAN Register Access from Software.................................................................................................................. 3358
Table 30-2. CAN Register Access from Code Composer Studio™ IDE................................................................................ 3359
Table 30-3. PIE Module Nomenclature for Interrupts.............................................................................................................3366
Table 30-4. Programmable Ranges Required by CAN Protocol............................................................................................3378
Table 30-5. Message Object Field Descriptions.................................................................................................................... 3388
Table 30-6. Message RAM Addressing in Debug Mode........................................................................................................ 3391
Table 30-7. CAN Base Address Table (C28)......................................................................................................................... 3398
Table 30-8. CM CAN Base Address Table (CM)....................................................................................................................3398
Table 30-9. CAN_REGS Registers........................................................................................................................................ 3399
Table 30-10. CAN_REGS Access Type Codes..................................................................................................................... 3400
Table 30-11. CAN_CTL Register Field Descriptions.............................................................................................................. 3401
Table 30-12. CAN_ES Register Field Descriptions................................................................................................................3404
Table 30-13. CAN_ERRC Register Field Descriptions.......................................................................................................... 3406
Table 30-14. CAN_BTR Register Field Descriptions............................................................................................................. 3407
Table 30-15. CAN_INT Register Field Descriptions...............................................................................................................3409
Table 30-16. CAN_TEST Register Field Descriptions........................................................................................................... 3410
Table 30-17. CAN_PERR Register Field Descriptions.......................................................................................................... 3412
Table 30-18. CAN_RAM_INIT Register Field Descriptions....................................................................................................3413
Table 30-19. CAN_GLB_INT_EN Register Field Descriptions.............................................................................................. 3414
Table 30-20. CAN_GLB_INT_FLG Register Field Descriptions............................................................................................ 3415
Table 30-21. CAN_GLB_INT_CLR Register Field Descriptions............................................................................................ 3416
Table 30-22. CAN_ABOTR Register Field Descriptions........................................................................................................ 3417
Table 30-23. CAN_TXRQ_X Register Field Descriptions...................................................................................................... 3418
Table 30-24. CAN_TXRQ_21 Register Field Descriptions.................................................................................................... 3419
Table 30-25. CAN_NDAT_X Register Field Descriptions.......................................................................................................3420
Table 30-26. CAN_NDAT_21 Register Field Descriptions..................................................................................................... 3421
Table 30-27. CAN_IPEN_X Register Field Descriptions........................................................................................................3422
Table 30-28. CAN_IPEN_21 Register Field Descriptions...................................................................................................... 3423
Table 30-29. CAN_MVAL_X Register Field Descriptions.......................................................................................................3424
Table 30-30. CAN_MVAL_21 Register Field Descriptions..................................................................................................... 3425
Table 30-31. CAN_IP_MUX21 Register Field Descriptions................................................................................................... 3426
Table 30-32. CAN_IF1CMD Register Field Descriptions....................................................................................................... 3427
Table 30-33. CAN_IF1MSK Register Field Descriptions....................................................................................................... 3430
Table 30-34. CAN_IF1ARB Register Field Descriptions........................................................................................................3431
Table 30-35. CAN_IF1MCTL Register Field Descriptions..................................................................................................... 3433
Table 30-36. CAN_IF1DATA Register Field Descriptions...................................................................................................... 3435
Table 30-37. CAN_IF1DATB Register Field Descriptions...................................................................................................... 3436
Table 30-38. CAN_IF2CMD Register Field Descriptions....................................................................................................... 3437
Table 30-39. CAN_IF2MSK Register Field Descriptions....................................................................................................... 3440
Table 30-40. CAN_IF2ARB Register Field Descriptions........................................................................................................3441
Table 30-41. CAN_IF2MCTL Register Field Descriptions..................................................................................................... 3443
Table 30-42. CAN_IF2DATA Register Field Descriptions...................................................................................................... 3445
Table 30-43. CAN_IF2DATB Register Field Descriptions...................................................................................................... 3446

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Table 30-44. CAN_IF3OBS Register Field Descriptions........................................................................................................3447

Table 30-45. CAN_IF3MSK Register Field Descriptions....................................................................................................... 3449
Table 30-46. CAN_IF3ARB Register Field Descriptions........................................................................................................3450
Table 30-47. CAN_IF3MCTL Register Field Descriptions..................................................................................................... 3451
Table 30-48. CAN_IF3DATA Register Field Descriptions...................................................................................................... 3453
Table 30-49. CAN_IF3DATB Register Field Descriptions...................................................................................................... 3454
Table 30-50. CAN_IF3UPD Register Field Descriptions........................................................................................................3455
Table 30-51. CAN Registers to Driverlib Functions............................................................................................................... 3455
Table 31-1. Abbreviations...................................................................................................................................................... 3460
Table 31-2. F2838x ESC versus Beckhoff ET1100................................................................................................................3462
Table 31-3. EtherCAT Physical Layer Signals....................................................................................................................... 3466
Table 31-4. EtherCAT IP Errata............................................................................................................................................. 3470
Table 31-5. ESC Integration Figure Sections.........................................................................................................................3472
Table 31-6. ESC Address Map on CPU1...............................................................................................................................3472
Table 31-7. ESC Address Map on CM ..................................................................................................................................3473
Table 31-8. Service Request Generation Map.......................................................................................................................3476
Table 31-9. Status LED Options and Priority......................................................................................................................... 3479
Table 31-10. LINKACT and PHY MII_LINK States................................................................................................................ 3479
Table 31-11. ESC SYNC Integration Map.............................................................................................................................. 3485
Table 31-12. ESC LATCH0/1 Trigger Table........................................................................................................................... 3488
Table 31-13. CPU1 Software Initialization Sequence............................................................................................................ 3491
Table 31-14. CM Software Initialization Sequence................................................................................................................ 3492
Table 31-15. ESC Configuration Constants Table................................................................................................................. 3492
Table 31-16. ESC IP Register Constants Table..................................................................................................................... 3492
Table 31-17. EtherCAT IP Register Documentation...............................................................................................................3493
Table 31-18. ECAT Base Address Table (C28)......................................................................................................................3493
Table 31-19. ESCSS_REGS Registers................................................................................................................................. 3494
Table 31-20. ESCSS_REGS Access Type Codes.................................................................................................................3494
Table 31-21. ESCSS_IPREVNUM Register Field Descriptions.............................................................................................3496
Table 31-22. ESCSS_INTR_RIS Register Field Descriptions............................................................................................... 3497
Table 31-23. ESCSS_INTR_MASK Register Field Descriptions........................................................................................... 3499
Table 31-24. ESCSS_INTR_MIS Register Field Descriptions............................................................................................... 3501
Table 31-25. ESCSS_INTR_CLR Register Field Descriptions.............................................................................................. 3503
Table 31-26. ESCSS_INTR_SET Register Field Descriptions.............................................................................................. 3504
Table 31-27. ESCSS_LATCH_SEL Register Field Descriptions............................................................................................3506
Table 31-28. ESCSS_ACCESS_CTRL Register Field Descriptions......................................................................................3507
Table 31-29. ESCSS_GPIN_DAT Register Field Descriptions.............................................................................................. 3508
Table 31-30. ESCSS_GPIN_PIPE Register Field Descriptions.............................................................................................3509
Table 31-31. ESCSS_GPIN_GRP_CAP_SEL Register Field Descriptions........................................................................... 3510
Table 31-32. ESCSS_GPOUT_DAT Register Field Descriptions.......................................................................................... 3512
Table 31-33. ESCSS_GPOUT_PIPE Register Field Descriptions.........................................................................................3513
Table 31-34. ESCSS_GPOUT_GRP_CAP_SEL Register Field Descriptions....................................................................... 3514
Table 31-35. ESCSS_MEM_TEST Register Field Descriptions............................................................................................ 3515
Table 31-36. ESCSS_RESET_DEST_CONFIG Register Field Descriptions........................................................................ 3516
Table 31-37. ESCSS_SYNC0_CONFIG Register Field Descriptions....................................................................................3518
Table 31-38. ESCSS_SYNC1_CONFIG Register Field Descriptions....................................................................................3519
Table 31-39. ESCSS_CONFIG_REGS Registers................................................................................................................. 3520
Table 31-40. ESCSS_CONFIG_REGS Access Type Codes.................................................................................................3520
Table 31-41. ESCSS_CONFIG_LOCK Register Field Descriptions...................................................................................... 3521
Table 31-42. ESCSS_MISC_IO_CONFIG Register Field Descriptions................................................................................. 3522
Table 31-43. ESCSS_PHY_IO_CONFIG Register Field Descriptions...................................................................................3523
Table 31-44. ESCSS_SYNC_IO_CONFIG Register Field Descriptions................................................................................ 3524
Table 31-45. ESCSS_LATCH_IO_CONFIG Register Field Descriptions...............................................................................3525
Table 31-46. ESCSS_GPIN_SEL Register Field Descriptions.............................................................................................. 3526
Table 31-47. ESCSS_GPIN_IOPAD_SEL Register Field Descriptions................................................................................. 3527
Table 31-48. ESCSS_GPOUT_SEL Register Field Descriptions.......................................................................................... 3528
Table 31-49. ESCSS_GPOUT_IOPAD_SEL Register Field Descriptions............................................................................. 3529
Table 31-50. ESCSS_LED_CONFIG Register Field Descriptions.........................................................................................3530
Table 31-51. ESCSS_MISC_CONFIG Register Field Descriptions.......................................................................................3532
Table 31-52. ESC_SS Registers to Driverlib Functions.........................................................................................................3532
Table 32-1. FSI Receiver Core Signals..................................................................................................................................3541

108 TMS320F2838x Real-Time Microcontrollers With Connectivity Manager SPRUII0E – MAY 2019 – REVISED SEPTEMBER 2023
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Table 32-2. FSI Transmitter Core Signals..............................................................................................................................3541

Table 32-3. External Trigger Sources and Their Index.......................................................................................................... 3545
Table 32-4. Basic Frame Structure........................................................................................................................................ 3559
Table 32-5. Frame Types and Their 4-bit Codes................................................................................................................... 3561
Table 32-6. Ping Frame......................................................................................................................................................... 3561
Table 32-7. Error Frame.........................................................................................................................................................3562
Table 32-8. Data Frame......................................................................................................................................................... 3562
Table 32-9. Multi-Lane Frame Format................................................................................................................................... 3562
Table 32-10. FSI TDM Inputs.................................................................................................................................................3568
Table 32-11. RX_TRIGx Trigger Select Signals.....................................................................................................................3570
Table 32-12. FSI-SPI Compatibility Frame Structure.............................................................................................................3571
Table 32-13. Contents of Data Received by a Standard SPI.................................................................................................3571
Table 32-14. FSI as Master Transmitter, SPI as Slave Receiver........................................................................................... 3572
Table 32-15. SPI as Master Transmitter, FSI as Slave Receiver........................................................................................... 3573
Table 32-16. FSI Base Address Table (C28)......................................................................................................................... 3588
Table 32-17. FSI_TX_REGS Registers................................................................................................................................. 3589
Table 32-18. FSI_TX_REGS Access Type Codes.................................................................................................................3589
Table 32-19. TX_MASTER_CTRL Register Field Descriptions............................................................................................. 3591
Table 32-20. TX_CLK_CTRL Register Field Descriptions..................................................................................................... 3592
Table 32-21. TX_OPER_CTRL_LO Register Field Descriptions........................................................................................... 3593
Table 32-22. TX_OPER_CTRL_HI Register Field Descriptions............................................................................................ 3595
Table 32-23. TX_FRAME_CTRL Register Field Descriptions............................................................................................... 3596
Table 32-24. TX_FRAME_TAG_UDATA Register Field Descriptions.................................................................................... 3597
Table 32-25. TX_BUF_PTR_LOAD Register Field Descriptions........................................................................................... 3598
Table 32-26. TX_BUF_PTR_STS Register Field Descriptions.............................................................................................. 3599
Table 32-27. TX_PING_CTRL Register Field Descriptions................................................................................................... 3600
Table 32-28. TX_PING_TAG Register Field Descriptions......................................................................................................3601
Table 32-29. TX_PING_TO_REF Register Field Descriptions...............................................................................................3602
Table 32-30. TX_PING_TO_CNT Register Field Descriptions.............................................................................................. 3603
Table 32-31. TX_INT_CTRL Register Field Descriptions...................................................................................................... 3604
Table 32-32. TX_DMA_CTRL Register Field Descriptions.................................................................................................... 3606
Table 32-33. TX_LOCK_CTRL Register Field Descriptions.................................................................................................. 3607
Table 32-34. TX_EVT_STS Register Field Descriptions....................................................................................................... 3608
Table 32-35. TX_EVT_CLR Register Field Descriptions....................................................................................................... 3609
Table 32-36. TX_EVT_FRC Register Field Descriptions....................................................................................................... 3610
Table 32-37. TX_USER_CRC Register Field Descriptions.................................................................................................... 3611
Table 32-38. TX_ECC_DATA Register Field Descriptions.....................................................................................................3612
Table 32-39. TX_ECC_VAL Register Field Descriptions....................................................................................................... 3613
Table 32-40. TX_BUF_BASE_y Register Field Descriptions.................................................................................................3614
Table 32-41. FSI_RX_REGS Registers................................................................................................................................. 3615
Table 32-42. FSI_RX_REGS Access Type Codes................................................................................................................ 3616
Table 32-43. RX_MASTER_CTRL Register Field Descriptions.............................................................................................3617
Table 32-44. RX_OPER_CTRL Register Field Descriptions................................................................................................. 3618
Table 32-45. RX_FRAME_INFO Register Field Descriptions................................................................................................3619
Table 32-46. RX_FRAME_TAG_UDATA Register Field Descriptions....................................................................................3620
Table 32-47. RX_DMA_CTRL Register Field Descriptions....................................................................................................3621
Table 32-48. RX_EVT_STS Register Field Descriptions....................................................................................................... 3622
Table 32-49. RX_CRC_INFO Register Field Descriptions.....................................................................................................3625
Table 32-50. RX_EVT_CLR Register Field Descriptions.......................................................................................................3626
Table 32-51. RX_EVT_FRC Register Field Descriptions.......................................................................................................3628
Table 32-52. RX_BUF_PTR_LOAD Register Field Descriptions...........................................................................................3631
Table 32-53. RX_BUF_PTR_STS Register Field Descriptions..............................................................................................3632
Table 32-54. RX_FRAME_WD_CTRL Register Field Descriptions....................................................................................... 3633
Table 32-55. RX_FRAME_WD_REF Register Field Descriptions......................................................................................... 3634
Table 32-56. RX_FRAME_WD_CNT Register Field Descriptions......................................................................................... 3635
Table 32-57. RX_PING_WD_CTRL Register Field Descriptions...........................................................................................3636
Table 32-58. RX_PING_TAG Register Field Descriptions..................................................................................................... 3637
Table 32-59. RX_PING_WD_REF Register Field Descriptions............................................................................................. 3638
Table 32-60. RX_PING_WD_CNT Register Field Descriptions.............................................................................................3639
Table 32-61. RX_INT1_CTRL Register Field Descriptions....................................................................................................3640
Table 32-62. RX_INT2_CTRL Register Field Descriptions....................................................................................................3643

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Table 32-63. RX_LOCK_CTRL Register Field Descriptions..................................................................................................3646

Table 32-64. RX_ECC_DATA Register Field Descriptions.................................................................................................... 3647
Table 32-65. RX_ECC_VAL Register Field Descriptions....................................................................................................... 3648
Table 32-66. RX_ECC_SEC_DATA Register Field Descriptions........................................................................................... 3649
Table 32-67. RX_ECC_LOG Register Field Descriptions......................................................................................................3650
Table 32-68. RX_FRAME_TAG_CMP Register Field Descriptions....................................................................................... 3651
Table 32-69. RX_PING_TAG_CMP Register Field Descriptions........................................................................................... 3652
Table 32-70. RX_DLYLINE_CTRL Register Field Descriptions............................................................................................. 3653
Table 32-71. RX_VIS_1 Register Field Descriptions............................................................................................................. 3654
Table 32-72. RX_BUF_BASE_y Register Field Descriptions................................................................................................ 3655
Table 32-73. FSI Registers to Driverlib Functions................................................................................................................. 3655
Table 33-1. Dependency of Delay d on the Divide-Down Value IPSC................................................................................... 3666
Table 33-2. Operating Modes of the I2C Module................................................................................................................... 3668
Table 33-3. Master-Transmitter/Receiver Bus Activity Defined by the RM, STT, and STP Bits of I2CMDR.......................... 3668
Table 33-4. How the MST and FDF Bits of I2CMDR Affect the Role of the TRX Bit of I2CMDR...........................................3674
Table 33-5. Ways to Generate a NACK Bit............................................................................................................................ 3678
Table 33-6. Descriptions of the Basic I2C Interrupt Requests............................................................................................... 3679
Table 33-7. I2C Base Address Table (C28)........................................................................................................................... 3685
Table 33-8. I2C_REGS Registers.......................................................................................................................................... 3686
Table 33-9. I2C_REGS Access Type Codes......................................................................................................................... 3686
Table 33-10. I2COAR Register Field Descriptions.................................................................................................................3688
Table 33-11. I2CIER Register Field Descriptions...................................................................................................................3689
Table 33-12. I2CSTR Register Field Descriptions................................................................................................................. 3690
Table 33-13. I2CCLKL Register Field Descriptions............................................................................................................... 3694
Table 33-14. I2CCLKH Register Field Descriptions...............................................................................................................3695
Table 33-15. I2CCNT Register Field Descriptions................................................................................................................. 3696
Table 33-16. I2CDRR Register Field Descriptions.................................................................................................................3697
Table 33-17. I2CSAR Register Field Descriptions................................................................................................................. 3698
Table 33-18. I2CDXR Register Field Descriptions.................................................................................................................3699
Table 33-19. I2CMDR Register Field Descriptions................................................................................................................ 3700
Table 33-20. I2CISRC Register Field Descriptions................................................................................................................3703
Table 33-21. I2CEMDR Register Field Descriptions..............................................................................................................3704
Table 33-22. I2CPSC Register Field Descriptions................................................................................................................. 3705
Table 33-23. I2CFFTX Register Field Descriptions............................................................................................................... 3706
Table 33-24. I2CFFRX Register Field Descriptions............................................................................................................... 3708
Table 33-25. I2C Registers to Driverlib Functions................................................................................................................. 3709
Table 34-1. McBSP Interface Pins/Signals............................................................................................................................ 3713
Table 34-2. Register Bits That Determine the Number of Phases, Words, and Bits..............................................................3720
Table 34-3. Interrupts and DMA Events Generated by a McBSP.......................................................................................... 3724
Table 34-4. Effects of DLB and CLKSTP on Clock Modes.................................................................................................... 3726
Table 34-5. Choosing an Input Clock for the Sample Rate Generator with the SCLKME and CLKSM Bits.......................... 3726
Table 34-6. Polarity Options for the Input to the Sample Rate Generator............................................................................. 3727
Table 34-7. Input Clock Selection for Sample Rate Generator.............................................................................................. 3731
Table 34-8. Block - Channel Assignment...............................................................................................................................3740
Table 34-9. 2-Partition Mode..................................................................................................................................................3740
Table 34-10. 8-Partition Mode................................................................................................................................................3740
Table 34-11. Receive Channel Assignment and Control With Eight Receive Partitions........................................................ 3743
Table 34-12. Transmit Channel Assignment and Control When Eight Transmit Partitions Are Used.................................... 3743
Table 34-13. Selecting a Transmit Multichannel Selection Mode With the XMCM Bits......................................................... 3745
Table 34-14. Bits Used to Enable and Configure the Clock Stop Mode................................................................................ 3748
Table 34-15. Effects of CLKSTP, CLKXP, and CLKRP on the Clock Scheme....................................................................... 3749
Table 34-16. Bit Values Required to Configure the McBSP as an SPI Master ..................................................................... 3752
Table 34-17. Bit Values Required to Configure the McBSP as an SPI Slave ....................................................................... 3753
Table 34-18. Register Bits Used to Reset or Enable the McBSP Receiver Field Descriptions..............................................3755
Table 34-19. Reset State of Each McBSP Pin.......................................................................................................................3755
Table 34-20. Register Bit Used to Enable/Disable the Digital Loopback Mode..................................................................... 3756
Table 34-21. Receive Signals Connected to Transmit Signals in Digital Loopback Mode.....................................................3756
Table 34-22. Register Bits Used to Enable/Disable the Clock Stop Mode.............................................................................3756
Table 34-23. Effects of CLKSTP, CLKXP, and CLKRP on the Clock Scheme....................................................................... 3757
Table 34-24. Register Bit Used to Enable/Disable the Receive Multichannel Selection Mode..............................................3757
Table 34-25. Register Bit Used to Choose One or Two Phases for the Receive Frame....................................................... 3757

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Table 34-26. Register Bits Used to Set the Receive Word Lengths.......................................................................................3758
Table 34-27. Register Bits Used to Set the Receive Frame Length...................................................................................... 3759
Table 34-28. How to Calculate the Length of the Receive Frame......................................................................................... 3759
Table 34-29. Register Bit Used to Enable/Disable the Receive Frame-Synchronization Ignore Function.............................3760
Table 34-30. Register Bits Used to Set the Receive Companding Mode.............................................................................. 3761
Table 34-31. Register Bits Used to Set the Receive Data Delay........................................................................................... 3763
Table 34-32. Register Bits Used to Set the Receive Sign-Extension and Justification Mode................................................3765
Table 34-33. Example: Use of RJUST Field With 12-Bit Data Value ABCh...........................................................................3765
Table 34-34. Example: Use of RJUST Field With 20-Bit Data Value ABCDEh......................................................................3765
Table 34-35. Register Bits Used to Set the Receive Interrupt Mode..................................................................................... 3766
Table 34-36. Register Bits Used to Set the Receive Frame Synchronization Mode..............................................................3767
Table 34-37. Select Sources to Provide the Receive Frame-Synchronization Signal and the Effect on the FSR Pin........... 3768
Table 34-38. Register Bit Used to Set Receive Frame-Synchronization Polarity.................................................................. 3768
Table 34-39. Register Bits Used to Set the SRG Frame-Synchronization Period and Pulse Width...................................... 3770
Table 34-40. Register Bits Used to Set the Receive Clock Mode..........................................................................................3771
Table 34-41. Receive Clock Signal Source Selection............................................................................................................3772
Table 34-42. Register Bit Used to Set Receive Clock Polarity...............................................................................................3772
Table 34-43. Register Bits Used to Set the Sample Rate Generator (SRG) Clock Divide-Down Value................................ 3774
Table 34-44. Register Bit Used to Set the SRG Clock Synchronization Mode...................................................................... 3774
Table 34-45. Register Bits Used to Set the SRG Clock Mode (Choose an Input Clock)....................................................... 3775
Table 34-46. Register Bits Used to Set the SRG Input Clock Polarity................................................................................... 3775
Table 34-47. Register Bits Used to Place Transmitter in Reset Field Descriptions............................................................... 3777
Table 34-48. Register Bit Used to Enable/Disable the Digital Loopback Mode..................................................................... 3778
Table 34-49. Receive Signals Connected to Transmit Signals in Digital Loopback Mode.....................................................3778
Table 34-50. Register Bits Used to Enable/Disable the Clock Stop Mode.............................................................................3778
Table 34-51. Effects of CLKSTP, CLKXP, and CLKRP on the Clock Scheme....................................................................... 3779
Table 34-52. Register Bits Used to Enable/Disable Transmit Multichannel Selection........................................................... 3779
Table 34-53. Use of the Transmit Channel Enable Registers................................................................................................ 3780
Table 34-54. Register Bit Used to Choose 1 or 2 Phases for the Transmit Frame................................................................ 3782
Table 34-55. Register Bits Used to Set the Transmit Word Lengths......................................................................................3782
Table 34-56. Register Bits Used to Set the Transmit Frame Length......................................................................................3783
Table 34-57. How to Calculate Frame Length....................................................................................................................... 3783
Table 34-58. Register Bit Used to Enable/Disable the Transmit Frame-Synchronization Ignore Function............................3784
Table 34-59. Register Bits Used to Set the Transmit Companding Mode..............................................................................3785
Table 34-60. Register Bits Used to Set the Transmit Data Delay.......................................................................................... 3786
Table 34-61. Register Bit Used to Set the Transmit DXENA (DX Delay Enabler) Mode....................................................... 3788
Table 34-62. Register Bits Used to Set the Transmit Interrupt Mode.....................................................................................3788
Table 34-63. Register Bits Used to Set the Transmit Frame-Synchronization Mode.............................................................3789
Table 34-64. How FSXM and FSGM Select the Source of Transmit Frame-Synchronization Pulses................................... 3789
Table 34-65. Register Bit Used to Set Transmit Frame-Synchronization Polarity..................................................................3790
Table 34-66. Register Bits Used to Set SRG Frame-Synchronization Period and Pulse Width............................................ 3791
Table 34-67. Register Bit Used to Set the Transmit Clock Mode...........................................................................................3792
Table 34-68. How the CLKXM Bit Selects the Transmit Clock and the Corresponding Status of the MCLKX pin.................3792
Table 34-69. Register Bit Used to Set Transmit Clock Polarity..............................................................................................3792
Table 34-70. McBSP Emulation Modes Selectable with FREE and SOFT Bits of SPCR2....................................................3794
Table 34-71. Reset State of Each McBSP Pin.......................................................................................................................3794
Table 34-72. Receive Interrupt Sources and Signals.............................................................................................................3799
Table 34-73. Transmit Interrupt Sources and Signals............................................................................................................3800
Table 34-74. Error Flags........................................................................................................................................................ 3800
Table 34-75. McBSP Mode Selection.................................................................................................................................... 3801
Table 34-76. MCBSP Base Address Table (C28).................................................................................................................. 3806
Table 34-77. MCBSP_REGS Registers.................................................................................................................................3807
Table 34-78. McBSP_REGS Access Type Codes................................................................................................................. 3807
Table 34-79. DRR2 Register Field Descriptions.................................................................................................................... 3809
Table 34-80. DRR1 Register Field Descriptions.................................................................................................................... 3810
Table 34-81. DXR2 Register Field Descriptions.....................................................................................................................3811
Table 34-82. DXR1 Register Field Descriptions.................................................................................................................... 3812
Table 34-83. SPCR2 Register Field Descriptions.................................................................................................................. 3813
Table 34-84. SPCR1 Register Field Descriptions.................................................................................................................. 3816
Table 34-85. RCR2 Register Field Descriptions.................................................................................................................... 3819
Table 34-86. RCR1 Register Field Descriptions.................................................................................................................... 3821

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Table 34-87. XCR2 Register Field Descriptions.................................................................................................................... 3822

Table 34-88. XCR1 Register Field Descriptions.................................................................................................................... 3824
Table 34-89. SRGR2 Register Field Descriptions..................................................................................................................3825
Table 34-90. SRGR1 Register Field Descriptions..................................................................................................................3827
Table 34-91. MCR2 Register Field Descriptions....................................................................................................................3828
Table 34-92. MCR1 Register Field Descriptions....................................................................................................................3830
Table 34-93. RCERA Register Field Descriptions................................................................................................................. 3832
Table 34-94. RCERB Register Field Descriptions................................................................................................................. 3833
Table 34-95. XCERA Register Field Descriptions..................................................................................................................3834
Table 34-96. XCERB Register Field Descriptions..................................................................................................................3835
Table 34-97. PCR Register Field Descriptions...................................................................................................................... 3836
Table 34-98. RCERC Register Field Descriptions................................................................................................................. 3839
Table 34-99. RCERD Register Field Descriptions................................................................................................................. 3840
Table 34-100. XCERC Register Field Descriptions............................................................................................................... 3841
Table 34-101. XCERD Register Field Descriptions............................................................................................................... 3842
Table 34-102. RCERE Register Field Descriptions............................................................................................................... 3843
Table 34-103. RCERF Register Field Descriptions................................................................................................................3844
Table 34-104. XCERE Register Field Descriptions................................................................................................................3845
Table 34-105. XCERF Register Field Descriptions................................................................................................................3846
Table 34-106. RCERG Register Field Descriptions............................................................................................................... 3847
Table 34-107. RCERH Register Field Descriptions............................................................................................................... 3848
Table 34-108. XCERG Register Field Descriptions............................................................................................................... 3849
Table 34-109. XCERH Register Field Descriptions............................................................................................................... 3850
Table 34-110. MFFINT Register Field Descriptions............................................................................................................... 3851
Table 34-111. MCBSP Registers to Driverlib Functions.........................................................................................................3851
Table 35-1. PMBUS Base Address Table (C28).................................................................................................................... 3879
Table 35-2. PMBUS_REGS Registers...................................................................................................................................3880
Table 35-3. PMBUS_REGS Access Type Codes.................................................................................................................. 3880
Table 35-4. PMBMC Register Field Descriptions...................................................................................................................3881
Table 35-5. PMBTXBUF Register Field Descriptions............................................................................................................ 3882
Table 35-6. PMBRXBUF Register Field Descriptions............................................................................................................ 3883
Table 35-7. PMBACK Register Field Descriptions.................................................................................................................3884
Table 35-8. PMBSTS Register Field Descriptions................................................................................................................. 3885
Table 35-9. PMBINTM Register Field Descriptions............................................................................................................... 3887
Table 35-10. PMBSC Register Field Descriptions................................................................................................................. 3889
Table 35-11. PMBHSA Register Field Descriptions............................................................................................................... 3891
Table 35-12. PMBCTRL Register Field Descriptions.............................................................................................................3892
Table 35-13. PMBTIMCTL Register Field Descriptions......................................................................................................... 3894
Table 35-14. PMBTIMCLK Register Field Descriptions......................................................................................................... 3895
Table 35-15. PMBTIMSTSETUP Register Field Descriptions............................................................................................... 3896
Table 35-16. PMBTIMBIDLE Register Field Descriptions......................................................................................................3897
Table 35-17. PMBTIMLOWTIMOUT Register Field Descriptions.......................................................................................... 3898
Table 35-18. PMBTIMHIGHTIMOUT Register Field Descriptions......................................................................................... 3899
Table 35-19. PMBUS Registers to Driverlib Functions.......................................................................................................... 3899
Table 36-1. SCI Module Signal Summary..............................................................................................................................3903
Table 36-2. Programming the Data Format Using SCICCR.................................................................................................. 3906
Table 36-3. Asynchronous Baud Register Values for Common SCI Bit Rates...................................................................... 3913
Table 36-4. SCI Interrupt Flags..............................................................................................................................................3915
Table 36-5. SCI Base Address Table (C28)........................................................................................................................... 3919
Table 36-6. SCI_REGS Registers..........................................................................................................................................3920
Table 36-7. SCI_REGS Access Type Codes......................................................................................................................... 3920
Table 36-8. SCICCR Register Field Descriptions.................................................................................................................. 3921
Table 36-9. SCICTL1 Register Field Descriptions................................................................................................................. 3923
Table 36-10. SCIHBAUD Register Field Descriptions........................................................................................................... 3925
Table 36-11. SCILBAUD Register Field Descriptions............................................................................................................ 3926
Table 36-12. SCICTL2 Register Field Descriptions............................................................................................................... 3927
Table 36-13. SCIRXST Register Field Descriptions.............................................................................................................. 3929
Table 36-14. SCIRXEMU Register Field Descriptions........................................................................................................... 3931
Table 36-15. SCIRXBUF Register Field Descriptions............................................................................................................3932
Table 36-16. SCITXBUF Register Field Descriptions............................................................................................................ 3933
Table 36-17. SCIFFTX Register Field Descriptions............................................................................................................... 3934

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Table 36-18. SCIFFRX Register Field Descriptions...............................................................................................................3936

Table 36-19. SCIFFCT Register Field Descriptions...............................................................................................................3938
Table 36-20. SCIPRI Register Field Descriptions.................................................................................................................. 3939
Table 36-21. SCI Registers to Driverlib Functions................................................................................................................. 3939
Table 37-1. SPI Module Signal Summary.............................................................................................................................. 3946
Table 37-2. SPI Interrupt Flag Modes.................................................................................................................................... 3948
Table 37-3. SPI Clocking Scheme Selection Guide...............................................................................................................3956
Table 37-4. 4-wire versus 3-wire SPI Pin Functions.............................................................................................................. 3959
Table 37-5. 3-Wire SPI Pin Configuration.............................................................................................................................. 3960
Table 37-6. SPI Base Address Table (C28)........................................................................................................................... 3969
Table 37-7. SPI_REGS Registers..........................................................................................................................................3970
Table 37-8. SPI_REGS Access Type Codes......................................................................................................................... 3970
Table 37-9. SPICCR Register Field Descriptions.................................................................................................................. 3971
Table 37-10. SPICTL Register Field Descriptions................................................................................................................. 3973
Table 37-11. SPISTS Register Field Descriptions..................................................................................................................3975
Table 37-12. SPIBRR Register Field Descriptions.................................................................................................................3977
Table 37-13. SPIRXEMU Register Field Descriptions........................................................................................................... 3978
Table 37-14. SPIRXBUF Register Field Descriptions............................................................................................................ 3979
Table 37-15. SPITXBUF Register Field Descriptions............................................................................................................ 3980
Table 37-16. SPIDAT Register Field Descriptions................................................................................................................. 3981
Table 37-17. SPIFFTX Register Field Descriptions............................................................................................................... 3982
Table 37-18. SPIFFRX Register Field Descriptions...............................................................................................................3984
Table 37-19. SPIFFCT Register Field Descriptions............................................................................................................... 3986
Table 37-20. SPIPRI Register Field Descriptions.................................................................................................................. 3987
Table 37-21. SPI Registers to Driverlib Functions................................................................................................................. 3988
Table 38-1. USB Memory Access from Software...................................................................................................................4004
Table 38-2. USB Memory Access from CCS IDE.................................................................................................................. 4005
Table 38-3. USB Base Address Table (C28)..........................................................................................................................4012
Table 38-4. USB_REGS Registers........................................................................................................................................ 4013
Table 38-5. USB_REGS Access Type Codes........................................................................................................................4015
Table 38-6. USBFADDR Register Field Descriptions............................................................................................................ 4017
Table 38-7. USBPOWER Register Field Descriptions........................................................................................................... 4018
Table 38-8. USBTXIS Register Field Descriptions.................................................................................................................4019
Table 38-9. USBRXIS Register Field Descriptions................................................................................................................ 4020
Table 38-10. USBTXIE Register Field Descriptions...............................................................................................................4021
Table 38-11. USBRXIE Register Field Descriptions...............................................................................................................4022
Table 38-12. USBIS Register Field Descriptions................................................................................................................... 4023
Table 38-13. USBIE Register Field Descriptions................................................................................................................... 4024
Table 38-14. USBFRAME Register Field Descriptions.......................................................................................................... 4025
Table 38-15. USBEPIDX Register Field Descriptions............................................................................................................4026
Table 38-16. USBTEST Register Field Descriptions............................................................................................................. 4027
Table 38-17. USBFIFO0 Register Field Descriptions............................................................................................................ 4028
Table 38-18. USBFIFO1 Register Field Descriptions............................................................................................................ 4029
Table 38-19. USBFIFO2 Register Field Descriptions............................................................................................................ 4030
Table 38-20. USBFIFO3 Register Field Descriptions............................................................................................................ 4031
Table 38-21. USBDEVCTL Register Field Descriptions........................................................................................................ 4032
Table 38-22. USBTXFIFOSZ Register Field Descriptions..................................................................................................... 4034
Table 38-23. USBRXFIFOSZ Register Field Descriptions.....................................................................................................4035
Table 38-24. USBTXFIFOADD Register Field Descriptions.................................................................................................. 4036
Table 38-25. USBRXFIFOADD Register Field Descriptions..................................................................................................4045
Table 38-26. USBCONTIM Register Field Descriptions........................................................................................................ 4054
Table 38-27. USBFSEOF Register Field Descriptions...........................................................................................................4055
Table 38-28. USBLSEOF Register Field Descriptions...........................................................................................................4056
Table 38-29. USBTXFUNCADDR0 Register Field Descriptions............................................................................................4057
Table 38-30. USBTXHUBADDR0 Register Field Descriptions.............................................................................................. 4058
Table 38-31. USBTXHUBPORT0 Register Field Descriptions...............................................................................................4059
Table 38-32. USBTXFUNCADDR1 Register Field Descriptions............................................................................................4060
Table 38-33. USBTXHUBADDR1 Register Field Descriptions.............................................................................................. 4061
Table 38-34. USBTXHUBPORT1 Register Field Descriptions...............................................................................................4062
Table 38-35. USBRXFUNCADDR1 Register Field Descriptions........................................................................................... 4063
Table 38-36. USBRXHUBADDR1 Register Field Descriptions..............................................................................................4064

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Table 38-37. USBRXHUBPORT1 Register Field Descriptions.............................................................................................. 4065

Table 38-38. USBTXFUNCADDR2 Register Field Descriptions............................................................................................4066
Table 38-39. USBTXHUBADDR2 Register Field Descriptions.............................................................................................. 4067
Table 38-40. USBTXHUBPORT2 Register Field Descriptions...............................................................................................4068
Table 38-41. USBRXFUNCADDR2 Register Field Descriptions........................................................................................... 4069
Table 38-42. USBRXHUBADDR2 Register Field Descriptions..............................................................................................4070
Table 38-43. USBRXHUBPORT2 Register Field Descriptions.............................................................................................. 4071
Table 38-44. USBTXFUNCADDR3 Register Field Descriptions............................................................................................4072
Table 38-45. USBTXHUBADDR3 Register Field Descriptions.............................................................................................. 4073
Table 38-46. USBTXHUBPORT3 Register Field Descriptions...............................................................................................4074
Table 38-47. USBRXFUNCADDR3 Register Field Descriptions........................................................................................... 4075
Table 38-48. USBRXHUBADDR3 Register Field Descriptions..............................................................................................4076
Table 38-49. USBRXHUBPORT3 Register Field Descriptions.............................................................................................. 4077
Table 38-50. USBCSRL0 Register Field Descriptions........................................................................................................... 4078
Table 38-51. USBCSRH0 Register Field Descriptions.......................................................................................................... 4080
Table 38-52. USBCOUNT0 Register Field Descriptions........................................................................................................4081
Table 38-53. USBTYPE0 Register Field Descriptions........................................................................................................... 4082
Table 38-54. USBNAKLMT Register Field Descriptions........................................................................................................ 4083
Table 38-55. USBTXMAXP1 Register Field Descriptions......................................................................................................4084
Table 38-56. USBTXCSRL1 Register Field Descriptions...................................................................................................... 4085
Table 38-57. USBTXCSRH1 Register Field Descriptions......................................................................................................4087
Table 38-58. USBRXMAXP1 Register Field Descriptions..................................................................................................... 4089
Table 38-59. USBRXCSRL1 Register Field Descriptions...................................................................................................... 4090
Table 38-60. USBRXCSRH1 Register Field Descriptions..................................................................................................... 4092
Table 38-61. USBRXCOUNT1 Register Field Descriptions...................................................................................................4094
Table 38-62. USBTXTYPE1 Register Field Descriptions.......................................................................................................4095
Table 38-63. USBTXINTERVAL1 Register Field Descriptions...............................................................................................4096
Table 38-64. USBRXTYPE1 Register Field Descriptions...................................................................................................... 4097
Table 38-65. USBRXINTERVAL1 Register Field Descriptions.............................................................................................. 4098
Table 38-66. USBTXMAXP2 Register Field Descriptions......................................................................................................4099
Table 38-67. USBTXCSRL2 Register Field Descriptions...................................................................................................... 4100
Table 38-68. USBTXCSRH2 Register Field Descriptions......................................................................................................4102
Table 38-69. USBRXMAXP2 Register Field Descriptions..................................................................................................... 4104
Table 38-70. USBRXCSRL2 Register Field Descriptions...................................................................................................... 4105
Table 38-71. USBRXCSRH2 Register Field Descriptions..................................................................................................... 4107
Table 38-72. USBRXCOUNT2 Register Field Descriptions...................................................................................................4109
Table 38-73. USBTXTYPE2 Register Field Descriptions....................................................................................................... 4110
Table 38-74. USBTXINTERVAL2 Register Field Descriptions............................................................................................... 4111
Table 38-75. USBRXTYPE2 Register Field Descriptions.......................................................................................................4112
Table 38-76. USBRXINTERVAL2 Register Field Descriptions...............................................................................................4113
Table 38-77. USBTXMAXP3 Register Field Descriptions...................................................................................................... 4114
Table 38-78. USBTXCSRL3 Register Field Descriptions.......................................................................................................4115
Table 38-79. USBTXCSRH3 Register Field Descriptions...................................................................................................... 4117
Table 38-80. USBRXMAXP3 Register Field Descriptions......................................................................................................4119
Table 38-81. USBRXCSRL3 Register Field Descriptions...................................................................................................... 4120
Table 38-82. USBRXCSRH3 Register Field Descriptions..................................................................................................... 4122
Table 38-83. USBRXCOUNT3 Register Field Descriptions...................................................................................................4124
Table 38-84. USBTXTYPE3 Register Field Descriptions.......................................................................................................4125
Table 38-85. USBTXINTERVAL3 Register Field Descriptions...............................................................................................4126
Table 38-86. USBRXTYPE3 Register Field Descriptions...................................................................................................... 4127
Table 38-87. USBRXINTERVAL3 Register Field Descriptions.............................................................................................. 4128
Table 38-88. USBRQPKTCOUNT1 Register Field Descriptions........................................................................................... 4129
Table 38-89. USBRQPKTCOUNT2 Register Field Descriptions........................................................................................... 4130
Table 38-90. USBRQPKTCOUNT3 Register Field Descriptions........................................................................................... 4131
Table 38-91. USBRXDPKTBUFDIS Register Field Descriptions...........................................................................................4132
Table 38-92. USBTXDPKTBUFDIS Register Field Descriptions........................................................................................... 4133
Table 38-93. USBEPC Register Field Descriptions............................................................................................................... 4134
Table 38-94. USBEPCRIS Register Field Descriptions......................................................................................................... 4136
Table 38-95. USBEPCIM Register Field Descriptions........................................................................................................... 4137
Table 38-96. USBEPCISC Register Field Descriptions......................................................................................................... 4138
Table 38-97. USBDRRIS Register Field Descriptions........................................................................................................... 4139

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Table 38-98. USBDRIM Register Field Descriptions............................................................................................................. 4140

Table 38-99. USBDRISC Register Field Descriptions........................................................................................................... 4141
Table 38-100. USBGPCS Register Field Descriptions.......................................................................................................... 4142
Table 38-101. USBVDC Register Field Descriptions............................................................................................................. 4143
Table 38-102. USBVDCRIS Register Field Descriptions....................................................................................................... 4144
Table 38-103. USBVDCIM Register Field Descriptions......................................................................................................... 4145
Table 38-104. USBVDCISC Register Field Descriptions....................................................................................................... 4146
Table 38-105. USBIDVRIS Register Field Descriptions.........................................................................................................4147
Table 38-106. USBIDVIM Register Field Descriptions...........................................................................................................4148
Table 38-107. USBIDVISC Register Field Descriptions.........................................................................................................4149
Table 38-108. USBDMASEL Register Field Descriptions......................................................................................................4150
Table 38-109. USB_GLB_INT_EN Register Field Descriptions.............................................................................................4151
Table 38-110. USB_GLB_INT_FLG Register Field Descriptions........................................................................................... 4152
Table 38-111. USB_GLB_INT_FLG_CLR Register Field Descriptions.................................................................................. 4153
Table 38-112. USBDMARIS Register Field Descriptions....................................................................................................... 4154
Table 38-113. USBDMAIM Register Field Descriptions......................................................................................................... 4155
Table 38-114. USBDMAISC Register Field Descriptions....................................................................................................... 4156
Table 38-115. USB Registers to Driverlib Functions.............................................................................................................. 4157
Table 40-1. Connectivity Manager Architectural Features..................................................................................................... 4178
Table 41-1. CM Clock Connections....................................................................................................................................... 4185
Table 41-2. CM Subsystem Exceptions................................................................................................................................. 4187
Table 41-3. Interrupts and NMI From CM to CPU1................................................................................................................4191
Table 41-4. Interrupts and NMI From CM to CPU2................................................................................................................4191
Table 41-5. NVIC Interrupt Mapping...................................................................................................................................... 4192
Table 41-6. CM Message RAM Accesses............................................................................................................................. 4198
Table 41-7. Error Handling of Memories................................................................................................................................ 4200
Table 41-8. Mapping of ECC Bits in Read Data From ECC/Parity Address Map.................................................................. 4201
Table 41-9. Mapping of Parity Bits in Read Data From ECC/Parity Address Map.................................................................4201
Table 41-10. Key Attributes of Trace Data Export..................................................................................................................4205
Table 41-11. CM SYSCTRL Base Address Table (CM)......................................................................................................... 4206
Table 41-12. CM_MEMCFG_REGS Registers...................................................................................................................... 4207
Table 41-13. CM_MEMCFG_REGS Access Type Codes..................................................................................................... 4207
Table 41-14. CxLOCK Register Field Descriptions................................................................................................................4209
Table 41-15. CxTEST Register Field Descriptions................................................................................................................ 4210
Table 41-16. CxINIT Register Field Descriptions................................................................................................................... 4211
Table 41-17. CxINITDONE Register Field Descriptions........................................................................................................ 4212
Table 41-18. CMMSGxLOCK Register Field Descriptions.....................................................................................................4213
Table 41-19. CMMSGxTEST Register Field Descriptions..................................................................................................... 4214
Table 41-20. CMMSGxINIT Register Field Descriptions........................................................................................................4216
Table 41-21. CMMSGxINITDONE Register Field Descriptions............................................................................................. 4217
Table 41-22. SxGROUP1_LOCK Register Field Descriptions...............................................................................................4218
Table 41-23. SxGROUP1_TEST Register Field Descriptions............................................................................................... 4219
Table 41-24. SxGROUP1_INIT Register Field Descriptions..................................................................................................4221
Table 41-25. SxGROUP1_INITDONE Register Field Descriptions....................................................................................... 4222
Table 41-26. ROM_LOCK Register Field Descriptions..........................................................................................................4223
Table 41-27. ROM_TEST Register Field Descriptions.......................................................................................................... 4224
Table 41-28. ROM_FORCE_ERROR Register Field Descriptions........................................................................................ 4225
Table 41-29. PERI_MEM_TEST_LOCK Register Field Descriptions.................................................................................... 4226
Table 41-30. PERI_MEM_TEST_CONTROL Register Field Descriptions............................................................................ 4227
Table 41-31. CM_MEMORYDIAGERROR_REGS Registers................................................................................................ 4228
Table 41-32. CM_MEMORYDIAGERROR_REGS Access Type Codes................................................................................4228
Table 41-33. DIAGERRFLG Register Field Descriptions.......................................................................................................4229
Table 41-34. DIAGERRCLR Register Field Descriptions...................................................................................................... 4231
Table 41-35. DIAGERRADDR Register Field Descriptions................................................................................................... 4232
Table 41-36. CM_MEMORYERROR_REGS Registers......................................................................................................... 4233
Table 41-37. CM_MEMORYERROR_REGS Access Type Codes........................................................................................ 4233
Table 41-38. UCERRFLG Register Field Descriptions.......................................................................................................... 4235
Table 41-39. UCERRSET Register Field Descriptions.......................................................................................................... 4237
Table 41-40. UCERRCLR Register Field Descriptions.......................................................................................................... 4238
Table 41-41. UCM4EADDR Register Field Descriptions....................................................................................................... 4239
Table 41-42. UCEMACEADDR Register Field Descriptions..................................................................................................4240

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Table 41-43. UCuDMAEADDR Register Field Descriptions.................................................................................................. 4241

Table 41-44. UCEtherCATMEMREADDR Register Field Descriptions..................................................................................4242
Table 41-45. UCEMACMEMREADDR Register Field Descriptions.......................................................................................4243
Table 41-46. BUSFAULTFLG Register Field Descriptions.....................................................................................................4244
Table 41-47. BUSFAULTCLR Register Field Descriptions.....................................................................................................4245
Table 41-48. M4BUSFAULTADDR Register Field Descriptions.............................................................................................4246
Table 41-49. uDMABUSFAULTADDR Register Field Descriptions........................................................................................4247
Table 41-50. EMACBUSFAULTADDR Register Field Descriptions....................................................................................... 4248
Table 41-51. CERRFLG Register Field Descriptions.............................................................................................................4249
Table 41-52. CERRSET Register Field Descriptions.............................................................................................................4250
Table 41-53. CERRCLR Register Field Descriptions.............................................................................................................4251
Table 41-54. CM4EADDR Register Field Descriptions..........................................................................................................4252
Table 41-55. CEMACEADDR Register Field Descriptions.................................................................................................... 4253
Table 41-56. CuDMAEADDR Register Field Descriptions.....................................................................................................4254
Table 41-57. CERRCNT Register Field Descriptions............................................................................................................ 4255
Table 41-58. CERRTHRES Register Field Descriptions........................................................................................................4256
Table 41-59. CEINTFLG Register Field Descriptions............................................................................................................ 4257
Table 41-60. CEINTSET Register Field Descriptions............................................................................................................ 4258
Table 41-61. CEINTCLR Register Field Descriptions............................................................................................................ 4259
Table 41-62. CEINTEN Register Field Descriptions.............................................................................................................. 4260
Table 41-63. CMSYSCTL_REGS Registers.......................................................................................................................... 4261
Table 41-64. CMSYSCTL_REGS Access Type Codes......................................................................................................... 4261
Table 41-65. CMPCLKCR0 Register Field Descriptions........................................................................................................4263
Table 41-66. CMPCLKCR1 Register Field Descriptions........................................................................................................4264
Table 41-67. CMPCLKCR2 Register Field Descriptions........................................................................................................4266
Table 41-68. CMSOFTPRESET0 Register Field Descriptions.............................................................................................. 4268
Table 41-69. CMSOFTPRESET1 Register Field Descriptions.............................................................................................. 4269
Table 41-70. CMSOFTPRESET2 Register Field Descriptions.............................................................................................. 4271
Table 41-71. CMCLKSTOPREQ0 Register Field Descriptions.............................................................................................. 4272
Table 41-72. CMCLKSTOPREQ1 Register Field Descriptions.............................................................................................. 4273
Table 41-73. CMCLKSTOPREQ2 Register Field Descriptions.............................................................................................. 4274
Table 41-74. CMCLKSTOPACK0 Register Field Descriptions...............................................................................................4275
Table 41-75. CMCLKSTOPACK1 Register Field Descriptions...............................................................................................4276
Table 41-76. CMCLKSTOPACK2 Register Field Descriptions...............................................................................................4277
Table 41-77. MCANWAKESTATUS Register Field Descriptions........................................................................................... 4278
Table 41-78. MCANWAKESTATUSCLR Register Field Descriptions.................................................................................... 4279
Table 41-79. PALLOCATESTS Register Field Descriptions.................................................................................................. 4280
Table 41-80. CMRESCCLR Register Field Descriptions....................................................................................................... 4281
Table 41-81. CMRESC Register Field Descriptions.............................................................................................................. 4283
Table 41-82. CMSYSCTLLOCK Register Field Descriptions.................................................................................................4285
Table 41-83. CM_CPUTIMER_REGS Registers................................................................................................................... 4286
Table 41-84. CM_CPUTIMER_REGS Access Type Codes...................................................................................................4286
Table 41-85. TIM Register Field Descriptions........................................................................................................................4287
Table 41-86. PRD Register Field Descriptions...................................................................................................................... 4288
Table 41-87. TCR Register Field Descriptions.......................................................................................................................4289
Table 41-88. TPR Register Field Descriptions.......................................................................................................................4291
Table 41-89. MPU_REGS Registers......................................................................................................................................4292
Table 41-90. MPU_REGS Access Type Codes..................................................................................................................... 4292
Table 41-91. MPU_CONTROL_REG Register Field Descriptions.........................................................................................4294
Table 41-92. ACC_VIO_INTEN Register Field Descriptions................................................................................................. 4295
Table 41-93. ACC_VIO_FLAGS Register Field Descriptions................................................................................................ 4296
Table 41-94. ACC_VIO_FLAGS_SET Register Field Descriptions....................................................................................... 4297
Table 41-95. ACC_VIO_FLAGS_CLR Register Field Descriptions....................................................................................... 4298
Table 41-96. ACC_VIO_ADDR_REG Register Field Descriptions........................................................................................ 4299
Table 41-97. REGION0_STARTADDRESSS Register Field Descriptions.............................................................................4300
Table 41-98. REGION0_CONFIG Register Field Descriptions..............................................................................................4301
Table 41-99. REGION1_STARTADDRESSS Register Field Descriptions.............................................................................4303
Table 41-100. REGION1_CONFIG Register Field Descriptions............................................................................................4304
Table 41-101. REGION2_STARTADDRESSS Register Field Descriptions...........................................................................4306
Table 41-102. REGION2_CONFIG Register Field Descriptions............................................................................................4307
Table 41-103. REGION3_STARTADDRESSS Register Field Descriptions...........................................................................4309

116 TMS320F2838x Real-Time Microcontrollers With Connectivity Manager SPRUII0E – MAY 2019 – REVISED SEPTEMBER 2023
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Table 41-104. REGION3_CONFIG Register Field Descriptions............................................................................................4310

Table 41-105. REGION4_STARTADDRESSS Register Field Descriptions...........................................................................4312
Table 41-106. REGION4_CONFIG Register Field Descriptions............................................................................................4313
Table 41-107. REGION5_STARTADDRESSS Register Field Descriptions...........................................................................4315
Table 41-108. REGION5_CONFIG Register Field Descriptions............................................................................................4316
Table 41-109. REGION6_STARTADDRESSS Register Field Descriptions...........................................................................4318
Table 41-110. REGION6_CONFIG Register Field Descriptions............................................................................................ 4319
Table 41-111. REGION7_STARTADDRESSS Register Field Descriptions........................................................................... 4321
Table 41-112. REGION7_CONFIG Register Field Descriptions............................................................................................ 4322
Table 41-113. CM_NMI_INTRUPT_REGS Registers............................................................................................................ 4324
Table 41-114. CM_NMI_INTRUPT_REGS Access Type Codes............................................................................................4324
Table 41-115. CMNMICFG Register Field Descriptions.........................................................................................................4325
Table 41-116. CMNMIFLG Register Field Descriptions......................................................................................................... 4326
Table 41-117. CMNMIFLGCLR Register Field Descriptions.................................................................................................. 4328
Table 41-118. CMNMIFLGFRC Register Field Descriptions..................................................................................................4330
Table 41-119. CMNMIWDCNT Register Field Descriptions...................................................................................................4332
Table 41-120. CMNMIWDPRD Register Field Descriptions.................................................................................................. 4333
Table 41-121. CMNMISHDWFLG Register Field Descriptions..............................................................................................4334
Table 41-122. NVIC Registers............................................................................................................................................... 4336
Table 41-123. NVIC Access Type Codes...............................................................................................................................4336
Table 41-124. NVIC_ISER0 Register Field Descriptions....................................................................................................... 4338
Table 41-125. NVIC_ISER1 Register Field Descriptions....................................................................................................... 4343
Table 41-126. NVIC_ICER0 Register Field Descriptions.......................................................................................................4348
Table 41-127. NVIC_ICER1 Register Field Descriptions.......................................................................................................4353
Table 41-128. NVIC_ISPR0 Register Field Descriptions....................................................................................................... 4358
Table 41-129. NVIC_ISPR1 Register Field Descriptions....................................................................................................... 4363
Table 41-130. NVIC_ISPR2 Register Field Descriptions....................................................................................................... 4368
Table 41-131. NVIC_ICPR0 Register Field Descriptions.......................................................................................................4373
Table 41-132. NVIC_ICPR1 Register Field Descriptions.......................................................................................................4378
Table 41-133. NVIC_IABR0 Register Field Descriptions....................................................................................................... 4383
Table 41-134. NVIC_IABR1 Register Field Descriptions....................................................................................................... 4386
Table 41-135. NVIC_IPR0 Register Field Descriptions......................................................................................................... 4389
Table 41-136. NVIC_IPR1 Register Field Descriptions......................................................................................................... 4390
Table 41-137. NVIC_IPR2 Register Field Descriptions......................................................................................................... 4391
Table 41-138. NVIC_IPR3 Register Field Descriptions......................................................................................................... 4392
Table 41-139. NVIC_IPR4 Register Field Descriptions......................................................................................................... 4393
Table 41-140. NVIC_IPR5 Register Field Descriptions......................................................................................................... 4394
Table 41-141. NVIC_IPR6 Register Field Descriptions......................................................................................................... 4395
Table 41-142. NVIC_IPR7 Register Field Descriptions......................................................................................................... 4396
Table 41-143. NVIC_IPR8 Register Field Descriptions......................................................................................................... 4397
Table 41-144. NVIC_IPR9 Register Field Descriptions......................................................................................................... 4398
Table 41-145. NVIC_IPR10 Register Field Descriptions....................................................................................................... 4399
Table 41-146. NVIC_IPR11 Register Field Descriptions........................................................................................................4400
Table 41-147. NVIC_IPR12 Register Field Descriptions....................................................................................................... 4401
Table 41-148. NVIC_IPR13 Register Field Descriptions....................................................................................................... 4402
Table 41-149. NVIC_IPR14 Register Field Descriptions....................................................................................................... 4403
Table 41-150. NVIC_IPR15 Register Field Descriptions....................................................................................................... 4404
Table 41-151. STIR Register Field Descriptions....................................................................................................................4405
Table 41-152. SCB Registers................................................................................................................................................ 4406
Table 41-153. SCB Access Type Codes................................................................................................................................4406
Table 41-154. ACTLR Register Field Descriptions................................................................................................................ 4408
Table 41-155. CPUID Register Field Descriptions.................................................................................................................4409
Table 41-156. ICSR Register Field Descriptions................................................................................................................... 4410
Table 41-157. VTOR Register Field Descriptions.................................................................................................................. 4412
Table 41-158. AIRCR Register Field Descriptions.................................................................................................................4413
Table 41-159. SCR Register Field Descriptions.................................................................................................................... 4415
Table 41-160. CCR Register Field Descriptions.................................................................................................................... 4416
Table 41-161. SHPR1 Register Field Descriptions................................................................................................................ 4418
Table 41-162. SHPR2 Register Field Descriptions................................................................................................................ 4419
Table 41-163. SHPR3 Register Field Descriptions................................................................................................................ 4420
Table 41-164. SHCSRS Register Field Descriptions............................................................................................................. 4421

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Table 41-165. CFSR Register Field Descriptions.................................................................................................................. 4425

Table 41-166. HFSR Register Field Descriptions.................................................................................................................. 4429
Table 41-167. MMFAR Register Field Descriptions............................................................................................................... 4430
Table 41-168. BFAR Register Field Descriptions...................................................................................................................4431
Table 41-169. AFSR Register Field Descriptions.................................................................................................................. 4432
Table 41-170. CSFR Registers.............................................................................................................................................. 4433
Table 41-171. CSFR Access Type Codes............................................................................................................................. 4433
Table 41-172. MMSR Register Field Descriptions................................................................................................................. 4434
Table 41-173. BFSR Register Field Descriptions.................................................................................................................. 4436
Table 41-174. UFSR Register Field Descriptions.................................................................................................................. 4438
Table 41-175. SYSTICK Registers........................................................................................................................................ 4440
Table 41-176. SYSTICK Access Type Codes........................................................................................................................4440
Table 41-177. SYST_CSR Register Field Descriptions......................................................................................................... 4441
Table 41-178. SYST_RVR Register Field Descriptions......................................................................................................... 4442
Table 41-179. SYST_CVR Register Field Descriptions......................................................................................................... 4443
Table 41-180. SYST_CALIB Register Field Descriptions...................................................................................................... 4444
Table 41-181. MPU Registers................................................................................................................................................4445
Table 41-182. MPU Access Type Codes............................................................................................................................... 4445
Table 41-183. MPU_TYPE Register Field Descriptions.........................................................................................................4446
Table 41-184. MPU_CTRL Register Field Descriptions.........................................................................................................4447
Table 41-185. MPU_RNR Register Field Descriptions.......................................................................................................... 4448
Table 41-186. MPU_RBAR Register Field Descriptions........................................................................................................ 4449
Table 41-187. MPU_RASR Register Field Descriptions........................................................................................................ 4450
Table 41-188. MPU_RBAR_A1 Register Field Descriptions..................................................................................................4454
Table 41-189. MPU_RASR_A1 Register Field Descriptions..................................................................................................4455
Table 41-190. MPU_RBAR_A2 Register Field Descriptions..................................................................................................4459
Table 41-191. MPU_RASR_A2 Register Field Descriptions..................................................................................................4460
Table 41-192. MPU_RBAR_A3 Register Field Descriptions..................................................................................................4464
Table 41-193. MPU_RASR_A3 Register Field Descriptions..................................................................................................4465
Table 41-194. CM_WD_REGS Registers.............................................................................................................................. 4469
Table 41-195. CM_WD_REGS Access Type Codes............................................................................................................. 4469
Table 41-196. SCSR Register Field Descriptions.................................................................................................................. 4470
Table 41-197. WDCNTR Register Field Descriptions............................................................................................................ 4471
Table 41-198. WDKEY Register Field Descriptions...............................................................................................................4472
Table 41-199. WDCR Register Field Descriptions.................................................................................................................4473
Table 41-200. WDWCR Register Field Descriptions............................................................................................................. 4475
Table 42-1. AES Subsystem Interrupt Status........................................................................................................................ 4480
Table 42-2. Key-Block-Round Combinations......................................................................................................................... 4481
Table 42-3. Interrupts and Events..........................................................................................................................................4492
Table 42-4. AES Base Address Table (CM)...........................................................................................................................4499
Table 42-5. AES_SS_REGS Registers..................................................................................................................................4500
Table 42-6. AES_SS_REGS Access Type Codes................................................................................................................. 4500
Table 42-7. AESDMAINTEN Register Field Descriptions...................................................................................................... 4501
Table 42-8. AESDMASTATUS Register Field Descriptions................................................................................................... 4502
Table 42-9. AESDMASTATUSCLR Register Field Descriptions............................................................................................ 4503
Table 42-10. AES_REGS Registers...................................................................................................................................... 4504
Table 42-11. AES_REGS Access Type Codes...................................................................................................................... 4505
Table 42-12. AES_KEY2_6 Register Field Descriptions........................................................................................................4506
Table 42-13. AES_KEY2_7 Register Field Descriptions........................................................................................................4507
Table 42-14. AES_KEY2_4 Register Field Descriptions........................................................................................................4508
Table 42-15. AES_KEY2_5 Register Field Descriptions........................................................................................................4509
Table 42-16. AES_KEY2_2 Register Field Descriptions........................................................................................................4510
Table 42-17. AES_KEY2_3 Register Field Descriptions........................................................................................................ 4511
Table 42-18. AES_KEY2_0 Register Field Descriptions........................................................................................................4512
Table 42-19. AES_KEY2_1 Register Field Descriptions........................................................................................................4513
Table 42-20. AES_KEY1_6 Register Field Descriptions........................................................................................................4514
Table 42-21. AES_KEY1_7 Register Field Descriptions........................................................................................................4515
Table 42-22. AES_KEY1_4 Register Field Descriptions........................................................................................................4516
Table 42-23. AES_KEY1_5 Register Field Descriptions........................................................................................................4517
Table 42-24. AES_KEY1_2 Register Field Descriptions........................................................................................................4518
Table 42-25. AES_KEY1_3 Register Field Descriptions........................................................................................................4519

118 TMS320F2838x Real-Time Microcontrollers With Connectivity Manager SPRUII0E – MAY 2019 – REVISED SEPTEMBER 2023
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Table 42-26. AES_KEY1_0 Register Field Descriptions........................................................................................................4520

Table 42-27. AES_KEY1_1 Register Field Descriptions........................................................................................................4521
Table 42-28. AES_IV_IN_OUT_0 Register Field Descriptions.............................................................................................. 4522
Table 42-29. AES_IV_IN_OUT_1 Register Field Descriptions.............................................................................................. 4523
Table 42-30. AES_IV_IN_OUT_2 Register Field Descriptions.............................................................................................. 4524
Table 42-31. AES_IV_IN_OUT_3 Register Field Descriptions.............................................................................................. 4525
Table 42-32. AES_CTRL Register Field Descriptions........................................................................................................... 4526
Table 42-33. AES_C_LENGTH_0 Register Field Descriptions..............................................................................................4530
Table 42-34. AES_C_LENGTH_1 Register Field Descriptions..............................................................................................4531
Table 42-35. AES_AUTH_LENGTH Register Field Descriptions.......................................................................................... 4532
Table 42-36. AES_DATA_IN_OUT_0 Register Field Descriptions.........................................................................................4533
Table 42-37. AES_DATA_IN_OUT_1 Register Field Descriptions.........................................................................................4534
Table 42-38. AES_DATA_IN_OUT_2 Register Field Descriptions.........................................................................................4535
Table 42-39. AES_DATA_IN_OUT_3 Register Field Descriptions.........................................................................................4536
Table 42-40. AES_TAG_OUT_0 Register Field Descriptions................................................................................................ 4537
Table 42-41. AES_TAG_OUT_1 Register Field Descriptions................................................................................................ 4538
Table 42-42. AES_TAG_OUT_2 Register Field Descriptions................................................................................................ 4539
Table 42-43. AES_TAG_OUT_3 Register Field Descriptions................................................................................................ 4540
Table 42-44. AES_REV Register Field Descriptions............................................................................................................. 4541
Table 42-45. AES_SYSCONFIG Register Field Descriptions................................................................................................4542
Table 42-46. AES_SYSSTATUS Register Field Descriptions................................................................................................ 4544
Table 42-47. AES_IRQSTATUS Register Field Descriptions.................................................................................................4545
Table 42-48. AES_IRQENABLE Register Field Descriptions................................................................................................ 4546
Table 42-49. AES_DIRTY_BITS Register Field Descriptions................................................................................................ 4547
Table 43-1. MII Interface Signals........................................................................................................................................... 4552
Table 43-2. RMII Interface Signals.........................................................................................................................................4553
Table 43-3. RevMII Interface Signals.....................................................................................................................................4555
Table 43-4. Pulse Per Second Signals.................................................................................................................................. 4556
Table 43-5. Auxiliary Trigger Sources.................................................................................................................................... 4559
Table 43-6. Fixed Priority Scheme for DMA Channels.......................................................................................................... 4562
Table 43-7. Weight for DMA Channels...................................................................................................................................4562
Table 43-8. Priority Scheme for Tx DMA and Rx DMA.......................................................................................................... 4563
Table 43-9. Ordinary Clock PTM Messages for Snapshot.....................................................................................................4567
Table 43-10. End to End Transparent Clock: PTP Messages for Snapshot.......................................................................... 4567
Table 43-11. Peer to Peer Transparent Clock: PTP Messages for Snapshot........................................................................ 4568
Table 43-12. Minimum PTP Clock Frequency Example........................................................................................................ 4571
Table 43-13. Message Format Defined in IEEE 1588-2008.................................................................................................. 4572
Table 43-14. IPv4-UDP PTP Packet Fields Required for Control and Status........................................................................4573
Table 43-15. IPv6-UDP PTP Packet Fields Required for Control and Status........................................................................4574
Table 43-16. PTP Packets Over Ethernet..............................................................................................................................4575
Table 43-17. Timestamp Snapshot Dependency on Register Bits.........................................................................................4576
Table 43-18. Destination Address Filtering............................................................................................................................ 4582
Table 43-19. Source Address Filtering...................................................................................................................................4583
Table 43-20. OTS and ITS Bit Values with At Least 1 Perfect Filter Enabled........................................................................ 4586
Table 43-21. OTS and ITS Bit Values with Only VLAN Hash Filter Enabled......................................................................... 4586
Table 43-22. Double VLAN Processing Features in Transmit Path....................................................................................... 4588
Table 43-23. Receive Path.....................................................................................................................................................4589
Table 43-24. VLAN Insertion or Replacement Based on VLTI Bit..........................................................................................4590
Table 43-25. Transmit Checksum Offload Engine Functions for Different Packet Types.......................................................4592
Table 43-26. Receive Checksum Offload Engine Functions for Different Packet Types....................................................... 4593
Table 43-27. TSO: TCP and IP Header Fields.......................................................................................................................4596
Table 43-28. Segmentation Versus Fragmentation................................................................................................................4597
Table 43-29. RevMII Register Maps - MAC........................................................................................................................... 4607
Table 43-30. RevMII Register Map - Remote MAC............................................................................................................... 4607
Table 43-31. MAC_RevMII_PHY_Control Register............................................................................................................... 4608
Table 43-32. MAC_RevMII_PHY_Control Register Description............................................................................................ 4608
Table 43-33. MAC_RevMII_Common_Status Register......................................................................................................... 4609
Table 43-34. MAC_RevMII_Common_Status Register Description...................................................................................... 4609
Table 43-35. MAC_RevMII_Common_Ext_Status Register.................................................................................................. 4610
Table 43-36. MAC_RevMII_Common_Ext_Status Register Description............................................................................... 4610
Table 43-37. MAC_RevMII_Interrupt_Status_Mask Register................................................................................................ 4611

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Table 43-38. MAC_RevMII_Interrupt_Status_Mask Register Description............................................................................. 4611

Table 43-39. MAC_RevMII_Remote_PHY_Status Register.................................................................................................. 4611
Table 43-40. MAC_RevMII_Remote_PHY_Status Register Description............................................................................... 4611
Table 43-41. MAC_RevMII_PHY_Status Register.................................................................................................................4612
Table 43-42. MAC_RevMII_PHY_Status Register Description..............................................................................................4612
Table 43-43. TDES0 Normal Descriptor (Read Format) Description..................................................................................... 4615
Table 43-44. TDES1 Normal Descriptor (Read Format) Description..................................................................................... 4615
Table 43-45. TDES2 Normal Descriptor (Read Format) Description..................................................................................... 4616
Table 43-46. TDES2 Normal Descriptor (Read Format) Description..................................................................................... 4616
Table 43-47. TDES3 Normal Descriptor (Read Format)........................................................................................................ 4617
Table 43-48. TDES3 Normal Descriptor (Read Format) Description..................................................................................... 4617
Table 43-49. TDES0 Normal Descriptor (Write-Back Format) Description............................................................................ 4620
Table 43-50. TDES1 Normal Descriptor (Write-Back Format) Description............................................................................ 4620
Table 43-51. TDES2 Normal Descriptor (Write-Back Format) Description............................................................................ 4621
Table 43-52. TDES3 Normal Descriptor Layout (Write-Back Format)................................................................................... 4621
Table 43-53. TDES3 Normal Descriptor (Write-Back Format) Description............................................................................ 4621
Table 43-54. TDES0 Context Descriptor Description.............................................................................................................4624
Table 43-55. TDES1 Context Descriptor Description.............................................................................................................4624
Table 43-56. TDES2 Context Descriptor Description.............................................................................................................4625
Table 43-57. TDES3 Context Descriptor Layout....................................................................................................................4625
Table 43-58. TDES3 Context Descriptor Description.............................................................................................................4625
Table 43-59. RDES0 Normal Descriptor (Read Format) Description.....................................................................................4628
Table 43-60. RDES1 Normal Descriptor (Read Format) Description.....................................................................................4628
Table 43-61. RDES2 Normal Descriptor (Read Format) Description.....................................................................................4628
Table 43-62. RDES3 Normal Descriptor................................................................................................................................ 4629
Table 43-63. RDES3 Normal Descriptor (Read Format) Description.....................................................................................4629
Table 43-64. RDES0 Normal Descriptor (Write-Back Format) Description............................................................................4630
Table 43-65. RDES1 Normal Descriptor (Write-Back Format)...............................................................................................4631
Table 43-66. RDES1 Normal Descriptor (Write-Back Format) Description............................................................................4631
Table 43-67. RDES2 Normal Descriptor (Write-Back Format)...............................................................................................4633
Table 43-68. RDES2 Normal Descriptor (Write-Back Format) Description............................................................................4633
Table 43-69. RDES3 Normal Descriptor (Write-Back Format)...............................................................................................4635
Table 43-70. RDES3 Normal Descriptor (Write-Back Format) Description............................................................................4635
Table 43-71. RDES0 Context Descriptor............................................................................................................................... 4637
Table 43-72. RDES1 Context Descriptor............................................................................................................................... 4637
Table 43-73. RDES2 Context Descriptor............................................................................................................................... 4637
Table 43-74. RDES3 Context Descriptor............................................................................................................................... 4638
Table 43-75. RDES3 Context Descriptor Description............................................................................................................ 4638
Table 43-76. EMAC Base Address Table (CM)......................................................................................................................4654
Table 43-77. ETHERNETSS_REGS Registers..................................................................................................................... 4655
Table 43-78. ETHERNETSS_REGS Access Type Codes.....................................................................................................4655
Table 43-79. ETHERNETSS_IPREVNUM Register Field Descriptions.................................................................................4657
Table 43-80. ETHERNETSS_CTRLSTS Register Field Descriptions................................................................................... 4658
Table 43-81. ETHERNETSS_PTPTSTRIGSEL0 Register Field Descriptions.......................................................................4660
Table 43-82. ETHERNETSS_PTPTSTRIGSEL1 Register Field Descriptions.......................................................................4661
Table 43-83. ETHERNETSS_PTPTSSWTRIG0 Register Field Descriptions........................................................................4662
Table 43-84. ETHERNETSS_PTPTSSWTRIG1 Register Field Descriptions........................................................................4663
Table 43-85. ETHERNETSS_PTPPPSR0 Register Field Descriptions................................................................................. 4664
Table 43-86. ETHERNETSS_PTPPPSR1 Register Field Descriptions................................................................................. 4665
Table 43-87. ETHERNETSS_PTP_TSRL Register Field Descriptions..................................................................................4666
Table 43-88. ETHERNETSS_PTP_TSRH Register Field Descriptions................................................................................. 4667
Table 43-89. ETHERNETSS_PTP_TSWL Register Field Descriptions.................................................................................4668
Table 43-90. ETHERNETSS_PTP_TSWH Register Field Descriptions................................................................................ 4669
Table 43-91. ETHERNETSS_REVMII_CTRL Register Field Descriptions............................................................................ 4670
Table 43-92. EMAC_REGS Registers................................................................................................................................... 4671
Table 43-93. EMAC_REGS Access Type Codes...................................................................................................................4696
Table 43-94. MAC_Configuration Register Field Descriptions...............................................................................................4697
Table 43-95. MAC_Ext_Configuration Register Field Descriptions....................................................................................... 4703
Table 43-96. MAC_Packet_Filter Register Field Descriptions............................................................................................... 4705
Table 43-97. MAC_Watchdog_Timeout Register Field Descriptions..................................................................................... 4708
Table 43-98. MAC_Hash_Table_Reg0 Register Field Descriptions...................................................................................... 4709

120 TMS320F2838x Real-Time Microcontrollers With Connectivity Manager SPRUII0E – MAY 2019 – REVISED SEPTEMBER 2023
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Table 43-99. MAC_Hash_Table_Reg1 Register Field Descriptions...................................................................................... 4710

Table 43-100. MAC_VLAN_Tag_Ctrl Register Field Descriptions..........................................................................................4711
Table 43-101. MAC_VLAN_Tag_Data Register Field Descriptions....................................................................................... 4713
Table 43-102. MAC_VLAN_Hash_Table Register Field Descriptions....................................................................................4715
Table 43-103. MAC_VLAN_Incl Register Field Descriptions................................................................................................. 4716
Table 43-104. MAC_Inner_VLAN_Incl Register Field Descriptions.......................................................................................4718
Table 43-105. MAC_Q0_Tx_Flow_Ctrl Register Field Descriptions...................................................................................... 4720
Table 43-106. MAC_Rx_Flow_Ctrl Register Field Descriptions............................................................................................ 4722
Table 43-107. MAC_RxQ_Ctrl4 Register Field Descriptions................................................................................................. 4723
Table 43-108. MAC_RxQ_Ctrl0 Register Field Descriptions................................................................................................. 4725
Table 43-109. MAC_RxQ_Ctrl1 Register Field Descriptions................................................................................................. 4726
Table 43-110. MAC_RxQ_Ctrl2 Register Field Descriptions..................................................................................................4728
Table 43-111. MAC_Interrupt_Status Register Field Descriptions......................................................................................... 4729
Table 43-112. MAC_Interrupt_Enable Register Field Descriptions........................................................................................4732
Table 43-113. MAC_Rx_Tx_Status Register Field Descriptions............................................................................................4734
Table 43-114. MAC_PMT_Control_Status Register Field Descriptions................................................................................. 4736
Table 43-115. MAC_RWK_Packet_Filter Register Field Descriptions................................................................................... 4740
Table 43-116. MAC_LPI_Control_Status Register Field Descriptions................................................................................... 4741
Table 43-117. MAC_LPI_Timers_Control Register Field Descriptions.................................................................................. 4744
Table 43-118. MAC_LPI_Entry_Timer Register Field Descriptions....................................................................................... 4745
Table 43-119. MAC_1US_Tic_Counter Register Field Descriptions......................................................................................4746
Table 43-120. MAC_Version Register Field Descriptions...................................................................................................... 4747
Table 43-121. MAC_Debug Register Field Descriptions....................................................................................................... 4748
Table 43-122. MAC_HW_Feature0 Register Field Descriptions............................................................................................4749
Table 43-123. MAC_HW_Feature1 Register Field Descriptions............................................................................................4752
Table 43-124. MAC_HW_Feature2 Register Field Descriptions............................................................................................4755
Table 43-125. MAC_HW_Feature3 Register Field Descriptions............................................................................................4757
Table 43-126. MAC_MDIO_Address Register Field Descriptions......................................................................................... 4759
Table 43-127. MAC_MDIO_Data Register Field Descriptions............................................................................................... 4762
Table 43-128. MAC_ARP_Address Register Field Descriptions........................................................................................... 4763
Table 43-129. MAC_CSR_SW_Ctrl Register Field Descriptions........................................................................................... 4764
Table 43-130. MAC_Ext_Cfg1 Register Field Descriptions................................................................................................... 4765
Table 43-131. MAC_Address0_High Register Field Descriptions......................................................................................... 4766
Table 43-132. MAC_Address0_Low Register Field Descriptions.......................................................................................... 4767
Table 43-133. MAC_Address1_High Register Field Descriptions......................................................................................... 4768
Table 43-134. MAC_Address1_Low Register Field Descriptions.......................................................................................... 4769
Table 43-135. MAC_Address2_High Register Field Descriptions......................................................................................... 4770
Table 43-136. MAC_Address2_Low Register Field Descriptions.......................................................................................... 4771
Table 43-137. MAC_Address3_High Register Field Descriptions......................................................................................... 4772
Table 43-138. MAC_Address3_Low Register Field Descriptions.......................................................................................... 4773
Table 43-139. MAC_Address4_High Register Field Descriptions......................................................................................... 4774
Table 43-140. MAC_Address4_Low Register Field Descriptions.......................................................................................... 4775
Table 43-141. MAC_Address5_High Register Field Descriptions......................................................................................... 4776
Table 43-142. MAC_Address5_Low Register Field Descriptions.......................................................................................... 4777
Table 43-143. MAC_Address6_High Register Field Descriptions......................................................................................... 4778
Table 43-144. MAC_Address6_Low Register Field Descriptions.......................................................................................... 4779
Table 43-145. MAC_Address7_High Register Field Descriptions......................................................................................... 4780
Table 43-146. MAC_Address7_Low Register Field Descriptions.......................................................................................... 4781
Table 43-147. MMC_Control Register Field Descriptions......................................................................................................4782
Table 43-148. MMC_Rx_Interrupt Register Field Descriptions..............................................................................................4784
Table 43-149. MMC_Tx_Interrupt Register Field Descriptions.............................................................................................. 4790
Table 43-150. MMC_Rx_Interrupt_Mask Register Field Descriptions................................................................................... 4796
Table 43-151. MMC_Tx_Interrupt_Mask Register Field Descriptions................................................................................... 4801
Table 43-152. Tx_Octet_Count_Good_Bad Register Field Descriptions...............................................................................4805
Table 43-153. Tx_Packet_Count_Good_Bad Register Field Descriptions............................................................................ 4806
Table 43-154. Tx_Broadcast_Packets_Good Register Field Descriptions............................................................................ 4807
Table 43-155. Tx_Multicast_Packets_Good Register Field Descriptions.............................................................................. 4808
Table 43-156. Tx_64Octets_Packets_Good_Bad Register Field Descriptions......................................................................4809
Table 43-157. Tx_65To127Octets_Packets_Good_Bad Register Field Descriptions............................................................4810
Table 43-158. Tx_128To255Octets_Packets_Good_Bad Register Field Descriptions.......................................................... 4811
Table 43-159. Tx_256To511Octets_Packets_Good_Bad Register Field Descriptions.......................................................... 4812

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Table 43-160. Tx_512To1023Octets_Packets_Good_Bad Register Field Descriptions........................................................4813

Table 43-161. Tx_1024ToMaxOctets_Packets_Good_Bad Register Field Descriptions....................................................... 4814
Table 43-162. Tx_Unicast_Packets_Good_Bad Register Field Descriptions........................................................................ 4815
Table 43-163. Tx_Multicast_Packets_Good_Bad Register Field Descriptions......................................................................4816
Table 43-164. Tx_Broadcast_Packets_Good_Bad Register Field Descriptions....................................................................4817
Table 43-165. Tx_Underflow_Error_Packets Register Field Descriptions............................................................................. 4818
Table 43-166. Tx_Single_Collision_Good_Packets Register Field Descriptions...................................................................4819
Table 43-167. Tx_Multiple_Collision_Good_Packets Register Field Descriptions................................................................ 4820
Table 43-168. Tx_Deferred_Packets Register Field Descriptions......................................................................................... 4821
Table 43-169. Tx_Late_Collision_Packets Register Field Descriptions.................................................................................4822
Table 43-170. Tx_Excessive_Collision_Packets Register Field Descriptions....................................................................... 4823
Table 43-171. Tx_Carrier_Error_Packets Register Field Descriptions.................................................................................. 4824
Table 43-172. Tx_Octet_Count_Good Register Field Descriptions....................................................................................... 4825
Table 43-173. Tx_Packet_Count_Good Register Field Descriptions.....................................................................................4826
Table 43-174. Tx_Excessive_Deferral_Error Register Field Descriptions............................................................................. 4827
Table 43-175. Tx_Pause_Packets Register Field Descriptions............................................................................................. 4828
Table 43-176. Tx_VLAN_Packets_Good Register Field Descriptions................................................................................... 4829
Table 43-177. Tx_OSize_Packets_Good Register Field Descriptions...................................................................................4830
Table 43-178. Rx_Packets_Count_Good_Bad Register Field Descriptions.......................................................................... 4831
Table 43-179. Rx_Octet_Count_Good_Bad Register Field Descriptions.............................................................................. 4832
Table 43-180. Rx_Octet_Count_Good Register Field Descriptions.......................................................................................4833
Table 43-181. Rx_Broadcast_Packets_Good Register Field Descriptions............................................................................4834
Table 43-182. Rx_Multicast_Packets_Good Register Field Descriptions..............................................................................4835
Table 43-183. Rx_CRC_Error_Packets Register Field Descriptions..................................................................................... 4836
Table 43-184. Rx_Alignment_Error_Packets Register Field Descriptions.............................................................................4837
Table 43-185. Rx_Runt_Error_Packets Register Field Descriptions..................................................................................... 4838
Table 43-186. Rx_Jabber_Error_Packets Register Field Descriptions..................................................................................4839
Table 43-187. Rx_Undersize_Packets_Good Register Field Descriptions............................................................................4840
Table 43-188. Rx_Oversize_Packets_Good Register Field Descriptions..............................................................................4841
Table 43-189. Rx_64Octets_Packets_Good_Bad Register Field Descriptions..................................................................... 4842
Table 43-190. Rx_65To127Octets_Packets_Good_Bad Register Field Descriptions........................................................... 4843
Table 43-191. Rx_128To255Octets_Packets_Good_Bad Register Field Descriptions......................................................... 4844
Table 43-192. Rx_256To511Octets_Packets_Good_Bad Register Field Descriptions..........................................................4845
Table 43-193. Rx_512To1023Octets_Packets_Good_Bad Register Field Descriptions....................................................... 4846
Table 43-194. Rx_1024ToMaxOctets_Packets_Good_Bad Register Field Descriptions.......................................................4847
Table 43-195. Rx_Unicast_Packets_Good Register Field Descriptions................................................................................ 4848
Table 43-196. Rx_Length_Error_Packets Register Field Descriptions..................................................................................4849
Table 43-197. Rx_Out_Of_Range_Type_Packets Register Field Descriptions.....................................................................4850
Table 43-198. Rx_Pause_Packets Register Field Descriptions.............................................................................................4851
Table 43-199. Rx_FIFO_Overflow_Packets Register Field Descriptions.............................................................................. 4852
Table 43-200. Rx_VLAN_Packets_Good_Bad Register Field Descriptions.......................................................................... 4853
Table 43-201. Rx_Watchdog_Error_Packets Register Field Descriptions.............................................................................4854
Table 43-202. Rx_Receive_Error_Packets Register Field Descriptions................................................................................4855
Table 43-203. Rx_Control_Packets_Good Register Field Descriptions................................................................................ 4856
Table 43-204. Tx_LPI_USEC_Cntr Register Field Descriptions............................................................................................4857
Table 43-205. Tx_LPI_Tran_Cntr Register Field Descriptions...............................................................................................4858
Table 43-206. Rx_LPI_USEC_Cntr Register Field Descriptions........................................................................................... 4859
Table 43-207. Rx_LPI_Tran_Cntr Register Field Descriptions.............................................................................................. 4860
Table 43-208. MMC_IPC_Rx_Interrupt_Mask Register Field Descriptions........................................................................... 4861
Table 43-209. MMC_IPC_Rx_Interrupt Register Field Descriptions......................................................................................4865
Table 43-210. RxIPv4_Good_Packets Register Field Descriptions.......................................................................................4870
Table 43-211. RxIPv4_Header_Error_Packets Register Field Descriptions.......................................................................... 4871
Table 43-212. RxIPv4_No_Payload_Packets Register Field Descriptions............................................................................ 4872
Table 43-213. RxIPv4_Fragmented_Packets Register Field Descriptions............................................................................ 4873
Table 43-214. RxIPv4_UDP_Checksum_Disabled_Packets Register Field Descriptions..................................................... 4874
Table 43-215. RxIPv6_Good_Packets Register Field Descriptions.......................................................................................4875
Table 43-216. RxIPv6_Header_Error_Packets Register Field Descriptions..........................................................................4876
Table 43-217. RxIPv6_No_Payload_Packets Register Field Descriptions............................................................................ 4877
Table 43-218. RxUDP_Good_Packets Register Field Descriptions...................................................................................... 4878
Table 43-219. RxUDP_Error_Packets Register Field Descriptions....................................................................................... 4879
Table 43-220. RxTCP_Good_Packets Register Field Descriptions.......................................................................................4880

122 TMS320F2838x Real-Time Microcontrollers With Connectivity Manager SPRUII0E – MAY 2019 – REVISED SEPTEMBER 2023
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Table 43-221. RxTCP_Error_Packets Register Field Descriptions........................................................................................4881

Table 43-222. RxICMP_Good_Packets Register Field Descriptions..................................................................................... 4882
Table 43-223. RxICMP_Error_Packets Register Field Descriptions......................................................................................4883
Table 43-224. RxIPv4_Good_Octets Register Field Descriptions......................................................................................... 4884
Table 43-225. RxIPv4_Header_Error_Octets Register Field Descriptions............................................................................ 4885
Table 43-226. RxIPv4_No_Payload_Octets Register Field Descriptions.............................................................................. 4886
Table 43-227. RxIPv4_Fragmented_Octets Register Field Descriptions...............................................................................4887
Table 43-228. RxIPv4_UDP_Checksum_Disable_Octets Register Field Descriptions......................................................... 4888
Table 43-229. RxIPv6_Good_Octets Register Field Descriptions......................................................................................... 4889
Table 43-230. RxIPv6_Header_Error_Octets Register Field Descriptions............................................................................ 4890
Table 43-231. RxIPv6_No_Payload_Octets Register Field Descriptions.............................................................................. 4891
Table 43-232. RxUDP_Good_Octets Register Field Descriptions.........................................................................................4892
Table 43-233. RxUDP_Error_Octets Register Field Descriptions..........................................................................................4893
Table 43-234. RxTCP_Good_Octets Register Field Descriptions......................................................................................... 4894
Table 43-235. RxTCP_Error_Octets Register Field Descriptions.......................................................................................... 4895
Table 43-236. RxICMP_Good_Octets Register Field Descriptions....................................................................................... 4896
Table 43-237. RxICMP_Error_Octets Register Field Descriptions........................................................................................ 4897
Table 43-238. MAC_L3_L4_Control0 Register Field Descriptions........................................................................................ 4898
Table 43-239. MAC_Layer4_Address0 Register Field Descriptions......................................................................................4901
Table 43-240. MAC_Layer3_Addr0_Reg0 Register Field Descriptions.................................................................................4902
Table 43-241. MAC_Layer3_Addr1_Reg0 Register Field Descriptions.................................................................................4903
Table 43-242. MAC_Layer3_Addr2_Reg0 Register Field Descriptions.................................................................................4904
Table 43-243. MAC_Layer3_Addr3_Reg0 Register Field Descriptions.................................................................................4905
Table 43-244. MAC_L3_L4_Control1 Register Field Descriptions........................................................................................ 4906
Table 43-245. MAC_Layer4_Address1 Register Field Descriptions......................................................................................4909
Table 43-246. MAC_Layer3_Addr0_Reg1 Register Field Descriptions.................................................................................4910
Table 43-247. MAC_Layer3_Addr1_Reg1 Register Field Descriptions................................................................................. 4911
Table 43-248. MAC_Layer3_Addr2_Reg1 Register Field Descriptions.................................................................................4912
Table 43-249. MAC_Layer3_Addr3_Reg1 Register Field Descriptions.................................................................................4913
Table 43-250. MAC_L3_L4_Control2 Register Field Descriptions........................................................................................ 4914
Table 43-251. MAC_Layer4_Address2 Register Field Descriptions......................................................................................4917
Table 43-252. MAC_Layer3_Addr0_Reg2 Register Field Descriptions.................................................................................4918
Table 43-253. MAC_Layer3_Addr1_Reg2 Register Field Descriptions.................................................................................4919
Table 43-254. MAC_Layer3_Addr2_Reg2 Register Field Descriptions.................................................................................4920
Table 43-255. MAC_Layer3_Addr3_Reg2 Register Field Descriptions.................................................................................4921
Table 43-256. MAC_L3_L4_Control3 Register Field Descriptions........................................................................................ 4922
Table 43-257. MAC_Layer4_Address3 Register Field Descriptions......................................................................................4925
Table 43-258. MAC_Layer3_Addr0_Reg3 Register Field Descriptions.................................................................................4926
Table 43-259. MAC_Layer3_Addr1_Reg3 Register Field Descriptions.................................................................................4927
Table 43-260. MAC_Layer3_Addr2_Reg3 Register Field Descriptions.................................................................................4928
Table 43-261. MAC_Layer3_Addr3_Reg3 Register Field Descriptions.................................................................................4929
Table 43-262. MAC_Timestamp_Control Register Field Descriptions...................................................................................4930
Table 43-263. MAC_Sub_Second_Increment Register Field Descriptions........................................................................... 4934
Table 43-264. MAC_System_Time_Seconds Register Field Descriptions............................................................................ 4935
Table 43-265. MAC_System_Time_Nanoseconds Register Field Descriptions.................................................................... 4936
Table 43-266. MAC_System_Time_Seconds_Update Register Field Descriptions...............................................................4937
Table 43-267. MAC_System_Time_Nanoseconds_Update Register Field Descriptions.......................................................4938
Table 43-268. MAC_Timestamp_Addend Register Field Descriptions.................................................................................. 4939
Table 43-269. MAC_System_Time_Higher_Word_Seconds Register Field Descriptions..................................................... 4940
Table 43-270. MAC_Timestamp_Status Register Field Descriptions.................................................................................... 4941
Table 43-271. MAC_Tx_Timestamp_Status_Nanoseconds Register Field Descriptions...................................................... 4944
Table 43-272. MAC_Tx_Timestamp_Status_Seconds Register Field Descriptions.............................................................. 4945
Table 43-273. MAC_Auxiliary_Control Register Field Descriptions.......................................................................................4946
Table 43-274. MAC_Auxiliary_Timestamp_Nanoseconds Register Field Descriptions.........................................................4947
Table 43-275. MAC_Auxiliary_Timestamp_Seconds Register Field Descriptions.................................................................4948
Table 43-276. MAC_Timestamp_Ingress_Asym_Corr Register Field Descriptions...............................................................4949
Table 43-277. MAC_Timestamp_Egress_Asym_Corr Register Field Descriptions............................................................... 4950
Table 43-278. MAC_Timestamp_Ingress_Corr_Nanosecond Register Field Descriptions................................................... 4951
Table 43-279. MAC_Timestamp_Egress_Corr_Nanosecond Register Field Descriptions.................................................... 4952
Table 43-280. MAC_Timestamp_Ingress_Corr_Subnanosec Register Field Descriptions....................................................4953
Table 43-281. MAC_Timestamp_Egress_Corr_Subnanosec Register Field Descriptions.................................................... 4954

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Table 43-282. MAC_PPS_Control Register Field Descriptions............................................................................................. 4955

Table 43-283. MAC_PPS0_Target_Time_Seconds Register Field Descriptions................................................................... 4959
Table 43-284. MAC_PPS0_Target_Time_Nanoseconds Register Field Descriptions........................................................... 4960
Table 43-285. MAC_PPS0_Interval Register Field Descriptions........................................................................................... 4961
Table 43-286. MAC_PPS0_Width Register Field Descriptions..............................................................................................4962
Table 43-287. MAC_PPS1_Target_Time_Seconds Register Field Descriptions................................................................... 4963
Table 43-288. MAC_PPS1_Target_Time_Nanoseconds Register Field Descriptions........................................................... 4964
Table 43-289. MAC_PPS1_Interval Register Field Descriptions........................................................................................... 4965
Table 43-290. MAC_PPS1_Width Register Field Descriptions..............................................................................................4966
Table 43-291. MAC_PTO_Control Register Field Descriptions............................................................................................. 4967
Table 43-292. MAC_Source_Port_Identity0 Register Field Descriptions.............................................................................. 4969
Table 43-293. MAC_Source_Port_Identity1 Register Field Descriptions.............................................................................. 4970
Table 43-294. MAC_Source_Port_Identity2 Register Field Descriptions.............................................................................. 4971
Table 43-295. MAC_Log_Message_Interval Register Field Descriptions..............................................................................4972
Table 43-296. MTL_Operation_Mode Register Field Descriptions........................................................................................ 4973
Table 43-297. MTL_DBG_CTL Register Field Descriptions.................................................................................................. 4975
Table 43-298. MTL_DBG_STS Register Field Descriptions.................................................................................................. 4978
Table 43-299. MTL_FIFO_Debug_Data Register Field Descriptions.................................................................................... 4980
Table 43-300. MTL_Interrupt_Status Register Field Descriptions......................................................................................... 4981
Table 43-301. MTL_RxQ_DMA_Map0 Register Field Descriptions.......................................................................................4983
Table 43-302. MTL_TxQ0_Operation_Mode Register Field Descriptions............................................................................. 4985
Table 43-303. MTL_TxQ0_Underflow Register Field Descriptions........................................................................................4987
Table 43-304. MTL_TxQ0_Debug Register Field Descriptions............................................................................................. 4988
Table 43-305. MTL_TxQ0_ETS_Status Register Field Descriptions.....................................................................................4990
Table 43-306. MTL_TxQ0_Quantum_Weight Register Field Descriptions............................................................................ 4991
Table 43-307. MTL_Q0_Interrupt_Control_Status Register Field Descriptions.....................................................................4992
Table 43-308. MTL_RxQ0_Operation_Mode Register Field Descriptions.............................................................................4994
Table 43-309. MTL_RxQ0_Missed_Packet_Overflow_Cnt Register Field Descriptions....................................................... 4997
Table 43-310. MTL_RxQ0_Debug Register Field Descriptions............................................................................................. 4999
Table 43-311. MTL_RxQ0_Control Register Field Descriptions............................................................................................ 5000
Table 43-312. MTL_TxQ1_Operation_Mode Register Field Descriptions............................................................................. 5001
Table 43-313. MTL_TxQ1_Underflow Register Field Descriptions........................................................................................5003
Table 43-314. MTL_TxQ1_Debug Register Field Descriptions............................................................................................. 5004
Table 43-315. MTL_TxQ1_ETS_Status Register Field Descriptions.....................................................................................5006
Table 43-316. MTL_TxQ1_Quantum_Weight Register Field Descriptions............................................................................ 5007
Table 43-317. MTL_Q1_Interrupt_Control_Status Register Field Descriptions.....................................................................5008
Table 43-318. MTL_RxQ1_Operation_Mode Register Field Descriptions.............................................................................5010
Table 43-319. MTL_RxQ1_Missed_Packet_Overflow_Cnt Register Field Descriptions....................................................... 5013
Table 43-320. MTL_RxQ1_Debug Register Field Descriptions............................................................................................. 5015
Table 43-321. MTL_RxQ1_Control Register Field Descriptions............................................................................................ 5016
Table 43-322. DMA_Mode Register Field Descriptions......................................................................................................... 5017
Table 43-323. DMA_SysBus_Mode Register Field Descriptions...........................................................................................5019
Table 43-324. DMA_Interrupt_Status Register Field Descriptions........................................................................................ 5021
Table 43-325. DMA_Debug_Status0 Register Field Descriptions......................................................................................... 5023
Table 43-326. DMA_CH0_Control Register Field Descriptions............................................................................................. 5025
Table 43-327. DMA_CH0_Tx_Control Register Field Descriptions....................................................................................... 5027
Table 43-328. DMA_CH0_Rx_Control Register Field Descriptions.......................................................................................5029
Table 43-329. DMA_CH0_TxDesc_List_Address Register Field Descriptions......................................................................5031
Table 43-330. DMA_CH0_RxDesc_List_Address Register Field Descriptions..................................................................... 5032
Table 43-331. DMA_CH0_TxDesc_Tail_Pointer Register Field Descriptions........................................................................5033
Table 43-332. DMA_CH0_RxDesc_Tail_Pointer Register Field Descriptions....................................................................... 5034
Table 43-333. DMA_CH0_TxDesc_Ring_Length Register Field Descriptions...................................................................... 5035
Table 43-334. DMA_CH0_RxDesc_Ring_Length Register Field Descriptions......................................................................5036
Table 43-335. DMA_CH0_Interrupt_Enable Register Field Descriptions.............................................................................. 5037
Table 43-336. DMA_CH0_Rx_Interrupt_Watchdog_Timer Register Field Descriptions........................................................ 5039
Table 43-337. DMA_CH0_Current_App_TxDesc Register Field Descriptions...................................................................... 5040
Table 43-338. DMA_CH0_Current_App_RxDesc Register Field Descriptions......................................................................5041
Table 43-339. DMA_CH0_Current_App_TxBuffer Register Field Descriptions..................................................................... 5042
Table 43-340. DMA_CH0_Current_App_RxBuffer Register Field Descriptions.....................................................................5043
Table 43-341. DMA_CH0_Status Register Field Descriptions...............................................................................................5044
Table 43-342. DMA_CH0_Miss_Frame_Cnt Register Field Descriptions............................................................................. 5048

124 TMS320F2838x Real-Time Microcontrollers With Connectivity Manager SPRUII0E – MAY 2019 – REVISED SEPTEMBER 2023
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Table 43-343. DMA_CH0_RX_ERI_Cnt Register Field Descriptions.................................................................................... 5049

Table 43-344. DMA_CH1_Control Register Field Descriptions............................................................................................. 5050
Table 43-345. DMA_CH1_Tx_Control Register Field Descriptions....................................................................................... 5052
Table 43-346. DMA_CH1_Rx_Control Register Field Descriptions.......................................................................................5054
Table 43-347. DMA_CH1_TxDesc_List_Address Register Field Descriptions......................................................................5056
Table 43-348. DMA_CH1_RxDesc_List_Address Register Field Descriptions..................................................................... 5057
Table 43-349. DMA_CH1_TxDesc_Tail_Pointer Register Field Descriptions........................................................................5058
Table 43-350. DMA_CH1_RxDesc_Tail_Pointer Register Field Descriptions....................................................................... 5059
Table 43-351. DMA_CH1_TxDesc_Ring_Length Register Field Descriptions...................................................................... 5060
Table 43-352. DMA_CH1_RxDesc_Ring_Length Register Field Descriptions......................................................................5061
Table 43-353. DMA_CH1_Interrupt_Enable Register Field Descriptions.............................................................................. 5062
Table 43-354. DMA_CH1_Rx_Interrupt_Watchdog_Timer Register Field Descriptions........................................................ 5064
Table 43-355. DMA_CH1_Current_App_TxDesc Register Field Descriptions...................................................................... 5065
Table 43-356. DMA_CH1_Current_App_RxDesc Register Field Descriptions......................................................................5066
Table 43-357. DMA_CH1_Current_App_TxBuffer Register Field Descriptions..................................................................... 5067
Table 43-358. DMA_CH1_Current_App_RxBuffer Register Field Descriptions.....................................................................5068
Table 43-359. DMA_CH1_Status Register Field Descriptions...............................................................................................5069
Table 43-360. DMA_CH1_Miss_Frame_Cnt Register Field Descriptions............................................................................. 5073
Table 43-361. DMA_CH1_RX_ERI_Cnt Register Field Descriptions.................................................................................... 5074
Table 44-1. Fixed Polynomial Data Path Settings..................................................................................................................5077
Table 44-2. Endianness Table................................................................................................................................................5079
Table 44-3. Data Mask Table................................................................................................................................................. 5079
Table 44-4. Bit Reverse Table................................................................................................................................................5080
Table 44-5. GCRC Base Address Table (CM)....................................................................................................................... 5081
Table 44-6. GCRC_REGS Registers..................................................................................................................................... 5082
Table 44-7. GCRC_REGS Access Type Codes.................................................................................................................... 5082
Table 44-8. CRCCTRL Register Field Descriptions...............................................................................................................5083
Table 44-9. CRCPOLY Register Field Descriptions............................................................................................................... 5084
Table 44-10. CRCDATAMASK Register Field Descriptions................................................................................................... 5085
Table 44-11. CRCDATAIN Register Field Descriptions..........................................................................................................5086
Table 44-12. CRCDATAOUT Register Field Descriptions......................................................................................................5087
Table 44-13. CRCDATATRANS Register Field Descriptions................................................................................................. 5088
Table 45-1. MCAN I/O Description.........................................................................................................................................5092
Table 45-2. MCAN Clocks and Resets.................................................................................................................................. 5094
Table 45-3. MCAN Hardware Requests.................................................................................................................................5094
Table 45-4. Steps to Configure MCAN Module......................................................................................................................5097
Table 45-5. CAN FD Frame Description................................................................................................................................ 5098
Table 45-6. DLC Coding in CAN FD...................................................................................................................................... 5099
Table 45-7. Rx Buffer/Rx FIFO Element Size.........................................................................................................................5115
Table 45-8. Example Filter Configuration for Rx Buffers........................................................................................................ 5117
Table 45-9. Possible Configurations for Message Transmission........................................................................................... 5117
Table 45-10. Tx Buffer, Tx FIFO, Tx Queue Element Size.....................................................................................................5118
Table 45-11. Rx Buffer/Rx FIFO Element Field Descriptions................................................................................................. 5123
Table 45-12. Tx Buffer Element Field Descriptions................................................................................................................5125
Table 45-13. Tx Event FIFO Element Field Descriptions.......................................................................................................5127
Table 45-14. Standard Message ID Filter Element Field Descriptions.................................................................................. 5129
Table 45-15. Extended Message ID Filter Element Field Descriptions..................................................................................5130
Table 45-16. MCANSS_REGS Registers.............................................................................................................................. 5136
Table 45-17. MCANSS_REGS Access Type Codes..............................................................................................................5136
Table 45-18. MCANSS_PID Register Field Descriptions.......................................................................................................5138
Table 45-19. MCANSS_CTRL Register Field Descriptions................................................................................................... 5139
Table 45-20. MCANSS_STAT Register Field Descriptions.................................................................................................... 5140
Table 45-21. MCANSS_ICS Register Field Descriptions.......................................................................................................5141
Table 45-22. MCANSS_IRS Register Field Descriptions.......................................................................................................5142
Table 45-23. MCANSS_IECS Register Field Descriptions.................................................................................................... 5143
Table 45-24. MCANSS_IE Register Field Descriptions......................................................................................................... 5144
Table 45-25. MCANSS_IES Register Field Descriptions.......................................................................................................5145
Table 45-26. MCANSS_EOI Register Field Descriptions...................................................................................................... 5146
Table 45-27. MCANSS_EXT_TS_PRESCALER Register Field Descriptions....................................................................... 5147
Table 45-28. MCANSS_EXT_TS_UNSERVICED_INTR_CNTR Register Field Descriptions............................................... 5148
Table 45-29. MCAN_REGS Registers................................................................................................................................... 5149

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Table 45-30. MCAN_REGS Access Type Codes.................................................................................................................. 5150

Table 45-31. MCAN_CREL Register Field Descriptions........................................................................................................5151
Table 45-32. MCAN_ENDN Register Field Descriptions....................................................................................................... 5152
Table 45-33. MCAN_DBTP Register Field Descriptions........................................................................................................5153
Table 45-34. MCAN_TEST Register Field Descriptions........................................................................................................ 5155
Table 45-35. MCAN_RWD Register Field Descriptions......................................................................................................... 5156
Table 45-36. MCAN_CCCR Register Field Descriptions....................................................................................................... 5157
Table 45-37. MCAN_NBTP Register Field Descriptions........................................................................................................5160
Table 45-38. MCAN_TSCC Register Field Descriptions........................................................................................................5162
Table 45-39. MCAN_TSCV Register Field Descriptions........................................................................................................5163
Table 45-40. MCAN_TOCC Register Field Descriptions....................................................................................................... 5164
Table 45-41. MCAN_TOCV Register Field Descriptions........................................................................................................5165
Table 45-42. MCAN_ECR Register Field Descriptions..........................................................................................................5166
Table 45-43. MCAN_PSR Register Field Descriptions.......................................................................................................... 5167
Table 45-44. MCAN_TDCR Register Field Descriptions....................................................................................................... 5170
Table 45-45. MCAN_IR Register Field Descriptions..............................................................................................................5171
Table 45-46. MCAN_IE Register Field Descriptions.............................................................................................................. 5174
Table 45-47. MCAN_ILS Register Field Descriptions............................................................................................................ 5176
Table 45-48. MCAN_ILE Register Field Descriptions............................................................................................................ 5179
Table 45-49. MCAN_GFC Register Field Descriptions..........................................................................................................5180
Table 45-50. MCAN_SIDFC Register Field Descriptions.......................................................................................................5181
Table 45-51. MCAN_XIDFC Register Field Descriptions.......................................................................................................5182
Table 45-52. MCAN_XIDAM Register Field Descriptions...................................................................................................... 5183
Table 45-53. MCAN_HPMS Register Field Descriptions....................................................................................................... 5184
Table 45-54. MCAN_NDAT1 Register Field Descriptions...................................................................................................... 5185
Table 45-55. MCAN_NDAT2 Register Field Descriptions...................................................................................................... 5188
Table 45-56. MCAN_RXF0C Register Field Descriptions......................................................................................................5191
Table 45-57. MCAN_RXF0S Register Field Descriptions......................................................................................................5192
Table 45-58. MCAN_RXF0A Register Field Descriptions......................................................................................................5193
Table 45-59. MCAN_RXBC Register Field Descriptions....................................................................................................... 5194
Table 45-60. MCAN_RXF1C Register Field Descriptions......................................................................................................5195
Table 45-61. MCAN_RXF1S Register Field Descriptions......................................................................................................5196
Table 45-62. MCAN_RXF1A Register Field Descriptions......................................................................................................5197
Table 45-63. MCAN_RXESC Register Field Descriptions..................................................................................................... 5198
Table 45-64. MCAN_TXBC Register Field Descriptions........................................................................................................5200
Table 45-65. MCAN_TXFQS Register Field Descriptions..................................................................................................... 5202
Table 45-66. MCAN_TXESC Register Field Descriptions..................................................................................................... 5203
Table 45-67. MCAN_TXBRP Register Field Descriptions..................................................................................................... 5204
Table 45-68. MCAN_TXBAR Register Field Descriptions..................................................................................................... 5207
Table 45-69. MCAN_TXBCR Register Field Descriptions..................................................................................................... 5209
Table 45-70. MCAN_TXBTO Register Field Descriptions......................................................................................................5211
Table 45-71. MCAN_TXBCF Register Field Descriptions......................................................................................................5213
Table 45-72. MCAN_TXBTIE Register Field Descriptions.....................................................................................................5215
Table 45-73. MCAN_TXBCIE Register Field Descriptions.................................................................................................... 5219
Table 45-74. MCAN_TXEFC Register Field Descriptions......................................................................................................5223
Table 45-75. MCAN_TXEFS Register Field Descriptions......................................................................................................5224
Table 45-76. MCAN_TXEFA Register Field Descriptions...................................................................................................... 5225
Table 45-77. MCAN_ERROR_REGS Registers.................................................................................................................... 5226
Table 45-78. MCAN_ERROR_REGS Access Type Codes................................................................................................... 5226
Table 45-79. MCANERR_REV Register Field Descriptions.................................................................................................. 5228
Table 45-80. MCANERR_VECTOR Register Field Descriptions........................................................................................... 5229
Table 45-81. MCANERR_STAT Register Field Descriptions................................................................................................. 5230
Table 45-82. MCANERR_WRAP_REV Register Field Descriptions......................................................................................5231
Table 45-83. MCANERR_CTRL Register Field Descriptions................................................................................................ 5232
Table 45-84. MCANERR_ERR_CTRL1 Register Field Descriptions.....................................................................................5234
Table 45-85. MCANERR_ERR_CTRL2 Register Field Descriptions.....................................................................................5235
Table 45-86. MCANERR_ERR_STAT1 Register Field Descriptions......................................................................................5236
Table 45-87. MCANERR_ERR_STAT2 Register Field Descriptions......................................................................................5238
Table 45-88. MCANERR_ERR_STAT3 Register Field Descriptions......................................................................................5239
Table 45-89. MCANERR_SEC_EOI Register Field Descriptions.......................................................................................... 5240
Table 45-90. MCANERR_SEC_STATUS Register Field Descriptions...................................................................................5241

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Table 45-91. MCANERR_SEC_ENABLE_SET Register Field Descriptions......................................................................... 5242

Table 45-92. MCANERR_SEC_ENABLE_CLR Register Field Descriptions......................................................................... 5243
Table 45-93. MCANERR_DED_EOI Register Field Descriptions.......................................................................................... 5244
Table 45-94. MCANERR_DED_STATUS Register Field Descriptions...................................................................................5245
Table 45-95. MCANERR_DED_ENABLE_SET Register Field Descriptions......................................................................... 5246
Table 45-96. MCANERR_DED_ENABLE_CLR Register Field Descriptions.........................................................................5247
Table 45-97. MCANERR_AGGR_ENABLE_SET Register Field Descriptions...................................................................... 5248
Table 45-98. MCANERR_AGGR_ENABLE_CLR Register Field Descriptions......................................................................5249
Table 45-99. MCANERR_AGGR_STATUS_SET Register Field Descriptions.......................................................................5250
Table 45-100. MCANERR_AGGR_STATUS_CLR Register Field Descriptions.................................................................... 5251
Table 46-1. Examples of I2C Master Timer Period Versus Speed Mode...............................................................................5261
Table 46-2. Examples of I2C Master Timer Period in High-Speed Mode.............................................................................. 5262
Table 46-3. CM I2C Base Address Table (CM)......................................................................................................................5274
Table 46-4. CM_I2C_REGS Registers.................................................................................................................................. 5275
Table 46-5. CM_I2C_REGS Access Type Codes..................................................................................................................5275
Table 46-6. I2CMSA Register Field Descriptions...................................................................................................................5277
Table 46-7. I2CMCS Register Field Descriptions.................................................................................................................. 5278
Table 46-8. I2CMDR Register Field Descriptions.................................................................................................................. 5280
Table 46-9. I2CMTPR Register Field Descriptions................................................................................................................ 5281
Table 46-10. I2CMIMR Register Field Descriptions...............................................................................................................5282
Table 46-11. I2CMRIS Register Field Descriptions................................................................................................................5284
Table 46-12. I2CMMIS Register Field Descriptions............................................................................................................... 5287
Table 46-13. I2CMICR Register Field Descriptions............................................................................................................... 5289
Table 46-14. I2CMCR Register Field Descriptions................................................................................................................ 5291
Table 46-15. I2CMCLKOCNT Register Field Descriptions.................................................................................................... 5292
Table 46-16. I2CMBMON Register Field Descriptions...........................................................................................................5293
Table 46-17. I2CMBLEN Register Field Descriptions............................................................................................................ 5294
Table 46-18. I2CMBCNT Register Field Descriptions............................................................................................................5295
Table 46-19. I2CSOAR Register Field Descriptions.............................................................................................................. 5296
Table 46-20. I2CSCSR Register Field Descriptions.............................................................................................................. 5297
Table 46-21. I2CSDR Register Field Descriptions.................................................................................................................5299
Table 46-22. I2CSIMR Register Field Descriptions............................................................................................................... 5300
Table 46-23. I2CSRIS Register Field Descriptions................................................................................................................ 5302
Table 46-24. I2CSMIS Register Field Descriptions................................................................................................................5304
Table 46-25. I2CSICR Register Field Descriptions................................................................................................................5306
Table 46-26. I2CSOAR2 Register Field Descriptions............................................................................................................ 5308
Table 46-27. I2CSACKCTL Register Field Descriptions........................................................................................................5309
Table 46-28. I2CFIFODATARX Register Field Descriptions.................................................................................................. 5310
Table 46-29. I2CFIFOCTL Register Field Descriptions..........................................................................................................5311
Table 46-30. I2CFIFOSTATUS Register Field Descriptions...................................................................................................5313
Table 46-31. I2CPP Register Field Descriptions....................................................................................................................5315
Table 46-32. I2CPC Register Field Descriptions................................................................................................................... 5316
Table 46-33. CM_I2C_WRITE_REGS Registers...................................................................................................................5317
Table 46-34. CM_I2C_WRITE_REGS Access Type Codes.................................................................................................. 5317
Table 46-35. I2CMCS_WRITE Register Field Descriptions...................................................................................................5318
Table 46-36. I2CSCSR_WRITE Register Field Descriptions.................................................................................................5320
Table 46-37. I2CFIFODATATX Register Field Descriptions...................................................................................................5321
Table 47-1. SSInFss Functionality......................................................................................................................................... 5327
Table 47-2. SSI Base Address Table (CM)............................................................................................................................ 5335
Table 47-3. SSI_REGS Registers..........................................................................................................................................5336
Table 47-4. SSI_REGS Access Type Codes......................................................................................................................... 5336
Table 47-5. SSICR0 Register Field Descriptions................................................................................................................... 5338
Table 47-6. SSICR1 Register Field Descriptions................................................................................................................... 5340
Table 47-7. SSIDR Register Field Descriptions..................................................................................................................... 5342
Table 47-8. SSISR Register Field Descriptions..................................................................................................................... 5343
Table 47-9. SSICPSR Register Field Descriptions................................................................................................................ 5344
Table 47-10. SSIIM Register Field Descriptions.................................................................................................................... 5345
Table 47-11. SSIRIS Register Field Descriptions...................................................................................................................5347
Table 47-12. SSIMIS Register Field Descriptions..................................................................................................................5349
Table 47-13. SSIICR Register Field Descriptions.................................................................................................................. 5351
Table 47-14. SSIDMACTL Register Field Descriptions......................................................................................................... 5352

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Table 47-15. SSIPV Register Field Descriptions................................................................................................................... 5353

Table 47-16. SSIPP Register Field Descriptions................................................................................................................... 5354
Table 47-17. SSIPC Register Field Descriptions................................................................................................................... 5355
Table 47-18. SSIPeriphID4 Register Field Descriptions........................................................................................................ 5356
Table 47-19. SSIPeriphID5 Register Field Descriptions........................................................................................................ 5357
Table 47-20. SSIPeriphID6 Register Field Descriptions........................................................................................................ 5358
Table 47-21. SSIPeriphID7 Register Field Descriptions........................................................................................................ 5359
Table 47-22. SSIPeriphID0 Register Field Descriptions........................................................................................................ 5360
Table 47-23. SSIPeriphID1 Register Field Descriptions........................................................................................................ 5361
Table 47-24. SSIPeriphID2 Register Field Descriptions........................................................................................................ 5362
Table 47-25. SSIPeriphID3 Register Field Descriptions........................................................................................................ 5363
Table 47-26. SSIPCellID0 Register Field Descriptions.......................................................................................................... 5364
Table 47-27. SSIPCellID1 Register Field Descriptions.......................................................................................................... 5365
Table 47-28. SSIPCellID2 Register Field Descriptions.......................................................................................................... 5366
Table 47-29. SSIPCellID3 Register Field Descriptions.......................................................................................................... 5367
Table 48-1. UART Base Address Table (CM)........................................................................................................................ 5379
Table 48-2. UART_REGS Registers...................................................................................................................................... 5380
Table 48-3. UART_REGS Access Type Codes..................................................................................................................... 5380
Table 48-4. UARTDR Register Field Descriptions................................................................................................................. 5382
Table 48-5. UARTRSR Register Field Descriptions...............................................................................................................5384
Table 48-6. UARTFR Register Field Descriptions..................................................................................................................5386
Table 48-7. UARTILPR Register Field Descriptions.............................................................................................................. 5388
Table 48-8. UARTIBRD Register Field Descriptions..............................................................................................................5389
Table 48-9. UARTFBRD Register Field Descriptions.............................................................................................................5390
Table 48-10. UARTLCRH Register Field Descriptions...........................................................................................................5391
Table 48-11. UARTCTL Register Field Descriptions..............................................................................................................5393
Table 48-12. UARTIFLS Register Field Descriptions.............................................................................................................5395
Table 48-13. UARTIM Register Field Descriptions................................................................................................................ 5396
Table 48-14. UARTRIS Register Field Descriptions.............................................................................................................. 5398
Table 48-15. UARTMIS Register Field Descriptions.............................................................................................................. 5400
Table 48-16. UARTICR Register Field Descriptions.............................................................................................................. 5402
Table 48-17. UARTDMACTL Register Field Descriptions......................................................................................................5404
Table 48-18. UART9BITADDR Register Field Descriptions...................................................................................................5405
Table 48-19. UART9BITAMASK Register Field Descriptions................................................................................................ 5406
Table 48-20. UARTPP Register Field Descriptions................................................................................................................5407
Table 48-21. UARTPeriphID4 Register Field Descriptions.................................................................................................... 5408
Table 48-22. UARTPeriphID5 Register Field Descriptions.................................................................................................... 5409
Table 48-23. UARTPeriphID6 Register Field Descriptions.................................................................................................... 5410
Table 48-24. UARTPeriphID7 Register Field Descriptions.....................................................................................................5411
Table 48-25. UARTPeriphID0 Register Field Descriptions.................................................................................................... 5412
Table 48-26. UARTPeriphID1 Register Field Descriptions.................................................................................................... 5413
Table 48-27. UARTPeriphID2 Register Field Descriptions.................................................................................................... 5414
Table 48-28. UARTPeriphID3 Register Field Descriptions.................................................................................................... 5415
Table 48-29. UARTPCellID0 Register Field Descriptions...................................................................................................... 5416
Table 48-30. UARTPCellID1 Register Field Descriptions...................................................................................................... 5417
Table 48-31. UARTPCellID2 Register Field Descriptions...................................................................................................... 5418
Table 48-32. UARTPCellID3 Register Field Descriptions...................................................................................................... 5419
Table 48-33. UART_REGS_WRITE Registers...................................................................................................................... 5420
Table 48-34. UART_REGS_WRITE Access Type Codes......................................................................................................5420
Table 48-35. UARTECR Register Field Descriptions.............................................................................................................5421
Table 49-1. µDMA Channel Assignment Mapping................................................................................................................. 5426
Table 49-2. Request Type Support........................................................................................................................................ 5428
Table 49-3. Control Structure Memory Map...........................................................................................................................5429
Table 49-4. Channel Control Structure.................................................................................................................................. 5429
Table 49-5. µDMA Read Example: 8-Bit Peripheral...............................................................................................................5438
Table 49-6. µDMA Interrupt Assignments.............................................................................................................................. 5439
Table 49-7. Channel Control Structure Offsets for Channel 30..............................................................................................5440
Table 49-8. Channel Control Word Configuration for Memory Transfer Example..................................................................5440
Table 49-9. Channel Control Structure Offsets for Channel 7................................................................................................5441
Table 49-10. Channel Control Word Configuration for Peripheral Transmit Example............................................................5442
Table 49-11. Primary and Alternate Channel Control Structure Offsets for Channel 8.......................................................... 5443

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Table 49-12. Channel Control Word Configuration for Peripheral Ping-Pong Receive Example...........................................5444
Table 49-13. UDMA Base Address Table (CM)..................................................................................................................... 5446
Table 49-14. UDMAREGS Registers..................................................................................................................................... 5447
Table 49-15. UDMAREGS Access Type Codes.................................................................................................................... 5447
Table 49-16. DMASTAT Register Field Descriptions............................................................................................................. 5449
Table 49-17. DMACFG Register Field Descriptions.............................................................................................................. 5450
Table 49-18. DMACTLBASE Register Field Descriptions......................................................................................................5451
Table 49-19. DMAALTBASE Register Field Descriptions...................................................................................................... 5452
Table 49-20. DMASWREQ Register Field Descriptions........................................................................................................ 5453
Table 49-21. DMAUSEBURSTSET Register Field Descriptions........................................................................................... 5454
Table 49-22. DMAUSEBURSTCLR Register Field Descriptions........................................................................................... 5455
Table 49-23. DMAREQMASKSET Register Field Descriptions............................................................................................. 5456
Table 49-24. DMAREQMASKCLR Register Field Descriptions.............................................................................................5457
Table 49-25. DMAENASET Register Field Descriptions........................................................................................................5458
Table 49-26. DMAENACLR Register Field Descriptions....................................................................................................... 5459
Table 49-27. DMAALTSET Register Field Descriptions.........................................................................................................5460
Table 49-28. DMAALTCLR Register Field Descriptions.........................................................................................................5461
Table 49-29. DMAPRIOSET Register Field Descriptions...................................................................................................... 5462
Table 49-30. DMAPRIOCLR Register Field Descriptions...................................................................................................... 5463
Table 49-31. DMAERRCLR Register Field Descriptions....................................................................................................... 5464
Table 49-32. DMACHMAP0 Register Field Descriptions....................................................................................................... 5465
Table 49-33. DMACHMAP1 Register Field Descriptions....................................................................................................... 5466
Table 49-34. DMACHMAP2 Register Field Descriptions....................................................................................................... 5467
Table 49-35. DMACHMAP3 Register Field Descriptions....................................................................................................... 5468
Table 49-36. DMAPeriphID4 Register Field Descriptions...................................................................................................... 5469
Table 49-37. DMAPeriphID0 Register Field Descriptions...................................................................................................... 5470
Table 49-38. DMAPeriphID1 Register Field Descriptions...................................................................................................... 5471
Table 49-39. DMAPeriphID2 Register Field Descriptions...................................................................................................... 5472
Table 49-40. DMAPeriphID3 Register Field Descriptions...................................................................................................... 5473
Table 49-41. DMAPCellID0 Register Field Descriptions........................................................................................................5474
Table 49-42. DMAPCellID1 Register Field Descriptions........................................................................................................5475
Table 49-43. DMAPCellID2 Register Field Descriptions........................................................................................................5476
Table 49-44. DMAPCellID3 Register Field Descriptions........................................................................................................5477
Table 49-45. UDMACHDES Registers...................................................................................................................................5478
Table 49-46. UDMACHDES Access Type Codes.................................................................................................................. 5478
Table 49-47. DMASRCENDP Register Field Descriptions.................................................................................................... 5479
Table 49-48. DMADSTENDP Register Field Descriptions.....................................................................................................5480
Table 49-49. DMACHCTL Register Field Descriptions.......................................................................................................... 5481

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Preface
Read This First

About This Manual

This Technical Reference Manual (TRM) details the integration, the environment, the functional description, and
the programming models for each peripheral and subsystem in the device.
The TRM should not be considered a substitute for the data manual, rather a companion guide that should be
used alongside the device-specific data manual to understand the details to program the device. The primary
purpose of the TRM is to abstract the programming details of the device from the data manual. This allows
the data manual to outline the high-level features of the device without unnecessary information about register
descriptions or programming models.
Notational Conventions
This document uses the following conventions.
• Hexadecimal numbers can be shown with the suffix h or the prefix 0x. For example, the following number is
40 hexadecimal (decimal 64): 40h or 0x40.
• Registers in this document are shown in figures and described in tables.
– Each register figure shows a rectangle divided into fields that represent the fields of the register. Each field
is labeled with its bit name, its beginning and ending bit numbers above, and its read/write properties with
default reset value below. A legend explains the notation used for the properties.
– Reserved bits in a register figure can have one of multiple meanings:
• Not implemented on the device
• Reserved for future device expansion
• Reserved for TI testing
• Reserved configurations of the device that are not supported
– Writing nondefault values to the Reserved bits could cause unexpected behavior and should be avoided.
Glossary
TI Glossary This glossary lists and explains terms, acronyms, and definitions.
Related Documentation From Texas Instruments
For a complete listing of related documentation and development-support tools for these devices, visit the Texas
Instruments website at http://www.ti.com. Additionally, the following documents must be used in conjunction with
this TRM:
• TMS320C28x DSP CPU and Instruction Set Reference Guide
• TMS320C28x Floating Point Unit and Instruction Set Reference Guide

Support Resources
TI E2E™ support forums are an engineer's go-to source for fast, verified answers and design help — straight
from the experts. Search existing answers or ask your own question to get the quick design help you need.
Linked content is provided "AS IS" by the respective contributors. They do not constitute TI specifications and do
not necessarily reflect TI's views; see TI's Terms of Use.

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Trademarks
TI E2E™, C2000™, Code Composer Studio™, and Texas Instruments™ are trademarks of Texas Instruments.
Xilinx™ is a trademark of Advanced Micro Devices, Inc.
USB Specification Revision 2.0™ is a trademark of Compaq Computer Corp.
EtherCAT® and Beckhoff ® are registered trademarks of Beckhoff Automation GmbH.
Arm®, Cortex®, and Arm7® are registered trademarks of Arm Limited (or its subsidiaries).
All trademarks are the property of their respective owners.

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www.ti.com ► C28x SYSTEM RESOURCES

Chapter 1
► C28x SYSTEM RESOURCES

The following chapters describe the C28x Configuration and System Resources.
1.1 Technical Reference Manual Overview
The block diagram for the F2838x device is shown in Figure 1-1. This Technical Reference Manual is organized
into five major sections:
• C28x SYSTEM RESOURCES
These chapters describe the C28x CPU subsystem, C28x Boot ROM, device configuration, and other system
peripherals.

• ANALOG PERIPHERALS
These chapters describe the Analog-to-Digital Converter (ADC), Buffered Digital-to-Analog Converter (DAC),
Comparator Subsystem (CMPSS), and general analog subsystem configuration.

• CONTROL PERIPHERALS
These chapters describe the Enhanced Capture (eCAP), High Resolution Capture (HRCAP), Enhanced
Pulse Width Modulator (ePWM), Enhanced Quadrature Encoder Pulse (eQEP), and Sigma Delta Filter
Module (SDFM) peripherals.

• COMMUNICATION PERIPHERALS
These chapters describe the communication peripherals available to the C28x subsystem such as the I2C,
SCI, FSI, McBSP, PMBUS, and SPI. The CAN, EtherCAT, and USB peripherals are also described in this
section and can be assigned to the CM subsystem.

• CONNECTIVITY MANAGER (CM)

These chapters describe the Connectivity Manager (CM) subsystem as well as the AES, GCRC, CM-I2C,
CM-UART, SSI, and Ethernet peripherals.

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► C28x SYSTEM RESOURCES www.ti.com

C28 CPU1 CPU1 - CM C28 CPU2 Connectivity

IPC Manager (CM) CPU1
FPU64 FPU64 CPU1.CLA
FPU32 MSGRAM0 FPU32 CPU1.DMA
CPU1.CLA1 TMU TMU CPU2.CLA1 Arm Cortex-M4
MSGRAM1
VCRC VCRC CPU2
CPU2.CLA
CPU2.DMA
CPU2 - CM AES
BGCRC BGCRC IPC BGCRC BGCRC CPU Timers CM M4 CODE
CPU Timers CPU Timers GCRC CM M4 SYS
DCC MSGRAM0 NVIC CM µDMA
CPU - CLA ePIE ePIE CPU - CLA NMI WD CM Bus Matrix
MSGRAM MSGRAM1 MSGRAM Windowed WD
ERAD ERAD Ethernet DMA
NMI WD NMI WD
Windowed WD Windowed WD
CPU1 - CPU2 Boot ROM
IPC Secure
CLA ROM Boot ROM Boot ROM CLA ROM Secure ROM Memories
Secure ROM MSGRAM0 Secure ROM shown in Red
Flash (512KB)
MSGRAM1
Flash (512KB) Flash (512KB)
C0-C1 RAM (16KB)

M0-M1 RAM (4KB) M0-M1 RAM (4KB) E0 RAM (16KB)

LS0-LS7 RAM GS0-GS15 RAM LS0-LS7 RAM
(32KB) D0-D1 RAM (8KB) (128KB) D0-D1 RAM (8KB) (32KB) S0-S3 RAM (64KB)

DMA - CLA DMA - CLA

MSGRAM CPU1.DMA CPU2.DMA MSGRAM CM µDMA

CM Bus
Matrix

PF3 PF1 PF9 PF2 PF5 PF6 PF10 PF4 MUX MUX MUX MUX

Result 8x CMPSS 2x I2C 8x FSIRX EMIF1 EMIF2 8x CLB Data 2x CAN 1x USB 1x CAN FD 1x EtherCAT DMA
3x DAC 4x SCI 2x FSITX 169x GPIO (2 Ports) 1x Ethernet
4x ADC
(16-bit / 12-bit) 7x eCAP 2x McBSP INPUT XBAR 1x CM-I2C
(2 Hi-Res) 1x PMBUS OUTPUT XBAR 1x CM-UART
32x ePWM 4x SPI ePWM XBAR 1x SSI
Channels
CLB XBAR
(16 Hi-Res)
CLB INPUT XBAR
3x eQEP
8x SD Filters CLB OUTPUT XBAR

Figure 1-1. F2838x Block Diagram

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www.ti.com C2000™ Microcontrollers Software Support

Chapter 2
C2000™ Microcontrollers Software Support

This chapter discusses the C2000Ware for the C2000™ microcontrollers. The C2000Ware can be downloaded
from: www.ti.com/tool/C2000WARE

2.1 Introduction...............................................................................................................................................................136
2.2 C2000Ware Structure............................................................................................................................................... 136
2.3 Documentation..........................................................................................................................................................136
2.4 Devices...................................................................................................................................................................... 136
2.5 Libraries.................................................................................................................................................................... 136
2.6 Code Composer Studio™ Integrated Development Environment (IDE)..............................................................136
2.7 SysConfig and PinMUX Tool....................................................................................................................................137

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2.1 Introduction
C2000Ware for the C2000™ microcontrollers is a cohesive set of development software and documentation
designed to minimize software development time. From device-specific drivers and libraries to device peripheral
examples, C2000Ware provides a solid foundation to begin development and evaluation of your product.
C2000Ware can be downloaded from: www.ti.com/tool/C2000WARE
2.2 C2000Ware Structure
The C2000Ware software package is organized into the following directory structure as shown in Table 2-1.
Table 2-1. C2000Ware Root Directories
Directory Name Description
boards Contains the hardware design schematics, BOM, Gerber files, and documentation for C2000 controlCARDS.
device_support Contains all device-specific support files, bit field headers and device development user's guides.
docs Contains the C2000Ware package user's guides and the HTML index page of all package documentation.
driverlib Contains the device-specific driver library and driver-based peripheral examples.
libraries Contains the device-specific and core libraries.

2.3 Documentation
Within C2000Ware, there is an extensive amount of development documentation ranging from board design
documentation, to library user's guides, to driver API documentation. The "boards" directory contains all the
hardware design, BOM, Gerber files, and more for controlCARDs. To assist with locating the necessary
documentation, an HTML page is provided that contains a full list of all the documents in the C2000Ware
package. Locate this page in the "docs" directory.
2.4 Devices
C2000Ware contains the necessary software and documentation to jumpstart development for C2000™
microcontrollers. Each device includes device-specific common source files, peripheral example projects, bit
field headers, and if available, a device peripheral driver library. Additionally, documentation is provided for each
device on how to set up a CCS project, as well as give an overview of all the included example projects and
assist with troubleshooting. For devices with a driver library, documentation is also included that details all the
peripheral APIs available.
To learn more about C2000™ microcontrollers, visit: www.ti.com/c2000.
2.5 Libraries
The libraries included in C2000Ware range from fixed-point and floating-point math libraries, to specialized DSP
libraries, as well as calibration libraries. Each library includes documentation and examples, where applicable.
Additionally, the Flash API files and boot ROM source code are located in the "libraries" directory.
2.6 Code Composer Studio™ Integrated Development Environment (IDE)
Code Composer Studio™ is an integrated development environment (IDE) that supports TI's microcontroller and
embedded processors portfolio. The Code Composer Studio™ IDE comprises a suite of tools used to develop
and debug embedded applications. The latest version of Code Composer Studio™ IDE can be obtained at:
www.ti.com/ccstudio
All projects and examples in C2000Ware are built for and tested with the Code Composer Studio™ IDE.
Although the Code Composer Studio™ IDE is not included with the C2000Ware installer, Code Composer
Studio™ IDE is easily obtainable in a variety of versions.

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2.7 SysConfig and PinMUX Tool

To help simplify configuration challenges and accelerate software development, Texas Instruments™ created
SysConfig, an intuitive and comprehensive collection of graphical utilities for configuring pins, peripherals,
subsystems, and other components. SysConfig helps you manage, expose, and resolve conflicts visually so that
you have more time to create differentiated applications.
The tool's output includes C header and code files that can be used with C2000Ware examples or used to
configure custom software.
The SysConfig tool automatically selects the pinmux settings that satisfy the entered requirements. The
SysConfig tool is delivered integrated in the Code Composer Studio™ IDE, in the C2000Ware GPIO example,
as a standalone installer, or can be used by way of the cloud tools portal at: dev.ti.com

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www.ti.com C28x System Control and Interrupts

Chapter 3
C28x System Control and Interrupts

This chapter explains system control and interrupts for the C28x cores found on this MCU. The system control
module configures and manages the overall operation of the device, and provides information about the device
status. Configurable features in system control include reset control, NMI operation, peripheral interrupts, power
control, clock control, and low-power modes.

3.1 C28x System Control Introduction..........................................................................................................................140

3.2 System Control Functional Description................................................................................................................. 141
3.3 Resets........................................................................................................................................................................142
3.4 Peripheral Interrupts................................................................................................................................................ 145
3.5 Exceptions and Non-Maskable Interrupts..............................................................................................................159
3.6 Safety Features.........................................................................................................................................................161
3.7 Clocking.....................................................................................................................................................................163
3.8 Clock Configuration Semaphore.............................................................................................................................176
3.9 32-Bit CPU Timers 0/1/2........................................................................................................................................... 177
3.10 Watchdog Timers....................................................................................................................................................178
3.11 Low Power Modes.................................................................................................................................................. 181
3.12 Memory Controller Module.................................................................................................................................... 182
3.13 JTAG........................................................................................................................................................................ 192
3.14 System Control Register Configuration Restrictions......................................................................................... 193
3.15 Software.................................................................................................................................................................. 194
3.16 System Control Registers......................................................................................................................................200

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3.1 C28x System Control Introduction

On this device, the CPU1 subsystem acts as a master, and by default (upon reset), it owns all the configuration
and control. Through software running on CPU1, peripherals and I/Os can be configured to be accessible by the
CPU2 subsystem or the CM subsystem and the chosen configurations can be locked.
The PLL clock configuration is also owned by the CPU1 subsystem by default, but a clock control semaphore is
provided by which CPU2 can grab access to the clock configuration registers.
Each CPU can be independently configured to accept interrupts from different peripherals. The interrupt path is
divided into three stages – the peripheral, the PIE, and the CPU. All stages must be configured and enabled for
an interrupt to propagate to the CPU.
Each CPU has its own NMI module to handle different exceptions during run time. If the NMI was on CPU1,
any NMI exception that is unhandled before the NMI Watchdog (NMIWD) timer expiration will reset the entire
device. If the NMI was on the CPU2 subsystem, then the CPU2 subsystem alone will be reset, in which case the
CPU1 subsystem will be informed by another NMI that the CPU2 subsystem was reset because of NMIWD timer
expiration.
Each CPU subsystem has its own watchdog timer module for software to use. Watchdog timer expiration on
CPU2 will reset the CPU2 subsystem alone when configured to generate a reset, but watchdog timer expiration
on CPU1 will reset the entire device.
Except for a CPU2 standalone internal reset such as CPU2.NMIWD or CPU2.WD each time the device is reset,
the CPU2 subsystem will be held under reset until the CPU1 subsystem brings it out of reset. This is done by the
boot ROM software running on the CPU1 core.
The register space of the device system control module can be found in Section 3.16.
This chapter explains the system control module on both the CPU subsystems.
3.1.1 SYSCTL Related Collateral

Foundational Materials
• C2000 MCU JTAG Connectivity Debug Application Report

Getting Started Materials

• C28x Interrupt Nesting
• Debugging JTAG
• Enhancing Device Security by Using JTAGLOCK Feature Application Report
• XDS Target Connection Guide

Expert Materials
• C2000 CPU Memory Built-In Self-Test Application Report
• C2000 Memory Power-On Self-Test (M-POST) Application Report
• Programming of External Nonvolatile Memory Using SDFlash for TMS320C28x Devices Application Report
• Software Phased-Locked Loop (PLL) Design Using C2000 Microcontrollers Application Report

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3.2 System Control Functional Description

The system control module provides the following capabilities:
• Device identification and configuration registers
• Reset control
• Exceptions and Interrupt control
• Safety and error handling features of the device
• Power control
• Clock control
• Low Power modes
• Security module
• Inter-Processor Communication (IPC)

3.2.1 Device Identification

Device identification registers provide information on device class, device family, revision, part number, pin
count, and device qualification status.
All of the device information is part of the DEV_CFG_REGS space and is accessible only by the software
running on the CPU1 subsystem.
The C28x device identification registers are: PARTIDL, PARTIDH, and REVID.
A 256-bit Unique ID (UID) is available in UID_REGS. The 256 bits are separated into these registers:
• UID_PSRAND0-5: 192 bits of pseudo-random data
• UID_UNIQUE: 32-bit unique data; the value in this register will be unique across all devices with the same
PARTIDH
• UID_CHECKSUM: 32-bit fletcher checksum of UID_PSRAND0-5 and UID_UNIQUE and calculated as either
little- or big-endian during factory testing
• CPU ID: 16-bit location in OTP. The value at this location provides the information about CPU (CPU1 or
CPU2).
3.2.2 Device Configuration Registers
Several registers provide users with configuration information for the C28x subsystems for debug and
identification purposes. This information includes the features of the peripherals and how much RAM and FLASH
memory is available on this part.
These registers are part of DEV_CFG_REGS space and are accessible only by the software running on the
CPU1 subsystem.
• DC0 – DC27: Device Configuration or Capabilities registers.
If a particular bit in these registers is set to 1, then the associated/feature or module is available in the device.
• PERCNF: Peripheral configuration register.
This register configures ADC capabilities, and enables or disables the USB internal PHY.
• CPUID: CPU identification register.
This register is available for software to identify on which CPU the software is executing.

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3.3 Resets
This section explains the types and effects of the different resets on this device.
3.3.1 Reset Sources
Table 3-1 summarizes the various reset signals and their effect on the device. CM subsystem resets are
described in Section 41.2.
Table 3-1. Reset Signals
Reset Source CPU1 Core CPU1 CPU2 Core CPU2 and CPU2 and JTAG / IOs XRSn
Reset Peripheral Reset CM CM Held In Debug Output
(C28x, Reset (C28x, Peripheral Reset Logic Reset
TMU, FPU, TMU, FPU, Reset
VCRC) VCRC)
POR Yes Yes Yes Yes Yes Yes Hi-Z Yes
XRSn Pin Yes Yes Yes Yes Yes - Hi-Z -
CPU1.SIMRESET.XRSn Yes Yes Yes Yes Yes - Hi-Z Yes
CPU1.WDRS Yes Yes Yes Yes Yes - Hi-Z Yes
CPU1.NMIWDRS Yes Yes Yes Yes Yes - Hi-Z Yes
CPU1.SYSRS Yes Yes Yes Yes Yes - Hi-Z -
(Debugger Reset)
CPU1.SIMRESET.CPU1RSn Yes Yes Yes Yes Yes - Hi-Z -
CPU1.SCCRESET Yes Yes Yes Yes Yes - Hi-Z -
CPU1.HWBISTRS Yes - - - - - - -
CPU2.SYSRS - - Yes Yes - - - -
(Debugger Reset)
CPU2.WDRS - - Yes Yes - - - -
CPU2.NMIWDRS - - Yes Yes - - - -
CPU2.SCCRESET - - Yes Yes - - - -
CPU2.HWBISTRS - - Yes - - - - -
ECAT_RESET_OUT Yes Yes Yes Yes Yes - Hi-Z Yes
TRSTn - - - - - Yes - -

Note
After a reset, the reset cause register (RESC) is updated with the reset cause. The bits in this register
maintain their state across multiple resets. These can only be cleared by a power-on reset (POR) or
by writing 1 to the corresponding bit in RESCCLR register (status can be cleared by writing 1 to RESC
register bits also). Each CPU has a RESC register, referred to as CPU1.RESC and CPU2.RESC.

The resets can be divided into a few groups:

• Chip-level resets (XRSn, POR, CPU1.WDRS, and CPU1.NMIWDRS, SIMRESET.XRSn, ECAT_RESET_OUT
(if enabled) ), which reset all or almost all of the device.
• System resets (CPU1.SYSRS and CPU1.SCCRESET, SIMRESET.CPU1RSn), which reset a large subset of
the device but maintain some system-level configuration.
• CPU2 subsystem resets (CPU2.SYSRS, CPU2.WDRS, CPU2.NMIWDRS, and CPU2.SCCRESET), which
reset only CPU2 and the peripherals owned by it.
• Special resets (CPU1.HWBISTRS, CPU2.HWBISTRS, and TRSTn), which enable specific device functions.
Whenever the CPU1 subsystem is reset, CPU2, CM and the peripherals owned by them also get reset and held
in reset until CPU1 brings CPU2 and CM out of reset by writing to the CPU2RESCTL and CMRESCTL registers
respectively. This is done by user application code on CPU1.
Many peripheral modules have individual resets accessible through the system control registers. For information
about a module's reset state, refer to the appropriate chapter for that module.

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After a POR the boot ROMs clear all of the system and message RAMs on both CPUs.
3.3.2 External Reset (XRSn)
The external reset (XRS) is the main chip-level reset for the device. XRS resets both C28x CPUs , the CM
subsystem, all peripherals and I/O pin configurations, and most of the system control registers. XRS also holds
CPU2 and the CM subsystem in reset. There is a dedicated open-drain pin for XRSn. This pin can be used to
drive reset pins for other ICs in the application, and can be driven by an external source. The XRSn is driven
internally during watchdog, NMI, and power-on resets.
The XRSn bit in the RESC register is set whenever XRS is driven low for any reason. This bit is then cleared by
the boot ROM.
3.3.3 Simulate External Reset
In some cases, there can be a need to simulate the external reset (XRS) in software. This can be done by
setting XRSn bit to 1 in SIMRESET register by CPU1 software. This toggles XRS pin; hence, resets full device
(just like external reset).
After this reset SIMRESET_XRSn bit in the RESC register is set. Software can read this bit to know the cause of
reset and clear the status by writing 1 into corresponding bit in RESCCLR register.
3.3.4 Power-On Reset (POR)
The power-on reset (POR) circuit creates a clean reset throughout the device during power-up, suppressing
glitches on the GPIOs. The XRS pin is held low for the duration of the POR. In most applications, XRS is held
low long enough to reset other system ICs, but some applications may require a longer pulse. In these cases,
XRS can be driven low externally to provide the correct reset duration. A POR resets everything that XRS does,
along with a few other registers – the reset cause register (RESC), the NMI shadow flag register (NMISHDFLG).
After a POR, the POR and XRSn bits in RESC are set. These bits are then cleared by the boot ROM.
3.3.5 Debugger Reset (SYSRS)
During development, it is sometimes necessary to reset the CPU and the peripherals without disconnecting the
debugger or disrupting the system-level configuration. To facilitate this, each CPU has a subsystem reset, which
can be triggered by a debugger using Code Composer Studio IDE. CPU2 subsystem reset (CPU2.SYSRS)
resets only CPU2, the peripherals owned by it, clock gating and LPM configuration. It does not hold CPU2 in
reset. CPU1 subsystem reset (CPU1.SYSRS) resets CPU1, the peripherals owned by it, many system control
registers (including its clock gating and LPM configuration and the peripherals' CPU ownership), and all I/O pin
configurations. It also produces a CPU2.SYSRS and CM.RESETn and holds both, CPU2 and CM, in reset (CCS
Gel file has code to release CPU2 and CM out of reset on CPU1 debug reset).
Neither SYSRS resets the ICEPick debug module, the device capability registers, the clock source and PLL
configurations, the missing clock detection state, the PIE vector fetch error handler address, the NMI flags, the
analog trims, or anything reset only by a POR (see Section 3.3.4).
3.3.6 Simulate CPU1 Reset
In some cases, there can be a need to simulate the CPU1 reset (CPU1.SYSRS) in software. This can be done
by setting CPU1RSn bit to 1 in SIMRESET register by CPU1 software. This toggles CPU1.SYSRS signals;
hence, resetting CPU1 as well as CPU2 and CM subsystem (just like the debugger reset).
After this reset SIMRESET_CPU1RSn bit in the RESC register is set. Software can read this bit to know the
cause of reset and clear the status by writing 1 into corresponding bit in RESCCLR register.

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3.3.7 Watchdog Reset (WDRS)

Each CPU has a watchdog timer that can optionally trigger a reset that lasts for 512 INTOSC1 cycles.
CPU1 watchdog reset (CPU1.WDRS) produces an XRS. CPU2 watchdog reset (CPU2.WDRS) produces a
CPU2.SYSRS and triggers an NMI on CPU1.
After a watchdog reset, the WDRSn bit in RESC is set. Software can read this bit to know the cause of reset and
clear the status by writing 1 into corresponding bit in RESCCLR register.
3.3.8 NMI Watchdog Reset (NMIWDRS)
Each CPU has a non-maskable interrupt (NMI) module that detects hardware errors in the system. Each NMI
module has a watchdog timer that triggers a reset if the CPU does not respond to an error within a user-specified
amount of time. CPU1 NMI watchdog reset (CPU1.NMIWDRS) produces an XRS. CPU2 NMI watchdog reset
(CPU2.NMIWDRS) produces a CPU2.SYSRS and triggers an NMI on CPU1.
After an NMI watchdog reset, the NMIWDRSn bit in RESC is set.
3.3.9 Secure Code Copy Reset (SCCRESET)
Dual-zone Code Security Module (DCSM) on this device locks read access to secure memories of each CPU
subsystem. To facilitate CRC checks and copying of CLA code, TI provides ROM functions to securely access
those memory areas. To prevent security breaches, interrupts must be disabled before calling these functions.
If a vector fetch occurs in a secure copy or CRC function, the DCSM triggers a reset. CPU1'security reset
(CPU1.SCCRESET) is similar to a CPU1.SYSRS, and CPU2 security reset (CPU2.SCCRESET) is similar to a
CPU2.SYSRS. However, the security reset also resets the debug logic to deny access to a potential attacker.
After a security reset, the SCCRESETn bit in RESC is set. Software can read this bit to know the cause of reset
and clear the status by writing 1 into corresponding bit in RESCCLR register.
3.3.10 ESC Reset Output
The user can configure the EtherCAT Slave Controller (ESC) module to drive the XRSn pin low whenever
the ESC module receives a reset. This is done by setting the DEVICE_RESET_EN bit to 1 in the
ECAT_RESET_DEST_CONFIG register of the ESC module (EtherCAT subsystem). By default this is not
enabled. Since this toggles the XRSn pin, all effects of an external XRSn reset take effect.
After an ECAT_RESET_OUT reset, the ECAT_RESET_OUT bit in RESC is set. Software can read this bit to
know the cause of reset and clear the status by writing 1 into corresponding bit in RESCCLR register.
3.3.11 Test Reset (TRST)
The ICEPick debug module and associated JTAG logic has a reset (TRST) that is controlled by a dedicated pin.
This reset is normally active unless the user connects a debugger to the device. For more information on the
debug module, see the TI Processors Wiki page on ICEPick: http://processors.wiki.ti.com/index.php/ICEPICK.
The TRST does not have a normal RESC bit, but the TRSTn_pin_status bit indicates the state of the pin.

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3.4 Peripheral Interrupts

This section explains the peripheral interrupt handling on the device. Non-maskable interrupts are covered in
Section 3.5. Software interrupts and emulation interrupts are not covered in this document. For information on
those, see the TMS320C28x CPU and Instruction Set Reference Guide.
3.4.1 Interrupt Concepts
An interrupt is a signal that causes the CPU to pause its current execution and branch to a different piece of
code known as an interrupt service routine (ISR). This is a useful mechanism for handling peripheral events,
and involves less CPU overhead or program complexity than register polling. However, because interrupts are
asynchronous to the program flow, care must be taken to avoid conflicts over resources that are accessed both
in interrupts and in the main program code.
Interrupts propagate to the CPU through a series of flag and enable registers. The flag registers store the
interrupt until it is processed. The enable registers block the propagation of the interrupt. When an interrupt
signal reaches the CPU, the CPU fetches the appropriate ISR address from a list called the vector table.
3.4.2 Interrupt Architecture
The C28x CPU has fourteen peripheral interrupt lines. Two of them (INT13 and INT14) are connected directly
to CPU timers 1 and 2, respectively. The remaining twelve are connected to peripheral interrupt signals through
the enhanced Peripheral Interrupt Expansion module (ePIE, or PIE as a shortened version). The PIE multiplexes
up to sixteen peripheral interrupts into each CPU interrupt line. It also expands the vector table to allow each
interrupt to have its own ISR. This allows the CPU to support a large number of peripherals.
An interrupt path is divided into three stages – the peripheral, the PIE, and the CPU. Each stage has its
own enable and flag registers. This system allows the CPU to handle one interrupt while others are pending,
implement and prioritize nested interrupts in software, and disable interrupts during certain critical tasks.
Figure 3-1 shows the interrupt architecture for this device.

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CM_STATUS

SYS_ERR

CPU1.CRC
CPU1.CLA1.CRC
CPU1.TINT0
CPU1.TIMER0
CPU1.LPMINT CPU1.NMIWD
LPM Logic CPU1.WAKEINT
CPU1.WD NMI
CPU1.WDINT CMNMIWDRSn CPU1
CPU1
ePIE

INPUTXBAR4 CPU1.XINT1 Control INT1

GPIO0
INPUTXBAR5 CPU1.XINT2 Control To
GPIO1 Input INT12
... INPUTXBAR6 CPU1.XINT3 Control
X-Bar
... INPUTXBAR13 CPU1.XINT4 Control
GPIOx
INPUTXBAR14 CPU1.XINT5 Control CPU1.TINT1
CPU1.TIMER1 INT13
CPU1.TINT2
IPC CPU1.TIMER2 INT14
4 CPU-to-CPU
8 CM-to-CPU
Interrupts

Peripherals

CPU2.NMIWD NMI

CPU2
CPU2.XINT1 Control
CPU2.XINT2 Control INT1
To
CPU2.XINT3 Control INT12
CPU2.XINT4 Control
CPU2.XINT5 Control CPU2
ePIE CPU2.TINT1
CPU2.LPMINT CPU2.TIMER1 INT13
LPM Logic CPU2.WAKEINT
CPU2.TINT2
CPU2.WD CPU2.TIMER2 INT14
CPU2.WDINT
CPU2.TINT0
CPU2.TIMER0

CPU2.CRC
CPU2.CLA1.CRC

SYS_ERR

Figure 3-1. Device Interrupt Architecture

3.4.2.1 Peripheral Stage

Each peripheral has its own unique interrupt configuration, which is described in that peripheral's chapter. Some
peripherals allow multiple events to trigger the same interrupt signal. For example, a communications peripheral
might use the same interrupt to indicate that data has been received or that there has been a transmission error.
The cause of the interrupt can be determined by reading the peripheral's status register. Often, the bits in the
status register must be cleared manually before another interrupt will be generated.

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3.4.2.2 PIE Stage

The PIE provides individual flag and enable register bits for each of the peripheral interrupt signals, which are
sometimes called PIE channels. These channels are grouped according to their associated CPU interrupt. Each
PIE group has one 16-bit enable register (PIEIERx), one 16-bit flag register (PIEIFRx), and one bit in the PIE
acknowledge register (PIEACK). The PIEACK register bit acts as a common interrupt mask for the entire PIE
group.
When the CPU receives an interrupt, it fetches the address of the ISR from the PIE. The PIE returns the vector
for the lowest-numbered channel in the group that is both flagged and enabled. This gives lower-numbered
interrupts a higher priority when multiple interrupts are pending.
If no interrupt is both flagged and enabled, the PIE returns the vector for channel 1. This condition will not
happen unless software changes the state of the PIE while an interrupt is propagating. Section 3.4.4 contains
procedures for safely modifying the PIE configuration once interrupts have been enabled.
3.4.2.3 CPU Stage
Like the PIE, the CPU provides flag and enable register bits for each of its interrupts. There is one enable
register (IER) and one flag register (IFR), both of which are internal CPU registers. There is also a global
interrupt mask, which is controlled by the INTM bit in the ST1 register. This mask can be set and cleared using
the CPU's SETC instruction. In C code, C2000Ware's DINT and EINT macros can be used for this purpose.
Writes to IER and INTM are atomic operations. In particular, if INTM is cleared, the next instruction in the
pipeline will run with interrupts disabled. No software delays are needed.
3.4.2.4 Dual-CPU Interrupt Handling
Each CPU has its own PIE. Both PIEs must be configured independently.
Some interrupts come from shared peripherals that can be owned by either CPU, such as the ADCs and SPIs.
These interrupts are sent to both PIEs regardless of the ownership of the peripheral. Thus, a peripheral owned
by one CPU can cause an interrupt on the other CPU, if that interrupt is enabled in the other CPU's PIE.
3.4.3 Interrupt Entry Sequence
Figure 3-2 shows how peripheral interrupts propagate to the CPU.
PIEIERx.1
0
Peripheral
PIEIFRx.1 1
Interrupt
Latch
A

PIEIERx.2
Peripheral 0 Set
PIEIFRx.2 1 PIEACK.x IER.x ST1.INTM
Interrupt
Latch 1 0 1
CPU
B 0 IFR.x 1 0
Interrupt
Latch
Logic

PIEIERx.16
0
Peripheral
PIEIFRx.16 1
Interrupt
Latch
P

Figure 3-2. Interrupt Propagation Path

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When a peripheral generates an interrupt (on PIE group x, channel y), it triggers the following sequence of
events:
1. The interrupt is latched in PIEIFRx.y.
2. If PIEIERx.y is set, the interrupt propagates.
3. If PIEACK.x is clear, the interrupt propagates and PIEACK.x is set.
4. The interrupt is latched in IFR.x.
5. If IER.x is set, the interrupt propagates.
6. If INTM is clear, the CPU receives the interrupt.
7. Any instructions in the D2 or later stage of the pipeline are run to completion. Instructions in earlier stages
are flushed.
8. The CPU saves its context on the stack.
9. IFR.x and IER.x are cleared. INTM is set. EALLOW is cleared.
10. The CPU fetches the ISR vector from the PIE. PIEIFRx.y is cleared.
11. The CPU branches to the ISR.
The interrupt latency is the time between PIEIFRx.y latching the interrupt and the first ISR instruction entering
the execution stage of the CPU pipeline. The minimum interrupt latency is 14 SYSCLK cycles. Wait states on
the ISR or stack memories will add to the latency. External interrupts add a minimum of two SYSCLK cycles
for GPIO synchronization plus extra time for input qualification (if used). Loops created using the C28x RPT
instruction cannot be interrupted.
3.4.4 Configuring and Using Interrupts
At power-up, no interrupts are enabled by default. The PIEIER and IER registers are cleared and INTM is set.
The application code is responsible for configuring and enabling all peripheral interrupts.
3.4.4.1 Enabling Interrupts
To enable a peripheral interrupt, perform the following steps:
1. Disable interrupts globally (DINT or SETC INTM).
2. Enable the PIE by setting the ENPIE bit of the PIECTRL register.
3. Write the ISR vector for each interrupt to the appropriate location in the PIE vector table, which is found in
Table 3-2.
4. Set the appropriate PIEIERx bit for each interrupt. The PIE group and channel assignments are found in
Table 3-2.
5. Set the CPU IER bit for any PIE group containing enabled interrupts.
6. Enable the interrupt in the peripheral.
7. Enable interrupts globally (EINT or CLRC INTM).
Step 4 does not apply to the Timer1 and Timer2 interrupts, which connect directly to the CPU.
3.4.4.2 Handling Interrupts
ISRs are similar to normal functions, but must do the following:
1. Save and restore the state of certain CPU registers (if used).
2. Clear the PIEACK bit for the interrupt group.
3. Return using the IRET instruction.
Requirements 1 and 3 are handled automatically by the TMS320C28x C compiler if the function is defined
using the __interrupt keyword. For information on this keyword, see the Keywords section of the TMS320C28x
Optimizing C/C++ Compiler v6.2.4 User's Guide. For information on writing assembly code to handle interrupts,
see the Standard Operation for Maskable Interrupts section of the TMS320C28x CPU and Instruction Set
Reference Guide.
The PIEACK bit for the interrupt group must be cleared manually in user code. This is normally done at the end
of the ISR. If the PIEACK bit is not cleared, the CPU will not receive any further interrupts from that group. This
does not apply to the Timer1 and Timer2 interrupts, which do not go through the PIE.

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3.4.4.3 Disabling Interrupts

To disable all interrupts, set the CPU's global interrupt mask via DINT or SETC INTM. It is not necessary to add
NOPs after setting INTM or modifying IER – the next instruction will execute with interrupts disabled.
Individual interrupts can be disabled using the PIEIERx registers, but care must be taken to avoid race
conditions. If an interrupt signal is already propagating when the PIEIER write completes, it may reach the
CPU and trigger a spurious interrupt condition. To avoid this, use the following procedure:
1. Disable interrupts globally (DINT or SETC INTM).
2. Clear the PIEIER bit for the interrupt.
3. Wait 5 cycles to make sure that any propagating interrupt has reached the CPU IFR register.
4. Clear the CPU IFR bit for the interrupt's PIE group.
5. Clear the PIEACK bit for the interrupt's PIE group.
6. Enable interrupts globally (EINT or CLRC INTM).
Interrupt groups can be disabled using the CPU IER register. This cannot cause a race condition, so no special
procedure is needed.
PIEIFR bits must never be cleared in software since the read/modify/write operation may cause incoming
interrupts to be lost. The only safe way to clear a PIEIFR bit is to have the CPU take the interrupt. The following
procedure can be used to bypass the normal ISR:
1. Disable interrupts globally (DINT or SETC INTM).
2. Modify the PIE vector table to map the PIEIFR bit's interrupt vector to an empty ISR. This ISR will only
contain a return from interrupt instruction (IRET).
3. Disable the interrupt in the peripheral registers.
4. Enable interrupts globally (EINT or CLRC INTM).
5. Wait for the pending interrupt to be serviced by the empty ISR.
6. Disable interrupts globally.
7. Modify the PIE vector table to map the interrupt vector back to its original ISR.
8. Clear the PIEACK bit for the interrupt's PIE group.
9. Enable interrupts globally.
3.4.4.4 Nesting Interrupts
By default, interrupts do not nest. It is possible to nest and prioritize interrupts via software control of the
IER and PIEIERx registers. Example code can be found in C2000Ware and documentation is available at
software-dl.ti.com/C2000/docs/c28x_interrupt_nesting/html/index.html.

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3.4.5 PIE Channel Mapping

Table 3-2 shows the PIE group and channel assignments for each peripheral interrupt. Each row is a group, and each column is a channel within that
group. When multiple interrupts are pending, the lowest-numbered channel in the lowest-numbered group is serviced first. Thus, the interrupts at the top
of the table have the highest priority, and the interrupts at the bottom have the lowest priority.

Note
Cells marked "-" are Reserved. CPUx is CPU1 for CPU1 PIE and CPU2 for CPU2 PIE.

Table 3-2. PIE Channel Mapping

INTx.1 INTx.2 INTx.3 INTx.4 INTx.5 INTx.6 INTx.7 INTx.8 INTx.9 INTx.10 INTx.11 INTx.12 INTx.13 INTx.14 INTx.15 INTx.16
INT1.y ADCA1 ADCB1 ADCC1 XINT1 XINT2 ADCD1 TIMER0 WAKE/ I2CA SYS_ ECAT ECAT CIPC0 CIPC1 CIPC2 CIPC3
WDINT ERR SYNC0 INTn
(CPU1 only) (CPU1 only)
INT2.y EPWM1_ EPWM2_ EPWM3_ EPWM4_ EPWM5_ EPWM6_ EPWM7_ EPWM8_ EPWM9_ EPWM10_ EPWM11_ EPWM12_ EPWM13_ EPWM14_ EPWM15_ EPWM16_
TZ TZ TZ TZ TZ TZ TZ TZ TZ TZ TZ TZ TZ TZ TZ TZ
INT3.y EPWM1 EPWM2 EPWM3 EPWM4 EPWM5 EPWM6 EPWM7 EPWM8 EPWM9 EPWM10 EPWM11 EPWM12 EPWM13 EPWM14 EPWM15 EPWM16
INT4.y ECAP1 ECAP2 ECAP3 ECAP4 ECAP5 ECAP6 ECAP7 - FSITXA_ FSITXA_ FSITXB_ FSITXB_ FSIRXA_ FSIRXA_ FSIRXB_ FSIRXB_
INT1 INT2 INT1 INT2 INT1 INT2 INT1 INT2
INT5.y EQEP1 EQEP2 EQEP3 - CLB1 CLB2 CLB3 CLB4 SDFM1 SDFM2 ECAT ECAT SDFM1 SDFM1 SDFM1 SDFM1
RSTINTn SYNC1 DR1 DR2 DR3 DR4
(CPU1 only) (CPU1 only)
INT6.y SPIA_RX SPIA_TX SPIB_RX SPIB_TX MCBSPA_ MCBSPA_ MCBSPB_ MCBSPB_ SPIC_RX SPIC_TX SPID_RX SPID_TX SDFM2 SDFM2 SDFM2 SDFM2
RX TX RX TX DR1 DR2 DR3 DR4
INT7.y DMA_CH1 DMA_CH2 DMA_CH3 DMA_CH4 DMA_CH5 DMA_CH6 - - FSIRXC_ FSIRXC_ FSIRXD_ FSIRXD_ FSIRXE_ FSIRXE_ FSIRXF_ FSIRXF_
INT1 INT2 INT1 INT2 INT1 INT2 INT1 INT2
INT8.y I2CA I2CA_ I2CB I2CB_ SCIC_RX SCIC_TX SCID_RX SCID_TX FSIRXG_ FSIRXG_ FSIRXH_ FSIRXH_ CLB5 CLB6 CLB7 CLB8
FIFO FIFO INT1 INT2 INT1 INT2
INT9.y SCIA_RX SCIA_TX SCIB_RX SCIB_TX CANA_0 CANA_1 CANB_0 CANB_1 MCANSS_ MCANSS_ MCANSS_ MCANSS_ PMBUSA CM_ USBA -
INT0 INT1 ECC_ WAKE_ STATUS (CPU1 only)
(CPU1 only) (CPU1 only) CORR_ AND_TS_ (CPU1 only)
PUL_INT PLS_INT
(CPU1 only) (CPU1 only)
INT10.y ADCA_ ADCA2 ADCA3 ADCA4 ADCB_ ADCB2 ADCB3 ADCB4 ADCC_EVT ADCC2 ADCC3 ADCC4 ADCD_EVT ADCD2 ADCD3 ADCD4
EVT EVT
INT11.y CLA1_1 CLA1_2 CLA1_3 CLA1_4 CLA1_5 CLA1_6 CLA1_7 CLA1_8 CMTOCPUx CMTOCPUx CMTOCPUx CMTOCPUx CMTOCPUx CMTOCPUx CMTOCPUx CMTOCPUx
IPCINTR0 IPCINTR1 IPCINTR2 IPCINTR3 IPCINTR4 IPCINTR5 IPCINTR6 IPCINTR7
INT12.y XINT3 XINT4 XINT5 MPOST FMC. VCRC FPU FPU - ECAP6 ECAP7 - CPUxCRC_ CLA1CRC_ CLA CLA
DONE OVER UNDER INT2 INT2 INT INT OVER UNDER
FLOW FLOW FLOW FLOW

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3.4.5.1 PIE Interrupt Priority

3.4.5.1.1 Channel Priority
For every PIE group, the low number channels in the group have the highest priority. For instance in PIE group
1, channel 1.1 has priority over channel 1.3. If those two enabled interrupts occurred simultaneously, channel
1.1 will be serviced first with channel 1.3 left pending. Once the ISR for channel 1.1 completes and provided
there are no other enabled and pending interrupts for PIE group 1, channel 1.3 will be serviced. However, for the
CPU to service any more interrupts from a PIE group, PIEACK for the group must be cleared. For this specific
example, in order for channel 1.3 to be serviced, channel 1.1’s ISR has to clear PIEACK for group 1.
The following example describes an alternative scenario: channel 1.1 is currently being serviced by the CPU,
channel 1.3 is pending and before channel 1.1’s ISR completes, channel 1.2 which is enabled also comes in.
Since channel 1.2 has a higher priority than channel 1.3, the CPU will service channel 1.2 and channel 1.3 will
still be left pending. Using the steps from the Interrupt Entry Sequence (Section 3.4.3), channel 1.2 interrupt can
happen as late as step 10 (The CPU fetches the ISR vector from the PIE. PIEIFRx.y is cleared) and it will still be
serviced ahead of channel 1.3.
3.4.5.1.2 Group Priority
Generally, the lowest channel in the lowest PIE group has the highest priority. An example of this is channels 1.1
and 2.1. Those two channels have the highest priority in their respective groups. If the interrupts for those two
enabled channels happened simultaneously and provided there are no other enabled and pending interrupts,
channel 1.1 will be serviced first by the CPU with channel 2.1 left pending.
However, there are cases where channel priority supersedes group priority. This special case happens
depending on which step the CPU is currently at in the Interrupt Entry Sequence (Section 3.4.3).
The following illustrates an example of this special case.
The CPU is about to service channel 2.3 and is currently going through the steps in the Interrupt Entry Sequence
(Section 3.4.3).
1. As the CPU reaches step 10 (The CPU fetches the ISR vector from the PIE. PIEIFRx.y is cleared), two
enabled interrupts: channel 1.1 and channel 2.1 come in.
2. Due to channel priority, channel 2.1 will be serviced ahead of channel 2.3. However, group priority dictates
that channel 1.1 be serviced ahead of channels 2.1 and 2.3.
3. Channel priority supersedes here and channel 2.1 will be serviced ahead of 1.1 and 2.3.
4. After channel 2.1 completes, channel 1.1 is serviced followed by channel 2.3.
Group priority is only guaranteed if no interrupts are currently being serviced, that is, the Interrupt Entry
Sequence (Section 3.4.3) is not executing.
3.4.6 System Error and CM Status Interrupts
SYS_ERR and CM_STATUS consolidate several sources of interrupts. These sources set the respective bit
in the SYS_ERR_INT_FLG and CM_STATUS_INT_FLG registers. Any set bit in the SYS_ERR_INT_FLG and
CM_STATUS_INT_FLG registers will also set the GINT (Global Interrupt) bit. GINT has to be cleared before
anymore SYS_ERR or CM_STATUS interrupts are generated. If GINT is cleared with the source flags still set,
another SYS_ERR or CM_STATUS interrupt will be fired, therefore it is recommended to clear the source flags
before clearing GINT.
Figure 3-3 shows the sources for SYS_ERR and CM_STATUS interrupts.

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Figure 3-3. System Error and CM Status Interrupt Sources

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3.4.7 Vector Tables

Table 3-3 shows the CPU interrupt vector table. The vectors for INT1–INT12 are not used in this device. The
reset vector is fetched from the boot ROM instead of from this table.
Table 3-3. CPU Interrupt Vectors
Name Vector ID Address Size (x16) Description Core Priority ePIE Group
Priority
Reset 0 0x0000 0D00 2 Reset is always fetched from 1 (Highest) -
location 0x003F_FFC0 in Boot ROM
INT1 1 0x0000 0D02 2 Not used. See PIE Group 1 5 -
INT2 2 0x0000 0D04 2 Not used. See PIE Group 2 6 -
INT3 3 0x0000 0D06 2 Not used. See PIE Group 3 7 -
INT4 4 0x0000 0D08 2 Not used. See PIE Group 4 8 -
INT5 5 0x0000 0D0A 2 Not used. See PIE Group 5 9 -
INT6 6 0x0000 0D0C 2 Not used. See PIE Group 6 10 -
INT7 7 0x0000 0D0E 2 Not used. See PIE Group 7 11 -
INT8 8 0x0000 0D10 2 Not used. See PIE Group 8 12 -
INT9 9 0x0000 0D12 2 Not used. See PIE Group 9 13 -
INT10 10 0x0000 0D14 2 Not used. See PIE Group 10 14 -
INT11 11 0x0000 0D16 2 Not used. See PIE Group 11 15 -
INT12 12 0x0000 0D18 2 Not used. See PIE Group 12 16 -
INT13 13 0x0000 0D1A 2 CPU TIMER1 Interrupt 17 -
INT14 14 0x0000 0D1C 2 CPU TIMER2 Interrupt 18 -
(for TI/RTOS use)
DATALOG 15 0x0000 0D1E 2 CPU Data Logging Interrupt 19 (Lowest) -
RTOSINT 16 0x0000 0D20 2 CPU Real-Time OS Interrupt 4 -
RSVD 17 0x0000 0D22 2 Reserved 2 -
NMI 18 0x0000 0D24 2 Non-Maskable Interrupt 3 -
ILLEGAL 19 0x0000 0D26 2 Illegal Instruction (ITRAP) - -
USER 1 20 0x0000 0D28 2 User-Defined Trap - -
USER 2 21 0x0000 0D2A 2 User-Defined Trap - -
USER 3 22 0x0000 0D2C 2 User-Defined Trap - -
USER 4 23 0x0000 0D2E 2 User-Defined Trap - -
USER 5 24 0x0000 0D30 2 User-Defined Trap - -
USER 6 25 0x0000 0D32 2 User-Defined Trap - -
USER 7 26 0x0000 0D34 2 User-Defined Trap - -
USER 8 27 0x0000 0D36 2 User-Defined Trap - -
USER 9 28 0x0000 0D38 2 User-Defined Trap - -
USER 10 29 0x0000 0D3A 2 User-Defined Trap - -
USER 11 30 0x0000 0D3C 2 User-Defined Trap - -
USER 12 31 0x0000 0D3E 2 User-Defined Trap - -

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Table 3-4 shows the PIE vector table.

Table 3-4. PIE Interrupt Vectors
Name Vector ID Address Size (x16) Description Core ePIE Group
Priority Priority
PIE Group 1 Vectors - Muxed into CPU INT1
INT1.1 32 0x0000 0D40 2 ADCA1 interrupt 5 1 (Highest)
INT1.2 33 0x0000 0D42 2 ADCB1 interrupt 5 2
INT1.3 34 0x0000 0D44 2 ADCC1 interrupt 5 3
INT1.4 35 0x0000 0D46 2 XINT1 interrupt 5 4
INT1.5 36 0x0000 0D48 2 XINT2 interrupt 5 5
INT1.6 37 0x0000 0D4A 2 ADCD1 interrupt 5 6
INT1.7 38 0x0000 0D4C 2 TIMER0 interrupt 5 7
INT1.8 39 0x0000 0D4E 2 WAKE/WD interrupt 5 8
INT1.9 128 0x0000 0E00 2 I2CA interrupt 5 9
INT1.10 129 0x0000 0E02 2 SYS_ERR interrupt 5 10
INT1.11 130 0x0000 0E04 2 ECAT SYNC0 interrupt 5 11
(CPU1 only)
INT1.12 131 0x0000 0E06 2 ECAT interrupt n 5 12
(CPU1 only)
INT1.13 132 0x0000 0E08 2 CIPC0 interrupt 5 13
INT1.14 133 0x0000 0E0A 2 CIPC1 interrupt 5 14
INT1.15 134 0x0000 0E0C 2 CIPC2 interrupt 5 15
INT1.16 135 0x0000 0E0E 2 CIPC3 interrupt 5 16 (Lowest)
PIE Group 2 Vectors - Muxed into CPU INT2
INT2.1 40 0x0000 0D50 2 EPWM1_TZ interrupt 6 1 (Highest)
INT2.2 41 0x0000 0D52 2 EPWM2_TZ interrupt 6 2
INT2.3 42 0x0000 0D54 2 EPWM3_TZ interrupt 6 3
INT2.4 43 0x0000 0D56 2 EPWM4_TZ interrupt 6 4
INT2.5 44 0x0000 0D58 2 EPWM5_TZ interrupt 6 5
INT2.6 45 0x0000 0D5A 2 EPWM6_TZ interrupt 6 6
INT2.7 46 0x0000 0D5C 2 EPWM7_TZ interrupt 6 7
INT2.8 47 0x0000 0D5E 2 EPWM8_TZ interrupt 6 8
INT2.9 136 0x0000 0E10 2 EPWM9_TZ interrupt 6 9
INT2.10 137 0x0000 0E12 2 EPWM10_TZ interrupt 6 10
INT2.11 138 0x0000 0E14 2 EPWM11_TZ interrupt 6 11
INT2.12 139 0x0000 0E16 2 EPWM12_TZ interrupt 6 12
INT2.13 140 0x0000 0E18 2 EPWM13_TZ interrupt 6 13
INT2.14 141 0x0000 0E1A 2 EPWM14_TZ interrupt 6 14
INT2.15 142 0x0000 0E1C 2 EPWM15_TZ interrupt 6 15
INT2.16 143 0x0000 0E1E 2 EPWM16_TZ interrupt 6 16 (Lowest)
PIE Group 3 Vectors - Muxed into CPU INT3
INT3.1 48 0x0000 0D60 2 EPWM1 interrupt 7 1 (Highest)
INT3.2 49 0x0000 0D62 2 EPWM2 interrupt 7 2
INT3.3 50 0x0000 0D64 2 EPWM3 interrupt 7 3
INT3.4 51 0x0000 0D66 2 EPWM4 interrupt 7 4
INT3.5 52 0x0000 0D68 2 EPWM5 interrupt 7 5
INT3.6 53 0x0000 0D6A 2 EPWM6 interrupt 7 6
INT3.7 54 0x0000 0D6C 2 EPWM7 interrupt 7 7

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Table 3-4. PIE Interrupt Vectors (continued)

Name Vector ID Address Size (x16) Description Core ePIE Group
Priority Priority
INT3.8 55 0x0000 0D6E 2 EPWM8 interrupt 7 8
INT3.9 144 0x0000 0E20 2 EPWM9 interrupt 7 9
INT3.10 145 0x0000 0E22 2 EPWM10 interrupt 7 10
INT3.11 146 0x0000 0E24 2 EPWM11 interrupt 7 11
INT3.12 147 0x0000 0E26 2 EPWM12 interrupt 7 12
INT3.13 148 0x0000 0E28 2 EPWM13 interrupt 7 13
INT3.14 149 0x0000 0E2A 2 EPWM14 interrupt 7 14
INT3.15 150 0x0000 0E2C 2 EPWM15 interrupt 7 15
INT3.16 151 0x0000 0E2E 2 EPWM16 interrupt 7 16 (Lowest)
PIE Group 4 Vectors - Muxed into CPU INT4
INT4.1 56 0x0000 0D70 2 ECAP1 interrupt 8 1 (Highest)
INT4.2 57 0x0000 0D72 2 ECAP2 interrupt 8 2
INT4.3 58 0x0000 0D74 2 ECAP3 interrupt 8 3
INT4.4 59 0x0000 0D76 2 ECAP4 interrupt 8 4
INT4.5 60 0x0000 0D78 2 ECAP5 interrupt 8 5
INT4.6 61 0x0000 0D7A 2 ECAP6 interrupt 8 6
INT4.7 62 0x0000 0D7C 2 ECAP7 interrupt 8 7
INT4.8 63 0x0000 0D7E 2 Reserved 8 8
INT4.9 152 0x0000 0E30 2 FSITXA interrupt 1 8 9
INT4.10 153 0x0000 0E32 2 FSITXA interrupt 2 8 10
INT4.11 154 0x0000 0E34 2 FSITXB interrupt 1 8 11
INT4.12 155 0x0000 0E36 2 FSITXB interrupt 2 8 12
INT4.13 156 0x0000 0E38 2 FSIRXA interrupt 1 8 13
INT4.14 157 0x0000 0E3A 2 FSIRXA interrupt 2 8 14
INT4.15 158 0x0000 0E3C 2 FSIRXB interrupt 1 8 15
INT4.16 159 0x0000 0E3E 2 FSIRXB interrupt 2 8 16 (Lowest)
PIE Group 5 Vectors - Muxed into CPU INT5
INT5.1 64 0x0000 0D80 2 EQEP1 interrupt 9 1 (Highest)
INT5.2 65 0x0000 0D82 2 EQEP2 interrupt 9 2
INT5.3 66 0x0000 0D84 2 EQEP3 interrupt 9 3
INT5.4 67 0x0000 0D86 2 Reserved 9 4
INT5.5 68 0x0000 0D88 2 CLB1 interrupt 9 5
INT5.6 69 0x0000 0D8A 2 CLB2 interrupt 9 6
INT5.7 70 0x0000 0D8C 2 CLB3 interrupt 9 7
INT5.8 71 0x0000 0D8E 2 CLB4 interrupt 9 8
INT5.9 160 0x0000 0E40 2 SDFM1 interrupt 9 9
INT5.10 161 0x0000 0E42 2 SDFM2 interrupt 9 10
INT5.11 162 0x0000 0E44 2 ECATRST interrupt n 9 11
(CPU1 only)
INT5.12 163 0x0000 0E46 2 ECATSYNC1 interrupt 9 12
(CPU1 only)
INT5.13 164 0x0000 0E48 2 SDFM1DR1 interrupt 9 13
INT5.14 165 0x0000 0E4A 2 SDFM1DR2 interrupt 9 14
INT5.15 166 0x0000 0E4C 2 SDFM1DR3 interrupt 9 15
INT5.16 167 0x0000 0E4E 2 SDFM1DR4 interrupt 9 16 (Lowest)

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Table 3-4. PIE Interrupt Vectors (continued)

Name Vector ID Address Size (x16) Description Core ePIE Group
Priority Priority
PIE Group 6 Vectors - Muxed into CPU INT6
INT6.1 72 0x0000 0D90 2 SPIA_RX interrupt 10 1 (Highest)
INT6.2 73 0x0000 0D92 2 SPIA_TX interrupt 10 2
INT6.3 74 0x0000 0D94 2 SPIB_RX interrupt 10 3
INT6.4 75 0x0000 0D96 2 SPIB_TX interrupt 10 4
INT6.5 76 0x0000 0D98 2 MCBSPA_RX interrupt 10 5
INT6.6 77 0x0000 0D9A 2 MCBSPA_TX interrupt 10 6
INT6.7 78 0x0000 0D9C 2 MCBSPB_RX interrupt 10 7
INT6.8 79 0x0000 0D9E 2 MCBSPB_TX interrupt 10 8
INT6.9 168 0x0000 0E50 2 SPIC_RX interrupt 10 9
INT6.10 169 0x0000 0E52 2 SPIC_TX interrupt 10 10
INT6.11 170 0x0000 0E54 2 SPID_RX interrupt 10 11
INT6.12 171 0x0000 0E56 2 SPID_TX interrupt 10 12
INT6.13 172 0x0000 0E58 2 SDFM2DR1 interrupt 10 13
INT6.14 173 0x0000 0E5A 2 SDFM2DR2 interrupt 10 14
INT6.15 174 0x0000 0E5C 2 SDFM2DR3 interrupt 10 15
INT6.16 175 0x0000 0E5E 2 SDFM2DR4 interrupt 10 16 (Lowest)
PIE Group 7 Vectors - Muxed into CPU INT7
INT7.1 80 0x0000 0DA0 2 DMA_CH1 interrupt 11 1 (Highest)
INT7.2 81 0x0000 0DA2 2 DMA_CH2 interrupt 11 2
INT7.3 82 0x0000 0DA4 2 DMA_CH3 interrupt 11 3
INT7.4 83 0x0000 0DA6 2 DMA_CH4 interrupt 11 4
INT7.5 84 0x0000 0DA8 2 DMA_CH5 interrupt 11 5
INT7.6 85 0x0000 0DAA 2 DMA_CH6 interrupt 11 6
INT7.7 86 0x0000 0DAC 2 Reserved 11 7
INT7.8 87 0x0000 0DAE 2 Reserved 11 8
INT7.9 176 0x0000 0E60 2 FSIRXC interrupt 1 11 9
INT7.10 177 0x0000 0E62 2 FSIRXC interrupt 2 11 10
INT7.11 178 0x0000 0E64 2 FSIRXD interrupt 1 11 11
INT7.12 179 0x0000 0E66 2 FSIRXD interrupt 2 11 12
INT7.13 180 0x0000 0E68 2 FSIRXE interrupt 1 11 13
INT7.14 181 0x0000 0E6A 2 FSIRXE interrupt 2 11 14
INT7.15 182 0x0000 0E6C 2 FSIRXF interrupt 1 11 15
INT7.16 183 0x0000 0E6E 2 FSIRXF interrupt 2 11 16 (Lowest)
PIE Group 8 Vectors - Muxed into CPU INT8
INT8.1 88 0x0000 0DB0 2 I2CA interrupt 12 1 (Highest)
INT8.2 89 0x0000 0DB2 2 I2CA_FIFO interrupt 12 2
INT8.3 90 0x0000 0DB4 2 I2CB interrupt 12 3
INT8.4 91 0x0000 0DB6 2 I2CB_FIFO interrupt 12 4
INT8.5 92 0x0000 0DB8 2 SCIC_RX interrupt 12 5
INT8.6 93 0x0000 0DBA 2 SCIC_TX interrupt 12 6
INT8.7 94 0x0000 0DBC 2 SCID_RX interrupt 12 7
INT8.8 95 0x0000 0DBE 2 SCID_TX interrupt 12 8
INT8.9 184 0x0000 0E70 2 FSIRXG interrupt 1 12 9

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Table 3-4. PIE Interrupt Vectors (continued)

Name Vector ID Address Size (x16) Description Core ePIE Group
Priority Priority
INT8.10 185 0x0000 0E72 2 FSIRXG interrupt 2 12 10
INT8.11 186 0x0000 0E74 2 FSIRXH interrupt 1 12 11
INT8.12 187 0x0000 0E76 2 FSIRXH interrupt 2 12 12
INT8.13 188 0x0000 0E78 2 CLB5 interrupt 12 13
INT8.14 189 0x0000 0E7A 2 CLB6 interrupt 12 14
INT8.15 190 0x0000 0E7C 2 CLB7 interrupt 12 15
INT8.16 191 0x0000 0E7E 2 CLB8 interrupt 12 16 (Lowest)
PIE Group 9 Vectors - Muxed into CPU INT9
INT9.1 96 0x0000 0DC0 2 SCIA_RX interrupt 13 1 (Highest)
INT9.2 97 0x0000 0DC2 2 SCIA_TX interrupt 13 2
INT9.3 98 0x0000 0DC4 2 SCIB_RX interrupt 13 3
INT9.4 99 0x0000 0DC6 2 SCIB_TX interrupt 13 4
INT9.5 100 0x0000 0DC8 2 CANA interrupt 0 13 5
INT9.6 101 0x0000 0DCA 2 CANA interrupt 1 13 6
INT9.7 102 0x0000 0DCC 2 CANB interrupt 0 13 7
INT9.8 103 0x0000 0DCE 2 CANB interrupt 1 13 8
INT9.9 192 0x0000 0E80 2 MCANSS interrupt 0 13 9
(CPU1 only)
INT9.10 193 0x0000 0E82 2 MCANSS interrupt 1 13 10
(CPU1 only)
INT9.11 194 0x0000 0E84 2 MCANSS_ECC_CORR_ 13 11
PUL interrupt
(CPU1 only)
INT9.12 195 0x0000 0E86 2 MCANSS_WAKE_AND_ 13 12
TS_PLS interrupt
(CPU1 only)
INT9.13 196 0x0000 0E88 2 PMBUSA interrupt 13 13
INT9.14 197 0x0000 0E8A 2 CM_STATUS interrupt 13 14
(CPU1 only)
INT9.15 198 0x0000 0E8C 2 USBA interrupt 13 15
(CPU1 only)
INT9.16 199 0x0000 0E8E 2 Reserved 13 16 (Lowest)
PIE Group 10 Vectors - Muxed into CPU INT10
INT10.1 104 0x0000 0DD0 2 ADCA_EVT interrupt 14 1 (Highest)
INT10.2 105 0x0000 0DD2 2 ADCA2 interrupt 14 2
INT10.3 106 0x0000 0DD4 2 ADCA3 interrupt 14 3
INT10.4 107 0x0000 0DD6 2 ADCA4 interrupt 14 4
INT10.5 108 0x0000 0DD8 2 ADCB_EVT interrupt 14 5
INT10.6 109 0x0000 0DDA 2 ADCB2 interrupt 14 6
INT10.7 110 0x0000 0DDC 2 ADCB3 interrupt 14 7
INT10.8 111 0x0000 0DDE 2 ADCB4 interrupt 14 8
INT10.9 200 0x0000 0E90 2 ADCC_EVT interrupt 14 9
INT10.10 201 0x0000 0E92 2 ADCC2 interrupt 14 10
INT10.11 202 0x0000 0E94 2 ADCC3 interrupt 14 11
INT10.12 203 0x0000 0E96 2 ADCC4 interrupt 14 12
INT10.13 204 0x0000 0E98 2 ADCD_EVT interrupt 14 13
INT10.14 205 0x0000 0E9A 2 ADCD2 interrupt 14 14

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Table 3-4. PIE Interrupt Vectors (continued)

Name Vector ID Address Size (x16) Description Core ePIE Group
Priority Priority
INT10.15 206 0x0000 0E9C 2 ADCD3 interrupt 14 15
INT10.16 207 0x0000 0E9E 2 ADCD4 interrupt 14 16 (Lowest)
PIE Group 11 Vectors - Muxed into CPU INT11
INT11.1 112 0x0000 0DE0 2 CLA1_1 interrupt 15 1 (Highest)
INT11.2 113 0x0000 0DE2 2 CLA1_2 interrupt 15 2
INT11.3 114 0x0000 0DE4 2 CLA1_3 interrupt 15 3
INT11.4 115 0x0000 0DE6 2 CLA1_4 interrupt 15 4
INT11.5 116 0x0000 0DE8 2 CLA1_5 interrupt 15 5
INT11.6 117 0x0000 0DEA 2 CLA1_6 interrupt 15 6
INT11.7 118 0x0000 0DEC 2 CLA1_7 interrupt 15 7
INT11.8 119 0x0000 0DEE 2 CLA1_8 interrupt 15 8
INT11.9 208 0x0000 0EA0 2 CMTOCPUx IPC interrupt 0 15 9
INT11.10 209 0x0000 0EA2 2 CMTOCPUx IPC interrupt 1 15 10
INT11.11 210 0x0000 0EA4 2 CMTOCPUx IPC interrupt 2 15 11
INT11.12 211 0x0000 0EA6 2 CMTOCPUx IPC interrupt 3 15 12
INT11.13 212 0x0000 0EA8 2 CMTOCPUx IPC interrupt 4 15 13
INT11.14 213 0x0000 0EAA 2 CMTOCPUx IPC interrupt 5 15 14
INT11.15 214 0x0000 0EAC 2 CMTOCPUx IPC interrupt 6 15 15
INT11.16 215 0x0000 0EAE 2 CMTOCPUx IPC interrupt 7 15 16 (Lowest)
PIE Group 12 Vectors - Muxed into CPU INT12
INT12.1 120 0x0000 0DF0 2 XINT3 interrupt 16 1 (Highest)
INT12.2 121 0x0000 0DF2 2 XINT4 interrupt 16 2
INT12.3 122 0x0000 0DF4 2 XINT5 interrupt 16 3
INT12.4 123 0x0000 0DF6 2 MPOST interrupt 16 4
INT12.5 124 0x0000 0DF8 2 FMC.DONE interrupt 16 5
INT12.6 125 0x0000 0DFA 2 VCRC interrupt 16 6
INT12.7 126 0x0000 0DFC 2 FPU OVERFLOW interrupt 16 7
INT12.8 127 0x0000 0DFE 2 FPU UNDERFLOW interrupt 16 8
INT12.9 216 0x0000 0EB0 2 Reserved 16 9
INT12.10 217 0x0000 0EB2 2 ECAP6 interrupt 16 10
INT12.11 218 0x0000 0EB4 2 ECAP7 interrupt 16 11
INT12.12 219 0x0000 0EB6 2 Reserved 16 12
INT12.13 220 0x0000 0EB8 2 CPUxCRC interrupt 16 13
INT12.14 221 0x0000 0EBA 2 CLA1CRC interrupt 16 14
INT12.15 222 0x0000 0EBC 2 CLA OVERFLOW interrupt 16 15
INT12.16 223 0x0000 0EBE 2 CLA UNDERFLOW interrupt 16 16 (Lowest)

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3.5 Exceptions and Non-Maskable Interrupts

This section describes system-level error conditions that can trigger a non-maskable interrupt (NMI). The
interrupt allows the application to respond to the error.
3.5.1 Configuring and Using NMIs
Each CPU subsystem has its own NMI module. This section will provide detail of NMI on C28x subsystems.
An incoming NMI sets a status bit in the NMIFLG register and starts the NMI watchdog counter. This counter
is clocked by the SYSCLK, and if it reaches the value programmed in NMIWDPRD register, it triggers an NMI
watchdog reset (NMIWDRS). To prevent this, the NMI handler must clear the flag bit using the NMIFLGCLR
register. Once all flag bits are clear, the NMIINT bit in the NMIFLG register should be cleared to allow future
NMIs to be taken.
The NMI module is enabled by the boot ROM during the startup process. To respond to NMIs, an NMI handler
vector must be written to the PIE vector table.
3.5.2 Emulation Considerations
The NMI watchdog counter behaves as follows under debug conditions:

CPU Suspended: When the CPU is suspended, the NMI watchdog counter is suspended.
Run-Free Mode: When the CPU is placed in run-free mode, the NMI watchdog counter resumes
operation as normal.
Real-Time Single-Step Mode: When the CPU is in real-time single-step mode, the NMI watchdog counter is
suspended. The counter remains suspended even within real-time interrupts.
Real-Time Run-Free Mode: When the CPU is in real-time run-free mode, the NMI watchdog counter
operates as normal.

3.5.3 NMI Sources

There are several types of hardware errors that can trigger an NMI. Additional information about the error is
usually available from the module that detects it.
3.5.3.1 Missing Clock Detection
The missing clock detection logic monitors OSCCLK for failure. If the OSCCLK source stops, the PLL is
bypassed, OSCCLK is connected to INTOSC1, and NMIs are fired to both CPUs. For more information on
missing clock detection, see Section 3.7.7.1.
3.5.3.2 RAM Uncorrectable Error
A single-bit parity error, double-bit ECC data error, or single-bit ECC address error in a RAM read will trigger
an NMI. This applies to CPU, CLA, and DMA reads. Single-bit ECC data errors do not trigger an NMI, but
can optionally trigger a normal peripheral interrupt. For more information on RAM error detection, see Section
3.12.1.9.
3.5.3.3 Flash Uncorrectable ECC Error
A double-bit ECC data error or single-bit ECC address error in a Flash read will trigger an NMI. Single-bit ECC
data errors do not trigger an NMI, but can optionally trigger a normal peripheral interrupt.
3.5.3.4 ROM Uncorrectable Error
On this device ROM has a parity feature and a parity mismatch during read or execution will trigger an NMI.
3.5.3.5 NMI Vector Fetch Mismatch
Each CPU's Peripheral Interrupt Expansion module (PIE) has redundant vector tables. If a mismatch in these
tables is detected during a vector fetch, a user-specified error handler is run instead of the ISR. If the vector
fetch was caused by an NMI, a second NMI is fired to the other CPU. Mismatches for other interrupts do not
trigger an NMI. For more information about the vector address check, see Section 3.6.2.

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3.5.3.6 CPU2 Watchdog or NMI Watchdog Reset

A watchdog reset or NMI watchdog reset on CPU2 will trigger an NMI on CPU1. Since a CPU1 reset also resets
CPU2, this NMI source is not available on CPU2. Watchdog interrupts do not trigger an NMI.
3.5.3.7 CM NMI Watchdog Reset
A NMI watchdog reset on CM can generate NMI on CPU1. To enable this feature user need to set
CMNMIWDRST configuration bit in CMTOCPU1NMICTL register.
3.5.3.8 EtherCAT Reset out
A reset out from EtherCAT module can generate NMI on CPU1. To enable this feature user need to set
CPU_NMI_EN configuration bit in ESCSS_RESET_DEST_CONFIG register.
3.5.3.9 CRC Fail
A CRC fail result from BGCRC module can generate NMI to respective CPU. By default this NMI is enable.
To disable this feature user need to configure NMIDIS configuration field in BGCRC_CTRL1 register with value
"1010".
3.5.3.10 ERAD NMI
ERAD module can generate NMI based on different events which user can configure in ERAD.
3.5.4 Illegal Instruction Trap (ITRAP)
If the CPU tries to execute an illegal instruction, it generates a special interrupt called an illegal instruction trap
(ITRAP). This interrupt is non-maskable and has its own vector in the PIE vector table. For more information
about ITRAPs, see the Illegal-Instruction Trap section of the TMS320C28x DSP CPU and Instruction Set
Reference Guide.

Note
A RAM fetch access violation will trigger an ITRAP in addition to the normal peripheral interrupt for
RAM access violations. The CPU will handle the ITRAP first.

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3.6 Safety Features

This section gives details on features that monitor device operation during run-time to detect any error in
operation.
3.6.1 Write Protection on Registers
3.6.1.1 LOCK Protection on System Configuration Registers
Several system configuration registers are protected from spurious CPU writes by “LOCK” registers. Once these
associated LOCK register bits are set, the respective locked registers can no longer be modified by software.
See the register descriptions for details.
3.6.1.2 EALLOW Protection
Several control registers are protected from spurious CPU writes by the EALLOW protection mechanism. The
EALLOW bit in status register 1 (ST1) indicates the state of protection as shown in Table 3-5.
Table 3-5. Access to EALLOW-Protected Registers
EALLOW Bit CPU Writes CPU Reads JTAG Writes JTAG Reads
0 Ignored Allowed Allowed(1) Allowed
1 Allowed Allowed Allowed Allowed

(1) The EALLOW bit is overridden via the JTAG port, allowing full access of protected registers during debug from the Code Composer
Studio IDE.

At reset, the EALLOW bit is cleared, enabling EALLOW protection. While protected, all writes to protected
registers by the CPU are ignored and only CPU reads, JTAG reads, and JTAG writes are allowed. If this bit
is set, by executing the EALLOW instruction, the CPU is allowed to write freely to protected registers. After
modifying registers, the registers can once again be protected by executing the EDIS instruction to clear the
EALLOW bit.

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3.6.2 CPU1 and CPU2 ePIE Vector Address Validity Check

The ePIE vector table on each CPU is duplicated into these two parts:
• Main ePIE Vector Table mapped from 0xD00 to 0xEFF in the C28x memory space
• Redundant ePIE Vector Table mapped from 0x1000D00 to 0x1000EFF in the C28x memory space
Following is the behavior of accesses to the ePIE memories:
• Data Writes to Main Vector Table: Writes to both memories
• Data Writes to Redundant Vector Table: Writes only to the Redundant Vector Table
• Vector Fetch: Data from both the vector tables are compared
• Data Read: Can read the Main and Redundant vector table separately
On every vector fetch from the ePIE, a hardware comparison (no cycle penalty is incurred to do the comparison)
of both the vector table outputs is performed and if there is a mismatch between the two vector table outputs, the
following occurs:
1. If the PIEVERRADDR register (default value 0x3F FFFF) is not initialized, the default error handler at
address 0x3FFFBE gets executed.
But, when the PIEVERRADDR register is initialized to the address of the user-defined routine, the user-
defined routine is executed instead of the default error handler.
Note: Each CPU has a copy of the PIE Vector Fetch Error Handler register (CPU1.PIEVERRADDR and
CPU2.PIEVERRADDR).
2. Hardware also generates EPWM Trip signals that trip the PWM outputs using TRIPIN15.
3. An NMI to the other CPU is sent, if the current mismatch is during a vector fetch. For example, on an NMI
vector fetch error for CPU2, an NMI is also fired to CPU1.NMIWD.
If there is no mismatch, the correct vector is jammed onto the C28 program control.
3.6.3 NMIWDs
Each CPU has user-programmable NMIWD period registers, in which users can set a limit on how much time
they want to allocate for the device to acknowledge the NMI. If the NMI is not acknowledged, it will cause a
device reset.
3.6.4 ECC and Parity Enabled RAMs, Shared RAMs Protection
Each CPU subsystem has different RAM blocks. Some RAM blocks are ECC-enabled and others are parity-
enabled. All single-bit errors in ECC RAM are auto-corrected and an error counter is incremented every time
a single bit error is detected. If the error counter reaches a predefined user configured limit, an interrupt is
generated to the corresponding CPU. Refer to Section 3.12 for more details on RAM errors.
All uncorrectable double-bit errors end up triggering an NMI to corresponding CPUs.
3.6.5 ECC Enabled Flash Memory
When ECC is programmed and enabled, Flash single-bit errors are corrected automatically by ECC logic before
giving data to the CPU, but they are not corrected in Flash memory. Flash memory will still contain wrong data
until another erase/program operation happens to correct the Flash contents. Irrespective of whether the error
interrupt is enabled or disabled, single-bit errors are always corrected before giving data to the CPU. When the
interrupt is disabled, users can check the single-bit error counter register for any single-bit error occurrences.
The error counter stops incrementing once its value is equal to the threshold + 1. It is always suggested to set
the threshold register to a non-zero value so that the error counter can increment. It is up to the user to decide
the threshold value at which they have to reprogram the Flash with the correct data.
When ECC is programmed and enabled, Flash uncorrectable errors end up triggering an NMI to the respective
CPU. Refer to Section 3.12 for more details on Flash error correction and error catching mechanisms.

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3.6.6 ERRORSTS Pin

The ERRORSTS pin is an ‘always output’ pin and remains high until an error is detected inside the chip. On
an error, the ERRORSTS pin goes low (default polarity) until the corresponding internal error status flag for that
error source is cleared. Figure 3-4 shows the functionality of the ERRORSTS pin.
The ERRORSTS pin is tri-stated until the chip power-rails ramp up to the lower operational limit. As the
ERRORSTS pin is an active-low pin (default polarity), users who care about the state of this pin during power-up
must connect an external pull-down on this pin.
Following enhancement has been made on this device for ERRORSTS pin logic:
• Polarity of Error pin has been made configurable (default setting is active-low polarity).
• To enable testing of the Error pin, capability to force and clear the Error pin from software has been provided.
• Additional sources of Error have been added to ERRORSTS:
– CPU1 Watchdog reset
– Error on a PIE vector fetch
– NMI on CM
CPU1's NMIWD Shadow flags

CPU1.NMIWD.NMISHDFLG.Bit-0

CPU1.NMIWD.NMISHDFLG.Bit-1

CPU1.NMIWD.NMISHDFLG.Bit-15

CPU2's NMIWD Shadow flags

ERROR

CPU2.NMIWD.NMISHDFLG.Bit-0

CPU2.NMIWD.NMISHDFLG.Bit-1

CPU2.NMIWD.NMISHDFLG.Bit-15

Figure 3-4. ERRORSTS Pin Diagram

3.7 Clocking
This section explains the clock sources and clock domains on this device, and how to configure them for
application use. Figure 3-5 provides an overview of the device's clocking system.

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PLLCLKEN AUXPLLDIV

AUXOSCCLK AUX PLL

AUXCLK
PLLSYSCLKDIV Divider

AUXOSCCLKSRCSEL
SYS
SYS PLL PLLRAWCLK Divider
AUXPLLRAWCLK
USBBITCLK

OSCCLKSRCSEL PLLCLKEN PLLSYSCLK

One per CMCLK peripheral

CMPCLKCRx.PERx
PLLSYSCLK CMDIVSRCSEL
WDCLK
CMCLK CMCLK
DIVSRCSEL
DIVIDER
NMIWDs
Watch Dog GSx RAMs
Timers GPIOs CPU1 CPU2 ETHERCATCLK
MSG RAMs CM.PERx.SYSCLK
IPC
XBARs ECATDIV ETHERCATCLK
CPU2.CPUCLK Divider
AnalogSubsys
SystemControl CM.PERx.SYSCLK
EMIF1 FPU
CPU1.CPUCLK TMU PHYCLKEN
VCRC
CPU1.SYSCLK Flash
FPU
DCSM /4
TMU
CPU2.SYSCLK MxRAM
VCRC CPUTIMERx DxRAM ETHERCAT PALLOCATE0
Flash DMA ETHERCATPHYCLK

CPU1.PERx.SYSCLK
CPUTIMERx BootROM .USB
DCSM CLA1
DMA HWBIST
HWBIST XINT CPU1.PCLKCRx
CLA1 USB
PIE
XINT
LSx RAM
PIE
MSG RAMs CPU1/CPU2/CM
LSx RAM
MxRAM .PERx.SYSCLK
MSG RAMs
DxRAM CPU2.PCLKCRx
BGCRC
BootROM
ERAD CPU2.PERx.SYSCLK
BGCRC
ERAD CANx
EMIF2 PALLOCATE0.CANx
WD
CPUSELx.CANx
CPU1.SYSCLK

CPU2.SYSCLK

X1 (XTAL)
One per SYSCLK peripheral
CPU2.PCLKCRx CPUSELx AUXCLKIN
One per LSPCLK peripheral
CANxBITCLK
CPUSELx CPU1.PCLKCRx

CANxBIT Clock
LSP CPU1.PCLKCRx
LSPCLKDIV PERx.SYSCLK
Divider
PLLSYSCLK

CPU2.PCLKCRx
PERx.SYSCLK
EPWMCLKDIV

/1 HRCAL
PERx.LSPCLK ECAPx
/2
EQEPx
One per ePWM peripheral SDFMx
McBSPx Bit CPU1.PCLKCRx SPIx
SPIx Bit Clock SCIx Bit Clock CPUSELx
Clock SCIx
McBSPx
EPWMCLK ADC
CMPSSx
DACx
CPU2.PCLKCRx ePWM FSIx
HRPWM I2C
HRCAL PMBUS
CPU1.PCLKCRx DCCx

HRCALCLK

CLB

CLB TILEx
CLBCLK TILECLK Clock
AUX PLL Divider
Divider

CLBCLKCTL.CLKMODECLBx

CLBx Register
Clock

Figure 3-5. Clocking System

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3.7.1 Clock Sources

The needs of the application are what ultimately determine the clock configuration. Specific concerns such
as application performance, power consumption, total system cost, and EMC are beyond the scope of this
document, but must provide answers to the following questions:
1. What is the desired CPU frequency?
2. Are there any additional communication protocols or peripherals, such as CAN or USB, required?
3. What types of external oscillators or clock sources are available?
If CAN or USB is required, an external clock source with a precise frequency must be used as a reference clock.
Otherwise, use only INTOSC2 and avoid the need for more external components.
All of the clocks in the device are derived from one of four clock sources.
3.7.1.1 Primary Internal Oscillator (INTOSC2)
At power-up, the device is clocked from an on-chip 10 MHz oscillator (INTOSC2). INTOSC2 is the primary
internal clock source, and is the default system clock at reset. It is used to run the boot ROM and can be used as
the system clock source for the application.

Note
INTOSC2's frequency tolerance is too loose to meet the timing requirements for some peripherals
such as CAN and USB, so an external clock must be used to support those features.

3.7.1.2 Backup Internal Oscillator (INTOSC1)

The device also includes a redundant on-chip 10 MHz oscillator (INTOSC1). INTOSC1 is a backup clock source
that normally only clocks the watchdog timers and missing clock detection circuit (MCD). If MCD is enabled
and a missing system clock is detected, the system PLL is bypassed and all system clocks are connected to
INTOSC1 automatically. INTOSC1 may also be manually selected as the system and auxiliary clock source for
debug purposes.
3.7.1.3 External Oscillator (XTAL)
The dedicated X1 and X2 pins support an external clock source (XTAL), which can be used as the main system
and auxiliary clock source. Frequency limits and timing requirements can be found in the device datasheet.
Three types of external clock sources are supported:
• A single-ended 3.3V external clock. The clock signal should be connected to X1 while X2 is left unconnected,
as shown in Figure 3-6.

VDDOSC X1 VSSOSC X2

3.3V NC
3.3V
Clk

VDD OUT

GND
3.3V Oscillator

Figure 3-6. Single-ended 3.3V External Clock

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• An external crystal. The crystal should be connected across X1 and X2 with its load capacitors connected to
VSSOSC as shown in Figure 3-7.

VDDOSC X1 VSSOSC X2

3.3V
Crystal

RD CL2 CL1

Figure 3-7. External Crystal

• An external resonator. The resonator should be connected across X1 and X2 with its ground connected to
VSSOSC as shown in Figure 3-8.

VDDOSC X1 VSSOSC X2

3.3V

Resonator

Figure 3-8. External Resonator

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3.7.1.4 Auxiliary Clock Input (AUXCLKIN)

An additional external clock source is supported on GPIO133 (AUXCLKIN). This must be a single-ended 3.3V
external clock. It can be used as the clock source for the USB, CAN, and Communication Manager Subsystem.
Frequency limits and timing requirements can be found in the device datasheet. The external clock should be
connected directly to the GPIO133 pin, as shown in Figure 3-9.

Device

GPIO133_AUXCLKIN

CLK
3.3V

VDD OUT

GND
3.3V OSCILLATOR

Figure 3-9. AUXCLKIN

3.7.2 Derived Clocks

The clock sources discussed in the previous section can be multiplied (via PLL) and divided down to produce the
desired clock frequencies for the application. This process produces a set of derived clocks, which are described
in this section.
3.7.2.1 Oscillator Clock (OSCCLK)
One of INTOSC2, XTAL, or INTOSC1 must be chosen to be the master reference clock (OSCCLK) for the CPU
and most of the peripherals. OSCCLK may be used directly or fed through the system PLL to reach a higher
frequency. At reset, OSCCLK is the default system clock, and is connected to INTOSC2.
3.7.2.2 System PLL Output Clock (PLLRAWCLK)
The system PLL allows the device to run at the maximum rated operating frequency, and in most applications
generates the main system clock. This PLL uses OSCCLK as a reference. For configuration instructions, see
Section 3.7.6.

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3.7.2.3 Auxiliary Oscillator Clock (AUXOSCCLK)

One of INTOSC2, XTAL, or AUXCLKIN may be chosen to be the auxiliary reference clock (AUXOSCCLK) for the
USB module. (This selection does not affect the CAN bit clock, which uses AUXCLKIN directly). AUXOSCCLK
may be used directly or fed through the auxiliary PLL to reach a higher frequency. At reset, AUXOSCCLK is
connected to INTOSC2, but only an external oscillator can meet the USB timing requirements.
3.7.2.4 Auxiliary PLL Output Clock (AUXPLLRAWCLK)
The auxiliary PLL is used to generate a clock for USB, CAN, EtherCAT, and the CM Subsystem. This PLL uses
AUXOSCCLK as a reference. For configuration instructions, see Section 3.7.6.
3.7.3 Device Clock Domains
The device clock domains feed the clock inputs of the various modules in the device. They are connected to the
derived clocks, either directly or through an additional divider.
3.7.3.1 System Clock (PLLSYSCLK)
The system control registers, GS RAMs, IPC module, GPIO qualification, and NMI watchdog timers have
their own clock domain (PLLSYSCLK). Despite the name, PLLSYSCLK may be connected to the system PLL
(PLLRAWCLK) or to OSCCLK. The chosen clock source is run through a frequency divider, which is configured
via the SYSCLKDIVSEL register.
3.7.3.2 CPU Clock (CPUCLK)
Each CPU has its own clock (CPU1.CPUCLK and CPU2.CPUCLK) which is used to clock the CPU, its
coprocessors, its private RAMs (M0, M1, D0, and D1), and its boot ROM and Flash wrapper. This clock is
identical to PLLSYSCLK, but is gated when the CPU enters IDLE or STANDBY mode.
3.7.3.3 CPU Subsystem Clock (SYSCLK and PERx.SYSCLK)
Each CPU provides a clock (CPU1.SYSCLK and CPU2.SYSCLK) to its CLA, DMA, and most owned peripherals.
This clock is identical to PLLSYSCLK, but is gated when the CPU enters STANDBY mode.
Each peripheral clock can be connected to either CPU1.SYSCLK or CPU2.SYSCLK. This selection is made by
CPU1 via the CPUSELx registers. Each peripheral clock also has its own independent clock gating which is
controlled by the CPU's PCLKCRx registers. By default, the ePWM, EMIF1, and EMIF2 clocks each have an
additional /2 divider, which is required to support CPU frequencies over 100 MHz. At slower CPU frequencies,
these dividers can be disabled via the PERCLKDIVSEL register.
A peripheral may be assigned to either CPU. That is, code for a peripheral can be executed from either CPU1
or CPU2. CPUSELx register is used to assign a peripheral to either CPU1 or CPU2. This register must be
configured prior to enabling the clock for the chosen peripheral since the clock for each peripheral is derived
from the selected CPU subsystem. The clock multiplexer controlled by the CPUSELx register is not glitch-free.
Therefore the CPUSELx register must be configured before the PCLKCRx register. Note that the reset for each
peripheral is also driven from the selected CPU.

Note
Application needs to wait for 5 SYSCLK cycles after enabling clock to the peripherals when using
PCLKCRx.

3.7.3.4 Low-Speed Peripheral Clock (LSPCLK and PERx.LSPCLK)

The SCI, SPI, and McBSP modules can communicate at bit rates that are much slower than the CPU
frequency. These modules are connected to a shared clock divider, which generates a low-speed peripheral
clock (LSPCLK) derived from SYSCLK. LSPCLK uses a /4 divider by default, but the ratio can be changed via
the LOSPCP register. Each SCI, SPI, and McBSP module's clock (PERx.LSPCLK) can be gated independently
via the PCLKCRx registers.

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3.7.3.5 USB Auxiliary Clock (AUXPLLCLK)

The USB module requires a fixed 60 MHz clock for bit sampling. Since the main system clock is usually not a
multiple of 60 MHz, the correct frequency cannot be achieved with a simple divider. Instead, the USB clock is
provided through an auxiliary clock path (AUXPLLCLK), which can use an independent clock source and PLL to
generate the correct frequency.
USB clock tolerances are very tight. As stated in section 7.1.11 of the USB 2.0 specification, low-speed devices
(1.50 Mb/s) have a tolerance of +/- 1.5% , while high-speed devices (12.000 Mb/s) have a tolerance of +/-
0.25%. Typically these tolerances are achieved by using an external crystal or resonator as the source for
AUXOSCCLK.
3.7.3.6 CAN Bit Clock
The required frequency tolerance for the CAN bit clock depends on the bit timing setup and network
configuration, and can be as tight as 0.1%. Since the main system clock (in the form of PERx.SYSCLK) may not
be precise enough, the bit clock can also be connected to XTAL or AUXCLKIN via the CLKSRCCTL2 register.
There is an independent selection for each CAN module.
3.7.3.7 CPU Timer2 Clock (TIMER2CLK)
CPU timers 0 and 1 are connected to PERx.SYSCLK. Timer 2 is connected to PERx.SYSCLK by default, but
may also be connected to INTOSC1, INTOSC2, XTAL, or AUXPLLCLK via the TMR2CLKCTL register. This
register also provides a separate pre-scale divider for timer 2. If a source other than SYSCLK is used, the
SYSCLK frequency must be at least twice the source frequency to ensure correct sampling. Each CPU has its
own independent CPU timers and TMR2CLKCTL register.
The main reason to use a non-SYSCLK source would be for internal frequency measurement. In most
applications, timer 2 will run off of the SYSCLK.
3.7.4 External Clock Output (XCLKOUT)
It is sometimes necessary to observe a clock directly for debug and testing purposes. The external clock output
(XCLKOUT) feature supports this by connecting a clock to an external pin, GPIO73. The available clock sources
are PLLSYSCLK, PLLRAWCLK, CPU1.SYSCLK, AUXPLLRAWCLK, CPU2.SYSCLK, ,INTOSC1, and INTOSC2.
To use XCLKOUT, first select the clock source via the CLKSRCCTL3 register. Next, select the desired
output divider via the XCLKOUTDIVSEL register. Finally, connect GPIO73 to mux channel 3 using the GPIO
configuration registers.
3.7.5 Clock Connectivity
Table 3-6 provide details on the clock connections of every module present in the device.
Table 3-6. Clock Connections Sorted by Clock Domain
Clock Domain CPU1 Subsystem CPU2 Subsystem Shared Modules
CPUx.CPUCLK CPU1 CPU2
CPU1VCRC CPU2.VCRC
CPU1.FPU CPU2.FPU
CPU1.TMU CPU2.TMU
CPU1.Flash CPU2.Flash
CPU1.DCSM CPU2.DCSM
CPU1.HWBIST CPU2.HWBIST

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Table 3-6. Clock Connections Sorted by Clock Domain (continued)

Clock Domain CPU1 Subsystem CPU2 Subsystem Shared Modules
CPUx.SYSCLK CPU1.ePIE CPU2.ePIE
CPU1.LS0 - LS7 RAMs CPU2.LS0 - LS7 RAMs
CPU1.M0 - M1 RAMs CPU2.M0 - M1 RAMs
CPU1.D0 - D1 RAMs CPU2.D0 - D1 RAMs
CPU1.BootROM CPU2.BootROM
CPU1.CLA1 Message RAMs CPU2.CLA1 Message RAMs
CPU1.Timer0-2 CPU2.Timer0-2
CPU1.DMA CPU2.DMA
CPU1.XINT CPU2.XINT
CPU1.CLA1 CPU2.CLA1
CPU1.BGCRC CPU2.BGCRC
CPU1.ERAD CPU2.ERAD
CPU1.CM Message RAMs CPU2.CM Message RAMs
EMIF2
PLLSYSCLK CPU1.NMIWD CPU2.NMIWD GS0 - GS15 RAMs
GPIO Input Sync and Qual
IPC
CPU1 & CPU2 MSG RAMs
XBARS
EMIF1
AnalogSubsys
EPWM
System Control Registers
PERx.SYSCLK USB ADC
CMPSS
DAC
ePWM & HRPWM
eCAP
eQEP
I2C
McBSP
SDFM
FSI
PMBUS
HRCAL
SPI
SCI
DCC
CAN
PERx.LSPCLK McBSP
SCI
SPI
CAN Bit Clock CAN
AUXPLLCLK USB
WDCLK (INTOSC1) CPU1.Watchdog CPU2.Watchdog

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3.7.6 PLL/AUXPLL
The PLL/AUXPLL is responsible for synthesizing an output frequency from the input clock (from the oscillator);
Figure 3-10 shows a simple block diagram of the PLL/AUXPLL. The PLL/AUXPLL divides the reference input
for a lower frequency input into the PLL/AUXPLL by (REFDIV+1). Then multiplies this internal frequency by
IMULT to get the VCO output clock. The PLL/AUXPLL output is divided by (ODIV+1) to generate PLLRAWCLK/
AUXPLLRAWCLK which is further divided by SYSCLKDIVSEL.PLLSYSCLKDIV/AUXCLKDIVSEL.AUXPLLDIV
to generate PLLSYSCLK/AUXCLK

SYSPLL / AUXPLL

OSCCLK/ INTCLK/ VCOCLK/ PLLRAWCLK/

AUXOSCCLK ÷ AUXINTCLK AUXVCOCLK ÷ AUXPLLRAWCLK
VCO
(REFDIV+1) (ODIV+1)

÷
IMULT

B15%%.- +/7.6
fPLLRAWCLK = ×
(4'(&+8 +1) (1&+8 +1)

B#7: 15%%.- +/7.6

fAUXPLLRAWCLK = (4'(&+8 +1)
× (1&+8+1)

Figure 3-10. PLL/AUXPLL

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3.7.6.1 Choosing PLL Settings

There are two PLLs (SYSPLL and AUXPLL) and equations shown in Figure 3-10 should be used to configure
respective PLL
IMULT is the integer value of the multiplier.
REFDIV is the reference divider for the OSCCLK/AUXOSCCLK.
ODIV is the output divider of the PLLRAWCLK/AUXPLLRAWCLK.
PLLSYSCLKDIV is the system clock divider.
AUXPLLDIV is the auxiliary clock divider.
For the permissible values of the multipliers and dividers, see the documentation for their respective registers.
Many combinations of multiplier and divider can produce the same output frequency. However, the product of the
reference clock frequency and the multiplier (known as the VCO frequency) must be in the range specified in the
data manual.

Note
The system clock frequency (PLLSYSCLK) may not exceed the limit specified in the datasheet. This
limit does not allow for oscillator tolerance.

The clock source and PLL configuration registers are shared between the two CPUs (CPU1 and CPU2).
Register access is controlled by way of a semaphore, which is described in the Interprocessor Communication
(IPC) chapter.
3.7.6.2 System Clock Setup
Once the application requirements are understood, a specific clock configuration can be determined. The default
configuration is for INTOSC2 to be used as the system clock (PLLSYSCLK) with a divider of 1. The following
procedure should be used to set up the desired application configuration:
Refer to your device SysCtl_setClock() function inside C2000Ware installation for an example.
Recommended sequence to set up the system PLL:
1. Bypass the PLL by clearing SYSPLLCTL1[PLLCLKEN] and wait for at least 120 CPU clock cycles by adding
120 NOP instructions.
2. Power down the PLL by writing to SYSPLLCTL1.PLLEN = 0 and wait for at least 60 CPU clock cycles by
adding 60 NOP instructions.
3. Select the reference clock source (OSCCLK) by writing to CLKSRCCTL1.OSCCLKSRCSEL and wait for at
least 300 CPU clock cycles by adding 300 NOP instructions.
4. Set the system clock divider to "/1" to ensure the fastest PLL configuration by clearing
SYSCLKDIVSEL[ PLLSYSCLKDIV].
5. Set the IMULT, REFDIV & ODIV simultaneously by writing 32-bit value in SYSPLLMULT at once. This will
automatically enable the PLL. Be sure the settings for multiplier and dividers do not violate the frequency
specifications as defined in the data sheet.
6. Wait for PLL to lock by polling for lock status bit to go high, that is, SYSPLLSTS.LOCKS = 1
7. Configure DCC with reference clock as OSCCLK and clock under measurement as PLLRAWCLK, and verify
the frequency of the PLL. If the frequency is out of range, do not enable PLLRAWCLK as SYSCLK, stop
here and troubleshoot. Refer to DCC chapter for more information on its configuration and usage.
8. If the PLLRAWCLK is within the valid range, then set the system clock divider one setting higher than the
final desired value. For example ClkCfgRegs.SYSCLKDIVSEL.bit.PLLSYSCLKDIV = divsel + 1. This limits
the current increase when switching to the PLL.
9. Switch to the PLL as the system clock by setting SYSPLLCTL1[PLLCLKEN] and wait for 200 PLLSYSCLK
cycles for current to stabilize by adding 200 NOP instructions.
10. Change the system clock divider (PLLSYSCLKDIV) to the appropriate value.

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Note
1. SYSPLL must be bypassed and powered down manually before changing the OSCCLK source.
2. At least 120 CPU clock cycles delay is needed after bypassing PLL, that is,
SYSPLLCTL1.PLLCLKEN=0.
3. At least 60 CPU clock cycles delay is needed after PLL is powered down, that is,
SYSPLLCTL1.PLLEN=0.
4. At least 300 CPU clock cycles delay is needed after OSSCLK source is changed.
5. PLL SLIP bit is not supported. DCC should be used to check the validity of the PLL clock. This
feature is included as part of SysCtl_setClock() function inside C2000Ware.

3.7.6.3 USB Auxiliary Clock Setup

Refer to your device SysCtl_setAuxClock() function inside C2000Ware installation for an example.
If USB functionality is needed, the auxiliary clock (AUXPLLCLK) must be configured to produce 60 MHz. The
procedure is similar to the system clock setup:
1. Bypass the PLL by clearing AUXPLLCTL1[PLLCLKEN] and wait for at least 120 CPU clock cycles by adding
120 NOP instructions..
2. Power down the PLL by writing to AUXPLLCTL1.PLLEN=0 and wait for at least 60 CPU clock cycles by
adding 60 NOP instructions.
3. Select the reference clock source (AUXOSCCLK) by writing to CLKSRCCTL2.AUXOSCCLKSRCSEL and
wait for at least 60 CPU clock cycles by adding 60 NOP instructions.
4. Set the IMULT, REFDIV & ODIV simultaneously by writing 32-bit value in AUXPLLMULT at once. This will
automatically enable the PLL. Be sure the settings for multiplier and dividers do not violate the frequency
specifications as defined in the data sheet.
5. Wait for PLL to lock by polling for lock status bit to go high (AUXPLLSTS.LOCKS = 1)
6. Configure DCC with reference clock as AUXOSCCLK and clock under measurement as AUXPLLRAWCLK,
and verify the frequency of the PLL. If the frequency is out of range, stop here and troubleshoot. Refer to
DCC chapter for more information on its configuration and usage.
7. Connect the auxiliary PLL output clock (AUXPLLRAWCLK) to AUXPLLCLK by writing a 1 to
AUXPLLCTL1.PLLCLKEN.
The auxiliary clock configuration can be changed at run time. Changing the AUXOSCCLK source will
automatically bypass the PLL and set the multiplier to zero. Changing the multiplier from one non-zero value to
another will temporarily bypass the PLL until it re-locks.

Note
1. AUXPLL must be bypassed and powered down manually before changing the AUXOSCCLK
source.
2. At least 120 CPU clock cycles delay is needed after bypassing PLL, that is,
AUXPLLCTL1.PLLCLKEN = 0.
3. At least 60 CPU clock cycles delay is needed after PLL is powered down, that is,
AUXPLLCTL1.PLLEN = 0.
4. At least 60 CPU clock cycles delay is needed after AUXOSSCLK source is changed.
5. AUXPLL SLIP bit is not supported. DCC should be used to check the validity of the AUXPLL
clock. This feature is included as part of SysCtl_setAuxClock() function inside C2000Ware.

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3.7.6.4 SYS PLL / AUX PLL Bypass

If the application requires the PLL clock to be bypassed from the system, then the application needs to configure
SYSPLLCTL1.PLLCLKEN=0 or AUXPLLCTL1.PLLCLKEN=0. It takes up to 120 CPU clock cycles before the
bypass is effective. In the meantime, if PLLSYSCLKDIV / AUXPLLDIV is reduced to a lower value (for example,
from /2 to /1 or /4 to /2), the device may be clocked above the maximum rated frequency and can lead to
unpredictable device behavior. Hence, a delay of 120 CPU clock cycles is required after bypassing the PLL from
the enable state, that is, going from PLLCLKEN=1 to PLLCLKEN=0.
3.7.7 Clock (OSCCLK) Failure Detection
To achieve safety diagnostic, Missing Clock Detection (MCD) can be used.
Table 3-7 lists the details.
Table 3-7. Clock Source (OSCCLK) Failure Detection
Clock Failure Time for Detection
Clocks Detected Limitations
Detection Circuitry (in Cycles)
Missing Clock Detection (MCD) INTOSC2, XTAL/X1 8192 INTOSC1 cycles Cannot detect INTOSC1 clock failure.

3.7.7.1 Missing Clock Detection Logic

The missing clock detect (MCD) logic detects OSCCLK failure, using INTOSC1 as the reference clock source.
This circuit only detects complete loss of OSCCLK and doesn’t do any detection of frequency drift on the
OSCCLK.
This circuit monitors the OSCLK (primary clock) using the 10 MHz clock provided by the INTOSC1 (secondary
clock) as a backup clock. This circuit functions as:
1. The primary clock (OSCCLK) clock keeps ticking a 7-bit counter (named as MCDPCNT). This counter is
asynchronously reset with XRSn.
2. The secondary clock (INTOSC1) clock keeps ticking a 13-bit counter (named as MCDSCNT). This counter is
asynchronously reset with XRSn.
3. Each time MCDPCNT overflows, the MCDSCNT counter is reset. Thus, if OSCCLK is present or not slower
than INTOSC1 by a factor of 64, MCDSCNT never overflows.
4. If OSCCLK stops for some reason or is slower than INTOSC1 by at least a factor of 64, the MCDSCNT
overflows and a missing clock condition is detected on OSCCLK.
5. The above check is continuously active, unless the MCD is disabled using MCDCR register (by making the
MCLKOFF bit 1).
6. If the circuit ever detects a missing OSCCLK, the following occurs:
• The MCDSTS flag is set.
• The MCDSCNT counter is frozen to prevent further missing clock detection.
• The CLOCKFAIL signal goes high, which generates TRIP events to PWM modules and fires NMIs to
CPU1.NMIWDand CPU2.NMIWD.
• PLL is forcefully bypassed and OSCCLK source is switched to INTOSC1 (System Clock Frequency =
INTOSC1 Freq (10MHz)/SYSDIV). PLLMULT is zeroed out automatically in this case.
• While the MCDSTS bit is set, the OSCCLKSRCSEL bits have no effect and OSCCLK is forcefully
connected to INTOSC1.
• PLLRAWCLK going to the system is switched to INTOSC1 automatically.
7. If the MCLKCLR bit is written (this is a W=1 bit), MCDSTS bit is cleared and OSCCLK source is decided
by the OSCCLKSRCSEL bits. Writing to MCLKCLR also clears the MCDPCNT and MCDSCNT counters to
allow the circuit re-evaluate missing clock detection. If the user wants to lock the PLL after missing clock
detection, switch the clock source to INTOSC1 (using OSCCLKSRCSEL register), do a MCLKCLR, and
re-lock the PLL.
8. The MCD is enabled at power up.
Figure 3-11 shows the missing clock logic functional flow.

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Secondary Clock CLOCKFAIL

INTOSC1 Missing
Clock INTOSC1
Detect
Primary Clock (MCD)
Logic
Low
OSCCLK Power
INTOSC2 Source Mode
Select OSCCLK Ckt
Ckt
X1/X2

CLKSRCCTL1.OSCCLRSRCSEL /1,
Switch
SYSPLL /2,
Ckt
/4
Mux
PLLRAWCLK ..
(glitch- PLLSYSCLK
/124
PLL Locking free)
/126
Registers Control
Ckt

Clock Dividers

Clock Sources SYSPLLCTL1/2/3,

SYSPLLMULT,
SYSPLLSTS

Figure 3-11. Missing Clock Detection Logic

Note
On a complete clock failure when OSCCLK is dead, it may take a maximum time of 8192 INTOSC1
cycles (that is, 0.8192 ms) before CLOCKFAIL signal goes high, after which:
• NMI is generated
• OSCCLK is switched to INTOSC1
• PWM Trip happens

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3.8 Clock Configuration Semaphore

Both CPUs can access the PLL and peripheral clock configuration registers. The clock configuration semaphore
allows one CPU to access the registers without being interrupted by the other CPU.
The clock configuration semaphore is implemented as a two-bit field in a register with special write protections.
This register requires a key field to be written at the same time as the semaphore bits. The possible semaphore
states are:

00 or 11 Either CPU writes to the semaphore. CPU1 has control of the clock configuration registers by
default. 00 is the reset state.
01 CPU2 has exclusive control of the clock configuration registers and exclusive write access to
the semaphore.
10 CPU1 has exclusive control of the clock configuration registers and exclusive write access to
the semaphore.

Each CPU is only allowed to take control of the clock configuration registers for itself. However, CPU1 can force
both semaphores into the default state (00) at any time by putting CPU2 into reset. Figure 3-12 shows the
allowed states and state transitions.
CPU1 should write 10 to gain CPU2 should write 01 to gain
mastership of the clock configuration Semaphore state 00 or 11 mastership of the clock configuration
registers. registers.
Clock configuration registers
are controlled by CPU1
CPU1 should write 00 to relinquish
Default at reset CPU2 should write 00 to relinquish
mastership once configuration is
mastership once configuration is
complete.
complete.

Semaphore state 10 Semaphore state 01

Not allowed
Clock configuration registers Clock configuration registers
are controlled by CPU1 Not allowed are controlled by CPU2

CPU2 cannot take control of the pump in this CPU1 cannot take control of the pump in this
state state

Figure 3-12. Clock Configuration Semaphore (CLKSEM) State Transitions

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3.9 32-Bit CPU Timers 0/1/2

This section describes the three 32-bit CPU-Timers (TIMER0/1/2) shown in Figure 3-13.
CPU-Timer2 is reserved for real-time operating system uses (for example, TI-RTOS), but if CPU-Timer2 is not
used by real-time operating systems then, CPU-Timer2 can also be used for other applications. The CPU-Timer0
and CPU-Timer1 run off of SYSCLK. The CPU-Timer2 normally runs off of SYSCLK, but can also use INTOSC1,
INTOSC2, XTAL, and AUXPLLCLK. The CPU-Timer interrupt signals (TINT0, TINT1, TINT2) are connected as
shown in Figure 3-14.

Reset
Timer reload

16-bit timer divide-down

32-bit timer period
TDDRH:TDDR
PRDH:PRD

16-bit prescale counter

SYSCLKOUT
PSCH:PSC
TCR.4 32-bit counter
(Timer start status) Borrow TIMH:TIM

Borrow

TINT

Figure 3-13. CPU-Timers

INT1 TINT0
to PIE TIMER0
INT12

28x
CPU
TINT1
INT13 TIMER1

TINT2
INT14 TIMER2

A. The timer registers are connected to the memory bus of the C28x processor.
B. The CPU Timers are synchronized to SYSCLKOUT.

Figure 3-14. CPU-Timer Interrupts Signals and Output Signal

The general operation of the CPU-Timer is as follows:

• The 32-bit counter register, TIMH:TIM, is loaded with the value in the period register PRDH:PRD.
• The counter decrements once every (TPR[TDDRH:TDDR]+1) SYSCLKOUT cycles, where TDDRH:TDDR is
the timer divider.
• When the counter reaches 0, a timer interrupt output signal generates an interrupt pulse.
The registers listed in Section 3.16 are used to configure the timers.

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3.10 Watchdog Timers

The watchdog module generates an output pulse 512 watchdog clocks (WDCLKs) wide whenever the 8-bit
watchdog up counter has reached its maximum value. The watchdog clock source is INTOSC1. Software must
periodically write a 0x55 + 0xAA sequence into the watchdog key register to reset the watchdog counter. The
counter can also be disabled. Figure 3-15 shows the various functional blocks within the watchdog module.
WDCR.WDPRECLKDIV WDCR.WDPS WDCR.WDDIS

WDCNTR

WDCLK 8-bit
(INTOSC1) WDCLK Watchdog Watchdog Overflow 1-count
Divider Prescaler Counter delay

SYSRSn
Clear
Count

WDWCR.MIN
WDKEY (7:0)
Out of Window Watchdog
Watchdog Good Key
Window
Key Detector Detector
WDCR(WDCHK(2:0))
55 + AA

Bad Key

WDRSTn Generate
1 0 1 512-WDCLK Watchdog Time-out
WDINTn Output Pulse

SCSR.WDENINT

Figure 3-15. CPU Watchdog Timer Module

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3.10.1 Servicing the Watchdog Timer

The watchdog counter (WDCNTR) is reset when the proper sequence is written to the WDKEY register before
the 8-bit watchdog counter overflows. The WDCNTR is reset-enabled when a value of 0x55 is written to the
WDKEY. When the next value written to the WDKEY register is 0xAA, then the WDCNTR is reset. Any value
written to the WDKEY other than 0x55 or 0xAA causes no action. Any sequence of 0x55 and 0xAA values can
be written to the WDKEY without causing a system reset; only a write of 0x55 followed by a write of 0xAA to the
WDKEY resets the WDCNTR.
Table 3-8. Example Watchdog Key Sequences
Step Value Written to WDKEY Result
1 0xAA No action
2 0xAA No action
3 0x55 WDCNTR is enabled to be reset if next value is 0xAA.
4 0x55 WDCNTR is enabled to be reset if next value is 0xAA.
5 0x55 WDCNTR is enabled to be reset if next value is 0xAA.
6 0xAA WDCNTR is reset.
7 0xAA No action
8 0x55 WDCNTR is enabled to be reset if next value is 0xAA.
9 0xAA WDCNTR is reset.
10 0x55 WDCNTR is enabled to be reset if next value is 0xAA.
11 0x32 Improper value written to WDKEY.
No action, WDCNTR no longer enabled to be reset by next 0xAA.
12 0xAA No action due to previous invalid value.
13 0x55 WDCNTR is enabled to be reset if next value is 0xAA.
14 0xAA WDCNTR is reset.

Step 3 in Table 3-8 is the first action that enables the WDCNTR to be reset. The WDCNTR is not actually reset
until step 6. Step 8 again re-enables the WDCNTR to be reset and step 9 resets the WDCNTR. Step 10 again
re-enables the WDCNTR to be reset. Writing the wrong key value to the WDKEY in step 11 causes no action,
however the WDCNTR is no longer enabled to be reset and the 0xAA in step 12 now has no effect.
If the watchdog is configured to reset the device, then a WDCNTR overflow or writing the incorrect value to the
WDCR[WDCHK] bits resets the device and sets the watchdog flag (WDRSn) in the reset cause register (RESC).
After a reset, the program can read the state of this flag to determine whether the reset was caused by the
watchdog. After doing this, the program must clear WDRSn to allow subsequent watchdog resets to be detected.
Watchdog resets are not prevented when the flag is set.
3.10.2 Minimum Window Check
To complement the timeout mechanism, the watchdog also contains an optional "windowing" feature that
requires a minimum delay between counter resets. This can help protect against error conditions that bypass
large parts of the normal program flow but still include watchdog handling.
To set the window minimum, write the desired minimum watchdog count to the WDWCR register. This value will
take effect after the next WDKEY sequence. From then on, any attempt to service the watchdog when WDCNTR
is less than WDWCR will trigger a watchdog interrupt or reset. When WDCNTR is greater than or equal to
WDWCR, the watchdog can be serviced normally.
At reset, the window minimum is zero, which disables the windowing feature.

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3.10.3 Watchdog Reset or Watchdog Interrupt Mode

The watchdog can be configured in the SCSR register to either reset the device (WDRST) or assert an interrupt
(WDINT), if the watchdog counter reaches the maximum value. The behavior of each condition is:
• Reset mode:
If the watchdog is configured to reset the device, then the WDRST signal pulls the device reset (XRS) pin low
for 512 OSCCLK cycles when the watchdog counter reaches the maximum value.
• Interrupt mode:
When the watchdog counter expires, the watchdog counter asserts an interrupt by driving the WDINT signal
low for 512 OSCCLK cycles. The falling edge of WDINT triggers a WAKEINT interrupt in the PIE, if the
interrupt is enabled. Because the PIE is edge-triggered, re-enabling the WAKEINT while WDINT is active
does not produce a duplicate interrupt.
To avoid unexpected behavior, software must not change the configuration of the watchdog while WDINT is
active. For example, changing from interrupt mode to reset mode while WDINT is active immediately resets
the device. Disabling the watchdog while WDINT is active causes a duplicate interrupt if the watchdog is
later re-enabled. If a debug reset is issued while WDINT is active, the reset cause register (RESC) shows a
watchdog reset. The WDINTS bit in the SCSR register can be read to determine the current state of WDINT.

3.10.4 Watchdog Operation in Low Power Modes

In IDLE mode, the watchdog interrupt ( WDINT) signal can generate an interrupt to the CPU to take the CPU out
of IDLE mode. As with any other peripheral, the watchdog interrupt will trigger a WAKEINT interrupt in the PIE
during IDLE mode. User software must determine which peripheral caused the interrupt.
In STANDBY mode, all of the clocks to the peripherals are turned off within the CPU subsystem. The only
peripheral that remains functional is the watchdog since the watchdog module runs off the oscillator clock
(OSCCLK). The WDINT signal is fed to the Low Power Modes (LPM) block so that it can be used to wake the
CPU from STANDBY low power mode. This feature is enabled by setting LPMCR.WDINTE = 1. See Section
3.11 for details.
Note: If the watchdog interrupt is used to wake-up from an IDLE or STANDBY low power mode condition,
software must make sure that the WDINT signal goes back high before attempting to reenter the IDLE or
STANDBY mode. The WDINT signal will be held low for 512 OSCCLK cycles when the watchdog interrupt
is generated. The current state of WDINT can be determined by reading the watchdog interrupt status bit
(WDINTS) bit in the SCSR register. WDINTS follows the state of WDINT by two SYSCLKOUT cycles.
3.10.5 Emulation Considerations
The watchdog module behaves as follows under various debug conditions:

CPU Suspended: When the CPU is suspended, the watchdog clock (WDCLK) is suspended
Run-Free Mode: When the CPU is placed in run-free mode, then the watchdog module resumes
operation as normal.
Real-Time Single-Step Mode: When the CPU is in real-time single-step mode, the watchdog clock (WDCLK)
is suspended. The watchdog remains suspended even within real-time
interrupts.
Real-Time Run-Free Mode: When the CPU is in real-time run-free mode, the watchdog operates as normal.

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3.11 Low Power Modes

This device has two clock-gating, low-power modes. All low-power modes are entered by setting the LPMCR
register and executing the IDLE instruction. More information about this instruction can be found in the
TMS320C28x CPU and Instruction Set Reference Guide.
Low-power modes should not be entered into while a Flash program or erase is ongoing.
The application should verify the following before entering STANDBY:
1. Check the value of the GPIODAT register of the pin selected for STANDBY(GPIOLPMSEL0/1) prior to
entering the Low-Power mode to ensure that the wake event has not already been asserted.
2. The LPMCR.QUALSTDBY register should be set to a value greater than the ratio of INTOSC1/PLLSYSCLK
to ensure proper wake up.
3.11.1 IDLE
IDLE is a standard feature of the C28x CPU. In this mode, the CPU clock is gated while all peripheral clocks are
left running. IDLE can thus be used to conserve power while a CPU is waiting for peripheral events. When one
CPU is in IDLE, there is no effect on the other CPU subsystem.
Any enabled interrupt wakes up the CPU from IDLE mode.
To enter IDLE mode, set LPMCR.LPM to 0x0 and execute the IDLE instruction.
3.11.2 STANDBY
STANDBY is a more aggressive low-power mode that gates both the CPU clock and any peripheral clocks
derived from the CPU SYSCLK. The watchdog, however, is left active. Like IDLE, this mode affects only one
CPU subsystem. The other CPU subsystem and all of the peripherals are unaffected. STANDBY is best used
for an application where the wake-up signal comes from an external system (or CPU subsystem) rather than a
peripheral input.
An NMI (or optionally) a watchdog interrupt or a configured GPIO can wake the CPU from STANDBY mode.
Each GPIO from GPIO0-63 can be configured to wake the CPU when the GPIO are driven active low. Upon
wakeup, the CPU receives the WAKEINT interrupt if configured.
IPC interrupt 1 (flag 0), an NMI fired to the other CPU, or (optionally) a watchdog interrupt, wakes up the CPU
subsystem from STANDBY mode. Any of GPIO0-63 can also be configured to wake up the subsystem when the
GPIO are driven active low. Upon wake up, the CPU receives a WAKEINT interrupt, even if the CPU was woken
by an IPCINT1 signal.
To enter STANDBY mode:
1. Set LPMCR.LPM to 0x1.
2. Enable the WAKEINT interrupt in the PIE.
3. For watchdog interrupt wakeup, set LPMCR.WDINTE to 1 and configure the watchdog to generate
interrupts.
4. For GPIO wakeup, set GPIOLPMSEL0 and GPIOLPMSEL1 to connect the chosen GPIOs to the LPM
module, and set LPMCR.QUALSTDBY to select the number of OSCCLK cycles for input qualification.
5. Execute the IDLE instruction to enter STANDBY.
To wake up from Standby mode:
1. Configure the desired GPIO to trigger the wakeup.
2. Drive the selected GPIO signal low; the signal must remain low for the number of OSCCLK cycles specified
in the QUALSTDBY bits in the LPMCR register. If the signal is sampled high during this period, the count
restarts.
At the end of the qualification period, the PLL enables the CLKIN to the CPU and the WAKEINT interrupt is
latched in the PIE block. The WAKEINT interrupt can also triggered by IPCINT1 sent from the other CPU and a
watchdog interrupt.

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The CPU is now out of STANDBY mode and can resume normal execution.
If CPU2 is in STANDBY mode, writing a 1 to the RESET bit of the CPU2RESCTL register has no effect. CPU2
can be reset by any chip-level reset (POR, XRSn, CPU1.WDRSn, or CPU1.NMIWDRSn). Alternately, CPU2 can
be woken up by any configured wake-up event.
If CPU2 is in STANDBY mode and the debugger is connected, executing a debug reset on CPU2 has no effect.
To wake up the CPU2 with the debugger, Click Run, Single Step, or Step over in the Debug toolbar. CCS IDE
prompts the user requesting to bring the CPU out of the low-power mode. Click Yes. This wakes up CPU2 from
STANDBY and continues execution.
3.12 Memory Controller Module
This device has CPU1 subsystem, CPU2 subsystem, and CM subsystem. This section describes the memory
controller used for CPU1 and CPU2 subsystem.
The different RAMs available on CPU1 and CPU2 subsystem have different characteristics. Some are:
• Dedicated to each CPU (M0, M1, and Dx RAMs),
• Shared between the CPU and a CLA (LSx RAM),
• Shared between the CPU and DMA of both subsystems (GSx RAM), and
• Used to send and receive messages between processors (MSGRAM).
• Used to exchange data between CLA and DMA
All these RAMs are highly configurable to achieve control for write access and fetch access from different
masters. There are also RAMs - called IPC MSGRAMs - that are used for interprocessor communication. All
RAMs are enabled with the ECC or parity feature (both data and address). Some of the dedicated memories
are secure memory as well. Refer to Chapter 6 for more details. Each RAM has a controller that takes care
of the access protection/security related checks and ECC/Parity features for that RAM. Figure 3-16 shows the
configuration of these RAMs.

CPU1 LSx RAM GSx RAM CPU2 LSx RAM

CPU1 To CPU2 To
CPU1 CLA1 CPU1 CLA1 CPU2 CLA1 CPU2 CLA1
MSGRAM MSGRAM

CPU1 CLA1 To CPU2 CLA1 To

CPU1 MSGRAM CPU2 MSGRAM
CPU1 DMA CPU2 DMA
CPU1 CPU2

CPU1 M0 RAM CPU2 M0 RAM

CLA-DMA CPU2 TO CPU1 CLA-DMA

MSGRAM MSGRAM MSGRAM
CPU1 M1 RAM CPU2 M1 RAM

CPU1 TO CPU2
MSGRAM
CPU1 Dx RAM CPU2 Dx RAM

Figure 3-16. Memory Architecture

Note
All RAMs on these devices are SRAMs.

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3.12.1 Functional Description

This section further defines and discusses the dedicated RAMs, shared RAMs, and MSG RAMs on this device.
3.12.1.1 Dedicated RAM (Dx RAM)
Each CPU subsystem has four dedicated RAM blocks: M0, M1, D0, and D1. M0/M1 memories are small blocks
of memory that are tightly coupled with the CPU. Only the CPU has access to these memories. No other masters
(including DMA) have any access to these memories.
All dedicated RAMs have the ECC feature. All dedicated memories are secure memory (except for M0/M1) and
have the access protection (CPU write protection/CPU fetch protection) feature. Each type of access protection
for each RAM block can be enabled/disabled by configuring the specific bit in the access protection register,
allocated to each subsystem (DxACCPROT).
3.12.1.2 Local Shared RAM (LSx RAM)
RAM blocks that are dedicated to each subsystem and are accessible to the respective CPU and CLA only,
are called local shared RAMs (LSx RAMs). All such memories are secure memory and have the ECC feature.
By default, these memories are dedicated to the CPU only, and the user can choose to share these memories
with the CLA by appropriately configuring the MSEL_LSx bit field in the LSxMSEL register. Further, when these
memories are shared between the CPU and CLA, the user can choose to use these memories as CLA program
memory by configuring the CLAPGM_LSx bit field in the LSxCLAPGM registers. CPU access to all memory
blocks, which are programmed as CLA program memory, are blocked.
All these RAMs have the access protection (CPU write and CPU fetch) feature. Each type of access protection
for each RAM block can be enabled or disabled by configuring the specific bit in the local shared RAM access
protection registers, mapped to each CPU subsystem. Table 3-9 shows the LSx RAM features.
Table 3-9. Local Shared RAM
MSEL_LSx CLAPGM_LSx CPUx Allowed CPUx.CLA1 Allowed Comment
Access Access
00 X All - LSx memory is configured as CPU dedicated RAM
01 0 All Data Read LSx memory is shared between CPU and CLA1
Data Write
01 1 Emulation Read Fetch Only LSx memory is CLA1 program memory
Emulation Write Emulation Read
Emulation Write

3.12.1.3 Global Shared RAM (GSx RAM)

RAM blocks that are accessible from both the CPU and their respective DMA are called global shared RAMs
(GSx RAMs). Each shared RAM can be owned by either CPU subsystem based on the configuration of their
respective bits (one bit for each GSx memory) in the GSxMSEL register. When a particular GSx RAM block
is owned by the CPU1 subsystem, CPU1 and CPU1.DMA have full access to that RAM block, whereas CPU2
and CPU2.DMA have only read access to that RAM block (no fetch/write access). Similarly, when a particular
GSx RAM block is owned by the CPU2 subsystem, CPU1 and CPU1.DMA has only read access (no fetch/write
access) to that RAM block, whereas CPU2 and CPU2.DMA has full access to that RAM block. Table 3-10 shows
the features of the GSx RAM.
Table 3-10. Global Shared RAM
GSxMSEL CPU1 CPU1 CPU1 CPU1.DMA CPU1.DMA CPU2 CPU2 CPU2 CPU2.DMA CPU2.DMA
Fetch Read Write Read Write Fetch Read Write Read Write
0 Yes Yes Yes Yes Yes No Yes No Yes No
1 No Yes No Yes No Yes Yes Yes Yes Yes

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Note
Emulation/Debugger access is allowed from both the CPUs, irrespective of the GSxMSEL setting.

Like other shared RAMs, these RAMs also have different levels of access protection that can be enabled or
disabled by configuring specific bits in the GSxACCPROT registers mapped in each subsystem.
Master select and access protection configuration for each GSx RAM block can be individually locked by the
user to prevent further update to these bit fields. The user can also choose to permanently lock the configuration
to individual bit fields by setting the specific bit fields in the GSxCOMMIT register (refer to the register description
for more details). Once configuration is committed for a particular GSx RAM block, it can not be changed further
until CPUx.SYSRS is issued. Only the CPU1 software can change the master select configuration by writing
into the GSxMSEL register, mapped on the CPU1. The GSxMSEL register, which is mapped to the CPU2
subsystem, is a status register that can only be used by CPU2 software to know the master ownership for each
GSx RAM block.
3.12.1.4 CPU Message RAM (CPU MSG RAM)
These RAM blocks can be used to share data between CPU1 and CPU2. Since these RAMs are used for
interprocessor communication, they are also called IPC RAMs. The CPU MSGRAMs have CPU and DMA
read and write access from its own CPU subsystem, and has CPU and DMA read only access from the other
subsystem.
This RAM has parity.
3.12.1.5 CLA Message RAM (CLA MSGRAM)
These RAM blocks can be used to share data between the CPU and CLA. The CLA has read and write access
to the "CLA to CPU MSGRAM." The CPU has read and write access to the "CPU to CLA MSGRAM." The CPU
and CLA both have read access to both MSGRAMs.
This RAM has parity.
3.12.1.6 CLA-DMA MSG RAM
These RAMs blocks can be used to share data between CLA and DMA. The CLA has read and write access to
the "CLA to DMA MSGRAM." The DMA has read and write access to the "DMA to CLA MSGRAM." The CLA
and DMA both have read access to both MSGRAMs.
3.12.1.7 Access Arbitration
For a shared RAM, multiple accesses can happen at a given time. The maximum number of accesses to any
shared RAM at any given time depends on the type of shared RAM. On this device, a combination of a fixed and
round robin scheme is followed to arbitrate multiple access at any given time. Accesses from the same masters
are arbitrated in a fixed priority manner, but the accesses from different masters are arbitrated using the round
robin scheme.
The following is the order of fixed priority for CPU accesses:
1. Data Write/Program Write
2. Data Read
3. Program Read/Program Fetch
The following is the order of fixed priority for CLA accesses:
1. Data Write
2. Data Read/Program Fetch
Figure 3-17 represents the arbitration scheme on global shared memories:

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Round Robin Arbitration

CPU1-DWRITE CPU1
Fixed Granted CPU1 Access
CPU1-DREAD Priority RR-CPU1
CPU1-PREAD/FETCH Arbiter

CPU1.DMA READ/WRITE

RR-CPU2.DMA RR-CPU1.DMA

CPU2-DWRITE
CPU2
CPU2-DREAD Fixed Granted CPU2 Access
Priority
CPU2-PREAD/FETCH Arbiter

RR-CPU2

CPU2.DMA READ/WRITE

Figure 3-17. Arbitration Scheme on Global Shared Memories

Figure 3-18 represents the arbitration scheme on local shared memories.

Round Robin Arbitration

CPU-DWRITE CPU
Fixed Granted CPU1 Access
CPU-DREAD
Priority
Arbiter RR-CPU
CPU-PREAD/FETCH

CLA-DWRITE CLA RR-CPU.CLA

Fixed
Priority Granted CLA Access
CLA-DREAD
Arbiter

Figure 3-18. Arbitration Scheme on Local Shared Memories

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3.12.1.8 Access Protection

All RAM blocks on both subsystems have different levels of protection. This feature allows the user to enable
or disable specific access to individual RAM blocks from individual masters. There is no protection for read
accesses, hence reads are always allowed from all the masters which have access to that RAM block.
The following sections describe the different kinds of protection available for RAM blocks on this device.
Note: For debug accesses, all the protections are disabled.
3.12.1.8.1 CPU Fetch Protection
A CPU has execution permission from a memory, only if that memory is dedicated to that CPU or the respective
subsystem is master for that memory (in case of GSx memory). When fetch accesses are allowed based on the
mastership, fetch accesses can be further protected by setting the FETCHPROTx bit of the specific register to
1. If fetch access is done by the CPU to a memory where CPU fetch protection is enabled, a fetch protection
violation occurs.
There are two types of fetch protection violations:
• Non-master CPU fetch protection violation
• Master CPU fetch protection violation
If a fetch access is made to a memory by a non-master CPU, the fetch access is called a non-master fetch
protection violation. If a fetch access is made to a dedicated or shared memory by the master CPU, and
FETCHPROTx is set to 1 for that memory, the violation is called a master CPU fetch protection violation.
If a fetch protection violation occurs, the violation results in an ITRAP for CPU. A flag gets set into the
appropriate access violation flag register, and the memory address for which the access violation occurred,
get latched into the appropriate CPU fetch access violation address register.
3.12.1.8.2 CPU Write Protection
A CPU has write permission to a memory only if that memory is dedicated to that CPU, or if the respective
subsystem is the master for that memory (in case of GSx memory). When write accesses are allowed based on
the mastership, write accesses can be further protected by setting the CPUWRPROTx bit of the specific register
to 1. If write access is done by a CPU to memory where the write access is protected, a write protection violation
occurs.
There are two types of CPU write protection violations:
• Non-master CPU write protection violation
• Master CPU write protection violation
If a write access is made to a dedicated or shared memory by the master CPU and CPUWRPROTx is set to
1 for that memory, the violation is called a master CPU write protection violation.
If a write protection violation occurs, write gets ignored, a flag gets set into the appropriate access violation flag
register, and the memory address for which the access violation occurred, gets latched into the appropriate CPU
write access violation address register. Also, an access violation interrupt is generated if enabled in the interrupt
enable register.
3.12.1.8.3 CPU Read Protection
For local shared RAM, if memory is shared between the CPU and the CLA, the CPU only has access if the
memory is configured as data RAM for the CLA. If the memory is programmed as program RAM, all the access
from the CPU, including a read, is blocked and the violation is considered as a non-master access violation.
If a read protection violation occurs, a flag gets set into the appropriate access violation flag register, and the
memory address for which the access violation occurred, gets latched into the appropriate CPU read access
violation address register. Also, if enabled in the interrupt enable register, an access violation interrupt is
generated.

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3.12.1.8.4 CLA Fetch Protection

If local shared RAM is configured as dedicated RAM for the CPU, or if the RAM is configured as data RAM for
the CLA, any fetch access from the CLA to that particular LSx RAM results in a CLA fetch protection violation,
which is a non-master access violation.
If a CLA fetch protection violation occurs, the violation results in a MSTOP, a flag gets set into the appropriate
access violation flag register, and the memory address for which the access violation occurred, gets latched into
the appropriate CLA fetch access violation address register. Also, an access violation interrupt is generated to
the master CPU if enabled in the interrupt enable register.
3.12.1.8.5 CLA Write Protection
If local shared RAM is configured as dedicated RAM for the CPU, or if the RAM is configured as program RAM
for the CLA, any data write access from the CLA to that particular LSx RAM results in a CLA write protection
violation, which is a non-master access violation. Similarly any data write access from CLA to CPUTOCLA or
DMATOCLA MSGRAM results in a CLA write protection violation, which is a non-master access violation.
If a CLA write protection violation occurs, write gets ignored, a flag gets set into the appropriate access violation
flag register, and the memory address for which the access violation occurred, gets latched into the appropriate
CLA write access violation address register. Also, an access violation interrupt is generated to the master CPU if
enabled in the interrupt enable register.
3.12.1.8.6 CLA Read Protection
If local shared RAM is configured as dedicated RAM for the CPU, or if the RAM is configured as program RAM
for the CLA, any data read access from the CLA to that particular LSx RAM results in a CLA read protection
violation, which is a non-master access violation.
If a CLA read protection violation occurs, a flag gets set into the appropriate access violation flag register, and
the memory address for which the access violation occurred, gets latched into the appropriate CLA read access
violation address register. Also, an access violation interrupt is generated to the master CPU if enabled in the
interrupt enable register.
3.12.1.8.7 DMA Write Protection
The CPU1 or CPU2 DMA has write permission to a GSx memory only if the respective subsystem is master for
that memory. When write accesses from a DMA are allowed based on the mastership, the write access can be
further protected by setting the DMAWRPROTx bit of a specific register to 1. If write access is done by the DMA
to protected memory, a write protection violation occurs.
There are two types of DMA write protection violations:
• Non-master DMA write protection violation (applicable to GSx RAMs and DMATOCLA MSGRAM)
• Master DMA write protection violation
If a write access is made to GSx memory by a non-master DMA, the write is called a non-master write protection
violation. If a write access is made to a dedicated or shared memory by a master DMA, and DMAWRPROTx is
set to 1 for that memory, the write is called a master DMA write protection violation.
If a DMA write protection violation occurs, the write gets ignored, a flag gets set into the appropriate access
violation flag register, and the memory address for which the access violation occurred gets latched into the
appropriate DMA write access violation address register. Also, an access violation interrupt is generated to the
respective CPU, if enabled in the interrupt enable register. These are dedicated registers for each subsystem.

Note 1: All access protections are ignored during debug accesses. Write access to a protected
memory go through when the write access is done by way of the debugger, irrespective of
the write protection configuration for that memory.

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Note 2: In the case of local shared RAM, if memory is shared between the CPU and the CLA, the
CPU only has access if the memory is configured as data RAM for the CLA. If the memory
is programmed as program RAM, all the access from the CPU (including read) and data
access from the CLA is blocked, and the violation is considered as a non-master access
violation. If the memory is configured as dedicated to the CPU, all access from the CLA is
blocked and the violation is considered a non-master access violation.

3.12.1.9 Memory Error Detection, Correction and Error Handling

These devices have memory error detection and correction features to satisfy safety standards requirements.
These requirements warrant the addition of detection mechanisms for finite dangerous failures.
In this device, all dedicated RAMs and LSx RAMs support error correction code (ECC) protection and other
shared RAMs have parity protection. The ECC scheme used is Single Error Correction Double Error Detection
(SECDED). The parity scheme used is even parity. ECC/Parity will cover the data bits stored in memory as well
as address.
ECC/Parity calculation is done inside the memory controller module and then calculated. ECC/Parity is written
into the memory along with the data. ECC/Parity is computed for 16-bit data; hence, for each 32-bit data, there
will be three 7-bit ECC codes (or 3-bit parity), two of which are for data and a third one for the address.
3.12.1.9.1 Error Detection and Correction
Error detection is done while reading the data from memory. The error detection is performed for data as well
as address. For parity memory, only a single-bit error gets detected, whereas in the case of ECC memory,
along with a single-bit error, a double-bit error also gets detected. These errors are called correctable error and
uncorrectable errors. The following are characteristics of these errors:
• Parity errors are always uncorrectable errors
• Single-bit ECC errors are correctable errors
• Double-bit ECC errors are uncorrectable errors
• Address ECC errors are also uncorrectable errors
Correctable errors get corrected by the memory controller module and then correct data is given back as read
data to the master. It is also written back into the memory to prevent double-bit error due to another single-bit
error at the same memory address.

Note
ECC/Parity for address is calculated for address offset only (based on RAM block size) of
corresponding 32-bit aligned address. In case of LSx RAM which are 4KB RAM block, only 11 LSB of
32-bit aligned address are used. So if address is 0x8F8F, address ECC (or Parity) will be calculated
for address 0x78E (11-bit offset of 32-bit aligned address). Similarly for 8KB RAM block,12-bit address
offset will be used.

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3.12.1.9.2 Error Handling

For each correctable error, the count in the correctable error count register increments by one. When the value
in this count register becomes equal to the value configured into the correctable error threshold register, an
interrupt is generated to the respective CPU, that is, if the interrupt is enabled in the correctable interrupt enable
register. The user needs to configure the correctable error threshold register based on the system requirements.
Also, the address for which the error occurred, gets latched into the master-specific status register and a flag
gets set. Each of these registers are dedicated for each CPU subsystem.
If there are uncorrectable errors, an NMI gets generated for the respective CPU. In this case, the address for
which the error occurred, also gets latched into the master-specific address status register, and a flag gets set.
Table 3-11 summarizes different error situations that can arise. These need to be handled appropriately in the
software, using the status and interrupt indications provided.
Table 3-11. Error Handling in Different Scenarios
Access Type Error Found In Error Type Status Indication Error Notification
Reads Data read from Uncorrectable Yes -CPUx/CPUx.DMA/CPUx.CLA1 NMI for CPUx access
memory Error CPU/DMA/CLA Read Error Address NMI for CPUx.DMA access
(Single-bit error for Register Data returned to CPUx/ NMI to CPU for CPUx.CLA1 access
Parity RAMs OR CPUx.DMA/CPUx.CLA1 is incorrect
Double bit Error for
ECC RAMs)
Reads Data read from Single-bit error for Yes - CPUx/CPUx.DMA CPU/DMA Interrupt when error counter reaches the
memory ECC RAMs Read Error Address Register Increment user programmable threshold for single
single error counter errors
Reads Address Address error Yes - CPUx/CPUx.DMA/CPUx.CLA1 NMI to CPU for CPUx access
CPU/DMA/CLA Read Address Error NMI to CPU for CPUx.DMA access
Register Data returned to CPUx/ NMI to CPU for CPUx.CLA1 access
CPUx.DMA/CPUx.CLA1 is incorrect

Note
In the case of an uncorrectable error during fetch on the CPU, there is the possibility of getting an
ITRAP before an NMI exception, since garbage instructions enter into the CPU pipeline before the
NMI gets generated.
During debug accesses, correctable as well as uncorrectable errors are masked.

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3.12.1.10 Application Test Hooks for Error Detection and Correction

Since error detection and correction logic is part of safety critical logic, safety applications need to make sure
that the logic is always working fine (during run time also). To enable this, different test modes are provided
to generate ecc/parity error in RAM locations. These test modes can be configured in RAM Test registers of
different RAM blocks. (for example, for D0 RAM, TEST_D0 bit in DxTEST register). Different test modes are for
different usage. In test mode user can modify the data bits (without modifying the ECC/Parity bits) or ECC/Parity
bits directly. Using this feature, an ECC/Parity error can be injected into data. Since an uncorrectable error
generates NMI, you can avoid generating this during test mode as one of the test modes (11) is provided where
NMI generation gets disabled. This mode is just like functional mode except NMI generation on uncorrectable
error.

Note
The memory-map for ECC/Parity bits and data bits are the same. Choose a different test mode (10) to
access ECC/Parity bits.

The following tables show the bit mapping for the ECC and Parity bits when the bits are read in RAMTEST mode
using their respective addresses.
Table 3-12. Mapping of ECC Bits in Read Data from ECC/Parity Address Map
Data Bits Location in Read Data Content (ECC Memory)
6:0 ECC Code for lower 16 bits of data
7 Not Used
14:8 ECC Code for upper 16 bits of data
15 Not Used
22:16 ECC Code for address
31:23 Not Used

Table 3-13. Mapping of Parity Bits in Read Data from ECC/Parity Address Map
Data Bits Location in Read Data Content (Parity Memory)
0 Parity for lower 16 bits of data
7:1 Not Used
8 Parity for upper 16 bits of data
15:9 Not Used
16 Parity for address
31:17 Not Used

Following is the sequence that must be followed to test the ecc/parity logic.
• Set the test mode to 01 or 10, depending on whether data field or ecc/parity field needs to be written.
• Write the data pattern into the memory.
• Set the test mode to 11 to read from memory and exercise the ecc/parity logic.
• Check the test log registers to verify the correctness of the logic.
• The above sequence can be repeated for any number of data patterns.
• Once the test is complete, re-initialize the locations used in test, and set the test mode to 00 that changes the
RAM block back into functional mode.

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3.12.1.11 ROM Test

ROMs are read only memory, unlike RAMs, data or parity bits cannot be modified to introduce errors for
diagnostic coverage of parity checking logic. Following method is used to check health of parity checking logic in
ROMs.
• Added duplicate Parity check logic and feed the same data into duplicate parity checker
• Generate uncorrectable error if parity check status of these two separate parity checkers do not match
Probability of both circuits having fault is unlikely hence Parity Errors are certainly detected.
To generate the error, a test bit FORCE_ERROR is added. When the FORCE_ERROR bit is set, the parity bit
going to one of the party checkers is inverted thereby introducing an uncorrectable error. An uncorrectable error
is generated only if there is an error on all parity checkers that is: address, data [15:0], and data [31:16]. This
makes sure that all three parity checkers are working as expected.
P3[0] Offset Addr P2[0] Data[31:16] P1[0] Data[15:0]

ForceError ForceError ForceError

Addr Parity Checker Addr Parity Checker Data[31:16] Parity Data[31:16] Parity Data[15:0] Parity Data[15:0] Parity
2 1 Checker 2 Checker 1 Checker 2 Checker 1
Parity Error Parity Error Parity Error Parity Error Parity Error Parity Error
p1
p1 p3 p5 p3
0
p5
p2 Uncorrectable error
p2 p4 p6 p4
1
p6

ForceError

Figure 3-19. ROM Parity Checking Logic

3.12.1.12 RAM Initialization

To make sure that read/fetch from uninitialized RAM locations do not cause ECC or parity errors, the RAM_INIT
feature is provided for each memory block. Using this feature, any RAM block can be initialized with 0x0 data
and respective ECC/Parity bits accordingly. This can be initiated by setting the INIT bit to 1 for the specific RAM
block in INIT registers. To check the status of RAM initialization, software must poll for the INITDONE bit for that
RAM block in the INITDONE register to be set. Unless this bit gets set, no access must be made to that RAM
memory block.
In the case of GSx memory, only the CPU of the subsystem that is configured as the master for the particular
GSx RAM block can initiate the RAM initialization.

Note
The INIT bit must not be set again until the INITDONE bit for the corresponding RAM block has been
polled to be set.
None of the masters must access the memory while initialization is taking place. If memory is
accessed before RAMINITDONE is set, the memory read/write as well as initialization does not
happen correctly.

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3.13 JTAG
Gel files perform certain initialization tasks. This helps the users in a debug environment. However, when
executed standalone (without the emulator connected) the application could potentially not work as expected,
since there is no gel file to perform those initializations. For example, gel file disables watchdog. If user code
does not service the watchdog in the application (or fails to disable the watchdog), there would be a difference in
how the application behaves with the debugger and without the debugger.
Common tasks performed by the gel files (but not boot-ROM):
• On Reset:
– Disable Flash ECC on some devices.
• Disabling ECC only when using Flash API functions, see the Flash API User Guide for details.
Otherwise, TI suggests to always program ECC and enable ECC-check.
– Disable Watchdog
– Enable CLA clock
– Select real-time mode or C28x mode
• On Restart:
– Select real-time mode or C28x mode
– Clear IER and IFR
• On Target Connect:
– Select real-time mode or C28x mode

For more information, see C2000 MCU JTAG Connectivity Debug.

3.13.1 JTAG Noise and TAP_STATUS
The TAP_STATUS register reflects the status of the JTAG TAP at any given time. Normally when no JTAG
is connected to the device, the status can be IDLE. In some cases with excessive PCB noise, there can be
unwanted TMS and TCK toggles that take JTAG out of the IDLE state. When persistent, this can ultimately
lead to unwanted activation of the JTAG Boundary Scan or some other JTAG mode that can interfere with the
intended application. To avoid this scenario, place strong enough pull resistors on the board to prevent noise
from activating JTAG. As a debug tool, the TAP_STATUS register can be polled by the application code to detect
if this is a cause of device disturbance. The SOFTPRES40[JTAG_nTRST] register can also be used to reset the
JTAG TAP through software. Use this reset register with caution, as this prevents connecting a debugger unless
the code qualifies writes to this register with some other GPIO state or other means to distinguish between noise
and debugger accesses.

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3.14 System Control Register Configuration Restrictions

Memory-mapped registers in the System Control operate on INTOSC1 clock domain; hence, any CPU writes
to these registers requires a delay between subsequent writes otherwise a second write can be lost. The
application needs to take this into consideration and add a delay in terms of the number of NOP instructions
after every write to these registers that are mentioned in Table 3-14. The formula to compute delay between
subsequent writes:
Delay (in SYSCLK cycles) = 3 × (FSYSCLK ÷ FINTOSC1) + 9
For Example - For SYSCLK = 100200 MHz
Delay (in SYSCLK cycles) = 3 × (100 MHz ÷ 10 MHz) + 9 = 39 SYSCLK cycles
Table 3-14. System Control Registers Impacted
Registers requiring delay after every write
CLBCLKCTL
PERCLKDIVSEL
SYSCLKDIVSEL
SYSPLLCTL1
SYSPLLMULT
WDCR
XCLKOUTDIVSEL
XTALCR
CLKSRCCTL1
CLKSRCCTL2
CLKSRCCTL3
CPU1TMR2CTL (TMR2CLKCTL)

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3.15 Software
3.15.1 SYSCTL Examples
NOTE: These examples are located in the C2000Ware installation at the following location:
C2000Ware_VERSION#/driverlib/DEVICE_GPN/examples/CORE_IF_MULTICORE/sysctl
Cloud access to these examples is available at the following link: dev.ti.com C2000Ware Examples.
3.15.1.1 Missing clock detection (MCD)
FILE: sysctl_ex1_missing_clock_detection.c
This example demonstrates the missing clock detection functionality and the way to handle it. Once the MCD is
simulated by disconnecting the OSCCLK to the MCD module an NMI would be generated. This NMI determines
that an MCD was generated due to a clock failure which is handled in the ISR.
Before an MCD the clock frequency would be as per device initialization (200Mhz). Post MCD the frequency
would move to 10Mhz or INTOSC1.
The example also shows how we can lock the PLL after missing clock, detection, by first explicitly switching the
clock source to INTOSC1, resetting the missing clock detect circuit and then re-locking the PLL. Post a re-lock
the clock frequency would be 200Mhz but using the INTOSC1 as clock source.
External Connections
• None.
Watch Variables
• fail - Indicates that a missing clock was either not detected or was not handled correctly.
• mcd_clkfail_isr - Indicates that the missing clock failure caused an NMI to be triggered and called an the ISR
to handle it.
• mcd_detect - Indicates that a missing clock was detected.
• result - Status of a successful handling of missing clock detection
3.15.1.2 XCLKOUT (External Clock Output) Configuration
FILE: sysctl_ex2_xclkout_config.c
This example demonstrates how to configure the XCLKOUT pin for observing internal clocks through an external
pin, for debugging and testing purposes.
In this example, we are using INTOSC1 as the XCLKOUT clock source and configuring the divider as 8.
Expected frequency of XCLKOUT = (INTOSC1 freq)/8 = 10/8 = 1.25MHz
View the XCLKOUT on GPIO73 using an oscilloscope.
3.15.2 MEMCFG Examples
NOTE: These examples are located in the C2000Ware installation at the following location:
C2000Ware_VERSION#/driverlib/DEVICE_GPN/examples/CORE_IF_MULTICORE/memcfg
Cloud access to these examples is available at the following link: dev.ti.com C2000Ware Examples.
3.15.2.1 Correctable & Uncorrectable Memory Error Handling
FILE: memcfg_ex1_error_handling.c
This example demonstrates error handling in case of various erroneous memory read/write operations.
Error handling in case of CPU read/write violations, correctable & uncorrectable memory errors has been
demonstrated. Correctable memory errors & violations can generate SYS_INT interrupt to CPU while
uncorrectable errors lead to NMI generation.
External Connections
• None

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Watch Variables
• testStatusGlobal - Equivalent to TEST_PASS if test finished correctly, else the value is set to TEST_FAIL
• errCountGlobal - Error counter
3.15.2.2 Shared RAM Management (CPU1) - C28X_DUAL
FILE: memcfg_ex1_ram_management_cpu1.c
This example shows how to assign shared RAM for use by both the CPU2 and CPU1 core. Shared RAM regions
are defined in both the CPU2 and CPU1 linker files. In this example GS0 and GS14 are assigned to/owned by
CPU2. The remaining shared RAM regions are owned by CPU1.
In this example, a pattern is written to cpu1RWArray and then an IPC flag is sent to notify CPU2 that data is
ready to be read. CPU2 then reads the data from cpu2RArray and writes a modified pattern to cpu2RWArray.
Once CPU2 acknowledges the IPC flag, CPU1 reads the data from cpu1RArray and compares with expected
result.
A timer ISR is also serviced in both CPUs. The ISRs are copied into the shared RAM region owned by the
respective CPUs. Each ISR toggles a GPIO. Watch the GPIOs on an oscilloscope, or if using the controlCARD,
watch LED1 and LED2 blink at different rates.
Following are the memory allocation details of CPU Timer interrupt ISRs & read(R)/read write(RW) arrays in
CPU1 & CPU2 as configured in the example.
• cpu1RWArray[] is mapped to shared RAM GS1
• cpu1RArray[] is mapped to shared RAM GS0
• cpu2RArray[] is mapped to shared RAM GS1
• cpu2RWArray[] is mapped to shared RAM GS0
• cpuTimer0ISR in CPU2 is copied to shared RAM GS14, toggles LED1
• cpuTimer0ISR in CPU1 is copied to shared RAM GS15, toggles LED2

Watch Variables
• error Indicates that the data written is not correctly received by the other CPU.
3.15.2.3 Shared RAM Management (CPU2) - C28X_DUAL
FILE: memcfg_ex1_ram_management_cpu2.c
This example shows how to assign shared RAM for use by both the CPU2 and CPU1 core. Shared RAM regions
are defined in both the CPU2 and CPU1 linker files. In this example GS0 and GS14 are assigned to/owned by
CPU2. The remaining shared RAM regions are owned by CPU1.
In this example, a pattern is written to cpu1RWArray and then an IPC flag is sent to notify CPU2 that data is
ready to be read. CPU2 then reads the data from cpu2RArray and writes a modified pattern to cpu2RWArray.
Once CPU2 acknowledges the IPC flag, CPU1 reads the data from cpu1RArray and compares with expected
result.
A timer ISR is also serviced in both CPUs. The ISRs are copied into the shared RAM region owned by the
respective CPUs. Each ISR toggles a GPIO. Watch the GPIOs on an oscilloscope, or if using the controlCARD,
watch LED1 and LED2 blink at different rates.
Following are the memory allocation details of CPU Timer interrupt ISRs & read(R)/read write(RW) arrays in
CPU1 & CPU2 as configured in the example.
• cpu1RWArray[] is mapped to shared RAM GS1
• cpu1RArray[] is mapped to shared RAM GS0
• cpu2RArray[] is mapped to shared RAM GS1
• cpu2RWArray[] is mapped to shared RAM GS0
• cpuTimer0ISR in CPU2 is copied to shared RAM GS14, toggles LED1
• cpuTimer0ISR in CPU1 is copied to shared RAM GS15, toggles LED2

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3.15.2.4 Demonstrate memconfig diagnostics and error handling. - CM

FILE: memcfg_ex1_error_handling.c
This example demonstrates how to configure the diagnostic mode and induce ECC errors. This example induces
single and two bit ECC errors in E0RAM and tries to read the corrupted location in diagnostic and functional
mode. cm_common_config_c28x example needs to be run on C28x1 before running this example on the CM
core
External Connections
• None
Watch Variables
• testStatus - Equivalent to TEST_PASS if test finished correctly, else the value is set to TEST_FAIL
• errorGlobalCount - Error counter
• retx - Individual test status
3.15.2.5 Shared RAM Management (CPU1) - C28X_DUAL
FILE: memcfg_ex2_ram_sysconfig_cpu1.c
This example shows how to assign shared RAM for use by both the CPU2 and CPU1 core. Shared RAM regions
are defined in both the CPU2 and CPU1 linker files. In this example GS0 and GS14 are assigned to/owned by
CPU2. The remaining shared RAM regions are owned by CPU1.
In this example, a pattern is written to cpu1RWArray and then an IPC flag is sent to notify CPU2 that data is
ready to be read. CPU2 then reads the data from cpu2RArray and writes a modified pattern to cpu2RWArray.
Once CPU2 acknowledges the IPC flag, CPU1 reads the data from cpu1RArray and compares with expected
result.
A timer ISR is also serviced in both CPUs. The ISRs are copied into the shared RAM region owned by the
respective CPUs. Each ISR toggles a GPIO. Watch the GPIOs on an oscilloscope, or if using the controlCARD,
watch LED1 and LED2 blink at different rates.
Following are the memory allocation details of CPU Timer interrupt ISRs & read(R)/read write(RW) arrays in
CPU1 & CPU2 as configured in the example.
• cpu1RWArray[] is mapped to shared RAM GS1
• cpu1RArray[] is mapped to shared RAM GS0
• cpu2RArray[] is mapped to shared RAM GS1
• cpu2RWArray[] is mapped to shared RAM GS0
• cpuTimer0ISR in CPU2 is copied to shared RAM GS14, toggles LED1
• cpuTimer0ISR in CPU1 is copied to shared RAM GS15, toggles LED2
Watch Variables
• error Indicates that the data written is not correctly received by the other CPU.
3.15.2.6 Shared RAM Management (CPU2) - C28X_DUAL
FILE: memcfg_ex2_ram_sysconfig_cpu2.c
This example shows how to assign shared RAM for use by both the CPU2 and CPU1 core. Shared RAM regions
are defined in both the CPU2 and CPU1 linker files. In this example GS0 and GS14 are assigned to/owned by
CPU2. The remaining shared RAM regions are owned by CPU1.
In this example, a pattern is written to cpu1RWArray and then an IPC flag is sent to notify CPU2 that data is
ready to be read. CPU2 then reads the data from cpu2RArray and writes a modified pattern to cpu2RWArray.
Once CPU2 acknowledges the IPC flag, CPU1 reads the data from cpu1RArray and compares with expected
result.
A timer ISR is also serviced in both CPUs. The ISRs are copied into the shared RAM region owned by the
respective CPUs. Each ISR toggles a GPIO. Watch the GPIOs on an oscilloscope, or if using the controlCARD,
watch LED1 and LED2 blink at different rates.

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Following are the memory allocation details of CPU Timer interrupt ISRs & read(R)/read write(RW) arrays in
CPU1 & CPU2 as configured in the example.
• cpu1RWArray[] is mapped to shared RAM GS1
• cpu1RArray[] is mapped to shared RAM GS0
• cpu2RArray[] is mapped to shared RAM GS1
• cpu2RWArray[] is mapped to shared RAM GS0
• cpuTimer0ISR in CPU2 is copied to shared RAM GS14, toggles LED1
• cpuTimer0ISR in CPU1 is copied to shared RAM GS15, toggles LED2
3.15.3 NMI Examples
NOTE: These examples are located in the C2000Ware installation at the following location:
C2000Ware_VERSION#/driverlib/DEVICE_GPN/examples/CORE_IF_MULTICORE/nmi
Cloud access to these examples is available at the following link: dev.ti.com C2000Ware Examples.
3.15.3.1 NMI handling - C28X_DUAL
FILE: nmi_ex1_cpu1handling.c
This example demonstrates how to handle an NMI.
The watchdog of CPU2 is configured to reset the core once the watchdog overflows and in the CPU1 the NMI is
triggered. The NMI status is read and is verified to be due to CPU2 Watchdog reset. The NMI ISR reboots the
CPU2 core and the process is repeated.

Watch Variables
• nmi_isr_count Indicates the number of times the NMI ISR was hit because of CPU2 watchdog reset.
3.15.3.2 Watchdog Reset - C28X_DUAL
FILE: nmi_ex1_cpu2wdreset.c
This example shows how to configure the watchdog to reset CPU2 which will trigger an NMI in CPU1. LED1 is
toggled at the start of main indicating CPU reset.
External Connections
• None.
Watch Variables
• loopCount - The number of loops performed while not in ISR
3.15.3.3 NMI handling - C28X_DUAL
FILE: nmi_ex2_sysconfig_cpu1.c
This example demonstrates how to handle an NMI.
The watchdog of CPU2 is configured to reset the core once the watchdog overflows and in the CPU1 the NMI is
triggered. The NMI status is read and is verified to be due to CPU2 Watchdog reset. The NMI ISR reboots the
CPU2 core and the process is repeated.
Watch Variables
• nmi_isr_count Indicates the number of times the NMI ISR was hit because of CPU2 watchdog reset.
3.15.3.4 Watchdog Reset - C28X_DUAL
FILE: nmi_ex2_sysconfig_cpu2.c
This example shows how to configure the watchdog to reset CPU2 which will trigger an NMI in CPU1. LED1 is
toggled at the start of main indicating CPU reset.
External Connections
• None.

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Watch Variables
• loopCount - The number of loops performed while not in ISR
3.15.4 TIMER Examples
NOTE: These examples are located in the C2000Ware installation at the following location:
C2000Ware_VERSION#/driverlib/DEVICE_GPN/examples/CORE_IF_MULTICORE/timer
Cloud access to these examples is available at the following link: dev.ti.com C2000Ware Examples.
3.15.4.1 CPU Timers
FILE: timer_ex1_cputimers.c
This example configures CPU Timer0, 1, and 2 and increments a counter each time the timer asserts an
interrupt.
External Connections
• None
Watch Variables
• cpuTimer0IntCount
• cpuTimer1IntCount
• cpuTimer2IntCount
3.15.4.2 CPU Timers - CM
FILE: timer_ex1_cputimers.c
This example configures CPU Timer0, 1, and 2 and increments a counter each time the timer asserts an
interrupt.
Before running this example, please run the cm_common_config_c28x Example from the c28x folder. It will
initialize the clock and configure the GPIOs.
External Connections
• None
Watch Variables
• cpuTimer0IntCount
• cpuTimer1IntCount
• cpuTimer2IntCount
3.15.4.3 CPU Timers
FILE: timer_ex1_cputimers_sysconfig.c
This example configures CPU Timer0, 1, and 2 and increments a counter each time the timer asserts an
interrupt.
External Connections
• None
Watch Variables
• cpuTimer0IntCount
• cpuTimer1IntCount
• cpuTimer2IntCount
3.15.5 WATCHDOG Examples
NOTE: These examples are located in the C2000Ware installation at the following location:
C2000Ware_VERSION#/driverlib/DEVICE_GPN/examples/CORE_IF_MULTICORE/watchdog
Cloud access to these examples is available at the following link: dev.ti.com C2000Ware Examples.

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3.15.5.1 Watchdog
FILE: watchdog_ex1_service.c
This example shows how to service the watchdog or generate a wakeup interrupt using the watchdog. By default
the example will generate a Wake interrupt. To service the watchdog and not generate the interrupt, uncomment
the SysCtl_serviceWatchdog() line in the main for loop.
External Connections
• None.
Watch Variables
• wakeCount - The number of times entered into the watchdog ISR
• loopCount - The number of loops performed while not in ISR
3.15.5.2 Windowed watchdog expiry with NMI handling - CM
FILE: watchdog_ex1_nmi_handling.c
This program demonstrates an NMI generation to the CM4 core when the Windowed watchdog ( WWD ) expires.
A delay is provided after enabling the WWD to make the watchdog count up from 0 to 0xFF. Once 0 is reached,
an NMI is triggered. Currently on triggering an NMI, a status flag is set indicating if the NMI was handled after the
WWD expired.
External Connections
• None
Watch Variables
• wdstatus - Indicates if the WWD caused an NMI on expiry.
• cmnmi - Indicates if the NMI was handled after the WWD expired
• fail - Status if the Windowed watchdog expired generating an NMI with proper NMI handling

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3.16 System Control Registers

This section describes the various System Control Registers.
3.16.1 SYSCTRL Base Address Table (C28)
Table 3-15. SYSCTRL Base Address Table (C28)
Bit Field Name Pipeline
DriverLib Name Base Address CPU1 CPU2 DMA CLA
Instance Structure Protected

ACCESS_PROTECTION ACCESSPROTECTION_
AccessProtectionRegs 0x0005_F500 YES YES - - YES
_REGS BASE
ClkCfgRegs CLK_CFG_REGS CLKCFG_BASE 0x0005_D200 YES YES - - YES
CmConfRegs CM_CONF_REGS CMCONF_BASE 0x0005_DC00 YES - - - YES
CpuIdRegs CPU_ID_REGS CPUID_BASE 0x0007_0223 YES YES - - -
CpuSysRegs CPU_SYS_REGS CPUSYS_BASE 0x0005_D300 YES YES - - YES
CpuTimer0Regs CPUTIMER_REGS CPUTIMER0_BASE 0x0000_0C00 YES YES - - -
CpuTimer1Regs CPUTIMER_REGS CPUTIMER1_BASE 0x0000_0C08 YES YES - - -
CpuTimer2Regs CPUTIMER_REGS CPUTIMER2_BASE 0x0000_0C10 YES YES - - -
DevCfgRegs DEV_CFG_REGS DEVCFG_BASE 0x0005_D000 YES - - - YES
DMA_CLA_SRC_SEL_R DMACLASRCSEL_BAS
DmaClaSrcSelRegs 0x0000_7980 YES YES - - YES
EGS E
MemCfgRegs MEM_CFG_REGS MEMCFG_BASE 0x0005_F400 YES YES - - YES
MEMORY_ERROR_RE MEMORYERROR_BAS
MemoryErrorRegs 0x0005_F540 YES YES - - YES
GS E
NmiIntruptRegs NMI_INTRUPT_REGS NMI_BASE 0x0000_7060 YES YES - - YES
PieCtrlRegs PIE_CTRL_REGS PIECTRL_BASE 0x0000_0CE0 YES YES - - -
PieVectTable PIE_VECT_TABLE PIEVECTTABLE_BASE 0x0000_0D00 YES YES - - -
ROM_PREFETCH_REG
RomPrefetchRegs ROMPREFETCH_BASE 0x0005_F588 YES YES - - YES
S
ROM_WAIT_STATE_RE
RomWaitStateRegs ROMWAITSTATE_BASE 0x0005_F580 YES YES - - YES
GS
SyncSocRegs SYNC_SOC_REGS SYNCSOC_BASE 0x0000_7940 YES - - - YES
CPU1_PERIPH_AC_RE
SysPeriphAcRegs PERIPHAC_BASE 0x0005_D500 YES - - - YES
GS
CPU2_PERIPH_AC_RE
SysPeriphAcRegs PERIPHAC_BASE 0x0005_D500 - YES - - YES
GS
SysStatusRegs SYS_STATUS_REGS SYSSTAT_BASE 0x0005_D400 YES YES - - YES
TestErrorRegs TEST_ERROR_REGS TESTERROR_BASE 0x0005_F590 YES YES - - YES
UidRegs UID_REGS UID_BASE 0x0007_0200 YES YES - - -
WdRegs WD_REGS WD_BASE 0x0000_7000 YES YES - - YES
XintRegs XINT_REGS XINT_BASE 0x0000_7070 YES YES - - YES

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3.16.2 ACCESS_PROTECTION_REGS Registers

Table 3-16 lists the memory-mapped registers for the ACCESS_PROTECTION_REGS registers. All register
offset addresses not listed in Table 3-16 should be considered as reserved locations and the register contents
should not be modified.
Table 3-16. ACCESS_PROTECTION_REGS Registers
Offset Acronym Register Name Write Protection Section
0h NMAVFLG Non-Master Access Violation Flag Register Go
2h NMAVSET Non-Master Access Violation Flag Set Register EALLOW Go
4h NMAVCLR Non-Master Access Violation Flag Clear Register EALLOW Go
6h NMAVINTEN Non-Master Access Violation Interrupt Enable EALLOW Go
Register
8h NMCPURDAVADDR Non-Master CPU Read Access Violation Address Go
Ah NMCPUWRAVADDR Non-Master CPU Write Access Violation Address Go
Ch NMCPUFAVADDR Non-Master CPU Fetch Access Violation Address Go
Eh NMDMAWRAVADDR Non-Master DMA Write Access Violation Address Go
10h NMCLA1RDAVADDR Non-Master CLA1 Read Access Violation Go
Address
12h NMCLA1WRAVADDR Non-Master CLA1 Write Access Violation Address Go
14h NMCLA1FAVADDR Non-Master CLA1 Fetch Access Violation Go
Address
1Ch NMDMARDAVADDR Non-Master DMA Read Access Violation Address Go
20h MAVFLG Master Access Violation Flag Register Go
22h MAVSET Master Access Violation Flag Set Register EALLOW Go
24h MAVCLR Master Access Violation Flag Clear Register EALLOW Go
26h MAVINTEN Master Access Violation Interrupt Enable Register EALLOW Go
28h MCPUFAVADDR Master CPU Fetch Access Violation Address Go
2Ah MCPUWRAVADDR Master CPU Write Access Violation Address Go
2Ch MDMAWRAVADDR Master DMA Write Access Violation Address Go

Complex bit access types are encoded to fit into small table cells. Table 3-17 shows the codes that are used for
access types in this section.
Table 3-17. ACCESS_PROTECTION_REGS Access
Type Codes
Access Type Code Description
Read Type
R R Read
R-0 R Read
-0 Returns 0s
Write Type
W W Write
W1S W Write
1S 1 to set
Reset or Default Value
-n Value after reset or the default
value
Register Array Variables

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Table 3-17. ACCESS_PROTECTION_REGS Access

Type Codes (continued)
Access Type Code Description
i,j,k,l,m,n When these variables are used in
a register name, an offset, or an
address, they refer to the value of
a register array where the register
is part of a group of repeating
registers. The register groups
form a hierarchical structure and
the array is represented with a
formula.
y When this variable is used in a
register name, an offset, or an
address it refers to the value of
a register array.

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3.16.2.1 NMAVFLG Register (Offset = 0h) [Reset = 0h]

NMAVFLG is shown in Figure 3-20 and described in Table 3-18.
Return to the Summary Table.
Non-Master Access Violation Flag Register
Figure 3-20. NMAVFLG Register
31 30 29 28 27 26 25 24
RESERVED
R-0h

23 22 21 20 19 18 17 16
RESERVED
R-0h

15 14 13 12 11 10 9 8
RESERVED DMAREAD RESERVED RESERVED
R-0h R-0h R-0h R-0h

7 6 5 4 3 2 1 0
RESERVED CLA1FETCH CLA1WRITE CLA1READ DMAWRITE CPUFETCH CPUWRITE CPUREAD
R-0h R-0h R-0h R-0h R-0h R-0h R-0h R-0h

Table 3-18. NMAVFLG Register Field Descriptions

Bit Field Type Reset Description
31-16 RESERVED R 0h Reserved
15-11 RESERVED R 0h Reserved
10 DMAREAD R 0h Non Master DMA Read Access Violation Flag:
0: No violation.
1: Access violation occured.
Reset type: SYSRSn
9 RESERVED R 0h Reserved
8 RESERVED R 0h Reserved
7 RESERVED R 0h Reserved
6 CLA1FETCH R 0h Non Master CLA1 Fetch Access Violation Flag:
0: No violation.
1: Access violation occured.
Reset type: SYSRSn
5 CLA1WRITE R 0h Non Master CLA1 Write Access Violation Flag:
0: No violation.
1: Access violation occured.
Reset type: SYSRSn
4 CLA1READ R 0h Non Master CLA1 Read Access Violation Flag:
0: No violation.
1: Access violation occured.
Reset type: SYSRSn
3 DMAWRITE R 0h Non Master DMA Write Access Violation Flag:
0: No violation.
1: Access violation occured.
Reset type: SYSRSn
2 CPUFETCH R 0h Non Master CPU Fetch Access Violation Flag:
0: No violation.
1: Access violation occured.
Reset type: SYSRSn

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Table 3-18. NMAVFLG Register Field Descriptions (continued)

Bit Field Type Reset Description
1 CPUWRITE R 0h Non Master CPU Write Access Violation Flag:
0: No violation.
1: Access violation occured.
Reset type: SYSRSn
0 CPUREAD R 0h Non Master CPU Read Access Violation Flag:
0: No violation.
1: Access violation occured.
Reset type: SYSRSn

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3.16.2.2 NMAVSET Register (Offset = 2h) [Reset = 0h]

NMAVSET is shown in Figure 3-21 and described in Table 3-19.
Return to the Summary Table.
Non-Master Access Violation Flag Set Register
Figure 3-21. NMAVSET Register
31 30 29 28 27 26 25 24
RESERVED
R-0h

23 22 21 20 19 18 17 16
RESERVED
R-0h

15 14 13 12 11 10 9 8
RESERVED DMAREAD RESERVED RESERVED
R-0h R-0/W1S-0h R-0/W1S-0h R-0/W1S-0h

7 6 5 4 3 2 1 0
RESERVED CLA1FETCH CLA1WRITE CLA1READ DMAWRITE CPUFETCH CPUWRITE CPUREAD
R-0/W1S-0h R-0/W1S-0h R-0/W1S-0h R-0/W1S-0h R-0/W1S-0h R-0/W1S-0h R-0/W1S-0h R-0/W1S-0h

Table 3-19. NMAVSET Register Field Descriptions

Bit Field Type Reset Description
31-16 RESERVED R 0h Reserved
15-11 RESERVED R 0h Reserved
10 DMAREAD R-0/W1S 0h 0: No action.
1: DMA Read Access Violation Flag in NMAVFLG register will be set
and interrupt will be generated if enabled..
Reset type: SYSRSn
9 RESERVED R-0/W1S 0h Reserved
8 RESERVED R-0/W1S 0h Reserved
7 RESERVED R-0/W1S 0h Reserved
6 CLA1FETCH R-0/W1S 0h 0: No action.
1: CLA1 Fetch Access Violation Flag in NMAVFLG register will be set
and interrupt will be generated if enabled.
Reset type: SYSRSn
5 CLA1WRITE R-0/W1S 0h 0: No action.
1: CLA1 Write Access Violation Flag in NMAVFLG register will be set
and interrupt will be generated if enabled.
Reset type: SYSRSn
4 CLA1READ R-0/W1S 0h 0: No action.
1: CLA1 Read Access Violation Flag in NMAVFLG register will be set
and interrupt will be generated if enabled.
Reset type: SYSRSn
3 DMAWRITE R-0/W1S 0h 0: No action.
1: DMA Write Access Violation Flag in NMAVFLG register will be set
and interrupt will be generated if enabled.
Reset type: SYSRSn
2 CPUFETCH R-0/W1S 0h 0: No action.
1: CPU Fetch Access Violation Flag in NMAVFLG register will be set
and interrupt will be generated if enabled.
Reset type: SYSRSn

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Table 3-19. NMAVSET Register Field Descriptions (continued)

Bit Field Type Reset Description
1 CPUWRITE R-0/W1S 0h 0: No action.
1: CPU Write Access Violation Flag in NMAVFLG register will be set
and interrupt will be generated if enabled.
Reset type: SYSRSn
0 CPUREAD R-0/W1S 0h 0: No action.
1: CPU Read Access Violation Flag in NMAVFLG register will be set
and interrupt will be generated if enabled.
Reset type: SYSRSn

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3.16.2.3 NMAVCLR Register (Offset = 4h) [Reset = 0h]

NMAVCLR is shown in Figure 3-22 and described in Table 3-20.
Return to the Summary Table.
Non-Master Access Violation Flag Clear Register
Figure 3-22. NMAVCLR Register
31 30 29 28 27 26 25 24
RESERVED
R-0h

23 22 21 20 19 18 17 16
RESERVED
R-0h

15 14 13 12 11 10 9 8
RESERVED DMAREAD RESERVED RESERVED
R-0h R-0/W1S-0h R-0/W1S-0h R-0/W1S-0h

7 6 5 4 3 2 1 0
RESERVED CLA1FETCH CLA1WRITE CLA1READ DMAWRITE CPUFETCH CPUWRITE CPUREAD
R-0/W1S-0h R-0/W1S-0h R-0/W1S-0h R-0/W1S-0h R-0/W1S-0h R-0/W1S-0h R-0/W1S-0h R-0/W1S-0h

Table 3-20. NMAVCLR Register Field Descriptions

Bit Field Type Reset Description
31-16 RESERVED R 0h Reserved
15-11 RESERVED R 0h Reserved
10 DMAREAD R-0/W1S 0h 0: No action.
1: DMA Read Access Violation Flag in NMAVFLG register will be
cleared.
Reset type: SYSRSn
9 RESERVED R-0/W1S 0h Reserved
8 RESERVED R-0/W1S 0h Reserved
7 RESERVED R-0/W1S 0h Reserved
6 CLA1FETCH R-0/W1S 0h 0: No action.
1: CLA1 Fetch Access Violation Flag in NMAVFLG register will be
cleared.
Reset type: SYSRSn
5 CLA1WRITE R-0/W1S 0h 0: No action.
1: CLA1 Write Access Violation Flag in NMAVFLG register will be
cleared.
Reset type: SYSRSn
4 CLA1READ R-0/W1S 0h 0: No action.
1: CLA1 Read Access Violation Flag in NMAVFLG register will be
cleared.
Reset type: SYSRSn
3 DMAWRITE R-0/W1S 0h 0: No action.
1: DMA Write Access Violation Flag in NMAVFLG register will be
cleared.
Reset type: SYSRSn
2 CPUFETCH R-0/W1S 0h 0: No action.
1: CPU Fetch Access Violation Flag in NMAVFLG register will be
cleared.
Reset type: SYSRSn

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Table 3-20. NMAVCLR Register Field Descriptions (continued)

Bit Field Type Reset Description
1 CPUWRITE R-0/W1S 0h 0: No action.
1: CPU Write Access Violation Flag in NMAVFLG register will be
cleared.
Reset type: SYSRSn
0 CPUREAD R-0/W1S 0h 0: No action.
1: CPU Read Access Violation Flag in NMAVFLG register will be
cleared.
Reset type: SYSRSn

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3.16.2.4 NMAVINTEN Register (Offset = 6h) [Reset = 0h]

NMAVINTEN is shown in Figure 3-23 and described in Table 3-21.
Return to the Summary Table.
Non-Master Access Violation Interrupt Enable Register
Figure 3-23. NMAVINTEN Register
31 30 29 28 27 26 25 24
RESERVED
R-0h

23 22 21 20 19 18 17 16
RESERVED
R-0h

15 14 13 12 11 10 9 8
RESERVED DMAREAD RESERVED RESERVED
R-0h R/W-0h R/W-0h R/W-0h

7 6 5 4 3 2 1 0
RESERVED CLA1FETCH CLA1WRITE CLA1READ DMAWRITE CPUFETCH CPUWRITE CPUREAD
R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h

Table 3-21. NMAVINTEN Register Field Descriptions

Bit Field Type Reset Description
31-16 RESERVED R 0h Reserved
15-11 RESERVED R 0h Reserved
10 DMAREAD R/W 0h 0: DMA Non Master Read Access Violation Interrupt is disabled.
1: DMA Non Master Read Access Violation Interrupt is enabled.
Reset type: SYSRSn
9 RESERVED R/W 0h Reserved
8 RESERVED R/W 0h Reserved
7 RESERVED R/W 0h Reserved
6 CLA1FETCH R/W 0h 0: CLA1 Non Master Fetch Access Violation Interrupt is disabled.
1: CLA1 Non Master Fetch Access Violation Interrupt is enabled.
Reset type: SYSRSn
5 CLA1WRITE R/W 0h 0: CLA1 Non Master Write Access Violation Interrupt is disabled.
1: CLA1 Non Master Write Access Violation Interrupt is enabled.
Reset type: SYSRSn
4 CLA1READ R/W 0h 0: CLA1 Non Master Read Access Violation Interrupt is disabled.
1: CLA1 Non Master Read Access Violation Interrupt is enabled.
Reset type: SYSRSn
3 DMAWRITE R/W 0h 0: DMA Non Master Write Access Violation Interrupt is disabled.
1: DMA Non Master Write Access Violation Interrupt is enabled.
Reset type: SYSRSn
2 CPUFETCH R/W 0h 0: CPU Non Master Fetch Access Violation Interrupt is disabled.
1: CPU Non Master Fetch Access Violation Interrupt is enabled.
Reset type: SYSRSn
1 CPUWRITE R/W 0h 0: CPU Non Master Write Access Violation Interrupt is disabled.
1: CPU Non Master Write Access Violation Interrupt is enabled.
Reset type: SYSRSn
0 CPUREAD R/W 0h 0: CPU Non Master Read Access Violation Interrupt is disabled.
1: CPU Non Master Read Access Violation Interrupt is enabled.
Reset type: SYSRSn

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3.16.2.5 NMCPURDAVADDR Register (Offset = 8h) [Reset = 0h]

NMCPURDAVADDR is shown in Figure 3-24 and described in Table 3-22.
Return to the Summary Table.
Non-Master CPU Read Access Violation Address
Figure 3-24. NMCPURDAVADDR Register
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
NMCPURDAVADDR
R-0h

Table 3-22. NMCPURDAVADDR Register Field Descriptions

Bit Field Type Reset Description
31-0 NMCPURDAVADDR R 0h This register captures the address location for which non master
CPU read access vaiolation occurred.
Reset type: SYSRSn

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3.16.2.6 NMCPUWRAVADDR Register (Offset = Ah) [Reset = 0h]

NMCPUWRAVADDR is shown in Figure 3-25 and described in Table 3-23.
Return to the Summary Table.
Non-Master CPU Write Access Violation Address
Figure 3-25. NMCPUWRAVADDR Register
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
NMCPUWRAVADDR
R-0h

Table 3-23. NMCPUWRAVADDR Register Field Descriptions

Bit Field Type Reset Description
31-0 NMCPUWRAVADDR R 0h This register captures the address location for which non master
CPU write access vaiolation occurred.
Reset type: SYSRSn

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3.16.2.7 NMCPUFAVADDR Register (Offset = Ch) [Reset = 0h]

NMCPUFAVADDR is shown in Figure 3-26 and described in Table 3-24.
Return to the Summary Table.
Non-Master CPU Fetch Access Violation Address
Figure 3-26. NMCPUFAVADDR Register
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
NMCPUFAVADDR
R-0h

Table 3-24. NMCPUFAVADDR Register Field Descriptions

Bit Field Type Reset Description
31-0 NMCPUFAVADDR R 0h This register captures the address location for which non master
CPU fetch access vaiolation occurred.
Reset type: SYSRSn

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3.16.2.8 NMDMAWRAVADDR Register (Offset = Eh) [Reset = 0h]

NMDMAWRAVADDR is shown in Figure 3-27 and described in Table 3-25.
Return to the Summary Table.
Non-Master DMA Write Access Violation Address
Figure 3-27. NMDMAWRAVADDR Register
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
NMDMAWRAVADDR
R-0h

Table 3-25. NMDMAWRAVADDR Register Field Descriptions

Bit Field Type Reset Description
31-0 NMDMAWRAVADDR R 0h This register captures the address location for which non master
DMA write access vaiolation occurred.
Reset type: SYSRSn

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3.16.2.9 NMCLA1RDAVADDR Register (Offset = 10h) [Reset = 0h]

NMCLA1RDAVADDR is shown in Figure 3-28 and described in Table 3-26.
Return to the Summary Table.
Non-Master CLA1 Read Access Violation Address
Figure 3-28. NMCLA1RDAVADDR Register
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
NMCLA1RDAVADDR
R-0h

Table 3-26. NMCLA1RDAVADDR Register Field Descriptions

Bit Field Type Reset Description
31-0 NMCLA1RDAVADDR R 0h This register captures the address location for which non master
CLA1 read access vaiolation occurred.
Reset type: SYSRSn

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3.16.2.10 NMCLA1WRAVADDR Register (Offset = 12h) [Reset = 0h]

NMCLA1WRAVADDR is shown in Figure 3-29 and described in Table 3-27.
Return to the Summary Table.
Non-Master CLA1 Write Access Violation Address
Figure 3-29. NMCLA1WRAVADDR Register
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
NMCLA1WRAVADDR
R-0h

Table 3-27. NMCLA1WRAVADDR Register Field Descriptions

Bit Field Type Reset Description
31-0 NMCLA1WRAVADDR R 0h This register captures the address location for which non master
CLA1 write access vaiolation occurred.
Reset type: SYSRSn

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3.16.2.11 NMCLA1FAVADDR Register (Offset = 14h) [Reset = 0h]

NMCLA1FAVADDR is shown in Figure 3-30 and described in Table 3-28.
Return to the Summary Table.
Non-Master CLA1 Fetch Access Violation Address
Figure 3-30. NMCLA1FAVADDR Register
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
NMCLA1FAVADDR
R-0h

Table 3-28. NMCLA1FAVADDR Register Field Descriptions

Bit Field Type Reset Description
31-0 NMCLA1FAVADDR R 0h This register captures the address location for which non master
CLA1 fetch access vaiolation occurred.
Reset type: SYSRSn

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3.16.2.12 NMDMARDAVADDR Register (Offset = 1Ch) [Reset = 0h]

NMDMARDAVADDR is shown in Figure 3-31 and described in Table 3-29.
Return to the Summary Table.
Non-Master DMA Read Access Violation Address
Figure 3-31. NMDMARDAVADDR Register
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
NMDMARDAVADDR
R-0h

Table 3-29. NMDMARDAVADDR Register Field Descriptions

Bit Field Type Reset Description
31-0 NMDMARDAVADDR R 0h This register captures the address location for which non master
DMA read access vaiolation occurred.
Reset type: SYSRSn

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3.16.2.13 MAVFLG Register (Offset = 20h) [Reset = 0h]

MAVFLG is shown in Figure 3-32 and described in Table 3-30.
Return to the Summary Table.
Master Access Violation Flag Register
Figure 3-32. MAVFLG Register
31 30 29 28 27 26 25 24
RESERVED
R-0h

23 22 21 20 19 18 17 16
RESERVED
R-0h

15 14 13 12 11 10 9 8
RESERVED
R-0h

7 6 5 4 3 2 1 0
RESERVED DMAWRITE CPUWRITE CPUFETCH
R-0h R-0h R-0h R-0h

Table 3-30. MAVFLG Register Field Descriptions

Bit Field Type Reset Description
31-16 RESERVED R 0h Reserved
15-3 RESERVED R 0h Reserved
2 DMAWRITE R 0h Master DMA Write Access Violation Flag:
0: No violation.
1: Access violation occured.
Reset type: SYSRSn
1 CPUWRITE R 0h Master CPU Write Access Violation Flag:
0: No violation.
1: Access violation occured.
Reset type: SYSRSn
0 CPUFETCH R 0h Master CPU Fetch Access Violation Flag:
0: No violation.
1: Access violation occured.
Reset type: SYSRSn

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3.16.2.14 MAVSET Register (Offset = 22h) [Reset = 0h]

MAVSET is shown in Figure 3-33 and described in Table 3-31.
Return to the Summary Table.
Master Access Violation Flag Set Register
Figure 3-33. MAVSET Register
31 30 29 28 27 26 25 24
RESERVED
R-0h

23 22 21 20 19 18 17 16
RESERVED
R-0h

15 14 13 12 11 10 9 8
RESERVED
R-0h

7 6 5 4 3 2 1 0
RESERVED DMAWRITE CPUWRITE CPUFETCH
R-0h R-0/W1S-0h R-0/W1S-0h R-0/W1S-0h

Table 3-31. MAVSET Register Field Descriptions

Bit Field Type Reset Description
31-16 RESERVED R 0h Reserved
15-3 RESERVED R 0h Reserved
2 DMAWRITE R-0/W1S 0h 0: No action.
1: DMA Write Access Violation Flag in MAVFLG register will be set
and interrupt will be generated if enabled.
Reset type: SYSRSn
1 CPUWRITE R-0/W1S 0h 0: No action.
1: CPU Write Access Violation Flag in MAVFLG register will be set
and interrupt will be generated if enabled.
Reset type: SYSRSn
0 CPUFETCH R-0/W1S 0h 0: No action.
1: CPU Fetch Access Violation Flag in MAVFLG register will be set
and interrupt will be generated if enabled.
Reset type: SYSRSn

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3.16.2.15 MAVCLR Register (Offset = 24h) [Reset = 0h]

MAVCLR is shown in Figure 3-34 and described in Table 3-32.
Return to the Summary Table.
Master Access Violation Flag Clear Register
Figure 3-34. MAVCLR Register
31 30 29 28 27 26 25 24
RESERVED
R-0h

23 22 21 20 19 18 17 16
RESERVED
R-0h

15 14 13 12 11 10 9 8
RESERVED
R-0h

7 6 5 4 3 2 1 0
RESERVED DMAWRITE CPUWRITE CPUFETCH
R-0h R-0/W1S-0h R-0/W1S-0h R-0/W1S-0h

Table 3-32. MAVCLR Register Field Descriptions

Bit Field Type Reset Description
31-16 RESERVED R 0h Reserved
15-3 RESERVED R 0h Reserved
2 DMAWRITE R-0/W1S 0h 0: No action.
1: DMA Write Access Violation Flag in MAVFLG register will be
cleared.
Reset type: SYSRSn
1 CPUWRITE R-0/W1S 0h 0: No action.
1: CPU Write Access Violation Flag in MAVFLG register will be
cleared .
Reset type: SYSRSn
0 CPUFETCH R-0/W1S 0h 0: No action.
1: CPU Fetch Access Violation Flag in MAVFLG register will be
cleared.
Reset type: SYSRSn

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3.16.2.16 MAVINTEN Register (Offset = 26h) [Reset = 0h]

MAVINTEN is shown in Figure 3-35 and described in Table 3-33.
Return to the Summary Table.
Master Access Violation Interrupt Enable Register
Figure 3-35. MAVINTEN Register
31 30 29 28 27 26 25 24
RESERVED
R-0h

23 22 21 20 19 18 17 16
RESERVED
R-0h

15 14 13 12 11 10 9 8
RESERVED
R-0h

7 6 5 4 3 2 1 0
RESERVED DMAWRITE CPUWRITE CPUFETCH
R-0h R/W-0h R/W-0h R/W-0h

Table 3-33. MAVINTEN Register Field Descriptions

Bit Field Type Reset Description
31-16 RESERVED R 0h Reserved
15-3 RESERVED R 0h Reserved
2 DMAWRITE R/W 0h 0: DMA Write Access Violation Interrupt is disabled.
1: DMA Write Access Violation Interrupt is enabled.
Reset type: SYSRSn
1 CPUWRITE R/W 0h 0: CPU Write Access Violation Interrupt is disabled.
1: CPU Write Access Violation Interrupt is enabled.
Reset type: SYSRSn
0 CPUFETCH R/W 0h 0: CPU Fetch Access Violation Interrupt is disabled.
1: CPU Fetch Access Violation Interrupt is enabled.
Reset type: SYSRSn

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3.16.2.17 MCPUFAVADDR Register (Offset = 28h) [Reset = 0h]

MCPUFAVADDR is shown in Figure 3-36 and described in Table 3-34.
Return to the Summary Table.
Master CPU Fetch Access Violation Address
Figure 3-36. MCPUFAVADDR Register
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
MCPUFAVADDR
R-0h

Table 3-34. MCPUFAVADDR Register Field Descriptions

Bit Field Type Reset Description
31-0 MCPUFAVADDR R 0h This register captures the address location for which master CPU
fetch access vaiolation occurred.
Reset type: SYSRSn

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3.16.2.18 MCPUWRAVADDR Register (Offset = 2Ah) [Reset = 0h]

MCPUWRAVADDR is shown in Figure 3-37 and described in Table 3-35.
Return to the Summary Table.
Master CPU Write Access Violation Address
Figure 3-37. MCPUWRAVADDR Register
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
MCPUWRAVADDR
R-0h

Table 3-35. MCPUWRAVADDR Register Field Descriptions

Bit Field Type Reset Description
31-0 MCPUWRAVADDR R 0h This register captures the address location for which master CPU
write access vaiolation occurred.
Reset type: SYSRSn

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3.16.2.19 MDMAWRAVADDR Register (Offset = 2Ch) [Reset = 0h]

MDMAWRAVADDR is shown in Figure 3-38 and described in Table 3-36.
Return to the Summary Table.
Master DMA Write Access Violation Address
Figure 3-38. MDMAWRAVADDR Register
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
MDMAWRAVADDR
R-0h

Table 3-36. MDMAWRAVADDR Register Field Descriptions

Bit Field Type Reset Description
31-0 MDMAWRAVADDR R 0h This register captures the address location for which master DMA
write access vaiolation occurred.
Reset type: SYSRSn

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3.16.3 CLK_CFG_REGS Registers

Table 3-37 lists the memory-mapped registers for the CLK_CFG_REGS registers. All register offset addresses
not listed in Table 3-37 should be considered as reserved locations and the register contents should not be
modified.
Table 3-37. CLK_CFG_REGS Registers
Offset Acronym Register Name Write Protection Section
0h CLKSEM Clock Control Semaphore Register EALLOW Go
2h CLKCFGLOCK1 Lock bit for CLKCFG registers EALLOW Go
8h CLKSRCCTL1 Clock Source Control register-1 EALLOW Go
Ah CLKSRCCTL2 Clock Source Control register-2 EALLOW Go
Ch CLKSRCCTL3 Clock Source Control register-3 EALLOW Go
Eh SYSPLLCTL1 SYSPLL Control register-1 EALLOW Go
14h SYSPLLMULT SYSPLL Multiplier register EALLOW Go
16h SYSPLLSTS SYSPLL Status register Go
18h AUXPLLCTL1 AUXPLL Control register-1 EALLOW Go
1Eh AUXPLLMULT AUXPLL Multiplier register EALLOW Go
20h AUXPLLSTS AUXPLL Status register Go
22h SYSCLKDIVSEL System Clock Divider Select register EALLOW Go
24h AUXCLKDIVSEL Auxillary Clock Divider Select register EALLOW Go
26h PERCLKDIVSEL Peripheral Clock Divider Selet register EALLOW Go
28h XCLKOUTDIVSEL XCLKOUT Divider Select register EALLOW Go
2Ah CLBCLKCTL CLB Clocking Control Register EALLOW Go
2Ch LOSPCP Low Speed Clock Source Prescalar EALLOW Go
2Eh MCDCR Missing Clock Detect Control Register EALLOW Go
30h X1CNT 10-bit Counter on X1 Clock Go
32h XTALCR XTAL Control Register EALLOW Go
36h ETHERCATCLKCTL ETHERCATCLKCTL EALLOW Go
38h CMCLKCTL CMCLKCTL EALLOW Go

Complex bit access types are encoded to fit into small table cells. Table 3-38 shows the codes that are used for
access types in this section.
Table 3-38. CLK_CFG_REGS Access Type Codes
Access Type Code Description
Read Type
R R Read
R-0 R Read
-0 Returns 0s
Write Type
W W Write
W1S W Write
1S 1 to set
WSonce W Write
Sonce Set once
Reset or Default Value
-n Value after reset or the default
value
Register Array Variables

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Table 3-38. CLK_CFG_REGS Access Type Codes

(continued)
Access Type Code Description
i,j,k,l,m,n When these variables are used in
a register name, an offset, or an
address, they refer to the value of
a register array where the register
is part of a group of repeating
registers. The register groups
form a hierarchical structure and
the array is represented with a
formula.
y When this variable is used in a
register name, an offset, or an
address it refers to the value of
a register array.

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3.16.3.1 CLKSEM Register (Offset = 0h) [Reset = 0h]

CLKSEM is shown in Figure 3-39 and described in Table 3-39.
Return to the Summary Table.
Clock Control Semaphore Register
Figure 3-39. CLKSEM Register
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
KEY
R-0/W-0h

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RESERVED SEM
R-0-0h R/W-0h

Table 3-39. CLKSEM Register Field Descriptions

Bit Field Type Reset Description
31-16 KEY R-0/W 0h Writing the value 0xa5a5 will allow the writing of the SEM bits, else
writes are ignored. Reads will return 0.
Note:
[1] Due to this KEY, only 32-bit writes will succeed (provided the KEY
matches). 16-bit writes to the upper or lower half of this register will
be ignored
Reset type: CPU1.SYSRSn
15-2 RESERVED R-0 0h Reserved
1-0 SEM R/W 0h This register provides a mechanism to acquire all the CLKCFG
registers (except this register) by CPU1 or CPU2. A CPU can
perform read/writes to any of the CLKCFG registers (except this
register) only if it owns the semaphore. Otherwise, writes are ignored
and reads will return 0x0.
Semaphore State Transitions:
A value of 00, 10, 11 gives ownership to CPU1
A value of 01 gives ownership to CPU2.
The following are the only state transitions allowed on these bits.
00,11 <-> 01 (allowed by CPU2)
00,11 <-> 10 (allowed by CPU1)
If a CPU doesn't own the CLK_CFG_REGS set of registers (as
defined by the state of this semaphore), reads from that CPU to all
those registers return 0x0 and writes are ignore. Note that this is not
true of CLKSEM register. The CLKSEM register's reads and writes
are always allowed from both CPU1 and CPU2.
Reset type: CPU1.SYSRSn

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3.16.3.2 CLKCFGLOCK1 Register (Offset = 2h) [Reset = 0h]

CLKCFGLOCK1 is shown in Figure 3-40 and described in Table 3-40.
Return to the Summary Table.
Lock bit for CLKCFG registers
Notes:
[1] Any bit in this register, once set can only be cleared through a CPU1.SYSRSn. Write of 0 to any bit of this
register has no effect
[2] The locking mechanism applies to only writes. Reads to the registers which have LOCK protection are always
allowed
Figure 3-40. CLKCFGLOCK1 Register
31 30 29 28 27 26 25 24
RESERVED
R-0-0h

23 22 21 20 19 18 17 16
RESERVED CMCLKCTL ETHERCATCL XTALCR
KCTL
R-0-0h R/WSonce-0h R/WSonce-0h R/WSonce-0h

15 14 13 12 11 10 9 8
LOSPCP CLBCLKCTL PERCLKDIVSE AUXCLKDIVSE SYSCLKDIVSE AUXPLLMULT RESERVED RESERVED
L L L
R/WSonce-0h R/WSonce-0h R/WSonce-0h R/WSonce-0h R/WSonce-0h R/WSonce-0h R-0-0h R-0-0h

7 6 5 4 3 2 1 0
AUXPLLCTL1 SYSPLLMULT SYSPLLCTL3 SYSPLLCTL2 SYSPLLCTL1 CLKSRCCTL3 CLKSRCCTL2 CLKSRCCTL1
R/WSonce-0h R/WSonce-0h R/WSonce-0h R/WSonce-0h R/WSonce-0h R/WSonce-0h R/WSonce-0h R/WSonce-0h

Table 3-40. CLKCFGLOCK1 Register Field Descriptions

Bit Field Type Reset Description
31-19 RESERVED R-0 0h Reserved
18 CMCLKCTL R/WSonce 0h Lock bit for CMCLKCTL register:
0: Respective register is not locked
1: Respective register is locked.
Reset type: CPU1.SYSRSn
17 ETHERCATCLKCTL R/WSonce 0h Lock bit for ETHERCATCLKCTL register:
0: Respective register is not locked
1: Respective register is locked.
Reset type: CPU1.SYSRSn
16 XTALCR R/WSonce 0h Lock bit for XTALCR register:
0: Respective register is not locked
1: Respective register is locked.
Reset type: CPU1.SYSRSn
15 LOSPCP R/WSonce 0h Lock bit for LOSPCP register:
0: Respective register is not locked
1: Respective register is locked.
Reset type: CPU1.SYSRSn
14 CLBCLKCTL R/WSonce 0h Lock bit for CLBCLKCTL register:
0: Respective register is not locked
1: Respective register is locked.
Reset type: CPU1.SYSRSn
13 PERCLKDIVSEL R/WSonce 0h Lock bit for PERCLKDIVSEL register:
0: Respective register is not locked
1: Respective register is locked.
Reset type: CPU1.SYSRSn

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Table 3-40. CLKCFGLOCK1 Register Field Descriptions (continued)

Bit Field Type Reset Description
12 AUXCLKDIVSEL R/WSonce 0h Lock bit for AUXCLKDIVSEL register:
0: Respective register is not locked
1: Respective register is locked.
Reset type: CPU1.SYSRSn
11 SYSCLKDIVSEL R/WSonce 0h Lock bit for SYSCLKDIVSEL register:
0: Respective register is not locked
1: Respective register is locked.
Reset type: CPU1.SYSRSn
10 AUXPLLMULT R/WSonce 0h Lock bit for AUXPLLMULT register:
0: Respective register is not locked
1: Respective register is locked.
Reset type: CPU1.SYSRSn
9 RESERVED R-0 0h Reserved
8 RESERVED R-0 0h Reserved
7 AUXPLLCTL1 R/WSonce 0h Lock bit for AUXPLLCTL1 register:
0: Respective register is not locked
1: Respective register is locked.
Notes:
[1] Any bit in this register, once set can only be cleared through a
CPU1.SYSRSn. Write of 0 to any bit of this register has no effect
[2] The locking mechanism applies to only writes. Reads to the
registers which have LOCK protection are always allowed
Reset type: CPU1.SYSRSn
6 SYSPLLMULT R/WSonce 0h Lock bit for SYSPLLMULT register:
0: Respective register is not locked
1: Respective register is locked.
Notes:
[1] Any bit in this register, once set can only be cleared through a
CPU1.SYSRSn. Write of 0 to any bit of this register has no effect
[2] The locking mechanism applies to only writes. Reads to the
registers which have LOCK protection are always allowed
Reset type: CPU1.SYSRSn
5 SYSPLLCTL3 R/WSonce 0h Lock bit for SYSPLLCTL3 register:
0: Respective register is not locked
1: Respective register is locked.
Notes:
[1] Any bit in this register, once set can only be cleared through a
CPU1.SYSRSn. Write of 0 to any bit of this register has no effect
[2] The locking mechanism applies to only writes. Reads to the
registers which have LOCK protection are always allowed
Reset type: CPU1.SYSRSn
4 SYSPLLCTL2 R/WSonce 0h Lock bit for SYSPLLCTL2 register:
0: Respective register is not locked
1: Respective register is locked.
Notes:
[1] Any bit in this register, once set can only be cleared through a
CPU1.SYSRSn. Write of 0 to any bit of this register has no effect
[2] The locking mechanism applies to only writes. Reads to the
registers which have LOCK protection are always allowed
Reset type: CPU1.SYSRSn
3 SYSPLLCTL1 R/WSonce 0h Lock bit for SYSPLLCTL1 register:
0: Respective register is not locked
1: Respective register is locked.
Notes:
[1] Any bit in this register, once set can only be cleared through a
CPU1.SYSRSn. Write of 0 to any bit of this register has no effect
[2] The locking mechanism applies to only writes. Reads to the
registers which have LOCK protection are always allowed
Reset type: CPU1.SYSRSn

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Table 3-40. CLKCFGLOCK1 Register Field Descriptions (continued)

Bit Field Type Reset Description
2 CLKSRCCTL3 R/WSonce 0h Lock bit for CLKSRCCTL3 register:
0: Respective register is not locked
1: Respective register is locked.
Notes:
[1] Any bit in this register, once set can only be cleared through a
CPU1.SYSRSn. Write of 0 to any bit of this register has no effect
[2] The locking mechanism applies to only writes. Reads to the
registers which have LOCK protection are always allowed
Reset type: CPU1.SYSRSn
1 CLKSRCCTL2 R/WSonce 0h Lock bit for CLKSRCCTL2 register:
0: Respective register is not locked
1: Respective register is locked.
Notes:
[1] Any bit in this register, once set can only be cleared through a
CPU1.SYSRSn. Write of 0 to any bit of this register has no effect
[2] The locking mechanism applies to only writes. Reads to the
registers which have LOCK protection are always allowed
Reset type: CPU1.SYSRSn
0 CLKSRCCTL1 R/WSonce 0h Lock bit for CLKSRCCTL1 register:
0: Respective register is not locked
1: Respective register is locked.
Notes:
[1] Any bit in this register, once set can only be cleared through a
CPU1.SYSRSn. Write of 0 to any bit of this register has no effect
[2] The locking mechanism applies to only writes. Reads to the
registers which have LOCK protection are always allowed
Reset type: CPU1.SYSRSn

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3.16.3.3 CLKSRCCTL1 Register (Offset = 8h) [Reset = 0h]

CLKSRCCTL1 is shown in Figure 3-41 and described in Table 3-41.
Return to the Summary Table.
Clock Source Control register-1
This memory mapped register requires a delay of 69 SYSCLK cycles between subsequent writes to the register,
otherwise a second write can be lost. This delay can be realized by adding 69 NOP instructions.
Figure 3-41. CLKSRCCTL1 Register
31 30 29 28 27 26 25 24
RESERVED
R-0-0h

23 22 21 20 19 18 17 16
RESERVED
R-0-0h

15 14 13 12 11 10 9 8
RESERVED
R-0-0h

7 6 5 4 3 2 1 0
RESERVED RESERVED XTALOFF INTOSC2OFF_ RESERVED OSCCLKSRCSEL
NOTSUPPORT
ED
R-0-0h R/W-0h R/W-0h R/W-0h R-0-0h R/W-0h

Table 3-41. CLKSRCCTL1 Register Field Descriptions

Bit Field Type Reset Description
31-16 RESERVED R-0 0h Reserved
15-6 RESERVED R-0 0h Reserved
5 RESERVED R/W 0h Reserved
4 XTALOFF R/W 0h Crystal (External) Oscillator Off Bit: This bit turns external oscillator
off:
0 = Crystal (External) Oscillator On (default on reset)
1 = Crystal (External) Oscillator Off
NOTE: Ensure no resources are using a clock source prior
to disabling it. For example OSCCLKSRCSEL (SYSPLL),
AUXOSCCLKSRCSEL (AUXPLL), CANxBCLKSEL (CAN Clock),
TMR2CLKSRCSEL (CPUTIMER2) and XCLKOUTSEL(XCLKOUT).
Reset type: XRSn
3 INTOSC2OFF_NOTSUPP R/W 0h RESERVED: This bit is not supported any more, and should not be
ORTED set to 1.
Note: If this bit is set to 1 it will turn OFF INTOSC2 and lead to PLL
failure
Reset type: XRSn
2 RESERVED R-0 0h Reserved

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Table 3-41. CLKSRCCTL1 Register Field Descriptions (continued)

Bit Field Type Reset Description
1-0 OSCCLKSRCSEL R/W 0h Oscillator Clock Source Select Bit: This bit selects the source for
OSCCLK.
00 = INTOSC2 (default on reset)
01 = External Oscillator (XTAL)
10 = INTOSC1
11 = reserved (default to INTOSC1)
At power-up or after an XRSn, INTOSC2 is selected by default.
Whenever the user changes the clock source using these bits,
the SYSPLLMULT register will be forced to zero and the PLL
will be bypassed and powered down. This prevents potential PLL
overshoot. The user will then have to write to the SYSPLLMULT
register to configure the appropriate multiplier.
Notes:
[1] Reserved selection defaults to 00 configuration
[2] INTOSC1 is recommended to be used only after missing clock
detection. If user wants to re-lock the PLL with INTOSC1 (the
back-up clock source) after missing clock is detected, he can do a
MCLKCLR and lock the PLL.
[3] Any writes to this bit must be followed with at least 300 CPU
Cycles of wait time by adding at least 300 NOP instructions.
[4] Changing the OSCCLKSRC while PLL is running and used
by system (i.e. PLLCLKEN=1), can lead to dead System Clock.
User needs to first bypass the PLL clock from the system by
PLLCLKEN=0, and then change the OSCCLK source.
Reset type: XRSn

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3.16.3.4 CLKSRCCTL2 Register (Offset = Ah) [Reset = 0h]

CLKSRCCTL2 is shown in Figure 3-42 and described in Table 3-42.
Return to the Summary Table.
Clock Source Control register-2
This memory mapped register requires a delay of 69 SYSCLK cycles between subsequent writes to the register,
otherwise a second write can be lost. This delay can be realized by adding 69 NOP instructions.
Figure 3-42. CLKSRCCTL2 Register
31 30 29 28 27 26 25 24
RESERVED
R-0-0h

23 22 21 20 19 18 17 16
RESERVED
R-0-0h

15 14 13 12 11 10 9 8
RESERVED MCANABITCLKSEL RESERVED
R-0-0h R/W-0h R/W-0h

7 6 5 4 3 2 1 0
RESERVED CANBBCLKSEL CANABCLKSEL AUXOSCCLKSRCSEL
R/W-0h R/W-0h R/W-0h R/W-0h

Table 3-42. CLKSRCCTL2 Register Field Descriptions

Bit Field Type Reset Description
31-16 RESERVED R-0 0h Reserved
15-12 RESERVED R-0 0h Reserved
11-10 MCANABITCLKSEL R/W 0h MCAN Bit Clock Source Select Bit:
00 = CM.Perx.SYSCLK or CPU1.PERx.SYSCLK based on
PALLOCATE.MCAN_A setting.
01 = AUXPLLRAWCLK
10 = AUXCLKIN
11 = Rsvd
If bit timing clock source has to change, then PCLKCR bit for the
corresponding MCAN instance has to be cleared to '0' first before
updating the values in thies field. Once the value is updated, the
corresponding PCLKCR bit of this instance can be set back to '1'.
Reset type: XRSn
9-8 RESERVED R/W 0h Reserved
7-6 RESERVED R/W 0h Reserved
5-4 CANBBCLKSEL R/W 0h CANB Bit Clock Source Select Bit:
00 = CPUx.PERx.SYSCLK (default on reset), if PALLOCATE0.CANB
is 0. Else CM.Perx.SYSCLK.
01 = External Oscillator (XTAL)
10 = AUXCLKIN (from GPIO)
11 = Reserved
Missing clock detect circuit doesnt have any impact on these bits.
If bit timing clock source has to change, then PCLKCR bit for the
corresponding DCAN instance has to be cleared to '0' first before
updating the values in thies field. Once the value is updated, the
corresponding PCLKCR bit of this instance can be set back to '1'.
Reset type: XRSn

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Table 3-42. CLKSRCCTL2 Register Field Descriptions (continued)

Bit Field Type Reset Description
3-2 CANABCLKSEL R/W 0h CANA Bit Clock Source Select Bit:
00 = PERx.SYSCLK (default on reset),if PALLOCATE0.CANA is 0
else
CMCLK.
01 = External Oscillator (XTAL)
10 = AUXCLKIN (from GPIO)
11 = Reserved
Missing clock detect circuit doesnt have any impact on these bits.
If bit timing clock source has to change, then PCLKCR bit for the
corresponding DCAN instance has to be cleared to '0' first before
updating the values in thies field. Once the value is updated, the
corresponding PCLKCR bit of this instance can be set back to '1'.
Reset type: XRSn
1-0 AUXOSCCLKSRCSEL R/W 0h Oscillator Clock Source Select Bit: This bit selects the source for
AUXOSCCLK:
00 = INTOSC2 (default on reset)
01 = External Oscillator (XTAL)
10 = AUXCLKIN (from GPIO)
11 = Reserved(default to INTOSC2)
Whenever the user changes the clock source using these bits,
the AUXPLLMULT register will be forced to zero. The user will
then have to write to the AUXPLLMULT register to configure the
appropriate multiplier.
The user must wait 10 OSCCLK cycles before writing to
AUXPLLMULT
or disabling the previous clock source to allow the change to
complete.
The missing clock detection circuit does not affect these bits.
Notes:
[1] Changing the AUXOSCCLKSRC while PLL is running and
AUXPLLCLKEN=1, can lead to dead AUXPLLCLK. User needs to
first bypass the AUXPLL by AUXPLLCLKEN=0, and then change the
AUXOSCCLK source.
Reset type: XRSn

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3.16.3.5 CLKSRCCTL3 Register (Offset = Ch) [Reset = 0h]

CLKSRCCTL3 is shown in Figure 3-43 and described in Table 3-43.
Return to the Summary Table.
Clock Source Control register-3
This memory mapped register requires a delay of 69 SYSCLK cycles between subsequent writes to the register,
otherwise a second write can be lost. This delay can be realized by adding 69 NOP instructions.
Figure 3-43. CLKSRCCTL3 Register
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
RESERVED
R-0-0h

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RESERVED XCLKOUTSEL
R-0-0h R/W-0h

Table 3-43. CLKSRCCTL3 Register Field Descriptions

Bit Field Type Reset Description
31-16 RESERVED R-0 0h Reserved
15-4 RESERVED R-0 0h Reserved
3-0 XCLKOUTSEL R/W 0h XCLKOUT Source Select Bit: This bit selects the source for
XCLKOUT:
0000 = PLLSYSCLK (default on reset)
0001 = SYSPLLCLK
0010 = CPU1.SYSCLK
0011 = CPU2.SYSCLK
0100 = AUXPLLCLK
0101 = INTOSC1
0110 = INTOSC2
0111 = XTAL OSC o/p clock
1000 = CMCLK
1100 = PLLRAWCLK
1101 = AUXPLLRAWCLK
others = Reserved
Reset type: CPU1.SYSRSn

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3.16.3.6 SYSPLLCTL1 Register (Offset = Eh) [Reset = 0h]

SYSPLLCTL1 is shown in Figure 3-44 and described in Table 3-44.
Return to the Summary Table.
SYSPLL Control register-1
Figure 3-44. SYSPLLCTL1 Register
31 30 29 28 27 26 25 24
RESERVED
R-0-0h

23 22 21 20 19 18 17 16
RESERVED
R-0-0h

15 14 13 12 11 10 9 8
RESERVED
R-0-0h

7 6 5 4 3 2 1 0
RESERVED RESERVED RESERVED RESERVED PLLCLKEN PLLEN
R-0-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h

Table 3-44. SYSPLLCTL1 Register Field Descriptions

Bit Field Type Reset Description
31-16 RESERVED R-0 0h Reserved
15-5 RESERVED R-0 0h Reserved
4 RESERVED R/W 0h Reserved
3 RESERVED R/W 0h Reserved
2 RESERVED R/W 0h Reserved
1 PLLCLKEN R/W 0h SYSPLL bypassed or included in the PLLSYSCLK path: This bit
decides if the SYSPLL is bypassed when PLLSYSCLK is generated
1 = PLLSYSCLK is fed from the SYSPLL clock output. Users need
to make sure that the PLL is locked before enabling this clock to the
system.
0 = SYSPLL is bypassed. Clock to system is direct feed from
OSCCLK
Note: Any writes to this bit must be followed with at least 120 CPU
Cycles of wait time by adding at least 120 NOP instructions.
Reset type: XRSn
0 PLLEN R/W 0h SYSPLL enabled or disabled: This bit decides if the SYSPLL is
enabled or not
1 = SYSPLL is enabled
0 = SYSPLL is powered off. Clock to system is direct feed from
OSCCLK
Note: Any writes to this bit must be followed with at least 60 CPU
Cycles of wait time by adding at least 60 NOP instructions.
Reset type: XRSn

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3.16.3.7 SYSPLLMULT Register (Offset = 14h) [Reset = 0h]

SYSPLLMULT is shown in Figure 3-45 and described in Table 3-45.
Return to the Summary Table.
SYSPLL Multiplier register
NOTE:
IMULT and REFDIV fields in this register must be written at the same time and ONLY when
SYSPLLCTL1.PLLCLKEN=0 for correct PLL operation. If IMULT or REFDIV values are changed after
SYSPLLCTL1.PLLCLKEN=1 then it will disrupt PLL operation and cause system hangup.
This memory mapped register requires a delay of 69 SYSCLK cycles between subsequent writes to the register,
otherwise a second write can be lost. This delay can be realized by adding 69 NOP instructions.
Figure 3-45. SYSPLLMULT Register
31 30 29 28 27 26 25 24
RESERVED REFDIV
R-0-0h R/W-0h

23 22 21 20 19 18 17 16
RESERVED ODIV
R-0-0h R/W-0h

15 14 13 12 11 10 9 8
RESERVED RESERVED RESERVED RESERVED
R-0-0h R/W-0h R-0-0h R/W-0h

7 6 5 4 3 2 1 0
IMULT
R/W-0h

Table 3-45. SYSPLLMULT Register Field Descriptions

Bit Field Type Reset Description
31-29 RESERVED R-0 0h Reserved
28-24 REFDIV R/W 0h SYSPLL Reference Clock Divider
PLL Reference Divider = REFDIV + 1
NOTE:
IMULT and REFDIV fields in this register must be written at the
same time and ONLY when SYSPLLCTL1.PLLCLKEN=0 for correct
PLL operation. If IMULT or REFDIV values are changed after
SYSPLLCTL1.PLLCLKEN=1 then it will disrupt PLL operation and
cause system hangup.
Reset type: XRSn
23-21 RESERVED R-0 0h Reserved
20-16 ODIV R/W 0h SYSPLL Output Clock Divider
PLL Output Divider = ODIV + 1
ODIV should be set to at least 1 to ensure the PLL output meets
system duty cycle requirements.
NOTE:
If PLL is powered when SYSPLLCTL1.PLLCLKEN=0, then
it is recommended to write IMULT, REFDIV and ODIV at
the same time. This field can ALSO be programmed after
SYSPLLCTL1.PLLCLKEN=1 if application desires to change the
output divider of PLL clock, but proper care must be taken to
make sure values of IMULT and REFDIV are left unchanged when
SYSPLLCTL1.PLLCLKEN=1, if values of IMULT or REFDIV are
change after SYSPLLCTL1.PLLCLKEN=1 then it will disrupt PLL
operation and cause system hangup.
Reset type: XRSn
15-14 RESERVED R-0 0h Reserved

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Table 3-45. SYSPLLMULT Register Field Descriptions (continued)

Bit Field Type Reset Description
13-12 RESERVED R/W 0h Reserved
11-10 RESERVED R-0 0h Reserved
9-8 RESERVED R/W 0h Reserved
7-0 IMULT R/W 0h SYSPLL Integer Multiplier:
For 0000000 Fout = Fref (PLLBYPASS) Integer Multiplier = 1
0000001 Integer Multiplier = 1
0000010 Integer Multiplier = 2
0000011 Integer Multiplier = 3
.......
1111111 Integer Multipler = 127
NOTE:
IMULT and REFDIV fields in this register must be written at the
same time and ONLY when SYSPLLCTL1.PLLCLKEN=0 for correct
PLL operation. If IMULT or REFDIV values are changed after
SYSPLLCTL1.PLLCLKEN=1 then it will disrupt PLL opeartion and
cause system hangup.
Reset type: XRSn

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3.16.3.8 SYSPLLSTS Register (Offset = 16h) [Reset = 0h]

SYSPLLSTS is shown in Figure 3-46 and described in Table 3-46.
Return to the Summary Table.
SYSPLL Status register
Figure 3-46. SYSPLLSTS Register
31 30 29 28 27 26 25 24
RESERVED
R-0-0h

23 22 21 20 19 18 17 16
RESERVED
R-0-0h

15 14 13 12 11 10 9 8
RESERVED
R-0-0h

7 6 5 4 3 2 1 0
RESERVED RESERVED RESERVED SLIPS_NOTSU LOCKS
PPORTED
R-0-0h R-0h R-0h R-0h R-0h

Table 3-46. SYSPLLSTS Register Field Descriptions

Bit Field Type Reset Description
31-16 RESERVED R-0 0h Reserved
15-4 RESERVED R-0 0h Reserved
3 RESERVED R 0h Reserved
2 RESERVED R 0h Reserved
1 SLIPS_NOTSUPPORTED R 0h RESERVED: This bit is reserved and the value read should be
ignored. TI recommends using DCC to evaluate SYSPLL Slip status.
Refer to InitSysPll() or SysCtl_setClock() functions inside the latest
example software from C2000Ware for checking SYSPLL Slip status
using DCC.
Reset type: XRSn
0 LOCKS R 0h SYSPLL Lock Status Bit: This bit indicates whether the SYSPLL is
locked or not
0 = SYSPLL is not yet locked
1 = SYSPLL is locked
Reset type: XRSn

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3.16.3.9 AUXPLLCTL1 Register (Offset = 18h) [Reset = 0h]

AUXPLLCTL1 is shown in Figure 3-47 and described in Table 3-47.
Return to the Summary Table.
AUXPLL Control register-1
Figure 3-47. AUXPLLCTL1 Register
31 30 29 28 27 26 25 24
RESERVED
R-0-0h

23 22 21 20 19 18 17 16
RESERVED
R-0-0h

15 14 13 12 11 10 9 8
RESERVED
R-0-0h

7 6 5 4 3 2 1 0
RESERVED RESERVED RESERVED RESERVED PLLCLKEN PLLEN
R-0-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h

Table 3-47. AUXPLLCTL1 Register Field Descriptions

Bit Field Type Reset Description
31-16 RESERVED R-0 0h Reserved
15-5 RESERVED R-0 0h Reserved
4 RESERVED R/W 0h Reserved
3 RESERVED R/W 0h Reserved
2 RESERVED R/W 0h Reserved
1 PLLCLKEN R/W 0h AUXPLL bypassed or included in the AUXPLLCLK path: This bit
decides if the AUXPLL is bypassed when AUXPLLCLK is generated
1 = AUXPLLCLK is fed from the AUXPLL clock output. Users need
to make sure that the PLL is locked before enabling this clock to the
AUXPLLCLK connected modules.
0 = AUXPLL is bypassed. Clock to modules connected to
AUXPLLCLK is direct feed from AUXOSCCLK
Reset type: XRSn
0 PLLEN R/W 0h AUXPLL enabled or disabled: This bit decides if the AUXPLL is
enabled or not
1 = AUXPLL is enabled
0 = AUXPLL is powered off. Clock to system is direct feed from
AUXOSCCLK
Reset type: XRSn

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3.16.3.10 AUXPLLMULT Register (Offset = 1Eh) [Reset = 0h]

AUXPLLMULT is shown in Figure 3-48 and described in Table 3-48.
Return to the Summary Table.
AUXPLL Multiplier register
NOTE:
IMULT and REFDIV fields in this register must be written at the same time and ONLY when
AUXPLLCTL1.PLLCLKEN=0 for correct PLL operation. If IMULT or REFDIV values are changed after
AUXPLLCTL1.PLLCLKEN=1 then it will disrupt PLL operation.
This memory mapped register requires a delay of 69 SYSCLK cycles between subsequent writes to the register,
otherwise a second write can be lost. This delay can be realized by adding 69 NOP instructions.
Figure 3-48. AUXPLLMULT Register
31 30 29 28 27 26 25 24
RESERVED REFDIV
R-0-0h R/W-0h

23 22 21 20 19 18 17 16
RESERVED ODIV
R-0-0h R/W-0h

15 14 13 12 11 10 9 8
RESERVED RESERVED RESERVED RESERVED
R-0-0h R/W-0h R-0-0h R/W-0h

7 6 5 4 3 2 1 0
IMULT
R/W-0h

Table 3-48. AUXPLLMULT Register Field Descriptions

Bit Field Type Reset Description
31-29 RESERVED R-0 0h Reserved
28-24 REFDIV R/W 0h AUXPLL Reference Clock Divider
PLL Reference Divider = REFDIV + 1
NOTE:
IMULT and REFDIV fields in this register must be written at the
same time and ONLY when AUXPLLCTL1.PLLCLKEN=0 for correct
PLL operation. If IMULT or REFDIV values are changed after
AUXPLLCTL1.PLLCLKEN=1 then it will disrupt PLL operation.
Reset type: XRSn
23-21 RESERVED R-0 0h Reserved
20-16 ODIV R/W 0h AUXPLL Output Clock Divider
PLL Output Divider = ODIV + 1
ODIV should be set to at least 1 to ensure the PLL output meets
system duty cycle requirements.
NOTE:
If PLL is powered when AUXPLLCTL1.PLLCLKEN=0, then
it is recommended to write IMULT, REFDIV and ODIV at
the same time. This field can ALSO be programmed after
AUXPLLCTL1.PLLCLKEN=1 if application desires to change the
output divider of PLL clock, but proper care must be taken to
make sure values of IMULT and REFDIV are left unchanged when
AUXPLLCTL1.PLLCLKEN=1, if values of IMULT or REFDIV are
change after AUXPLLCTL1.PLLCLKEN=1 then it will disrupt PLL
operation.
Reset type: XRSn
15-14 RESERVED R-0 0h Reserved
13-12 RESERVED R/W 0h Reserved

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Table 3-48. AUXPLLMULT Register Field Descriptions (continued)

Bit Field Type Reset Description
11-10 RESERVED R-0 0h Reserved
9-8 RESERVED R/W 0h Reserved
7-0 IMULT R/W 0h AUXPLL Integer Multiplier:
For 0000000 Fout = Fref (PLLBYPASS) Integer Multiplier = 1
0000001 Integer Multiplier = 1
0000010 Integer Multiplier = 2
0000011 Integer Multiplier = 3
.......
1111111 Integer Multipler = 127
NOTE:
IMULT and REFDIV fields in this register must be written at the
same time and ONLY when AUXPLLCTL1.PLLCLKEN=0 for correct
PLL operation. If IMULT or REFDIV values are changed after
AUXPLLCTL1.PLLCLKEN=1 then it will disrupt PLL operation.
Reset type: XRSn

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3.16.3.11 AUXPLLSTS Register (Offset = 20h) [Reset = 0h]

AUXPLLSTS is shown in Figure 3-49 and described in Table 3-49.
Return to the Summary Table.
AUXPLL Status register
Figure 3-49. AUXPLLSTS Register
31 30 29 28 27 26 25 24
RESERVED
R-0-0h

23 22 21 20 19 18 17 16
RESERVED
R-0-0h

15 14 13 12 11 10 9 8
RESERVED
R-0-0h

7 6 5 4 3 2 1 0
RESERVED RESERVED RESERVED SLIPS_NOTSU LOCKS
PPORTED
R-0-0h R-0h R-0h R-0h R-0h

Table 3-49. AUXPLLSTS Register Field Descriptions

Bit Field Type Reset Description
31-16 RESERVED R-0 0h Reserved
15-4 RESERVED R-0 0h Reserved
3 RESERVED R 0h Reserved
2 RESERVED R 0h Reserved
1 SLIPS_NOTSUPPORTED R 0h RESERVED: This bit is reserved and the value read should be
ignored. TI recommends using DCC to evaluate AUXPLL Slip status.
Refer to InitAuxPll() or SysCtl_setAuxClock() functions inside the
latest example software from C2000Ware for checking AUXPLL Slip
status using DCC.
Reset type: XRSn
0 LOCKS R 0h AUXPLL Lock Status Bit: This bit indicates whether the AUXPLL is
locked or not
0 = AUXPLL is not yet locked
1 = AUXPLL is locked
Reset type: XRSn

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3.16.3.12 SYSCLKDIVSEL Register (Offset = 22h) [Reset = 0h]

SYSCLKDIVSEL is shown in Figure 3-50 and described in Table 3-50.
Return to the Summary Table.
System Clock Divider Select register
This memory mapped register requires a delay of 69 SYSCLK cycles between subsequent writes to the register,
otherwise a second write can be lost. This delay can be realized by adding 69 NOP instructions.
Figure 3-50. SYSCLKDIVSEL Register
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
RESERVED
R-0-0h

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RESERVED PLLSYSCLKDIV
R-0-0h R/W-0h

Table 3-50. SYSCLKDIVSEL Register Field Descriptions

Bit Field Type Reset Description
31-16 RESERVED R-0 0h Reserved
15-6 RESERVED R-0 0h Reserved
5-0 PLLSYSCLKDIV R/W 0h PLLSYSCLK Divide Select: This bit selects the divider setting for the
PLLSYSCLK.
0000 = /1
0001 = /2
0010 = /4
0011 = /6
0100 = /8
0101 = /10
0110 = /12
0111 = /14
1000 = /16
Others: Reserved
Reset type: XRSn

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3.16.3.13 AUXCLKDIVSEL Register (Offset = 24h) [Reset = 1301h]

AUXCLKDIVSEL is shown in Figure 3-51 and described in Table 3-51.
Return to the Summary Table.
Auxillary Clock Divider Select register
This memory mapped register requires a delay of 69 SYSCLK cycles between subsequent writes to the register,
otherwise a second write can be lost. This delay can be realized by adding 69 NOP instructions.
Figure 3-51. AUXCLKDIVSEL Register
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
RESERVED
R-0-0h

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RESERVED MCANCLKDIV RESERVED AUXPLLDIV
R-0-0h R/W-13h R-0-0h R/W-1h

Table 3-51. AUXCLKDIVSEL Register Field Descriptions

Bit Field Type Reset Description
31-13 RESERVED R-0 0h Reserved
12-8 MCANCLKDIV R/W 13h This bit-field divides the source clock (chosen by the
CLKSRCCTL2.MCANABITCLKSEL bit-field) before feeding it as the
bit-clock to the MCAN module
00000 = /1
00001 = /2
...
10010 = /19
10011 = /20
101xx = Rsvd
11xxx = Rsvd
Reset type: XRSn
7-3 RESERVED R-0 0h Reserved
2-0 AUXPLLDIV R/W 1h AUXPLLCLK Divide Select: This bit selects the divider setting for the
AUXPLLCK.
000 = /1
001 = /2 (default on reset)
010 = /4
011 = /8
100 = /3
101 = /5
110 = /6
111 = /7
Reset type: XRSn

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3.16.3.14 PERCLKDIVSEL Register (Offset = 26h) [Reset = 51h]

PERCLKDIVSEL is shown in Figure 3-52 and described in Table 3-52.
Return to the Summary Table.
Peripheral Clock Divider Selet register
This memory mapped register requires a delay of 69 SYSCLK cycles between subsequent writes to the register,
otherwise a second write can be lost. This delay can be realized by adding 69 NOP instructions.
Figure 3-52. PERCLKDIVSEL Register
31 30 29 28 27 26 25 24
RESERVED
R-0-0h

23 22 21 20 19 18 17 16
RESERVED
R-0-0h

15 14 13 12 11 10 9 8
RESERVED
R-0-0h

7 6 5 4 3 2 1 0
RESERVED EMIF2CLKDIV RESERVED EMIF1CLKDIV RESERVED EPWMCLKDIV
R-0-0h R/W-1h R-0-0h R/W-1h R/W-0h R/W-1h

Table 3-52. PERCLKDIVSEL Register Field Descriptions

Bit Field Type Reset Description
31-16 RESERVED R-0 0h Reserved
15-7 RESERVED R-0 0h Reserved
6 EMIF2CLKDIV R/W 1h EMIF2 Clock Divide Select: This bit selects whether the EMIF2
module run with a /1 or /2 clock.
0: /1 of CPU1.SYSCLK is selected
1: /2 of CPU1.SYSCLK is selected
Reset type: CPU1.SYSRSn
5 RESERVED R-0 0h Reserved
4 EMIF1CLKDIV R/W 1h EMIF1 Clock Divide Select: This bit selects whether the EMIF1
module run with a /1 or /2 clock.
For single core device
0: /1 of CPU1.SYSCLK is selected
1: /2 of CPU1.SYSCLK is selected
For Dual core device
0: /1 of PLLSYSCLK is selected
1: /2 of PLLSYSCLK is selected
Reset type: CPU1.SYSRSn
3-2 RESERVED R/W 0h Reserved
1-0 EPWMCLKDIV R/W 1h EPWM Clock Divide Select: This bit selects whether the EPWM
modules run with a /1 or /2 clock. This divider sits in front of the
PLLSYSCLK
x0 = /1 of PLLSYSCLK
x1 = /2 of PLLSYSLCK (default on reset)
Note: Refer to the EPWM User Guide for maximum EPWM
Frequency
Reset type: CPU1.SYSRSn

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3.16.3.15 XCLKOUTDIVSEL Register (Offset = 28h) [Reset = 3h]

XCLKOUTDIVSEL is shown in Figure 3-53 and described in Table 3-53.
Return to the Summary Table.
XCLKOUT Divider Select register
This memory mapped register requires a delay of 69 SYSCLK cycles between subsequent writes to the register,
otherwise a second write can be lost. This delay can be realized by adding 69 NOP instructions.
Figure 3-53. XCLKOUTDIVSEL Register
31 30 29 28 27 26 25 24
RESERVED
R-0-0h

23 22 21 20 19 18 17 16
RESERVED
R-0-0h

15 14 13 12 11 10 9 8
RESERVED
R-0-0h

7 6 5 4 3 2 1 0
RESERVED XCLKOUTDIV
R-0-0h R/W-3h

Table 3-53. XCLKOUTDIVSEL Register Field Descriptions

Bit Field Type Reset Description
31-16 RESERVED R-0 0h Reserved
15-2 RESERVED R-0 0h Reserved
1-0 XCLKOUTDIV R/W 3h XCLKOUT Divide Select: This bit selects the divider setting for the
XCLKOUT.
00 = /1
01 = /2
10 = /4
11 = /8 (default on reset)
Reset type: CPU1.SYSRSn

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3.16.3.16 CLBCLKCTL Register (Offset = 2Ah) [Reset = 7h]

CLBCLKCTL is shown in Figure 3-54 and described in Table 3-54.
Return to the Summary Table.
CLB Clocking Control Register
This memory mapped register requires a delay of 69 SYSCLK cycles between subsequent writes to the register,
otherwise a second write can be lost. This delay can be realized by adding 69 NOP instructions.
Figure 3-54. CLBCLKCTL Register
31 30 29 28 27 26 25 24
RESERVED
R-0-0h

23 22 21 20 19 18 17 16
CLKMODECLB CLKMODECLB CLKMODECLB CLKMODECLB CLKMODECLB CLKMODECLB CLKMODECLB CLKMODECLB
8 7 6 5 4 3 2 1
R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h

15 14 13 12 11 10 9 8
RESERVED
R-0-0h

7 6 5 4 3 2 1 0
RESERVED TILECLKDIV RESERVED CLBCLKDIV
R-0-0h R/W-0h R-0-0h R/W-7h

Table 3-54. CLBCLKCTL Register Field Descriptions

Bit Field Type Reset Description
31-24 RESERVED R-0 0h Reserved
23 CLKMODECLB8 R/W 0h 0 : CLB8 is synchronous to SYSCLK
1 : CLB8 runs of asynchronous clock
Reset type: SYSRSn
22 CLKMODECLB7 R/W 0h 0 : CLB7 is synchronous to SYSCLK
1 : CLB7 runs of asynchronous clock
Reset type: SYSRSn
21 CLKMODECLB6 R/W 0h 0 : CLB6 is synchronous to SYSCLK
1 : CLB6 runs of asynchronous clock
Reset type: SYSRSn
20 CLKMODECLB5 R/W 0h 0 : CLB5 is synchronous to SYSCLK
1 : CLB5 runs of asynchronous clock
Reset type: SYSRSn
19 CLKMODECLB4 R/W 0h 0 : CLB4 is synchronous to SYSCLK
1 : CLB4 runs of asynchronous clock
Reset type: SYSRSn
18 CLKMODECLB3 R/W 0h 0 : CLB3 is synchronous to SYSCLK
1 : CLB3 runs of asynchronous clock
Reset type: SYSRSn
17 CLKMODECLB2 R/W 0h 0 : CLB2 is synchronous to SYSCLK
1 : CLB2 runs of asynchronous clock
Reset type: SYSRSn
16 CLKMODECLB1 R/W 0h 0 : CLB1 is synchronous to SYSCLK
1 : CLB1 runs of asynchronous clock
Reset type: SYSRSn
15-5 RESERVED R-0 0h Reserved
4 TILECLKDIV R/W 0h 0: /1
1: /2
Reset type: SYSRSn

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Table 3-54. CLBCLKCTL Register Field Descriptions (continued)

Bit Field Type Reset Description
3 RESERVED R-0 0h Reserved
2-0 CLBCLKDIV R/W 7h 000: /1
001: /2
010: /3
011: /4
100: /5
101: /6
110: /7
111: /8
Reset type: SYSRSn

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3.16.3.17 LOSPCP Register (Offset = 2Ch) [Reset = 2h]

LOSPCP is shown in Figure 3-55 and described in Table 3-55.
Return to the Summary Table.
Low Speed Clock Source Prescalar
Figure 3-55. LOSPCP Register
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
RESERVED
R-0-0h

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RESERVED LSPCLKDIV
R-0-0h R/W-2h

Table 3-55. LOSPCP Register Field Descriptions

Bit Field Type Reset Description
31-16 RESERVED R-0 0h Reserved
15-3 RESERVED R-0 0h Reserved
2-0 LSPCLKDIV R/W 2h These bits configure the low-speed peripheral clock (LSPCLK) rate
relative to SYSCLK of CPU1 and CPU2.
000,LSPCLK = / 1
001,LSPCLK = / 2
010,LSPCLK = / 4 (default on reset)
011,LSPCLK = / 6
100,LSPCLK = / 8
101,LSPCLK = / 10
110,LSPCLK = / 12
111,LSPCLK = / 14
Note:
[1] This clock is used as strobe for the SCI and SPI modules.
Reset type: CPU1.SYSRSn

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3.16.3.18 MCDCR Register (Offset = 2Eh) [Reset = 0h]

MCDCR is shown in Figure 3-56 and described in Table 3-56.
Return to the Summary Table.
Missing Clock Detect Control Register
Figure 3-56. MCDCR Register
31 30 29 28 27 26 25 24
RESERVED
R-0-0h

23 22 21 20 19 18 17 16
RESERVED
R-0-0h

15 14 13 12 11 10 9 8
RESERVED
R-0-0h

7 6 5 4 3 2 1 0
RESERVED OSCOFF MCLKOFF MCLKCLR MCLKSTS
R-0-0h R/W-0h R/W-0h R-0/W1S-0h R-0h

Table 3-56. MCDCR Register Field Descriptions

Bit Field Type Reset Description
31-16 RESERVED R-0 0h Reserved
15-4 RESERVED R-0 0h Reserved
3 OSCOFF R/W 0h Oscillator Clock Disconnect from MCD Bit:
0 = OSCCLK Connected to OSCCLK Counter in MCD module
1 = OSCCLK Disconnected to OSCCLK Counter in MCD module
Reset type: XRSn
2 MCLKOFF R/W 0h Missing Clock Detect Off Bit:
0 = Missing Clock Detect Circuit Enabled
1 = Missing Clock Detect Circuit Disabled
Reset type: XRSn
1 MCLKCLR R-0/W1S 0h Missing Clock Clear Bit:
Write 1" to this bit to clear MCLKSTS bit and reset the missing clock
detect circuit."
Reset type: XRSn
0 MCLKSTS R 0h Missing Clock Status Bit:
0 = OSCCLK Is OK
1 = OSCCLK Detected Missing, CLOCKFAILn Generated
Reset type: XRSn

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3.16.3.19 X1CNT Register (Offset = 30h) [Reset = 0h]

X1CNT is shown in Figure 3-57 and described in Table 3-57.
Return to the Summary Table.
10-bit Counter on X1 Clock
Figure 3-57. X1CNT Register
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
RESERVED CLR
R-0-0h R/W-0h

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RESERVED X1CNT
R-0-0h R-0h

Table 3-57. X1CNT Register Field Descriptions

Bit Field Type Reset Description
31-17 RESERVED R-0 0h Reserved
16 CLR R/W 0h X1 Counter clear:
1: X1CNT clear is asserted
0: X1CNT clear is de-asserted
Reset type: XRSn
15-10 RESERVED R-0 0h Reserved
9-0 X1CNT R 0h X1 Counter:
- This counter increments on every X1 CLOCKs positive-edge.
- Once it reaches the values of 0x3ff, it freezes
- Before switching from INTOSC2 to X1, application must check this
counter and make sure that it has saturated. This will ensure that the
Crystal connected to X1/X2 is oscillating.
Note: Before switching the OSCCCLKSRC to X1, X1CNT register
needs to be read at least 3 times for 0x3FF value. Refer C2000Ware
function "SysCtl_pollX1Counter" for SW implementation.
Reset type: XRSn

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3.16.3.20 XTALCR Register (Offset = 32h) [Reset = 4h]

XTALCR is shown in Figure 3-58 and described in Table 3-58.
Return to the Summary Table.
XTAL Control Register
This memory mapped register requires a delay of 69 SYSCLK cycles between subsequent writes to the register,
otherwise a second write can be lost. This delay can be realized by adding 69 NOP instructions.
Figure 3-58. XTALCR Register
31 30 29 28 27 26 25 24
RESERVED
R-0-0h

23 22 21 20 19 18 17 16
RESERVED
R-0-0h

15 14 13 12 11 10 9 8
RESERVED
R-0-0h

7 6 5 4 3 2 1 0
RESERVED RESERVED SE OSCOFF
R-0-0h R/W-1h R/W-0h R/W-0h

Table 3-58. XTALCR Register Field Descriptions

Bit Field Type Reset Description
31-3 RESERVED R-0 0h Reserved
2 RESERVED R/W 1h Reserved
1 SE R/W 0h Configures XTAL oscillator in single-ended or Crystal mode when
XTAL oscillator is powered (OFF = 0)
0 XTAL oscillator in Crystal mode
1 XTAL oscilator in single0ended mode (through X1)
Reset type: XRSn
0 OSCOFF R/W 0h This bit if '1', powers-down the XTAL oscillator macro and hence
doesn't let X2 to be driven by the XTAL oscillator. If a crystal is
connected to X1/X2, user needs to first clear this bit, wait for the
oscillator to power up (using X1CNT) and then only switch the clock
source to X1/X2
Reset type: XRSn

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3.16.3.21 ETHERCATCLKCTL Register (Offset = 36h) [Reset = Eh]

ETHERCATCLKCTL is shown in Figure 3-59 and described in Table 3-59.
Return to the Summary Table.
ETHERCAT clock control register.
This memory mapped register requires a delay of 69 SYSCLK cycles between subsequent writes to the register,
otherwise a second write can be lost. This delay can be realized by adding 69 NOP instructions.
Figure 3-59. ETHERCATCLKCTL Register
31 30 29 28 27 26 25 24
RESERVED
R-0h

23 22 21 20 19 18 17 16
RESERVED
R-0h

15 14 13 12 11 10 9 8
RESERVED PHYCLKEN
R-0h R/W-0h

7 6 5 4 3 2 1 0
RESERVED ECATDIV DIVSRCSEL
R-0-0h R/W-7h R/W-0h

Table 3-59. ETHERCATCLKCTL Register Field Descriptions

Bit Field Type Reset Description
31-9 RESERVED R 0h Reserved
8 PHYCLKEN R/W 0h 0 : etherCAT phy clock disabled
1 : etherCAT phy clock enabled
Reset type: XRSn
7-4 RESERVED R-0 0h Reserved
3-1 ECATDIV R/W 7h 000: /1
001: /2
010: /3
011: /4
100: /5
101: /6
110: /7
111: /8
Reset type: XRSn
0 DIVSRCSEL R/W 0h 0: Auxillary PLL is the source for the etherCAT clock divider.
1: System PLL is the source for etherCAT clock divider.
Reset type: XRSn

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3.16.3.22 CMCLKCTL Register (Offset = 38h) [Reset = E6h]

CMCLKCTL is shown in Figure 3-60 and described in Table 3-60.
Return to the Summary Table.
CM Clock control register
This memory mapped register requires a delay of 69 SYSCLK cycles between subsequent writes to the register,
otherwise a second write can be lost. This delay can be realized by adding 69 NOP instructions.
Figure 3-60. CMCLKCTL Register
31 30 29 28 27 26 25 24
RESERVED
R-0h

23 22 21 20 19 18 17 16
RESERVED
R-0h

15 14 13 12 11 10 9 8
RESERVED
R-0h

7 6 5 4 3 2 1 0
ETHDIV ETHDIVSRCSE CMCLKDIV CMDIVSRCSEL
L
R/W-7h R/W-0h R/W-3h R/W-0h

Table 3-60. CMCLKCTL Register Field Descriptions

Bit Field Type Reset Description
31-8 RESERVED R 0h Reserved
7-5 ETHDIV R/W 7h 000: /1
001: /2
010: /3
011: /4
100: /5
101: /6
110: /7
111: /8
Reset type: XRSn
4 ETHDIVSRCSEL R/W 0h 0: Auxillary PLL is the source for the etherNET clock divider.
1: System PLL is the source for etherNET clock divider.
Reset type: XRSn
3-1 CMCLKDIV R/W 3h 000: /1
001: /2
010: /3
011: /4
100: /5
101: /6
110: /7
111: /8
Note: CMCLKDIV should be configured prior or along with
CMCLKDIV configuration. If CMCLKDIV is configured after
CMDIVSRCSEL in the next cycle, the writes to this field gets
ignored.
Reset type: XRSn
0 CMDIVSRCSEL R/W 0h 0: Auxillary PLL is the source for the CM clock divider.
1: System PLL is the source for CM clock divider.
Reset type: XRSn

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3.16.4 CM_CONF_REGS Registers

Table 3-61 lists the memory-mapped registers for the CM_CONF_REGS registers. All register offset addresses
not listed in Table 3-61 should be considered as reserved locations and the register contents should not be
modified.
Table 3-61. CM_CONF_REGS Registers
Offset Acronym Register Name Write Protection Section
0h CMRESCTL CM Reset Control Register EALLOW Go
2h CMTOCPU1NMICTL CM To CPU1 NMI Control register EALLOW Go
4h CMTOCPU1INTCTL CM To CPU1 interrupt Control register EALLOW Go
20h PALLOCATE0 CM Peripheral Allocation Register. EALLOW Go
3FEh CM_CONF_REGS_LOCK CM Configuration Registers Lock EALLOW Go

Complex bit access types are encoded to fit into small table cells. Table 3-62 shows the codes that are used for
access types in this section.
Table 3-62. CM_CONF_REGS Access Type Codes
Access Type Code Description
Read Type
R R Read
R-0 R Read
-0 Returns 0s
Write Type
W W Write
WSonce W Write
Sonce Set once
Reset or Default Value
-n Value after reset or the default
value
Register Array Variables
i,j,k,l,m,n When these variables are used in
a register name, an offset, or an
address, they refer to the value of
a register array where the register
is part of a group of repeating
registers. The register groups
form a hierarchical structure and
the array is represented with a
formula.
y When this variable is used in a
register name, an offset, or an
address it refers to the value of
a register array.

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3.16.4.1 CMRESCTL Register (Offset = 0h) [Reset = 1h]

CMRESCTL is shown in Figure 3-61 and described in Table 3-63.
Return to the Summary Table.
Software reset of CM.
Figure 3-61. CMRESCTL Register
31 30 29 28 27 26 25 24
KEY
R-0/W-0h

23 22 21 20 19 18 17 16
KEY
R-0/W-0h

15 14 13 12 11 10 9 8
RESERVED
R-0h

7 6 5 4 3 2 1 0
RESERVED RESETSTS RESET
R-0h R-0h R/W-1h

Table 3-63. CMRESCTL Register Field Descriptions

Bit Field Type Reset Description
31-16 KEY R-0/W 0h Write to this register succeeds only if this field is written with a value
of 0xa5a5
Note:
[1] Due to this KEY, only 32-bit writes will succeed (provided the KEY
matches). 16-bit writes to the upper or lower half of this register will
be ignored
Reset type: CPU1.SYSRSn
15-2 RESERVED R 0h Reserved
1 RESETSTS R 0h 0: CM is under reset
1: CM is out of reset.
Reset type: CPU1.SYSRSn
0 RESET R/W 1h 1: Asserts reset to CM.
0: De-asserts reset to CM.
Software Note: This bit should be kept high until RESETSTS bit of
CMRSTCTL register goes low.
Reset type: CPU1.SYSRSn

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3.16.4.2 CMTOCPU1NMICTL Register (Offset = 2h) [Reset = 0h]

CMTOCPU1NMICTL is shown in Figure 3-62 and described in Table 3-64.
Return to the Summary Table.
CM To CPU1 NMI Control register
Figure 3-62. CMTOCPU1NMICTL Register
31 30 29 28 27 26 25 24
RESERVED
R-0h

23 22 21 20 19 18 17 16
RESERVED
R-0h

15 14 13 12 11 10 9 8
RESERVED
R-0h

7 6 5 4 3 2 1 0
RESERVED CMNMIWDRST RESERVED RESERVED
R-0h R/W-0h R/W-0h R/W-0h

Table 3-64. CMTOCPU1NMICTL Register Field Descriptions

Bit Field Type Reset Description
31-3 RESERVED R 0h Reserved
2 CMNMIWDRST R/W 0h 0: NMI to CPU1 is not fired on a CMNMIWDRST to CM4.
1: NMI to CPU1 is fired on a CMNMIWDRST to CM4.
Reset type: XRSn
1 RESERVED R/W 0h Reserved
0 RESERVED R/W 0h Reserved

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3.16.4.3 CMTOCPU1INTCTL Register (Offset = 4h) [Reset = 0h]

CMTOCPU1INTCTL is shown in Figure 3-63 and described in Table 3-65.
Return to the Summary Table.
CM To CPU1 interrupt Control register
Figure 3-63. CMTOCPU1INTCTL Register
31 30 29 28 27 26 25 24
RESERVED
R-0h

23 22 21 20 19 18 17 16
RESERVED
R-0h

15 14 13 12 11 10 9 8
RESERVED
R-0h

7 6 5 4 3 2 1 0
RESERVED CMNMIWDRST SYSRESETRE VECTRESET
Q
R-0h R/W-0h R/W-0h R/W-0h

Table 3-65. CMTOCPU1INTCTL Register Field Descriptions

Bit Field Type Reset Description
31-3 RESERVED R 0h Reserved
2 CMNMIWDRST R/W 0h 0: Interrupt to CPU1 is not fired on a CMNMIWDRST to CM4.
1: Interrupt to CPU1 is fired on a CMNMIWDRST to CM4.
Reset type: XRSn
1 SYSRESETREQ R/W 0h 0: Interrupt to CPU1 is not fired on a SYSRESETREQ to CM4.
1: Interrupt to CPU1 is fired on a SYSRESETREQ to CM4.
Reset type: XRSn
0 VECTRESET R/W 0h 0: Interrupt to CPU1 is not fired on a VECTRESET to CM4.
1: Interrupt to CPU1 is fired on a VECTRESET to CM4.
Reset type: XRSn

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3.16.4.4 PALLOCATE0 Register (Offset = 20h) [Reset = 10h]

PALLOCATE0 is shown in Figure 3-64 and described in Table 3-66.
Return to the Summary Table.
CM Peripheral Allocation Register for shared peripherals.
This register must be configured prior to enabling the peripheral clocks.
The clock for each peripheral is derived from the selected CPU subsystem. The clock mux controlled by this
register is not glitch-free, therefore the PALLOCATEx register must be configured before the PCLKCRx register.
Figure 3-64. PALLOCATE0 Register
31 30 29 28 27 26 25 24
RESERVED
R-0h

23 22 21 20 19 18 17 16
RESERVED
R-0h

15 14 13 12 11 10 9 8
RESERVED
R-0h

7 6 5 4 3 2 1 0
RESERVED MCAN_A CAN_B CAN_A ETHERCAT USB_A
R-0h R/W-1h R/W-0h R/W-0h R/W-0h R/W-0h

Table 3-66. PALLOCATE0 Register Field Descriptions

Bit Field Type Reset Description
31-5 RESERVED R 0h Reserved
4 MCAN_A R/W 1h 0: MCAN_A is allocated to C28x CPU1, CM accesses to MCAN_A
will be ignored and interrupts from MCAN_A will not be generated to
CM.
1: MCAN_A is allocated to CM, C28x CPU1 accesses to MCAN_A
will be ignored and interrupts from MCAN_A will not be generated to
C28x CPU1.
Note:CPU2 does not have access to MCAN_A.
Reset type: XRSn
3 CAN_B R/W 0h 0: CAN_B is allocated to C28x CPU1 or CPU2 (Mapping to CPU1 or
CPU2 is determined by CPUSELx.CAN_B bit setting), CM accesses
to CAN_B will be ignored and interrupts from CAN_B will not be
generated to CM.
1: CAN_B is allocated to CM, C28x CPU1/2 accesses to CAN_B will
be ignored and interrupts from CAN_B will not be generated to C28x
CPU1/2.
Reset type: XRSn
2 CAN_A R/W 0h 0: CAN_A is allocated to C28x CPU1 or CPU2 (Mapping to CPU1 or
CPU2 is determined by CPUSELx.CAN_A bit setting), CM accesses
to CAN_A will be ignored and interrupts from CAN_A will not be
generated to CM.
1: CAN_A is allocated to CM, C28x CPU1/2 accesses to CAN_A will
be ignored and interrupts from CAN_A will not be generated to C28x
CPU1/2.
Reset type: XRSn

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Table 3-66. PALLOCATE0 Register Field Descriptions (continued)

Bit Field Type Reset Description
1 ETHERCAT R/W 0h 0: ETHERCAT is allocated to C28x CPU1, CM accesses to
ETHERCAT will be ignored and interrupts from ETHERCAT will not
be generated to CM.
1: ETHERCAT is allocated to CM, C28x CPU1 accesses to
ETHERCAT will be ignored and interrupts from ETHERCAT will not
be generated to C28x CPU1.
Note:CPU2 does not have access to ETHERCAT.
Reset type: XRSn
0 USB_A R/W 0h 0: USB_A is allocated to C28x CPU1, CM accesses to USB_A will
be ignored and interrupts from USB_A will not be generated to CM.
1: USB_A is allocated to CM, C28x CPU1 accesses to USB_A will
be ignored and interrupts from USB_A will not be generated to C28x
CPU1.
Note:CPU2 does not have access to USB_A.
Reset type: XRSn

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3.16.4.5 CM_CONF_REGS_LOCK Register (Offset = 3FEh) [Reset = 0h]

CM_CONF_REGS_LOCK is shown in Figure 3-65 and described in Table 3-67.
Return to the Summary Table.
CM Configuration Registers Lock
Figure 3-65. CM_CONF_REGS_LOCK Register
31 30 29 28 27 26 25 24
RESERVED
R-0h

23 22 21 20 19 18 17 16
RESERVED
R-0h

15 14 13 12 11 10 9 8
RESERVED
R-0h

7 6 5 4 3 2 1 0
RESERVED LOCK
R-0h R/WSonce-0h

Table 3-67. CM_CONF_REGS_LOCK Register Field Descriptions

Bit Field Type Reset Description
31-1 RESERVED R 0h Reserved
0 LOCK R/WSonce 0h 0: Allows write to the following registers
1: Writes to following registers are ignored.
1. PALLOCATE0
2. RAMALLOCATE
3. CMTOCPU1NMICTL
4. CMTOCPU1INTCTL
Reset type: XRSn

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3.16.5 CPU_SYS_REGS Registers

Table 3-68 lists the memory-mapped registers for the CPU_SYS_REGS registers. All register offset addresses
not listed in Table 3-68 should be considered as reserved locations and the register contents should not be
modified.
Table 3-68. CPU_SYS_REGS Registers
Offset Acronym Register Name Write Protection Section
0h CPUSYSLOCK1 Lock bit for CPUSYS registers EALLOW Go
2h CPUSYSLOCK2 Lock bit for CPUSYS registers EALLOW Go
Ah PIEVERRADDR PIE Vector Fetch Error Address register EALLOW Go
22h PCLKCR0 Peripheral Clock Gating Registers EALLOW Go
24h PCLKCR1 Peripheral Clock Gating Registers EALLOW Go
26h PCLKCR2 Peripheral Clock Gating Registers EALLOW Go
28h PCLKCR3 Peripheral Clock Gating Registers EALLOW Go
2Ah PCLKCR4 Peripheral Clock Gating Registers EALLOW Go
2Eh PCLKCR6 Peripheral Clock Gating Registers EALLOW Go
30h PCLKCR7 Peripheral Clock Gating Registers EALLOW Go
32h PCLKCR8 Peripheral Clock Gating Registers EALLOW Go
34h PCLKCR9 Peripheral Clock Gating Registers EALLOW Go
36h PCLKCR10 Peripheral Clock Gating Registers EALLOW Go
38h PCLKCR11 Peripheral Clock Gating Registers EALLOW Go
3Ch PCLKCR13 Peripheral Clock Gating Registers EALLOW Go
3Eh PCLKCR14 Peripheral Clock Gating Registers EALLOW Go
42h PCLKCR16 Peripheral Clock Gating Registers EALLOW Go
44h PCLKCR17 Peripheral Clock Gating Registers EALLOW Go
46h PCLKCR18 Peripheral Clock Gating Registers EALLOW Go
4Ah PCLKCR20 Peripheral Clock Gating Registers EALLOW Go
4Ch PCLKCR21 Peripheral Clock Gating Registers EALLOW Go
4Eh PCLKCR22 Peripheral Clock Gating Registers EALLOW Go
50h PCLKCR23 Peripheral Clock Gating Registers EALLOW Go
70h SIMRESET Simulated Reset Register Go
76h LPMCR LPM Control Register EALLOW Go
78h GPIOLPMSEL0 GPIO LPM Wakeup select registers EALLOW Go
7Ah GPIOLPMSEL1 GPIO LPM Wakeup select registers EALLOW Go
7Ch TMR2CLKCTL Timer2 Clock Measurement functionality control EALLOW Go
register
7Eh RESCCLR Reset Cause Clear Register Go
80h RESC Reset Cause register Go
98h MCANWAKESTATUS MCAN Wake Status Register Go
9Ah MCANWAKESTATUSCLR MCAN Wake Status Clear Register Go

Complex bit access types are encoded to fit into small table cells. Table 3-69 shows the codes that are used for
access types in this section.
Table 3-69. CPU_SYS_REGS Access Type Codes
Access Type Code Description
Read Type
R R Read

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Table 3-69. CPU_SYS_REGS Access Type Codes

(continued)
Access Type Code Description
R-0 R Read
-0 Returns 0s
Write Type
W W Write
W1C W Write
1C 1 to clear
W1S W Write
1S 1 to set
WSonce W Write
Sonce Set once
Reset or Default Value
-n Value after reset or the default
value
Register Array Variables
i,j,k,l,m,n When these variables are used in
a register name, an offset, or an
address, they refer to the value of
a register array where the register
is part of a group of repeating
registers. The register groups
form a hierarchical structure and
the array is represented with a
formula.
y When this variable is used in a
register name, an offset, or an
address it refers to the value of
a register array.

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3.16.5.1 CPUSYSLOCK1 Register (Offset = 0h) [Reset = 0h]

CPUSYSLOCK1 is shown in Figure 3-66 and described in Table 3-70.
Return to the Summary Table.
Lock bit for CPUSYS registers
Notes:
[1] Any bit in this register, once set can only be cleared through a CPU1.SYSRSn. Write of 0 to any bit of this
register has no effect
[2] The locking mechanism applies to only writes. Reads to the registers which have LOCK protection are always
allowed
Figure 3-66. CPUSYSLOCK1 Register
31 30 29 28 27 26 25 24
RESERVED PCLKCR23 PCLKCR22 PCLKCR21 PCLKCR20 RESERVED PCLKCR18 PCLKCR17
R/WSonce-0h R/WSonce-0h R/WSonce-0h R/WSonce-0h R/WSonce-0h R/WSonce-0h R/WSonce-0h R/WSonce-0h

23 22 21 20 19 18 17 16
GPIOLPMSEL1 GPIOLPMSEL0 LPMCR RESERVED PCLKCR16 RESERVED PCLKCR14 PCLKCR13
R/WSonce-0h R/WSonce-0h R/WSonce-0h R/WSonce-0h R/WSonce-0h R/WSonce-0h R/WSonce-0h R/WSonce-0h

15 14 13 12 11 10 9 8
RESERVED PCLKCR11 PCLKCR10 PCLKCR9 PCLKCR8 PCLKCR7 PCLKCR6 RESERVED
R/WSonce-0h R/WSonce-0h R/WSonce-0h R/WSonce-0h R/WSonce-0h R/WSonce-0h R/WSonce-0h R/WSonce-0h

7 6 5 4 3 2 1 0
PCLKCR4 PCLKCR3 PCLKCR2 PCLKCR1 PCLKCR0 PIEVERRADDR RESERVED RESERVED
R/WSonce-0h R/WSonce-0h R/WSonce-0h R/WSonce-0h R/WSonce-0h R/WSonce-0h R/WSonce-0h R/WSonce-0h

Table 3-70. CPUSYSLOCK1 Register Field Descriptions

Bit Field Type Reset Description
31 RESERVED R/WSonce 0h Reserved
30 PCLKCR23 R/WSonce 0h Lock bit for PCLKCR23 Register
0: Respective register is not locked
1: Respective register is locked.
Note: This bit will be reserved for CPU2.
Reset type: SYSRSn
29 PCLKCR22 R/WSonce 0h Lock bit for PCLKCR22 Register
0: Respective register is not locked
1: Respective register is locked.
Reset type: SYSRSn
28 PCLKCR21 R/WSonce 0h Lock bit for PCLKCR21 Register
0: Respective register is not locked
1: Respective register is locked.
Reset type: SYSRSn
27 PCLKCR20 R/WSonce 0h Lock bit for PCLKCR20 Register
0: Respective register is not locked
1: Respective register is locked.
Reset type: SYSRSn
26 RESERVED R/WSonce 0h Reserved
25 PCLKCR18 R/WSonce 0h Lock bit for PCLKCR18 Register
0: Respective register is not locked
1: Respective register is locked.
Reset type: SYSRSn
24 PCLKCR17 R/WSonce 0h Lock bit for PCLKCR17 Register
0: Respective register is not locked
1: Respective register is locked.
Reset type: SYSRSn

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Table 3-70. CPUSYSLOCK1 Register Field Descriptions (continued)

Bit Field Type Reset Description
23 GPIOLPMSEL1 R/WSonce 0h Lock bit for GPIOLPMSEL1 Register:
0: Respective register is not locked
1: Respective register is locked.
Reset type: SYSRSn
22 GPIOLPMSEL0 R/WSonce 0h Lock bit for GPIOLPMSEL0 Register:
0: Respective register is not locked
1: Respective register is locked.
Reset type: SYSRSn
21 LPMCR R/WSonce 0h Lock bit for LPMCR Register:
0: Respective register is not locked
1: Respective register is locked.
Reset type: SYSRSn
20 RESERVED R/WSonce 0h Reserved
19 PCLKCR16 R/WSonce 0h Lock bit for PCLKCR16 Register:
0: Respective register is not locked
1: Respective register is locked.
Reset type: SYSRSn
18 RESERVED R/WSonce 0h Reserved
17 PCLKCR14 R/WSonce 0h Lock bit for PCLKCR14 Register:
0: Respective register is not locked
1: Respective register is locked.
Reset type: SYSRSn
16 PCLKCR13 R/WSonce 0h Lock bit for PCLKCR13 Register:
0: Respective register is not locked
1: Respective register is locked.
Reset type: SYSRSn
15 RESERVED R/WSonce 0h Reserved
14 PCLKCR11 R/WSonce 0h Lock bit for PCLKCR11 Register:
0: Respective register is not locked
1: Respective register is locked.
Reset type: SYSRSn
13 PCLKCR10 R/WSonce 0h Lock bit for PCLKCR10 Register:
0: Respective register is not locked
1: Respective register is locked.
Reset type: SYSRSn
12 PCLKCR9 R/WSonce 0h Lock bit for PCLKCR9 Register:
0: Respective register is not locked
1: Respective register is locked.
Reset type: SYSRSn
11 PCLKCR8 R/WSonce 0h Lock bit for PCLKCR8 Register:
0: Respective register is not locked
1: Respective register is locked.
Reset type: SYSRSn
10 PCLKCR7 R/WSonce 0h Lock bit for PCLKCR7 Register:
0: Respective register is not locked
1: Respective register is locked.
Reset type: SYSRSn
9 PCLKCR6 R/WSonce 0h Lock bit for PCLKCR6 Register:
0: Respective register is not locked
1: Respective register is locked.
Reset type: SYSRSn
8 RESERVED R/WSonce 0h Reserved
7 PCLKCR4 R/WSonce 0h Lock bit for PCLKCR4 Register:
0: Respective register is not locked
1: Respective register is locked.
Reset type: SYSRSn

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Table 3-70. CPUSYSLOCK1 Register Field Descriptions (continued)

Bit Field Type Reset Description
6 PCLKCR3 R/WSonce 0h Lock bit for PCLKCR3 Register:
0: Respective register is not locked
1: Respective register is locked.
Reset type: SYSRSn
5 PCLKCR2 R/WSonce 0h Lock bit for PCLKCR2 Register:
0: Respective register is not locked
1: Respective register is locked.
Reset type: SYSRSn
4 PCLKCR1 R/WSonce 0h Lock bit for PCLKCR1 Register:
0: Respective register is not locked
1: Respective register is locked.
Reset type: SYSRSn
3 PCLKCR0 R/WSonce 0h Lock bit for PCLKCR0 Register:
0: Respective register is not locked
1: Respective register is locked.
Reset type: SYSRSn
2 PIEVERRADDR R/WSonce 0h Lock bit for PIEVERRADDR Register:
0: Respective register is not locked
1: Respective register is locked.
Reset type: SYSRSn
1 RESERVED R/WSonce 0h Reserved
0 RESERVED R/WSonce 0h Reserved

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3.16.5.2 CPUSYSLOCK2 Register (Offset = 2h) [Reset = 0h]

CPUSYSLOCK2 is shown in Figure 3-67 and described in Table 3-71.
Return to the Summary Table.
Lock bit for CPUSYS registers
Notes:
[1] Any bit in this register, once set can only be cleared through a CPU1.SYSRSn. Write of 0 to any bit of this
register has no effect
[2] The locking mechanism applies to only writes. Reads to the registers which have LOCK protection are always
allowed
Figure 3-67. CPUSYSLOCK2 Register
31 30 29 28 27 26 25 24
RESERVED
R-0h

23 22 21 20 19 18 17 16
RESERVED
R-0h

15 14 13 12 11 10 9 8
RESERVED
R-0h

7 6 5 4 3 2 1 0
RESERVED ETHERCATCTL
R-0h R/WSonce-0h

Table 3-71. CPUSYSLOCK2 Register Field Descriptions

Bit Field Type Reset Description
31-1 RESERVED R 0h Reserved
0 ETHERCATCTL R/WSonce 0h Lock bit for ETHERCATCTL register:
0: Respective register is not locked
1: Respective register is locked.
Notes:
1 Any bit in this register, once set can only be cleared through a
CPU1.SYSRSn. Write of 0 to any bit of this register has no effect
2 The locking mechanism applies to only writes. Reads to the
registers which have LOCK protection are always allowed
3 This bit is reserved for CPU2
Reset type: SYSRSn

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3.16.5.3 PIEVERRADDR Register (Offset = Ah) [Reset = 003FFFFFh]

PIEVERRADDR is shown in Figure 3-68 and described in Table 3-72.
Return to the Summary Table.
PIE Vector Fetch Error Address register
Figure 3-68. PIEVERRADDR Register
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RESERVED ADDR
R-0-0h R/W-003FFFFFh

Table 3-72. PIEVERRADDR Register Field Descriptions

Bit Field Type Reset Description
31-22 RESERVED R-0 0h Reserved
21-0 ADDR R/W 003FFFFFh This register defines the address of the PIE Vector Fetch Error
handler routine. Its the responsibility of user to initialize this register.
If this register is not initialized, a default error handler at address
0x3fffbe will get executed.
Reset type: XRSn

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3.16.5.4 PCLKCR0 Register (Offset = 22h) [Reset = 38h]

PCLKCR0 is shown in Figure 3-69 and described in Table 3-73.
Return to the Summary Table.
Peripheral Clock Gating Registers
Note: All the clock inputs of the specific IP may be gated using bits of PCLKCR registers.
Figure 3-69. PCLKCR0 Register
31 30 29 28 27 26 25 24
RESERVED ERAD
R-0-0h R/W-0h

23 22 21 20 19 18 17 16
RESERVED GTBCLKSYNC TBCLKSYNC RESERVED HRCAL
R-0-0h R/W-0h R/W-0h R-0-0h R/W-0h

15 14 13 12 11 10 9 8
RESERVED CLA1BGCRC CPUBGCRC RESERVED
R/W-0h R/W-0h R/W-0h R-0-0h

7 6 5 4 3 2 1 0
RESERVED CPUTIMER2 CPUTIMER1 CPUTIMER0 DMA RESERVED CLA1
R-0-0h R/W-1h R/W-1h R/W-1h R/W-0h R/W-0h R/W-0h

Table 3-73. PCLKCR0 Register Field Descriptions

Bit Field Type Reset Description
31-25 RESERVED R-0 0h Reserved
24 ERAD R/W 0h ERAD Clock Enable Bit: When set, this enables the clock to the
HRPWM module
1: ERAD clock is enabled
0: ERAD clock is disabled
Reset type: SYSRSn
23-20 RESERVED R-0 0h Reserved
19 GTBCLKSYNC R/W 0h EPWM Time Base Clock Global sync: When set by CPU1, PWM
time bases of all modules start counting. The effect of this bit is seen
on all the EPMW modules irrespective of their partitioning based on
CPUSEL
Notes:
1. This bit on the CPU2.PCLKCR0 register has no effect.
2. Writing '1' to this bit overrides the effect of write '1' to the
TBCLKSYNC bit at the same time
Reset type: SYSRSn
18 TBCLKSYNC R/W 0h EPWM Time Base Clock sync: When set PWM time bases of
all the PWM modules belonging to the same CPU-Subsystem (as
partitioned using their CPUSEL bits) start counting
Notes:
1. This bit from CPU1.PCLKCR0 or CPU2.PCLKCR0 is selected
and fed to the individual EPWM modules based on their respective
CPUSEL bit.
Reset type: SYSRSn
17 RESERVED R-0 0h Reserved
16 HRCAL R/W 0h HRCAL Clock Enable Bit: When set, this enables the clock to the
HRPWM module
1: HRCALclock is enabled
0: HRCAL clock is disabled
Reset type: SYSRSn
15 RESERVED R/W 0h Reserved

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Table 3-73. PCLKCR0 Register Field Descriptions (continued)

Bit Field Type Reset Description
14 CLA1BGCRC R/W 0h CLA1BGCRC Clock Enable Bit:
0: Module clock is gated-off
1: Module clock is turned-on
Reset type: SYSRSn
13 CPUBGCRC R/W 0h CPUBGCRC Clock Enable Bit:
0: Module clock is gated-off
1: Module clock is turned-on
Reset type: SYSRSn
12-6 RESERVED R-0 0h Reserved
5 CPUTIMER2 R/W 1h CPUTIMER2 Clock Enable bit:
0: Module clock is gated-off
1: Module clock is turned-on
Reset type: SYSRSn
4 CPUTIMER1 R/W 1h CPUTIMER1 Clock Enable bit:
0: Module clock is gated-off
1: Module clock is turned-on
Reset type: SYSRSn
3 CPUTIMER0 R/W 1h CPUTIMER0 Clock Enable bit:
0: Module clock is gated-off
1: Module clock is turned-on
Reset type: SYSRSn
2 DMA R/W 0h DMA Clock Enable bit:
0: Module clock is gated-off
1: Module clock is turned-on
Reset type: SYSRSn
1 RESERVED R/W 0h Reserved
0 CLA1 R/W 0h CLA1 Clock Enable Bit:
0: Module clock is gated-off
1: Module clock is turned-on
Reset type: SYSRSn

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3.16.5.5 PCLKCR1 Register (Offset = 24h) [Reset = 0h]

PCLKCR1 is shown in Figure 3-70 and described in Table 3-74.
Return to the Summary Table.
Peripheral Clock Gating Registers
Note: All the clock inputs of the specific IP may be gated using bits of PCLKCR registers.
Figure 3-70. PCLKCR1 Register
31 30 29 28 27 26 25 24
RESERVED
R-0-0h

23 22 21 20 19 18 17 16
RESERVED
R-0-0h

15 14 13 12 11 10 9 8
RESERVED
R-0-0h

7 6 5 4 3 2 1 0
RESERVED EMIF2 EMIF1
R-0-0h R/W-0h R/W-0h

Table 3-74. PCLKCR1 Register Field Descriptions

Bit Field Type Reset Description
31-16 RESERVED R-0 0h Reserved
15-2 RESERVED R-0 0h Reserved
1 EMIF2 R/W 0h EMIF2 Clock Enable bit:
0: Module clock is gated-off
1: Module clock is turned-on
Notes:
[1] These bits are not used (R/W) in CPU2.PCLKCR1 register.
EMIF1 & EMIF2 clock enabled are controlled only from
CPU1.PCLKCR1 register.
Reset type: SYSRSn
0 EMIF1 R/W 0h EMIF1 Clock Enable bit:
0: Module clock is gated-off
1: Module clock is turned-on
Notes:
[1] These bits are not used (R/W) in CPU2.PCLKCR1 register.
EMIF1 & EMIF2 clock enabled are controlled only from
CPU1.PCLKCR1 register.
Reset type: SYSRSn

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3.16.5.6 PCLKCR2 Register (Offset = 26h) [Reset = 0h]

PCLKCR2 is shown in Figure 3-71 and described in Table 3-75.
Return to the Summary Table.
Peripheral Clock Gating Registers
Note: All the clock inputs of the specific IP may be gated using bits of PCLKCR registers.
Figure 3-71. PCLKCR2 Register
31 30 29 28 27 26 25 24
RESERVED
R-0-0h

23 22 21 20 19 18 17 16
RESERVED
R-0-0h

15 14 13 12 11 10 9 8
EPWM16 EPWM15 EPWM14 EPWM13 EPWM12 EPWM11 EPWM10 EPWM9
R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h

7 6 5 4 3 2 1 0
EPWM8 EPWM7 EPWM6 EPWM5 EPWM4 EPWM3 EPWM2 EPWM1
R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h

Table 3-75. PCLKCR2 Register Field Descriptions

Bit Field Type Reset Description
31-16 RESERVED R-0 0h Reserved
15 EPWM16 R/W 0h EPWM16 Clock Enable bit:
0: Module clock is gated-off
1: Module clock is turned-on
Reset type: SYSRSn
14 EPWM15 R/W 0h EPWM15 Clock Enable bit:
0: Module clock is gated-off
1: Module clock is turned-on
Reset type: SYSRSn
13 EPWM14 R/W 0h EPWM14 Clock Enable bit:
0: Module clock is gated-off
1: Module clock is turned-on
Reset type: SYSRSn
12 EPWM13 R/W 0h EPWM13 Clock Enable bit:
0: Module clock is gated-off
1: Module clock is turned-on
Reset type: SYSRSn
11 EPWM12 R/W 0h EPWM12 Clock Enable bit:
0: Module clock is gated-off
1: Module clock is turned-on
Reset type: SYSRSn
10 EPWM11 R/W 0h EPWM11 Clock Enable bit:
0: Module clock is gated-off
1: Module clock is turned-on
Reset type: SYSRSn
9 EPWM10 R/W 0h EPWM10 Clock Enable bit:
0: Module clock is gated-off
1: Module clock is turned-on
Reset type: SYSRSn

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Table 3-75. PCLKCR2 Register Field Descriptions (continued)

Bit Field Type Reset Description
8 EPWM9 R/W 0h EPWM9 Clock Enable bit:
0: Module clock is gated-off
1: Module clock is turned-on
Reset type: SYSRSn
7 EPWM8 R/W 0h EPWM8 Clock Enable bit:
0: Module clock is gated-off
1: Module clock is turned-on
Reset type: SYSRSn
6 EPWM7 R/W 0h EPWM7 Clock Enable bit:
0: Module clock is gated-off
1: Module clock is turned-on
Reset type: SYSRSn
5 EPWM6 R/W 0h EPWM6 Clock Enable bit:
0: Module clock is gated-off
1: Module clock is turned-on
Reset type: SYSRSn
4 EPWM5 R/W 0h EPWM5 Clock Enable bit:
0: Module clock is gated-off
1: Module clock is turned-on
Reset type: SYSRSn
3 EPWM4 R/W 0h EPWM4 Clock Enable bit:
0: Module clock is gated-off
1: Module clock is turned-on
Reset type: SYSRSn
2 EPWM3 R/W 0h EPWM3 Clock Enable bit:
0: Module clock is gated-off
1: Module clock is turned-on
Reset type: SYSRSn
1 EPWM2 R/W 0h EPWM2 Clock Enable bit:
0: Module clock is gated-off
1: Module clock is turned-on
Reset type: SYSRSn
0 EPWM1 R/W 0h EPWM1 Clock Enable bit:
0: Module clock is gated-off
1: Module clock is turned-on
Reset type: SYSRSn

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3.16.5.7 PCLKCR3 Register (Offset = 28h) [Reset = 0h]

PCLKCR3 is shown in Figure 3-72 and described in Table 3-76.
Return to the Summary Table.
Peripheral Clock Gating Registers
Note: All the clock inputs of the specific IP may be gated using bits of PCLKCR registers.
Figure 3-72. PCLKCR3 Register
31 30 29 28 27 26 25 24
RESERVED
R-0-0h

23 22 21 20 19 18 17 16
RESERVED
R-0-0h

15 14 13 12 11 10 9 8
RESERVED
R-0-0h

7 6 5 4 3 2 1 0
RESERVED ECAP7 ECAP6 ECAP5 ECAP4 ECAP3 ECAP2 ECAP1
R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h

Table 3-76. PCLKCR3 Register Field Descriptions

Bit Field Type Reset Description
31-16 RESERVED R-0 0h Reserved
15-8 RESERVED R-0 0h Reserved
7 RESERVED R/W 0h Reserved
6 ECAP7 R/W 0h ECAP7 Clock Enable bit:
0: Module clock is gated-off
1: Module clock is turned-on
Reset type: SYSRSn
5 ECAP6 R/W 0h ECAP6 Clock Enable bit:
0: Module clock is gated-off
1: Module clock is turned-on
Reset type: SYSRSn
4 ECAP5 R/W 0h ECAP5 Clock Enable bit:
0: Module clock is gated-off
1: Module clock is turned-on
Reset type: SYSRSn
3 ECAP4 R/W 0h ECAP4 Clock Enable bit:
0: Module clock is gated-off
1: Module clock is turned-on
Reset type: SYSRSn
2 ECAP3 R/W 0h ECAP3 Clock Enable bit:
0: Module clock is gated-off
1: Module clock is turned-on
Reset type: SYSRSn
1 ECAP2 R/W 0h ECAP2 Clock Enable bit:
0: Module clock is gated-off
1: Module clock is turned-on
Reset type: SYSRSn

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Table 3-76. PCLKCR3 Register Field Descriptions (continued)

Bit Field Type Reset Description
0 ECAP1 R/W 0h ECAP1 Clock Enable bit:
0: Module clock is gated-off
1: Module clock is turned-on
Reset type: SYSRSn

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3.16.5.8 PCLKCR4 Register (Offset = 2Ah) [Reset = 0h]

PCLKCR4 is shown in Figure 3-73 and described in Table 3-77.
Return to the Summary Table.
Peripheral Clock Gating Registers
Note: All the clock inputs of the specific IP may be gated using bits of PCLKCR registers.
Figure 3-73. PCLKCR4 Register
31 30 29 28 27 26 25 24
RESERVED
R-0-0h

23 22 21 20 19 18 17 16
RESERVED
R-0-0h

15 14 13 12 11 10 9 8
RESERVED
R-0-0h

7 6 5 4 3 2 1 0
RESERVED RESERVED EQEP3 EQEP2 EQEP1
R-0-0h R/W-0h R/W-0h R/W-0h R/W-0h

Table 3-77. PCLKCR4 Register Field Descriptions

Bit Field Type Reset Description
31-16 RESERVED R-0 0h Reserved
15-4 RESERVED R-0 0h Reserved
3 RESERVED R/W 0h Reserved
2 EQEP3 R/W 0h EQEP3 Clock Enable bit:
0: Module clock is gated-off
1: Module clock is turned-on
Reset type: SYSRSn
1 EQEP2 R/W 0h EQEP2 Clock Enable bit:
0: Module clock is gated-off
1: Module clock is turned-on
Reset type: SYSRSn
0 EQEP1 R/W 0h EQEP1 Clock Enable bit:
0: Module clock is gated-off
1: Module clock is turned-on
Reset type: SYSRSn

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3.16.5.9 PCLKCR6 Register (Offset = 2Eh) [Reset = 0h]

PCLKCR6 is shown in Figure 3-74 and described in Table 3-78.
Return to the Summary Table.
Peripheral Clock Gating Registers
Note: All the clock inputs of the specific IP may be gated using bits of PCLKCR registers.
Figure 3-74. PCLKCR6 Register
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
RESERVED
R-0-0h

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RESERVED RESE RESE RESE RESE RESE RESE SD2 SD1
RVED RVED RVED RVED RVED RVED
R-0-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h

Table 3-78. PCLKCR6 Register Field Descriptions

Bit Field Type Reset Description
31-16 RESERVED R-0 0h Reserved
15-8 RESERVED R-0 0h Reserved
7 RESERVED R/W 0h Reserved
6 RESERVED R/W 0h Reserved
5 RESERVED R/W 0h Reserved
4 RESERVED R/W 0h Reserved
3 RESERVED R/W 0h Reserved
2 RESERVED R/W 0h Reserved
1 SD2 R/W 0h SD2 Clock Enable bit:
0: Module clock is gated-off
1: Module clock is turned-on
Reset type: SYSRSn
0 SD1 R/W 0h SD1 Clock Enable bit:
0: Module clock is gated-off
1: Module clock is turned-on
Reset type: SYSRSn

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3.16.5.10 PCLKCR7 Register (Offset = 30h) [Reset = 0h]

PCLKCR7 is shown in Figure 3-75 and described in Table 3-79.
Return to the Summary Table.
Peripheral Clock Gating Registers
Note: All the clock inputs of the specific IP may be gated using bits of PCLKCR registers.
Figure 3-75. PCLKCR7 Register
31 30 29 28 27 26 25 24
RESERVED
R-0-0h

23 22 21 20 19 18 17 16
RESERVED
R-0-0h

15 14 13 12 11 10 9 8
RESERVED
R-0-0h

7 6 5 4 3 2 1 0
RESERVED SCI_D SCI_C SCI_B SCI_A
R-0-0h R/W-0h R/W-0h R/W-0h R/W-0h

Table 3-79. PCLKCR7 Register Field Descriptions

Bit Field Type Reset Description
31-16 RESERVED R-0 0h Reserved
15-4 RESERVED R-0 0h Reserved
3 SCI_D R/W 0h SCI_D Clock Enable bit:
0: Module clock is gated-off
1: Module clock is turned-on
Reset type: SYSRSn
2 SCI_C R/W 0h SCI_C Clock Enable bit:
0: Module clock is gated-off
1: Module clock is turned-on
Reset type: SYSRSn
1 SCI_B R/W 0h SCI_B Clock Enable bit:
0: Module clock is gated-off
1: Module clock is turned-on
Reset type: SYSRSn
0 SCI_A R/W 0h SCI_A Clock Enable bit:
0: Module clock is gated-off
1: Module clock is turned-on
Reset type: SYSRSn

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3.16.5.11 PCLKCR8 Register (Offset = 32h) [Reset = 0h]

PCLKCR8 is shown in Figure 3-76 and described in Table 3-80.
Return to the Summary Table.
Peripheral Clock Gating Registers
Note: All the clock inputs of the specific IP may be gated using bits of PCLKCR registers.
Figure 3-76. PCLKCR8 Register
31 30 29 28 27 26 25 24
RESERVED
R-0-0h

23 22 21 20 19 18 17 16
RESERVED RESERVED RESERVED
R-0-0h R/W-0h R/W-0h

15 14 13 12 11 10 9 8
RESERVED
R-0-0h

7 6 5 4 3 2 1 0
RESERVED SPI_D SPI_C SPI_B SPI_A
R-0-0h R/W-0h R/W-0h R/W-0h R/W-0h

Table 3-80. PCLKCR8 Register Field Descriptions

Bit Field Type Reset Description
31-18 RESERVED R-0 0h Reserved
17 RESERVED R/W 0h Reserved
16 RESERVED R/W 0h Reserved
15-4 RESERVED R-0 0h Reserved
3 SPI_D R/W 0h SPI_D Clock Enable bit:
0: Module clock is gated-off
1: Module clock is turned-on
Reset type: SYSRSn
2 SPI_C R/W 0h SPI_C Clock Enable bit:
0: Module clock is gated-off
1: Module clock is turned-on
Reset type: SYSRSn
1 SPI_B R/W 0h SPI_B Clock Enable bit:
0: Module clock is gated-off
1: Module clock is turned-on
Reset type: SYSRSn
0 SPI_A R/W 0h SPI_A Clock Enable bit:
0: Module clock is gated-off
1: Module clock is turned-on
Reset type: SYSRSn

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3.16.5.12 PCLKCR9 Register (Offset = 34h) [Reset = 0h]

PCLKCR9 is shown in Figure 3-77 and described in Table 3-81.
Return to the Summary Table.
Peripheral Clock Gating Registers
Note: All the clock inputs of the specific IP may be gated using bits of PCLKCR registers.
Figure 3-77. PCLKCR9 Register
31 30 29 28 27 26 25 24
RESERVED
R-0-0h

23 22 21 20 19 18 17 16
RESERVED
R-0-0h

15 14 13 12 11 10 9 8
RESERVED
R-0-0h

7 6 5 4 3 2 1 0
RESERVED I2C_B I2C_A
R-0-0h R/W-0h R/W-0h

Table 3-81. PCLKCR9 Register Field Descriptions

Bit Field Type Reset Description
31-16 RESERVED R-0 0h Reserved
15-2 RESERVED R-0 0h Reserved
1 I2C_B R/W 0h I2C_B Clock Enable bit:
0: Module clock is gated-off
1: Module clock is turned-on
Reset type: SYSRSn
0 I2C_A R/W 0h I2C_A Clock Enable bit:
0: Module clock is gated-off
1: Module clock is turned-on
Reset type: SYSRSn

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3.16.5.13 PCLKCR10 Register (Offset = 36h) [Reset = 0h]

PCLKCR10 is shown in Figure 3-78 and described in Table 3-82.
Return to the Summary Table.
Peripheral Clock Gating Registers
Note: All the clock inputs of the specific IP may be gated using bits of PCLKCR registers.
Figure 3-78. PCLKCR10 Register
31 30 29 28 27 26 25 24
RESERVED
R-0-0h

23 22 21 20 19 18 17 16
RESERVED
R-0-0h

15 14 13 12 11 10 9 8
RESERVED
R-0-0h

7 6 5 4 3 2 1 0
RESERVED RESERVED RESERVED MCAN_A RESERVED RESERVED CAN_B CAN_A
R-0-0h R-0-0h R-0-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h

Table 3-82. PCLKCR10 Register Field Descriptions

Bit Field Type Reset Description
31-16 RESERVED R-0 0h Reserved
15-8 RESERVED R-0 0h Reserved
7 RESERVED R-0 0h Reserved
6 RESERVED R-0 0h Reserved
5 RESERVED R-0 0h Reserved
4 MCAN_A R/W 0h MCAN_A Clock Enable bit:
0: Module clock is gated-off including module bit clock.
1: Module clock is turned-on
Note: This bit is reserved on CPU2.
Reset type: SYSRSn
3 RESERVED R/W 0h Reserved
2 RESERVED R/W 0h Reserved
1 CAN_B R/W 0h CAN_B Clock Enable bit:
0: Module clock is gated-off i including module bit clock.
1: Module clock is turned-on
Reset type: SYSRSn
0 CAN_A R/W 0h CAN_A Clock Enable bit:
0: Module clock is gated-off including module bit clock.
1: Module clock is turned-on
Reset type: SYSRSn

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3.16.5.14 PCLKCR11 Register (Offset = 38h) [Reset = 0h]

PCLKCR11 is shown in Figure 3-79 and described in Table 3-83.
Return to the Summary Table.
Peripheral Clock Gating Registers
Note: All the clock inputs of the specific IP may be gated using bits of PCLKCR registers.
Figure 3-79. PCLKCR11 Register
31 30 29 28 27 26 25 24
RESERVED
R-0-0h

23 22 21 20 19 18 17 16
RESERVED RESERVED USB_A
R-0-0h R/W-0h R/W-0h

15 14 13 12 11 10 9 8
RESERVED
R-0-0h

7 6 5 4 3 2 1 0
RESERVED McBSP_B McBSP_A
R-0-0h R/W-0h R/W-0h

Table 3-83. PCLKCR11 Register Field Descriptions

Bit Field Type Reset Description
31-18 RESERVED R-0 0h Reserved
17 RESERVED R/W 0h Reserved
16 USB_A R/W 0h USB_A Clock Enable bit:
0: Module clock is gated-off
1: Module clock is turned-on
Notes:
[1] This bit is not used (R/W) in CPU2.PCLKCR11 register. USB_A
clock enabled is controlled only from CPU1.PCLKCR11 register
Reset type: SYSRSn
15-2 RESERVED R-0 0h Reserved
1 McBSP_B R/W 0h McBSP_B Clock Enable bit:
0: Module clock is gated-off
1: Module clock is turned-on
Reset type: SYSRSn
0 McBSP_A R/W 0h McBSP_A Clock Enable bit:
0: Module clock is gated-off
1: Module clock is turned-on
Reset type: SYSRSn

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3.16.5.15 PCLKCR13 Register (Offset = 3Ch) [Reset = 0h]

PCLKCR13 is shown in Figure 3-80 and described in Table 3-84.
Return to the Summary Table.
Peripheral Clock Gating Registers
Note: All the clock inputs of the specific IP may be gated using bits of PCLKCR registers.
Figure 3-80. PCLKCR13 Register
31 30 29 28 27 26 25 24
RESERVED
R-0-0h

23 22 21 20 19 18 17 16
RESERVED
R-0-0h

15 14 13 12 11 10 9 8
RESERVED
R-0-0h

7 6 5 4 3 2 1 0
RESERVED ADC_D ADC_C ADC_B ADC_A
R-0-0h R/W-0h R/W-0h R/W-0h R/W-0h

Table 3-84. PCLKCR13 Register Field Descriptions

Bit Field Type Reset Description
31-16 RESERVED R-0 0h Reserved
15-4 RESERVED R-0 0h Reserved
3 ADC_D R/W 0h ADC_D Clock Enable bit:
0: Module clock is gated-off
1: Module clock is turned-on
Reset type: SYSRSn
2 ADC_C R/W 0h ADC_C Clock Enable bit:
0: Module clock is gated-off
1: Module clock is turned-on
Reset type: SYSRSn
1 ADC_B R/W 0h ADC_B Clock Enable bit:
0: Module clock is gated-off
1: Module clock is turned-on
Reset type: SYSRSn
0 ADC_A R/W 0h ADC_A Clock Enable bit:
0: Module clock is gated-off
1: Module clock is turned-on
Reset type: SYSRSn

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3.16.5.16 PCLKCR14 Register (Offset = 3Eh) [Reset = 0h]

PCLKCR14 is shown in Figure 3-81 and described in Table 3-85.
Return to the Summary Table.
Peripheral Clock Gating Registers
Note: All the clock inputs of the specific IP may be gated using bits of PCLKCR registers.
Figure 3-81. PCLKCR14 Register
31 30 29 28 27 26 25 24
RESERVED
R-0-0h

23 22 21 20 19 18 17 16
RESERVED
R-0-0h

15 14 13 12 11 10 9 8
RESERVED
R-0-0h

7 6 5 4 3 2 1 0
CMPSS8 CMPSS7 CMPSS6 CMPSS5 CMPSS4 CMPSS3 CMPSS2 CMPSS1
R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h

Table 3-85. PCLKCR14 Register Field Descriptions

Bit Field Type Reset Description
31-16 RESERVED R-0 0h Reserved
15-8 RESERVED R-0 0h Reserved
7 CMPSS8 R/W 0h CMPSS8 Clock Enable bit:
0: Module clock is gated-off
1: Module clock is turned-on
Reset type: SYSRSn
6 CMPSS7 R/W 0h CMPSS7 Clock Enable bit:
0: Module clock is gated-off
1: Module clock is turned-on
Reset type: SYSRSn
5 CMPSS6 R/W 0h CMPSS6 Clock Enable bit:
0: Module clock is gated-off
1: Module clock is turned-on
Reset type: SYSRSn
4 CMPSS5 R/W 0h CMPSS5 Clock Enable bit:
0: Module clock is gated-off
1: Module clock is turned-on
Reset type: SYSRSn
3 CMPSS4 R/W 0h CMPSS4 Clock Enable bit:
0: Module clock is gated-off
1: Module clock is turned-on
Reset type: SYSRSn
2 CMPSS3 R/W 0h CMPSS3 Clock Enable bit:
0: Module clock is gated-off
1: Module clock is turned-on
Reset type: SYSRSn
1 CMPSS2 R/W 0h CMPSS2 Clock Enable bit:
0: Module clock is gated-off
1: Module clock is turned-on
Reset type: SYSRSn

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Table 3-85. PCLKCR14 Register Field Descriptions (continued)

Bit Field Type Reset Description
0 CMPSS1 R/W 0h CMPSS1 Clock Enable bit:
0: Module clock is gated-off
1: Module clock is turned-on
Reset type: SYSRSn

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3.16.5.17 PCLKCR16 Register (Offset = 42h) [Reset = 0h]

PCLKCR16 is shown in Figure 3-82 and described in Table 3-86.
Return to the Summary Table.
Peripheral Clock Gating Registers
Note: All the clock inputs of the specific IP may be gated using bits of PCLKCR registers.
Figure 3-82. PCLKCR16 Register
31 30 29 28 27 26 25 24
RESERVED
R-0-0h

23 22 21 20 19 18 17 16
RESERVED RESERVED DAC_C DAC_B DAC_A
R-0-0h R/W-0h R/W-0h R/W-0h R/W-0h

15 14 13 12 11 10 9 8
RESERVED
R-0-0h

7 6 5 4 3 2 1 0
RESERVED
R-0-0h

Table 3-86. PCLKCR16 Register Field Descriptions

Bit Field Type Reset Description
31-20 RESERVED R-0 0h Reserved
19 RESERVED R/W 0h Reserved
18 DAC_C R/W 0h Buffered_DAC12_3 Clock Enable Bit:
0: Module clock is gated-off
1: Module clock is turned-on
Reset type: SYSRSn
17 DAC_B R/W 0h Buffered_DAC12_2 Clock Enable Bit:
0: Module clock is gated-off
1: Module clock is turned-on
Reset type: SYSRSn
16 DAC_A R/W 0h Buffered_DAC12_1 Clock Enable Bit:
0: Module clock is gated-off
1: Module clock is turned-on
Reset type: SYSRSn
15-0 RESERVED R-0 0h Reserved

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3.16.5.18 PCLKCR17 Register (Offset = 44h) [Reset = 0h]

PCLKCR17 is shown in Figure 3-83 and described in Table 3-87.
Return to the Summary Table.
Peripheral Clock Gating Registers
Note: All the clock inputs of the specific IP may be gated using bits of PCLKCR registers.
Figure 3-83. PCLKCR17 Register
31 30 29 28 27 26 25 24
RESERVED
R-0-0h

23 22 21 20 19 18 17 16
RESERVED
R-0-0h

15 14 13 12 11 10 9 8
RESERVED
R-0-0h

7 6 5 4 3 2 1 0
CLB8 CLB7 CLB6 CLB5 CLB4 CLB3 CLB2 CLB1
R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h

Table 3-87. PCLKCR17 Register Field Descriptions

Bit Field Type Reset Description
31-8 RESERVED R-0 0h Reserved
7 CLB8 R/W 0h CLB8 Clock Enable bit:
0: Module clock is gated-off
1: Module clock is turned-on
Reset type: SYSRSn
6 CLB7 R/W 0h CLB7 Clock Enable bit:
0: Module clock is gated-off
1: Module clock is turned-on
Reset type: SYSRSn
5 CLB6 R/W 0h CLB6 Clock Enable bit:
0: Module clock is gated-off
1: Module clock is turned-on
Reset type: SYSRSn
4 CLB5 R/W 0h CLB5 Clock Enable bit:
0: Module clock is gated-off
1: Module clock is turned-on
Reset type: SYSRSn
3 CLB4 R/W 0h CLB4 Clock Enable bit:
0: Module clock is gated-off
1: Module clock is turned-on
Reset type: SYSRSn
2 CLB3 R/W 0h CLB3 Clock Enable bit:
0: Module clock is gated-off
1: Module clock is turned-on
Reset type: SYSRSn
1 CLB2 R/W 0h CLB2 Clock Enable bit:
0: Module clock is gated-off
1: Module clock is turned-on
Reset type: SYSRSn

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Table 3-87. PCLKCR17 Register Field Descriptions (continued)

Bit Field Type Reset Description
0 CLB1 R/W 0h CLB1 Clock Enable bit:
0: Module clock is gated-off
1: Module clock is turned-on
Reset type: SYSRSn

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3.16.5.19 PCLKCR18 Register (Offset = 46h) [Reset = 0h]

PCLKCR18 is shown in Figure 3-84 and described in Table 3-88.
Return to the Summary Table.
Peripheral Clock Gating Registers
Note: All the clock inputs of the specific IP may be gated using bits of PCLKCR registers.
Figure 3-84. PCLKCR18 Register
31 30 29 28 27 26 25 24
RESERVED
R-0-0h

23 22 21 20 19 18 17 16
FSIRX_H FSIRX_G FSIRX_F FSIRX_E FSIRX_D FSIRX_C FSIRX_B FSIRX_A
R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h

15 14 13 12 11 10 9 8
RESERVED
R-0-0h

7 6 5 4 3 2 1 0
RESERVED RESERVED RESERVED RESERVED RESERVED RESERVED FSITX_B FSITX_A
R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h

Table 3-88. PCLKCR18 Register Field Descriptions

Bit Field Type Reset Description
31-24 RESERVED R-0 0h Reserved
23 FSIRX_H R/W 0h FSIRX_H Clock Enable bit:
0: Module clock is gated-off
1: Module clock is turned-on
Reset type: SYSRSn
22 FSIRX_G R/W 0h FSIRX_G Clock Enable bit:
0: Module clock is gated-off
1: Module clock is turned-on
Reset type: SYSRSn
21 FSIRX_F R/W 0h FSIRX_F Clock Enable bit:
0: Module clock is gated-off
1: Module clock is turned-on
Reset type: SYSRSn
20 FSIRX_E R/W 0h FSIRX_E Clock Enable bit:
0: Module clock is gated-off
1: Module clock is turned-on
Reset type: SYSRSn
19 FSIRX_D R/W 0h FSIRX_D Clock Enable bit:
0: Module clock is gated-off
1: Module clock is turned-on
Reset type: SYSRSn
18 FSIRX_C R/W 0h FSIRX_C Clock Enable bit:
0: Module clock is gated-off
1: Module clock is turned-on
Reset type: SYSRSn
17 FSIRX_B R/W 0h FSIRX_B Clock Enable bit:
0: Module clock is gated-off
1: Module clock is turned-on
Reset type: SYSRSn

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Table 3-88. PCLKCR18 Register Field Descriptions (continued)

Bit Field Type Reset Description
16 FSIRX_A R/W 0h FSIRX_A Clock Enable bit:
0: Module clock is gated-off
1: Module clock is turned-on
Reset type: SYSRSn
15-8 RESERVED R-0 0h Reserved
7 RESERVED R/W 0h Reserved
6 RESERVED R/W 0h Reserved
5 RESERVED R/W 0h Reserved
4 RESERVED R/W 0h Reserved
3 RESERVED R/W 0h Reserved
2 RESERVED R/W 0h Reserved
1 FSITX_B R/W 0h FSITX_B Clock Enable bit:
0: Module clock is gated-off
1: Module clock is turned-on
Reset type: SYSRSn
0 FSITX_A R/W 0h FSITX_A Clock Enable bit:
0: Module clock is gated-off
1: Module clock is turned-on
Reset type: SYSRSn

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3.16.5.20 PCLKCR20 Register (Offset = 4Ah) [Reset = 0h]

PCLKCR20 is shown in Figure 3-85 and described in Table 3-89.
Return to the Summary Table.
Peripheral Clock Gating Registers
Note: All the clock inputs of the specific IP may be gated using bits of PCLKCR registers.
Figure 3-85. PCLKCR20 Register
31 30 29 28 27 26 25 24
RESERVED
R-0-0h

23 22 21 20 19 18 17 16
RESERVED
R-0-0h

15 14 13 12 11 10 9 8
RESERVED
R-0-0h

7 6 5 4 3 2 1 0
RESERVED RESERVED PMBUS_A
R-0-0h R/W-0h R/W-0h

Table 3-89. PCLKCR20 Register Field Descriptions

Bit Field Type Reset Description
31-2 RESERVED R-0 0h Reserved
1 RESERVED R/W 0h Reserved
0 PMBUS_A R/W 0h PMBUS_A Clock Enable bit:
0: Module clock is gated-off
1: Module clock is turned-on
Reset type: SYSRSn

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3.16.5.21 PCLKCR21 Register (Offset = 4Ch) [Reset = 0h]

PCLKCR21 is shown in Figure 3-86 and described in Table 3-90.
Return to the Summary Table.
Peripheral Clock Gating Registers
Note: All the clock inputs of the specific IP may be gated using bits of PCLKCR registers.
Figure 3-86. PCLKCR21 Register
31 30 29 28 27 26 25 24
RESERVED
R-0-0h

23 22 21 20 19 18 17 16
RESERVED
R-0-0h

15 14 13 12 11 10 9 8
RESERVED
R-0-0h

7 6 5 4 3 2 1 0
RESERVED DCC2 DCC1 DCC0
R-0-0h R/W-0h R/W-0h R/W-0h

Table 3-90. PCLKCR21 Register Field Descriptions

Bit Field Type Reset Description
31-3 RESERVED R-0 0h Reserved
2 DCC2 R/W 0h DCC2 Clock Enable Bit:
0: Module clock is gated-off
1: Module clock is turned-on
Reset type: SYSRSn
1 DCC1 R/W 0h DCC1 Clock Enable Bit:
0: Module clock is gated-off
1: Module clock is turned-on
Reset type: SYSRSn
0 DCC0 R/W 0h DCC0 Clock Enable Bit:
0: Module clock is gated-off
1: Module clock is turned-on
Reset type: SYSRSn

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3.16.5.22 PCLKCR22 Register (Offset = 4Eh) [Reset = 0h]

PCLKCR22 is shown in Figure 3-87 and described in Table 3-91.
Return to the Summary Table.
Peripheral Clock Gating Registers
Note: All the clock inputs of the specific IP may be gated using bits of PCLKCR registers.
Figure 3-87. PCLKCR22 Register
31 30 29 28 27 26 25 24
RESERVED
R-0-0h

23 22 21 20 19 18 17 16
RESERVED
R-0-0h

15 14 13 12 11 10 9 8
RESERVED
R-0-0h

7 6 5 4 3 2 1 0
RESERVED MPOSTCLK
R-0-0h R/W-0h

Table 3-91. PCLKCR22 Register Field Descriptions

Bit Field Type Reset Description
31-1 RESERVED R-0 0h Reserved
0 MPOSTCLK R/W 0h MPOST Clock Enable Bit:
0: Module clock is gated-off
1: Module clock is turned-on
Note: This bit is reserved on CPU2.
Reset type: SYSRSn

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3.16.5.23 PCLKCR23 Register (Offset = 50h) [Reset = 0h]

PCLKCR23 is shown in Figure 3-88 and described in Table 3-92.
Return to the Summary Table.
Peripheral Clock Gating Registers
Note: All the clock inputs of the specific IP may be gated using bits of PCLKCR registers.
Figure 3-88. PCLKCR23 Register
31 30 29 28 27 26 25 24
RESERVED
R-0-0h

23 22 21 20 19 18 17 16
RESERVED
R-0-0h

15 14 13 12 11 10 9 8
RESERVED
R-0-0h

7 6 5 4 3 2 1 0
RESERVED ETHERCAT
R-0-0h R/W-0h

Table 3-92. PCLKCR23 Register Field Descriptions

Bit Field Type Reset Description
31-1 RESERVED R-0 0h Reserved
0 ETHERCAT R/W 0h ETHERCAT Clock Enable Bit:
0: Module clock is gated-off
1: Module clock is turned-on
Note: This bit is reserved on CPU2.
Reset type: SYSRSn

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3.16.5.24 SIMRESET Register (Offset = 70h) [Reset = 0h]

SIMRESET is shown in Figure 3-89 and described in Table 3-93.
Return to the Summary Table.
Simulated Reset Register
Note: This register exists only on CPU1
Figure 3-89. SIMRESET Register
31 30 29 28 27 26 25 24
KEY
R-0/W-0h

23 22 21 20 19 18 17 16
KEY
R-0/W-0h

15 14 13 12 11 10 9 8
RESERVED
R-0h

7 6 5 4 3 2 1 0
RESERVED XRSn CPU1RSn
R-0h R-0/W1S-0h R-0/W1S-0h

Table 3-93. SIMRESET Register Field Descriptions

Bit Field Type Reset Description
31-16 KEY R-0/W 0h Write to this register succeeds only if this field is written with a value
of 0xa5a5
Note:
[1] Due to this KEY, only 32-bit writes will succeed (provided the KEY
matches). 16-bit writes to the upper or lower half of this register will
be ignored
Reset type: XRSn
15-2 RESERVED R 0h Reserved
1 XRSn R-0/W1S 0h Writing a 1 to this field generates a XRSn like reset.
Writing a 0 has no effect.
Note: Writing to this pin will pull the XRSn pin low for 512 INTOSC1
clock cycles.
Reset type: XRSn
0 CPU1RSn R-0/W1S 0h Writing a 1 to this field generates a reset to to CPU1.
Writing a 0 has no effect.
Reset type: XRSn

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3.16.5.25 LPMCR Register (Offset = 76h) [Reset = FCh]

LPMCR is shown in Figure 3-90 and described in Table 3-94.
Return to the Summary Table.
LPM Control Register
Figure 3-90. LPMCR Register
31 30 29 28 27 26 25 24
RESERVED RESERVED
R/W1S-0h R-0-0h

23 22 21 20 19 18 17 16
RESERVED RESERVED
R-0-0h R/W-0h

15 14 13 12 11 10 9 8
WDINTE RESERVED
R/W-0h R-0-0h

7 6 5 4 3 2 1 0
QUALSTDBY LPM
R/W-3Fh R/W-0h

Table 3-94. LPMCR Register Field Descriptions

Bit Field Type Reset Description
31 RESERVED R/W1S 0h Reserved
30-18 RESERVED R-0 0h Reserved
17-16 RESERVED R/W 0h Reserved
15 WDINTE R/W 0h When this bit is set to 1, it enables the watchdog interrupt signal to
wake the device from STANDBY mode.
Note:
[1] To use this signal, the user must also enable the WDINTn signal
using the WDENINT bit in the SCSR register.
Reset type: SYSRSn
14-8 RESERVED R-0 0h Reserved
7-2 QUALSTDBY R/W 3Fh Select number of OSCCLK clock cycles to qualify the selected inputs
when waking the from STANDBY mode:
000000 = 2 OSCCLKs
000001 = 3 OSCCLKs
......
111111 = 65 OSCCLKs
Note: The LPMCR.QUALSTDBY register should be set to a value
greater than the ratio of INTOSC1/PLLSYSCLK to ensure proper
wake up.
Reset type: SYSRSn
1-0 LPM R/W 0h These bits set the low power mode for the device. Takes effect when
CPU executes the IDLE instruction (when IDLE instruction is out of
EXE Phase of the Pipeline)
00: IDLE Mode
01: STANDBY Mode
1x: Reserved
Reset type: SYSRSn

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3.16.5.26 GPIOLPMSEL0 Register (Offset = 78h) [Reset = 0h]

GPIOLPMSEL0 is shown in Figure 3-91 and described in Table 3-95.
Return to the Summary Table.
GPIO LPM Wakeup select registers
Connects the selected pin to the LPM circuit. Refer to LPM section of the TRM for the wakeup capabilities of the
selected pin.
Figure 3-91. GPIOLPMSEL0 Register
31 30 29 28 27 26 25 24
GPIO31 GPIO30 GPIO29 GPIO28 GPIO27 GPIO26 GPIO25 GPIO24
R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h

23 22 21 20 19 18 17 16
GPIO23 GPIO22 GPIO21 GPIO20 GPIO19 GPIO18 GPIO17 GPIO16
R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h

15 14 13 12 11 10 9 8
GPIO15 GPIO14 GPIO13 GPIO12 GPIO11 GPIO10 GPIO9 GPIO8
R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h

7 6 5 4 3 2 1 0
GPIO7 GPIO6 GPIO5 GPIO4 GPIO3 GPIO2 GPIO1 GPIO0
R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h

Table 3-95. GPIOLPMSEL0 Register Field Descriptions

Bit Field Type Reset Description
31 GPIO31 R/W 0h 0 pin is dis-connected from LPM circuit
1 pin is connected to LPM circuit
Reset type: SYSRSn
30 GPIO30 R/W 0h 0 pin is dis-connected from LPM circuit
1 pin is connected to LPM circuit
Reset type: SYSRSn
29 GPIO29 R/W 0h 0 pin is dis-connected from LPM circuit
1 pin is connected to LPM circuit
Reset type: SYSRSn
28 GPIO28 R/W 0h 0 pin is dis-connected from LPM circuit
1 pin is connected to LPM circuit
Reset type: SYSRSn
27 GPIO27 R/W 0h 0 pin is dis-connected from LPM circuit
1 pin is connected to LPM circuit
Reset type: SYSRSn
26 GPIO26 R/W 0h 0 pin is dis-connected from LPM circuit
1 pin is connected to LPM circuit
Reset type: SYSRSn
25 GPIO25 R/W 0h 0 pin is dis-connected from LPM circuit
1 pin is connected to LPM circuit
Reset type: SYSRSn
24 GPIO24 R/W 0h 0 pin is dis-connected from LPM circuit
1 pin is connected to LPM circuit
Reset type: SYSRSn
23 GPIO23 R/W 0h 0 pin is dis-connected from LPM circuit
1 pin is connected to LPM circuit
Reset type: SYSRSn
22 GPIO22 R/W 0h 0 pin is dis-connected from LPM circuit
1 pin is connected to LPM circuit
Reset type: SYSRSn

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Table 3-95. GPIOLPMSEL0 Register Field Descriptions (continued)

Bit Field Type Reset Description
21 GPIO21 R/W 0h 0 pin is dis-connected from LPM circuit
1 pin is connected to LPM circuit
Reset type: SYSRSn
20 GPIO20 R/W 0h 0 pin is dis-connected from LPM circuit
1 pin is connected to LPM circuit
Reset type: SYSRSn
19 GPIO19 R/W 0h 0 pin is dis-connected from LPM circuit
1 pin is connected to LPM circuit
Reset type: SYSRSn
18 GPIO18 R/W 0h 0 pin is dis-connected from LPM circuit
1 pin is connected to LPM circuit
Reset type: SYSRSn
17 GPIO17 R/W 0h 0 pin is dis-connected from LPM circuit
1 pin is connected to LPM circuit
Reset type: SYSRSn
16 GPIO16 R/W 0h 0 pin is dis-connected from LPM circuit
1 pin is connected to LPM circuit
Reset type: SYSRSn
15 GPIO15 R/W 0h 0 pin is dis-connected from LPM circuit
1 pin is connected to LPM circuit
Reset type: SYSRSn
14 GPIO14 R/W 0h 0 pin is dis-connected from LPM circuit
1 pin is connected to LPM circuit
Reset type: SYSRSn
13 GPIO13 R/W 0h 0 pin is dis-connected from LPM circuit
1 pin is connected to LPM circuit
Reset type: SYSRSn
12 GPIO12 R/W 0h 0 pin is dis-connected from LPM circuit
1 pin is connected to LPM circuit
Reset type: SYSRSn
11 GPIO11 R/W 0h 0 pin is dis-connected from LPM circuit
1 pin is connected to LPM circuit
Reset type: SYSRSn
10 GPIO10 R/W 0h 0 pin is dis-connected from LPM circuit
1 pin is connected to LPM circuit
Reset type: SYSRSn
9 GPIO9 R/W 0h 0 pin is dis-connected from LPM circuit
1 pin is connected to LPM circuit
Reset type: SYSRSn
8 GPIO8 R/W 0h 0 pin is dis-connected from LPM circuit
1 pin is connected to LPM circuit
Reset type: SYSRSn
7 GPIO7 R/W 0h 0 pin is dis-connected from LPM circuit
1 pin is connected to LPM circuit
Reset type: SYSRSn
6 GPIO6 R/W 0h 0 pin is dis-connected from LPM circuit
1 pin is connected to LPM circuit
Reset type: SYSRSn
5 GPIO5 R/W 0h 0 pin is dis-connected from LPM circuit
1 pin is connected to LPM circuit
Reset type: SYSRSn
4 GPIO4 R/W 0h 0 pin is dis-connected from LPM circuit
1 pin is connected to LPM circuit
Reset type: SYSRSn
3 GPIO3 R/W 0h 0 pin is dis-connected from LPM circuit
1 pin is connected to LPM circuit
Reset type: SYSRSn

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Table 3-95. GPIOLPMSEL0 Register Field Descriptions (continued)

Bit Field Type Reset Description
2 GPIO2 R/W 0h 0 pin is dis-connected from LPM circuit
1 pin is connected to LPM circuit
Reset type: SYSRSn
1 GPIO1 R/W 0h 0 pin is dis-connected from LPM circuit
1 pin is connected to LPM circuit
Reset type: SYSRSn
0 GPIO0 R/W 0h 0 pin is dis-connected from LPM circuit
1 pin is connected to LPM circuit
Reset type: SYSRSn

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3.16.5.27 GPIOLPMSEL1 Register (Offset = 7Ah) [Reset = 0h]

GPIOLPMSEL1 is shown in Figure 3-92 and described in Table 3-96.
Return to the Summary Table.
GPIO LPM Wakeup select registers
Connects the selected pin to the LPM circuit. Refer to LPM section of the TRM for the wakeup capabilities of the
selected pin.
Figure 3-92. GPIOLPMSEL1 Register
31 30 29 28 27 26 25 24
GPIO63 GPIO62 GPIO61 GPIO60 GPIO59 GPIO58 GPIO57 GPIO56
R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h

23 22 21 20 19 18 17 16
GPIO55 GPIO54 GPIO53 GPIO52 GPIO51 GPIO50 GPIO49 GPIO48
R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h

15 14 13 12 11 10 9 8
GPIO47 GPIO46 GPIO45 GPIO44 GPIO43 GPIO42 GPIO41 GPIO40
R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h

7 6 5 4 3 2 1 0
GPIO39 GPIO38 GPIO37 GPIO36 GPIO35 GPIO34 GPIO33 GPIO32
R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h

Table 3-96. GPIOLPMSEL1 Register Field Descriptions

Bit Field Type Reset Description
31 GPIO63 R/W 0h 0 pin is dis-connected from LPM circuit
1 pin is connected to LPM circuit
Reset type: SYSRSn
30 GPIO62 R/W 0h 0 pin is dis-connected from LPM circuit
1 pin is connected to LPM circuit
Reset type: SYSRSn
29 GPIO61 R/W 0h 0 pin is dis-connected from LPM circuit
1 pin is connected to LPM circuit
Reset type: SYSRSn
28 GPIO60 R/W 0h 0 pin is dis-connected from LPM circuit
1 pin is connected to LPM circuit
Reset type: SYSRSn
27 GPIO59 R/W 0h 0 pin is dis-connected from LPM circuit
1 pin is connected to LPM circuit
Reset type: SYSRSn
26 GPIO58 R/W 0h 0 pin is dis-connected from LPM circuit
1 pin is connected to LPM circuit
Reset type: SYSRSn
25 GPIO57 R/W 0h 0 pin is dis-connected from LPM circuit
1 pin is connected to LPM circuit
Reset type: SYSRSn
24 GPIO56 R/W 0h 0 pin is dis-connected from LPM circuit
1 pin is connected to LPM circuit
Reset type: SYSRSn
23 GPIO55 R/W 0h 0 pin is dis-connected from LPM circuit
1 pin is connected to LPM circuit
Reset type: SYSRSn
22 GPIO54 R/W 0h 0 pin is dis-connected from LPM circuit
1 pin is connected to LPM circuit
Reset type: SYSRSn

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Table 3-96. GPIOLPMSEL1 Register Field Descriptions (continued)

Bit Field Type Reset Description
21 GPIO53 R/W 0h 0 pin is dis-connected from LPM circuit
1 pin is connected to LPM circuit
Reset type: SYSRSn
20 GPIO52 R/W 0h 0 pin is dis-connected from LPM circuit
1 pin is connected to LPM circuit
Reset type: SYSRSn
19 GPIO51 R/W 0h 0 pin is dis-connected from LPM circuit
1 pin is connected to LPM circuit
Reset type: SYSRSn
18 GPIO50 R/W 0h 0 pin is dis-connected from LPM circuit
1 pin is connected to LPM circuit
Reset type: SYSRSn
17 GPIO49 R/W 0h 0 pin is dis-connected from LPM circuit
1 pin is connected to LPM circuit
Reset type: SYSRSn
16 GPIO48 R/W 0h 0 pin is dis-connected from LPM circuit
1 pin is connected to LPM circuit
Reset type: SYSRSn
15 GPIO47 R/W 0h 0 pin is dis-connected from LPM circuit
1 pin is connected to LPM circuit
Reset type: SYSRSn
14 GPIO46 R/W 0h 0 pin is dis-connected from LPM circuit
1 pin is connected to LPM circuit
Reset type: SYSRSn
13 GPIO45 R/W 0h 0 pin is dis-connected from LPM circuit
1 pin is connected to LPM circuit
Reset type: SYSRSn
12 GPIO44 R/W 0h 0 pin is dis-connected from LPM circuit
1 pin is connected to LPM circuit
Reset type: SYSRSn
11 GPIO43 R/W 0h 0 pin is dis-connected from LPM circuit
1 pin is connected to LPM circuit
Reset type: SYSRSn
10 GPIO42 R/W 0h 0 pin is dis-connected from LPM circuit
1 pin is connected to LPM circuit
Reset type: SYSRSn
9 GPIO41 R/W 0h 0 pin is dis-connected from LPM circuit
1 pin is connected to LPM circuit
Reset type: SYSRSn
8 GPIO40 R/W 0h 0 pin is dis-connected from LPM circuit
1 pin is connected to LPM circuit
Reset type: SYSRSn
7 GPIO39 R/W 0h 0 pin is dis-connected from LPM circuit
1 pin is connected to LPM circuit
Reset type: SYSRSn
6 GPIO38 R/W 0h 0 pin is dis-connected from LPM circuit
1 pin is connected to LPM circuit
Reset type: SYSRSn
5 GPIO37 R/W 0h 0 pin is dis-connected from LPM circuit
1 pin is connected to LPM circuit
Reset type: SYSRSn
4 GPIO36 R/W 0h 0 pin is dis-connected from LPM circuit
1 pin is connected to LPM circuit
Reset type: SYSRSn
3 GPIO35 R/W 0h 0 pin is dis-connected from LPM circuit
1 pin is connected to LPM circuit
Reset type: SYSRSn

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Table 3-96. GPIOLPMSEL1 Register Field Descriptions (continued)

Bit Field Type Reset Description
2 GPIO34 R/W 0h 0 pin is dis-connected from LPM circuit
1 pin is connected to LPM circuit
Reset type: SYSRSn
1 GPIO33 R/W 0h 0 pin is dis-connected from LPM circuit
1 pin is connected to LPM circuit
Reset type: SYSRSn
0 GPIO32 R/W 0h 0 pin is dis-connected from LPM circuit
1 pin is connected to LPM circuit
Reset type: SYSRSn

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3.16.5.28 TMR2CLKCTL Register (Offset = 7Ch) [Reset = 0h]

TMR2CLKCTL is shown in Figure 3-93 and described in Table 3-97.
Return to the Summary Table.
Timer2 Clock Measurement functionality control register
This memory mapped register requires a delay of 69 SYSCLK cycles between subsequent writes to the register,
otherwise a second write can be lost. This delay can be realized by adding 69 NOP instructions.
Figure 3-93. TMR2CLKCTL Register
31 30 29 28 27 26 25 24
RESERVED
R-0-0h

23 22 21 20 19 18 17 16
RESERVED
R-0-0h

15 14 13 12 11 10 9 8
RESERVED
R-0-0h

7 6 5 4 3 2 1 0
RESERVED TMR2CLKPRESCALE TMR2CLKSRCSEL
R-0-0h R/W-0h R/W-0h

Table 3-97. TMR2CLKCTL Register Field Descriptions

Bit Field Type Reset Description
31-16 RESERVED R-0 0h Reserved
15-6 RESERVED R-0 0h Reserved
5-3 TMR2CLKPRESCALE R/W 0h CPU Timer 2 Clock Pre-Scale Value: These bits select the pre-scale
value for the selected clock source for CPU Timer 2:
000: /1 (default on reset)
001: /2
010: /4
011: /8
100: /16
101: spare (defaults to : /16)
110: spare (defaults to : /16)
111: spare (defaults to : /16)
Reset type: SYSRSn
2-0 TMR2CLKSRCSEL R/W 0h CPU Timer 2 Clock Source Select Bit: This bit selects the source for
CPU Timer 2:
000 =SYSCLK Selected (default on reset, pre-scale is bypassed)
001 = INTOSC1
010 = INTOSC2
011 = XTAL
110 = AUXPLLCLK
other values are reserved
Reset type: SYSRSn

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3.16.5.29 RESCCLR Register (Offset = 7Eh) [Reset = 0h]

RESCCLR is shown in Figure 3-94 and described in Table 3-98.
Return to the Summary Table.
Reset Cause Clear Register
Figure 3-94. RESCCLR Register
31 30 29 28 27 26 25 24
RESERVED
R-0-0h

23 22 21 20 19 18 17 16
RESERVED
R-0-0h

15 14 13 12 11 10 9 8
RESERVED SIMRESET_XR SIMRESET_CP ECAT_RESET_ SCCRESETn
Sn U1RSn OUT
R-0-0h W1C-0h W1C-0h W1C-0h W1C-0h

7 6 5 4 3 2 1 0
RESERVED RESERVED HWBISTn RESERVED NMIWDRSn WDRSn XRSn POR
R-0-0h W1C-0h W1C-0h R-0-0h W1C-0h W1C-0h W1C-0h W1C-0h

Table 3-98. RESCCLR Register Field Descriptions

Bit Field Type Reset Description
31-12 RESERVED R-0 0h Reserved
11 SIMRESET_XRSn W1C 0h Clear bit for corresponding status bit in RESC. Read of RESCCLR
always gives 0.
Writing a 1 to this bit clears the status bit in RESC to 0
Writing 0 has no effect.
Reset type: SYSRSn
10 SIMRESET_CPU1RSn W1C 0h Clear bit for corresponding status bit in RESC. Read of RESCCLR
always gives 0.
Writing a 1 to this bit clears the status bit in RESC to 0
Writing 0 has no effect.
Reset type: SYSRSn
9 ECAT_RESET_OUT W1C 0h Clear bit for corresponding status bit in RESC. Read of RESCCLR
always gives 0.
Writing a 1 to this bit clears the status bit in RESC to 0
Writing 0 has no effect.
Reset type: SYSRSn
8 SCCRESETn W1C 0h Clear bit for corresponding status bit in RESC. Read of RESCCLR
always gives 0.
Writing a 1 to this bit clears the status bit in RESC to 0
Writing 0 has no effect.
Reset type: SYSRSn
7 RESERVED R-0 0h Reserved
6 RESERVED W1C 0h Reserved
5 HWBISTn W1C 0h Clear bit for corresponding status bit in RESC. Read of RESCCLR
always gives 0.
Writing a 1 to this bit clears the status bit in RESC to 0
Writing 0 has no effect.
Reset type: SYSRSn
4 RESERVED R-0 0h Reserved

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Table 3-98. RESCCLR Register Field Descriptions (continued)

Bit Field Type Reset Description
3 NMIWDRSn W1C 0h Clear bit for corresponding status bit in RESC. Read of RESCCLR
always gives 0.
Writing a 1 to this bit clears the status bit in RESC to 0
Writing 0 has no effect.
Reset type: SYSRSn
2 WDRSn W1C 0h Clear bit for corresponding status bit in RESC. Read of RESCCLR
always gives 0.
Writing a 1 to this bit clears the status bit in RESC to 0
Writing 0 has no effect.
Reset type: SYSRSn
1 XRSn W1C 0h Clear bit for corresponding status bit in RESC. Read of RESCCLR
always gives 0.
Writing a 1 to this bit clears the status bit in RESC to 0
Writing 0 has no effect.
Reset type: SYSRSn
0 POR W1C 0h Clear bit for corresponding status bit in RESC. Read of RESCCLR
always gives 0.
Writing a 1 to this bit clears the status bit in RESC to 0
Writing 0 has no effect.
Reset type: SYSRSn

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3.16.5.30 RESC Register (Offset = 80h) [Reset = X]

RESC is shown in Figure 3-95 and described in Table 3-99.
Return to the Summary Table.
Reset Cause register
Figure 3-95. RESC Register
31 30 29 28 27 26 25 24
TRSTn_pin_stat XRSn_pin_statu RESERVED
us s
R-X R-X R-0-0h

23 22 21 20 19 18 17 16
RESERVED
R-0-0h

15 14 13 12 11 10 9 8
RESERVED SIMRESET_XR SIMRESET_CP ECAT_RESET_ SCCRESETn
Sn U1RSn OUT
R-0-0h R/W1C-0h R/W1C-0h R/W1C-0h R/W1C-0h

7 6 5 4 3 2 1 0
RESERVED RESERVED HWBISTn RESERVED NMIWDRSn WDRSn XRSn POR
R-0-0h R/W1C-0h R/W1C-0h R-0-0h R/W1C-0h R/W1C-0h R/W1C-1h R/W1C-1h

Table 3-99. RESC Register Field Descriptions

Bit Field Type Reset Description
31 TRSTn_pin_status R X Reading this bit provides the current status of TRSTn at the
respective C28x CPUs TRSTn input port. Reset value is reflective
of the pin status.
Reset type: PORESETn
30 XRSn_pin_status R X Reading this bit provides the current status of the XRSn pin. Reset
value is reflective of the pin status.
Reset type: PORESETn
29-12 RESERVED R-0 0h Reserved
11 SIMRESET_XRSn R/W1C 0h If this bit is set, indicates that the device was reset by
SIMRESET_XRSn
Writing a 1 to this bit will force the bit to 0
Writing of 0 will have no effect.
Reset type: PORESETn
10 SIMRESET_CPU1RSn R/W1C 0h If this bit is set, indicates that the device was reset by
SIMRESET_CPU1RSn
Writing a 1 to this bit will force the bit to 0
Writing of 0 will have no effect.
Reset type: PORESETn
9 ECAT_RESET_OUT R/W1C 0h If this bit is set, indicates that the device was reset by
ECAT_RESET_OUT
Writing a 1 to this bit will force the bit to 0
Writing of 0 will have no effect.
Reset type: PORESETn
8 SCCRESETn R/W1C 0h If this bit is set, indicates that the device was reset by SCCRESETn
Writing a 1 to this bit will force the bit to 0
Writing of 0 will have no effect.
Reset type: PORESETn
7 RESERVED R-0 0h Reserved
6 RESERVED R/W1C 0h Reserved

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Table 3-99. RESC Register Field Descriptions (continued)

Bit Field Type Reset Description
5 HWBISTn R/W1C 0h If this bit is set, indicates that the device was reset by HWBISTn
Writing a 1 to this bit will force the bit to 0
Writing of 0 will have no effect.
Reset type: PORESETn
4 RESERVED R-0 0h Reserved
3 NMIWDRSn R/W1C 0h If this bit is set, indicates that the device was reset by NMIWDRSn.
Writing a 1 to this bit will force the bit to 0
Writing of 0 will have no effect.
To know the exact cause of NMI after the reset, software needs to
read CPU1/2.NMISHDFLG registers
Reset type: PORESETn
2 WDRSn R/W1C 0h If this bit is set, indicates that the device was reset by WDRSn
Writing a 1 to this bit will force the bit to 0
Writing of 0 will have no effect.
Reset type: PORESETn
1 XRSn R/W1C 1h If this bit is set, indicates that the device was reset by XRSn
Writing a 1 to this bit will force the bit to 0
Writing of 0 will have no effect.
Reset type: PORESETn
0 POR R/W1C 1h If this bit is set, indicates that the device was reset by POR
Writing a 1 to this bit will force the bit to 0
Writing of 0 will have no effect.
Reset type: PORESETn

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3.16.5.31 MCANWAKESTATUS Register (Offset = 98h) [Reset = 0h]

MCANWAKESTATUS is shown in Figure 3-96 and described in Table 3-100.
Return to the Summary Table.
MCAN Wake Status Register
Figure 3-96. MCANWAKESTATUS Register
31 30 29 28 27 26 25 24
RESERVED
R-0h

23 22 21 20 19 18 17 16
RESERVED
R-0h

15 14 13 12 11 10 9 8
RESERVED
R-0h

7 6 5 4 3 2 1 0
RESERVED WAKE
R-0h R-0h

Table 3-100. MCANWAKESTATUS Register Field Descriptions

Bit Field Type Reset Description
31-1 RESERVED R 0h Reserved
0 WAKE R 0h 0 : wakeup event has not occured.
1 : wakeup event has occured.
Reset type: CPU1.SYSRSn

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3.16.5.32 MCANWAKESTATUSCLR Register (Offset = 9Ah) [Reset = 0h]

MCANWAKESTATUSCLR is shown in Figure 3-97 and described in Table 3-101.
Return to the Summary Table.
MCAN Wake Status Clear Register
Figure 3-97. MCANWAKESTATUSCLR Register
31 30 29 28 27 26 25 24
RESERVED
R-0h

23 22 21 20 19 18 17 16
RESERVED
R-0h

15 14 13 12 11 10 9 8
RESERVED
R-0h

7 6 5 4 3 2 1 0
RESERVED WAKE
R-0h R-0/W1S-0h

Table 3-101. MCANWAKESTATUSCLR Register Field Descriptions

Bit Field Type Reset Description
31-1 RESERVED R 0h Reserved
0 WAKE R-0/W1S 0h 0 : No effect.
1 : Clears WAKE bit of MCANWAKESTATUS register
Reset type: CPU1.SYSRSn

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3.16.6 CPU_ID_REGS Registers

Table 3-102 lists the memory-mapped registers for the CPU_ID_REGS registers. All register offset addresses
not listed in Table 3-102 should be considered as reserved locations and the register contents should not be
modified.
Table 3-102. CPU_ID_REGS Registers
Offset Acronym Register Name Write Protection Section
0h CPUID Indicates CPU1 or CPU2 Go

Complex bit access types are encoded to fit into small table cells. Table 3-103 shows the codes that are used for
access types in this section.
Table 3-103. CPU_ID_REGS Access Type Codes
Access Type Code Description
Read Type
R R Read
Reset or Default Value
-n Value after reset or the default
value
Register Array Variables
i,j,k,l,m,n When these variables are used in
a register name, an offset, or an
address, they refer to the value of
a register array where the register
is part of a group of repeating
registers. The register groups
form a hierarchical structure and
the array is represented with a
formula.
y When this variable is used in a
register name, an offset, or an
address it refers to the value of
a register array.

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3.16.6.1 CPUID Register (Offset = 0h) [Reset = X]

CPUID is shown in Figure 3-98 and described in Table 3-104.
Return to the Summary Table.
This register can be used to identify on which CPU the code is executing.
Figure 3-98. CPUID Register
15 14 13 12 11 10 9 8
RESERVED
R-X

7 6 5 4 3 2 1 0
CPUID
R-X

Table 3-104. CPUID Register Field Descriptions

Bit Field Type Reset Description
15-8 RESERVED R X Reserved
7-0 CPUID R X CPUID = 1 for CPU1, 2 for CPU2
Reset type: N/A

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3.16.7 CPU1_PERIPH_AC_REGS Registers

Table 3-105 lists the memory-mapped registers for the CPU1_PERIPH_AC_REGS registers. All register offset
addresses not listed in Table 3-105 should be considered as reserved locations and the register contents should
not be modified.
Table 3-105. CPU1_PERIPH_AC_REGS Registers
Offset Acronym Register Name Write Protection Section
0h ADCA_AC ADCA Master Access Control Register EALLOW Go
2h ADCB_AC ADCB Master Access Control Register EALLOW Go
4h ADCC_AC ADCC Master Access Control Register EALLOW Go
6h ADCD_AC ADCD Master Access Control Register EALLOW Go
10h CMPSS1_AC CMPSS1 Master Access Control Register EALLOW Go
12h CMPSS2_AC CMPSS2 Master Access Control Register EALLOW Go
14h CMPSS3_AC CMPSS3 Master Access Control Register EALLOW Go
16h CMPSS4_AC CMPSS4 Master Access Control Register EALLOW Go
18h CMPSS5_AC CMPSS5 Master Access Control Register EALLOW Go
1Ah CMPSS6_AC CMPSS6 Master Access Control Register EALLOW Go
1Ch CMPSS7_AC CMPSS7 Master Access Control Register EALLOW Go
1Eh CMPSS8_AC CMPSS8 Master Access Control Register EALLOW Go
28h DACA_AC DACA Master Access Control Register EALLOW Go
2Ah DACB_AC DACB Master Access Control Register EALLOW Go
2Ch DACC_AC DACC Master Access Control Register EALLOW Go
48h EPWM1_AC EPWM1 Master Access Control Register EALLOW Go
4Ah EPWM2_AC EPWM2 Master Access Control Register EALLOW Go
4Ch EPWM3_AC EPWM3 Master Access Control Register EALLOW Go
4Eh EPWM4_AC EPWM4 Master Access Control Register EALLOW Go
50h EPWM5_AC EPWM5 Master Access Control Register EALLOW Go
52h EPWM6_AC EPWM6 Master Access Control Register EALLOW Go
54h EPWM7_AC EPWM7 Master Access Control Register EALLOW Go
56h EPWM8_AC EPWM8 Master Access Control Register EALLOW Go
58h EPWM9_AC EPWM9 Master Access Control Register EALLOW Go
5Ah EPWM10_AC EPWM10 Master Access Control Register EALLOW Go
5Ch EPWM11_AC EPWM11 Master Access Control Register EALLOW Go
5Eh EPWM12_AC EPWM12 Master Access Control Register EALLOW Go
60h EPWM13_AC EPWM13 Master Access Control Register EALLOW Go
62h EPWM14_AC EPWM14 Master Access Control Register EALLOW Go
64h EPWM15_AC EPWM15 Master Access Control Register EALLOW Go
66h EPWM16_AC EPWM16 Master Access Control Register EALLOW Go
70h EQEP1_AC EQEP1 Master Access Control Register EALLOW Go
72h EQEP2_AC EQEP2 Master Access Control Register EALLOW Go
74h EQEP3_AC EQEP3 Master Access Control Register EALLOW Go
80h ECAP1_AC ECAP1 Master Access Control Register EALLOW Go
82h ECAP2_AC ECAP2 Master Access Control Register EALLOW Go
84h ECAP3_AC ECAP3 Master Access Control Register EALLOW Go
86h ECAP4_AC ECAP4 Master Access Control Register EALLOW Go
88h ECAP5_AC ECAP5 Master Access Control Register EALLOW Go
8Ah ECAP6_AC ECAP6 Master Access Control Register EALLOW Go
8Ch ECAP7_AC ECAP7 Master Access Control Register EALLOW Go

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Table 3-105. CPU1_PERIPH_AC_REGS Registers (continued)

Offset Acronym Register Name Write Protection Section
A8h SDFM1_AC SDFM1 Master Access Control Register EALLOW Go
AAh SDFM2_AC SDFM2 Master Access Control Register EALLOW Go
B0h CLB1_AC CLB1 Master Access Control Register EALLOW Go
B2h CLB2_AC CLB2 Master Access Control Register EALLOW Go
B4h CLB3_AC CLB3 Master Access Control Register EALLOW Go
B6h CLB4_AC CLB4 Master Access Control Register EALLOW Go
B8h CLB5_AC CLB5 Master Access Control Register EALLOW Go
BAh CLB6_AC CLB6 Master Access Control Register EALLOW Go
BCh CLB7_AC CLB7 Master Access Control Register EALLOW Go
BEh CLB8_AC CLB8 Master Access Control Register EALLOW Go
110h SPIA_AC SPIA Master Access Control Register EALLOW Go
112h SPIB_AC SPIB Master Access Control Register EALLOW Go
114h SPIC_AC SPIC Master Access Control Register EALLOW Go
116h SPID_AC SPID Master Access Control Register EALLOW Go
130h PMBUS_A_AC PMBUSA Master Access Control Register EALLOW Go
140h CAN_A_AC CAN_A Master Access Control Register EALLOW Go
142h CAN_B_AC CAN_B Master Access Control Register EALLOW Go
150h MCBSPA_AC MCBSPA Master Access Control Register EALLOW Go
152h MCBSPB_AC MCBSPB Master Access Control Register EALLOW Go
180h USBA_AC USBA Master Access Control Register EALLOW Go
1A8h HRPWM_AC HRPWM Master Access Control Register EALLOW Go
1AAh ETHERCAT_AC ETHERCAT Master Access Control Register EALLOW Go
1B0h FSIATX_AC FSIATX Master Access Control Register EALLOW Go
1B2h FSIARX_AC FSIARX Master Access Control Register EALLOW Go
1B4h FSIBTX_AC FSIBTX Master Access Control Register EALLOW Go
1B6h FSIBRX_AC FSIBRX Master Access Control Register EALLOW Go
1BAh FSICRX_AC FSICRX Master Access Control Register EALLOW Go
1BEh FSIDRX_AC FSIDRX Master Access Control Register EALLOW Go
1C2h FSIERX_AC FSIERX Master Access Control Register EALLOW Go
1C6h FSIFRX_AC FSIFRX Master Access Control Register EALLOW Go
1CAh FSIGRX_AC FSIGRX Master Access Control Register EALLOW Go
1CEh FSIHRX_AC FSIHRX Master Access Control Register EALLOW Go
1D0h MCANA_AC MCANA Master Access Control Register EALLOW Go
1FEh PERIPH_AC_LOCK Lock Register to stop Write access to peripheral EALLOW Go
Access register.

Complex bit access types are encoded to fit into small table cells. Table 3-106 shows the codes that are used for
access types in this section.
Table 3-106. CPU1_PERIPH_AC_REGS Access Type
Codes
Access Type Code Description
Read Type
R R Read
R-0 R Read
-0 Returns 0s
Write Type

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Table 3-106. CPU1_PERIPH_AC_REGS Access Type

Codes (continued)
Access Type Code Description
W W Write
WSonce W Write
Sonce Set once
Reset or Default Value
-n Value after reset or the default
value
Register Array Variables
i,j,k,l,m,n When these variables are used in
a register name, an offset, or an
address, they refer to the value of
a register array where the register
is part of a group of repeating
registers. The register groups
form a hierarchical structure and
the array is represented with a
formula.
y When this variable is used in a
register name, an offset, or an
address it refers to the value of
a register array.

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3.16.7.1 ADCA_AC Register (Offset = 0h) [Reset = 3Fh]

ADCA_AC is shown in Figure 3-99 and described in Table 3-107.
Return to the Summary Table.
Based on control settings allows Full, Protected Read, No Access to peripheral from corresponding connected
master.
Figure 3-99. ADCA_AC Register
31 30 29 28 27 26 25 24
RESERVED
R-0-0h

23 22 21 20 19 18 17 16
RESERVED
R-0-0h

15 14 13 12 11 10 9 8
RESERVED
R-0-0h

7 6 5 4 3 2 1 0
RESERVED DMA1_ACC CLA1_ACC CPUx_ACC
R-0-0h R/W-3h R/W-3h R/W-3h

Table 3-107. ADCA_AC Register Field Descriptions

Bit Field Type Reset Description
31-6 RESERVED R-0 0h Reserved
5-4 DMA1_ACC R/W 3h Defines Access control definition for the DMA1 as:
11: Full Access for both read and Write
10: Protected RD Access such that FIFOs, Clear on read registers
are not changed + No Write Access
01: Reserved
00: No Read/Write Access to peripheral
Reset type: XRSn
3-2 CLA1_ACC R/W 3h Defines Access control definition for the CLA1 as:
11: Full Access for both read and Write
10: Protected RD Access such that FIFOs, Clear on read registers
are not changed + No Write Access
01: Reserved
00: No Read/Write Access to peripheral
Reset type: XRSn
1-0 CPUx_ACC R/W 3h Defines Access control definition for the CPUx as:
11: Full Access for both read and Write
10: Protected RD Access such that FIFOs, Clear on read registers
are not changed + No Write Access
01: Reserved
00: No Read/Write Access to peripheral
Reset type: XRSn

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3.16.7.2 ADCB_AC Register (Offset = 2h) [Reset = 3Fh]

ADCB_AC is shown in Figure 3-100 and described in Table 3-108.
Return to the Summary Table.
Based on control settings allows Full, Protected Read, No Access to peripheral from corresponding connected
master.
Figure 3-100. ADCB_AC Register
31 30 29 28 27 26 25 24
RESERVED
R-0-0h

23 22 21 20 19 18 17 16
RESERVED
R-0-0h

15 14 13 12 11 10 9 8
RESERVED
R-0-0h

7 6 5 4 3 2 1 0
RESERVED DMA1_ACC CLA1_ACC CPUx_ACC
R-0-0h R/W-3h R/W-3h R/W-3h

Table 3-108. ADCB_AC Register Field Descriptions

Bit Field Type Reset Description
31-6 RESERVED R-0 0h Reserved
5-4 DMA1_ACC R/W 3h Defines Access control definition for the DMA1 as:
11: Full Access for both read and Write
10: Protected RD Access such that FIFOs, Clear on read registers
are not changed + No Write Access
01: Reserved
00: No Read/Write Access to peripheral
Reset type: XRSn
3-2 CLA1_ACC R/W 3h Defines Access control definition for the CLA1 as:
11: Full Access for both read and Write
10: Protected RD Access such that FIFOs, Clear on read registers
are not changed + No Write Access
01: Reserved
00: No Read/Write Access to peripheral
Reset type: XRSn
1-0 CPUx_ACC R/W 3h Defines Access control definition for the CPUx as:
11: Full Access for both read and Write
10: Protected RD Access such that FIFOs, Clear on read registers
are not changed + No Write Access
01: Reserved
00: No Read/Write Access to peripheral
Reset type: XRSn

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3.16.7.3 ADCC_AC Register (Offset = 4h) [Reset = 3Fh]

ADCC_AC is shown in Figure 3-101 and described in Table 3-109.
Return to the Summary Table.
Based on control settings allows Full, Protected Read, No Access to peripheral from corresponding connected
master.
Figure 3-101. ADCC_AC Register
31 30 29 28 27 26 25 24
RESERVED
R-0-0h

23 22 21 20 19 18 17 16
RESERVED
R-0-0h

15 14 13 12 11 10 9 8
RESERVED
R-0-0h

7 6 5 4 3 2 1 0
RESERVED DMA1_ACC CLA1_ACC CPUx_ACC
R-0-0h R/W-3h R/W-3h R/W-3h

Table 3-109. ADCC_AC Register Field Descriptions

Bit Field Type Reset Description
31-6 RESERVED R-0 0h Reserved
5-4 DMA1_ACC R/W 3h Defines Access control definition for the DMA1 as:
11: Full Access for both read and Write
10: Protected RD Access such that FIFOs, Clear on read registers
are not changed + No Write Access
01: Reserved
00: No Read/Write Access to peripheral
Reset type: XRSn
3-2 CLA1_ACC R/W 3h Defines Access control definition for the CLA1 as:
11: Full Access for both read and Write
10: Protected RD Access such that FIFOs, Clear on read registers
are not changed + No Write Access
01: Reserved
00: No Read/Write Access to peripheral
Reset type: XRSn
1-0 CPUx_ACC R/W 3h Defines Access control definition for the CPUx as:
11: Full Access for both read and Write
10: Protected RD Access such that FIFOs, Clear on read registers
are not changed + No Write Access
01: Reserved
00: No Read/Write Access to peripheral
Reset type: XRSn

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3.16.7.4 ADCD_AC Register (Offset = 6h) [Reset = 3Fh]

ADCD_AC is shown in Figure 3-102 and described in Table 3-110.
Return to the Summary Table.
Based on control settings allows Full, Protected Read, No Access to peripheral from corresponding connected
master.
Figure 3-102. ADCD_AC Register
31 30 29 28 27 26 25 24
RESERVED
R-0-0h

23 22 21 20 19 18 17 16
RESERVED
R-0-0h

15 14 13 12 11 10 9 8
RESERVED
R-0-0h

7 6 5 4 3 2 1 0
RESERVED DMA1_ACC CLA1_ACC CPUx_ACC
R-0-0h R/W-3h R/W-3h R/W-3h

Table 3-110. ADCD_AC Register Field Descriptions

Bit Field Type Reset Description
31-6 RESERVED R-0 0h Reserved
5-4 DMA1_ACC R/W 3h Defines Access control definition for the DMA1 as:
11: Full Access for both read and Write
10: Protected RD Access such that FIFOs, Clear on read registers
are not changed + No Write Access
01: Reserved
00: No Read/Write Access to peripheral
Reset type: XRSn
3-2 CLA1_ACC R/W 3h Defines Access control definition for the CLA1 as:
11: Full Access for both read and Write
10: Protected RD Access such that FIFOs, Clear on read registers
are not changed + No Write Access
01: Reserved
00: No Read/Write Access to peripheral
Reset type: XRSn
1-0 CPUx_ACC R/W 3h Defines Access control definition for the CPUx as:
11: Full Access for both read and Write
10: Protected RD Access such that FIFOs, Clear on read registers
are not changed + No Write Access
01: Reserved
00: No Read/Write Access to peripheral
Reset type: XRSn

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3.16.7.5 CMPSS1_AC Register (Offset = 10h) [Reset = 3Fh]

CMPSS1_AC is shown in Figure 3-103 and described in Table 3-111.
Return to the Summary Table.
Based on control settings allows Full, Protected Read, No Access to peripheral from corresponding connected
master.
Figure 3-103. CMPSS1_AC Register
31 30 29 28 27 26 25 24
RESERVED
R-0-0h

23 22 21 20 19 18 17 16
RESERVED
R-0-0h

15 14 13 12 11 10 9 8
RESERVED
R-0-0h

7 6 5 4 3 2 1 0
RESERVED DMA1_ACC CLA1_ACC CPUx_ACC
R-0-0h R/W-3h R/W-3h R/W-3h

Table 3-111. CMPSS1_AC Register Field Descriptions

Bit Field Type Reset Description
31-6 RESERVED R-0 0h Reserved
5-4 DMA1_ACC R/W 3h Defines Access control definition for the DMA1 as:
11: Full Access for both read and Write
10: Protected RD Access such that FIFOs, Clear on read registers
are not changed + No Write Access
01: Reserved
00: No Read/Write Access to peripheral
Reset type: XRSn
3-2 CLA1_ACC R/W 3h Defines Access control definition for the CLA1 as:
11: Full Access for both read and Write
10: Protected RD Access such that FIFOs, Clear on read registers
are not changed + No Write Access
01: Reserved
00: No Read/Write Access to peripheral
Reset type: XRSn
1-0 CPUx_ACC R/W 3h Defines Access control definition for the CPUx as:
11: Full Access for both read and Write
10: Protected RD Access such that FIFOs, Clear on read registers
are not changed + No Write Access
01: Reserved
00: No Read/Write Access to peripheral
Reset type: XRSn

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3.16.7.6 CMPSS2_AC Register (Offset = 12h) [Reset = 3Fh]

CMPSS2_AC is shown in Figure 3-104 and described in Table 3-112.
Return to the Summary Table.
Based on control settings allows Full, Protected Read, No Access to peripheral from corresponding connected
master.
Figure 3-104. CMPSS2_AC Register
31 30 29 28 27 26 25 24
RESERVED
R-0-0h

23 22 21 20 19 18 17 16
RESERVED
R-0-0h

15 14 13 12 11 10 9 8
RESERVED
R-0-0h

7 6 5 4 3 2 1 0
RESERVED DMA1_ACC CLA1_ACC CPUx_ACC
R-0-0h R/W-3h R/W-3h R/W-3h

Table 3-112. CMPSS2_AC Register Field Descriptions

Bit Field Type Reset Description
31-6 RESERVED R-0 0h Reserved
5-4 DMA1_ACC R/W 3h Defines Access control definition for the DMA1 as:
11: Full Access for both read and Write
10: Protected RD Access such that FIFOs, Clear on read registers
are not changed + No Write Access
01: Reserved
00: No Read/Write Access to peripheral
Reset type: XRSn
3-2 CLA1_ACC R/W 3h Defines Access control definition for the CLA1 as:
11: Full Access for both read and Write
10: Protected RD Access such that FIFOs, Clear on read registers
are not changed + No Write Access
01: Reserved
00: No Read/Write Access to peripheral
Reset type: XRSn
1-0 CPUx_ACC R/W 3h Defines Access control definition for the CPUx as:
11: Full Access for both read and Write
10: Protected RD Access such that FIFOs, Clear on read registers
are not changed + No Write Access
01: Reserved
00: No Read/Write Access to peripheral
Reset type: XRSn

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3.16.7.7 CMPSS3_AC Register (Offset = 14h) [Reset = 3Fh]

CMPSS3_AC is shown in Figure 3-105 and described in Table 3-113.
Return to the Summary Table.
Based on control settings allows Full, Protected Read, No Access to peripheral from corresponding connected
master.
Figure 3-105. CMPSS3_AC Register
31 30 29 28 27 26 25 24
RESERVED
R-0-0h

23 22 21 20 19 18 17 16
RESERVED
R-0-0h

15 14 13 12 11 10 9 8
RESERVED
R-0-0h

7 6 5 4 3 2 1 0
RESERVED DMA1_ACC CLA1_ACC CPUx_ACC
R-0-0h R/W-3h R/W-3h R/W-3h

Table 3-113. CMPSS3_AC Register Field Descriptions

Bit Field Type Reset Description
31-6 RESERVED R-0 0h Reserved
5-4 DMA1_ACC R/W 3h Defines Access control definition for the DMA1 as:
11: Full Access for both read and Write
10: Protected RD Access such that FIFOs, Clear on read registers
are not changed + No Write Access
01: Reserved
00: No Read/Write Access to peripheral
Reset type: XRSn
3-2 CLA1_ACC R/W 3h Defines Access control definition for the CLA1 as:
11: Full Access for both read and Write
10: Protected RD Access such that FIFOs, Clear on read registers
are not changed + No Write Access
01: Reserved
00: No Read/Write Access to peripheral
Reset type: XRSn
1-0 CPUx_ACC R/W 3h Defines Access control definition for the CPUx as:
11: Full Access for both read and Write
10: Protected RD Access such that FIFOs, Clear on read registers
are not changed + No Write Access
01: Reserved
00: No Read/Write Access to peripheral
Reset type: XRSn

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3.16.7.8 CMPSS4_AC Register (Offset = 16h) [Reset = 3Fh]

CMPSS4_AC is shown in Figure 3-106 and described in Table 3-114.
Return to the Summary Table.
Based on control settings allows Full, Protected Read, No Access to peripheral from corresponding connected
master.
Figure 3-106. CMPSS4_AC Register
31 30 29 28 27 26 25 24
RESERVED
R-0-0h

23 22 21 20 19 18 17 16
RESERVED
R-0-0h

15 14 13 12 11 10 9 8
RESERVED
R-0-0h

7 6 5 4 3 2 1 0
RESERVED DMA1_ACC CLA1_ACC CPUx_ACC
R-0-0h R/W-3h R/W-3h R/W-3h

Table 3-114. CMPSS4_AC Register Field Descriptions

Bit Field Type Reset Description
31-6 RESERVED R-0 0h Reserved
5-4 DMA1_ACC R/W 3h Defines Access control definition for the DMA1 as:
11: Full Access for both read and Write
10: Protected RD Access such that FIFOs, Clear on read registers
are not changed + No Write Access
01: Reserved
00: No Read/Write Access to peripheral
Reset type: XRSn
3-2 CLA1_ACC R/W 3h Defines Access control definition for the CLA1 as:
11: Full Access for both read and Write
10: Protected RD Access such that FIFOs, Clear on read registers
are not changed + No Write Access
01: Reserved
00: No Read/Write Access to peripheral
Reset type: XRSn
1-0 CPUx_ACC R/W 3h Defines Access control definition for the CPUx as:
11: Full Access for both read and Write
10: Protected RD Access such that FIFOs, Clear on read registers
are not changed + No Write Access
01: Reserved
00: No Read/Write Access to peripheral
Reset type: XRSn

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3.16.7.9 CMPSS5_AC Register (Offset = 18h) [Reset = 3Fh]

CMPSS5_AC is shown in Figure 3-107 and described in Table 3-115.
Return to the Summary Table.
Based on control settings allows Full, Protected Read, No Access to peripheral from corresponding connected
master.
Figure 3-107. CMPSS5_AC Register
31 30 29 28 27 26 25 24
RESERVED
R-0-0h

23 22 21 20 19 18 17 16
RESERVED
R-0-0h

15 14 13 12 11 10 9 8
RESERVED
R-0-0h

7 6 5 4 3 2 1 0
RESERVED DMA1_ACC CLA1_ACC CPUx_ACC
R-0-0h R/W-3h R/W-3h R/W-3h

Table 3-115. CMPSS5_AC Register Field Descriptions

Bit Field Type Reset Description
31-6 RESERVED R-0 0h Reserved
5-4 DMA1_ACC R/W 3h Defines Access control definition for the DMA1 as:
11: Full Access for both read and Write
10: Protected RD Access such that FIFOs, Clear on read registers
are not changed + No Write Access
01: Reserved
00: No Read/Write Access to peripheral
Reset type: XRSn
3-2 CLA1_ACC R/W 3h Defines Access control definition for the CLA1 as:
11: Full Access for both read and Write
10: Protected RD Access such that FIFOs, Clear on read registers
are not changed + No Write Access
01: Reserved
00: No Read/Write Access to peripheral
Reset type: XRSn
1-0 CPUx_ACC R/W 3h Defines Access control definition for the CPUx as:
11: Full Access for both read and Write
10: Protected RD Access such that FIFOs, Clear on read registers
are not changed + No Write Access
01: Reserved
00: No Read/Write Access to peripheral
Reset type: XRSn

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3.16.7.10 CMPSS6_AC Register (Offset = 1Ah) [Reset = 3Fh]

CMPSS6_AC is shown in Figure 3-108 and described in Table 3-116.
Return to the Summary Table.
Based on control settings allows Full, Protected Read, No Access to peripheral from corresponding connected
master.
Figure 3-108. CMPSS6_AC Register
31 30 29 28 27 26 25 24
RESERVED
R-0-0h

23 22 21 20 19 18 17 16
RESERVED
R-0-0h

15 14 13 12 11 10 9 8
RESERVED
R-0-0h

7 6 5 4 3 2 1 0
RESERVED DMA1_ACC CLA1_ACC CPUx_ACC
R-0-0h R/W-3h R/W-3h R/W-3h

Table 3-116. CMPSS6_AC Register Field Descriptions

Bit Field Type Reset Description
31-6 RESERVED R-0 0h Reserved
5-4 DMA1_ACC R/W 3h Defines Access control definition for the DMA1 as:
11: Full Access for both read and Write
10: Protected RD Access such that FIFOs, Clear on read registers
are not changed + No Write Access
01: Reserved
00: No Read/Write Access to peripheral
Reset type: XRSn
3-2 CLA1_ACC R/W 3h Defines Access control definition for the CLA1 as:
11: Full Access for both read and Write
10: Protected RD Access such that FIFOs, Clear on read registers
are not changed + No Write Access
01: Reserved
00: No Read/Write Access to peripheral
Reset type: XRSn
1-0 CPUx_ACC R/W 3h Defines Access control definition for the CPUx as:
11: Full Access for both read and Write
10: Protected RD Access such that FIFOs, Clear on read registers
are not changed + No Write Access
01: Reserved
00: No Read/Write Access to peripheral
Reset type: XRSn

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3.16.7.11 CMPSS7_AC Register (Offset = 1Ch) [Reset = 3Fh]

CMPSS7_AC is shown in Figure 3-109 and described in Table 3-117.
Return to the Summary Table.
Based on control settings allows Full, Protected Read, No Access to peripheral from corresponding connected
master.
Figure 3-109. CMPSS7_AC Register
31 30 29 28 27 26 25 24
RESERVED
R-0-0h

23 22 21 20 19 18 17 16
RESERVED
R-0-0h

15 14 13 12 11 10 9 8
RESERVED
R-0-0h

7 6 5 4 3 2 1 0
RESERVED DMA1_ACC CLA1_ACC CPUx_ACC
R-0-0h R/W-3h R/W-3h R/W-3h

Table 3-117. CMPSS7_AC Register Field Descriptions

Bit Field Type Reset Description
31-6 RESERVED R-0 0h Reserved
5-4 DMA1_ACC R/W 3h Defines Access control definition for the DMA1 as:
11: Full Access for both read and Write
10: Protected RD Access such that FIFOs, Clear on read registers
are not changed + No Write Access
01: Reserved
00: No Read/Write Access to peripheral
Reset type: XRSn
3-2 CLA1_ACC R/W 3h Defines Access control definition for the CLA1 as:
11: Full Access for both read and Write
10: Protected RD Access such that FIFOs, Clear on read registers
are not changed + No Write Access
01: Reserved
00: No Read/Write Access to peripheral
Reset type: XRSn
1-0 CPUx_ACC R/W 3h Defines Access control definition for the CPUx as:
11: Full Access for both read and Write
10: Protected RD Access such that FIFOs, Clear on read registers
are not changed + No Write Access
01: Reserved
00: No Read/Write Access to peripheral
Reset type: XRSn

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3.16.7.12 CMPSS8_AC Register (Offset = 1Eh) [Reset = 3Fh]

CMPSS8_AC is shown in Figure 3-110 and described in Table 3-118.
Return to the Summary Table.
Based on control settings allows Full, Protected Read, No Access to peripheral from corresponding connected
master.
Figure 3-110. CMPSS8_AC Register
31 30 29 28 27 26 25 24
RESERVED
R-0-0h

23 22 21 20 19 18 17 16
RESERVED
R-0-0h

15 14 13 12 11 10 9 8
RESERVED
R-0-0h

7 6 5 4 3 2 1 0
RESERVED DMA1_ACC CLA1_ACC CPUx_ACC
R-0-0h R/W-3h R/W-3h R/W-3h

Table 3-118. CMPSS8_AC Register Field Descriptions

Bit Field Type Reset Description
31-6 RESERVED R-0 0h Reserved
5-4 DMA1_ACC R/W 3h Defines Access control definition for the DMA1 as:
11: Full Access for both read and Write
10: Protected RD Access such that FIFOs, Clear on read registers
are not changed + No Write Access
01: Reserved
00: No Read/Write Access to peripheral
Reset type: XRSn
3-2 CLA1_ACC R/W 3h Defines Access control definition for the CLA1 as:
11: Full Access for both read and Write
10: Protected RD Access such that FIFOs, Clear on read registers
are not changed + No Write Access
01: Reserved
00: No Read/Write Access to peripheral
Reset type: XRSn
1-0 CPUx_ACC R/W 3h Defines Access control definition for the CPUx as:
11: Full Access for both read and Write
10: Protected RD Access such that FIFOs, Clear on read registers
are not changed + No Write Access
01: Reserved
00: No Read/Write Access to peripheral
Reset type: XRSn

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3.16.7.13 DACA_AC Register (Offset = 28h) [Reset = 3Fh]

DACA_AC is shown in Figure 3-111 and described in Table 3-119.
Return to the Summary Table.
Based on control settings allows Full, Protected Read, No Access to peripheral from corresponding connected
master.
Figure 3-111. DACA_AC Register
31 30 29 28 27 26 25 24
RESERVED
R-0-0h

23 22 21 20 19 18 17 16
RESERVED
R-0-0h

15 14 13 12 11 10 9 8
RESERVED
R-0-0h

7 6 5 4 3 2 1 0
RESERVED DMA1_ACC CLA1_ACC CPUx_ACC
R-0-0h R/W-3h R/W-3h R/W-3h

Table 3-119. DACA_AC Register Field Descriptions

Bit Field Type Reset Description
31-6 RESERVED R-0 0h Reserved
5-4 DMA1_ACC R/W 3h Defines Access control definition for the DMA1 as:
11: Full Access for both read and Write
10: Protected RD Access such that FIFOs, Clear on read registers
are not changed + No Write Access
01: Reserved
00: No Read/Write Access to peripheral
Reset type: XRSn
3-2 CLA1_ACC R/W 3h Defines Access control definition for the CLA1 as:
11: Full Access for both read and Write
10: Protected RD Access such that FIFOs, Clear on read registers
are not changed + No Write Access
01: Reserved
00: No Read/Write Access to peripheral
Reset type: XRSn
1-0 CPUx_ACC R/W 3h Defines Access control definition for the CPUx as:
11: Full Access for both read and Write
10: Protected RD Access such that FIFOs, Clear on read registers
are not changed + No Write Access
01: Reserved
00: No Read/Write Access to peripheral
Reset type: XRSn

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3.16.7.14 DACB_AC Register (Offset = 2Ah) [Reset = 3Fh]

DACB_AC is shown in Figure 3-112 and described in Table 3-120.
Return to the Summary Table.
Based on control settings allows Full, Protected Read, No Access to peripheral from corresponding connected
master.
Figure 3-112. DACB_AC Register
31 30 29 28 27 26 25 24
RESERVED
R-0-0h

23 22 21 20 19 18 17 16
RESERVED
R-0-0h

15 14 13 12 11 10 9 8
RESERVED
R-0-0h

7 6 5 4 3 2 1 0
RESERVED DMA1_ACC CLA1_ACC CPUx_ACC
R-0-0h R/W-3h R/W-3h R/W-3h

Table 3-120. DACB_AC Register Field Descriptions

Bit Field Type Reset Description
31-6 RESERVED R-0 0h Reserved
5-4 DMA1_ACC R/W 3h Defines Access control definition for the DMA1 as:
11: Full Access for both read and Write
10: Protected RD Access such that FIFOs, Clear on read registers
are not changed + No Write Access
01: Reserved
00: No Read/Write Access to peripheral
Reset type: XRSn
3-2 CLA1_ACC R/W 3h Defines Access control definition for the CLA1 as:
11: Full Access for both read and Write
10: Protected RD Access such that FIFOs, Clear on read registers
are not changed + No Write Access
01: Reserved
00: No Read/Write Access to peripheral
Reset type: XRSn
1-0 CPUx_ACC R/W 3h Defines Access control definition for the CPUx as:
11: Full Access for both read and Write
10: Protected RD Access such that FIFOs, Clear on read registers
are not changed + No Write Access
01: Reserved
00: No Read/Write Access to peripheral
Reset type: XRSn

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3.16.7.15 DACC_AC Register (Offset = 2Ch) [Reset = 3Fh]

DACC_AC is shown in Figure 3-113 and described in Table 3-121.
Return to the Summary Table.
Based on control settings allows Full, Protected Read, No Access to peripheral from corresponding connected
master.
Figure 3-113. DACC_AC Register
31 30 29 28 27 26 25 24
RESERVED
R-0-0h

23 22 21 20 19 18 17 16
RESERVED
R-0-0h

15 14 13 12 11 10 9 8
RESERVED
R-0-0h

7 6 5 4 3 2 1 0
RESERVED DMA1_ACC CLA1_ACC CPUx_ACC
R-0-0h R/W-3h R/W-3h R/W-3h

Table 3-121. DACC_AC Register Field Descriptions

Bit Field Type Reset Description
31-6 RESERVED R-0 0h Reserved
5-4 DMA1_ACC R/W 3h Defines Access control definition for the DMA1 as:
11: Full Access for both read and Write
10: Protected RD Access such that FIFOs, Clear on read registers
are not changed + No Write Access
01: Reserved
00: No Read/Write Access to peripheral
Reset type: XRSn
3-2 CLA1_ACC R/W 3h Defines Access control definition for the CLA1 as:
11: Full Access for both read and Write
10: Protected RD Access such that FIFOs, Clear on read registers
are not changed + No Write Access
01: Reserved
00: No Read/Write Access to peripheral
Reset type: XRSn
1-0 CPUx_ACC R/W 3h Defines Access control definition for the CPUx as:
11: Full Access for both read and Write
10: Protected RD Access such that FIFOs, Clear on read registers
are not changed + No Write Access
01: Reserved
00: No Read/Write Access to peripheral
Reset type: XRSn

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3.16.7.16 EPWM1_AC Register (Offset = 48h) [Reset = 3Fh]

EPWM1_AC is shown in Figure 3-114 and described in Table 3-122.
Return to the Summary Table.
Based on control settings allows Full, Protected Read, No Access to peripheral from corresponding connected
master.
Figure 3-114. EPWM1_AC Register
31 30 29 28 27 26 25 24
RESERVED
R-0-0h

23 22 21 20 19 18 17 16
RESERVED
R-0-0h

15 14 13 12 11 10 9 8
RESERVED
R-0-0h

7 6 5 4 3 2 1 0
RESERVED DMA1_ACC CLA1_ACC CPUx_ACC
R-0-0h R/W-3h R/W-3h R/W-3h

Table 3-122. EPWM1_AC Register Field Descriptions

Bit Field Type Reset Description
31-6 RESERVED R-0 0h Reserved
5-4 DMA1_ACC R/W 3h Defines Access control definition for the DMA1 as:
11: Full Access for both read and Write
10: Protected RD Access such that FIFOs, Clear on read registers
are not changed + No Write Access
01: Reserved
00: No Read/Write Access to peripheral
Reset type: XRSn
3-2 CLA1_ACC R/W 3h Defines Access control definition for the CLA1 as:
11: Full Access for both read and Write
10: Protected RD Access such that FIFOs, Clear on read registers
are not changed + No Write Access
01: Reserved
00: No Read/Write Access to peripheral
Reset type: XRSn
1-0 CPUx_ACC R/W 3h Defines Access control definition for the CPUx as:
11: Full Access for both read and Write
10: Protected RD Access such that FIFOs, Clear on read registers
are not changed + No Write Access
01: Reserved
00: No Read/Write Access to peripheral
Reset type: XRSn

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3.16.7.17 EPWM2_AC Register (Offset = 4Ah) [Reset = 3Fh]

EPWM2_AC is shown in Figure 3-115 and described in Table 3-123.
Return to the Summary Table.
Based on control settings allows Full, Protected Read, No Access to peripheral from corresponding connected
master.
Figure 3-115. EPWM2_AC Register
31 30 29 28 27 26 25 24
RESERVED
R-0-0h

23 22 21 20 19 18 17 16
RESERVED
R-0-0h

15 14 13 12 11 10 9 8
RESERVED
R-0-0h

7 6 5 4 3 2 1 0
RESERVED DMA1_ACC CLA1_ACC CPUx_ACC
R-0-0h R/W-3h R/W-3h R/W-3h

Table 3-123. EPWM2_AC Register Field Descriptions

Bit Field Type Reset Description
31-6 RESERVED R-0 0h Reserved
5-4 DMA1_ACC R/W 3h Defines Access control definition for the DMA1 as:
11: Full Access for both read and Write
10: Protected RD Access such that FIFOs, Clear on read registers
are not changed + No Write Access
01: Reserved
00: No Read/Write Access to peripheral
Reset type: XRSn
3-2 CLA1_ACC R/W 3h Defines Access control definition for the CLA1 as:
11: Full Access for both read and Write
10: Protected RD Access such that FIFOs, Clear on read registers
are not changed + No Write Access
01: Reserved
00: No Read/Write Access to peripheral
Reset type: XRSn
1-0 CPUx_ACC R/W 3h Defines Access control definition for the CPUx as:
11: Full Access for both read and Write
10: Protected RD Access such that FIFOs, Clear on read registers
are not changed + No Write Access
01: Reserved
00: No Read/Write Access to peripheral
Reset type: XRSn

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3.16.7.18 EPWM3_AC Register (Offset = 4Ch) [Reset = 3Fh]

EPWM3_AC is shown in Figure 3-116 and described in Table 3-124.
Return to the Summary Table.
Based on control settings allows Full, Protected Read, No Access to peripheral from corresponding connected
master.
Figure 3-116. EPWM3_AC Register
31 30 29 28 27 26 25 24
RESERVED
R-0-0h

23 22 21 20 19 18 17 16
RESERVED
R-0-0h

15 14 13 12 11 10 9 8
RESERVED
R-0-0h

7 6 5 4 3 2 1 0
RESERVED DMA1_ACC CLA1_ACC CPUx_ACC
R-0-0h R/W-3h R/W-3h R/W-3h

Table 3-124. EPWM3_AC Register Field Descriptions

Bit Field Type Reset Description
31-6 RESERVED R-0 0h Reserved
5-4 DMA1_ACC R/W 3h Defines Access control definition for the DMA1 as:
11: Full Access for both read and Write
10: Protected RD Access such that FIFOs, Clear on read registers
are not changed + No Write Access
01: Reserved
00: No Read/Write Access to peripheral
Reset type: XRSn
3-2 CLA1_ACC R/W 3h Defines Access control definition for the CLA1 as:
11: Full Access for both read and Write
10: Protected RD Access such that FIFOs, Clear on read registers
are not changed + No Write Access
01: Reserved
00: No Read/Write Access to peripheral
Reset type: XRSn
1-0 CPUx_ACC R/W 3h Defines Access control definition for the CPUx as:
11: Full Access for both read and Write
10: Protected RD Access such that FIFOs, Clear on read registers
are not changed + No Write Access
01: Reserved
00: No Read/Write Access to peripheral
Reset type: XRSn

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3.16.7.19 EPWM4_AC Register (Offset = 4Eh) [Reset = 3Fh]

EPWM4_AC is shown in Figure 3-117 and described in Table 3-125.
Return to the Summary Table.
Based on control settings allows Full, Protected Read, No Access to peripheral from corresponding connected
master.
Figure 3-117. EPWM4_AC Register
31 30 29 28 27 26 25 24
RESERVED
R-0-0h

23 22 21 20 19 18 17 16
RESERVED
R-0-0h

15 14 13 12 11 10 9 8
RESERVED
R-0-0h

7 6 5 4 3 2 1 0
RESERVED DMA1_ACC CLA1_ACC CPUx_ACC
R-0-0h R/W-3h R/W-3h R/W-3h

Table 3-125. EPWM4_AC Register Field Descriptions

Bit Field Type Reset Description
31-6 RESERVED R-0 0h Reserved
5-4 DMA1_ACC R/W 3h Defines Access control definition for the DMA1 as:
11: Full Access for both read and Write
10: Protected RD Access such that FIFOs, Clear on read registers
are not changed + No Write Access
01: Reserved
00: No Read/Write Access to peripheral
Reset type: XRSn
3-2 CLA1_ACC R/W 3h Defines Access control definition for the CLA1 as:
11: Full Access for both read and Write
10: Protected RD Access such that FIFOs, Clear on read registers
are not changed + No Write Access
01: Reserved
00: No Read/Write Access to peripheral
Reset type: XRSn
1-0 CPUx_ACC R/W 3h Defines Access control definition for the CPUx as:
11: Full Access for both read and Write
10: Protected RD Access such that FIFOs, Clear on read registers
are not changed + No Write Access
01: Reserved
00: No Read/Write Access to peripheral
Reset type: XRSn

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3.16.7.20 EPWM5_AC Register (Offset = 50h) [Reset = 3Fh]

EPWM5_AC is shown in Figure 3-118 and described in Table 3-126.
Return to the Summary Table.
Based on control settings allows Full, Protected Read, No Access to peripheral from corresponding connected
master.
Figure 3-118. EPWM5_AC Register
31 30 29 28 27 26 25 24
RESERVED
R-0-0h

23 22 21 20 19 18 17 16
RESERVED
R-0-0h

15 14 13 12 11 10 9 8
RESERVED
R-0-0h

7 6 5 4 3 2 1 0
RESERVED DMA1_ACC CLA1_ACC CPUx_ACC
R-0-0h R/W-3h R/W-3h R/W-3h

Table 3-126. EPWM5_AC Register Field Descriptions

Bit Field Type Reset Description
31-6 RESERVED R-0 0h Reserved
5-4 DMA1_ACC R/W 3h Defines Access control definition for the DMA1 as:
11: Full Access for both read and Write
10: Protected RD Access such that FIFOs, Clear on read registers
are not changed + No Write Access
01: Reserved
00: No Read/Write Access to peripheral
Reset type: XRSn
3-2 CLA1_ACC R/W 3h Defines Access control definition for the CLA1 as:
11: Full Access for both read and Write
10: Protected RD Access such that FIFOs, Clear on read registers
are not changed + No Write Access
01: Reserved
00: No Read/Write Access to peripheral
Reset type: XRSn
1-0 CPUx_ACC R/W 3h Defines Access control definition for the CPUx as:
11: Full Access for both read and Write
10: Protected RD Access such that FIFOs, Clear on read registers
are not changed + No Write Access
01: Reserved
00: No Read/Write Access to peripheral
Reset type: XRSn

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3.16.7.21 EPWM6_AC Register (Offset = 52h) [Reset = 3Fh]

EPWM6_AC is shown in Figure 3-119 and described in Table 3-127.
Return to the Summary Table.
Based on control settings allows Full, Protected Read, No Access to peripheral from corresponding connected
master.
Figure 3-119. EPWM6_AC Register
31 30 29 28 27 26 25 24
RESERVED
R-0-0h

23 22 21 20 19 18 17 16
RESERVED
R-0-0h

15 14 13 12 11 10 9 8
RESERVED
R-0-0h

7 6 5 4 3 2 1 0
RESERVED DMA1_ACC CLA1_ACC CPUx_ACC
R-0-0h R/W-3h R/W-3h R/W-3h

Table 3-127. EPWM6_AC Register Field Descriptions

Bit Field Type Reset Description
31-6 RESERVED R-0 0h Reserved
5-4 DMA1_ACC R/W 3h Defines Access control definition for the DMA1 as:
11: Full Access for both read and Write
10: Protected RD Access such that FIFOs, Clear on read registers
are not changed + No Write Access
01: Reserved
00: No Read/Write Access to peripheral
Reset type: XRSn
3-2 CLA1_ACC R/W 3h Defines Access control definition for the CLA1 as:
11: Full Access for both read and Write
10: Protected RD Access such that FIFOs, Clear on read registers
are not changed + No Write Access
01: Reserved
00: No Read/Write Access to peripheral
Reset type: XRSn
1-0 CPUx_ACC R/W 3h Defines Access control definition for the CPUx as:
11: Full Access for both read and Write
10: Protected RD Access such that FIFOs, Clear on read registers
are not changed + No Write Access
01: Reserved
00: No Read/Write Access to peripheral
Reset type: XRSn

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3.16.7.22 EPWM7_AC Register (Offset = 54h) [Reset = 3Fh]

EPWM7_AC is shown in Figure 3-120 and described in Table 3-128.
Return to the Summary Table.
Based on control settings allows Full, Protected Read, No Access to peripheral from corresponding connected
master.
Figure 3-120. EPWM7_AC Register
31 30 29 28 27 26 25 24
RESERVED
R-0-0h

23 22 21 20 19 18 17 16
RESERVED
R-0-0h

15 14 13 12 11 10 9 8
RESERVED
R-0-0h

7 6 5 4 3 2 1 0
RESERVED DMA1_ACC CLA1_ACC CPUx_ACC
R-0-0h R/W-3h R/W-3h R/W-3h

Table 3-128. EPWM7_AC Register Field Descriptions

Bit Field Type Reset Description
31-6 RESERVED R-0 0h Reserved
5-4 DMA1_ACC R/W 3h Defines Access control definition for the DMA1 as:
11: Full Access for both read and Write
10: Protected RD Access such that FIFOs, Clear on read registers
are not changed + No Write Access
01: Reserved
00: No Read/Write Access to peripheral
Reset type: XRSn
3-2 CLA1_ACC R/W 3h Defines Access control definition for the CLA1 as:
11: Full Access for both read and Write
10: Protected RD Access such that FIFOs, Clear on read registers
are not changed + No Write Access
01: Reserved
00: No Read/Write Access to peripheral
Reset type: XRSn
1-0 CPUx_ACC R/W 3h Defines Access control definition for the CPUx as:
11: Full Access for both read and Write
10: Protected RD Access such that FIFOs, Clear on read registers
are not changed + No Write Access
01: Reserved
00: No Read/Write Access to peripheral
Reset type: XRSn

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3.16.7.23 EPWM8_AC Register (Offset = 56h) [Reset = 3Fh]

EPWM8_AC is shown in Figure 3-121 and described in Table 3-129.
Return to the Summary Table.
Based on control settings allows Full, Protected Read, No Access to peripheral from corresponding connected
master.
Figure 3-121. EPWM8_AC Register
31 30 29 28 27 26 25 24
RESERVED
R-0-0h

23 22 21 20 19 18 17 16
RESERVED
R-0-0h

15 14 13 12 11 10 9 8
RESERVED
R-0-0h

7 6 5 4 3 2 1 0
RESERVED DMA1_ACC CLA1_ACC CPUx_ACC
R-0-0h R/W-3h R/W-3h R/W-3h

Table 3-129. EPWM8_AC Register Field Descriptions

Bit Field Type Reset Description
31-6 RESERVED R-0 0h Reserved
5-4 DMA1_ACC R/W 3h Defines Access control definition for the DMA1 as:
11: Full Access for both read and Write
10: Protected RD Access such that FIFOs, Clear on read registers
are not changed + No Write Access
01: Reserved
00: No Read/Write Access to peripheral
Reset type: XRSn
3-2 CLA1_ACC R/W 3h Defines Access control definition for the CLA1 as:
11: Full Access for both read and Write
10: Protected RD Access such that FIFOs, Clear on read registers
are not changed + No Write Access
01: Reserved
00: No Read/Write Access to peripheral
Reset type: XRSn
1-0 CPUx_ACC R/W 3h Defines Access control definition for the CPUx as:
11: Full Access for both read and Write
10: Protected RD Access such that FIFOs, Clear on read registers
are not changed + No Write Access
01: Reserved
00: No Read/Write Access to peripheral
Reset type: XRSn

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3.16.7.24 EPWM9_AC Register (Offset = 58h) [Reset = 3Fh]

EPWM9_AC is shown in Figure 3-122 and described in Table 3-130.
Return to the Summary Table.
Based on control settings allows Full, Protected Read, No Access to peripheral from corresponding connected
master.
Figure 3-122. EPWM9_AC Register
31 30 29 28 27 26 25 24
RESERVED
R-0-0h

23 22 21 20 19 18 17 16
RESERVED
R-0-0h

15 14 13 12 11 10 9 8
RESERVED
R-0-0h

7 6 5 4 3 2 1 0
RESERVED DMA1_ACC CLA1_ACC CPUx_ACC
R-0-0h R/W-3h R/W-3h R/W-3h

Table 3-130. EPWM9_AC Register Field Descriptions

Bit Field Type Reset Description
31-6 RESERVED R-0 0h Reserved
5-4 DMA1_ACC R/W 3h Defines Access control definition for the DMA1 as:
11: Full Access for both read and Write
10: Protected RD Access such that FIFOs, Clear on read registers
are not changed + No Write Access
01: Reserved
00: No Read/Write Access to peripheral
Reset type: XRSn
3-2 CLA1_ACC R/W 3h Defines Access control definition for the CLA1 as:
11: Full Access for both read and Write
10: Protected RD Access such that FIFOs, Clear on read registers
are not changed + No Write Access
01: Reserved
00: No Read/Write Access to peripheral
Reset type: XRSn
1-0 CPUx_ACC R/W 3h Defines Access control definition for the CPUx as:
11: Full Access for both read and Write
10: Protected RD Access such that FIFOs, Clear on read registers
are not changed + No Write Access
01: Reserved
00: No Read/Write Access to peripheral
Reset type: XRSn

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3.16.7.25 EPWM10_AC Register (Offset = 5Ah) [Reset = 3Fh]

EPWM10_AC is shown in Figure 3-123 and described in Table 3-131.
Return to the Summary Table.
Based on control settings allows Full, Protected Read, No Access to peripheral from corresponding connected
master.
Figure 3-123. EPWM10_AC Register
31 30 29 28 27 26 25 24
RESERVED
R-0-0h

23 22 21 20 19 18 17 16
RESERVED
R-0-0h

15 14 13 12 11 10 9 8
RESERVED
R-0-0h

7 6 5 4 3 2 1 0
RESERVED DMA1_ACC CLA1_ACC CPUx_ACC
R-0-0h R/W-3h R/W-3h R/W-3h

Table 3-131. EPWM10_AC Register Field Descriptions

Bit Field Type Reset Description
31-6 RESERVED R-0 0h Reserved
5-4 DMA1_ACC R/W 3h Defines Access control definition for the DMA1 as:
11: Full Access for both read and Write
10: Protected RD Access such that FIFOs, Clear on read registers
are not changed + No Write Access
01: Reserved
00: No Read/Write Access to peripheral
Reset type: XRSn
3-2 CLA1_ACC R/W 3h Defines Access control definition for the CLA1 as:
11: Full Access for both read and Write
10: Protected RD Access such that FIFOs, Clear on read registers
are not changed + No Write Access
01: Reserved
00: No Read/Write Access to peripheral
Reset type: XRSn
1-0 CPUx_ACC R/W 3h Defines Access control definition for the CPUx as:
11: Full Access for both read and Write
10: Protected RD Access such that FIFOs, Clear on read registers
are not changed + No Write Access
01: Reserved
00: No Read/Write Access to peripheral
Reset type: XRSn

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3.16.7.26 EPWM11_AC Register (Offset = 5Ch) [Reset = 3Fh]

EPWM11_AC is shown in Figure 3-124 and described in Table 3-132.
Return to the Summary Table.
Based on control settings allows Full, Protected Read, No Access to peripheral from corresponding connected
master.
Figure 3-124. EPWM11_AC Register
31 30 29 28 27 26 25 24
RESERVED
R-0-0h

23 22 21 20 19 18 17 16
RESERVED
R-0-0h

15 14 13 12 11 10 9 8
RESERVED
R-0-0h

7 6 5 4 3 2 1 0
RESERVED DMA1_ACC CLA1_ACC CPUx_ACC
R-0-0h R/W-3h R/W-3h R/W-3h

Table 3-132. EPWM11_AC Register Field Descriptions

Bit Field Type Reset Description
31-6 RESERVED R-0 0h Reserved
5-4 DMA1_ACC R/W 3h Defines Access control definition for the DMA1 as:
11: Full Access for both read and Write
10: Protected RD Access such that FIFOs, Clear on read registers
are not changed + No Write Access
01: Reserved
00: No Read/Write Access to peripheral
Reset type: XRSn
3-2 CLA1_ACC R/W 3h Defines Access control definition for the CLA1 as:
11: Full Access for both read and Write
10: Protected RD Access such that FIFOs, Clear on read registers
are not changed + No Write Access
01: Reserved
00: No Read/Write Access to peripheral
Reset type: XRSn
1-0 CPUx_ACC R/W 3h Defines Access control definition for the CPUx as:
11: Full Access for both read and Write
10: Protected RD Access such that FIFOs, Clear on read registers
are not changed + No Write Access
01: Reserved
00: No Read/Write Access to peripheral
Reset type: XRSn

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3.16.7.27 EPWM12_AC Register (Offset = 5Eh) [Reset = 3Fh]

EPWM12_AC is shown in Figure 3-125 and described in Table 3-133.
Return to the Summary Table.
Based on control settings allows Full, Protected Read, No Access to peripheral from corresponding connected
master.
Figure 3-125. EPWM12_AC Register
31 30 29 28 27 26 25 24
RESERVED
R-0-0h

23 22 21 20 19 18 17 16
RESERVED
R-0-0h

15 14 13 12 11 10 9 8
RESERVED
R-0-0h

7 6 5 4 3 2 1 0
RESERVED DMA1_ACC CLA1_ACC CPUx_ACC
R-0-0h R/W-3h R/W-3h R/W-3h

Table 3-133. EPWM12_AC Register Field Descriptions

Bit Field Type Reset Description
31-6 RESERVED R-0 0h Reserved
5-4 DMA1_ACC R/W 3h Defines Access control definition for the DMA1 as:
11: Full Access for both read and Write
10: Protected RD Access such that FIFOs, Clear on read registers
are not changed + No Write Access
01: Reserved
00: No Read/Write Access to peripheral
Reset type: XRSn
3-2 CLA1_ACC R/W 3h Defines Access control definition for the CLA1 as:
11: Full Access for both read and Write
10: Protected RD Access such that FIFOs, Clear on read registers
are not changed + No Write Access
01: Reserved
00: No Read/Write Access to peripheral
Reset type: XRSn
1-0 CPUx_ACC R/W 3h Defines Access control definition for the CPUx as:
11: Full Access for both read and Write
10: Protected RD Access such that FIFOs, Clear on read registers
are not changed + No Write Access
01: Reserved
00: No Read/Write Access to peripheral
Reset type: XRSn

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3.16.7.28 EPWM13_AC Register (Offset = 60h) [Reset = 3Fh]

EPWM13_AC is shown in Figure 3-126 and described in Table 3-134.
Return to the Summary Table.
Based on control settings allows Full, Protected Read, No Access to peripheral from corresponding connected
master.
Figure 3-126. EPWM13_AC Register
31 30 29 28 27 26 25 24
RESERVED
R-0-0h

23 22 21 20 19 18 17 16
RESERVED
R-0-0h

15 14 13 12 11 10 9 8
RESERVED
R-0-0h

7 6 5 4 3 2 1 0
RESERVED DMA1_ACC CLA1_ACC CPUx_ACC
R-0-0h R/W-3h R/W-3h R/W-3h

Table 3-134. EPWM13_AC Register Field Descriptions

Bit Field Type Reset Description
31-6 RESERVED R-0 0h Reserved
5-4 DMA1_ACC R/W 3h Defines Access control definition for the DMA1 as:
11: Full Access for both read and Write
10: Protected RD Access such that FIFOs, Clear on read registers
are not changed + No Write Access
01: Reserved
00: No Read/Write Access to peripheral
Reset type: XRSn
3-2 CLA1_ACC R/W 3h Defines Access control definition for the CLA1 as:
11: Full Access for both read and Write
10: Protected RD Access such that FIFOs, Clear on read registers
are not changed + No Write Access
01: Reserved
00: No Read/Write Access to peripheral
Reset type: XRSn
1-0 CPUx_ACC R/W 3h Defines Access control definition for the CPUx as:
11: Full Access for both read and Write
10: Protected RD Access such that FIFOs, Clear on read registers
are not changed + No Write Access
01: Reserved
00: No Read/Write Access to peripheral
Reset type: XRSn

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3.16.7.29 EPWM14_AC Register (Offset = 62h) [Reset = 3Fh]

EPWM14_AC is shown in Figure 3-127 and described in Table 3-135.
Return to the Summary Table.
Based on control settings allows Full, Protected Read, No Access to peripheral from corresponding connected
master.
Figure 3-127. EPWM14_AC Register
31 30 29 28 27 26 25 24
RESERVED
R-0-0h

23 22 21 20 19 18 17 16
RESERVED
R-0-0h

15 14 13 12 11 10 9 8
RESERVED
R-0-0h

7 6 5 4 3 2 1 0
RESERVED DMA1_ACC CLA1_ACC CPUx_ACC
R-0-0h R/W-3h R/W-3h R/W-3h

Table 3-135. EPWM14_AC Register Field Descriptions

Bit Field Type Reset Description
31-6 RESERVED R-0 0h Reserved
5-4 DMA1_ACC R/W 3h Defines Access control definition for the DMA1 as:
11: Full Access for both read and Write
10: Protected RD Access such that FIFOs, Clear on read registers
are not changed + No Write Access
01: Reserved
00: No Read/Write Access to peripheral
Reset type: XRSn
3-2 CLA1_ACC R/W 3h Defines Access control definition for the CLA1 as:
11: Full Access for both read and Write
10: Protected RD Access such that FIFOs, Clear on read registers
are not changed + No Write Access
01: Reserved
00: No Read/Write Access to peripheral
Reset type: XRSn
1-0 CPUx_ACC R/W 3h Defines Access control definition for the CPUx as:
11: Full Access for both read and Write
10: Protected RD Access such that FIFOs, Clear on read registers
are not changed + No Write Access
01: Reserved
00: No Read/Write Access to peripheral
Reset type: XRSn

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3.16.7.30 EPWM15_AC Register (Offset = 64h) [Reset = 3Fh]

EPWM15_AC is shown in Figure 3-128 and described in Table 3-136.
Return to the Summary Table.
Based on control settings allows Full, Protected Read, No Access to peripheral from corresponding connected
master.
Figure 3-128. EPWM15_AC Register
31 30 29 28 27 26 25 24
RESERVED
R-0-0h

23 22 21 20 19 18 17 16
RESERVED
R-0-0h

15 14 13 12 11 10 9 8
RESERVED
R-0-0h

7 6 5 4 3 2 1 0
RESERVED DMA1_ACC CLA1_ACC CPUx_ACC
R-0-0h R/W-3h R/W-3h R/W-3h

Table 3-136. EPWM15_AC Register Field Descriptions

Bit Field Type Reset Description
31-6 RESERVED R-0 0h Reserved
5-4 DMA1_ACC R/W 3h Defines Access control definition for the DMA1 as:
11: Full Access for both read and Write
10: Protected RD Access such that FIFOs, Clear on read registers
are not changed + No Write Access
01: Reserved
00: No Read/Write Access to peripheral
Reset type: XRSn
3-2 CLA1_ACC R/W 3h Defines Access control definition for the CLA1 as:
11: Full Access for both read and Write
10: Protected RD Access such that FIFOs, Clear on read registers
are not changed + No Write Access
01: Reserved
00: No Read/Write Access to peripheral
Reset type: XRSn
1-0 CPUx_ACC R/W 3h Defines Access control definition for the CPUx as:
11: Full Access for both read and Write
10: Protected RD Access such that FIFOs, Clear on read registers
are not changed + No Write Access
01: Reserved
00: No Read/Write Access to peripheral
Reset type: XRSn

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3.16.7.31 EPWM16_AC Register (Offset = 66h) [Reset = 3Fh]

EPWM16_AC is shown in Figure 3-129 and described in Table 3-137.
Return to the Summary Table.
Based on control settings allows Full, Protected Read, No Access to peripheral from corresponding connected
master.
Figure 3-129. EPWM16_AC Register
31 30 29 28 27 26 25 24
RESERVED
R-0-0h

23 22 21 20 19 18 17 16
RESERVED
R-0-0h

15 14 13 12 11 10 9 8
RESERVED
R-0-0h

7 6 5 4 3 2 1 0
RESERVED DMA1_ACC CLA1_ACC CPUx_ACC
R-0-0h R/W-3h R/W-3h R/W-3h

Table 3-137. EPWM16_AC Register Field Descriptions

Bit Field Type Reset Description
31-6 RESERVED R-0 0h Reserved
5-4 DMA1_ACC R/W 3h Defines Access control definition for the DMA1 as:
11: Full Access for both read and Write
10: Protected RD Access such that FIFOs, Clear on read registers
are not changed + No Write Access
01: Reserved
00: No Read/Write Access to peripheral
Reset type: XRSn
3-2 CLA1_ACC R/W 3h Defines Access control definition for the CLA1 as:
11: Full Access for both read and Write
10: Protected RD Access such that FIFOs, Clear on read registers
are not changed + No Write Access
01: Reserved
00: No Read/Write Access to peripheral
Reset type: XRSn
1-0 CPUx_ACC R/W 3h Defines Access control definition for the CPUx as:
11: Full Access for both read and Write
10: Protected RD Access such that FIFOs, Clear on read registers
are not changed + No Write Access
01: Reserved
00: No Read/Write Access to peripheral
Reset type: XRSn

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3.16.7.32 EQEP1_AC Register (Offset = 70h) [Reset = 3Fh]

EQEP1_AC is shown in Figure 3-130 and described in Table 3-138.
Return to the Summary Table.
Based on control settings allows Full, Protected Read, No Access to peripheral from corresponding connected
master.
Figure 3-130. EQEP1_AC Register
31 30 29 28 27 26 25 24
RESERVED
R-0-0h

23 22 21 20 19 18 17 16
RESERVED
R-0-0h

15 14 13 12 11 10 9 8
RESERVED
R-0-0h

7 6 5 4 3 2 1 0
RESERVED DMA1_ACC CLA1_ACC CPUx_ACC
R-0-0h R/W-3h R/W-3h R/W-3h

Table 3-138. EQEP1_AC Register Field Descriptions

Bit Field Type Reset Description
31-6 RESERVED R-0 0h Reserved
5-4 DMA1_ACC R/W 3h Defines Access control definition for the DMA1 as:
11: Full Access for both read and Write
10: Protected RD Access such that FIFOs, Clear on read registers
are not changed + No Write Access
01: Reserved
00: No Read/Write Access to peripheral
Reset type: XRSn
3-2 CLA1_ACC R/W 3h Defines Access control definition for the CLA1 as:
11: Full Access for both read and Write
10: Protected RD Access such that FIFOs, Clear on read registers
are not changed + No Write Access
01: Reserved
00: No Read/Write Access to peripheral
Reset type: XRSn
1-0 CPUx_ACC R/W 3h Defines Access control definition for the CPUx as:
11: Full Access for both read and Write
10: Protected RD Access such that FIFOs, Clear on read registers
are not changed + No Write Access
01: Reserved
00: No Read/Write Access to peripheral
Reset type: XRSn

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3.16.7.33 EQEP2_AC Register (Offset = 72h) [Reset = 3Fh]

EQEP2_AC is shown in Figure 3-131 and described in Table 3-139.
Return to the Summary Table.
Based on control settings allows Full, Protected Read, No Access to peripheral from corresponding connected
master.
Figure 3-131. EQEP2_AC Register
31 30 29 28 27 26 25 24
RESERVED
R-0-0h

23 22 21 20 19 18 17 16
RESERVED
R-0-0h

15 14 13 12 11 10 9 8
RESERVED
R-0-0h

7 6 5 4 3 2 1 0
RESERVED DMA1_ACC CLA1_ACC CPUx_ACC
R-0-0h R/W-3h R/W-3h R/W-3h

Table 3-139. EQEP2_AC Register Field Descriptions

Bit Field Type Reset Description
31-6 RESERVED R-0 0h Reserved
5-4 DMA1_ACC R/W 3h Defines Access control definition for the DMA1 as:
11: Full Access for both read and Write
10: Protected RD Access such that FIFOs, Clear on read registers
are not changed + No Write Access
01: Reserved
00: No Read/Write Access to peripheral
Reset type: XRSn
3-2 CLA1_ACC R/W 3h Defines Access control definition for the CLA1 as:
11: Full Access for both read and Write
10: Protected RD Access such that FIFOs, Clear on read registers
are not changed + No Write Access
01: Reserved
00: No Read/Write Access to peripheral
Reset type: XRSn
1-0 CPUx_ACC R/W 3h Defines Access control definition for the CPUx as:
11: Full Access for both read and Write
10: Protected RD Access such that FIFOs, Clear on read registers
are not changed + No Write Access
01: Reserved
00: No Read/Write Access to peripheral
Reset type: XRSn

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3.16.7.34 EQEP3_AC Register (Offset = 74h) [Reset = 3Fh]

EQEP3_AC is shown in Figure 3-132 and described in Table 3-140.
Return to the Summary Table.
Based on control settings allows Full, Protected Read, No Access to peripheral from corresponding connected
master.
Figure 3-132. EQEP3_AC Register
31 30 29 28 27 26 25 24
RESERVED
R-0-0h

23 22 21 20 19 18 17 16
RESERVED
R-0-0h

15 14 13 12 11 10 9 8
RESERVED
R-0-0h

7 6 5 4 3 2 1 0
RESERVED DMA1_ACC CLA1_ACC CPUx_ACC
R-0-0h R/W-3h R/W-3h R/W-3h

Table 3-140. EQEP3_AC Register Field Descriptions

Bit Field Type Reset Description
31-6 RESERVED R-0 0h Reserved
5-4 DMA1_ACC R/W 3h Defines Access control definition for the DMA1 as:
11: Full Access for both read and Write
10: Protected RD Access such that FIFOs, Clear on read registers
are not changed + No Write Access
01: Reserved
00: No Read/Write Access to peripheral
Reset type: XRSn
3-2 CLA1_ACC R/W 3h Defines Access control definition for the CLA1 as:
11: Full Access for both read and Write
10: Protected RD Access such that FIFOs, Clear on read registers
are not changed + No Write Access
01: Reserved
00: No Read/Write Access to peripheral
Reset type: XRSn
1-0 CPUx_ACC R/W 3h Defines Access control definition for the CPUx as:
11: Full Access for both read and Write
10: Protected RD Access such that FIFOs, Clear on read registers
are not changed + No Write Access
01: Reserved
00: No Read/Write Access to peripheral
Reset type: XRSn

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3.16.7.35 ECAP1_AC Register (Offset = 80h) [Reset = 3Fh]

ECAP1_AC is shown in Figure 3-133 and described in Table 3-141.
Return to the Summary Table.
Based on control settings allows Full, Protected Read, No Access to peripheral from corresponding connected
master.
Figure 3-133. ECAP1_AC Register
31 30 29 28 27 26 25 24
RESERVED
R-0-0h

23 22 21 20 19 18 17 16
RESERVED
R-0-0h

15 14 13 12 11 10 9 8
RESERVED
R-0-0h

7 6 5 4 3 2 1 0
RESERVED DMA1_ACC CLA1_ACC CPUx_ACC
R-0-0h R/W-3h R/W-3h R/W-3h

Table 3-141. ECAP1_AC Register Field Descriptions

Bit Field Type Reset Description
31-6 RESERVED R-0 0h Reserved
5-4 DMA1_ACC R/W 3h Defines Access control definition for the DMA1 as:
11: Full Access for both read and Write
10: Protected RD Access such that FIFOs, Clear on read registers
are not changed + No Write Access
01: Reserved
00: No Read/Write Access to peripheral
Reset type: XRSn
3-2 CLA1_ACC R/W 3h Defines Access control definition for the CLA1 as:
11: Full Access for both read and Write
10: Protected RD Access such that FIFOs, Clear on read registers
are not changed + No Write Access
01: Reserved
00: No Read/Write Access to peripheral
Reset type: XRSn
1-0 CPUx_ACC R/W 3h Defines Access control definition for the CPUx as:
11: Full Access for both read and Write
10: Protected RD Access such that FIFOs, Clear on read registers
are not changed + No Write Access
01: Reserved
00: No Read/Write Access to peripheral
Reset type: XRSn

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3.16.7.36 ECAP2_AC Register (Offset = 82h) [Reset = 3Fh]

ECAP2_AC is shown in Figure 3-134 and described in Table 3-142.
Return to the Summary Table.
Based on control settings allows Full, Protected Read, No Access to peripheral from corresponding connected
master.
Figure 3-134. ECAP2_AC Register
31 30 29 28 27 26 25 24
RESERVED
R-0-0h

23 22 21 20 19 18 17 16
RESERVED
R-0-0h

15 14 13 12 11 10 9 8
RESERVED
R-0-0h

7 6 5 4 3 2 1 0
RESERVED DMA1_ACC CLA1_ACC CPUx_ACC
R-0-0h R/W-3h R/W-3h R/W-3h

Table 3-142. ECAP2_AC Register Field Descriptions

Bit Field Type Reset Description
31-6 RESERVED R-0 0h Reserved
5-4 DMA1_ACC R/W 3h Defines Access control definition for the DMA1 as:
11: Full Access for both read and Write
10: Protected RD Access such that FIFOs, Clear on read registers
are not changed + No Write Access
01: Reserved
00: No Read/Write Access to peripheral
Reset type: XRSn
3-2 CLA1_ACC R/W 3h Defines Access control definition for the CLA1 as:
11: Full Access for both read and Write
10: Protected RD Access such that FIFOs, Clear on read registers
are not changed + No Write Access
01: Reserved
00: No Read/Write Access to peripheral
Reset type: XRSn
1-0 CPUx_ACC R/W 3h Defines Access control definition for the CPUx as:
11: Full Access for both read and Write
10: Protected RD Access such that FIFOs, Clear on read registers
are not changed + No Write Access
01: Reserved
00: No Read/Write Access to peripheral
Reset type: XRSn

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3.16.7.37 ECAP3_AC Register (Offset = 84h) [Reset = 3Fh]

ECAP3_AC is shown in Figure 3-135 and described in Table 3-143.
Return to the Summary Table.
Based on control settings allows Full, Protected Read, No Access to peripheral from corresponding connected
master.
Figure 3-135. ECAP3_AC Register
31 30 29 28 27 26 25 24
RESERVED
R-0-0h

23 22 21 20 19 18 17 16
RESERVED
R-0-0h

15 14 13 12 11 10 9 8
RESERVED
R-0-0h

7 6 5 4 3 2 1 0
RESERVED DMA1_ACC CLA1_ACC CPUx_ACC
R-0-0h R/W-3h R/W-3h R/W-3h

Table 3-143. ECAP3_AC Register Field Descriptions

Bit Field Type Reset Description
31-6 RESERVED R-0 0h Reserved
5-4 DMA1_ACC R/W 3h Defines Access control definition for the DMA1 as:
11: Full Access for both read and Write
10: Protected RD Access such that FIFOs, Clear on read registers
are not changed + No Write Access
01: Reserved
00: No Read/Write Access to peripheral
Reset type: XRSn
3-2 CLA1_ACC R/W 3h Defines Access control definition for the CLA1 as:
11: Full Access for both read and Write
10: Protected RD Access such that FIFOs, Clear on read registers
are not changed + No Write Access
01: Reserved
00: No Read/Write Access to peripheral
Reset type: XRSn
1-0 CPUx_ACC R/W 3h Defines Access control definition for the CPUx as:
11: Full Access for both read and Write
10: Protected RD Access such that FIFOs, Clear on read registers
are not changed + No Write Access
01: Reserved
00: No Read/Write Access to peripheral
Reset type: XRSn

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3.16.7.38 ECAP4_AC Register (Offset = 86h) [Reset = 3Fh]

ECAP4_AC is shown in Figure 3-136 and described in Table 3-144.
Return to the Summary Table.
Based on control settings allows Full, Protected Read, No Access to peripheral from corresponding connected
master.
Figure 3-136. ECAP4_AC Register
31 30 29 28 27 26 25 24
RESERVED
R-0-0h

23 22 21 20 19 18 17 16
RESERVED
R-0-0h

15 14 13 12 11 10 9 8
RESERVED
R-0-0h

7 6 5 4 3 2 1 0
RESERVED DMA1_ACC CLA1_ACC CPUx_ACC
R-0-0h R/W-3h R/W-3h R/W-3h

Table 3-144. ECAP4_AC Register Field Descriptions

Bit Field Type Reset Description
31-6 RESERVED R-0 0h Reserved
5-4 DMA1_ACC R/W 3h Defines Access control definition for the DMA1 as:
11: Full Access for both read and Write
10: Protected RD Access such that FIFOs, Clear on read registers
are not changed + No Write Access
01: Reserved
00: No Read/Write Access to peripheral
Reset type: XRSn
3-2 CLA1_ACC R/W 3h Defines Access control definition for the CLA1 as:
11: Full Access for both read and Write
10: Protected RD Access such that FIFOs, Clear on read registers
are not changed + No Write Access
01: Reserved
00: No Read/Write Access to peripheral
Reset type: XRSn
1-0 CPUx_ACC R/W 3h Defines Access control definition for the CPUx as:
11: Full Access for both read and Write
10: Protected RD Access such that FIFOs, Clear on read registers
are not changed + No Write Access
01: Reserved
00: No Read/Write Access to peripheral
Reset type: XRSn

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3.16.7.39 ECAP5_AC Register (Offset = 88h) [Reset = 3Fh]

ECAP5_AC is shown in Figure 3-137 and described in Table 3-145.
Return to the Summary Table.
Based on control settings allows Full, Protected Read, No Access to peripheral from corresponding connected
master.
Figure 3-137. ECAP5_AC Register
31 30 29 28 27 26 25 24
RESERVED
R-0-0h

23 22 21 20 19 18 17 16
RESERVED
R-0-0h

15 14 13 12 11 10 9 8
RESERVED
R-0-0h

7 6 5 4 3 2 1 0
RESERVED DMA1_ACC CLA1_ACC CPUx_ACC
R-0-0h R/W-3h R/W-3h R/W-3h

Table 3-145. ECAP5_AC Register Field Descriptions

Bit Field Type Reset Description
31-6 RESERVED R-0 0h Reserved
5-4 DMA1_ACC R/W 3h Defines Access control definition for the DMA1 as:
11: Full Access for both read and Write
10: Protected RD Access such that FIFOs, Clear on read registers
are not changed + No Write Access
01: Reserved
00: No Read/Write Access to peripheral
Reset type: XRSn
3-2 CLA1_ACC R/W 3h Defines Access control definition for the CLA1 as:
11: Full Access for both read and Write
10: Protected RD Access such that FIFOs, Clear on read registers
are not changed + No Write Access
01: Reserved
00: No Read/Write Access to peripheral
Reset type: XRSn
1-0 CPUx_ACC R/W 3h Defines Access control definition for the CPUx as:
11: Full Access for both read and Write
10: Protected RD Access such that FIFOs, Clear on read registers
are not changed + No Write Access
01: Reserved
00: No Read/Write Access to peripheral
Reset type: XRSn

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3.16.7.40 ECAP6_AC Register (Offset = 8Ah) [Reset = 3Fh]

ECAP6_AC is shown in Figure 3-138 and described in Table 3-146.
Return to the Summary Table.
Based on control settings allows Full, Protected Read, No Access to peripheral from corresponding connected
master.
Figure 3-138. ECAP6_AC Register
31 30 29 28 27 26 25 24
RESERVED
R-0-0h

23 22 21 20 19 18 17 16
RESERVED
R-0-0h

15 14 13 12 11 10 9 8
RESERVED
R-0-0h

7 6 5 4 3 2 1 0
RESERVED DMA1_ACC CLA1_ACC CPUx_ACC
R-0-0h R/W-3h R/W-3h R/W-3h

Table 3-146. ECAP6_AC Register Field Descriptions

Bit Field Type Reset Description
31-6 RESERVED R-0 0h Reserved
5-4 DMA1_ACC R/W 3h Defines Access control definition for the DMA1 as:
11: Full Access for both read and Write
10: Protected RD Access such that FIFOs, Clear on read registers
are not changed + No Write Access
01: Reserved
00: No Read/Write Access to peripheral
Reset type: XRSn
3-2 CLA1_ACC R/W 3h Defines Access control definition for the CLA1 as:
11: Full Access for both read and Write
10: Protected RD Access such that FIFOs, Clear on read registers
are not changed + No Write Access
01: Reserved
00: No Read/Write Access to peripheral
Reset type: XRSn
1-0 CPUx_ACC R/W 3h Defines Access control definition for the CPUx as:
11: Full Access for both read and Write
10: Protected RD Access such that FIFOs, Clear on read registers
are not changed + No Write Access
01: Reserved
00: No Read/Write Access to peripheral
Reset type: XRSn

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3.16.7.41 ECAP7_AC Register (Offset = 8Ch) [Reset = 3Fh]

ECAP7_AC is shown in Figure 3-139 and described in Table 3-147.
Return to the Summary Table.
Based on control settings allows Full, Protected Read, No Access to peripheral from corresponding connected
master.
Figure 3-139. ECAP7_AC Register
31 30 29 28 27 26 25 24
RESERVED
R-0-0h

23 22 21 20 19 18 17 16
RESERVED
R-0-0h

15 14 13 12 11 10 9 8
RESERVED
R-0-0h

7 6 5 4 3 2 1 0
RESERVED DMA1_ACC CLA1_ACC CPUx_ACC
R-0-0h R/W-3h R/W-3h R/W-3h

Table 3-147. ECAP7_AC Register Field Descriptions

Bit Field Type Reset Description
31-6 RESERVED R-0 0h Reserved
5-4 DMA1_ACC R/W 3h Defines Access control definition for the DMA1 as:
11: Full Access for both read and Write
10: Protected RD Access such that FIFOs, Clear on read registers
are not changed + No Write Access
01: Reserved
00: No Read/Write Access to peripheral
Reset type: XRSn
3-2 CLA1_ACC R/W 3h Defines Access control definition for the CLA1 as:
11: Full Access for both read and Write
10: Protected RD Access such that FIFOs, Clear on read registers
are not changed + No Write Access
01: Reserved
00: No Read/Write Access to peripheral
Reset type: XRSn
1-0 CPUx_ACC R/W 3h Defines Access control definition for the CPUx as:
11: Full Access for both read and Write
10: Protected RD Access such that FIFOs, Clear on read registers
are not changed + No Write Access
01: Reserved
00: No Read/Write Access to peripheral
Reset type: XRSn

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3.16.7.42 SDFM1_AC Register (Offset = A8h) [Reset = 3Fh]

SDFM1_AC is shown in Figure 3-140 and described in Table 3-148.
Return to the Summary Table.
Based on control settings allows Full, Protected Read, No Access to peripheral from corresponding connected
master.
Figure 3-140. SDFM1_AC Register
31 30 29 28 27 26 25 24
RESERVED
R-0-0h

23 22 21 20 19 18 17 16
RESERVED
R-0-0h

15 14 13 12 11 10 9 8
RESERVED
R-0-0h

7 6 5 4 3 2 1 0
RESERVED DMA1_ACC CLA1_ACC CPUx_ACC
R-0-0h R/W-3h R/W-3h R/W-3h

Table 3-148. SDFM1_AC Register Field Descriptions

Bit Field Type Reset Description
31-6 RESERVED R-0 0h Reserved
5-4 DMA1_ACC R/W 3h Defines Access control definition for the DMA1 as:
11: Full Access for both read and Write
10: Protected RD Access such that FIFOs, Clear on read registers
are not changed + No Write Access
01: Reserved
00: No Read/Write Access to peripheral
Reset type: XRSn
3-2 CLA1_ACC R/W 3h Defines Access control definition for the CLA1 as:
11: Full Access for both read and Write
10: Protected RD Access such that FIFOs, Clear on read registers
are not changed + No Write Access
01: Reserved
00: No Read/Write Access to peripheral
Reset type: XRSn
1-0 CPUx_ACC R/W 3h Defines Access control definition for the CPUx as:
11: Full Access for both read and Write
10: Protected RD Access such that FIFOs, Clear on read registers
are not changed + No Write Access
01: Reserved
00: No Read/Write Access to peripheral
Reset type: XRSn

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3.16.7.43 SDFM2_AC Register (Offset = AAh) [Reset = 3Fh]

SDFM2_AC is shown in Figure 3-141 and described in Table 3-149.
Return to the Summary Table.
Based on control settings allows Full, Protected Read, No Access to peripheral from corresponding connected
master.
Figure 3-141. SDFM2_AC Register
31 30 29 28 27 26 25 24
RESERVED
R-0-0h

23 22 21 20 19 18 17 16
RESERVED
R-0-0h

15 14 13 12 11 10 9 8
RESERVED
R-0-0h

7 6 5 4 3 2 1 0
RESERVED DMA1_ACC CLA1_ACC CPUx_ACC
R-0-0h R/W-3h R/W-3h R/W-3h

Table 3-149. SDFM2_AC Register Field Descriptions

Bit Field Type Reset Description
31-6 RESERVED R-0 0h Reserved
5-4 DMA1_ACC R/W 3h Defines Access control definition for the DMA1 as:
11: Full Access for both read and Write
10: Protected RD Access such that FIFOs, Clear on read registers
are not changed + No Write Access
01: Reserved
00: No Read/Write Access to peripheral
Reset type: XRSn
3-2 CLA1_ACC R/W 3h Defines Access control definition for the CLA1 as:
11: Full Access for both read and Write
10: Protected RD Access such that FIFOs, Clear on read registers
are not changed + No Write Access
01: Reserved
00: No Read/Write Access to peripheral
Reset type: XRSn
1-0 CPUx_ACC R/W 3h Defines Access control definition for the CPUx as:
11: Full Access for both read and Write
10: Protected RD Access such that FIFOs, Clear on read registers
are not changed + No Write Access
01: Reserved
00: No Read/Write Access to peripheral
Reset type: XRSn

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3.16.7.44 CLB1_AC Register (Offset = B0h) [Reset = 3Fh]

CLB1_AC is shown in Figure 3-142 and described in Table 3-150.
Return to the Summary Table.
Based on control settings allows Full, Protected Read, No Access to peripheral from corresponding connected
master.
Figure 3-142. CLB1_AC Register
31 30 29 28 27 26 25 24
RESERVED
R-0-0h

23 22 21 20 19 18 17 16
RESERVED
R-0-0h

15 14 13 12 11 10 9 8
RESERVED
R-0-0h

7 6 5 4 3 2 1 0
RESERVED RESERVED CLA1_ACC CPUx_ACC
R-0-0h R/W-3h R/W-3h R/W-3h

Table 3-150. CLB1_AC Register Field Descriptions

Bit Field Type Reset Description
31-6 RESERVED R-0 0h Reserved
5-4 RESERVED R/W 3h Reserved
3-2 CLA1_ACC R/W 3h Defines Access control definition for the CLA1 as:
11: Full Access for both read and Write
10: Protected RD Access such that FIFOs, Clear on read registers
are not changed + No Write Access
01: Reserved
00: No Read/Write Access to peripheral
Reset type: XRSn
1-0 CPUx_ACC R/W 3h Defines Access control definition for the CPUx as:
11: Full Access for both read and Write
10: Protected RD Access such that FIFOs, Clear on read registers
are not changed + No Write Access
01: Reserved
00: No Read/Write Access to peripheral
Reset type: XRSn

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3.16.7.45 CLB2_AC Register (Offset = B2h) [Reset = 3Fh]

CLB2_AC is shown in Figure 3-143 and described in Table 3-151.
Return to the Summary Table.
Based on control settings allows Full, Protected Read, No Access to peripheral from corresponding connected
master.
Figure 3-143. CLB2_AC Register
31 30 29 28 27 26 25 24
RESERVED
R-0-0h

23 22 21 20 19 18 17 16
RESERVED
R-0-0h

15 14 13 12 11 10 9 8
RESERVED
R-0-0h

7 6 5 4 3 2 1 0
RESERVED RESERVED CLA1_ACC CPUx_ACC
R-0-0h R/W-3h R/W-3h R/W-3h

Table 3-151. CLB2_AC Register Field Descriptions

Bit Field Type Reset Description
31-6 RESERVED R-0 0h Reserved
5-4 RESERVED R/W 3h Reserved
3-2 CLA1_ACC R/W 3h Defines Access control definition for the CLA1 as:
11: Full Access for both read and Write
10: Protected RD Access such that FIFOs, Clear on read registers
are not changed + No Write Access
01: Reserved
00: No Read/Write Access to peripheral
Reset type: XRSn
1-0 CPUx_ACC R/W 3h Defines Access control definition for the CPUx as:
11: Full Access for both read and Write
10: Protected RD Access such that FIFOs, Clear on read registers
are not changed + No Write Access
01: Reserved
00: No Read/Write Access to peripheral
Reset type: XRSn

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3.16.7.46 CLB3_AC Register (Offset = B4h) [Reset = 3Fh]

CLB3_AC is shown in Figure 3-144 and described in Table 3-152.
Return to the Summary Table.
Based on control settings allows Full, Protected Read, No Access to peripheral from corresponding connected
master.
Figure 3-144. CLB3_AC Register
31 30 29 28 27 26 25 24
RESERVED
R-0-0h

23 22 21 20 19 18 17 16
RESERVED
R-0-0h

15 14 13 12 11 10 9 8
RESERVED
R-0-0h

7 6 5 4 3 2 1 0
RESERVED RESERVED CLA1_ACC CPUx_ACC
R-0-0h R/W-3h R/W-3h R/W-3h

Table 3-152. CLB3_AC Register Field Descriptions

Bit Field Type Reset Description
31-6 RESERVED R-0 0h Reserved
5-4 RESERVED R/W 3h Reserved
3-2 CLA1_ACC R/W 3h Defines Access control definition for the CLA1 as:
11: Full Access for both read and Write
10: Protected RD Access such that FIFOs, Clear on read registers
are not changed + No Write Access
01: Reserved
00: No Read/Write Access to peripheral
Reset type: XRSn
1-0 CPUx_ACC R/W 3h Defines Access control definition for the CPUx as:
11: Full Access for both read and Write
10: Protected RD Access such that FIFOs, Clear on read registers
are not changed + No Write Access
01: Reserved
00: No Read/Write Access to peripheral
Reset type: XRSn

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3.16.7.47 CLB4_AC Register (Offset = B6h) [Reset = 3Fh]

CLB4_AC is shown in Figure 3-145 and described in Table 3-153.
Return to the Summary Table.
Based on control settings allows Full, Protected Read, No Access to peripheral from corresponding connected
master.
Figure 3-145. CLB4_AC Register
31 30 29 28 27 26 25 24
RESERVED
R-0-0h

23 22 21 20 19 18 17 16
RESERVED
R-0-0h

15 14 13 12 11 10 9 8
RESERVED
R-0-0h

7 6 5 4 3 2 1 0
RESERVED RESERVED CLA1_ACC CPUx_ACC
R-0-0h R/W-3h R/W-3h R/W-3h

Table 3-153. CLB4_AC Register Field Descriptions

Bit Field Type Reset Description
31-6 RESERVED R-0 0h Reserved
5-4 RESERVED R/W 3h Reserved
3-2 CLA1_ACC R/W 3h Defines Access control definition for the CLA1 as:
11: Full Access for both read and Write
10: Protected RD Access such that FIFOs, Clear on read registers
are not changed + No Write Access
01: Reserved
00: No Read/Write Access to peripheral
Reset type: XRSn
1-0 CPUx_ACC R/W 3h Defines Access control definition for the CPUx as:
11: Full Access for both read and Write
10: Protected RD Access such that FIFOs, Clear on read registers
are not changed + No Write Access
01: Reserved
00: No Read/Write Access to peripheral
Reset type: XRSn

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3.16.7.48 CLB5_AC Register (Offset = B8h) [Reset = 3Fh]

CLB5_AC is shown in Figure 3-146 and described in Table 3-154.
Return to the Summary Table.
Based on control settings allows Full, Protected Read, No Access to peripheral from corresponding connected
master.
Figure 3-146. CLB5_AC Register
31 30 29 28 27 26 25 24
RESERVED
R-0-0h

23 22 21 20 19 18 17 16
RESERVED
R-0-0h

15 14 13 12 11 10 9 8
RESERVED
R-0-0h

7 6 5 4 3 2 1 0
RESERVED RESERVED CLA1_ACC CPUx_ACC
R-0-0h R/W-3h R/W-3h R/W-3h

Table 3-154. CLB5_AC Register Field Descriptions

Bit Field Type Reset Description
31-6 RESERVED R-0 0h Reserved
5-4 RESERVED R/W 3h Reserved
3-2 CLA1_ACC R/W 3h Defines Access control definition for the CLA1 as:
11: Full Access for both read and Write
10: Protected RD Access such that FIFOs, Clear on read registers
are not changed + No Write Access
01: Reserved
00: No Read/Write Access to peripheral
Reset type: XRSn
1-0 CPUx_ACC R/W 3h Defines Access control definition for the CPUx as:
11: Full Access for both read and Write
10: Protected RD Access such that FIFOs, Clear on read registers
are not changed + No Write Access
01: Reserved
00: No Read/Write Access to peripheral
Reset type: XRSn

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3.16.7.49 CLB6_AC Register (Offset = BAh) [Reset = 3Fh]

CLB6_AC is shown in Figure 3-147 and described in Table 3-155.
Return to the Summary Table.
Based on control settings allows Full, Protected Read, No Access to peripheral from corresponding connected
master.
Figure 3-147. CLB6_AC Register
31 30 29 28 27 26 25 24
RESERVED
R-0-0h

23 22 21 20 19 18 17 16
RESERVED
R-0-0h

15 14 13 12 11 10 9 8
RESERVED
R-0-0h

7 6 5 4 3 2 1 0
RESERVED RESERVED CLA1_ACC CPUx_ACC
R-0-0h R/W-3h R/W-3h R/W-3h

Table 3-155. CLB6_AC Register Field Descriptions

Bit Field Type Reset Description
31-6 RESERVED R-0 0h Reserved
5-4 RESERVED R/W 3h Reserved
3-2 CLA1_ACC R/W 3h Defines Access control definition for the CLA1 as:
11: Full Access for both read and Write
10: Protected RD Access such that FIFOs, Clear on read registers
are not changed + No Write Access
01: Reserved
00: No Read/Write Access to peripheral
Reset type: XRSn
1-0 CPUx_ACC R/W 3h Defines Access control definition for the CPUx as:
11: Full Access for both read and Write
10: Protected RD Access such that FIFOs, Clear on read registers
are not changed + No Write Access
01: Reserved
00: No Read/Write Access to peripheral
Reset type: XRSn

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3.16.7.50 CLB7_AC Register (Offset = BCh) [Reset = 3Fh]

CLB7_AC is shown in Figure 3-148 and described in Table 3-156.
Return to the Summary Table.
Based on control settings allows Full, Protected Read, No Access to peripheral from corresponding connected
master.
Figure 3-148. CLB7_AC Register
31 30 29 28 27 26 25 24
RESERVED
R-0-0h

23 22 21 20 19 18 17 16
RESERVED
R-0-0h

15 14 13 12 11 10 9 8
RESERVED
R-0-0h

7 6 5 4 3 2 1 0
RESERVED RESERVED CLA1_ACC CPUx_ACC
R-0-0h R/W-3h R/W-3h R/W-3h

Table 3-156. CLB7_AC Register Field Descriptions

Bit Field Type Reset Description
31-6 RESERVED R-0 0h Reserved
5-4 RESERVED R/W 3h Reserved
3-2 CLA1_ACC R/W 3h Defines Access control definition for the CLA1 as:
11: Full Access for both read and Write
10: Protected RD Access such that FIFOs, Clear on read registers
are not changed + No Write Access
01: Reserved
00: No Read/Write Access to peripheral
Reset type: XRSn
1-0 CPUx_ACC R/W 3h Defines Access control definition for the CPUx as:
11: Full Access for both read and Write
10: Protected RD Access such that FIFOs, Clear on read registers
are not changed + No Write Access
01: Reserved
00: No Read/Write Access to peripheral
Reset type: XRSn

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3.16.7.51 CLB8_AC Register (Offset = BEh) [Reset = 3Fh]

CLB8_AC is shown in Figure 3-149 and described in Table 3-157.
Return to the Summary Table.
Based on control settings allows Full, Protected Read, No Access to peripheral from corresponding connected
master.
Figure 3-149. CLB8_AC Register
31 30 29 28 27 26 25 24
RESERVED
R-0-0h

23 22 21 20 19 18 17 16
RESERVED
R-0-0h

15 14 13 12 11 10 9 8
RESERVED
R-0-0h

7 6 5 4 3 2 1 0
RESERVED RESERVED CLA1_ACC CPUx_ACC
R-0-0h R/W-3h R/W-3h R/W-3h

Table 3-157. CLB8_AC Register Field Descriptions

Bit Field Type Reset Description
31-6 RESERVED R-0 0h Reserved
5-4 RESERVED R/W 3h Reserved
3-2 CLA1_ACC R/W 3h Defines Access control definition for the CLA1 as:
11: Full Access for both read and Write
10: Protected RD Access such that FIFOs, Clear on read registers
are not changed + No Write Access
01: Reserved
00: No Read/Write Access to peripheral
Reset type: XRSn
1-0 CPUx_ACC R/W 3h Defines Access control definition for the CPUx as:
11: Full Access for both read and Write
10: Protected RD Access such that FIFOs, Clear on read registers
are not changed + No Write Access
01: Reserved
00: No Read/Write Access to peripheral
Reset type: XRSn

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3.16.7.52 SPIA_AC Register (Offset = 110h) [Reset = 3Fh]

SPIA_AC is shown in Figure 3-150 and described in Table 3-158.
Return to the Summary Table.
Based on control settings allows Full, Protected Read, No Access to peripheral from corresponding connected
master.
Figure 3-150. SPIA_AC Register
31 30 29 28 27 26 25 24
RESERVED
R-0-0h

23 22 21 20 19 18 17 16
RESERVED
R-0-0h

15 14 13 12 11 10 9 8
RESERVED
R-0-0h

7 6 5 4 3 2 1 0
RESERVED DMA1_ACC CLA1_ACC CPUx_ACC
R-0-0h R/W-3h R/W-3h R/W-3h

Table 3-158. SPIA_AC Register Field Descriptions

Bit Field Type Reset Description
31-6 RESERVED R-0 0h Reserved
5-4 DMA1_ACC R/W 3h Defines Access control definition for the DMA1 as:
11: Full Access for both read and Write
10: Protected RD Access such that FIFOs, Clear on read registers
are not changed + No Write Access
01: Reserved
00: No Read/Write Access to peripheral
Reset type: XRSn
3-2 CLA1_ACC R/W 3h Defines Access control definition for the CLA1 as:
11: Full Access for both read and Write
10: Protected RD Access such that FIFOs, Clear on read registers
are not changed + No Write Access
01: Reserved
00: No Read/Write Access to peripheral
Reset type: XRSn
1-0 CPUx_ACC R/W 3h Defines Access control definition for the CPUx as:
11: Full Access for both read and Write
10: Protected RD Access such that FIFOs, Clear on read registers
are not changed + No Write Access
01: Reserved
00: No Read/Write Access to peripheral
Reset type: XRSn

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3.16.7.53 SPIB_AC Register (Offset = 112h) [Reset = 3Fh]

SPIB_AC is shown in Figure 3-151 and described in Table 3-159.
Return to the Summary Table.
Based on control settings allows Full, Protected Read, No Access to peripheral from corresponding connected
master.
Figure 3-151. SPIB_AC Register
31 30 29 28 27 26 25 24
RESERVED
R-0-0h

23 22 21 20 19 18 17 16
RESERVED
R-0-0h

15 14 13 12 11 10 9 8
RESERVED
R-0-0h

7 6 5 4 3 2 1 0
RESERVED DMA1_ACC CLA1_ACC CPUx_ACC
R-0-0h R/W-3h R/W-3h R/W-3h

Table 3-159. SPIB_AC Register Field Descriptions

Bit Field Type Reset Description
31-6 RESERVED R-0 0h Reserved
5-4 DMA1_ACC R/W 3h Defines Access control definition for the DMA1 as:
11: Full Access for both read and Write
10: Protected RD Access such that FIFOs, Clear on read registers
are not changed + No Write Access
01: Reserved
00: No Read/Write Access to peripheral
Reset type: XRSn
3-2 CLA1_ACC R/W 3h Defines Access control definition for the CLA1 as:
11: Full Access for both read and Write
10: Protected RD Access such that FIFOs, Clear on read registers
are not changed + No Write Access
01: Reserved
00: No Read/Write Access to peripheral
Reset type: XRSn
1-0 CPUx_ACC R/W 3h Defines Access control definition for the CPUx as:
11: Full Access for both read and Write
10: Protected RD Access such that FIFOs, Clear on read registers
are not changed + No Write Access
01: Reserved
00: No Read/Write Access to peripheral
Reset type: XRSn

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3.16.7.54 SPIC_AC Register (Offset = 114h) [Reset = 3Fh]

SPIC_AC is shown in Figure 3-152 and described in Table 3-160.
Return to the Summary Table.
Based on control settings allows Full, Protected Read, No Access to peripheral from corresponding connected
master.
Figure 3-152. SPIC_AC Register
31 30 29 28 27 26 25 24
RESERVED
R-0-0h

23 22 21 20 19 18 17 16
RESERVED
R-0-0h

15 14 13 12 11 10 9 8
RESERVED
R-0-0h

7 6 5 4 3 2 1 0
RESERVED DMA1_ACC CLA1_ACC CPUx_ACC
R-0-0h R/W-3h R/W-3h R/W-3h

Table 3-160. SPIC_AC Register Field Descriptions

Bit Field Type Reset Description
31-6 RESERVED R-0 0h Reserved
5-4 DMA1_ACC R/W 3h Defines Access control definition for the DMA1 as:
11: Full Access for both read and Write
10: Protected RD Access such that FIFOs, Clear on read registers
are not changed + No Write Access
01: Reserved
00: No Read/Write Access to peripheral
Reset type: XRSn
3-2 CLA1_ACC R/W 3h Defines Access control definition for the CLA1 as:
11: Full Access for both read and Write
10: Protected RD Access such that FIFOs, Clear on read registers
are not changed + No Write Access
01: Reserved
00: No Read/Write Access to peripheral
Reset type: XRSn
1-0 CPUx_ACC R/W 3h Defines Access control definition for the CPUx as:
11: Full Access for both read and Write
10: Protected RD Access such that FIFOs, Clear on read registers
are not changed + No Write Access
01: Reserved
00: No Read/Write Access to peripheral
Reset type: XRSn

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3.16.7.55 SPID_AC Register (Offset = 116h) [Reset = 3Fh]

SPID_AC is shown in Figure 3-153 and described in Table 3-161.
Return to the Summary Table.
Based on control settings allows Full, Protected Read, No Access to peripheral from corresponding connected
master.
Figure 3-153. SPID_AC Register
31 30 29 28 27 26 25 24
RESERVED
R-0-0h

23 22 21 20 19 18 17 16
RESERVED
R-0-0h

15 14 13 12 11 10 9 8
RESERVED
R-0-0h

7 6 5 4 3 2 1 0
RESERVED DMA1_ACC CLA1_ACC CPUx_ACC
R-0-0h R/W-3h R/W-3h R/W-3h

Table 3-161. SPID_AC Register Field Descriptions

Bit Field Type Reset Description
31-6 RESERVED R-0 0h Reserved
5-4 DMA1_ACC R/W 3h Defines Access control definition for the DMA1 as:
11: Full Access for both read and Write
10: Protected RD Access such that FIFOs, Clear on read registers
are not changed + No Write Access
01: Reserved
00: No Read/Write Access to peripheral
Reset type: XRSn
3-2 CLA1_ACC R/W 3h Defines Access control definition for the CLA1 as:
11: Full Access for both read and Write
10: Protected RD Access such that FIFOs, Clear on read registers
are not changed + No Write Access
01: Reserved
00: No Read/Write Access to peripheral
Reset type: XRSn
1-0 CPUx_ACC R/W 3h Defines Access control definition for the CPUx as:
11: Full Access for both read and Write
10: Protected RD Access such that FIFOs, Clear on read registers
are not changed + No Write Access
01: Reserved
00: No Read/Write Access to peripheral
Reset type: XRSn

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3.16.7.56 PMBUS_A_AC Register (Offset = 130h) [Reset = 3Fh]

PMBUS_A_AC is shown in Figure 3-154 and described in Table 3-162.
Return to the Summary Table.
Based on control settings allows Full, Protected Read, No Access to peripheral from corresponding connected
master.
Figure 3-154. PMBUS_A_AC Register
31 30 29 28 27 26 25 24
RESERVED
R-0-0h

23 22 21 20 19 18 17 16
RESERVED
R-0-0h

15 14 13 12 11 10 9 8
RESERVED
R-0-0h

7 6 5 4 3 2 1 0
RESERVED DMA1_ACC CLA1_ACC CPUx_ACC
R-0-0h R/W-3h R/W-3h R/W-3h

Table 3-162. PMBUS_A_AC Register Field Descriptions

Bit Field Type Reset Description
31-6 RESERVED R-0 0h Reserved
5-4 DMA1_ACC R/W 3h Defines Access control definition for the DMA1 as:
11: Full Access for both read and Write
10: Protected RD Access such that FIFOs, Clear on read registers
are not changed + No Write Access
01: Reserved
00: No Read/Write Access to peripheral
Reset type: XRSn
3-2 CLA1_ACC R/W 3h Defines Access control definition for the CLA1 as:
11: Full Access for both read and Write
10: Protected RD Access such that FIFOs, Clear on read registers
are not changed + No Write Access
01: Reserved
00: No Read/Write Access to peripheral
Reset type: XRSn
1-0 CPUx_ACC R/W 3h Defines Access control definition for the CPUx as:
11: Full Access for both read and Write
10: Protected RD Access such that FIFOs, Clear on read registers
are not changed + No Write Access
01: Reserved
00: No Read/Write Access to peripheral
Reset type: XRSn

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3.16.7.57 CAN_A_AC Register (Offset = 140h) [Reset = 3Fh]

CAN_A_AC is shown in Figure 3-155 and described in Table 3-163.
Return to the Summary Table.
Based on control settings allows Full, Protected Read, No Access to peripheral from corresponding connected
master.
Figure 3-155. CAN_A_AC Register
31 30 29 28 27 26 25 24
RESERVED
R-0-0h

23 22 21 20 19 18 17 16
RESERVED
R-0-0h

15 14 13 12 11 10 9 8
RESERVED
R-0-0h

7 6 5 4 3 2 1 0
RESERVED DMA1_ACC RESERVED CPUx_ACC
R-0-0h R/W-3h R/W-3h R/W-3h

Table 3-163. CAN_A_AC Register Field Descriptions

Bit Field Type Reset Description
31-6 RESERVED R-0 0h Reserved
5-4 DMA1_ACC R/W 3h Defines Access control definition for the DMA1 as:
11: Full Access for both read and Write
10: Protected RD Access such that FIFOs, Clear on read registers
are not changed + No Write Access
01: Reserved
00: No Read/Write Access to peripheral
Reset type: XRSn
3-2 RESERVED R/W 3h Reserved
1-0 CPUx_ACC R/W 3h Defines Access control definition for the CPUx as:
11: Full Access for both read and Write
10: Protected RD Access such that FIFOs, Clear on read registers
are not changed + No Write Access
01: Reserved
00: No Read/Write Access to peripheral
Reset type: XRSn

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3.16.7.58 CAN_B_AC Register (Offset = 142h) [Reset = 3Fh]

CAN_B_AC is shown in Figure 3-156 and described in Table 3-164.
Return to the Summary Table.
Based on control settings allows Full, Protected Read, No Access to peripheral from corresponding connected
master.
Figure 3-156. CAN_B_AC Register
31 30 29 28 27 26 25 24
RESERVED
R-0-0h

23 22 21 20 19 18 17 16
RESERVED
R-0-0h

15 14 13 12 11 10 9 8
RESERVED
R-0-0h

7 6 5 4 3 2 1 0
RESERVED DMA1_ACC RESERVED CPUx_ACC
R-0-0h R/W-3h R/W-3h R/W-3h

Table 3-164. CAN_B_AC Register Field Descriptions

Bit Field Type Reset Description
31-6 RESERVED R-0 0h Reserved
5-4 DMA1_ACC R/W 3h Defines Access control definition for the DMA1 as:
11: Full Access for both read and Write
10: Protected RD Access such that FIFOs, Clear on read registers
are not changed + No Write Access
01: Reserved
00: No Read/Write Access to peripheral
Reset type: XRSn
3-2 RESERVED R/W 3h Reserved
1-0 CPUx_ACC R/W 3h Defines Access control definition for the CPUx as:
11: Full Access for both read and Write
10: Protected RD Access such that FIFOs, Clear on read registers
are not changed + No Write Access
01: Reserved
00: No Read/Write Access to peripheral
Reset type: XRSn

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3.16.7.59 MCBSPA_AC Register (Offset = 150h) [Reset = 3Fh]

MCBSPA_AC is shown in Figure 3-157 and described in Table 3-165.
Return to the Summary Table.
Based on control settings allows Full, Protected Read, No Access to peripheral from corresponding connected
master.
Figure 3-157. MCBSPA_AC Register
31 30 29 28 27 26 25 24
RESERVED
R-0-0h

23 22 21 20 19 18 17 16
RESERVED
R-0-0h

15 14 13 12 11 10 9 8
RESERVED
R-0-0h

7 6 5 4 3 2 1 0
RESERVED DMA1_ACC CLA1_ACC CPUx_ACC
R-0-0h R/W-3h R/W-3h R/W-3h

Table 3-165. MCBSPA_AC Register Field Descriptions

Bit Field Type Reset Description
31-6 RESERVED R-0 0h Reserved
5-4 DMA1_ACC R/W 3h Defines Access control definition for the DMA1 as:
11: Full Access for both read and Write
10: Protected RD Access such that FIFOs, Clear on read registers
are not changed + No Write Access
01: Reserved
00: No Read/Write Access to peripheral
Reset type: XRSn
3-2 CLA1_ACC R/W 3h Defines Access control definition for the CLA1 as:
11: Full Access for both read and Write
10: Protected RD Access such that FIFOs, Clear on read registers
are not changed + No Write Access
01: Reserved
00: No Read/Write Access to peripheral
Reset type: XRSn
1-0 CPUx_ACC R/W 3h Defines Access control definition for the CPUx as:
11: Full Access for both read and Write
10: Protected RD Access such that FIFOs, Clear on read registers
are not changed + No Write Access
01: Reserved
00: No Read/Write Access to peripheral
Reset type: XRSn

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3.16.7.60 MCBSPB_AC Register (Offset = 152h) [Reset = 3Fh]

MCBSPB_AC is shown in Figure 3-158 and described in Table 3-166.
Return to the Summary Table.
Based on control settings allows Full, Protected Read, No Access to peripheral from corresponding connected
master.
Figure 3-158. MCBSPB_AC Register
31 30 29 28 27 26 25 24
RESERVED
R-0-0h

23 22 21 20 19 18 17 16
RESERVED
R-0-0h

15 14 13 12 11 10 9 8
RESERVED
R-0-0h

7 6 5 4 3 2 1 0
RESERVED DMA1_ACC CLA1_ACC CPUx_ACC
R-0-0h R/W-3h R/W-3h R/W-3h

Table 3-166. MCBSPB_AC Register Field Descriptions

Bit Field Type Reset Description
31-6 RESERVED R-0 0h Reserved
5-4 DMA1_ACC R/W 3h Defines Access control definition for the DMA1 as:
11: Full Access for both read and Write
10: Protected RD Access such that FIFOs, Clear on read registers
are not changed + No Write Access
01: Reserved
00: No Read/Write Access to peripheral
Reset type: XRSn
3-2 CLA1_ACC R/W 3h Defines Access control definition for the CLA1 as:
11: Full Access for both read and Write
10: Protected RD Access such that FIFOs, Clear on read registers
are not changed + No Write Access
01: Reserved
00: No Read/Write Access to peripheral
Reset type: XRSn
1-0 CPUx_ACC R/W 3h Defines Access control definition for the CPUx as:
11: Full Access for both read and Write
10: Protected RD Access such that FIFOs, Clear on read registers
are not changed + No Write Access
01: Reserved
00: No Read/Write Access to peripheral
Reset type: XRSn

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3.16.7.61 USBA_AC Register (Offset = 180h) [Reset = 3Fh]

USBA_AC is shown in Figure 3-159 and described in Table 3-167.
Return to the Summary Table.
Based on control settings allows Full, Protected Read, No Access to peripheral from corresponding connected
master.
Figure 3-159. USBA_AC Register
31 30 29 28 27 26 25 24
RESERVED
R-0-0h

23 22 21 20 19 18 17 16
RESERVED
R-0-0h

15 14 13 12 11 10 9 8
RESERVED
R-0-0h

7 6 5 4 3 2 1 0
RESERVED DMA1_ACC RESERVED CPUx_ACC
R-0-0h R/W-3h R/W-3h R/W-3h

Table 3-167. USBA_AC Register Field Descriptions

Bit Field Type Reset Description
31-6 RESERVED R-0 0h Reserved
5-4 DMA1_ACC R/W 3h Defines Access control definition for the DMA1 as:
11: Full Access for both read and Write
10: Protected RD Access such that FIFOs, Clear on read registers
are not changed + No Write Access
01: Reserved
00: No Read/Write Access to peripheral
Reset type: XRSn
3-2 RESERVED R/W 3h Reserved
1-0 CPUx_ACC R/W 3h Defines Access control definition for the CPUx as:
11: Full Access for both read and Write
10: Protected RD Access such that FIFOs, Clear on read registers
are not changed + No Write Access
01: Reserved
00: No Read/Write Access to peripheral
Reset type: XRSn

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3.16.7.62 HRPWM_AC Register (Offset = 1A8h) [Reset = 3Fh]

HRPWM_AC is shown in Figure 3-160 and described in Table 3-168.
Return to the Summary Table.
Based on control settings allows Full, Protected Read, No Access to peripheral from corresponding connected
master.
Note: Following registers are controlled by this register:
HRPWR
HRCAL
HRPRD
HRCNT0
HRCNT1
HRMSTEP
Figure 3-160. HRPWM_AC Register
31 30 29 28 27 26 25 24
RESERVED
R-0-0h

23 22 21 20 19 18 17 16
RESERVED
R-0-0h

15 14 13 12 11 10 9 8
RESERVED
R-0-0h

7 6 5 4 3 2 1 0
RESERVED DMA1_ACC CLA1_ACC CPUx_ACC
R-0-0h R/W-3h R/W-3h R/W-3h

Table 3-168. HRPWM_AC Register Field Descriptions

Bit Field Type Reset Description
31-6 RESERVED R-0 0h Reserved
5-4 DMA1_ACC R/W 3h Defines Access control definition for the DMA1 as:
11: Full Access for both read and Write
10: Protected RD Access such that FIFOs, Clear on read registers
are not changed + No Write Access
01: Reserved
00: No Read/Write Access to peripheral
Note: Following registers are covered by this register
HRPWR
HRCAL
HRPRD
HRCNT0
HRCNT1
HRMSTEP
Reset type: XRSn

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Table 3-168. HRPWM_AC Register Field Descriptions (continued)

Bit Field Type Reset Description
3-2 CLA1_ACC R/W 3h Defines Access control definition for the CLA1 as:
11: Full Access for both read and Write
10: Protected RD Access such that FIFOs, Clear on read registers
are not changed + No Write Access
01: Reserved
00: No Read/Write Access to peripheral
Note: Following registers are covered by this register
HRPWR
HRCAL
HRPRD
HRCNT0
HRCNT1
HRMSTEP
Reset type: XRSn
1-0 CPUx_ACC R/W 3h Defines Access control definition for the CPUx as:
11: Full Access for both read and Write
10: Protected RD Access such that FIFOs, Clear on read registers
are not changed + No Write Access
01: Reserved
00: No Read/Write Access to peripheral
Note: Following registers are covered by this register
HRPWR
HRCAL
HRPRD
HRCNT0
HRCNT1
HRMSTEP
Reset type: XRSn

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3.16.7.63 ETHERCAT_AC Register (Offset = 1AAh) [Reset = 3Fh]

ETHERCAT_AC is shown in Figure 3-161 and described in Table 3-169.
Return to the Summary Table.
Based on control settings allows Full, Protected Read, No Access to peripheral from corresponding connected
master.
Figure 3-161. ETHERCAT_AC Register
31 30 29 28 27 26 25 24
RESERVED
R-0-0h

23 22 21 20 19 18 17 16
RESERVED
R-0-0h

15 14 13 12 11 10 9 8
RESERVED
R-0-0h

7 6 5 4 3 2 1 0
RESERVED DMA1_ACC RESERVED CPU1_ACC
R-0-0h R/W-3h R/W-3h R/W-3h

Table 3-169. ETHERCAT_AC Register Field Descriptions

Bit Field Type Reset Description
31-6 RESERVED R-0 0h Reserved
5-4 DMA1_ACC R/W 3h Defines Access control definition for the DMA1 as:
11: Full Access for both read and Write
10: Protected RD Access such that FIFOs, Clear on read registers
are not changed + No Write Access
01: Reserved
00: No Read/Write Access to peripheral
Reset type: XRSn
3-2 RESERVED R/W 3h Reserved
1-0 CPU1_ACC R/W 3h Defines Access control definition for the CPUx as:
11: Full Access for both read and Write
10: Protected RD Access such that FIFOs, Clear on read registers
are not changed + No Write Access
01: Reserved
00: No Read/Write Access to peripheral
Reset type: XRSn

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3.16.7.64 FSIATX_AC Register (Offset = 1B0h) [Reset = 3Fh]

FSIATX_AC is shown in Figure 3-162 and described in Table 3-170.
Return to the Summary Table.
Based on control settings allows Full, Protected Read, No Access to peripheral from corresponding connected
master.
Figure 3-162. FSIATX_AC Register
31 30 29 28 27 26 25 24
RESERVED
R-0-0h

23 22 21 20 19 18 17 16
RESERVED
R-0-0h

15 14 13 12 11 10 9 8
RESERVED
R-0-0h

7 6 5 4 3 2 1 0
RESERVED DMA1_ACC CLA1_ACC CPUx_ACC
R-0-0h R/W-3h R/W-3h R/W-3h

Table 3-170. FSIATX_AC Register Field Descriptions

Bit Field Type Reset Description
31-6 RESERVED R-0 0h Reserved
5-4 DMA1_ACC R/W 3h Defines Access control definition for the DMA1 as:
11: Full Access for both read and Write
10: Protected RD Access such that FIFOs, Clear on read registers
are not changed + No Write Access
01: Reserved
00: No Read/Write Access to peripheral
Reset type: XRSn
3-2 CLA1_ACC R/W 3h Defines Access control definition for the CLA1 as:
11: Full Access for both read and Write
10: Protected RD Access such that FIFOs, Clear on read registers
are not changed + No Write Access
01: Reserved
00: No Read/Write Access to peripheral
Reset type: XRSn
1-0 CPUx_ACC R/W 3h Defines Access control definition for the CPUx as:
11: Full Access for both read and Write
10: Protected RD Access such that FIFOs, Clear on read registers
are not changed + No Write Access
01: Reserved
00: No Read/Write Access to peripheral
Reset type: XRSn

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3.16.7.65 FSIARX_AC Register (Offset = 1B2h) [Reset = 3Fh]

FSIARX_AC is shown in Figure 3-163 and described in Table 3-171.
Return to the Summary Table.
Based on control settings allows Full, Protected Read, No Access to peripheral from corresponding connected
master.
Figure 3-163. FSIARX_AC Register
31 30 29 28 27 26 25 24
RESERVED
R-0-0h

23 22 21 20 19 18 17 16
RESERVED
R-0-0h

15 14 13 12 11 10 9 8
RESERVED
R-0-0h

7 6 5 4 3 2 1 0
RESERVED DMA1_ACC CLA1_ACC CPUx_ACC
R-0-0h R/W-3h R/W-3h R/W-3h

Table 3-171. FSIARX_AC Register Field Descriptions

Bit Field Type Reset Description
31-6 RESERVED R-0 0h Reserved
5-4 DMA1_ACC R/W 3h Defines Access control definition for the DMA1 as:
11: Full Access for both read and Write
10: Protected RD Access such that FIFOs, Clear on read registers
are not changed + No Write Access
01: Reserved
00: No Read/Write Access to peripheral
Reset type: XRSn
3-2 CLA1_ACC R/W 3h Defines Access control definition for the CLA1 as:
11: Full Access for both read and Write
10: Protected RD Access such that FIFOs, Clear on read registers
are not changed + No Write Access
01: Reserved
00: No Read/Write Access to peripheral
Reset type: XRSn
1-0 CPUx_ACC R/W 3h Defines Access control definition for the CPUx as:
11: Full Access for both read and Write
10: Protected RD Access such that FIFOs, Clear on read registers
are not changed + No Write Access
01: Reserved
00: No Read/Write Access to peripheral
Reset type: XRSn

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3.16.7.66 FSIBTX_AC Register (Offset = 1B4h) [Reset = 3Fh]

FSIBTX_AC is shown in Figure 3-164 and described in Table 3-172.
Return to the Summary Table.
Based on control settings allows Full, Protected Read, No Access to peripheral from corresponding connected
master.
Figure 3-164. FSIBTX_AC Register
31 30 29 28 27 26 25 24
RESERVED
R-0-0h

23 22 21 20 19 18 17 16
RESERVED
R-0-0h

15 14 13 12 11 10 9 8
RESERVED
R-0-0h

7 6 5 4 3 2 1 0
RESERVED DMA1_ACC CLA1_ACC CPUx_ACC
R-0-0h R/W-3h R/W-3h R/W-3h

Table 3-172. FSIBTX_AC Register Field Descriptions

Bit Field Type Reset Description
31-6 RESERVED R-0 0h Reserved
5-4 DMA1_ACC R/W 3h Defines Access control definition for the DMA1 as:
11: Full Access for both read and Write
10: Protected RD Access such that FIFOs, Clear on read registers
are not changed + No Write Access
01: Reserved
00: No Read/Write Access to peripheral
Reset type: XRSn
3-2 CLA1_ACC R/W 3h Defines Access control definition for the CLA1 as:
11: Full Access for both read and Write
10: Protected RD Access such that FIFOs, Clear on read registers
are not changed + No Write Access
01: Reserved
00: No Read/Write Access to peripheral
Reset type: XRSn
1-0 CPUx_ACC R/W 3h Defines Access control definition for the CPUx as:
11: Full Access for both read and Write
10: Protected RD Access such that FIFOs, Clear on read registers
are not changed + No Write Access
01: Reserved
00: No Read/Write Access to peripheral
Reset type: XRSn

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3.16.7.67 FSIBRX_AC Register (Offset = 1B6h) [Reset = 3Fh]

FSIBRX_AC is shown in Figure 3-165 and described in Table 3-173.
Return to the Summary Table.
Based on control settings allows Full, Protected Read, No Access to peripheral from corresponding connected
master.
Figure 3-165. FSIBRX_AC Register
31 30 29 28 27 26 25 24
RESERVED
R-0-0h

23 22 21 20 19 18 17 16
RESERVED
R-0-0h

15 14 13 12 11 10 9 8
RESERVED
R-0-0h

7 6 5 4 3 2 1 0
RESERVED DMA1_ACC CLA1_ACC CPUx_ACC
R-0-0h R/W-3h R/W-3h R/W-3h

Table 3-173. FSIBRX_AC Register Field Descriptions

Bit Field Type Reset Description
31-6 RESERVED R-0 0h Reserved
5-4 DMA1_ACC R/W 3h Defines Access control definition for the DMA1 as:
11: Full Access for both read and Write
10: Protected RD Access such that FIFOs, Clear on read registers
are not changed + No Write Access
01: Reserved
00: No Read/Write Access to peripheral
Reset type: XRSn
3-2 CLA1_ACC R/W 3h Defines Access control definition for the CLA1 as:
11: Full Access for both read and Write
10: Protected RD Access such that FIFOs, Clear on read registers
are not changed + No Write Access
01: Reserved
00: No Read/Write Access to peripheral
Reset type: XRSn
1-0 CPUx_ACC R/W 3h Defines Access control definition for the CPUx as:
11: Full Access for both read and Write
10: Protected RD Access such that FIFOs, Clear on read registers
are not changed + No Write Access
01: Reserved
00: No Read/Write Access to peripheral
Reset type: XRSn

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3.16.7.68 FSICRX_AC Register (Offset = 1BAh) [Reset = 3Fh]

FSICRX_AC is shown in Figure 3-166 and described in Table 3-174.
Return to the Summary Table.
Based on control settings allows Full, Protected Read, No Access to peripheral from corresponding connected
master.
Figure 3-166. FSICRX_AC Register
31 30 29 28 27 26 25 24
RESERVED
R-0-0h

23 22 21 20 19 18 17 16
RESERVED
R-0-0h

15 14 13 12 11 10 9 8
RESERVED
R-0-0h

7 6 5 4 3 2 1 0
RESERVED DMA1_ACC CLA1_ACC CPUx_ACC
R-0-0h R/W-3h R/W-3h R/W-3h

Table 3-174. FSICRX_AC Register Field Descriptions

Bit Field Type Reset Description
31-6 RESERVED R-0 0h Reserved
5-4 DMA1_ACC R/W 3h Defines Access control definition for the DMA1 as:
11: Full Access for both read and Write
10: Protected RD Access such that FIFOs, Clear on read registers
are not changed + No Write Access
01: Reserved
00: No Read/Write Access to peripheral
Reset type: XRSn
3-2 CLA1_ACC R/W 3h Defines Access control definition for the CLA1 as:
11: Full Access for both read and Write
10: Protected RD Access such that FIFOs, Clear on read registers
are not changed + No Write Access
01: Reserved
00: No Read/Write Access to peripheral
Reset type: XRSn
1-0 CPUx_ACC R/W 3h Defines Access control definition for the CPUx as:
11: Full Access for both read and Write
10: Protected RD Access such that FIFOs, Clear on read registers
are not changed + No Write Access
01: Reserved
00: No Read/Write Access to peripheral
Reset type: XRSn

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3.16.7.69 FSIDRX_AC Register (Offset = 1BEh) [Reset = 3Fh]

FSIDRX_AC is shown in Figure 3-167 and described in Table 3-175.
Return to the Summary Table.
Based on control settings allows Full, Protected Read, No Access to peripheral from corresponding connected
master.
Figure 3-167. FSIDRX_AC Register
31 30 29 28 27 26 25 24
RESERVED
R-0-0h

23 22 21 20 19 18 17 16
RESERVED
R-0-0h

15 14 13 12 11 10 9 8
RESERVED
R-0-0h

7 6 5 4 3 2 1 0
RESERVED DMA1_ACC CLA1_ACC CPUx_ACC
R-0-0h R/W-3h R/W-3h R/W-3h

Table 3-175. FSIDRX_AC Register Field Descriptions

Bit Field Type Reset Description
31-6 RESERVED R-0 0h Reserved
5-4 DMA1_ACC R/W 3h Defines Access control definition for the DMA1 as:
11: Full Access for both read and Write
10: Protected RD Access such that FIFOs, Clear on read registers
are not changed + No Write Access
01: Reserved
00: No Read/Write Access to peripheral
Reset type: XRSn
3-2 CLA1_ACC R/W 3h Defines Access control definition for the CLA1 as:
11: Full Access for both read and Write
10: Protected RD Access such that FIFOs, Clear on read registers
are not changed + No Write Access
01: Reserved
00: No Read/Write Access to peripheral
Reset type: XRSn
1-0 CPUx_ACC R/W 3h Defines Access control definition for the CPUx as:
11: Full Access for both read and Write
10: Protected RD Access such that FIFOs, Clear on read registers
are not changed + No Write Access
01: Reserved
00: No Read/Write Access to peripheral
Reset type: XRSn

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3.16.7.70 FSIERX_AC Register (Offset = 1C2h) [Reset = 3Fh]

FSIERX_AC is shown in Figure 3-168 and described in Table 3-176.
Return to the Summary Table.
Based on control settings allows Full, Protected Read, No Access to peripheral from corresponding connected
master.
Figure 3-168. FSIERX_AC Register
31 30 29 28 27 26 25 24
RESERVED
R-0-0h

23 22 21 20 19 18 17 16
RESERVED
R-0-0h

15 14 13 12 11 10 9 8
RESERVED
R-0-0h

7 6 5 4 3 2 1 0
RESERVED DMA1_ACC CLA1_ACC CPUx_ACC
R-0-0h R/W-3h R/W-3h R/W-3h

Table 3-176. FSIERX_AC Register Field Descriptions

Bit Field Type Reset Description
31-6 RESERVED R-0 0h Reserved
5-4 DMA1_ACC R/W 3h Defines Access control definition for the DMA1 as:
11: Full Access for both read and Write
10: Protected RD Access such that FIFOs, Clear on read registers
are not changed + No Write Access
01: Reserved
00: No Read/Write Access to peripheral
Reset type: XRSn
3-2 CLA1_ACC R/W 3h Defines Access control definition for the CLA1 as:
11: Full Access for both read and Write
10: Protected RD Access such that FIFOs, Clear on read registers
are not changed + No Write Access
01: Reserved
00: No Read/Write Access to peripheral
Reset type: XRSn
1-0 CPUx_ACC R/W 3h Defines Access control definition for the CPUx as:
11: Full Access for both read and Write
10: Protected RD Access such that FIFOs, Clear on read registers
are not changed + No Write Access
01: Reserved
00: No Read/Write Access to peripheral
Reset type: XRSn

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3.16.7.71 FSIFRX_AC Register (Offset = 1C6h) [Reset = 3Fh]

FSIFRX_AC is shown in Figure 3-169 and described in Table 3-177.
Return to the Summary Table.
Based on control settings allows Full, Protected Read, No Access to peripheral from corresponding connected
master.
Figure 3-169. FSIFRX_AC Register
31 30 29 28 27 26 25 24
RESERVED
R-0-0h

23 22 21 20 19 18 17 16
RESERVED
R-0-0h

15 14 13 12 11 10 9 8
RESERVED
R-0-0h

7 6 5 4 3 2 1 0
RESERVED DMA1_ACC CLA1_ACC CPUx_ACC
R-0-0h R/W-3h R/W-3h R/W-3h

Table 3-177. FSIFRX_AC Register Field Descriptions

Bit Field Type Reset Description
31-6 RESERVED R-0 0h Reserved
5-4 DMA1_ACC R/W 3h Defines Access control definition for the DMA1 as:
11: Full Access for both read and Write
10: Protected RD Access such that FIFOs, Clear on read registers
are not changed + No Write Access
01: Reserved
00: No Read/Write Access to peripheral
Reset type: XRSn
3-2 CLA1_ACC R/W 3h Defines Access control definition for the CLA1 as:
11: Full Access for both read and Write
10: Protected RD Access such that FIFOs, Clear on read registers
are not changed + No Write Access
01: Reserved
00: No Read/Write Access to peripheral
Reset type: XRSn
1-0 CPUx_ACC R/W 3h Defines Access control definition for the CPUx as:
11: Full Access for both read and Write
10: Protected RD Access such that FIFOs, Clear on read registers
are not changed + No Write Access
01: Reserved
00: No Read/Write Access to peripheral
Reset type: XRSn

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3.16.7.72 FSIGRX_AC Register (Offset = 1CAh) [Reset = 3Fh]

FSIGRX_AC is shown in Figure 3-170 and described in Table 3-178.
Return to the Summary Table.
Based on control settings allows Full, Protected Read, No Access to peripheral from corresponding connected
master.
Figure 3-170. FSIGRX_AC Register
31 30 29 28 27 26 25 24
RESERVED
R-0-0h

23 22 21 20 19 18 17 16
RESERVED
R-0-0h

15 14 13 12 11 10 9 8
RESERVED
R-0-0h

7 6 5 4 3 2 1 0
RESERVED DMA1_ACC CLA1_ACC CPUx_ACC
R-0-0h R/W-3h R/W-3h R/W-3h

Table 3-178. FSIGRX_AC Register Field Descriptions

Bit Field Type Reset Description
31-6 RESERVED R-0 0h Reserved
5-4 DMA1_ACC R/W 3h Defines Access control definition for the DMA1 as:
11: Full Access for both read and Write
10: Protected RD Access such that FIFOs, Clear on read registers
are not changed + No Write Access
01: Reserved
00: No Read/Write Access to peripheral
Reset type: XRSn
3-2 CLA1_ACC R/W 3h Defines Access control definition for the CLA1 as:
11: Full Access for both read and Write
10: Protected RD Access such that FIFOs, Clear on read registers
are not changed + No Write Access
01: Reserved
00: No Read/Write Access to peripheral
Reset type: XRSn
1-0 CPUx_ACC R/W 3h Defines Access control definition for the CPUx as:
11: Full Access for both read and Write
10: Protected RD Access such that FIFOs, Clear on read registers
are not changed + No Write Access
01: Reserved
00: No Read/Write Access to peripheral
Reset type: XRSn

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3.16.7.73 FSIHRX_AC Register (Offset = 1CEh) [Reset = 3Fh]

FSIHRX_AC is shown in Figure 3-171 and described in Table 3-179.
Return to the Summary Table.
Based on control settings allows Full, Protected Read, No Access to peripheral from corresponding connected
master.
Figure 3-171. FSIHRX_AC Register
31 30 29 28 27 26 25 24
RESERVED
R-0-0h

23 22 21 20 19 18 17 16
RESERVED
R-0-0h

15 14 13 12 11 10 9 8
RESERVED
R-0-0h

7 6 5 4 3 2 1 0
RESERVED DMA1_ACC CLA1_ACC CPUx_ACC
R-0-0h R/W-3h R/W-3h R/W-3h

Table 3-179. FSIHRX_AC Register Field Descriptions

Bit Field Type Reset Description
31-6 RESERVED R-0 0h Reserved
5-4 DMA1_ACC R/W 3h Defines Access control definition for the DMA1 as:
11: Full Access for both read and Write
10: Protected RD Access such that FIFOs, Clear on read registers
are not changed + No Write Access
01: Reserved
00: No Read/Write Access to peripheral
Reset type: XRSn
3-2 CLA1_ACC R/W 3h Defines Access control definition for the CLA1 as:
11: Full Access for both read and Write
10: Protected RD Access such that FIFOs, Clear on read registers
are not changed + No Write Access
01: Reserved
00: No Read/Write Access to peripheral
Reset type: XRSn
1-0 CPUx_ACC R/W 3h Defines Access control definition for the CPUx as:
11: Full Access for both read and Write
10: Protected RD Access such that FIFOs, Clear on read registers
are not changed + No Write Access
01: Reserved
00: No Read/Write Access to peripheral
Reset type: XRSn

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3.16.7.74 MCANA_AC Register (Offset = 1D0h) [Reset = 3Fh]

MCANA_AC is shown in Figure 3-172 and described in Table 3-180.
Return to the Summary Table.
Based on control settings allows Full, Protected Read, No Access to peripheral from corresponding connected
master.
Figure 3-172. MCANA_AC Register
31 30 29 28 27 26 25 24
RESERVED
R-0-0h

23 22 21 20 19 18 17 16
RESERVED
R-0-0h

15 14 13 12 11 10 9 8
RESERVED
R-0-0h

7 6 5 4 3 2 1 0
RESERVED DMA1_ACC RESERVED CPUx_ACC
R-0-0h R/W-3h R/W-3h R/W-3h

Table 3-180. MCANA_AC Register Field Descriptions

Bit Field Type Reset Description
31-6 RESERVED R-0 0h Reserved
5-4 DMA1_ACC R/W 3h Defines Access control definition for the DMA1 as:
11: Full Access for both read and Write
10: Protected RD Access such that FIFOs, Clear on read registers
are not changed + No Write Access
01: Reserved
00: No Read/Write Access to peripheral
Reset type: XRSn
3-2 RESERVED R/W 3h Reserved
1-0 CPUx_ACC R/W 3h Defines Access control definition for the CPUx as:
11: Full Access for both read and Write
10: Protected RD Access such that FIFOs, Clear on read registers
are not changed + No Write Access
01: Reserved
00: No Read/Write Access to peripheral
Reset type: XRSn

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3.16.7.75 PERIPH_AC_LOCK Register (Offset = 1FEh) [Reset = 0h]

PERIPH_AC_LOCK is shown in Figure 3-173 and described in Table 3-181.
Return to the Summary Table.
Based on status bit control the Access registers are either RD/WR or RD only.
Figure 3-173. PERIPH_AC_LOCK Register
31 30 29 28 27 26 25 24
RESERVED
R-0-0h

23 22 21 20 19 18 17 16
RESERVED
R-0-0h

15 14 13 12 11 10 9 8
RESERVED
R-0-0h

7 6 5 4 3 2 1 0
RESERVED LOCK_AC_WR
R-0-0h R/WSonce-0h

Table 3-181. PERIPH_AC_LOCK Register Field Descriptions

Bit Field Type Reset Description
31-1 RESERVED R-0 0h Reserved
0 LOCK_AC_WR R/WSonce 0h Defines Access control definition for the CPUx as:
1: Access Control registers are Read Only
0: Read/Write Access allowed to Access Control registers.
Writing '1' sets the bit, writing '0' has no effect.
Reset type: CPUx.SYSRSn

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3.16.8 CPUTIMER_REGS Registers

Table 3-182 lists the memory-mapped registers for the CPUTIMER_REGS registers. All register offset addresses
not listed in Table 3-182 should be considered as reserved locations and the register contents should not be
modified.
Table 3-182. CPUTIMER_REGS Registers
Offset Acronym Register Name Write Protection Section
0h TIM CPU-Timer, Counter Register Go
2h PRD CPU-Timer, Period Register Go
4h TCR CPU-Timer, Control Register Go
6h TPR CPU-Timer, Prescale Register Go
7h TPRH CPU-Timer, Prescale Register High Go

Complex bit access types are encoded to fit into small table cells. Table 3-183 shows the codes that are used for
access types in this section.
Table 3-183. CPUTIMER_REGS Access Type Codes
Access Type Code Description
Read Type
R R Read
Write Type
W W Write
W1C W Write
1C 1 to clear
Reset or Default Value
-n Value after reset or the default
value
Register Array Variables
i,j,k,l,m,n When these variables are used in
a register name, an offset, or an
address, they refer to the value of
a register array where the register
is part of a group of repeating
registers. The register groups
form a hierarchical structure and
the array is represented with a
formula.
y When this variable is used in a
register name, an offset, or an
address it refers to the value of
a register array.

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3.16.8.1 TIM Register (Offset = 0h) [Reset = FFFFh]

TIM is shown in Figure 3-174 and described in Table 3-184.
Return to the Summary Table.
CPU-Timer, Counter Register
Figure 3-174. TIM Register
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
MSW LSW
R/W-0h R/W-FFFFh

Table 3-184. TIM Register Field Descriptions

Bit Field Type Reset Description
31-16 MSW R/W 0h CPU-Timer Counter Registers
The TIMH register holds the high 16 bits of the current 32-bit
count of the timer. The TIMH:TIM decrements by one every
(TDDRH:TDDR+1) clock cycles, where TDDRH:TDDR is the timer
prescale dividedown value. When the TIMH:TIM decrements to zero,
the TIMH:TIM register is reloaded with the period value contained
in the PRDH:PRD registers. The timer interrupt (TINT) signal is
generated.
Reset type: SYSRSn
15-0 LSW R/W FFFFh CPU-Timer Counter Registers
The TIM register holds the low 16 bits of the current 32-bit
count of the timer. The TIMH:TIM decrements by one every
(TDDRH:TDDR+1) clock cycles, where TDDRH:TDDR is the timer
prescale dividedown value. When the TIMH:TIM decrements to zero,
the TIMH:TIM register is reloaded with the period value contained
in the PRDH:PRD registers. The timer interrupt (TINT) signal is
generated.
Reset type: SYSRSn

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3.16.8.2 PRD Register (Offset = 2h) [Reset = FFFFh]

PRD is shown in Figure 3-175 and described in Table 3-185.
Return to the Summary Table.
CPU-Timer, Period Register
Figure 3-175. PRD Register
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
MSW LSW
R/W-0h R/W-FFFFh

Table 3-185. PRD Register Field Descriptions

Bit Field Type Reset Description
31-16 MSW R/W 0h CPU-Timer Period Registers
The PRDH register holds the high 16 bits of the 32-bit period. When
the TIMH:TIM decrements to zero, the TIMH:TIM register is reloaded
with the period value contained in the PRDH:PRD registers, at the
start of the next timer input clock cycle (the output of the prescaler).
The PRDH:PRD contents are also loaded into the TIMH:TIM when
you set the timer reload bit (TRB) in the Timer Control Register
(TCR).
Reset type: SYSRSn
15-0 LSW R/W FFFFh CPU-Timer Period Registers
The PRD register holds the low 16 bits of the 32-bit period. When
the TIMH:TIM decrements to zero, the TIMH:TIM register is reloaded
with the period value contained in the PRDH:PRD registers, at the
start of the next timer input clock cycle (the output of the prescaler).
The PRDH:PRD contents are also loaded into the TIMH:TIM when
you set the timer reload bit (TRB) in the Timer Control Register
(TCR).
Reset type: SYSRSn

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3.16.8.3 TCR Register (Offset = 4h) [Reset = 1h]

TCR is shown in Figure 3-176 and described in Table 3-186.
Return to the Summary Table.
CPU-Timer, Control Register
Figure 3-176. TCR Register
15 14 13 12 11 10 9 8
TIF TIE RESERVED FREE SOFT RESERVED
R/W1C-0h R/W-0h R-0h R/W-0h R/W-0h R-0h

7 6 5 4 3 2 1 0
RESERVED TRB TSS RESERVED
R-0h R/W-0h R/W-0h R-1h

Table 3-186. TCR Register Field Descriptions

Bit Field Type Reset Description
15 TIF R/W1C 0h CPU-Timer Overflow Flag.
TIF indicates whether a timer overflow has happened since TIF was
last cleared. TIF is not cleared automatically and does not need to be
cleared to enable the next timer interrupt.
Reset type: SYSRSn
0h (R/W) = The CPU-Timer has not decremented to zero.
Writes of 0 are ignored.
1h (R/W) = This flag gets set when the CPU-timer decrements to
zero.
Writing a 1 to this bit clears the flag.
14 TIE R/W 0h CPU-Timer Interrupt Enable.
Reset type: SYSRSn
0h (R/W) = The CPU-Timer interrupt is disabled.
1h (R/W) = The CPU-Timer interrupt is enabled. If the timer
decrements to zero, and TIE is set, the timer asserts its interrupt
request.
13-12 RESERVED R 0h Reserved
11 FREE R/W 0h If the FREE bit is set to 1, then, upon a software breakpoint, the
timer continues to run. If FREE is 0, then the SOFT bit controls the
emulation behavior.
Reset type: SYSRSn
0h (R/W) = Stop after the next decrement of the TIMH:TIM (hard
stop)
(SOFT bit controls the emulation behavior)
1h (R/W) = Free Run
(SOFT bit is don't care, counter is free running)
10 SOFT R/W 0h If the FREE bit is set to 1, then, upon a software breakpoint, the
timer continues to run (that is, free runs). In this case, SOFT is a
don't care. But if FREE is 0, then SOFT takes effect.
Reset type: SYSRSn
0h (R/W) = Stop after the next decrement of the TIMH:TIM (hard
stop).
(ONLY if FREE=0, if FREE=1 this bit is don't care)
1h (R/W) = Stop after the TIMH:TIM decrements to 0 (soft stop)
In the SOFT STOP mode, the timer generates an interrupt before
shutting down (since reaching 0 is the interrupt causing condition).
(ONLY if FREE=0, if FREE=1 this bit is don't care)
9-6 RESERVED R 0h Reserved

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Table 3-186. TCR Register Field Descriptions (continued)

Bit Field Type Reset Description
5 TRB R/W 0h Timer reload
Reset type: SYSRSn
0h (R/W) = The TRB bit is always read as zero. Writes of 0 are
ignored.
1h (R/W) = When you write a 1 to TRB, the TIMH:TIM is loaded with
the value in the PRDH:PRD,
and the prescaler counter (PSCH:PSC) is loaded with the value in
the timer dividedown
register (TDDRH:TDDR).
4 TSS R/W 0h CPU-Timer stop status bit.
TSS is a 1-bit flag that stops or starts the CPU-timer.
Reset type: SYSRSn
0h (R/W) = Reads of 0 indicate the CPU-timer is running.
To start or restart the CPU-timer, set TSS to 0. At reset, TSS is
cleared to 0 and the
CPU-timer immediately starts.
1h (R/W) = Reads of 1 indicate that the CPU-timer is stopped.
To stop the CPU-timer, set TSS to 1.
3-0 RESERVED R 1h Reserved

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3.16.8.4 TPR Register (Offset = 6h) [Reset = 0h]

TPR is shown in Figure 3-177 and described in Table 3-187.
Return to the Summary Table.
CPU-Timer, Prescale Register
Figure 3-177. TPR Register
15 14 13 12 11 10 9 8
PSC
R-0h

7 6 5 4 3 2 1 0
TDDR
R/W-0h

Table 3-187. TPR Register Field Descriptions

Bit Field Type Reset Description
15-8 PSC R 0h CPU-Timer Prescale Counter.
These bits hold the current prescale count for the timer. For every
timer clock source cycle that the PSCH:PSC value is greater than
0, the PSCH:PSC decrements by one. One timer clock (output
of the timer prescaler) cycle after the PSCH:PSC reaches 0, the
PSCH:PSC is loaded with the contents of the TDDRH:TDDR, and
the timer counter register (TIMH:TIM) decrements by one. The
PSCH:PSC is also reloaded whenever the timer reload bit (TRB)
is set by software. The PSCH:PSC can be checked by reading the
register, but it cannot be set directly. It must get its value from the
timer divide-down register
(TDDRH:TDDR). At reset, the PSCH:PSC is set to 0.
Reset type: SYSRSn
7-0 TDDR R/W 0h CPU-Timer Divide-Down.
Every (TDDRH:TDDR + 1) timer clock source cycles, the timer
counter register (TIMH:TIM) decrements by one. At reset, the
TDDRH:TDDR bits are cleared to 0. To increase the overall timer
count by an integer factor, write this factor minus one to the
TDDRH:TDDR bits. When the prescaler counter (PSCH:PSC)
value is 0, one timer clock source cycle later, the contents
of the TDDRH:TDDR reload the PSCH:PSC, and the TIMH:TIM
decrements by one. TDDRH:TDDR also reloads the PSCH:PSC
whenever the timer reload bit (TRB) is set by software.
Reset type: SYSRSn

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3.16.8.5 TPRH Register (Offset = 7h) [Reset = 0h]

TPRH is shown in Figure 3-178 and described in Table 3-188.
Return to the Summary Table.
CPU-Timer, Prescale Register High
Figure 3-178. TPRH Register
15 14 13 12 11 10 9 8
PSCH
R-0h

7 6 5 4 3 2 1 0
TDDRH
R/W-0h

Table 3-188. TPRH Register Field Descriptions

Bit Field Type Reset Description
15-8 PSCH R 0h See description of TIMERxTPR.
Reset type: SYSRSn
7-0 TDDRH R/W 0h See description of TIMERxTPR.
Reset type: SYSRSn

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3.16.9 DEV_CFG_REGS Registers

Table 3-189 lists the memory-mapped registers for the DEV_CFG_REGS registers. All register offset addresses
not listed in Table 3-189 should be considered as reserved locations and the register contents should not be
modified.
Table 3-189. DEV_CFG_REGS Registers
Offset Acronym Register Name Write Protection Section
0h DEVCFGLOCK1 Lock bit for DEVCFG registers EALLOW Go
2h DEVCFGLOCK2 Lock bit for DEVCFG registers EALLOW Go
8h PARTIDL Lower 32-bit of Device PART Identification Go
Number
Ah PARTIDH Upper 32-bit of Device PART Identification Go
Number
Ch REVID Device Revision Number Go
60h PERCNF1 Peripheral Configuration register Go
74h FUSEERR e-Fuse error Status register Go
82h SOFTPRES0 Processing Block Software Reset register EALLOW Go
84h SOFTPRES1 EMIF Software Reset register EALLOW Go
86h SOFTPRES2 Peripheral Software Reset register EALLOW Go
88h SOFTPRES3 Peripheral Software Reset register EALLOW Go
8Ah SOFTPRES4 Peripheral Software Reset register EALLOW Go
8Eh SOFTPRES6 Peripheral Software Reset register EALLOW Go
90h SOFTPRES7 Peripheral Software Reset register EALLOW Go
92h SOFTPRES8 Peripheral Software Reset register EALLOW Go
94h SOFTPRES9 Peripheral Software Reset register EALLOW Go
96h SOFTPRES10 Peripheral Software Reset register EALLOW Go
98h SOFTPRES11 Peripheral Software Reset register EALLOW Go
9Ch SOFTPRES13 Peripheral Software Reset register EALLOW Go
9Eh SOFTPRES14 Peripheral Software Reset register EALLOW Go
A2h SOFTPRES16 Peripheral Software Reset register EALLOW Go
A4h SOFTPRES17 Reserved Peripheral Software Reset register EALLOW Go
A6h SOFTPRES18 Reserved Peripheral Software Reset register EALLOW Go
AAh SOFTPRES20 Peripheral Software Reset register EALLOW Go
ACh SOFTPRES21 Peripheral Software Reset register EALLOW Go
B0h SOFTPRES23 Peripheral Software Reset register EALLOW Go
D6h CPUSEL0 CPU Select register for common peripherals EALLOW Go
D8h CPUSEL1 CPU Select register for common peripherals EALLOW Go
DAh CPUSEL2 CPU Select register for common peripherals EALLOW Go
DEh CPUSEL4 CPU Select register for common peripherals EALLOW Go
E0h CPUSEL5 CPU Select register for common peripherals EALLOW Go
E2h CPUSEL6 CPU Select register for common peripherals EALLOW Go
E4h CPUSEL7 CPU Select register for common peripherals EALLOW Go
E6h CPUSEL8 CPU Select register for common peripherals EALLOW Go
E8h CPUSEL9 CPU Select register for common peripherals EALLOW Go
ECh CPUSEL11 CPU Select register for common peripherals EALLOW Go
EEh CPUSEL12 CPU Select register for common peripherals EALLOW Go
F2h CPUSEL14 CPU Select register for common peripherals EALLOW Go
F4h CPUSEL15 CPU Select register for common peripherals EALLOW Go

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Table 3-189. DEV_CFG_REGS Registers (continued)

Offset Acronym Register Name Write Protection Section
F6h CPUSEL16 CPU Select register for common peripherals EALLOW Go
FAh CPUSEL18 CPU Select register for common peripherals EALLOW Go
108h CPUSEL25 CPU Select register for common peripherals EALLOW Go
122h CPU2RESCTL CPU2 Reset Control Register EALLOW Go
124h RSTSTAT Reset Status register for secondary C28x CPUs Go
125h LPMSTAT LPM Status Register for secondary C28x CPUs Go
19Ah USBTYPE Configures USB Type for the device EALLOW Go
19Bh ECAPTYPE Configures ECAP Type for the device EALLOW Go
19Ch SDFMTYPE Configures SDFM Type for the device EALLOW Go
19Eh MEMMAPTYPE Configures Memory Map Type for the device EALLOW Go

Complex bit access types are encoded to fit into small table cells. Table 3-190 shows the codes that are used for
access types in this section.
Table 3-190. DEV_CFG_REGS Access Type Codes
Access Type Code Description
Read Type
R R Read
R-0 R Read
-0 Returns 0s
Write Type
W W Write
W1S W Write
1S 1 to set
WOnce W Write
Once Write once
WSonce W Write
Sonce Set once
Reset or Default Value
-n Value after reset or the default
value
Register Array Variables
i,j,k,l,m,n When these variables are used in
a register name, an offset, or an
address, they refer to the value of
a register array where the register
is part of a group of repeating
registers. The register groups
form a hierarchical structure and
the array is represented with a
formula.
y When this variable is used in a
register name, an offset, or an
address it refers to the value of
a register array.

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3.16.9.1 DEVCFGLOCK1 Register (Offset = 0h) [Reset = 0h]

DEVCFGLOCK1 is shown in Figure 3-179 and described in Table 3-191.
Return to the Summary Table.
Lock bit for DEVCFG registers
The locking mechanism applies to only writes. Reads to the registers which have LOCK protection are always
allowed
Note:
Any SOnce bit in this register, once set can only be cleared through a CPU1.SYSRSn. Write of 0 to any bit of
this register has no effect
Figure 3-179. DEVCFGLOCK1 Register
31 30 29 28 27 26 25 24
RESERVED CPUSEL25 RESERVED
R-0-0h R/WSonce-0h R-0-0h

23 22 21 20 19 18 17 16
RESERVED CPUSEL18 RESERVED CPUSEL16
R-0-0h R/WSonce-0h R/WSonce-0h R/WSonce-0h

15 14 13 12 11 10 9 8
CPUSEL15 CPUSEL14 RESERVED CPUSEL12 CPUSEL11 RESERVED CPUSEL9 CPUSEL8
R/WSonce-0h R/WSonce-0h R/WSonce-0h R/WSonce-0h R/WSonce-0h R/WSonce-0h R/WSonce-0h R/WSonce-0h

7 6 5 4 3 2 1 0
CPUSEL7 CPUSEL6 CPUSEL5 CPUSEL4 RESERVED CPUSEL2 CPUSEL1 CPUSEL0
R/WSonce-0h R/WSonce-0h R/WSonce-0h R/WSonce-0h R/WSonce-0h R/WSonce-0h R/WSonce-0h R/WSonce-0h

Table 3-191. DEVCFGLOCK1 Register Field Descriptions

Bit Field Type Reset Description
31-26 RESERVED R-0 0h Reserved
25 CPUSEL25 R/WSonce 0h Lock bit for CPUSEL25 register:
0: Register is not locked
1: Register is locked.
Reset type: CPU1.SYSRSn
24-19 RESERVED R-0 0h Reserved
18 CPUSEL18 R/WSonce 0h Lock bit for CPUSEL18 register:
0: Register is not locked
1: Register is locked.
Reset type: CPU1.SYSRSn
17 RESERVED R/WSonce 0h Reserved
16 CPUSEL16 R/WSonce 0h Lock bit for CPUSEL16 register:
0: Register is not locked
1: Register is locked.
Reset type: CPU1.SYSRSn
15 CPUSEL15 R/WSonce 0h Lock bit for CPUSEL15 register:
0: Register is not locked
1: Register is locked.
Reset type: CPU1.SYSRSn
14 CPUSEL14 R/WSonce 0h Lock bit for CPUSEL14 register:
0: Register is not locked
1: Register is locked.
Reset type: CPU1.SYSRSn
13 RESERVED R/WSonce 0h Reserved

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Table 3-191. DEVCFGLOCK1 Register Field Descriptions (continued)

Bit Field Type Reset Description
12 CPUSEL12 R/WSonce 0h Lock bit for CPUSEL12 register:
0: Register is not locked
1: Register is locked.
Reset type: CPU1.SYSRSn
11 CPUSEL11 R/WSonce 0h Lock bit for CPUSEL11 register:
0: Register is not locked
1: Register is locked.
Reset type: CPU1.SYSRSn
10 RESERVED R/WSonce 0h Reserved
9 CPUSEL9 R/WSonce 0h Lock bit for CPUSEL9 register:
0: Register is not locked
1: Register is locked.
Reset type: CPU1.SYSRSn
8 CPUSEL8 R/WSonce 0h Lock bit for CPUSEL8 register:
0: Register is not locked
1: Register is locked.
Reset type: CPU1.SYSRSn
7 CPUSEL7 R/WSonce 0h Lock bit for CPUSEL7 register:
0: Register is not locked
1: Register is locked.
Reset type: CPU1.SYSRSn
6 CPUSEL6 R/WSonce 0h Lock bit for CPUSEL6 register:
0: Register is not locked
1: Register is locked.
Reset type: CPU1.SYSRSn
5 CPUSEL5 R/WSonce 0h Lock bit for CPUSEL5 register:
0: Register is not locked
1: Register is locked.
Reset type: CPU1.SYSRSn
4 CPUSEL4 R/WSonce 0h Lock bit for CPUSEL4 register:
0: Register is not locked
1: Register is locked.
Reset type: CPU1.SYSRSn
3 RESERVED R/WSonce 0h Reserved
2 CPUSEL2 R/WSonce 0h Lock bit for CPUSEL2 register:
0: Register is not locked
1: Register is locked.
Reset type: CPU1.SYSRSn
1 CPUSEL1 R/WSonce 0h Lock bit for CPUSEL1 register:
0: Register is not locked
1: Register is locked.
Reset type: CPU1.SYSRSn
0 CPUSEL0 R/WSonce 0h Lock bit for CPUSEL0 register:
0: Register is not locked
1: Register is locked.
Reset type: CPU1.SYSRSn

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3.16.9.2 DEVCFGLOCK2 Register (Offset = 2h) [Reset = 0h]

DEVCFGLOCK2 is shown in Figure 3-180 and described in Table 3-192.
Return to the Summary Table.
Lock bit for DEVCFG registers
The locking mechanism applies to only writes. Reads to the registers which have LOCK protection are always
allowed
Note:
Any SOnce bit in this register, once set can only be cleared through a CPU1.SYSRSn. Write of 0 to any bit of
this register has no effect
Figure 3-180. DEVCFGLOCK2 Register
31 30 29 28 27 26 25 24
RESERVED
R-0-0h

23 22 21 20 19 18 17 16
RESERVED
R-0-0h

15 14 13 12 11 10 9 8
RESERVED
R-0-0h

7 6 5 4 3 2 1 0
RESERVED RESERVED RESERVED
R-0-0h R/WSonce-0h R/WSonce-0h

Table 3-192. DEVCFGLOCK2 Register Field Descriptions

Bit Field Type Reset Description
31-2 RESERVED R-0 0h Reserved
1 RESERVED R/WSonce 0h Reserved
0 RESERVED R/WSonce 0h Reserved

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3.16.9.3 PARTIDL Register (Offset = 8h) [Reset = X]

PARTIDL is shown in Figure 3-181 and described in Table 3-193.
Return to the Summary Table.
Lower 32-bit of Device PART Identification Number
Figure 3-181. PARTIDL Register
31 30 29 28 27 26 25 24
PARTID_FORMAT_REVISION RESERVED
R/W-2h R-0h

23 22 21 20 19 18 17 16
FLASH_SIZE
R/W-7h

15 14 13 12 11 10 9 8
RESERVED INSTASPIN RESERVED RESERVED PIN_COUNT
R-0h R/W-1h R/W-0h R/W-0h R/W-X

7 6 5 4 3 2 1 0
QUAL RESERVED RESERVED RESERVED
R/W-X R-0h R/W-0h R/W-0h

Table 3-193. PARTIDL Register Field Descriptions

Bit Field Type Reset Description
31-28 PARTID_FORMAT_REVIS R/W 2h Loaded from OTP by boot ROM
ION 0xF = invalid PART ID (assume max config in flash tools)
0x0 = first revision of part id format
0x1 = second revision of format
0x2 = third revision of part id format
Reset type: PORESETn
27-24 RESERVED R 0h Reserved
23-16 FLASH_SIZE R/W 7h 0x8 - 1024KB
0x7 - 512KB
0x6 - 256KB
0x5 - 128KB
0x4 - 64KB
0x3 - 32KB
Reset type: PORESETn
15 RESERVED R 0h Reserved
14-13 INSTASPIN R/W 1h 0 = InstaSPIN Motion (Fast+Spin)
1 = InstaSPIN-FOC
2 = NONE
3 = NONE
Reset type: PORESETn
12 RESERVED R/W 0h Reserved
11 RESERVED R/W 0h Reserved
10-8 PIN_COUNT R/W X 0 = 56 pin (Reserved)
1 = 64 pin (Q100)
2 = 64 pin
3 = 80 pin
4 = 48 pin
5 = 100 pin (Reserved)
6 = 176 pin
7 = 337 pin
Reset type: PORESETn

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Table 3-193. PARTIDL Register Field Descriptions (continued)

Bit Field Type Reset Description
7-6 QUAL R/W X 0 = Engineering sample.(TMX)
1 = Pilot production (TMP)
2 = Fully qualified (TMS)
Reset type: PORESETn
5 RESERVED R 0h Reserved
4-3 RESERVED R/W 0h Reserved
2-0 RESERVED R/W 0h Reserved

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3.16.9.4 PARTIDH Register (Offset = Ah) [Reset = X]

PARTIDH is shown in Figure 3-182 and described in Table 3-194.
Return to the Summary Table.
Upper 32-bit of Device PART Identification Number
Figure 3-182. PARTIDH Register
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
DEVICE_CLASS_ID PARTNO
R-3h R/W-X

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FAMILY RESERVED RESERVED
R/W-X R-0h R-0h

Table 3-194. PARTIDH Register Field Descriptions

Bit Field Type Reset Description
31-24 DEVICE_CLASS_ID R 3h Device Class ID
Reset type: PORESETn
23-16 PARTNO R/W X Part Number Designator
0xFF - F28388x
0xFD - F28386x
0xFB - F28384x
Reset type: PORESETn
15-8 FAMILY R/W X Device Family
0x3 - DUAL CORE
0x4 - SINGLE CORE
Other values Reserved
Reset type: PORESETn
Reset type: PORESETn
7-4 RESERVED R 0h Reserved
3-0 RESERVED R 0h Reserved

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3.16.9.5 REVID Register (Offset = Ch) [Reset = 0h]

REVID is shown in Figure 3-183 and described in Table 3-195.
Return to the Summary Table.
Device Revision Number
Figure 3-183. REVID Register
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RESERVED REVID
R-0-0h R-0h

Table 3-195. REVID Register Field Descriptions

Bit Field Type Reset Description
31-16 RESERVED R-0 0h Reserved
15-0 REVID R 0h These 32-bits specify the silicon revision. See your device specific
datasheet for details.
Reset type: N/A

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3.16.9.6 PERCNF1 Register (Offset = 60h) [Reset = 0h]

PERCNF1 is shown in Figure 3-184 and described in Table 3-196.
Return to the Summary Table.
Peripheral Configuration register
Figure 3-184. PERCNF1 Register
31 30 29 28 27 26 25 24
RESERVED
R-0-0h

23 22 21 20 19 18 17 16
RESERVED RESERVED USB_A_PHY
R-0-0h R/W-0h R/W-0h

15 14 13 12 11 10 9 8
RESERVED
R-0-0h

7 6 5 4 3 2 1 0
RESERVED ADC_D_MODE ADC_C_MODE ADC_B_MODE ADC_A_MODE
R-0-0h R/W-0h R/W-0h R/W-0h R/W-0h

Table 3-196. PERCNF1 Register Field Descriptions

Bit Field Type Reset Description
31-18 RESERVED R-0 0h Reserved
17 RESERVED R/W 0h Reserved
16 USB_A_PHY R/W 0h Internal PHY is present present or not for the USB_A module:
0: Internal USB PHY Module is not present
1: Internal USB PHY Module is present.
Reset type: PORESETn
15-4 RESERVED R-0 0h Reserved
3 ADC_D_MODE R/W 0h 0: 16-bit or 12-bit configurable in software
1: Only 12-bit operation available
Reset type: PORESETn
2 ADC_C_MODE R/W 0h 0: 16-bit or 12-bit configurable in software
1: Only 12-bit operation available
Reset type: PORESETn
1 ADC_B_MODE R/W 0h 0: 16-bit or 12-bit configurable in software
1: Only 12-bit operation available
Reset type: PORESETn
0 ADC_A_MODE R/W 0h 0: 16-bit or 12-bit configurable in software
1: Only 12-bit operation available
Reset type: PORESETn

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3.16.9.7 FUSEERR Register (Offset = 74h) [Reset = 0h]

FUSEERR is shown in Figure 3-185 and described in Table 3-197.
Return to the Summary Table.
e-Fuse error Status register
Figure 3-185. FUSEERR Register
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
RESERVED
R-0-0h

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RESERVED ERR ALERR
R-0-0h R-0h R-0h

Table 3-197. FUSEERR Register Field Descriptions

Bit Field Type Reset Description
31-16 RESERVED R-0 0h Reserved
15-6 RESERVED R-0 0h Reserved
5 ERR R 0h Efuse Self Test Error Status set by hardware after fuse self test
completes, in case of self test error
0: No error during fuse self test
1: Fuse self test error
Reset type: XRSn
4-0 ALERR R 0h Efuse Autoload Error Status set by hardware after fuse auto load
completes
00000: No error in auto load
Other: Non zero value indicates error in autoload
Note:
[1] 10101 means a single-bit error during autoload. Since this gets
corrected by the ECC mechanism, this value shouldn't be treated as
an error condition.
Reset type: XRSn

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3.16.9.8 SOFTPRES0 Register (Offset = 82h) [Reset = 0h]

SOFTPRES0 is shown in Figure 3-186 and described in Table 3-198.
Return to the Summary Table.
Processing Block Software Reset register
When bits in this register are set, the respective module is in reset. All design data is lost and the module
registers are returned to their reset states. Bits must be manually cleared after being set.
Figure 3-186. SOFTPRES0 Register
31 30 29 28 27 26 25 24
RESERVED CPU2_ERAD CPU1_ERAD
R-0-0h R/W-0h R/W-0h

23 22 21 20 19 18 17 16
RESERVED RESERVED CPU2_CLA1BG CPU2_CPUBG
CRC CRC
R-0-0h R/W-0h R/W-0h R/W-0h

15 14 13 12 11 10 9 8
RESERVED CPU1_CLA1BG CPU1_CPUBG RESERVED
CRC CRC
R/W-0h R/W-0h R/W-0h R-0-0h

7 6 5 4 3 2 1 0
RESERVED RESERVED CPU2_CLA1 RESERVED CPU1_CLA1
R-0-0h R/W-0h R/W-0h R/W-0h R/W-0h

Table 3-198. SOFTPRES0 Register Field Descriptions

Bit Field Type Reset Description
31-26 RESERVED R-0 0h Reserved
25 CPU2_ERAD R/W 0h 1: Module is under reset
0: Module reset is determined by the normal device reset structure
Reset type: CPU1.SYSRSn
24 CPU1_ERAD R/W 0h 1: Module is under reset
0: Module reset is determined by the normal device reset structure
Reset type: CPU1.SYSRSn
23-19 RESERVED R-0 0h Reserved
18 RESERVED R/W 0h Reserved
17 CPU2_CLA1BGCRC R/W 0h 1: Module is under reset
0: Module reset is determined by the normal device reset structure
Reset type: CPU1.SYSRSn
16 CPU2_CPUBGCRC R/W 0h 1: Module is under reset
0: Module reset is determined by the normal device reset structure
Reset type: CPU1.SYSRSn
15 RESERVED R/W 0h Reserved
14 CPU1_CLA1BGCRC R/W 0h 1: Module is under reset
0: Module reset is determined by the normal device reset structure
Reset type: CPU1.SYSRSn
13 CPU1_CPUBGCRC R/W 0h 1: Module is under reset
0: Module reset is determined by the normal device reset structure
Reset type: CPU1.SYSRSn
12-4 RESERVED R-0 0h Reserved
3 RESERVED R/W 0h Reserved
2 CPU2_CLA1 R/W 0h 1: Module is under reset
0: Module reset is determined by the normal device reset structure
Reset type: CPU1.SYSRSn

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Table 3-198. SOFTPRES0 Register Field Descriptions (continued)

Bit Field Type Reset Description
1 RESERVED R/W 0h Reserved
0 CPU1_CLA1 R/W 0h 1: Module is under reset
0: Module reset is determined by the normal device reset structure
Reset type: CPU1.SYSRSn

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3.16.9.9 SOFTPRES1 Register (Offset = 84h) [Reset = 0h]

SOFTPRES1 is shown in Figure 3-187 and described in Table 3-199.
Return to the Summary Table.
Processing Block Software Reset register
When bits in this register are set, the respective module is in reset. All design data is lost and the module
registers are returned to their reset states. Bits must be manually cleared after being set.
Figure 3-187. SOFTPRES1 Register
31 30 29 28 27 26 25 24
RESERVED
R-0-0h

23 22 21 20 19 18 17 16
RESERVED
R-0-0h

15 14 13 12 11 10 9 8
RESERVED
R-0-0h

7 6 5 4 3 2 1 0
RESERVED EMIF2 EMIF1
R-0-0h R/W-0h R/W-0h

Table 3-199. SOFTPRES1 Register Field Descriptions

Bit Field Type Reset Description
31-16 RESERVED R-0 0h Reserved
15-2 RESERVED R-0 0h Reserved
1 EMIF2 R/W 0h When this bit is set, only the control logic of the respective EMIF2 is
reset. It does not reset the internal registers except the Total Access
register and the Total Activate register. Refer to EMIF chapter for
more details on the EMIF SOFTRESET feature. This bit must be
manually cleared after being set.
1: EMIF2 is under SOFTRESET
0: Module reset is determined by the normal device reset structure
Reset type: CPU1.SYSRSn
0 EMIF1 R/W 0h When this bit is set, only the control logic of the respective EMIF1 is
reset. It does not reset the internal registers except the Total Access
register and the Total Activate register. Refer to EMIF chapter for
more details on the EMIF SOFTRESET feature. This bit must be
manually cleared after being set.
1: EMIF1 is under SOFTRESET
0: Module reset is determined by the normal device reset structure
Reset type: CPU1.SYSRSn

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3.16.9.10 SOFTPRES2 Register (Offset = 86h) [Reset = 0h]

SOFTPRES2 is shown in Figure 3-188 and described in Table 3-200.
Return to the Summary Table.
Processing Block Software Reset register
When bits in this register are set, the respective module is in reset. All design data is lost and the module
registers are returned to their reset states. Bits must be manually cleared after being set.
Figure 3-188. SOFTPRES2 Register
31 30 29 28 27 26 25 24
RESERVED
R-0-0h

23 22 21 20 19 18 17 16
RESERVED
R-0-0h

15 14 13 12 11 10 9 8
EPWM16 EPWM15 EPWM14 EPWM13 EPWM12 EPWM11 EPWM10 EPWM9
R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h

7 6 5 4 3 2 1 0
EPWM8 EPWM7 EPWM6 EPWM5 EPWM4 EPWM3 EPWM2 EPWM1
R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h

Table 3-200. SOFTPRES2 Register Field Descriptions

Bit Field Type Reset Description
31-16 RESERVED R-0 0h Reserved
15 EPWM16 R/W 0h 1: Module is under reset
0: Module reset is determined by the normal device reset structure
Reset type: CPU1.SYSRSn
14 EPWM15 R/W 0h 1: Module is under reset
0: Module reset is determined by the normal device reset structure
Reset type: CPU1.SYSRSn
13 EPWM14 R/W 0h 1: Module is under reset
0: Module reset is determined by the normal device reset structure
Reset type: CPU1.SYSRSn
12 EPWM13 R/W 0h 1: Module is under reset
0: Module reset is determined by the normal device reset structure
Reset type: CPU1.SYSRSn
11 EPWM12 R/W 0h 1: Module is under reset
0: Module reset is determined by the normal device reset structure
Reset type: CPU1.SYSRSn
10 EPWM11 R/W 0h 1: Module is under reset
0: Module reset is determined by the normal device reset structure
Reset type: CPU1.SYSRSn
9 EPWM10 R/W 0h 1: Module is under reset
0: Module reset is determined by the normal device reset structure
Reset type: CPU1.SYSRSn
8 EPWM9 R/W 0h 1: Module is under reset
0: Module reset is determined by the normal device reset structure
Reset type: CPU1.SYSRSn
7 EPWM8 R/W 0h 1: Module is under reset
0: Module reset is determined by the normal device reset structure
Reset type: CPU1.SYSRSn

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Table 3-200. SOFTPRES2 Register Field Descriptions (continued)

Bit Field Type Reset Description
6 EPWM7 R/W 0h 1: Module is under reset
0: Module reset is determined by the normal device reset structure
Reset type: CPU1.SYSRSn
5 EPWM6 R/W 0h 1: Module is under reset
0: Module reset is determined by the normal device reset structure
Reset type: CPU1.SYSRSn
4 EPWM5 R/W 0h 1: Module is under reset
0: Module reset is determined by the normal device reset structure
Reset type: CPU1.SYSRSn
3 EPWM4 R/W 0h 1: Module is under reset
0: Module reset is determined by the normal device reset structure
Reset type: CPU1.SYSRSn
2 EPWM3 R/W 0h 1: Module is under reset
0: Module reset is determined by the normal device reset structure
Reset type: CPU1.SYSRSn
1 EPWM2 R/W 0h 1: Module is under reset
0: Module reset is determined by the normal device reset structure
Reset type: CPU1.SYSRSn
0 EPWM1 R/W 0h 1: Module is under reset
0: Module reset is determined by the normal device reset structure
Reset type: CPU1.SYSRSn

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3.16.9.11 SOFTPRES3 Register (Offset = 88h) [Reset = 0h]

SOFTPRES3 is shown in Figure 3-189 and described in Table 3-201.
Return to the Summary Table.
Processing Block Software Reset register
When bits in this register are set, the respective module is in reset. All design data is lost and the module
registers are returned to their reset states. Bits must be manually cleared after being set.
Figure 3-189. SOFTPRES3 Register
31 30 29 28 27 26 25 24
RESERVED
R-0-0h

23 22 21 20 19 18 17 16
RESERVED
R-0-0h

15 14 13 12 11 10 9 8
RESERVED
R-0-0h

7 6 5 4 3 2 1 0
RESERVED ECAP7 ECAP6 ECAP5 ECAP4 ECAP3 ECAP2 ECAP1
R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h

Table 3-201. SOFTPRES3 Register Field Descriptions

Bit Field Type Reset Description
31-16 RESERVED R-0 0h Reserved
15-8 RESERVED R-0 0h Reserved
7 RESERVED R/W 0h Reserved
6 ECAP7 R/W 0h 1: Module is under reset
0: Module reset is determined by the normal device reset structure
Reset type: CPU1.SYSRSn
5 ECAP6 R/W 0h 1: Module is under reset
0: Module reset is determined by the normal device reset structure
Reset type: CPU1.SYSRSn
4 ECAP5 R/W 0h 1: Module is under reset
0: Module reset is determined by the normal device reset structure
Reset type: CPU1.SYSRSn
3 ECAP4 R/W 0h 1: Module is under reset
0: Module reset is determined by the normal device reset structure
Reset type: CPU1.SYSRSn
2 ECAP3 R/W 0h 1: Module is under reset
0: Module reset is determined by the normal device reset structure
Reset type: CPU1.SYSRSn
1 ECAP2 R/W 0h 1: Module is under reset
0: Module reset is determined by the normal device reset structure
Reset type: CPU1.SYSRSn
0 ECAP1 R/W 0h 1: Module is under reset
0: Module reset is determined by the normal device reset structure
Reset type: CPU1.SYSRSn

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3.16.9.12 SOFTPRES4 Register (Offset = 8Ah) [Reset = 0h]

SOFTPRES4 is shown in Figure 3-190 and described in Table 3-202.
Return to the Summary Table.
Processing Block Software Reset register
When bits in this register are set, the respective module is in reset. All design data is lost and the module
registers are returned to their reset states. Bits must be manually cleared after being set.
Figure 3-190. SOFTPRES4 Register
31 30 29 28 27 26 25 24
RESERVED
R-0-0h

23 22 21 20 19 18 17 16
RESERVED
R-0-0h

15 14 13 12 11 10 9 8
RESERVED
R-0-0h

7 6 5 4 3 2 1 0
RESERVED RESERVED EQEP3 EQEP2 EQEP1
R-0-0h R/W-0h R/W-0h R/W-0h R/W-0h

Table 3-202. SOFTPRES4 Register Field Descriptions

Bit Field Type Reset Description
31-16 RESERVED R-0 0h Reserved
15-4 RESERVED R-0 0h Reserved
3 RESERVED R/W 0h Reserved
2 EQEP3 R/W 0h 1: Module is under reset
0: Module reset is determined by the normal device reset structure
Reset type: CPU1.SYSRSn
1 EQEP2 R/W 0h 1: Module is under reset
0: Module reset is determined by the normal device reset structure
Reset type: CPU1.SYSRSn
0 EQEP1 R/W 0h 1: Module is under reset
0: Module reset is determined by the normal device reset structure
Reset type: CPU1.SYSRSn

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3.16.9.13 SOFTPRES6 Register (Offset = 8Eh) [Reset = 0h]

SOFTPRES6 is shown in Figure 3-191 and described in Table 3-203.
Return to the Summary Table.
Processing Block Software Reset register
When bits in this register are set, the respective module is in reset. All design data is lost and the module
registers are returned to their reset states. Bits must be manually cleared after being set.
Figure 3-191. SOFTPRES6 Register
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
RESERVED
R-0-0h

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RESERVED RESE RESE RESE RESE RESE RESE SD2 SD1
RVED RVED RVED RVED RVED RVED
R-0-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h

Table 3-203. SOFTPRES6 Register Field Descriptions

Bit Field Type Reset Description
31-16 RESERVED R-0 0h Reserved
15-8 RESERVED R-0 0h Reserved
7 RESERVED R/W 0h Reserved
6 RESERVED R/W 0h Reserved
5 RESERVED R/W 0h Reserved
4 RESERVED R/W 0h Reserved
3 RESERVED R/W 0h Reserved
2 RESERVED R/W 0h Reserved
1 SD2 R/W 0h 1: Module is under reset
0: Module reset is determined by the normal device reset structure
Reset type: CPU1.SYSRSn
0 SD1 R/W 0h 1: Module is under reset
0: Module reset is determined by the normal device reset structure
Reset type: CPU1.SYSRSn

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3.16.9.14 SOFTPRES7 Register (Offset = 90h) [Reset = 0h]

SOFTPRES7 is shown in Figure 3-192 and described in Table 3-204.
Return to the Summary Table.
Processing Block Software Reset register
When bits in this register are set, the respective module is in reset. All design data is lost and the module
registers are returned to their reset states. Bits must be manually cleared after being set.
Figure 3-192. SOFTPRES7 Register
31 30 29 28 27 26 25 24
RESERVED
R-0-0h

23 22 21 20 19 18 17 16
RESERVED
R-0-0h

15 14 13 12 11 10 9 8
RESERVED
R-0-0h

7 6 5 4 3 2 1 0
RESERVED SCI_D SCI_C SCI_B SCI_A
R-0-0h R/W-0h R/W-0h R/W-0h R/W-0h

Table 3-204. SOFTPRES7 Register Field Descriptions

Bit Field Type Reset Description
31-16 RESERVED R-0 0h Reserved
15-4 RESERVED R-0 0h Reserved
3 SCI_D R/W 0h 1: Module is under reset
0: Module reset is determined by the normal device reset structure
Reset type: CPU1.SYSRSn
2 SCI_C R/W 0h 1: Module is under reset
0: Module reset is determined by the normal device reset structure
Reset type: CPU1.SYSRSn
1 SCI_B R/W 0h 1: Module is under reset
0: Module reset is determined by the normal device reset structure
Reset type: CPU1.SYSRSn
0 SCI_A R/W 0h 1: Module is under reset
0: Module reset is determined by the normal device reset structure
Reset type: CPU1.SYSRSn

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3.16.9.15 SOFTPRES8 Register (Offset = 92h) [Reset = 0h]

SOFTPRES8 is shown in Figure 3-193 and described in Table 3-205.
Return to the Summary Table.
Processing Block Software Reset register
When bits in this register are set, the respective module is in reset. All design data is lost and the module
registers are returned to their reset states. Bits must be manually cleared after being set.
Figure 3-193. SOFTPRES8 Register
31 30 29 28 27 26 25 24
RESERVED
R-0-0h

23 22 21 20 19 18 17 16
RESERVED RESERVED RESERVED
R-0-0h R/W-0h R/W-0h

15 14 13 12 11 10 9 8
RESERVED
R-0-0h

7 6 5 4 3 2 1 0
RESERVED SPI_D SPI_C SPI_B SPI_A
R-0-0h R/W-0h R/W-0h R/W-0h R/W-0h

Table 3-205. SOFTPRES8 Register Field Descriptions

Bit Field Type Reset Description
31-18 RESERVED R-0 0h Reserved
17 RESERVED R/W 0h Reserved
16 RESERVED R/W 0h Reserved
15-4 RESERVED R-0 0h Reserved
3 SPI_D R/W 0h 1: Module is under reset
0: Module reset is determined by the normal device reset structure
Reset type: CPU1.SYSRSn
2 SPI_C R/W 0h 1: Module is under reset
0: Module reset is determined by the normal device reset structure
Reset type: CPU1.SYSRSn
1 SPI_B R/W 0h 1: Module is under reset
0: Module reset is determined by the normal device reset structure
Reset type: CPU1.SYSRSn
0 SPI_A R/W 0h 1: Module is under reset
0: Module reset is determined by the normal device reset structure
Reset type: CPU1.SYSRSn

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3.16.9.16 SOFTPRES9 Register (Offset = 94h) [Reset = 0h]

SOFTPRES9 is shown in Figure 3-194 and described in Table 3-206.
Return to the Summary Table.
Processing Block Software Reset register
When bits in this register are set, the respective module is in reset. All design data is lost and the module
registers are returned to their reset states. Bits must be manually cleared after being set.
Figure 3-194. SOFTPRES9 Register
31 30 29 28 27 26 25 24
RESERVED
R-0-0h

23 22 21 20 19 18 17 16
RESERVED
R-0-0h

15 14 13 12 11 10 9 8
RESERVED
R-0-0h

7 6 5 4 3 2 1 0
RESERVED I2C_B I2C_A
R-0-0h R/W-0h R/W-0h

Table 3-206. SOFTPRES9 Register Field Descriptions

Bit Field Type Reset Description
31-16 RESERVED R-0 0h Reserved
15-2 RESERVED R-0 0h Reserved
1 I2C_B R/W 0h 1: Module is under reset
0: Module reset is determined by the normal device reset structure
Reset type: CPU1.SYSRSn
0 I2C_A R/W 0h 1: Module is under reset
0: Module reset is determined by the normal device reset structure
Reset type: CPU1.SYSRSn

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3.16.9.17 SOFTPRES10 Register (Offset = 96h) [Reset = 0h]

SOFTPRES10 is shown in Figure 3-195 and described in Table 3-207.
Return to the Summary Table.
Peripheral Software Reset register
When bits in this register are set, the respective peripheral is in reset. All data is lost and the peripheral registers
are returned to their reset states. Bits must be manually cleared after being set.
Figure 3-195. SOFTPRES10 Register
31 30 29 28 27 26 25 24
RESERVED
R-0-0h

23 22 21 20 19 18 17 16
RESERVED
R-0-0h

15 14 13 12 11 10 9 8
RESERVED
R-0-0h

7 6 5 4 3 2 1 0
RESERVED MCAN_A RESERVED RESERVED CAN_B CAN_A
R-0-0h R/W-0h R/W-0h R-0-0h R/W-0h R/W-0h

Table 3-207. SOFTPRES10 Register Field Descriptions

Bit Field Type Reset Description
31-5 RESERVED R-0 0h Reserved
4 MCAN_A R/W 0h 1: Module is under reset
0: Module reset is determined by the normal device reset structure
Reset type: CPU1.SYSRSn
3 RESERVED R/W 0h Reserved
2 RESERVED R-0 0h Reserved
1 CAN_B R/W 0h 1: Module is under reset
0: Module reset is determined by the normal device reset structure
Reset type: CPU1.SYSRSn
0 CAN_A R/W 0h 1: Module is under reset
0: Module reset is determined by the normal device reset structure
Reset type: CPU1.SYSRSn

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3.16.9.18 SOFTPRES11 Register (Offset = 98h) [Reset = 0h]

SOFTPRES11 is shown in Figure 3-196 and described in Table 3-208.
Return to the Summary Table.
Processing Block Software Reset register
When bits in this register are set, the respective module is in reset. All design data is lost and the module
registers are returned to their reset states. Bits must be manually cleared after being set.
Figure 3-196. SOFTPRES11 Register
31 30 29 28 27 26 25 24
RESERVED
R-0-0h

23 22 21 20 19 18 17 16
RESERVED RESERVED USB_A
R-0-0h R/W-0h R/W-0h

15 14 13 12 11 10 9 8
RESERVED
R-0-0h

7 6 5 4 3 2 1 0
RESERVED McBSP_B McBSP_A
R-0-0h R/W-0h R/W-0h

Table 3-208. SOFTPRES11 Register Field Descriptions

Bit Field Type Reset Description
31-18 RESERVED R-0 0h Reserved
17 RESERVED R/W 0h Reserved
16 USB_A R/W 0h 1: Module is under reset
0: Module reset is determined by the normal device reset structure
Reset type: CPU1.SYSRSn
15-2 RESERVED R-0 0h Reserved
1 McBSP_B R/W 0h 1: Module is under reset
0: Module reset is determined by the normal device reset structure
Reset type: CPU1.SYSRSn
0 McBSP_A R/W 0h 1: Module is under reset
0: Module reset is determined by the normal device reset structure
Reset type: CPU1.SYSRSn

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3.16.9.19 SOFTPRES13 Register (Offset = 9Ch) [Reset = 0h]

SOFTPRES13 is shown in Figure 3-197 and described in Table 3-209.
Return to the Summary Table.
Processing Block Software Reset register
When bits in this register are set, the respective module is in reset. All design data is lost and the module
registers are returned to their reset states. Bits must be manually cleared after being set.
Figure 3-197. SOFTPRES13 Register
31 30 29 28 27 26 25 24
RESERVED
R-0-0h

23 22 21 20 19 18 17 16
RESERVED
R-0-0h

15 14 13 12 11 10 9 8
RESERVED
R-0-0h

7 6 5 4 3 2 1 0
RESERVED ADC_D ADC_C ADC_B ADC_A
R-0-0h R/W-0h R/W-0h R/W-0h R/W-0h

Table 3-209. SOFTPRES13 Register Field Descriptions

Bit Field Type Reset Description
31-16 RESERVED R-0 0h Reserved
15-4 RESERVED R-0 0h Reserved
3 ADC_D R/W 0h 1: Module is under reset
0: Module reset is determined by the normal device reset structure
Reset type: CPU1.SYSRSn
2 ADC_C R/W 0h 1: Module is under reset
0: Module reset is determined by the normal device reset structure
Reset type: CPU1.SYSRSn
1 ADC_B R/W 0h 1: Module is under reset
0: Module reset is determined by the normal device reset structure
Reset type: CPU1.SYSRSn
0 ADC_A R/W 0h 1: Module is under reset
0: Module reset is determined by the normal device reset structure
Reset type: CPU1.SYSRSn

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3.16.9.20 SOFTPRES14 Register (Offset = 9Eh) [Reset = 0h]

SOFTPRES14 is shown in Figure 3-198 and described in Table 3-210.
Return to the Summary Table.
Processing Block Software Reset register
When bits in this register are set, the respective module is in reset. All design data is lost and the module
registers are returned to their reset states. Bits must be manually cleared after being set.
Figure 3-198. SOFTPRES14 Register
31 30 29 28 27 26 25 24
RESERVED
R-0-0h

23 22 21 20 19 18 17 16
RESERVED
R-0-0h

15 14 13 12 11 10 9 8
RESERVED
R-0-0h

7 6 5 4 3 2 1 0
CMPSS8 CMPSS7 CMPSS6 CMPSS5 CMPSS4 CMPSS3 CMPSS2 CMPSS1
R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h

Table 3-210. SOFTPRES14 Register Field Descriptions

Bit Field Type Reset Description
31-16 RESERVED R-0 0h Reserved
15-8 RESERVED R-0 0h Reserved
7 CMPSS8 R/W 0h 1: Module is under reset
0: Module reset is determined by the normal device reset structure
Reset type: CPU1.SYSRSn
6 CMPSS7 R/W 0h 1: Module is under reset
0: Module reset is determined by the normal device reset structure
Reset type: CPU1.SYSRSn
5 CMPSS6 R/W 0h 1: Module is under reset
0: Module reset is determined by the normal device reset structure
Reset type: CPU1.SYSRSn
4 CMPSS5 R/W 0h 1: Module is under reset
0: Module reset is determined by the normal device reset structure
Reset type: CPU1.SYSRSn
3 CMPSS4 R/W 0h 1: Module is under reset
0: Module reset is determined by the normal device reset structure
Reset type: CPU1.SYSRSn
2 CMPSS3 R/W 0h 1: Module is under reset
0: Module reset is determined by the normal device reset structure
Reset type: CPU1.SYSRSn
1 CMPSS2 R/W 0h 1: Module is under reset
0: Module reset is determined by the normal device reset structure
Reset type: CPU1.SYSRSn
0 CMPSS1 R/W 0h 1: Module is under reset
0: Module reset is determined by the normal device reset structure
Reset type: CPU1.SYSRSn

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3.16.9.21 SOFTPRES16 Register (Offset = A2h) [Reset = 0h]

SOFTPRES16 is shown in Figure 3-199 and described in Table 3-211.
Return to the Summary Table.
Processing Block Software Reset register
When bits in this register are set, the respective module is in reset. All design data is lost and the module
registers are returned to their reset states. Bits must be manually cleared after being set.
Figure 3-199. SOFTPRES16 Register
31 30 29 28 27 26 25 24
RESERVED
R-0-0h

23 22 21 20 19 18 17 16
RESERVED RESERVED DAC_C DAC_B DAC_A
R-0-0h R/W-0h R/W-0h R/W-0h R/W-0h

15 14 13 12 11 10 9 8
RESERVED
R-0-0h

7 6 5 4 3 2 1 0
RESERVED
R-0-0h

Table 3-211. SOFTPRES16 Register Field Descriptions

Bit Field Type Reset Description
31-20 RESERVED R-0 0h Reserved
19 RESERVED R/W 0h Reserved
18 DAC_C R/W 0h 1: Module is under reset
0: Module reset is determined by the normal device reset structure
Reset type: CPU1.SYSRSn
17 DAC_B R/W 0h 1: Module is under reset
0: Module reset is determined by the normal device reset structure
Reset type: CPU1.SYSRSn
16 DAC_A R/W 0h 1: Module is under reset
0: Module reset is determined by the normal device reset structure
Reset type: CPU1.SYSRSn
15-0 RESERVED R-0 0h Reserved

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3.16.9.22 SOFTPRES17 Register (Offset = A4h) [Reset = 0h]

SOFTPRES17 is shown in Figure 3-200 and described in Table 3-212.
Return to the Summary Table.
Processing Block Software Reset register
When bits in this register are set, the respective module is in reset. All design data is lost and the module
registers are returned to their reset states. Bits must be manually cleared after being set.
Figure 3-200. SOFTPRES17 Register
31 30 29 28 27 26 25 24
RESERVED
R-0-0h

23 22 21 20 19 18 17 16
RESERVED
R-0-0h

15 14 13 12 11 10 9 8
RESERVED
R-0-0h

7 6 5 4 3 2 1 0
CLB8 CLB7 CLB6 CLB5 CLB4 CLB3 CLB2 CLB1
R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h

Table 3-212. SOFTPRES17 Register Field Descriptions

Bit Field Type Reset Description
31-8 RESERVED R-0 0h Reserved
7 CLB8 R/W 0h 1: Module is under reset
0: Module reset is determined by the normal device reset structure
Reset type: CPU1.SYSRSn
6 CLB7 R/W 0h 1: Module is under reset
0: Module reset is determined by the normal device reset structure
Reset type: CPU1.SYSRSn
5 CLB6 R/W 0h 1: Module is under reset
0: Module reset is determined by the normal device reset structure
Reset type: CPU1.SYSRSn
4 CLB5 R/W 0h 1: Module is under reset
0: Module reset is determined by the normal device reset structure
Reset type: CPU1.SYSRSn
3 CLB4 R/W 0h 1: Module is under reset
0: Module reset is determined by the normal device reset structure
Reset type: CPU1.SYSRSn
2 CLB3 R/W 0h 1: Module is under reset
0: Module reset is determined by the normal device reset structure
Reset type: CPU1.SYSRSn
1 CLB2 R/W 0h 1: Module is under reset
0: Module reset is determined by the normal device reset structure
Reset type: CPU1.SYSRSn
0 CLB1 R/W 0h 1: Module is under reset
0: Module reset is determined by the normal device reset structure
Reset type: CPU1.SYSRSn

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3.16.9.23 SOFTPRES18 Register (Offset = A6h) [Reset = 0h]

SOFTPRES18 is shown in Figure 3-201 and described in Table 3-213.
Return to the Summary Table.
Processing Block Software Reset register
When bits in this register are set, the respective module is in reset. All design data is lost and the module
registers are returned to their reset states. Bits must be manually cleared after being set.
Figure 3-201. SOFTPRES18 Register
31 30 29 28 27 26 25 24
RESERVED
R-0-0h

23 22 21 20 19 18 17 16
FSIRX_H FSIRX_G FSIRX_F FSIRX_E FSIRX_D FSIRX_C FSIRX_B FSIRX_A
R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h

15 14 13 12 11 10 9 8
RESERVED
R/W-0h

7 6 5 4 3 2 1 0
RESERVED RESERVED RESERVED RESERVED RESERVED RESERVED FSITX_B FSITX_A
R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h

Table 3-213. SOFTPRES18 Register Field Descriptions

Bit Field Type Reset Description
31-24 RESERVED R-0 0h Reserved
23 FSIRX_H R/W 0h 1: Module is under reset
0: Module reset is determined by the normal device reset structure
Reset type: CPU1.SYSRSn
22 FSIRX_G R/W 0h 1: Module is under reset
0: Module reset is determined by the normal device reset structure
Reset type: CPU1.SYSRSn
21 FSIRX_F R/W 0h 1: Module is under reset
0: Module reset is determined by the normal device reset structure
Reset type: CPU1.SYSRSn
20 FSIRX_E R/W 0h 1: Module is under reset
0: Module reset is determined by the normal device reset structure
Reset type: CPU1.SYSRSn
19 FSIRX_D R/W 0h 1: Module is under reset
0: Module reset is determined by the normal device reset structure
Reset type: CPU1.SYSRSn
18 FSIRX_C R/W 0h 1: Module is under reset
0: Module reset is determined by the normal device reset structure
Reset type: CPU1.SYSRSn
17 FSIRX_B R/W 0h 1: Module is under reset
0: Module reset is determined by the normal device reset structure
Reset type: CPU1.SYSRSn
16 FSIRX_A R/W 0h 1: Module is under reset
0: Module reset is determined by the normal device reset structure
Reset type: CPU1.SYSRSn
15-8 RESERVED R/W 0h Reserved
7 RESERVED R/W 0h Reserved
6 RESERVED R/W 0h Reserved
5 RESERVED R/W 0h Reserved

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Table 3-213. SOFTPRES18 Register Field Descriptions (continued)

Bit Field Type Reset Description
4 RESERVED R/W 0h Reserved
3 RESERVED R/W 0h Reserved
2 RESERVED R/W 0h Reserved
1 FSITX_B R/W 0h 1: Module is under reset
0: Module reset is determined by the normal device reset structure
Reset type: CPU1.SYSRSn
0 FSITX_A R/W 0h 1: Module is under reset
0: Module reset is determined by the normal device reset structure
Reset type: CPU1.SYSRSn

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3.16.9.24 SOFTPRES20 Register (Offset = AAh) [Reset = 0h]

SOFTPRES20 is shown in Figure 3-202 and described in Table 3-214.
Return to the Summary Table.
Peripheral Software Reset register
When bits in this register are set, the respective peripheral is in reset. All data is lost and the peripheral registers
are returned to their reset states. Bits must be manually cleared after being set.
Figure 3-202. SOFTPRES20 Register
31 30 29 28 27 26 25 24
RESERVED
R-0-0h

23 22 21 20 19 18 17 16
RESERVED
R-0-0h

15 14 13 12 11 10 9 8
RESERVED
R-0-0h

7 6 5 4 3 2 1 0
RESERVED RESERVED PMBUS_A
R-0-0h R/W-0h R/W-0h

Table 3-214. SOFTPRES20 Register Field Descriptions

Bit Field Type Reset Description
31-2 RESERVED R-0 0h Reserved
1 RESERVED R/W 0h Reserved
0 PMBUS_A R/W 0h 1: Module is under reset
0: Module reset is determined by the normal device reset structure
Reset type: CPU1.SYSRSn

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3.16.9.25 SOFTPRES21 Register (Offset = ACh) [Reset = 0h]

SOFTPRES21 is shown in Figure 3-203 and described in Table 3-215.
Return to the Summary Table.
Peripheral Software Reset register
When bits in this register are set, the respective peripheral is in reset. All data is lost and the peripheral registers
are returned to their reset states. Bits must be manually cleared after being set.
Figure 3-203. SOFTPRES21 Register
31 30 29 28 27 26 25 24
RESERVED
R-0-0h

23 22 21 20 19 18 17 16
RESERVED
R-0-0h

15 14 13 12 11 10 9 8
RESERVED
R-0-0h

7 6 5 4 3 2 1 0
RESERVED DCC2 DCC1 DCC0
R-0-0h R/W-0h R/W-0h R/W-0h

Table 3-215. SOFTPRES21 Register Field Descriptions

Bit Field Type Reset Description
31-3 RESERVED R-0 0h Reserved
2 DCC2 R/W 0h 1: Module is under reset
0: Module reset is determined by the normal device reset structure
Reset type: CPU1.SYSRSn
1 DCC1 R/W 0h 1: Module is under reset
0: Module reset is determined by the normal device reset structure
Reset type: CPU1.SYSRSn
0 DCC0 R/W 0h 1: Module is under reset
0: Module reset is determined by the normal device reset structure
Reset type: CPU1.SYSRSn

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3.16.9.26 SOFTPRES23 Register (Offset = B0h) [Reset = 1h]

SOFTPRES23 is shown in Figure 3-204 and described in Table 3-216.
Return to the Summary Table.
Peripheral Software Reset register
When bits in this register are set, the respective peripheral is in reset. All data is lost and the peripheral registers
are returned to their reset states. Bits must be manually cleared after being set.
Figure 3-204. SOFTPRES23 Register
31 30 29 28 27 26 25 24
RESERVED
R-0h

23 22 21 20 19 18 17 16
RESERVED
R-0h

15 14 13 12 11 10 9 8
RESERVED
R-0h

7 6 5 4 3 2 1 0
RESERVED ETHERCAT
R-0h R/W-1h

Table 3-216. SOFTPRES23 Register Field Descriptions

Bit Field Type Reset Description
31-16 RESERVED R 0h Reserved
15-1 RESERVED R 0h Reserved
0 ETHERCAT R/W 1h 1: Module is under reset
0: Module reset is determined by the normal device reset structure
Reset type: CPU1.SYSRSn

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3.16.9.27 CPUSEL0 Register (Offset = D6h) [Reset = 0h]

CPUSEL0 is shown in Figure 3-205 and described in Table 3-217.
Return to the Summary Table.
CPU Select register for common peripherals
This register must be configured prior to enabling the peripheral clocks.
The clock for each peripheral is derived from the selected CPU subsystem. The clock mux controlled by this
register is not glitch-free, therefore the CPUSELx register must be configured before the PCLKCRx register.
The reset for each peripheral is also driven from the selected CPU.
Figure 3-205. CPUSEL0 Register
31 30 29 28 27 26 25 24
RESERVED
R-0-0h

23 22 21 20 19 18 17 16
RESERVED
R-0-0h

15 14 13 12 11 10 9 8
EPWM16 EPWM15 EPWM14 EPWM13 EPWM12 EPWM11 EPWM10 EPWM9
R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h

7 6 5 4 3 2 1 0
EPWM8 EPWM7 EPWM6 EPWM5 EPWM4 EPWM3 EPWM2 EPWM1
R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h

Table 3-217. CPUSEL0 Register Field Descriptions

Bit Field Type Reset Description
31-16 RESERVED R-0 0h Reserved
15 EPWM16 R/W 0h 0: Connected to CPU1
1: Connected to CPU2
Reset type: CPU1.SYSRSn
14 EPWM15 R/W 0h 0: Connected to CPU1
1: Connected to CPU2
Reset type: CPU1.SYSRSn
13 EPWM14 R/W 0h 0: Connected to CPU1
1: Connected to CPU2
Reset type: CPU1.SYSRSn
12 EPWM13 R/W 0h 0: Connected to CPU1
1: Connected to CPU2
Reset type: CPU1.SYSRSn
11 EPWM12 R/W 0h 0: Connected to CPU1
1: Connected to CPU2
Reset type: CPU1.SYSRSn
10 EPWM11 R/W 0h 0: Connected to CPU1
1: Connected to CPU2
Reset type: CPU1.SYSRSn
9 EPWM10 R/W 0h 0: Connected to CPU1
1: Connected to CPU2
Reset type: CPU1.SYSRSn
8 EPWM9 R/W 0h 0: Connected to CPU1
1: Connected to CPU2
Reset type: CPU1.SYSRSn
7 EPWM8 R/W 0h 0: Connected to CPU1
1: Connected to CPU2
Reset type: CPU1.SYSRSn

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Table 3-217. CPUSEL0 Register Field Descriptions (continued)

Bit Field Type Reset Description
6 EPWM7 R/W 0h 0: Connected to CPU1
1: Connected to CPU2
Reset type: CPU1.SYSRSn
5 EPWM6 R/W 0h 0: Connected to CPU1
1: Connected to CPU2
Reset type: CPU1.SYSRSn
4 EPWM5 R/W 0h 0: Connected to CPU1
1: Connected to CPU2
Reset type: CPU1.SYSRSn
3 EPWM4 R/W 0h 0: Connected to CPU1
1: Connected to CPU2
Reset type: CPU1.SYSRSn
2 EPWM3 R/W 0h 0: Connected to CPU1
1: Connected to CPU2
Reset type: CPU1.SYSRSn
1 EPWM2 R/W 0h 0: Connected to CPU1
1: Connected to CPU2
Reset type: CPU1.SYSRSn
0 EPWM1 R/W 0h 0: Connected to CPU1
1: Connected to CPU2
Reset type: CPU1.SYSRSn

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3.16.9.28 CPUSEL1 Register (Offset = D8h) [Reset = 0h]

CPUSEL1 is shown in Figure 3-206 and described in Table 3-218.
Return to the Summary Table.
CPU Select register for common peripherals
This register must be configured prior to enabling the peripheral clocks.
The clock for each peripheral is derived from the selected CPU subsystem. The clock mux controlled by this
register is not glitch-free, therefore the CPUSELx register must be configured before the PCLKCRx register.
The reset for each peripheral is also driven from the selected CPU.
Figure 3-206. CPUSEL1 Register
31 30 29 28 27 26 25 24
RESERVED
R-0-0h

23 22 21 20 19 18 17 16
RESERVED
R-0-0h

15 14 13 12 11 10 9 8
RESERVED
R-0-0h

7 6 5 4 3 2 1 0
RESERVED ECAP7 ECAP6 ECAP5 ECAP4 ECAP3 ECAP2 ECAP1
R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h

Table 3-218. CPUSEL1 Register Field Descriptions

Bit Field Type Reset Description
31-16 RESERVED R-0 0h Reserved
15-8 RESERVED R-0 0h Reserved
7 RESERVED R/W 0h Reserved
6 ECAP7 R/W 0h 0: Connected to CPU1
1: Connected to CPU2
Reset type: CPU1.SYSRSn
5 ECAP6 R/W 0h 0: Connected to CPU1
1: Connected to CPU2
Reset type: CPU1.SYSRSn
4 ECAP5 R/W 0h 0: Connected to CPU1
1: Connected to CPU2
Reset type: CPU1.SYSRSn
3 ECAP4 R/W 0h 0: Connected to CPU1
1: Connected to CPU2
Reset type: CPU1.SYSRSn
2 ECAP3 R/W 0h 0: Connected to CPU1
1: Connected to CPU2
Reset type: CPU1.SYSRSn
1 ECAP2 R/W 0h 0: Connected to CPU1
1: Connected to CPU2
Reset type: CPU1.SYSRSn
0 ECAP1 R/W 0h 0: Connected to CPU1
1: Connected to CPU2
Reset type: CPU1.SYSRSn

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3.16.9.29 CPUSEL2 Register (Offset = DAh) [Reset = 0h]

CPUSEL2 is shown in Figure 3-207 and described in Table 3-219.
Return to the Summary Table.
CPU Select register for common peripherals
This register must be configured prior to enabling the peripheral clocks.
The clock for each peripheral is derived from the selected CPU subsystem. The clock mux controlled by this
register is not glitch-free, therefore the CPUSELx register must be configured before the PCLKCRx register.
The reset for each peripheral is also driven from the selected CPU.
Figure 3-207. CPUSEL2 Register
31 30 29 28 27 26 25 24
RESERVED
R-0-0h

23 22 21 20 19 18 17 16
RESERVED
R-0-0h

15 14 13 12 11 10 9 8
RESERVED
R-0-0h

7 6 5 4 3 2 1 0
RESERVED RESERVED EQEP3 EQEP2 EQEP1
R-0-0h R/W-0h R/W-0h R/W-0h R/W-0h

Table 3-219. CPUSEL2 Register Field Descriptions

Bit Field Type Reset Description
31-16 RESERVED R-0 0h Reserved
15-4 RESERVED R-0 0h Reserved
3 RESERVED R/W 0h Reserved
2 EQEP3 R/W 0h 0: Connected to CPU1
1: Connected to CPU2
Reset type: CPU1.SYSRSn
1 EQEP2 R/W 0h 0: Connected to CPU1
1: Connected to CPU2
Reset type: CPU1.SYSRSn
0 EQEP1 R/W 0h 0: Connected to CPU1
1: Connected to CPU2
Reset type: CPU1.SYSRSn

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3.16.9.30 CPUSEL4 Register (Offset = DEh) [Reset = 0h]

CPUSEL4 is shown in Figure 3-208 and described in Table 3-220.
Return to the Summary Table.
CPU Select register for common peripherals
This register must be configured prior to enabling the peripheral clocks.
The clock for each peripheral is derived from the selected CPU subsystem. The clock mux controlled by this
register is not glitch-free, therefore the CPUSELx register must be configured before the PCLKCRx register.
The reset for each peripheral is also driven from the selected CPU.
Figure 3-208. CPUSEL4 Register
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
RESERVED
R-0-0h

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RESERVED RESE RESE RESE RESE RESE RESE SD2 SD1
RVED RVED RVED RVED RVED RVED
R-0-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h

Table 3-220. CPUSEL4 Register Field Descriptions

Bit Field Type Reset Description
31-16 RESERVED R-0 0h Reserved
15-8 RESERVED R-0 0h Reserved
7 RESERVED R/W 0h Reserved
6 RESERVED R/W 0h Reserved
5 RESERVED R/W 0h Reserved
4 RESERVED R/W 0h Reserved
3 RESERVED R/W 0h Reserved
2 RESERVED R/W 0h Reserved
1 SD2 R/W 0h 0: Connected to CPU1
1: Connected to CPU2
Reset type: CPU1.SYSRSn
0 SD1 R/W 0h 0: Connected to CPU1
1: Connected to CPU2
Reset type: CPU1.SYSRSn

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3.16.9.31 CPUSEL5 Register (Offset = E0h) [Reset = 0h]

CPUSEL5 is shown in Figure 3-209 and described in Table 3-221.
Return to the Summary Table.
CPU Select register for common peripherals
This register must be configured prior to enabling the peripheral clocks.
The clock for each peripheral is derived from the selected CPU subsystem. The clock mux controlled by this
register is not glitch-free, therefore the CPUSELx register must be configured before the PCLKCRx register.
The reset for each peripheral is also driven from the selected CPU.
Figure 3-209. CPUSEL5 Register
31 30 29 28 27 26 25 24
RESERVED
R-0-0h

23 22 21 20 19 18 17 16
RESERVED
R-0-0h

15 14 13 12 11 10 9 8
RESERVED
R-0-0h

7 6 5 4 3 2 1 0
RESERVED SCI_D SCI_C SCI_B SCI_A
R-0-0h R/W-0h R/W-0h R/W-0h R/W-0h

Table 3-221. CPUSEL5 Register Field Descriptions

Bit Field Type Reset Description
31-16 RESERVED R-0 0h Reserved
15-4 RESERVED R-0 0h Reserved
3 SCI_D R/W 0h 0: Connected to CPU1
1: Connected to CPU2
Reset type: CPU1.SYSRSn
2 SCI_C R/W 0h 0: Connected to CPU1
1: Connected to CPU2
Reset type: CPU1.SYSRSn
1 SCI_B R/W 0h 0: Connected to CPU1
1: Connected to CPU2
Reset type: CPU1.SYSRSn
0 SCI_A R/W 0h 0: Connected to CPU1
1: Connected to CPU2
Reset type: CPU1.SYSRSn

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3.16.9.32 CPUSEL6 Register (Offset = E2h) [Reset = 0h]

CPUSEL6 is shown in Figure 3-210 and described in Table 3-222.
Return to the Summary Table.
CPU Select register for common peripherals
This register must be configured prior to enabling the peripheral clocks.
The clock for each peripheral is derived from the selected CPU subsystem. The clock mux controlled by this
register is not glitch-free, therefore the CPUSELx register must be configured before the PCLKCRx register.
The reset for each peripheral is also driven from the selected CPU.
Figure 3-210. CPUSEL6 Register
31 30 29 28 27 26 25 24
RESERVED
R-0-0h

23 22 21 20 19 18 17 16
RESERVED RESERVED RESERVED
R-0-0h R/W-0h R/W-0h

15 14 13 12 11 10 9 8
RESERVED
R-0-0h

7 6 5 4 3 2 1 0
RESERVED SPI_D SPI_C SPI_B SPI_A
R-0-0h R/W-0h R/W-0h R/W-0h R/W-0h

Table 3-222. CPUSEL6 Register Field Descriptions

Bit Field Type Reset Description
31-18 RESERVED R-0 0h Reserved
17 RESERVED R/W 0h Reserved
16 RESERVED R/W 0h Reserved
15-4 RESERVED R-0 0h Reserved
3 SPI_D R/W 0h 0: Connected to CPU1
1: Connected to CPU2
Reset type: CPU1.SYSRSn
2 SPI_C R/W 0h 0: Connected to CPU1
1: Connected to CPU2
Reset type: CPU1.SYSRSn
1 SPI_B R/W 0h 0: Connected to CPU1
1: Connected to CPU2
Reset type: CPU1.SYSRSn
0 SPI_A R/W 0h 0: Connected to CPU1
1: Connected to CPU2
Reset type: CPU1.SYSRSn

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3.16.9.33 CPUSEL7 Register (Offset = E4h) [Reset = 0h]

CPUSEL7 is shown in Figure 3-211 and described in Table 3-223.
Return to the Summary Table.
CPU Select register for common peripherals
This register must be configured prior to enabling the peripheral clocks.
The clock for each peripheral is derived from the selected CPU subsystem. The clock mux controlled by this
register is not glitch-free, therefore the CPUSELx register must be configured before the PCLKCRx register.
The reset for each peripheral is also driven from the selected CPU.
Figure 3-211. CPUSEL7 Register
31 30 29 28 27 26 25 24
RESERVED
R-0-0h

23 22 21 20 19 18 17 16
RESERVED
R-0-0h

15 14 13 12 11 10 9 8
RESERVED
R-0-0h

7 6 5 4 3 2 1 0
RESERVED I2C_B I2C_A
R-0-0h R/W-0h R/W-0h

Table 3-223. CPUSEL7 Register Field Descriptions

Bit Field Type Reset Description
31-16 RESERVED R-0 0h Reserved
15-2 RESERVED R-0 0h Reserved
1 I2C_B R/W 0h 0: Connected to CPU1
1: Connected to CPU2
Reset type: CPU1.SYSRSn
0 I2C_A R/W 0h 0: Connected to CPU1
1: Connected to CPU2
Reset type: CPU1.SYSRSn

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3.16.9.34 CPUSEL8 Register (Offset = E6h) [Reset = 0h]

CPUSEL8 is shown in Figure 3-212 and described in Table 3-224.
Return to the Summary Table.
CPU Select register for common peripherals
This register must be configured prior to enabling the peripheral clocks.
The clock for each peripheral is derived from the selected CPU subsystem. The clock mux controlled by this
register is not glitch-free, therefore the CPUSELx register must be configured before the PCLKCRx register.
The reset for each peripheral is also driven from the selected CPU.
Figure 3-212. CPUSEL8 Register
31 30 29 28 27 26 25 24
RESERVED
R-0-0h

23 22 21 20 19 18 17 16
RESERVED
R-0-0h

15 14 13 12 11 10 9 8
RESERVED
R-0-0h

7 6 5 4 3 2 1 0
RESERVED MCAN_A RESERVED RESERVED CAN_B CAN_A
R-0-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h

Table 3-224. CPUSEL8 Register Field Descriptions

Bit Field Type Reset Description
31-16 RESERVED R-0 0h Reserved
15-5 RESERVED R-0 0h Reserved
4 MCAN_A R/W 0h 0: Connected to CPU1
1: Connected to CPU2
Reset type: CPU1.SYSRSn
3 RESERVED R/W 0h Reserved
2 RESERVED R/W 0h Reserved
1 CAN_B R/W 0h 0: Connected to CPU1
1: Connected to CPU2
Reset type: CPU1.SYSRSn
0 CAN_A R/W 0h 0: Connected to CPU1
1: Connected to CPU2
Reset type: CPU1.SYSRSn

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3.16.9.35 CPUSEL9 Register (Offset = E8h) [Reset = 0h]

CPUSEL9 is shown in Figure 3-213 and described in Table 3-225.
Return to the Summary Table.
CPU Select register for common peripherals
This register must be configured prior to enabling the peripheral clocks.
The clock for each peripheral is derived from the selected CPU subsystem. The clock mux controlled by this
register is not glitch-free, therefore the CPUSELx register must be configured before the PCLKCRx register.
The reset for each peripheral is also driven from the selected CPU.
Figure 3-213. CPUSEL9 Register
31 30 29 28 27 26 25 24
RESERVED
R-0-0h

23 22 21 20 19 18 17 16
RESERVED
R-0-0h

15 14 13 12 11 10 9 8
RESERVED
R-0-0h

7 6 5 4 3 2 1 0
RESERVED McBSP_B McBSP_A
R-0-0h R/W-0h R/W-0h

Table 3-225. CPUSEL9 Register Field Descriptions

Bit Field Type Reset Description
31-16 RESERVED R-0 0h Reserved
15-2 RESERVED R-0 0h Reserved
1 McBSP_B R/W 0h 0: Connected to CPU1
1: Connected to CPU2
Reset type: CPU1.SYSRSn
0 McBSP_A R/W 0h 0: Connected to CPU1
1: Connected to CPU2
Reset type: CPU1.SYSRSn

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3.16.9.36 CPUSEL11 Register (Offset = ECh) [Reset = 0h]

CPUSEL11 is shown in Figure 3-214 and described in Table 3-226.
Return to the Summary Table.
CPU Select register for common peripherals
This register must be configured prior to enabling the peripheral clocks.
The clock for each peripheral is derived from the selected CPU subsystem. The clock mux controlled by this
register is not glitch-free, therefore the CPUSELx register must be configured before the PCLKCRx register.
The reset for each peripheral is also driven from the selected CPU.
Figure 3-214. CPUSEL11 Register
31 30 29 28 27 26 25 24
RESERVED
R-0-0h

23 22 21 20 19 18 17 16
RESERVED
R-0-0h

15 14 13 12 11 10 9 8
RESERVED
R-0-0h

7 6 5 4 3 2 1 0
RESERVED ADC_D ADC_C ADC_B ADC_A
R-0-0h R/W-0h R/W-0h R/W-0h R/W-0h

Table 3-226. CPUSEL11 Register Field Descriptions

Bit Field Type Reset Description
31-16 RESERVED R-0 0h Reserved
15-4 RESERVED R-0 0h Reserved
3 ADC_D R/W 0h These CPUSEL bits affect the ownership of only ADC Configuration
registers by CPU1 or CPU2. ADC result registers are readable from
all masters without any CPUSEL dependency.
0: Connected to CPU1
1: Connected to CPU2
Reset type: CPU1.SYSRSn
2 ADC_C R/W 0h These CPUSEL bits affect the ownership of only ADC Configuration
registers by CPU1 or CPU2. ADC result registers are readable from
all masters without any CPUSEL dependency.
0: Connected to CPU1
1: Connected to CPU2
Reset type: CPU1.SYSRSn
1 ADC_B R/W 0h These CPUSEL bits affect the ownership of only ADC Configuration
registers by CPU1 or CPU2. ADC result registers are readable from
all masters without any CPUSEL dependency.
0: Connected to CPU1
1: Connected to CPU2
Reset type: CPU1.SYSRSn
0 ADC_A R/W 0h These CPUSEL bits affect the ownership of only ADC Configuration
registers by CPU1 or CPU2. ADC result registers are readable from
all masters without any CPUSEL dependency.
0: Connected to CPU1
1: Connected to CPU2
Reset type: CPU1.SYSRSn

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3.16.9.37 CPUSEL12 Register (Offset = EEh) [Reset = 0h]

CPUSEL12 is shown in Figure 3-215 and described in Table 3-227.
Return to the Summary Table.
CPU Select register for common peripherals
This register must be configured prior to enabling the peripheral clocks.
The clock for each peripheral is derived from the selected CPU subsystem. The clock mux controlled by this
register is not glitch-free, therefore the CPUSELx register must be configured before the PCLKCRx register.
The reset for each peripheral is also driven from the selected CPU.
Figure 3-215. CPUSEL12 Register
31 30 29 28 27 26 25 24
RESERVED
R-0-0h

23 22 21 20 19 18 17 16
RESERVED
R-0-0h

15 14 13 12 11 10 9 8
RESERVED
R-0-0h

7 6 5 4 3 2 1 0
CMPSS8 CMPSS7 CMPSS6 CMPSS5 CMPSS4 CMPSS3 CMPSS2 CMPSS1
R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h

Table 3-227. CPUSEL12 Register Field Descriptions

Bit Field Type Reset Description
31-16 RESERVED R-0 0h Reserved
15-8 RESERVED R-0 0h Reserved
7 CMPSS8 R/W 0h 0: Connected to CPU1
1: Connected to CPU2
Reset type: CPU1.SYSRSn
6 CMPSS7 R/W 0h 0: Connected to CPU1
1: Connected to CPU2
Reset type: CPU1.SYSRSn
5 CMPSS6 R/W 0h 0: Connected to CPU1
1: Connected to CPU2
Reset type: CPU1.SYSRSn
4 CMPSS5 R/W 0h 0: Connected to CPU1
1: Connected to CPU2
Reset type: CPU1.SYSRSn
3 CMPSS4 R/W 0h 0: Connected to CPU1
1: Connected to CPU2
Reset type: CPU1.SYSRSn
2 CMPSS3 R/W 0h 0: Connected to CPU1
1: Connected to CPU2
Reset type: CPU1.SYSRSn
1 CMPSS2 R/W 0h 0: Connected to CPU1
1: Connected to CPU2
Reset type: CPU1.SYSRSn
0 CMPSS1 R/W 0h 0: Connected to CPU1
1: Connected to CPU2
Reset type: CPU1.SYSRSn

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3.16.9.38 CPUSEL14 Register (Offset = F2h) [Reset = 0h]

CPUSEL14 is shown in Figure 3-216 and described in Table 3-228.
Return to the Summary Table.
CPU Select register for common peripherals
This register must be configured prior to enabling the peripheral clocks.
The clock for each peripheral is derived from the selected CPU subsystem. The clock mux controlled by this
register is not glitch-free, therefore the CPUSELx register must be configured before the PCLKCRx register.
The reset for each peripheral is also driven from the selected CPU.
Figure 3-216. CPUSEL14 Register
31 30 29 28 27 26 25 24
RESERVED
R-0-0h

23 22 21 20 19 18 17 16
RESERVED RESERVED DAC_C DAC_B DAC_A
R-0-0h R/W-0h R/W-0h R/W-0h R/W-0h

15 14 13 12 11 10 9 8
RESERVED
R-0-0h

7 6 5 4 3 2 1 0
RESERVED
R-0-0h

Table 3-228. CPUSEL14 Register Field Descriptions

Bit Field Type Reset Description
31-20 RESERVED R-0 0h Reserved
19 RESERVED R/W 0h Reserved
18 DAC_C R/W 0h 0: Connected to CPU1
1: Connected to CPU2
Reset type: CPU1.SYSRSn
17 DAC_B R/W 0h 0: Connected to CPU1
1: Connected to CPU2
Reset type: CPU1.SYSRSn
16 DAC_A R/W 0h 0: Connected to CPU1
1: Connected to CPU2
Reset type: CPU1.SYSRSn
15-0 RESERVED R-0 0h Reserved

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3.16.9.39 CPUSEL15 Register (Offset = F4h) [Reset = 0h]

CPUSEL15 is shown in Figure 3-217 and described in Table 3-229.
Return to the Summary Table.
CPU Select register for common peripherals
This register must be configured prior to enabling the peripheral clocks.
The clock for each peripheral is derived from the selected CPU subsystem. The clock mux controlled by this
register is not glitch-free, therefore the CPUSELx register must be configured before the PCLKCRx register.
The reset for each peripheral is also driven from the selected CPU.
Figure 3-217. CPUSEL15 Register
31 30 29 28 27 26 25 24
RESERVED
R/W-0h

23 22 21 20 19 18 17 16
RESERVED
R/W-0h

15 14 13 12 11 10 9 8
RESERVED
R/W-0h

7 6 5 4 3 2 1 0
CLB8 CLB7 CLB6 CLB5 CLB4 CLB3 CLB2 CLB1
R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h

Table 3-229. CPUSEL15 Register Field Descriptions

Bit Field Type Reset Description
31-8 RESERVED R/W 0h Reserved
7 CLB8 R/W 0h 0: Connected to CPU1
1: Connected to CPU2
Reset type: CPU1.SYSRSn
6 CLB7 R/W 0h 0: Connected to CPU1
1: Connected to CPU2
Reset type: CPU1.SYSRSn
5 CLB6 R/W 0h 0: Connected to CPU1
1: Connected to CPU2
Reset type: CPU1.SYSRSn
4 CLB5 R/W 0h 0: Connected to CPU1
1: Connected to CPU2
Reset type: CPU1.SYSRSn
3 CLB4 R/W 0h 0: Connected to CPU1
1: Connected to CPU2
Reset type: CPU1.SYSRSn
2 CLB3 R/W 0h 0: Connected to CPU1
1: Connected to CPU2
Reset type: CPU1.SYSRSn
1 CLB2 R/W 0h 0: Connected to CPU1
1: Connected to CPU2
Reset type: CPU1.SYSRSn
0 CLB1 R/W 0h 0: Connected to CPU1
1: Connected to CPU2
Reset type: CPU1.SYSRSn

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3.16.9.40 CPUSEL16 Register (Offset = F6h) [Reset = 0h]

CPUSEL16 is shown in Figure 3-218 and described in Table 3-230.
Return to the Summary Table.
CPU Select register for common peripherals
This register must be configured prior to enabling the peripheral clocks.
The clock for each peripheral is derived from the selected CPU subsystem. The clock mux controlled by this
register is not glitch-free, therefore the CPUSELx register must be configured before the PCLKCRx register.
The reset for each peripheral is also driven from the selected CPU.
Figure 3-218. CPUSEL16 Register
31 30 29 28 27 26 25 24
RESERVED
R-0-0h

23 22 21 20 19 18 17 16
FSIRX_H FSIRX_G FSIRX_F FSIRX_E FSIRX_D FSIRX_C FSIRX_B FSIRX_A
R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h

15 14 13 12 11 10 9 8
RESERVED
R-0-0h

7 6 5 4 3 2 1 0
RESERVED RESERVED RESERVED RESERVED RESERVED RESERVED FSITX_B FSITX_A
R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h

Table 3-230. CPUSEL16 Register Field Descriptions

Bit Field Type Reset Description
31-24 RESERVED R-0 0h Reserved
23 FSIRX_H R/W 0h 0: Connected to CPU1
1: Connected to CPU2
Reset type: CPU1.SYSRSn
22 FSIRX_G R/W 0h 0: Connected to CPU1
1: Connected to CPU2
Reset type: CPU1.SYSRSn
21 FSIRX_F R/W 0h 0: Connected to CPU1
1: Connected to CPU2
Reset type: CPU1.SYSRSn
20 FSIRX_E R/W 0h 0: Connected to CPU1
1: Connected to CPU2
Reset type: CPU1.SYSRSn
19 FSIRX_D R/W 0h 0: Connected to CPU1
1: Connected to CPU2
Reset type: CPU1.SYSRSn
18 FSIRX_C R/W 0h 0: Connected to CPU1
1: Connected to CPU2
Reset type: CPU1.SYSRSn
17 FSIRX_B R/W 0h 0: Connected to CPU1
1: Connected to CPU2
Reset type: CPU1.SYSRSn
16 FSIRX_A R/W 0h 0: Connected to CPU1
1: Connected to CPU2
Reset type: CPU1.SYSRSn
15-8 RESERVED R-0 0h Reserved
7 RESERVED R/W 0h Reserved

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Table 3-230. CPUSEL16 Register Field Descriptions (continued)

Bit Field Type Reset Description
6 RESERVED R/W 0h Reserved
5 RESERVED R/W 0h Reserved
4 RESERVED R/W 0h Reserved
3 RESERVED R/W 0h Reserved
2 RESERVED R/W 0h Reserved
1 FSITX_B R/W 0h 0: Connected to CPU1
1: Connected to CPU2
Reset type: CPU1.SYSRSn
0 FSITX_A R/W 0h 0: Connected to CPU1
1: Connected to CPU2
Reset type: CPU1.SYSRSn

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3.16.9.41 CPUSEL18 Register (Offset = FAh) [Reset = 0h]

CPUSEL18 is shown in Figure 3-219 and described in Table 3-231.
Return to the Summary Table.
CPU Select register for common peripherals
This register must be configured prior to enabling the peripheral clocks.
The clock for each peripheral is derived from the selected CPU subsystem. The clock mux controlled by this
register is not glitch-free, therefore the CPUSELx register must be configured before the PCLKCRx register.
The reset for each peripheral is also driven from the selected CPU.
Figure 3-219. CPUSEL18 Register
31 30 29 28 27 26 25 24
RESERVED
R-0h

23 22 21 20 19 18 17 16
RESERVED
R-0h

15 14 13 12 11 10 9 8
RESERVED
R-0h

7 6 5 4 3 2 1 0
RESERVED RESERVED PMBUS_A
R-0h R/W-0h R/W-0h

Table 3-231. CPUSEL18 Register Field Descriptions

Bit Field Type Reset Description
31-2 RESERVED R 0h Reserved
1 RESERVED R/W 0h Reserved
0 PMBUS_A R/W 0h 0: Connected to CPU1
1: Connected to CPU2
Reset type: CPU1.SYSRSn

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3.16.9.42 CPUSEL25 Register (Offset = 108h) [Reset = 0h]

CPUSEL25 is shown in Figure 3-220 and described in Table 3-232.
Return to the Summary Table.
CPU Select register for common peripherals
This register must be configured prior to enabling the peripheral clocks.
The clock for each peripheral is derived from the selected CPU subsystem. The clock mux controlled by this
register is not glitch-free, therefore the CPUSELx register must be configured before the PCLKCRx register.
The reset for each peripheral is also driven from the selected CPU.
Figure 3-220. CPUSEL25 Register
31 30 29 28 27 26 25 24
RESERVED
R-0h

23 22 21 20 19 18 17 16
RESERVED
R-0h

15 14 13 12 11 10 9 8
RESERVED
R-0h

7 6 5 4 3 2 1 0
RESERVED HRCAL_A
R-0h R/W-0h

Table 3-232. CPUSEL25 Register Field Descriptions

Bit Field Type Reset Description
31-1 RESERVED R 0h Reserved
0 HRCAL_A R/W 0h 0: Connected to CPU1
1: Connected to CPU2
Reset type: CPU1.SYSRSn

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3.16.9.43 CPU2RESCTL Register (Offset = 122h) [Reset = 1h]

CPU2RESCTL is shown in Figure 3-221 and described in Table 3-233.
Return to the Summary Table.
CPU2 Reset Control Register
Figure 3-221. CPU2RESCTL Register
31 30 29 28 27 26 25 24
KEY
R-0/W-0h

23 22 21 20 19 18 17 16
KEY
R-0/W-0h

15 14 13 12 11 10 9 8
RESERVED
R-0-0h

7 6 5 4 3 2 1 0
RESERVED RESET
R-0-0h R/W-1h

Table 3-233. CPU2RESCTL Register Field Descriptions

Bit Field Type Reset Description
31-16 KEY R-0/W 0h Write to this register succeeds only if this field is written with a value
of 0xa5a5
Note:
[1] Due to this KEY, only 32-bit writes will succeed (provided the KEY
matches). 16-bit writes to the upper or lower half of this register will
be ignored
Reset type: CPU1.SYSRSn
15-1 RESERVED R-0 0h Reserved
0 RESET R/W 1h This bit controls the reset input of CPU2 core.
1: CPU2 is held in reset (CPU2.RSn = 0)
0: CPU2 reset is deactivated (CPU2.RSn = 1)
Note:
[1] If CPU2 is not used at-all by an application, it's advisable to put
CPU2 in STANDBY mode rather than in reset to save on active
power component on the CPU2 subsystem. This is because, all
clocks keep toggling when reset is active on the CPU2 sub-system.
[2] Note: If CPU2 is in Standby mode, writing to this bit will have no
effect. CPU2 may be reset by any Chip-level reset (POR, XRSn,
CPU1.WDRSn, or CPU1.NMIWDRSn). Alternately CPU2 may be
woken up by any configured wake-up event.
Reset type: CPU1.SYSRSn

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3.16.9.44 RSTSTAT Register (Offset = 124h) [Reset = 0h]

RSTSTAT is shown in Figure 3-222 and described in Table 3-234.
Return to the Summary Table.
Reset Status register for secondary C28x CPUs
Figure 3-222. RSTSTAT Register
15 14 13 12 11 10 9 8
RESERVED
R-0-0h

7 6 5 4 3 2 1 0
RESERVED CPU2HWBISTRST CPU2NMIWDR CPU2RES
ST
R-0-0h R/W1S-0h R/W1S-0h R-0h

Table 3-234. RSTSTAT Register Field Descriptions

Bit Field Type Reset Description
15-4 RESERVED R-0 0h Reserved
3-2 CPU2HWBISTRST R/W1S 0h CPU2HWBISTRST0 and CPU2HWBISTRST1 together tells whether
a HWBIST reset was issued to CPU2 or not
00: CPU2 was not reset by the CPU2 HWBIST
11: CPU2 was reset due to CPU2 HWBIST reset
This status bit is a latched flag. This flag can be cleared by the CPU1
by writing a 1
Reset type: CPU1.SYSRSn
1 CPU2NMIWDRST R/W1S 0h Indicates whether a CPU2.NMIWD reset was issued to CPU2 or not
0: CPU2 was not reset by the CPU2.NMIWD
1: CPU2 was reset due to CPU2.NMIWD reset
Reset type: CPU1.SYSRSn
0 CPU2RES R 0h Reset status of CPU2 to CPU1
0: CPU2 core is in reset
1: CPU2 core is out of reset
Reset type: CPU1.SYSRSn

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3.16.9.45 LPMSTAT Register (Offset = 125h) [Reset = 0h]

LPMSTAT is shown in Figure 3-223 and described in Table 3-235.
Return to the Summary Table.
LPM Status Register for secondary C28x CPUs
Figure 3-223. LPMSTAT Register
15 14 13 12 11 10 9 8
RESERVED
R-0-0h

7 6 5 4 3 2 1 0
RESERVED CPU2LPMSTAT
R-0-0h R-0h

Table 3-235. LPMSTAT Register Field Descriptions

Bit Field Type Reset Description
15-2 RESERVED R-0 0h Reserved
1-0 CPU2LPMSTAT R 0h These bits indicate the power mode CPU2
00: CPU2 is in ACTIVE mode
01: CPU2 is in IDLE mode
10: CPU2 is in STANDBY mode
11: Reserved
Reset type: CPU1.SYSRSn

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3.16.9.46 USBTYPE Register (Offset = 19Ah) [Reset = 0h]

USBTYPE is shown in Figure 3-224 and described in Table 3-236.
Return to the Summary Table.
Based on the configuration enables disables features associated with the USB type.
Figure 3-224. USBTYPE Register
15 14 13 12 11 10 9 8
LOCK RESERVED
R/WSonce-0h R-0-0h

7 6 5 4 3 2 1 0
RESERVED TYPE
R-0-0h R/W-0h

Table 3-236. USBTYPE Register Field Descriptions

Bit Field Type Reset Description
15 LOCK R/WSonce 0h 1: Write to this register is not allowed.
0: Write to this register is allowed.
Reset type: CPU1.SYSRSn
14-2 RESERVED R-0 0h Reserved
1-0 TYPE R/W 0h "00,10,11" :
1. Global interrupt feature is not enabled, interrupts fired
unconditionally.
"01" :
1.Global interrupt feature is enabled, refer to the USB chapter for
more details about global interrupt feature.
Reset type: CPU1.SYSRSn

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3.16.9.47 ECAPTYPE Register (Offset = 19Bh) [Reset = 0h]

ECAPTYPE is shown in Figure 3-225 and described in Table 3-237.
Return to the Summary Table.
Based on the configuration enables disables features associated with the SDFM type.
Figure 3-225. ECAPTYPE Register
15 14 13 12 11 10 9 8
LOCK RESERVED
R/WSonce-0h R-0-0h

7 6 5 4 3 2 1 0
RESERVED TYPE
R-0-0h R/W-0h

Table 3-237. ECAPTYPE Register Field Descriptions

Bit Field Type Reset Description
15 LOCK R/WSonce 0h 1: Write to this register is not allowed.
0: Write to this register is allowed.
Reset type: CPU1.SYSRSn
14-2 RESERVED R-0 0h Reserved
1-0 TYPE R/W 0h "00,10,11" :
1. No EALLOW protection to ECAP registers.
"01" :
1. ECAP registers are EALLOW protected.
Reset type: CPU1.SYSRSn

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3.16.9.48 SDFMTYPE Register (Offset = 19Ch) [Reset = 0h]

SDFMTYPE is shown in Figure 3-226 and described in Table 3-238.
Return to the Summary Table.
Based on the configuration enables disables features associated with the SDFM type.
Figure 3-226. SDFMTYPE Register
15 14 13 12 11 10 9 8
LOCK RESERVED
R/WSonce-0h R-0-0h

7 6 5 4 3 2 1 0
RESERVED TYPE
R-0-0h R/W-0h

Table 3-238. SDFMTYPE Register Field Descriptions

Bit Field Type Reset Description
15 LOCK R/WSonce 0h 1: Write to this register is not allowed.
0: Write to this register is allowed.
Reset type: CPU1.SYSRSn
14-2 RESERVED R-0 0h Reserved
1-0 TYPE R/W 0h "00,10,11" :
1. Data Ready conditions combined with the fault conditions on the
SDFM interrupt line.
2. Data ready interrupts from individual filters are not generated.
"01" :
1. Data Ready conditions do not generate the SDFMINT.
2. Each filter generates a separate data ready interrupts.
Reset type: CPU1.SYSRSn

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3.16.9.49 MEMMAPTYPE Register (Offset = 19Eh) [Reset = 0h]

MEMMAPTYPE is shown in Figure 3-227 and described in Table 3-239.
Return to the Summary Table.
Based on the configuration enables the memory map.
Figure 3-227. MEMMAPTYPE Register
15 14 13 12 11 10 9 8
LOCK RESERVED
R/WSonce-0h R-0-0h

7 6 5 4 3 2 1 0
RESERVED TYPE
R-0-0h R/W-0h

Table 3-239. MEMMAPTYPE Register Field Descriptions

Bit Field Type Reset Description
15 LOCK R/WSonce 0h 1: Write to this register is not allowed.
0: Write to this register is allowed.
Reset type: CPU1.SYSRSn
14-2 RESERVED R-0 0h Reserved
1-0 TYPE R/W 0h "00,10,11" :
1. Disables re-mapping SDRAM in lower 128kb of address space.
"01" :
1. Enables re-mapping SDRAM in lower 128kb of address space.
Reset type: CPU1.SYSRSn

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3.16.10 DMA_CLA_SRC_SEL_REGS Registers

Table 3-240 lists the memory-mapped registers for the DMA_CLA_SRC_SEL_REGS registers. All register offset
addresses not listed in Table 3-240 should be considered as reserved locations and the register contents should
not be modified.
Table 3-240. DMA_CLA_SRC_SEL_REGS Registers
Offset Acronym Register Name Write Protection Section
0h CLA1TASKSRCSELLOCK CLA1 Task Trigger Source Select Lock Register EALLOW Go
4h DMACHSRCSELLOCK DMA Channel Triger Source Select Lock Register EALLOW Go
6h CLA1TASKSRCSEL1 CLA1 Task Trigger Source Select Register-1 EALLOW Go
8h CLA1TASKSRCSEL2 CLA1 Task Trigger Source Select Register-2 EALLOW Go
16h DMACHSRCSEL1 DMA Channel Trigger Source Select Register-1 EALLOW Go
18h DMACHSRCSEL2 DMA Channel Trigger Source Select Register-2 EALLOW Go

Complex bit access types are encoded to fit into small table cells. Table 3-241 shows the codes that are used for
access types in this section.
Table 3-241. DMA_CLA_SRC_SEL_REGS Access
Type Codes
Access Type Code Description
Read Type
R R Read
R-0 R Read
-0 Returns 0s
Write Type
W W Write
WSonce W Write
Sonce Set once
Reset or Default Value
-n Value after reset or the default
value
Register Array Variables
i,j,k,l,m,n When these variables are used in
a register name, an offset, or an
address, they refer to the value of
a register array where the register
is part of a group of repeating
registers. The register groups
form a hierarchical structure and
the array is represented with a
formula.
y When this variable is used in a
register name, an offset, or an
address it refers to the value of
a register array.

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3.16.10.1 CLA1TASKSRCSELLOCK Register (Offset = 0h) [Reset = 0h]

CLA1TASKSRCSELLOCK is shown in Figure 3-228 and described in Table 3-242.
Return to the Summary Table.
CLA1 Task Trigger Source Select Lock Register
Figure 3-228. CLA1TASKSRCSELLOCK Register
31 30 29 28 27 26 25 24
RESERVED
R-0-0h

23 22 21 20 19 18 17 16
RESERVED
R-0-0h

15 14 13 12 11 10 9 8
RESERVED
R-0-0h

7 6 5 4 3 2 1 0
RESERVED CLA1TASKSRC CLA1TASKSRC
SEL2 SEL1
R-0-0h R/WSonce-0h R/WSonce-0h

Table 3-242. CLA1TASKSRCSELLOCK Register Field Descriptions

Bit Field Type Reset Description
31-16 RESERVED R-0 0h Reserved
15-2 RESERVED R-0 0h Reserved
1 CLA1TASKSRCSEL2 R/WSonce 0h CLA1TASKSRCSEL2 Register Lock bit:
0: Respective register is not locked
1: Respective register is locked.
Notes:
[1] Any SOnce bit in this register, once set can only be cleared
through a SYSRSn. Write of 0 to any bit of this register has no effect
[2] The locking mechanism applies to only writes. Reads to the
registers which have LOCK protection are always allowed
Reset type: SYSRSn
0 CLA1TASKSRCSEL1 R/WSonce 0h CLA1TASKSRCSEL1 Register Lock bit:
0: Respective register is not locked
1: Respective register is locked.
Notes:
[1] Any SOnce bit in this register, once set can only be cleared
through a SYSRSn. Write of 0 to any bit of this register has no effect
[2] The locking mechanism applies to only writes. Reads to the
registers which have LOCK protection are always allowed
Reset type: SYSRSn

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3.16.10.2 DMACHSRCSELLOCK Register (Offset = 4h) [Reset = 0h]

DMACHSRCSELLOCK is shown in Figure 3-229 and described in Table 3-243.
Return to the Summary Table.
DMA Channel Triger Source Select Lock Register
Figure 3-229. DMACHSRCSELLOCK Register
31 30 29 28 27 26 25 24
RESERVED
R-0-0h

23 22 21 20 19 18 17 16
RESERVED
R-0-0h

15 14 13 12 11 10 9 8
RESERVED
R-0-0h

7 6 5 4 3 2 1 0
RESERVED DMACHSRCSE DMACHSRCSE
L2 L1
R-0-0h R/WSonce-0h R/WSonce-0h

Table 3-243. DMACHSRCSELLOCK Register Field Descriptions

Bit Field Type Reset Description
31-16 RESERVED R-0 0h Reserved
15-2 RESERVED R-0 0h Reserved
1 DMACHSRCSEL2 R/WSonce 0h DMACHSRCSEL2 Register Lock bit:
0: Respective register is not locked
1: Respective register is locked.
Notes:
[1] Any SOnce bit in this register, once set can only be cleared
through a SYSRSn. Write of 0 to any bit of this register has no effect
[2] The locking mechanism applies to only writes. Reads to the
registers which have LOCK protection are always allowed
Reset type: SYSRSn
0 DMACHSRCSEL1 R/WSonce 0h DMACHSRCSEL1 Register Lock bit:
0: Respective register is not locked
1: Respective register is locked.
Notes:
[1] Any SOnce bit in this register, once set can only be cleared
through a SYSRSn. Write of 0 to any bit of this register has no effect
[2] The locking mechanism applies to only writes. Reads to the
registers which have LOCK protection are always allowed
Reset type: SYSRSn

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3.16.10.3 CLA1TASKSRCSEL1 Register (Offset = 6h) [Reset = 0h]

CLA1TASKSRCSEL1 is shown in Figure 3-230 and described in Table 3-244.
Return to the Summary Table.
CLA1 Task Trigger Source Select Register-1
Figure 3-230. CLA1TASKSRCSEL1 Register
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TASK4 TASK3 TASK2 TASK1
R/W-0h R/W-0h R/W-0h R/W-0h

Table 3-244. CLA1TASKSRCSEL1 Register Field Descriptions

Bit Field Type Reset Description
31-24 TASK4 R/W 0h Selects the Trigger Source for TASK4 of CLA1
Reset type: SYSRSn
23-16 TASK3 R/W 0h Selects the Trigger Source for TASK3 of CLA1
Reset type: SYSRSn
15-8 TASK2 R/W 0h Selects the Trigger Source for TASK2 of CLA1
Reset type: SYSRSn
7-0 TASK1 R/W 0h Selects the Trigger Source for TASK1 of CLA1
Reset type: SYSRSn

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3.16.10.4 CLA1TASKSRCSEL2 Register (Offset = 8h) [Reset = 0h]

CLA1TASKSRCSEL2 is shown in Figure 3-231 and described in Table 3-245.
Return to the Summary Table.
CLA1 Task Trigger Source Select Register-2
Figure 3-231. CLA1TASKSRCSEL2 Register
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TASK8 TASK7 TASK6 TASK5
R/W-0h R/W-0h R/W-0h R/W-0h

Table 3-245. CLA1TASKSRCSEL2 Register Field Descriptions

Bit Field Type Reset Description
31-24 TASK8 R/W 0h Selects the Trigger Source for TASK8 of CLA1
Reset type: SYSRSn
23-16 TASK7 R/W 0h Selects the Trigger Source for TASK7 of CLA1
Reset type: SYSRSn
15-8 TASK6 R/W 0h Selects the Trigger Source for TASK6 of CLA1
Reset type: SYSRSn
7-0 TASK5 R/W 0h Selects the Trigger Source for TASK5 of CLA1
Reset type: SYSRSn

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3.16.10.5 DMACHSRCSEL1 Register (Offset = 16h) [Reset = 0h]

DMACHSRCSEL1 is shown in Figure 3-232 and described in Table 3-246.
Return to the Summary Table.
DMA Channel Trigger Source Select Register-1
Figure 3-232. DMACHSRCSEL1 Register
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CH4 CH3 CH2 CH1
R/W-0h R/W-0h R/W-0h R/W-0h

Table 3-246. DMACHSRCSEL1 Register Field Descriptions

Bit Field Type Reset Description
31-24 CH4 R/W 0h Selects the Trigger and Sync Source CH4 of DMA
Reset type: SYSRSn
23-16 CH3 R/W 0h Selects the Trigger and Sync Source CH3 of DMA
Reset type: SYSRSn
15-8 CH2 R/W 0h Selects the Trigger and Sync Source CH2 of DMA
Reset type: SYSRSn
7-0 CH1 R/W 0h Selects the Trigger and Sync Source CH1 of DMA
Reset type: SYSRSn

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3.16.10.6 DMACHSRCSEL2 Register (Offset = 18h) [Reset = 0h]

DMACHSRCSEL2 is shown in Figure 3-233 and described in Table 3-247.
Return to the Summary Table.
DMA Channel Trigger Source Select Register-2
Figure 3-233. DMACHSRCSEL2 Register
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RESERVED CH6 CH5
R-0-0h R/W-0h R/W-0h

Table 3-247. DMACHSRCSEL2 Register Field Descriptions

Bit Field Type Reset Description
31-16 RESERVED R-0 0h Reserved
15-8 CH6 R/W 0h Selects the Trigger and Sync Source CH6 of DMA
Reset type: SYSRSn
7-0 CH5 R/W 0h Selects the Trigger and Sync Source CH5 of DMA
Reset type: SYSRSn

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3.16.11 MEM_CFG_REGS Registers

Table 3-248 lists the memory-mapped registers for the MEM_CFG_REGS registers. All register offset addresses
not listed in Table 3-248 should be considered as reserved locations and the register contents should not be
modified.
Table 3-248. MEM_CFG_REGS Registers
Offset Acronym Register Name Write Protection Section
0h DxLOCK Dedicated RAM Config Lock Register EALLOW Go
2h DxCOMMIT Dedicated RAM Config Lock Commit Register EALLOW Go
8h DxACCPROT0 Dedicated RAM Config Register EALLOW Go
10h DxTEST Dedicated RAM TEST Register EALLOW Go
12h DxINIT Dedicated RAM Init Register EALLOW Go
14h DxINITDONE Dedicated RAM InitDone Status Register Go
16h DxRAMTEST_LOCK Lock register to Dx RAM TEST registers Go
20h LSxLOCK Local Shared RAM Config Lock Register EALLOW Go
22h LSxCOMMIT Local Shared RAM Config Lock Commit Register EALLOW Go
24h LSxMSEL Local Shared RAM Master Sel Register EALLOW Go
26h LSxCLAPGM Local Shared RAM Prog/Exe control Register EALLOW Go
28h LSxACCPROT0 Local Shared RAM Config Register 0 EALLOW Go
2Ah LSxACCPROT1 Local Shared RAM Config Register 1 EALLOW Go
30h LSxTEST Local Shared RAM TEST Register EALLOW Go
32h LSxINIT Local Shared RAM Init Register EALLOW Go
34h LSxINITDONE Local Shared RAM InitDone Status Register Go
36h LSxRAMTEST_LOCK Lock register to LSx RAM TEST registers Go
40h GSxLOCK Global Shared RAM Config Lock Register EALLOW Go
42h GSxCOMMIT Global Shared RAM Config Lock Commit EALLOW Go
Register
44h GSxMSEL Global Shared RAM Master Sel Register EALLOW Go
48h GSxACCPROT0 Global Shared RAM Access Protection Register 0 EALLOW Go
4Ah GSxACCPROT1 Global Shared RAM Access Protection Register 1 EALLOW Go
4Ch GSxACCPROT2 Global Shared RAM Access Protection Register 2 EALLOW Go
4Eh GSxACCPROT3 Global Shared RAM Access Protection Register 3 EALLOW Go
50h GSxTEST Global Shared RAM TEST Register EALLOW Go
52h GSxINIT Global Shared RAM Init Register EALLOW Go
54h GSxINITDONE Global Shared RAM InitDone Status Register Go
56h GSxRAMTEST_LOCK Lock register to GSx RAM TEST registers Go
60h MSGxLOCK Message RAM Config Lock Register Go
62h MSGxCOMMIT Message RAM Config Lock Commit Register Go
68h MSGxACCPROT0 Message RAM Access Protection Register 0 EALLOW Go
6Ah MSGxACCPROT1 Message RAM Access Protection Register 1 EALLOW Go
6Ch MSGxACCPROT2 Message RAM Access Protection Register 2 EALLOW Go
70h MSGxTEST Message RAM TEST Register EALLOW Go
72h MSGxINIT Message RAM Init Register EALLOW Go
74h MSGxINITDONE Message RAM InitDone Status Register Go
76h MSGxRAMTEST_LOCK Lock register to MSGx RAM TEST registers Go
A0h ROM_LOCK ROM Config Lock Register Go
A2h ROM_TEST ROM TEST Register Go
A4h ROM_FORCE_ERROR ROM Force Error register Go

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Table 3-248. MEM_CFG_REGS Registers (continued)

Offset Acronym Register Name Write Protection Section
AAh PERI_MEM_TEST_LOCK Peripheral Memory Test Lock Register Go
ACh PERI_MEM_TEST_CONTROL Peripheral Memory Test control Register Go

Complex bit access types are encoded to fit into small table cells. Table 3-249 shows the codes that are used for
access types in this section.
Table 3-249. MEM_CFG_REGS Access Type Codes
Access Type Code Description
Read Type
R R Read
R-0 R Read
-0 Returns 0s
Write Type
W W Write
W1S W Write
1S 1 to set
WSonce W Write
Sonce Set once
Reset or Default Value
-n Value after reset or the default
value
Register Array Variables
i,j,k,l,m,n When these variables are used in
a register name, an offset, or an
address, they refer to the value of
a register array where the register
is part of a group of repeating
registers. The register groups
form a hierarchical structure and
the array is represented with a
formula.
y When this variable is used in a
register name, an offset, or an
address it refers to the value of
a register array.

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3.16.11.1 DxLOCK Register (Offset = 0h) [Reset = 0h]

DxLOCK is shown in Figure 3-234 and described in Table 3-250.
Return to the Summary Table.
Dedicated RAM Config Lock Register
Figure 3-234. DxLOCK Register
31 30 29 28 27 26 25 24
RESERVED
R-0h

23 22 21 20 19 18 17 16
RESERVED
R-0h

15 14 13 12 11 10 9 8
RESERVED
R-0h

7 6 5 4 3 2 1 0
RESERVED LOCK_D1 LOCK_D0 LOCK_M1 LOCK_M0
R-0h R/W-0h R/W-0h R/W-0h R/W-0h

Table 3-250. DxLOCK Register Field Descriptions

Bit Field Type Reset Description
31-16 RESERVED R 0h Reserved
15-4 RESERVED R 0h Reserved
3 LOCK_D1 R/W 0h Locks the write to access protection, master select, initialization
control and test register fields for D1 RAM:
0: Write to ACCPROT, INIT and Mselect fields are allowed.
1: Write to ACCPROT, INIT and Mselect fields are blocked.
Reset type: SYSRSn
2 LOCK_D0 R/W 0h Locks the write to access protection, master select, initialization
control and test register fields for D0 RAM:
0: Write to ACCPROT, INIT and Mselect fields are allowed.
1: Write to ACCPROT, INIT and Mselect fields are blocked.
Reset type: SYSRSn
1 LOCK_M1 R/W 0h Locks the write to access protection, master select, initialization
control and test register fields for M1 RAM:
0: Write to ACCPROT, INIT and Mselect fields are allowed.
1: Write to ACCPROT, INIT and Mselect fields are blocked.
Reset type: SYSRSn
0 LOCK_M0 R/W 0h Locks the write to access protection, master select, initialization
control and test register fields for M0 RAM:
0: Write to ACCPROT, INIT and Mselect fields are allowed.
1: Write to ACCPROT, INIT and Mselect fields are blocked.
Reset type: SYSRSn

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3.16.11.2 DxCOMMIT Register (Offset = 2h) [Reset = 0h]

DxCOMMIT is shown in Figure 3-235 and described in Table 3-251.
Return to the Summary Table.
Dedicated RAM Config Lock Commit Register
Figure 3-235. DxCOMMIT Register
31 30 29 28 27 26 25 24
RESERVED
R-0h

23 22 21 20 19 18 17 16
RESERVED
R-0h

15 14 13 12 11 10 9 8
RESERVED
R-0h

7 6 5 4 3 2 1 0
RESERVED COMMIT_D1 COMMIT_D0 COMMIT_M1 COMMIT_M0
R-0h R/WSonce-0h R/WSonce-0h R/WSonce-0h R/WSonce-0h

Table 3-251. DxCOMMIT Register Field Descriptions

Bit Field Type Reset Description
31-16 RESERVED R 0h Reserved
15-4 RESERVED R 0h Reserved
3 COMMIT_D1 R/WSonce 0h Permanently Locks the write to access protection, master select,
initialization control and test register fields for D1 RAM:
0: Write to ACCPROT, INIT and Mselect fields are allowed based on
value of lock field in DxLOCK register.
1: Write to ACCPROT, INIT and Mselect fields are permanently
blocked.
Reset type: SYSRSn
2 COMMIT_D0 R/WSonce 0h Permanently Locks the write to access protection, master select,
initialization control and test register fields for D0 RAM:
0: Write to ACCPROT, INIT and Mselect fields are allowed based on
value of lock field in DxLOCK register.
1: Write to ACCPROT, INIT and Mselect fields are permanently
blocked.
Reset type: SYSRSn
1 COMMIT_M1 R/WSonce 0h Permanently Locks the write to access protection, master select,
initialization control and test register fields for M1 RAM:
0: Write to ACCPROT, INIT and Mselect fields are allowed based on
value of lock field in DxLOCK register.
1: Write to ACCPROT, INIT and Mselect fields are permanently
blocked.
Reset type: SYSRSn
0 COMMIT_M0 R/WSonce 0h Permanently Locks the write to access protection, master select,
initialization control and test register fields for M0 RAM:
0: Write to ACCPROT, INIT and Mselect fields are allowed based on
value of lock field in DxLOCK register.
1: Write to ACCPROT, INIT and Mselect fields are permanently
blocked.
Reset type: SYSRSn

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3.16.11.3 DxACCPROT0 Register (Offset = 8h) [Reset = 0h]

DxACCPROT0 is shown in Figure 3-236 and described in Table 3-252.
Return to the Summary Table.
Dedicated RAM Config Register
Figure 3-236. DxACCPROT0 Register
31 30 29 28 27 26 25 24
RESERVED CPUWRPROT_ FETCHPROT_
D1 D1
R-0h R/W-0h R/W-0h

23 22 21 20 19 18 17 16
RESERVED CPUWRPROT_ FETCHPROT_
D0 D0
R-0h R/W-0h R/W-0h

15 14 13 12 11 10 9 8
RESERVED CPUWRPROT_ FETCHPROT_
M1 M1
R-0h R/W-0h R/W-0h

7 6 5 4 3 2 1 0
RESERVED CPUWRPROT_ FETCHPROT_
M0 M0
R-0h R/W-0h R/W-0h

Table 3-252. DxACCPROT0 Register Field Descriptions

Bit Field Type Reset Description
31-26 RESERVED R 0h Reserved
25 CPUWRPROT_D1 R/W 0h CPU Write Protection For D1 RAM:
0: CPU Writes are allowed.
1: CPU Writes are blocked.
Reset type: SYSRSn
24 FETCHPROT_D1 R/W 0h Fetch Protection For D1 RAM:
0: CPU Fetch are allowed.
1: CPU Fetch are blocked.
Reset type: SYSRSn
23-18 RESERVED R 0h Reserved
17 CPUWRPROT_D0 R/W 0h CPU Write Protection For D0 RAM:
0: CPU Writes are allowed.
1: CPU Writes are block.
Reset type: SYSRSn
16 FETCHPROT_D0 R/W 0h Fetch Protection For D0 RAM:
0: CPU Fetch are allowed.
1: CPU Fetch are blocked.
Reset type: SYSRSn
15-10 RESERVED R 0h Reserved
9 CPUWRPROT_M1 R/W 0h CPU WR Protection For M1 RAM:
0: CPU Writes are allowed.
1: CPU Writes are block.
Reset type: SYSRSn
8 FETCHPROT_M1 R/W 0h Fetch Protection For M1 RAM:
0: CPU Fetch are allowed.
1: CPU Fetch are blocked.
Reset type: SYSRSn
7-2 RESERVED R 0h Reserved

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Table 3-252. DxACCPROT0 Register Field Descriptions (continued)

Bit Field Type Reset Description
1 CPUWRPROT_M0 R/W 0h CPU WR Protection For M0 RAM:
0: CPU Writes are allowed.
1: CPU Writes are block.
Reset type: SYSRSn
0 FETCHPROT_M0 R/W 0h Fetch Protection For M0 RAM:
0: CPU Fetch are allowed.
1: CPU Fetch are blocked.
Reset type: SYSRSn

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3.16.11.4 DxTEST Register (Offset = 10h) [Reset = 0h]

DxTEST is shown in Figure 3-237 and described in Table 3-253.
Return to the Summary Table.
Dedicated RAM TEST Register
Figure 3-237. DxTEST Register
31 30 29 28 27 26 25 24
RESERVED
R-0h

23 22 21 20 19 18 17 16
RESERVED
R-0h

15 14 13 12 11 10 9 8
RESERVED
R-0h

7 6 5 4 3 2 1 0
TEST_D1 TEST_D0 TEST_M1 TEST_M0
R/W-0h R/W-0h R/W-0h R/W-0h

Table 3-253. DxTEST Register Field Descriptions

Bit Field Type Reset Description
31-16 RESERVED R 0h Reserved
15-8 RESERVED R 0h Reserved
7-6 TEST_D1 R/W 0h Selects the defferent modes for D1 RAM:
00: Functional Mode.
01: Writes are allowed to data bits only. No write to ECC bits.
10: Writes are allowed to ECC bits only. No write to data bits.
11: Same as functional mode, but interrupt/nmi is not generated on
error.
Reset type: SYSRSn
5-4 TEST_D0 R/W 0h Selects the defferent modes for D0 RAM:
00: Functional Mode.
01: Writes are allowed to data bits only. No write to ECC bits.
10: Writes are allowed to ECC bits only. No write to data bits.
11: Same as functional mode, but interrupt/nmi is not generated on
error.
Reset type: SYSRSn
3-2 TEST_M1 R/W 0h Selects the defferent modes for M1 RAM:
00: Functional Mode.
01: Writes are allowed to data bits only. No write to ECC bits.
10: Writes are allowed to ECC bits only. No write to data bits.
11: Same as functional mode, but interrupt/nmi is not generated on
error.
Reset type: SYSRSn
1-0 TEST_M0 R/W 0h Selects the defferent modes for M0 RAM:
00: Functional Mode.
01: Writes are allowed to data bits only. No write to ECC bits.
10: Writes are allowed to ECC bits only. No write to data bits.
11: Same as functional mode, but interrupt/nmi is not generated on
error.
Reset type: SYSRSn

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3.16.11.5 DxINIT Register (Offset = 12h) [Reset = 0h]

DxINIT is shown in Figure 3-238 and described in Table 3-254.
Return to the Summary Table.
Dedicated RAM Init Register
Figure 3-238. DxINIT Register
31 30 29 28 27 26 25 24
RESERVED
R-0h

23 22 21 20 19 18 17 16
RESERVED
R-0h

15 14 13 12 11 10 9 8
RESERVED
R-0h

7 6 5 4 3 2 1 0
RESERVED INIT_D1 INIT_D0 INIT_M1 INIT_M0
R-0h R-0/W1S-0h R-0/W1S-0h R-0/W1S-0h R-0/W1S-0h

Table 3-254. DxINIT Register Field Descriptions

Bit Field Type Reset Description
31-16 RESERVED R 0h Reserved
15-4 RESERVED R 0h Reserved
3 INIT_D1 R-0/W1S 0h RAM Initialization control for D1 RAM:
0: None.
1: Start RAM Initialization.
Reset type: SYSRSn
2 INIT_D0 R-0/W1S 0h RAM Initialization control for D0 RAM:
0: None.
1: Start RAM Initialization.
Reset type: SYSRSn
1 INIT_M1 R-0/W1S 0h RAM Initialization control for M1 RAM:
0: None.
1: Start RAM Initialization.
Reset type: SYSRSn
0 INIT_M0 R-0/W1S 0h RAM Initialization control for M0 RAM:
0: None.
1: Start RAM Initialization.
Reset type: SYSRSn

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3.16.11.6 DxINITDONE Register (Offset = 14h) [Reset = 0h]

DxINITDONE is shown in Figure 3-239 and described in Table 3-255.
Return to the Summary Table.
Dedicated RAM InitDone Status Register
Figure 3-239. DxINITDONE Register
31 30 29 28 27 26 25 24
RESERVED
R-0h

23 22 21 20 19 18 17 16
RESERVED
R-0h

15 14 13 12 11 10 9 8
RESERVED
R-0h

7 6 5 4 3 2 1 0
RESERVED INITDONE_D1 INITDONE_D0 INITDONE_M1 INITDONE_M0
R-0h R-0h R-0h R-0h R-0h

Table 3-255. DxINITDONE Register Field Descriptions

Bit Field Type Reset Description
31-16 RESERVED R 0h Reserved
15-4 RESERVED R 0h Reserved
3 INITDONE_D1 R 0h RAM Initialization status for D1 RAM:
0: RAM Initialization has completed.
1: RAM Initialization has completed.
Reset type: SYSRSn
2 INITDONE_D0 R 0h RAM Initialization status for D0 RAM:
0: RAM Initialization is not done.
1: RAM Initialization is done.
Reset type: SYSRSn
1 INITDONE_M1 R 0h RAM Initialization status for M1 RAM:
0: RAM Initialization is not done.
1: RAM Initialization has completed.
Reset type: SYSRSn
0 INITDONE_M0 R 0h RAM Initialization status for M0 RAM:
0: RAM Initialization is not done.
1: RAM Initialization is done.
Reset type: SYSRSn

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3.16.11.7 DxRAMTEST_LOCK Register (Offset = 16h) [Reset = 0h]

DxRAMTEST_LOCK is shown in Figure 3-240 and described in Table 3-256.
Return to the Summary Table.
Lock register to Dx RAM TEST registers
Figure 3-240. DxRAMTEST_LOCK Register
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
KEY
R-0/W-0h

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RESERVED D1 D0 M1 M0
R-0h R/W-0h R/W-0h R/W-0h R/W-0h

Table 3-256. DxRAMTEST_LOCK Register Field Descriptions

Bit Field Type Reset Description
31-16 KEY R-0/W 0h A value of 0xa5a5 to this field is simultaneously required for the
writes to the rest of the fields of this register to succeed,
Reset type: SYSRSn
15-4 RESERVED R 0h Reserved
3 D1 R/W 0h 0: Allows writes to DxTEST.TEST_D1 field.
1: Blocks writes to DxTEST.TEST_D1 field
Reset type: SYSRSn
2 D0 R/W 0h 0: Allows writes to DxTEST.TEST_D0 field.
1: Blocks writes to DxTEST.TEST_D0 field
Reset type: SYSRSn
1 M1 R/W 0h 0: Allows writes to DxTEST.TEST_M1 field.
1: Blocks writes to DxTEST.TEST_M1 field
Reset type: SYSRSn
0 M0 R/W 0h 0: Allows writes to DxTEST.TEST_M0 field.
1: Blocks writes to DxTEST.TEST_M0 field
Reset type: SYSRSn

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3.16.11.8 LSxLOCK Register (Offset = 20h) [Reset = 0h]

LSxLOCK is shown in Figure 3-241 and described in Table 3-257.
Return to the Summary Table.
Local Shared RAM Config Lock Register
Figure 3-241. LSxLOCK Register
31 30 29 28 27 26 25 24
RESERVED
R-0h

23 22 21 20 19 18 17 16
RESERVED
R-0h

15 14 13 12 11 10 9 8
RESERVED
R-0h

7 6 5 4 3 2 1 0
LOCK_LS7 LOCK_LS6 LOCK_LS5 LOCK_LS4 LOCK_LS3 LOCK_LS2 LOCK_LS1 LOCK_LS0
R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h

Table 3-257. LSxLOCK Register Field Descriptions

Bit Field Type Reset Description
31-16 RESERVED R 0h Reserved
15-8 RESERVED R 0h Reserved
7 LOCK_LS7 R/W 0h Locks the write to access protection, master select, program or data
memory select, initialization control and register fields test for LS7
RAM:
0: Write to ACCPROT, INIT, CLAPGM and Mselect fields are
allowed.
1: Write to ACCPROT, INIT, CLAPGM and Mselect fields are
blocked.
Reset type: SYSRSn
6 LOCK_LS6 R/W 0h Locks the write to access protection, master select, program or data
memory select, initialization control and test register fields for LS6
RAM:
0: Write to ACCPROT, INIT, CLAPGM and Mselect fields are
allowed.
1: Write to ACCPROT, INIT, CLAPGM and Mselect fields are
blocked.
Reset type: SYSRSn
5 LOCK_LS5 R/W 0h Locks the write to access protection, master select, program or data
memory select, initialization control and test register fields for LS5
RAM:
0: Write to ACCPROT, INIT, CLAPGM and Mselect fields are
allowed.
1: Write to ACCPROT, INIT, CLAPGM and Mselect fields are
blocked.
Reset type: SYSRSn
4 LOCK_LS4 R/W 0h Locks the write to access protection, master select, program or data
memory select, initialization control and test register fields for LS4
RAM:
0: Write to ACCPROT, INIT, CLAPGM and Mselect fields are
allowed.
1: Write to ACCPROT, INIT, CLAPGM and Mselect fields are
blocked.
Reset type: SYSRSn

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Table 3-257. LSxLOCK Register Field Descriptions (continued)

Bit Field Type Reset Description
3 LOCK_LS3 R/W 0h Locks the write to access protection, master select, program or data
memory select, initialization control and test register fields for LS3
RAM:
0: Write to ACCPROT, INIT, CLAPGM and Mselect fields are
allowed.
1: Write to ACCPROT, INIT, CLAPGM and Mselect fields are
blocked.
Reset type: SYSRSn
2 LOCK_LS2 R/W 0h Locks the write to access protection, master select, program or data
memory select, initialization control and test register fields for LS2
RAM:
0: Write to ACCPROT, INIT, CLAPGM and Mselect fields are
allowed.
1: Write to ACCPROT, INIT, CLAPGM and Mselect fields are
blocked.
Reset type: SYSRSn
1 LOCK_LS1 R/W 0h Locks the write to access protection, master select, program or data
memory select, initialization control and test register fields for LS1
RAM:
0: Write to ACCPROT, INIT, CLAPGM and Mselect fields are
allowed.
1: Write to ACCPROT, INIT, CLAPGM and Mselect fields are
blocked.
Reset type: SYSRSn
0 LOCK_LS0 R/W 0h Locks the write to access protection, master select, program or data
memory select, initialization control and test register fields for LS0
RAM:
0: Write to ACCPROT, INIT, CLAPGM and Mselect fields are
allowed.
1: Write to ACCPROT, INIT, CLAPGM and Mselect fields are
blocked.
Reset type: SYSRSn

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3.16.11.9 LSxCOMMIT Register (Offset = 22h) [Reset = 0h]

LSxCOMMIT is shown in Figure 3-242 and described in Table 3-258.
Return to the Summary Table.
Local Shared RAM Config Lock Commit Register
Figure 3-242. LSxCOMMIT Register
31 30 29 28 27 26 25 24
RESERVED
R-0h

23 22 21 20 19 18 17 16
RESERVED
R-0h

15 14 13 12 11 10 9 8
RESERVED
R-0h

7 6 5 4 3 2 1 0
COMMIT_LS7 COMMIT_LS6 COMMIT_LS5 COMMIT_LS4 COMMIT_LS3 COMMIT_LS2 COMMIT_LS1 COMMIT_LS0
R/WSonce-0h R/WSonce-0h R/WSonce-0h R/WSonce-0h R/WSonce-0h R/WSonce-0h R/WSonce-0h R/WSonce-0h

Table 3-258. LSxCOMMIT Register Field Descriptions

Bit Field Type Reset Description
31-16 RESERVED R 0h Reserved
15-8 RESERVED R 0h Reserved
7 COMMIT_LS7 R/WSonce 0h Permanently Locks the write to access protection, master select,
program or data memory select, initialization control and test register
fields for LS7 RAM:
0: Write to ACCPROT, INIT, CLAPGM and Mselect fields are allowed
based on value of lock field in LSxLOCK register.
1: Write to ACCPROT, INIT, CLAPGM and Mselect fields are
permanently blocked.
Reset type: SYSRSn
6 COMMIT_LS6 R/WSonce 0h Permanently Locks the write to access protection, master select,
program or data memory select, initialization control and test register
fields for LS6 RAM:
0: Write to ACCPROT, INIT, CLAPGM and Mselect fields are allowed
based on value of lock field in LSxLOCK register.
1: Write to ACCPROT, INIT, CLAPGM and Mselect fields are
permanently blocked.
Reset type: SYSRSn
5 COMMIT_LS5 R/WSonce 0h Permanently Locks the write to access protection, master select,
program or data memory select, initialization control and test register
fields for LS5 RAM:
0: Write to ACCPROT, INIT, CLAPGM and Mselect fields are allowed
based on value of lock field in LSxLOCK register.
1: Write to ACCPROT, INIT, CLAPGM and Mselect fields are
permanently blocked.
Reset type: SYSRSn
4 COMMIT_LS4 R/WSonce 0h Permanently Locks the write to access protection, master select,
program or data memory select, initialization control and test register
fields for LS4 RAM:
0: Write to ACCPROT, INIT, CLAPGM and Mselect fields are allowed
based on value of lock field in LSxLOCK register.
1: Write to ACCPROT, INIT, CLAPGM and Mselect fields are
permanently blocked.
Reset type: SYSRSn

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Table 3-258. LSxCOMMIT Register Field Descriptions (continued)

Bit Field Type Reset Description
3 COMMIT_LS3 R/WSonce 0h Permanently Locks the write to access protection, master select,
program or data memory select, initialization control and test register
fields for LS3 RAM:
0: Write to ACCPROT, INIT, CLAPGM and Mselect fields are allowed
based on value of lock field in LSxLOCK register.
1: Write to ACCPROT, INIT, CLAPGM and Mselect fields are
permanently blocked.
Reset type: SYSRSn
2 COMMIT_LS2 R/WSonce 0h Permanently Locks the write to access protection, master select,
program or data memory select, initialization control and test register
fields for LS2 RAM:
0: Write to ACCPROT, INIT, CLAPGM and Mselect fields are allowed
based on value of lock field in LSxLOCK register.
1: Write to ACCPROT, INIT, CLAPGM and Mselect fields are
permanently blocked.
Reset type: SYSRSn
1 COMMIT_LS1 R/WSonce 0h Permanently Locks the write to access protection, master select,
program or data memory select, initialization control and test register
fields for LS1 RAM:
0: Write to ACCPROT, INIT, CLAPGM and Mselect fields are allowed
based on value of lock field in LSxLOCK register.
1: Write to ACCPROT, INIT, CLAPGM and Mselect fields are
permanently blocked.
Reset type: SYSRSn
0 COMMIT_LS0 R/WSonce 0h Permanently Locks the write to access protection, master select,
program or data memory select, initialization control and test register
fields for LS0 RAM:
0: Write to ACCPROT, INIT, CLAPGM and Mselect fields are allowed
based on value of lock field in LSxLOCK register.
1: Write to ACCPROT, INIT, CLAPGM and Mselect fields are
permanently blocked.
Reset type: SYSRSn

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3.16.11.10 LSxMSEL Register (Offset = 24h) [Reset = 0h]

LSxMSEL is shown in Figure 3-243 and described in Table 3-259.
Return to the Summary Table.
Local Shared RAM Master Sel Register
Figure 3-243. LSxMSEL Register
31 30 29 28 27 26 25 24
RESERVED
R-0h

23 22 21 20 19 18 17 16
RESERVED
R-0h

15 14 13 12 11 10 9 8
MSEL_LS7 MSEL_LS6 MSEL_LS5 MSEL_LS4
R/W-0h R/W-0h R/W-0h R/W-0h

7 6 5 4 3 2 1 0
MSEL_LS3 MSEL_LS2 MSEL_LS1 MSEL_LS0
R/W-0h R/W-0h R/W-0h R/W-0h

Table 3-259. LSxMSEL Register Field Descriptions

Bit Field Type Reset Description
31-16 RESERVED R 0h Reserved
15-14 MSEL_LS7 R/W 0h Master Select for LS7 RAM:
00: Memory is dedicated to CPU.
01: Memory is shared between CPU and CLA1 if CLAPGM_LSx bit
in LSxCLAPGM register is programmed as '0'.
10: Reserved.
11: Reserved.
Reset type: SYSRSn
13-12 MSEL_LS6 R/W 0h Master Select for LS6 RAM:
00: Memory is dedicated to CPU.
01: Memory is shared between CPU and CLA1 if CLAPGM_LSx bit
in LSxCLAPGM register is programmed as '0'.
10: Reserved.
11: Reserved.
Reset type: SYSRSn
11-10 MSEL_LS5 R/W 0h Master Select for LS5 RAM:
00: Memory is dedicated to CPU.
01: Memory is shared between CPU and CLA1 if CLAPGM_LSx bit
in LSxCLAPGM register is programmed as '0'.
10: Reserved.
11: Reserved.
Reset type: SYSRSn
9-8 MSEL_LS4 R/W 0h Master Select for LS4 RAM:
00: Memory is dedicated to CPU.
01: Memory is shared between CPU and CLA1 if CLAPGM_LSx bit
in LSxCLAPGM register is programmed as '0'.
10: Reserved.
11: Reserved.
Reset type: SYSRSn

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Table 3-259. LSxMSEL Register Field Descriptions (continued)

Bit Field Type Reset Description
7-6 MSEL_LS3 R/W 0h Master Select for LS3 RAM:
00: Memory is dedicated to CPU.
01: Memory is shared between CPU and CLA1 if CLAPGM_LSx bit
in LSxCLAPGM register is programmed as '0'.
10: Reserved.
11: Reserved.
Reset type: SYSRSn
5-4 MSEL_LS2 R/W 0h Master Select for LS2 RAM:
00: Memory is dedicated to CPU.
01: Memory is shared between CPU and CLA1 if CLAPGM_LSx bit
in LSxCLAPGM register is programmed as '0'.
10: Reserved.
11: Reserved.
Reset type: SYSRSn
3-2 MSEL_LS1 R/W 0h Master Select for LS1 RAM:
00: Memory is dedicated to CPU.
01: Memory is shared between CPU and CLA1 if CLAPGM_LSx bit
in LSxCLAPGM register is programmed as '0'.
10: Reserved.
11: Reserved.
Reset type: SYSRSn
1-0 MSEL_LS0 R/W 0h Master Select for LS0 RAM:
00: Memory is dedicated to CPU.
01: Memory is shared between CPU and CLA1 if CLAPGM_LSx bit
in LSxCLAPGM register is programmed as '0'.
10: Reserved.
11: Reserved.
Reset type: SYSRSn

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3.16.11.11 LSxCLAPGM Register (Offset = 26h) [Reset = 0h]

LSxCLAPGM is shown in Figure 3-244 and described in Table 3-260.
Return to the Summary Table.
Local Shared RAM Prog/Exe control Register
Figure 3-244. LSxCLAPGM Register
31 30 29 28 27 26 25 24
RESERVED
R-0h

23 22 21 20 19 18 17 16
RESERVED
R-0h

15 14 13 12 11 10 9 8
RESERVED
R-0h

7 6 5 4 3 2 1 0
CLAPGM_LS7 CLAPGM_LS6 CLAPGM_LS5 CLAPGM_LS4 CLAPGM_LS3 CLAPGM_LS2 CLAPGM_LS1 CLAPGM_LS0
R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h

Table 3-260. LSxCLAPGM Register Field Descriptions

Bit Field Type Reset Description
31-16 RESERVED R 0h Reserved
15-8 RESERVED R 0h Reserved
7 CLAPGM_LS7 R/W 0h Selects LS7 RAM as program vs data memory for CLA:
0: CLA Data memory.
1: CLA Program memory.
Reset type: SYSRSn
6 CLAPGM_LS6 R/W 0h Selects LS6 RAM as program vs data memory for CLA:
0: CLA Data memory.
1: CLA Program memory.
Reset type: SYSRSn
5 CLAPGM_LS5 R/W 0h Selects LS5 RAM as program vs data memory for CLA:
0: CLA Data memory.
1: CLA Program memory.
Reset type: SYSRSn
4 CLAPGM_LS4 R/W 0h Selects LS4 RAM as program vs data memory for CLA:
0: CLA Data memory.
1: CLA Program memory.
Reset type: SYSRSn
3 CLAPGM_LS3 R/W 0h Selects LS3 RAM as program vs data memory for CLA:
0: CLA Data memory.
1: CLA Program memory.
Reset type: SYSRSn
2 CLAPGM_LS2 R/W 0h Selects LS2 RAM as program vs data memory for CLA:
0: CLA Data memory.
1: CLA Program memory.
Reset type: SYSRSn
1 CLAPGM_LS1 R/W 0h Selects LS1 RAM as program vs data memory for CLA:
0: CLA Data memory.
1: CLA Program memory.
Reset type: SYSRSn

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Table 3-260. LSxCLAPGM Register Field Descriptions (continued)

Bit Field Type Reset Description
0 CLAPGM_LS0 R/W 0h Selects LS0 RAM as program vs data memory for CLA:
0: CLA Data memory.
1: CLA Program memory.
Reset type: SYSRSn

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3.16.11.12 LSxACCPROT0 Register (Offset = 28h) [Reset = 0h]

LSxACCPROT0 is shown in Figure 3-245 and described in Table 3-261.
Return to the Summary Table.
Local Shared RAM Config Register 0
Figure 3-245. LSxACCPROT0 Register
31 30 29 28 27 26 25 24
RESERVED CPUWRPROT_ FETCHPROT_L
LS3 S3
R-0h R/W-0h R/W-0h

23 22 21 20 19 18 17 16
RESERVED CPUWRPROT_ FETCHPROT_L
LS2 S2
R-0h R/W-0h R/W-0h

15 14 13 12 11 10 9 8
RESERVED CPUWRPROT_ FETCHPROT_L
LS1 S1
R-0h R/W-0h R/W-0h

7 6 5 4 3 2 1 0
RESERVED CPUWRPROT_ FETCHPROT_L
LS0 S0
R-0h R/W-0h R/W-0h

Table 3-261. LSxACCPROT0 Register Field Descriptions

Bit Field Type Reset Description
31-26 RESERVED R 0h Reserved
25 CPUWRPROT_LS3 R/W 0h CPU WR Protection For LS3 RAM:
0: CPU Writes are allowed.
1: CPU Writes are blocked.
Reset type: SYSRSn
24 FETCHPROT_LS3 R/W 0h Fetch Protection For LS3 RAM:
0: CPU Fetch are allowed.
1: CPU Fetch are blocked.
Reset type: SYSRSn
23-18 RESERVED R 0h Reserved
17 CPUWRPROT_LS2 R/W 0h CPU WR Protection For LS2 RAM:
0: CPU Writes are allowed.
1: CPU Writes are blocked.
Reset type: SYSRSn
16 FETCHPROT_LS2 R/W 0h Fetch Protection For LS2 RAM:
0: CPU Fetch are allowed.
1: CPU Fetch are blocked.
Reset type: SYSRSn
15-10 RESERVED R 0h Reserved
9 CPUWRPROT_LS1 R/W 0h CPU WR Protection For LS1 RAM:
0: CPU Writes are allowed.
1: CPU Writes are blocked.
Reset type: SYSRSn
8 FETCHPROT_LS1 R/W 0h Fetch Protection For LS1 RAM:
0: CPU Fetch are allowed.
1: CPU Fetch are blocked.
Reset type: SYSRSn
7-2 RESERVED R 0h Reserved

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Table 3-261. LSxACCPROT0 Register Field Descriptions (continued)

Bit Field Type Reset Description
1 CPUWRPROT_LS0 R/W 0h CPU WR Protection For LS0 RAM:
0: CPU Writes are allowed.
1: CPU Writes are blocked.
Reset type: SYSRSn
0 FETCHPROT_LS0 R/W 0h Fetch Protection For LS0 RAM:
0: CPU Fetch are allowed.
1: CPU Fetch are blocked.
Reset type: SYSRSn

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3.16.11.13 LSxACCPROT1 Register (Offset = 2Ah) [Reset = 0h]

LSxACCPROT1 is shown in Figure 3-246 and described in Table 3-262.
Return to the Summary Table.
Local Shared RAM Config Register 1
Figure 3-246. LSxACCPROT1 Register
31 30 29 28 27 26 25 24
RESERVED CPUWRPROT_ FETCHPROT_L
LS7 S7
R-0h R/W-0h R/W-0h

23 22 21 20 19 18 17 16
RESERVED CPUWRPROT_ FETCHPROT_L
LS6 S6
R-0h R/W-0h R/W-0h

15 14 13 12 11 10 9 8
RESERVED CPUWRPROT_ FETCHPROT_L
LS5 S5
R-0h R/W-0h R/W-0h

7 6 5 4 3 2 1 0
RESERVED CPUWRPROT_ FETCHPROT_L
LS4 S4
R-0h R/W-0h R/W-0h

Table 3-262. LSxACCPROT1 Register Field Descriptions

Bit Field Type Reset Description
31-26 RESERVED R 0h Reserved
25 CPUWRPROT_LS7 R/W 0h CPU WR Protection For LS7 RAM:
0: CPU Writes are allowed.
1: CPU Writes are blocked.
Reset type: SYSRSn
24 FETCHPROT_LS7 R/W 0h Fetch Protection For LS7 RAM:
0: CPU Fetch are allowed.
1: CPU Fetch are blocked.
Reset type: SYSRSn
23-18 RESERVED R 0h Reserved
17 CPUWRPROT_LS6 R/W 0h CPU WR Protection For LS6 RAM:
0: CPU Writes are allowed.
1: CPU Writes are blocked.
Reset type: SYSRSn
16 FETCHPROT_LS6 R/W 0h Fetch Protection For LS6 RAM:
0: CPU Fetch are allowed.
1: CPU Fetch are blocked.
Reset type: SYSRSn
15-10 RESERVED R 0h Reserved
9 CPUWRPROT_LS5 R/W 0h CPU WR Protection For LS5 RAM:
0: CPU Writes are allowed.
1: CPU Writes are blocked.
Reset type: SYSRSn
8 FETCHPROT_LS5 R/W 0h Fetch Protection For LS5 RAM:
0: CPU Fetch are allowed.
1: CPU Fetch are blocked.
Reset type: SYSRSn
7-2 RESERVED R 0h Reserved

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Table 3-262. LSxACCPROT1 Register Field Descriptions (continued)

Bit Field Type Reset Description
1 CPUWRPROT_LS4 R/W 0h CPU WR Protection For LS4 RAM:
0: CPU Writes are allowed.
1: CPU Writes are blocked.
Reset type: SYSRSn
0 FETCHPROT_LS4 R/W 0h Fetch Protection For LS4 RAM:
0: CPU Fetch are allowed.
1: CPU Fetch are blocked.
Reset type: SYSRSn

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3.16.11.14 LSxTEST Register (Offset = 30h) [Reset = 0h]

LSxTEST is shown in Figure 3-247 and described in Table 3-263.
Return to the Summary Table.
Local Shared RAM TEST Register
Figure 3-247. LSxTEST Register
31 30 29 28 27 26 25 24
RESERVED
R-0h

23 22 21 20 19 18 17 16
RESERVED
R-0h

15 14 13 12 11 10 9 8
TEST_LS7 TEST_LS6 TEST_LS5 TEST_LS4
R/W-0h R/W-0h R/W-0h R/W-0h

7 6 5 4 3 2 1 0
TEST_LS3 TEST_LS2 TEST_LS1 TEST_LS0
R/W-0h R/W-0h R/W-0h R/W-0h

Table 3-263. LSxTEST Register Field Descriptions

Bit Field Type Reset Description
31-16 RESERVED R 0h Reserved
15-14 TEST_LS7 R/W 0h Selects the defferent modes for LS7 RAM:
00: Functional Mode.
01: Writes are allowed to data bits only. No write to ecc bits.
10: Writes are allowed to ecc bits only. No write to data bits.
11: Functional Mode.
Reset type: SYSRSn
13-12 TEST_LS6 R/W 0h Selects the defferent modes for LS6 RAM:
00: Functional Mode.
01: Writes are allowed to data bits only. No write to ecc bits.
10: Writes are allowed to ecc bits only. No write to data bits.
11: Functional Mode.
Reset type: SYSRSn
11-10 TEST_LS5 R/W 0h Selects the defferent modes for LS5 RAM:
00: Functional Mode.
01: Writes are allowed to data bits only. No write to ecc bits.
10: Writes are allowed to ecc bits only. No write to data bits.
11: Functional Mode.
Reset type: SYSRSn
9-8 TEST_LS4 R/W 0h Selects the defferent modes for LS4 RAM:
00: Functional Mode.
01: Writes are allowed to data bits only. No write to ecc bits.
10: Writes are allowed to ecc bits only. No write to data bits.
11: Functional Mode.
Reset type: SYSRSn
7-6 TEST_LS3 R/W 0h Selects the defferent modes for LS3 RAM:
00: Functional Mode.
01: Writes are allowed to data bits only. No write to ecc bits.
10: Writes are allowed to ecc bits only. No write to data bits.
11: Functional Mode.
Reset type: SYSRSn

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Table 3-263. LSxTEST Register Field Descriptions (continued)

Bit Field Type Reset Description
5-4 TEST_LS2 R/W 0h Selects the defferent modes for LS2 RAM:
00: Functional Mode.
01: Writes are allowed to data bits only. No write to ecc bits.
10: Writes are allowed to ecc bits only. No write to data bits.
11: Functional Mode.
Reset type: SYSRSn
3-2 TEST_LS1 R/W 0h Selects the defferent modes for LS1 RAM:
00: Functional Mode.
01: Writes are allowed to data bits only. No write to ecc bits.
10: Writes are allowed to ecc bits only. No write to data bits.
11: Functional Mode.
Reset type: SYSRSn
1-0 TEST_LS0 R/W 0h Selects the defferent modes for LS0 RAM:
00: Functional Mode.
01: Writes are allowed to data bits only. No write to ecc bits.
10: Writes are allowed to ecc bits only. No write to data bits.
11: Functional Mode.
Reset type: SYSRSn

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3.16.11.15 LSxINIT Register (Offset = 32h) [Reset = 0h]

LSxINIT is shown in Figure 3-248 and described in Table 3-264.
Return to the Summary Table.
Local Shared RAM Init Register
Figure 3-248. LSxINIT Register
31 30 29 28 27 26 25 24
RESERVED
R-0h

23 22 21 20 19 18 17 16
RESERVED
R-0h

15 14 13 12 11 10 9 8
RESERVED
R-0h

7 6 5 4 3 2 1 0
INIT_LS7 INIT_LS6 INIT_LS5 INIT_LS4 INIT_LS3 INIT_LS2 INIT_LS1 INIT_LS0
R-0/W1S-0h R-0/W1S-0h R-0/W1S-0h R-0/W1S-0h R-0/W1S-0h R-0/W1S-0h R-0/W1S-0h R-0/W1S-0h

Table 3-264. LSxINIT Register Field Descriptions

Bit Field Type Reset Description
31-16 RESERVED R 0h Reserved
15-8 RESERVED R 0h Reserved
7 INIT_LS7 R-0/W1S 0h RAM Initialization control for LS7 RAM:
0: None.
1: Start RAM Initialization.
Reset type: SYSRSn
6 INIT_LS6 R-0/W1S 0h RAM Initialization control for LS6 RAM:
0: None.
1: Start RAM Initialization.
Reset type: SYSRSn
5 INIT_LS5 R-0/W1S 0h RAM Initialization control for LS5 RAM:
0: None.
1: Start RAM Initialization.
Reset type: SYSRSn
4 INIT_LS4 R-0/W1S 0h RAM Initialization control for LS4 RAM:
0: None.
1: Start RAM Initialization.
Reset type: SYSRSn
3 INIT_LS3 R-0/W1S 0h RAM Initialization control for LS3 RAM:
0: None.
1: Start RAM Initialization.
Reset type: SYSRSn
2 INIT_LS2 R-0/W1S 0h RAM Initialization control for LS2 RAM:
0: None.
1: Start RAM Initialization.
Reset type: SYSRSn
1 INIT_LS1 R-0/W1S 0h RAM Initialization control for LS1 RAM:
0: None.
1: Start RAM Initialization.
Reset type: SYSRSn

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Table 3-264. LSxINIT Register Field Descriptions (continued)

Bit Field Type Reset Description
0 INIT_LS0 R-0/W1S 0h RAM Initialization control for LS0 RAM:
0: None.
1: Start RAM Initialization.
Reset type: SYSRSn

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3.16.11.16 LSxINITDONE Register (Offset = 34h) [Reset = 0h]

LSxINITDONE is shown in Figure 3-249 and described in Table 3-265.
Return to the Summary Table.
Local Shared RAM InitDone Status Register
Figure 3-249. LSxINITDONE Register
31 30 29 28 27 26 25 24
RESERVED
R-0h

23 22 21 20 19 18 17 16
RESERVED
R-0h

15 14 13 12 11 10 9 8
RESERVED
R-0h

7 6 5 4 3 2 1 0
INITDONE_LS7 INITDONE_LS6 INITDONE_LS5 INITDONE_LS4 INITDONE_LS3 INITDONE_LS2 INITDONE_LS1 INITDONE_LS0
R-0h R-0h R-0h R-0h R-0h R-0h R-0h R-0h

Table 3-265. LSxINITDONE Register Field Descriptions

Bit Field Type Reset Description
31-16 RESERVED R 0h Reserved
15-8 RESERVED R 0h Reserved
7 INITDONE_LS7 R 0h RAM Initialization status for LS7 RAM:
0: RAM Initialization is not done.
1: RAM Initialization is done.
Reset type: SYSRSn
6 INITDONE_LS6 R 0h RAM Initialization status for LS6 RAM:
0: RAM Initialization is not done.
1: RAM Initialization is done.
Reset type: SYSRSn
5 INITDONE_LS5 R 0h RAM Initialization status for LS5 RAM:
0: RAM Initialization is not done.
1: RAM Initialization is done.
Reset type: SYSRSn
4 INITDONE_LS4 R 0h RAM Initialization status for LS4 RAM:
0: RAM Initialization is not done.
1: RAM Initialization is done.
Reset type: SYSRSn
3 INITDONE_LS3 R 0h RAM Initialization status for LS3 RAM:
0: RAM Initialization is not done.
1: RAM Initialization is done.
Reset type: SYSRSn
2 INITDONE_LS2 R 0h RAM Initialization status for LS2 RAM:
0: RAM Initialization is not done.
1: RAM Initialization is done.
Reset type: SYSRSn
1 INITDONE_LS1 R 0h RAM Initialization status for LS1 RAM:
0: RAM Initialization is not done.
1: RAM Initialization is done.
Reset type: SYSRSn

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Table 3-265. LSxINITDONE Register Field Descriptions (continued)

Bit Field Type Reset Description
0 INITDONE_LS0 R 0h RAM Initialization status for LS0 RAM:
0: RAM Initialization is not done.
1: RAM Initialization is done.
Reset type: SYSRSn

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3.16.11.17 LSxRAMTEST_LOCK Register (Offset = 36h) [Reset = 0h]

LSxRAMTEST_LOCK is shown in Figure 3-250 and described in Table 3-266.
Return to the Summary Table.
Lock register to LSx RAM TEST registers
Figure 3-250. LSxRAMTEST_LOCK Register
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
KEY
R-0/W-0h

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RESERVED LS7 LS6 LS5 LS4 LS3 LS2 LS1 LS0
R-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h

Table 3-266. LSxRAMTEST_LOCK Register Field Descriptions

Bit Field Type Reset Description
31-16 KEY R-0/W 0h A value of 0xa5a5 to this field is simultaneously required for the
writes to the rest of the fields of this register to succeed,
Reset type: SYSRSn
15-8 RESERVED R 0h Reserved
7 LS7 R/W 0h 0: Allows writes to LSxTEST.TEST_LS7 field.
1: Blocks writes to LSxTEST.TEST_LS7 field.
Reset type: SYSRSn
6 LS6 R/W 0h 0: Allows writes to LSxTEST.TEST_LS6 field.
1: Blocks writes to LSxTEST.TEST_LS6 field.
Reset type: SYSRSn
5 LS5 R/W 0h 0: Allows writes to LSxTEST.TEST_LS5 field.
1: Blocks writes to LSxTEST.TEST_LS5 field.
Reset type: SYSRSn
4 LS4 R/W 0h 0: Allows writes to LSxTEST.TEST_LS4 field.
1: Blocks writes to LSxTEST.TEST_LS4 field.
Reset type: SYSRSn
3 LS3 R/W 0h 0: Allows writes to LSxTEST.TEST_LS3 field.
1: Blocks writes to LSxTEST.TEST_LS3 field.
Reset type: SYSRSn
2 LS2 R/W 0h 0: Allows writes to LSxTEST.TEST_LS2 field.
1: Blocks writes to LSxTEST.TEST_LS2 field.
Reset type: SYSRSn
1 LS1 R/W 0h 0: Allows writes to LSxTEST.TEST_LS1 field.
1: Blocks writes to LSxTEST.TEST_LS1 field.
Reset type: SYSRSn
0 LS0 R/W 0h 0: Allows writes to LSxTEST.TEST_LS0 field.
1: Blocks writes to LSxTEST.TEST_LS0 field.
Reset type: SYSRSn

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3.16.11.18 GSxLOCK Register (Offset = 40h) [Reset = 0h]

GSxLOCK is shown in Figure 3-251 and described in Table 3-267.
Return to the Summary Table.
Global Shared RAM Config Lock Register
Figure 3-251. GSxLOCK Register
31 30 29 28 27 26 25 24
RESERVED
R-0h

23 22 21 20 19 18 17 16
RESERVED
R-0h

15 14 13 12 11 10 9 8
LOCK_GS15 LOCK_GS14 LOCK_GS13 LOCK_GS12 LOCK_GS11 LOCK_GS10 LOCK_GS9 LOCK_GS8
R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h

7 6 5 4 3 2 1 0
LOCK_GS7 LOCK_GS6 LOCK_GS5 LOCK_GS4 LOCK_GS3 LOCK_GS2 LOCK_GS1 LOCK_GS0
R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h

Table 3-267. GSxLOCK Register Field Descriptions

Bit Field Type Reset Description
31-16 RESERVED R 0h Reserved
15 LOCK_GS15 R/W 0h Locks the write to access protection, master select, initialization
control and test register fields for GS15 RAM:
0: Write to ACCPROT, INIT and Mselect fields are allowed.
1: Write to ACCPROT, INIT and Mselect fields are blocked.
Reset type: SYSRSn
14 LOCK_GS14 R/W 0h Locks the write to access protection, master select, initialization
control and test register fields for GS14 RAM:
0: Write to ACCPROT, INIT and Mselect fields are allowed.
1: Write to ACCPROT, INIT and Mselect fields are blocked.
Reset type: SYSRSn
13 LOCK_GS13 R/W 0h Locks the write to access protection, master select, initialization
control and test register fields for GS13 RAM:
0: Write to ACCPROT, INIT and Mselect fields are allowed.
1: Write to ACCPROT, INIT and Mselect fields are blocked.
Reset type: SYSRSn
12 LOCK_GS12 R/W 0h Locks the write to access protection, master select, initialization
control and test register fields for GS12 RAM:
0: Write to ACCPROT, INIT and Mselect fields are allowed.
1: Write to ACCPROT, INIT and Mselect fields are blocked.
Reset type: SYSRSn
11 LOCK_GS11 R/W 0h Locks the write to access protection, master select, initialization
control and test register fields for GS11 RAM:
0: Write to ACCPROT, INIT and Mselect fields are allowed.
1: Write to ACCPROT, INIT and Mselect fields are blocked.
Reset type: SYSRSn
10 LOCK_GS10 R/W 0h Locks the write to access protection, master select, initialization
control and test register fields for GS10 RAM:
0: Write to ACCPROT, INIT and Mselect fields are allowed.
1: Write to ACCPROT, INIT and Mselect fields are blocked.
Reset type: SYSRSn

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Table 3-267. GSxLOCK Register Field Descriptions (continued)

Bit Field Type Reset Description
9 LOCK_GS9 R/W 0h Locks the write to access protection, master select, initialization
control and test register fields for GS9 RAM:
0: Write to ACCPROT, INIT and Mselect fields are allowed.
1: Write to ACCPROT, INIT and Mselect fields are blocked.
Reset type: SYSRSn
8 LOCK_GS8 R/W 0h Locks the write to access protection, master select, initialization
control and test register fields for GS8 RAM:
0: Write to ACCPROT, INIT and Mselect fields are allowed.
1: Write to ACCPROT, INIT and Mselect fields are blocked.
Reset type: SYSRSn
7 LOCK_GS7 R/W 0h Locks the write to access protection, master select, initialization
control and test register fields for GS7 RAM:
0: Write to ACCPROT, INIT and Mselect fields are allowed.
1: Write to ACCPROT, INIT and Mselect fields are blocked.
Reset type: SYSRSn
6 LOCK_GS6 R/W 0h Locks the write to access protection, master select, initialization
control and test register fields for GS6 RAM:
0: Write to ACCPROT, INIT and Mselect fields are allowed.
1: Write to ACCPROT, INIT and Mselect fields are blocked.
Reset type: SYSRSn
5 LOCK_GS5 R/W 0h Locks the write to access protection, master select, initialization
control and test register fields for GS5 RAM:
0: Write to ACCPROT, INIT and Mselect fields are allowed.
1: Write to ACCPROT, INIT and Mselect fields are blocked.
Reset type: SYSRSn
4 LOCK_GS4 R/W 0h Locks the write to access protection, master select, initialization
control and test register fields for GS4 RAM:
0: Write to ACCPROT, INIT and Mselect fields are allowed.
1: Write to ACCPROT, INIT and Mselect fields are blocked.
Reset type: SYSRSn
3 LOCK_GS3 R/W 0h Locks the write to access protection, master select, initialization
control and test register fields for GS3 RAM:
0: Write to ACCPROT, INIT and Mselect fields are allowed.
1: Write to ACCPROT, INIT and Mselect fields are blocked.
Reset type: SYSRSn
2 LOCK_GS2 R/W 0h Locks the write to access protection, master select, initialization
control and test register fields for GS2 RAM:
0: Write to ACCPROT, INIT and Mselect fields are allowed.
1: Write to ACCPROT, INIT and Mselect fields are blocked.
Reset type: SYSRSn
1 LOCK_GS1 R/W 0h Locks the write to access protection, master select, initialization
control and test register fields for GS1 RAM:
0: Write to ACCPROT, INIT and Mselect fields are allowed.
1: Write to ACCPROT, INIT and Mselect fields are blocked.
Reset type: SYSRSn
0 LOCK_GS0 R/W 0h Locks the write to access protection, master select, initialization
control and test register fields for GS0 RAM:
0: Write to ACCPROT, INIT and Mselect fields are allowed.
1: Write to ACCPROT, INIT and Mselect fields are blocked.
Reset type: SYSRSn

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3.16.11.19 GSxCOMMIT Register (Offset = 42h) [Reset = 0h]

GSxCOMMIT is shown in Figure 3-252 and described in Table 3-268.
Return to the Summary Table.
Global Shared RAM Config Lock Commit Register
Figure 3-252. GSxCOMMIT Register
31 30 29 28 27 26 25 24
RESERVED
R-0h

23 22 21 20 19 18 17 16
RESERVED
R-0h

15 14 13 12 11 10 9 8
COMMIT_GS15 COMMIT_GS14 COMMIT_GS13 COMMIT_GS12 COMMIT_GS11 COMMIT_GS10 COMMIT_GS9 COMMIT_GS8
R/WSonce-0h R/WSonce-0h R/WSonce-0h R/WSonce-0h R/WSonce-0h R/WSonce-0h R/WSonce-0h R/WSonce-0h

7 6 5 4 3 2 1 0
COMMIT_GS7 COMMIT_GS6 COMMIT_GS5 COMMIT_GS4 COMMIT_GS3 COMMIT_GS2 COMMIT_GS1 COMMIT_GS0
R/WSonce-0h R/WSonce-0h R/WSonce-0h R/WSonce-0h R/WSonce-0h R/WSonce-0h R/WSonce-0h R/WSonce-0h

Table 3-268. GSxCOMMIT Register Field Descriptions

Bit Field Type Reset Description
31-16 RESERVED R 0h Reserved
15 COMMIT_GS15 R/WSonce 0h Permanently Locks the write to access protection, master select,
initialization control and test register fields for GS15 RAM:
0: Write to ACCPROT, INIT and Mselect fields are allowed based on
value of lock field in GSxLOCK register.
1: Write to ACCPROT, INIT and Mselect fields are permanently
blocked.
Reset type: SYSRSn
14 COMMIT_GS14 R/WSonce 0h Permanently Locks the write to access protection, master select,
initialization control and test register fields for GS14 RAM:
0: Write to ACCPROT, INIT and Mselect fields are allowed based on
value of lock field in GSxLOCK register.
1: Write to ACCPROT, INIT and Mselect fields are permanently
blocked.
Reset type: SYSRSn
13 COMMIT_GS13 R/WSonce 0h Permanently Locks the write to access protection, master select,
initialization control and test register fields for GS13 RAM:
0: Write to ACCPROT, INIT and Mselect fields are allowed based on
value of lock field in GSxLOCK register.
1: Write to ACCPROT, INIT and Mselect fields are permanently
blocked.
Reset type: SYSRSn
12 COMMIT_GS12 R/WSonce 0h Permanently Locks the write to access protection, master select,
initialization control and test register fields for GS12 RAM:
0: Write to ACCPROT, INIT and Mselect fields are allowed based on
value of lock field in GSxLOCK register.
1: Write to ACCPROT, INIT and Mselect fields are permanently
blocked.
Reset type: SYSRSn

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Table 3-268. GSxCOMMIT Register Field Descriptions (continued)

Bit Field Type Reset Description
11 COMMIT_GS11 R/WSonce 0h Permanently Locks the write to access protection, master select,
initialization control and test register fields for GS11 RAM:
0: Write to ACCPROT, INIT and Mselect fields are allowed based on
value of lock field in GSxLOCK register.
1: Write to ACCPROT, INIT and Mselect fields are permanently
blocked.
Reset type: SYSRSn
10 COMMIT_GS10 R/WSonce 0h Permanently Locks the write to access protection, master select,
initialization control and test register fields for GS10 RAM:
0: Write to ACCPROT, INIT and Mselect fields are allowed based on
value of lock field in GSxLOCK register.
1: Write to ACCPROT, INIT and Mselect fields are permanently
blocked.
Reset type: SYSRSn
9 COMMIT_GS9 R/WSonce 0h Permanently Locks the write to access protection, master select,
initialization control and test register fields for GS9 RAM:
0: Write to ACCPROT, INIT and Mselect fields are allowed based on
value of lock field in GSxLOCK register.
1: Write to ACCPROT, INIT and Mselect fields are permanently
blocked.
Reset type: SYSRSn
8 COMMIT_GS8 R/WSonce 0h Permanently Locks the write to access protection, master select,
initialization control and test register fields for GS8 RAM:
0: Write to ACCPROT, INIT and Mselect fields are allowed based on
value of lock field in GSxLOCK register.
1: Write to ACCPROT, INIT and Mselect fields are permanently
blocked.
Reset type: SYSRSn
7 COMMIT_GS7 R/WSonce 0h Permanently Locks the write to access protection, master select,
initialization control and test register fields for GS7 RAM:
0: Write to ACCPROT, INIT and Mselect fields are allowed based on
value of lock field in GSxLOCK register.
1: Write to ACCPROT, INIT and Mselect fields are permanently
blocked.
Reset type: SYSRSn
6 COMMIT_GS6 R/WSonce 0h Permanently Locks the write to access protection, master select,
initialization control and test register fields for GS6 RAM:
0: Write to ACCPROT, INIT and Mselect fields are allowed based on
value of lock field in GSxLOCK register.
1: Write to ACCPROT, INIT and Mselect fields are permanently
blocked.
Reset type: SYSRSn
5 COMMIT_GS5 R/WSonce 0h Permanently Locks the write to access protection, master select,
initialization control and test register fields for GS5 RAM:
0: Write to ACCPROT, INIT and Mselect fields are allowed based on
value of lock field in GSxLOCK register.
1: Write to ACCPROT, INIT and Mselect fields are permanently
blocked.
Reset type: SYSRSn
4 COMMIT_GS4 R/WSonce 0h Permanently Locks the write to access protection, master select,
initialization control and test register fields for GS4 RAM:
0: Write to ACCPROT, INIT and Mselect fields are allowed based on
value of lock field in GSxLOCK register.
1: Write to ACCPROT, INIT and Mselect fields are permanently
blocked.
Reset type: SYSRSn

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Table 3-268. GSxCOMMIT Register Field Descriptions (continued)

Bit Field Type Reset Description
3 COMMIT_GS3 R/WSonce 0h Permanently Locks the write to access protection, master select,
initialization control and test register fields for GS3 RAM:
0: Write to ACCPROT, INIT and Mselect fields are allowed based on
value of lock field in GSxLOCK register.
1: Write to ACCPROT, INIT and Mselect fields are permanently
blocked.
Reset type: SYSRSn
2 COMMIT_GS2 R/WSonce 0h Permanently Locks the write to access protection, master select,
initialization control and test register fields for GS2 RAM:
0: Write to ACCPROT, INIT and Mselect fields are allowed based on
value of lock field in GSxLOCK register.
1: Write to ACCPROT, INIT and Mselect fields are permanently
blocked.
Reset type: SYSRSn
1 COMMIT_GS1 R/WSonce 0h Permanently Locks the write to access protection, master select,
initialization control and test register fields for GS1 RAM:
0: Write to ACCPROT, INIT and Mselect fields are allowed based on
value of lock field in GSxLOCK register.
1: Write to ACCPROT, INIT and Mselect fields are permanently
blocked.
Reset type: SYSRSn
0 COMMIT_GS0 R/WSonce 0h Permanently Locks the write to access protection, master select,
initialization control and test register fields for GS0 RAM:
0: Write to ACCPROT, INIT and Mselect fields are allowed based on
value of lock field in GSxLOCK register.
1: Write to ACCPROT, INIT and Mselect fields are permanently
blocked.
Reset type: SYSRSn

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3.16.11.20 GSxMSEL Register (Offset = 44h) [Reset = 0h]

GSxMSEL is shown in Figure 3-253 and described in Table 3-269.
Return to the Summary Table.
Global Shared RAM Master Sel Register
Figure 3-253. GSxMSEL Register
31 30 29 28 27 26 25 24
RESERVED
R-0h

23 22 21 20 19 18 17 16
RESERVED
R-0h

15 14 13 12 11 10 9 8
MSEL_GS15 MSEL_GS14 MSEL_GS13 MSEL_GS12 MSEL_GS11 MSEL_GS10 MSEL_GS9 MSEL_GS8
R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h

7 6 5 4 3 2 1 0
MSEL_GS7 MSEL_GS6 MSEL_GS5 MSEL_GS4 MSEL_GS3 MSEL_GS2 MSEL_GS1 MSEL_GS0
R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h

Table 3-269. GSxMSEL Register Field Descriptions

Bit Field Type Reset Description
31-16 RESERVED R 0h Reserved
15 MSEL_GS15 R/W 0h Master Select for GS15 RAM:
0: CPU1 is master for this memory.
1: CPU2 is master for this memory.
Reset type: CPU1.SYSRSn
14 MSEL_GS14 R/W 0h Master Select for GS14 RAM:
0: CPU1 is master for this memory.
1: CPU2 is master for this memory.
Reset type: CPU1.SYSRSn
13 MSEL_GS13 R/W 0h Master Select for GS13 RAM:
0: CPU1 is master for this memory.
1: CPU2 is master for this memory.
Reset type: CPU1.SYSRSn
12 MSEL_GS12 R/W 0h Master Select for GS12 RAM:
0: CPU1 is master for this memory.
1: CPU2 is master for this memory.
Reset type: CPU1.SYSRSn
11 MSEL_GS11 R/W 0h Master Select for GS11 RAM:
0: CPU1 is master for this memory.
1: CPU2 is master for this memory.
Reset type: CPU1.SYSRSn
10 MSEL_GS10 R/W 0h Master Select for GS10 RAM:
0: CPU1 is master for this memory.
1: CPU2 is master for this memory.
Reset type: CPU1.SYSRSn
9 MSEL_GS9 R/W 0h Master Select for GS9 RAM:
0: CPU1 is master for this memory.
1: CPU2 is master for this memory.
Reset type: CPU1.SYSRSn
8 MSEL_GS8 R/W 0h Master Select for GS8 RAM:
0: CPU1 is master for this memory.
1: CPU2 is master for this memory.
Reset type: CPU1.SYSRSn

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Table 3-269. GSxMSEL Register Field Descriptions (continued)

Bit Field Type Reset Description
7 MSEL_GS7 R/W 0h Master Select for GS7 RAM:
0: CPU1 is master for this memory.
1: CPU2 is master for this memory.
Reset type: CPU1.SYSRSn
6 MSEL_GS6 R/W 0h Master Select for GS6 RAM:
0: CPU1 is master for this memory.
1: CPU2 is master for this memory.
Reset type: CPU1.SYSRSn
5 MSEL_GS5 R/W 0h Master Select for GS5 RAM:
0: CPU1 is master for this memory.
1: CPU2 is master for this memory.
Reset type: CPU1.SYSRSn
4 MSEL_GS4 R/W 0h Master Select for GS4 RAM:
0: CPU1 is master for this memory.
1: CPU2 is master for this memory.
Reset type: CPU1.SYSRSn
3 MSEL_GS3 R/W 0h Master Select for GS3 RAM:
0: CPU1 is master for this memory.
1: CPU2 is master for this memory.
Reset type: CPU1.SYSRSn
2 MSEL_GS2 R/W 0h Master Select for GS2 RAM:
0: CPU1 is master for this memory.
1: CPU2 is master for this memory.
Reset type: CPU1.SYSRSn
1 MSEL_GS1 R/W 0h Master Select for GS1 RAM:
0: CPU1 is master for this memory.
1: CPU2 is master for this memory.
Reset type: CPU1.SYSRSn
0 MSEL_GS0 R/W 0h Master Select for GS0 RAM:
0: CPU1 is master for this memory.
1: CPU2 is master for this memory.
Reset type: CPU1.SYSRSn

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3.16.11.21 GSxACCPROT0 Register (Offset = 48h) [Reset = 0h]

GSxACCPROT0 is shown in Figure 3-254 and described in Table 3-270.
Return to the Summary Table.
Global Shared RAM Access Protection Register 0
Figure 3-254. GSxACCPROT0 Register
31 30 29 28 27 26 25 24
RESERVED DMAWRPROT_ CPUWRPROT_ FETCHPROT_
GS3 GS3 GS3
R-0h R/W-0h R/W-0h R/W-0h

23 22 21 20 19 18 17 16
RESERVED DMAWRPROT_ CPUWRPROT_ FETCHPROT_
GS2 GS2 GS2
R-0h R/W-0h R/W-0h R/W-0h

15 14 13 12 11 10 9 8
RESERVED DMAWRPROT_ CPUWRPROT_ FETCHPROT_
GS1 GS1 GS1
R-0h R/W-0h R/W-0h R/W-0h

7 6 5 4 3 2 1 0
RESERVED DMAWRPROT_ CPUWRPROT_ FETCHPROT_
GS0 GS0 GS0
R-0h R/W-0h R/W-0h R/W-0h

Table 3-270. GSxACCPROT0 Register Field Descriptions

Bit Field Type Reset Description
31-27 RESERVED R 0h Reserved
26 DMAWRPROT_GS3 R/W 0h DMA WR Protection For GS3 RAM:
0: DMA Writes are allowed.
1: DMA Writes are blocked.
Reset type: SYSRSn
25 CPUWRPROT_GS3 R/W 0h CPU WR Protection For GS3 RAM:
0: CPU Writes are allowed.
1: CPU Writes are blocked.
Reset type: SYSRSn
24 FETCHPROT_GS3 R/W 0h Fetch Protection For GS3 RAM:
0: CPU Fetch are allowed.
1: CPU Fetch are blocked.
Reset type: SYSRSn
23-19 RESERVED R 0h Reserved
18 DMAWRPROT_GS2 R/W 0h DMA WR Protection For GS2 RAM:
0: DMA Writes are allowed.
1: DMA Writes are blocked.
Reset type: SYSRSn
17 CPUWRPROT_GS2 R/W 0h CPU WR Protection For GS2 RAM:
0: CPU Writes are allowed.
1: CPU Writes are blocked.
Reset type: SYSRSn
16 FETCHPROT_GS2 R/W 0h Fetch Protection For GS2 RAM:
0: CPU Fetch are allowed.
1: CPU Fetch are blocked.
Reset type: SYSRSn
15-11 RESERVED R 0h Reserved

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Table 3-270. GSxACCPROT0 Register Field Descriptions (continued)

Bit Field Type Reset Description
10 DMAWRPROT_GS1 R/W 0h DMA WR Protection For GS1 RAM:
0: DMA Writes are allowed.
1: DMA Writes are blocked.
Reset type: SYSRSn
9 CPUWRPROT_GS1 R/W 0h CPU WR Protection For GS1 RAM:
0: CPU Writes are allowed.
1: CPU Writes are blocked.
Reset type: SYSRSn
8 FETCHPROT_GS1 R/W 0h Fetch Protection For GS1 RAM:
0: CPU Fetch are allowed.
1: CPU Fetch are blocked.
Reset type: SYSRSn
7-3 RESERVED R 0h Reserved
2 DMAWRPROT_GS0 R/W 0h DMA WR Protection For GS0 RAM:
0: DMA Writes are allowed.
1: DMA Writes are blocked.
Reset type: SYSRSn
1 CPUWRPROT_GS0 R/W 0h CPU WR Protection For GS0 RAM:
0: CPU Writes are allowed.
1: CPU Writes are blocked.
Reset type: SYSRSn
0 FETCHPROT_GS0 R/W 0h Fetch Protection For GS0 RAM:
0: CPU Fetch are allowed.
1: CPU Fetch are blocked.
Reset type: SYSRSn

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3.16.11.22 GSxACCPROT1 Register (Offset = 4Ah) [Reset = 0h]

GSxACCPROT1 is shown in Figure 3-255 and described in Table 3-271.
Return to the Summary Table.
Global Shared RAM Access Protection Register 1
Figure 3-255. GSxACCPROT1 Register
31 30 29 28 27 26 25 24
RESERVED DMAWRPROT_ CPUWRPROT_ FETCHPROT_
GS7 GS7 GS7
R-0h R/W-0h R/W-0h R/W-0h

23 22 21 20 19 18 17 16
RESERVED DMAWRPROT_ CPUWRPROT_ FETCHPROT_
GS6 GS6 GS6
R-0h R/W-0h R/W-0h R/W-0h

15 14 13 12 11 10 9 8
RESERVED DMAWRPROT_ CPUWRPROT_ FETCHPROT_
GS5 GS5 GS5
R-0h R/W-0h R/W-0h R/W-0h

7 6 5 4 3 2 1 0
RESERVED DMAWRPROT_ CPUWRPROT_ FETCHPROT_
GS4 GS4 GS4
R-0h R/W-0h R/W-0h R/W-0h

Table 3-271. GSxACCPROT1 Register Field Descriptions

Bit Field Type Reset Description
31-27 RESERVED R 0h Reserved
26 DMAWRPROT_GS7 R/W 0h DMA WR Protection For GS7 RAM:
0: DMA Writes are allowed.
1: DMA Writes are blocked.
Reset type: SYSRSn
25 CPUWRPROT_GS7 R/W 0h CPU WR Protection For GS7 RAM:
0: CPU Writes are allowed.
1: CPU Writes are blocked.
Reset type: SYSRSn
24 FETCHPROT_GS7 R/W 0h Fetch Protection For GS7 RAM:
0: CPU Fetch are allowed.
1: CPU Fetch are blocked.
Reset type: SYSRSn
23-19 RESERVED R 0h Reserved
18 DMAWRPROT_GS6 R/W 0h DMA WR Protection For GS6 RAM:
0: DMA Writes are allowed.
1: DMA Writes are blocked.
Reset type: SYSRSn
17 CPUWRPROT_GS6 R/W 0h CPU WR Protection For GS6 RAM:
0: CPU Writes are allowed.
1: CPU Writes are blocked.
Reset type: SYSRSn
16 FETCHPROT_GS6 R/W 0h Fetch Protection For GS6 RAM:
0: CPU Fetch are allowed.
1: CPU Fetch are blocked.
Reset type: SYSRSn
15-11 RESERVED R 0h Reserved

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Table 3-271. GSxACCPROT1 Register Field Descriptions (continued)

Bit Field Type Reset Description
10 DMAWRPROT_GS5 R/W 0h DMA WR Protection For GS5 RAM:
0: DMA Writes are allowed.
1: DMA Writes are blocked.
Reset type: SYSRSn
9 CPUWRPROT_GS5 R/W 0h CPU WR Protection For GS5 RAM:
0: CPU Writes are allowed.
1: CPU Writes are blocked.
Reset type: SYSRSn
8 FETCHPROT_GS5 R/W 0h Fetch Protection For GS5 RAM:
0: CPU Fetch are allowed.
1: CPU Fetch are blocked.
Reset type: SYSRSn
7-3 RESERVED R 0h Reserved
2 DMAWRPROT_GS4 R/W 0h DMA WR Protection For GS4 RAM:
0: DMA Writes are allowed.
1: DMA Writes are blocked.
Reset type: SYSRSn
1 CPUWRPROT_GS4 R/W 0h CPU WR Protection For GS4 RAM:
0: CPU Writes are allowed.
1: CPU Writes are blocked.
Reset type: SYSRSn
0 FETCHPROT_GS4 R/W 0h Fetch Protection For GS4 RAM:
0: CPU Fetch are allowed.
1: CPU Fetch are blocked.
Reset type: SYSRSn

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3.16.11.23 GSxACCPROT2 Register (Offset = 4Ch) [Reset = 0h]

GSxACCPROT2 is shown in Figure 3-256 and described in Table 3-272.
Return to the Summary Table.
Global Shared RAM Access Protection Register 2
Figure 3-256. GSxACCPROT2 Register
31 30 29 28 27 26 25 24
RESERVED DMAWRPROT_ CPUWRPROT_ FETCHPROT_
GS11 GS11 GS11
R-0h R/W-0h R/W-0h R/W-0h

23 22 21 20 19 18 17 16
RESERVED DMAWRPROT_ CPUWRPROT_ FETCHPROT_
GS10 GS10 GS10
R-0h R/W-0h R/W-0h R/W-0h

15 14 13 12 11 10 9 8
RESERVED DMAWRPROT_ CPUWRPROT_ FETCHPROT_
GS9 GS9 GS9
R-0h R/W-0h R/W-0h R/W-0h

7 6 5 4 3 2 1 0
RESERVED DMAWRPROT_ CPUWRPROT_ FETCHPROT_
GS8 GS8 GS8
R-0h R/W-0h R/W-0h R/W-0h

Table 3-272. GSxACCPROT2 Register Field Descriptions

Bit Field Type Reset Description
31-27 RESERVED R 0h Reserved
26 DMAWRPROT_GS11 R/W 0h DMA WR Protection For GS11 RAM:
0: DMA Writes are allowed.
1: DMA Writes are blocked.
Reset type: SYSRSn
25 CPUWRPROT_GS11 R/W 0h CPU WR Protection For GS11 RAM:
0: CPU Writes are allowed.
1: CPU Writes are blocked.
Reset type: SYSRSn
24 FETCHPROT_GS11 R/W 0h Fetch Protection For GS11 RAM:
0: CPU Fetch are allowed.
1: CPU Fetch are blocked.
Reset type: SYSRSn
23-19 RESERVED R 0h Reserved
18 DMAWRPROT_GS10 R/W 0h DMA WR Protection For GS10 RAM:
0: DMA Writes are allowed.
1: DMA Writes are blocked.
Reset type: SYSRSn
17 CPUWRPROT_GS10 R/W 0h CPU WR Protection For GS10 RAM:
0: CPU Writes are allowed.
1: CPU Writes are blocked.
Reset type: SYSRSn
16 FETCHPROT_GS10 R/W 0h Fetch Protection For GS10 RAM:
0: CPU Fetch are allowed.
1: CPU Fetch are blocked.
Reset type: SYSRSn
15-11 RESERVED R 0h Reserved

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Table 3-272. GSxACCPROT2 Register Field Descriptions (continued)

Bit Field Type Reset Description
10 DMAWRPROT_GS9 R/W 0h DMA WR Protection For GS9 RAM:
0: DMA Writes are allowed.
1: DMA Writes are blocked.
Reset type: SYSRSn
9 CPUWRPROT_GS9 R/W 0h CPU WR Protection For GS9 RAM:
0: CPU Writes are allowed.
1: CPU Writes are blocked.
Reset type: SYSRSn
8 FETCHPROT_GS9 R/W 0h Fetch Protection For GS9 RAM:
0: CPU Fetch are allowed.
1: CPU Fetch are blocked.
Reset type: SYSRSn
7-3 RESERVED R 0h Reserved
2 DMAWRPROT_GS8 R/W 0h DMA WR Protection For GS8 RAM:
0: DMA Writes are allowed.
1: DMA Writes are blocked.
Reset type: SYSRSn
1 CPUWRPROT_GS8 R/W 0h CPU WR Protection For GS8 RAM:
0: CPU Writes are allowed.
1: CPU Writes are blocked.
Reset type: SYSRSn
0 FETCHPROT_GS8 R/W 0h Fetch Protection For GS8 RAM:
0: CPU Fetch are allowed.
1: CPU Fetch are blocked.
Reset type: SYSRSn

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3.16.11.24 GSxACCPROT3 Register (Offset = 4Eh) [Reset = 0h]

GSxACCPROT3 is shown in Figure 3-257 and described in Table 3-273.
Return to the Summary Table.
Global Shared RAM Access Protection Register 3
Figure 3-257. GSxACCPROT3 Register
31 30 29 28 27 26 25 24
RESERVED DMAWRPROT_ CPUWRPROT_ FETCHPROT_
GS15 GS15 GS15
R-0h R/W-0h R/W-0h R/W-0h

23 22 21 20 19 18 17 16
RESERVED DMAWRPROT_ CPUWRPROT_ FETCHPROT_
GS14 GS14 GS14
R-0h R/W-0h R/W-0h R/W-0h

15 14 13 12 11 10 9 8
RESERVED DMAWRPROT_ CPUWRPROT_ FETCHPROT_
GS13 GS13 GS13
R-0h R/W-0h R/W-0h R/W-0h

7 6 5 4 3 2 1 0
RESERVED DMAWRPROT_ CPUWRPROT_ FETCHPROT_
GS12 GS12 GS12
R-0h R/W-0h R/W-0h R/W-0h

Table 3-273. GSxACCPROT3 Register Field Descriptions

Bit Field Type Reset Description
31-27 RESERVED R 0h Reserved
26 DMAWRPROT_GS15 R/W 0h DMA WR Protection For GS15 RAM:
0: DMA Writes are allowed.
1: DMA Writes are blocked.
Reset type: SYSRSn
25 CPUWRPROT_GS15 R/W 0h CPU WR Protection For GS15 RAM:
0: CPU Writes are allowed.
1: CPU Writes are blocked.
Reset type: SYSRSn
24 FETCHPROT_GS15 R/W 0h Fetch Protection For GS15 RAM:
0: CPU Fetch are allowed.
1: CPU Fetch are blocked.
Reset type: SYSRSn
23-19 RESERVED R 0h Reserved
18 DMAWRPROT_GS14 R/W 0h DMA WR Protection For GS14 RAM:
0: DMA Writes are allowed.
1: DMA Writes are blocked.
Reset type: SYSRSn
17 CPUWRPROT_GS14 R/W 0h CPU WR Protection For GS14 RAM:
0: CPU Writes are allowed.
1: CPU Writes are blocked.
Reset type: SYSRSn
16 FETCHPROT_GS14 R/W 0h Fetch Protection For GS14 RAM:
0: CPU Fetch are allowed.
1: CPU Fetch are blocked.
Reset type: SYSRSn
15-11 RESERVED R 0h Reserved

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Table 3-273. GSxACCPROT3 Register Field Descriptions (continued)

Bit Field Type Reset Description
10 DMAWRPROT_GS13 R/W 0h DMA WR Protection For GS13 RAM:
0: DMA Writes are allowed.
1: DMA Writes are blocked.
Reset type: SYSRSn
9 CPUWRPROT_GS13 R/W 0h CPU WR Protection For GS13 RAM:
0: CPU Writes are allowed.
1: CPU Writes are blocked.
Reset type: SYSRSn
8 FETCHPROT_GS13 R/W 0h Fetch Protection For GS13 RAM:
0: CPU Fetch are allowed.
1: CPU Fetch are blocked.
Reset type: SYSRSn
7-3 RESERVED R 0h Reserved
2 DMAWRPROT_GS12 R/W 0h DMA WR Protection For GS12 RAM:
0: DMA Writes are allowed.
1: DMA Writes are blocked.
Reset type: SYSRSn
1 CPUWRPROT_GS12 R/W 0h CPU WR Protection For GS12 RAM:
0: CPU Writes are allowed.
1: CPU Writes are blocked.
Reset type: SYSRSn
0 FETCHPROT_GS12 R/W 0h Fetch Protection For GS12 RAM:
0: CPU Fetch are allowed.
1: CPU Fetch are blocked.
Reset type: SYSRSn

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3.16.11.25 GSxTEST Register (Offset = 50h) [Reset = 0h]

GSxTEST is shown in Figure 3-258 and described in Table 3-274.
Return to the Summary Table.
Global Shared RAM TEST Register
Figure 3-258. GSxTEST Register
31 30 29 28 27 26 25 24
TEST_GS15 TEST_GS14 TEST_GS13 TEST_GS12
R/W-0h R/W-0h R/W-0h R/W-0h

23 22 21 20 19 18 17 16
TEST_GS11 TEST_GS10 TEST_GS9 TEST_GS8
R/W-0h R/W-0h R/W-0h R/W-0h

15 14 13 12 11 10 9 8
TEST_GS7 TEST_GS6 TEST_GS5 TEST_GS4
R/W-0h R/W-0h R/W-0h R/W-0h

7 6 5 4 3 2 1 0
TEST_GS3 TEST_GS2 TEST_GS1 TEST_GS0
R/W-0h R/W-0h R/W-0h R/W-0h

Table 3-274. GSxTEST Register Field Descriptions

Bit Field Type Reset Description
31-30 TEST_GS15 R/W 0h Selects the defferent modes for GS15 RAM:
00: Functional Mode.
01: Writes are allowed to data bits only. No write to parity bits.
10: Writes are allowed to parity bits only. No write to data bits.
11: Same as functional mode, but interrupt/nmi is not generated on
error.
Note: Any non zero value would enable CPU writes over-riding write
access protection if any and will not generate a access protection
violation.
Reset type: SYSRSn
29-28 TEST_GS14 R/W 0h Selects the defferent modes for GS14 RAM:
00: Functional Mode.
01: Writes are allowed to data bits only. No write to parity bits.
10: Writes are allowed to parity bits only. No write to data bits.
11: Same as functional mode, but interrupt/nmi is not generated on
error.
Note: Any non zero value would enable CPU writes over-riding write
access protection if any and will not generate a access protection
violation.
Reset type: SYSRSn
27-26 TEST_GS13 R/W 0h Selects the defferent modes for GS13 RAM:
00: Functional Mode.
01: Writes are allowed to data bits only. No write to parity bits.
10: Writes are allowed to parity bits only. No write to data bits.
11: Same as functional mode, but interrupt/nmi is not generated on
error.
Note: Any non zero value would enable CPU writes over-riding write
access protection if any and will not generate a access protection
violation.
Reset type: SYSRSn

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Table 3-274. GSxTEST Register Field Descriptions (continued)

Bit Field Type Reset Description
25-24 TEST_GS12 R/W 0h Selects the defferent modes for GS12 RAM:
00: Functional Mode.
01: Writes are allowed to data bits only. No write to parity bits.
10: Writes are allowed to parity bits only. No write to data bits.
11: Same as functional mode, but interrupt/nmi is not generated on
error.
Note: Any non zero value would enable CPU writes over-riding write
access protection if any and will not generate a access protection
violation.
Reset type: SYSRSn
23-22 TEST_GS11 R/W 0h Selects the defferent modes for GS11 RAM:
00: Functional Mode.
01: Writes are allowed to data bits only. No write to parity bits.
10: Writes are allowed to parity bits only. No write to data bits.
11: Same as functional mode, but interrupt/nmi is not generated on
error.
Note: Any non zero value would enable CPU writes over-riding write
access protection if any and will not generate a access protection
violation.
Reset type: SYSRSn
21-20 TEST_GS10 R/W 0h Selects the defferent modes for GS10 RAM:
00: Functional Mode.
01: Writes are allowed to data bits only. No write to parity bits.
10: Writes are allowed to parity bits only. No write to data bits.
11: Same as functional mode, but interrupt/nmi is not generated on
error.
Note: Any non zero value would enable CPU writes over-riding write
access protection if any and will not generate a access protection
violation.
Reset type: SYSRSn
19-18 TEST_GS9 R/W 0h Selects the defferent modes for GS9 RAM:
00: Functional Mode.
01: Writes are allowed to data bits only. No write to parity bits.
10: Writes are allowed to parity bits only. No write to data bits.
11: Same as functional mode, but interrupt/nmi is not generated on
error.
Note: Any non zero value would enable CPU writes over-riding write
access protection if any and will not generate a access protection
violation.
Reset type: SYSRSn
17-16 TEST_GS8 R/W 0h Selects the defferent modes for GS8 RAM:
00: Functional Mode.
01: Writes are allowed to data bits only. No write to parity bits.
10: Writes are allowed to parity bits only. No write to data bits.
11: Same as functional mode, but interrupt/nmi is not generated on
error.
Note: Any non zero value would enable CPU writes over-riding write
access protection if any and will not generate a access protection
violation.
Reset type: SYSRSn
15-14 TEST_GS7 R/W 0h Selects the defferent modes for GS7 RAM:
00: Functional Mode.
01: Writes are allowed to data bits only. No write to parity bits.
10: Writes are allowed to parity bits only. No write to data bits.
11: Same as functional mode, but interrupt/nmi is not generated on
error.
Note: Any non zero value would enable CPU writes over-riding write
access protection if any and will not generate a access protection
violation.
Reset type: SYSRSn

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Table 3-274. GSxTEST Register Field Descriptions (continued)

Bit Field Type Reset Description
13-12 TEST_GS6 R/W 0h Selects the defferent modes for GS6 RAM:
00: Functional Mode.
01: Writes are allowed to data bits only. No write to parity bits.
10: Writes are allowed to parity bits only. No write to data bits.
11: Same as functional mode, but interrupt/nmi is not generated on
error.
Note: Any non zero value would enable CPU writes over-riding write
access protection if any and will not generate a access protection
violation.
Reset type: SYSRSn
11-10 TEST_GS5 R/W 0h Selects the defferent modes for GS5 RAM:
00: Functional Mode.
01: Writes are allowed to data bits only. No write to parity bits.
10: Writes are allowed to parity bits only. No write to data bits.
11: Same as functional mode, but interrupt/nmi is not generated on
error.
Note: Any non zero value would enable CPU writes over-riding write
access protection if any and will not generate a access protection
violation.
Reset type: SYSRSn
9-8 TEST_GS4 R/W 0h Selects the defferent modes for GS4 RAM:
00: Functional Mode.
01: Writes are allowed to data bits only. No write to parity bits.
10: Writes are allowed to parity bits only. No write to data bits.
11: Same as functional mode, but interrupt/nmi is not generated on
error.
Note: Any non zero value would enable CPU writes over-riding write
access protection if any and will not generate a access protection
violation.
Reset type: SYSRSn
7-6 TEST_GS3 R/W 0h Selects the defferent modes for GS3 RAM:
00: Functional Mode.
01: Writes are allowed to data bits only. No write to parity bits.
10: Writes are allowed to parity bits only. No write to data bits.
11: Same as functional mode, but interrupt/nmi is not generated on
error.
Note: Any non zero value would enable CPU writes over-riding write
access protection if any and will not generate a access protection
violation.
Reset type: SYSRSn
5-4 TEST_GS2 R/W 0h Selects the defferent modes for GS2 RAM:
00: Functional Mode.
01: Writes are allowed to data bits only. No write to parity bits.
10: Writes are allowed to parity bits only. No write to data bits.
11: Same as functional mode, but interrupt/nmi is not generated on
error.
Note: Any non zero value would enable CPU writes over-riding write
access protection if any and will not generate a access protection
violation.
Reset type: SYSRSn
3-2 TEST_GS1 R/W 0h Selects the defferent modes for GS1 RAM:
00: Functional Mode.
01: Writes are allowed to data bits only. No write to parity bits.
10: Writes are allowed to parity bits only. No write to data bits.
11: Same as functional mode, but interrupt/nmi is not generated on
error.
Note: Any non zero value would enable CPU writes over-riding write
access protection if any and will not generate a access protection
violation.
Reset type: SYSRSn

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Table 3-274. GSxTEST Register Field Descriptions (continued)

Bit Field Type Reset Description
1-0 TEST_GS0 R/W 0h Selects the defferent modes for GS0 RAM:
00: Functional Mode.
01: Writes are allowed to data bits only. No write to parity bits.
10: Writes are allowed to parity bits only. No write to data bits.
11: Same as functional mode, but interrupt/nmi is not generated on
error.
Note: Any non zero value would enable CPU writes over-riding write
access protection if any and will not generate a access protection
violation.
Reset type: SYSRSn

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3.16.11.26 GSxINIT Register (Offset = 52h) [Reset = 0h]

GSxINIT is shown in Figure 3-259 and described in Table 3-275.
Return to the Summary Table.
Global Shared RAM Init Register
Figure 3-259. GSxINIT Register
31 30 29 28 27 26 25 24
RESERVED
R-0h

23 22 21 20 19 18 17 16
RESERVED
R-0h

15 14 13 12 11 10 9 8
INIT_GS15 INIT_GS14 INIT_GS13 INIT_GS12 INIT_GS11 INIT_GS10 INIT_GS9 INIT_GS8
R-0/W1S-0h R-0/W1S-0h R-0/W1S-0h R-0/W1S-0h R-0/W1S-0h R-0/W1S-0h R-0/W1S-0h R-0/W1S-0h

7 6 5 4 3 2 1 0
INIT_GS7 INIT_GS6 INIT_GS5 INIT_GS4 INIT_GS3 INIT_GS2 INIT_GS1 INIT_GS0
R-0/W1S-0h R-0/W1S-0h R-0/W1S-0h R-0/W1S-0h R-0/W1S-0h R-0/W1S-0h R-0/W1S-0h R-0/W1S-0h

Table 3-275. GSxINIT Register Field Descriptions

Bit Field Type Reset Description
31-16 RESERVED R 0h Reserved
15 INIT_GS15 R-0/W1S 0h RAM Initialization control for GS15 RAM:
0: None.
1: Start RAM Initialization.
Reset type: SYSRSn
14 INIT_GS14 R-0/W1S 0h RAM Initialization control for GS14 RAM:
0: None.
1: Start RAM Initialization.
Reset type: SYSRSn
13 INIT_GS13 R-0/W1S 0h RAM Initialization control for GS13 RAM:
0: None.
1: Start RAM Initialization.
Reset type: SYSRSn
12 INIT_GS12 R-0/W1S 0h RAM Initialization control for GS12 RAM:
0: None.
1: Start RAM Initialization.
Reset type: SYSRSn
11 INIT_GS11 R-0/W1S 0h RAM Initialization control for GS11 RAM:
0: None.
1: Start RAM Initialization.
Reset type: SYSRSn
10 INIT_GS10 R-0/W1S 0h RAM Initialization control for GS10 RAM:
0: None.
1: Start RAM Initialization.
Reset type: SYSRSn
9 INIT_GS9 R-0/W1S 0h RAM Initialization control for GS9 RAM:
0: None.
1: Start RAM Initialization.
Reset type: SYSRSn
8 INIT_GS8 R-0/W1S 0h RAM Initialization control for GS8 RAM:
0: None.
1: Start RAM Initialization.
Reset type: SYSRSn

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Table 3-275. GSxINIT Register Field Descriptions (continued)

Bit Field Type Reset Description
7 INIT_GS7 R-0/W1S 0h RAM Initialization control for GS7 RAM:
0: None.
1: Start RAM Initialization.
Reset type: SYSRSn
6 INIT_GS6 R-0/W1S 0h RAM Initialization control for GS6 RAM:
0: None.
1: Start RAM Initialization.
Reset type: SYSRSn
5 INIT_GS5 R-0/W1S 0h RAM Initialization control for GS5 RAM:
0: None.
1: Start RAM Initialization.
Reset type: SYSRSn
4 INIT_GS4 R-0/W1S 0h RAM Initialization control for GS4 RAM:
0: None.
1: Start RAM Initialization.
Reset type: SYSRSn
3 INIT_GS3 R-0/W1S 0h RAM Initialization control for GS3 RAM:
0: None.
1: Start RAM Initialization.
Reset type: SYSRSn
2 INIT_GS2 R-0/W1S 0h RAM Initialization control for GS2 RAM:
0: None.
1: Start RAM Initialization.
Reset type: SYSRSn
1 INIT_GS1 R-0/W1S 0h RAM Initialization control for GS1 RAM:
0: None.
1: Start RAM Initialization.
Reset type: SYSRSn
0 INIT_GS0 R-0/W1S 0h RAM Initialization control for GS0 RAM:
0: None.
1: Start RAM Initialization.
Reset type: SYSRSn

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3.16.11.27 GSxINITDONE Register (Offset = 54h) [Reset = 0h]

GSxINITDONE is shown in Figure 3-260 and described in Table 3-276.
Return to the Summary Table.
Global Shared RAM InitDone Status Register
Figure 3-260. GSxINITDONE Register
31 30 29 28 27 26 25 24
RESERVED
R-0h

23 22 21 20 19 18 17 16
RESERVED
R-0h

15 14 13 12 11 10 9 8
INITDONE_GS INITDONE_GS INITDONE_GS INITDONE_GS INITDONE_GS INITDONE_GS INITDONE_GS INITDONE_GS
15 14 13 12 11 10 9 8
R-0h R-0h R-0h R-0h R-0h R-0h R-0h R-0h

7 6 5 4 3 2 1 0
INITDONE_GS INITDONE_GS INITDONE_GS INITDONE_GS INITDONE_GS INITDONE_GS INITDONE_GS INITDONE_GS
7 6 5 4 3 2 1 0
R-0h R-0h R-0h R-0h R-0h R-0h R-0h R-0h

Table 3-276. GSxINITDONE Register Field Descriptions

Bit Field Type Reset Description
31-16 RESERVED R 0h Reserved
15 INITDONE_GS15 R 0h RAM Initialization status for GS15 RAM:
0: RAM Initialization is not done.
1: RAM Initialization is done.
Reset type: SYSRSn
14 INITDONE_GS14 R 0h RAM Initialization status for GS14 RAM:
0: RAM Initialization is not done.
1: RAM Initialization is done.
Reset type: SYSRSn
13 INITDONE_GS13 R 0h RAM Initialization status for GS13 RAM:
0: RAM Initialization is not done.
1: RAM Initialization is done.
Reset type: SYSRSn
12 INITDONE_GS12 R 0h RAM Initialization status for GS12 RAM:
0: RAM Initialization is not done.
1: RAM Initialization is done.
Reset type: SYSRSn
11 INITDONE_GS11 R 0h RAM Initialization status for GS11 RAM:
0: RAM Initialization is not done.
1: RAM Initialization is done.
Reset type: SYSRSn
10 INITDONE_GS10 R 0h RAM Initialization status for GS10 RAM:
0: RAM Initialization is not done.
1: RAM Initialization is done.
Reset type: SYSRSn
9 INITDONE_GS9 R 0h RAM Initialization status for GS9 RAM:
0: RAM Initialization is not done.
1: RAM Initialization is done.
Reset type: SYSRSn

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Table 3-276. GSxINITDONE Register Field Descriptions (continued)

Bit Field Type Reset Description
8 INITDONE_GS8 R 0h RAM Initialization status for GS8 RAM:
0: RAM Initialization is not done.
1: RAM Initialization is done.
Reset type: SYSRSn
7 INITDONE_GS7 R 0h RAM Initialization status for GS7 RAM:
0: RAM Initialization is not done.
1: RAM Initialization is done.
Reset type: SYSRSn
6 INITDONE_GS6 R 0h RAM Initialization status for GS6 RAM:
0: RAM Initialization is not done.
1: RAM Initialization is done.
Reset type: SYSRSn
5 INITDONE_GS5 R 0h RAM Initialization status for GS5 RAM:
0: RAM Initialization is not done.
1: RAM Initialization is done.
Reset type: SYSRSn
4 INITDONE_GS4 R 0h RAM Initialization status for GS4 RAM:
0: RAM Initialization is not done.
1: RAM Initialization is done.
Reset type: SYSRSn
3 INITDONE_GS3 R 0h RAM Initialization status for GS3 RAM:
0: RAM Initialization is not done.
1: RAM Initialization is done.
Reset type: SYSRSn
2 INITDONE_GS2 R 0h RAM Initialization status for GS2 RAM:
0: RAM Initialization is not done.
1: RAM Initialization is done.
Reset type: SYSRSn
1 INITDONE_GS1 R 0h RAM Initialization status for GS1 RAM:
0: RAM Initialization is not done.
1: RAM Initialization is done.
Reset type: SYSRSn
0 INITDONE_GS0 R 0h RAM Initialization status for GS0 RAM:
0: RAM Initialization is not done.
1: RAM Initialization is done.
Reset type: SYSRSn

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3.16.11.28 GSxRAMTEST_LOCK Register (Offset = 56h) [Reset = 0h]

GSxRAMTEST_LOCK is shown in Figure 3-261 and described in Table 3-277.
Return to the Summary Table.
Lock register to GSx RAM TEST registers
Figure 3-261. GSxRAMTEST_LOCK Register
31 30 29 28 27 26 25 24
KEY
R-0/W-0h

23 22 21 20 19 18 17 16
KEY
R-0/W-0h

15 14 13 12 11 10 9 8
GS15 GS14 GS13 GS12 GS11 GS10 GS9 GS8
R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h

7 6 5 4 3 2 1 0
GS7 GS6 GS5 GS4 GS3 GS2 GS1 GS0
R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h

Table 3-277. GSxRAMTEST_LOCK Register Field Descriptions

Bit Field Type Reset Description
31-16 KEY R-0/W 0h A value of 0xa5a5 to this field is simultaneously required for the
writes to the rest of the fields of this register to succeed,
Reset type: SYSRSn
15 GS15 R/W 0h 0: Allows writes to GSxTEST.TEST_GS15 field.
1: Blocks writes to GSxTEST.TEST_GS15 field.
Reset type: SYSRSn
14 GS14 R/W 0h 0: Allows writes to GSxTEST.TEST_GS14 field.
1: Blocks writes to GSxTEST.TEST_GS14 field.
Reset type: SYSRSn
13 GS13 R/W 0h 0: Allows writes to GSxTEST.TEST_GS13 field.
1: Blocks writes to GSxTEST.TEST_GS13 field.
Reset type: SYSRSn
12 GS12 R/W 0h 0: Allows writes to GSxTEST.TEST_GS12 field.
1: Blocks writes to GSxTEST.TEST_GS12 field.
Reset type: SYSRSn
11 GS11 R/W 0h 0: Allows writes to GSxTEST.TEST_GS11 field.
1: Blocks writes to GSxTEST.TEST_GS11 field.
Reset type: SYSRSn
10 GS10 R/W 0h 0: Allows writes to GSxTEST.TEST_GS10 field.
1: Blocks writes to GSxTEST.TEST_GS10 field.
Reset type: SYSRSn
9 GS9 R/W 0h 0: Allows writes to GSxTEST.TEST_GS9 field.
1: Blocks writes to GSxTEST.TEST_GS9 field.
Reset type: SYSRSn
8 GS8 R/W 0h 0: Allows writes to GSxTEST.TEST_GS8 field.
1: Blocks writes to GSxTEST.TEST_GS8 field.
Reset type: SYSRSn
7 GS7 R/W 0h 0: Allows writes to GSxTEST.TEST_GS7 field.
1: Blocks writes to GSxTEST.TEST_GS7 field.
Reset type: SYSRSn

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Table 3-277. GSxRAMTEST_LOCK Register Field Descriptions (continued)

Bit Field Type Reset Description
6 GS6 R/W 0h 0: Allows writes to GSxTEST.TEST_GS6 field.
1: Blocks writes to GSxTEST.TEST_GS6 field.
Reset type: SYSRSn
5 GS5 R/W 0h 0: Allows writes to GSxTEST.TEST_GS5 field.
1: Blocks writes to GSxTEST.TEST_GS5 field.
Reset type: SYSRSn
4 GS4 R/W 0h 0: Allows writes to GSxTEST.TEST_GS4 field.
1: Blocks writes to GSxTEST.TEST_GS4 field.
Reset type: SYSRSn
3 GS3 R/W 0h 0: Allows writes to GSxTEST.TEST_GS3 field.
1: Blocks writes to GSxTEST.TEST_GS3 field.
Reset type: SYSRSn
2 GS2 R/W 0h 0: Allows writes to GSxTEST.TEST_GS2 field.
1: Blocks writes to GSxTEST.TEST_GS2 field.
Reset type: SYSRSn
1 GS1 R/W 0h 0: Allows writes to GSxTEST.TEST_GS1 field.
1: Blocks writes to GSxTEST.TEST_GS1 field.
Reset type: SYSRSn
0 GS0 R/W 0h 0: Allows writes to GSxTEST.TEST_GS0 field.
1: Blocks writes to GSxTEST.TEST_GS0 field.
Reset type: SYSRSn

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3.16.11.29 MSGxLOCK Register (Offset = 60h) [Reset = 0h]

MSGxLOCK is shown in Figure 3-262 and described in Table 3-278.
Return to the Summary Table.
Message RAM Config Lock Register
Figure 3-262. MSGxLOCK Register
31 30 29 28 27 26 25 24
RESERVED
R-0h

23 22 21 20 19 18 17 16
RESERVED
R-0h

15 14 13 12 11 10 9 8
RESERVED LOCK_DMATO LOCK_CLA2TO LOCK_CPUTO LOCK_CPUTO
CLA2 DMA CM_MSGRAM1 CM_MSGRAM0
R-0h R/W-0h R/W-0h R/W-0h R/W-0h

7 6 5 4 3 2 1 0
LOCK_CPUTO LOCK_DMATO LOCK_CLA1TO RESERVED RESERVED LOCK_CLA1TO LOCK_CPUTO LOCK_CPUTO
CPU_MSGRAM CLA1 DMA CPU CLA1 CPU_MSGRAM
1 0
R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h

Table 3-278. MSGxLOCK Register Field Descriptions

Bit Field Type Reset Description
31-12 RESERVED R 0h Reserved
11 LOCK_DMATOCLA2 R/W 0h Locks the write to access protection, master select, initialization
control and test register fields for DMA2CLA MSG RAM:
0: Write to INIT fields are allowed.
1: Write to INIT fields are blocked.
Reset type: SYSRSn
10 LOCK_CLA2TODMA R/W 0h Locks the write to access protection, master select, initialization
control and test register fields for CLA2DMA MSG RAM:
0: Write to INIT fields are allowed.
1: Write to INIT fields are blocked.
Reset type: SYSRSn
9 LOCK_CPUTOCM_MSGR R/W 0h Locks the write to access protection, master select, initialization
AM1 control and test register fields for CPU2CM MSG RAM1:
0: Write to INIT fields are allowed.
1: Write to INIT fields are blocked.
Reset type: SYSRSn
8 LOCK_CPUTOCM_MSGR R/W 0h Locks the write to access protection, master select, initialization
AM0 control and test register fields for CPU2CM MSG RAM0:
0: Write to INIT fields are allowed.
1: Write to INIT fields are blocked.
Reset type: SYSRSn
7 LOCK_CPUTOCPU_MSG R/W 0h Locks the write to access protection, master select, initialization
RAM1 control and test register fields for CPU2CPU MSG RAM1:
0: Write to INIT fields are allowed.
1: Write to INIT fields are blocked.
Reset type: SYSRSn
6 LOCK_DMATOCLA1 R/W 0h Locks the write to access protection, master select, initialization
control and test for DMATOCLA1 RAM:
0: Write to INIT fields are allowed.
1: Write to INIT fields are blocked.
Reset type: SYSRSn

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Table 3-278. MSGxLOCK Register Field Descriptions (continued)

Bit Field Type Reset Description
5 LOCK_CLA1TODMA R/W 0h Locks the write to access protection, master select, initialization
control and test for CLA1TODMA RAM:
0: Write to INIT fields are allowed.
1: Write to INIT fields are blocked.
Reset type: SYSRSn
4 RESERVED R/W 0h Reserved
3 RESERVED R/W 0h Reserved
2 LOCK_CLA1TOCPU R/W 0h Locks the write to access protection, master select, initialization
control and test register fields for CLA1TOCPU RAM:
0: Write to INIT fields are allowed.
1: Write to INIT fields are blocked.
Reset type: SYSRSn
1 LOCK_CPUTOCLA1 R/W 0h Locks the write to access protection, master select, initialization
control and test register fields for CPUTOCLA1 RAM:
0: Write to INIT fields are allowed.
1: Write to INIT fields are blocked.
Reset type: SYSRSn
0 LOCK_CPUTOCPU_MSG R/W 0h Locks the write to access protection, master select, initialization
RAM0 control and test register fields for CPU2CPU MSG RAM0:
0: Write to ACCPROT, INIT fields are allowed.
1: Write to ACCPROT, INIT fields are blocked.
Reset type: SYSRSn

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3.16.11.30 MSGxCOMMIT Register (Offset = 62h) [Reset = 0h]

MSGxCOMMIT is shown in Figure 3-263 and described in Table 3-279.
Return to the Summary Table.
Message RAM Config Lock Commit Register
Figure 3-263. MSGxCOMMIT Register
31 30 29 28 27 26 25 24
RESERVED
R-0h

23 22 21 20 19 18 17 16
RESERVED
R-0h

15 14 13 12 11 10 9 8
RESERVED COMMIT_DMA COMMIT_CLAT COMMIT_CPU COMMIT_CPU
TOCLA_MSGR ODMA_MSGRA TOCM_MSGRA TOCM_MSGRA
AM1 M0 M1 M0
R-0h R/WSonce-0h R/WSonce-0h R/WSonce-0h R/WSonce-0h

7 6 5 4 3 2 1 0
COMMIT_CPU COMMIT_DMA COMMIT_CLA1 RESERVED RESERVED COMMIT_CLA1 COMMIT_CPU COMMIT_CPU
TOCPU_MSGR TOCLA1 TODMA TOCPU TOCLA1 TOCPU_MSGR
AM1 AM0
R/WSonce-0h R/WSonce-0h R/WSonce-0h R/WSonce-0h R/WSonce-0h R/WSonce-0h R/WSonce-0h R/WSonce-0h

Table 3-279. MSGxCOMMIT Register Field Descriptions

Bit Field Type Reset Description
31-12 RESERVED R 0h Reserved
11 COMMIT_DMATOCLA_M R/WSonce 0h Permanently Locks the write to access protection, master select,
SGRAM1 initialization control and test register fields for DMA2CLA MSG RAM:
0: Write to INIT fields are allowed.
1: Write to INIT fields are blocked.
Reset type: SYSRSn
10 COMMIT_CLATODMA_M R/WSonce 0h Permanently Locks the write to access protection, master select,
SGRAM0 initialization control and test register fields for CLA2DMA MSG RAM:
0: Write to INIT fields are allowed.
1: Write to INIT fields are blocked.
Reset type: SYSRSn
9 COMMIT_CPUTOCM_MS R/WSonce 0h Permanently Locks the write to access protection, master select,
GRAM1 initialization control and test register fields for CPU2CM MSG RAM1:
0: Write to INIT fields are allowed.
1: Write to INIT fields are blocked.
Reset type: SYSRSn
8 COMMIT_CPUTOCM_MS R/WSonce 0h Permanently Locks the write to access protection, master select,
GRAM0 initialization control and test register fields for CPU2CM MSG RAM0:
0: Write to INIT fields are allowed.
1: Write to INIT fields are blocked.
Reset type: SYSRSn
7 COMMIT_CPUTOCPU_M R/WSonce 0h Permanently Locks the write to access protection, master select,
SGRAM1 initialization control and test register fields for CPU2CPU MSG
RAM1:
0: Write to INIT fields are allowed.
1: Write to INIT fields are blocked.
Reset type: SYSRSn
6 COMMIT_DMATOCLA1 R/WSonce 0h 0: Write to, INIT fields are allowed.
1: Write to, INIT fields are blocked.
Reset type: SYSRSn

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Table 3-279. MSGxCOMMIT Register Field Descriptions (continued)

Bit Field Type Reset Description
5 COMMIT_CLA1TODMA R/WSonce 0h 0: Write to, INIT fields are allowed.
1: Write to, INIT fields are blocked.
Reset type: SYSRSn
4 RESERVED R/WSonce 0h Reserved
3 RESERVED R/WSonce 0h Reserved
2 COMMIT_CLA1TOCPU R/WSonce 0h Locks the write to access protection, master select, initialization
control and test register fields for CLA1TOCPU RAM:
0: Write to ACCPROT, INIT and Mselect fields are allowed.
1: Write to ACCPROT, INIT and Mselect fields are blocked.
Reset type: SYSRSn
1 COMMIT_CPUTOCLA1 R/WSonce 0h Locks the write to access protection, master select, initialization
control and test register fields for CPUTOCLA1 RAM:
0: Write to ACCPROT, INIT and Mselect fields are allowed.
1: Write to ACCPROT, INIT and Mselect fields are blocked.
Reset type: SYSRSn
0 COMMIT_CPUTOCPU_M R/WSonce 0h Permanently Locks the write to access protection, master select,
SGRAM0 initialization control and test register fields for D0 RAM:
0: Write to ACCPROT, INIT fields are allowed based on value of lock
field in MSGxLOCK register.
1: Write to ACCPROT, INIT are permanently blocked.
Reset type: SYSRSn

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3.16.11.31 MSGxACCPROT0 Register (Offset = 68h) [Reset = 0h]

MSGxACCPROT0 is shown in Figure 3-264 and described in Table 3-280.
Return to the Summary Table.
Message RAM Access Protection Register 0
Figure 3-264. MSGxACCPROT0 Register
31 30 29 28 27 26 25 24
RESERVED RESERVED RESERVED RESERVED
R-0h R/W-0h R/W-0h R/W-0h

23 22 21 20 19 18 17 16
RESERVED RESERVED RESERVED RESERVED
R-0h R/W-0h R/W-0h R/W-0h

15 14 13 12 11 10 9 8
RESERVED RESERVED RESERVED RESERVED
R-0h R/W-0h R/W-0h R/W-0h

7 6 5 4 3 2 1 0
RESERVED DMAWRPROT_ CPUWRPROT_ RESERVED
CPUTOCPU_M CPUTOCPU_M
SGRAM0 SGRAM0
R-0h R/W-0h R/W-0h R/W-0h

Table 3-280. MSGxACCPROT0 Register Field Descriptions

Bit Field Type Reset Description
31-27 RESERVED R 0h Reserved
26 RESERVED R/W 0h Reserved
25 RESERVED R/W 0h Reserved
24 RESERVED R/W 0h Reserved
23-19 RESERVED R 0h Reserved
18 RESERVED R/W 0h Reserved
17 RESERVED R/W 0h Reserved
16 RESERVED R/W 0h Reserved
15-11 RESERVED R 0h Reserved
10 RESERVED R/W 0h Reserved
9 RESERVED R/W 0h Reserved
8 RESERVED R/W 0h Reserved
7-3 RESERVED R 0h Reserved
2 DMAWRPROT_CPUTOC R/W 0h DMA WR Protection For CPUTOCPU_MSGRAM0 RAM:
PU_MSGRAM0 0: DMA Writes are allowed.
1: DMA Writes are blocked.
Reset type: SYSRSn
1 CPUWRPROT_CPUTOC R/W 0h CPU WR Protection For CPUTOCPU_MSGRAM0 RAM:
PU_MSGRAM0 0: CPU Writes are allowed.
1: CPU Writes are blocked.
Reset type: SYSRSn
0 RESERVED R/W 0h Reserved

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3.16.11.32 MSGxACCPROT1 Register (Offset = 6Ah) [Reset = 0h]

MSGxACCPROT1 is shown in Figure 3-265 and described in Table 3-281.
Return to the Summary Table.
Message RAM Access Protection Register 1
Figure 3-265. MSGxACCPROT1 Register
31 30 29 28 27 26 25 24
RESERVED DMAWRPROT_ CPUWRPROT_ RESERVED
CPUTOCPU_M CPUTOCPU_M
SGRAM1 SGRAM1
R-0h R/W-0h R/W-0h R/W-0h

23 22 21 20 19 18 17 16
RESERVED RESERVED RESERVED RESERVED
R-0h R/W-0h R/W-0h R/W-0h

15 14 13 12 11 10 9 8
RESERVED RESERVED RESERVED RESERVED
R-0h R/W-0h R/W-0h R/W-0h

7 6 5 4 3 2 1 0
RESERVED RESERVED RESERVED RESERVED
R-0h R/W-0h R/W-0h R/W-0h

Table 3-281. MSGxACCPROT1 Register Field Descriptions

Bit Field Type Reset Description
31-27 RESERVED R 0h Reserved
26 DMAWRPROT_CPUTOC R/W 0h DMA WR Protection For CPUTOCPU_MSGRAM1 RAM:
PU_MSGRAM1 0: DMA Writes are allowed.
1: DMA Writes are blocked.
Reset type: SYSRSn
25 CPUWRPROT_CPUTOC R/W 0h CPU WR Protection For CPUTOCPU_MSGRAM1 RAM:
PU_MSGRAM1 0: CPU Writes are allowed.
1: CPU Writes are blocked.
Reset type: SYSRSn
24 RESERVED R/W 0h Reserved
23-19 RESERVED R 0h Reserved
18 RESERVED R/W 0h Reserved
17 RESERVED R/W 0h Reserved
16 RESERVED R/W 0h Reserved
15-11 RESERVED R 0h Reserved
10 RESERVED R/W 0h Reserved
9 RESERVED R/W 0h Reserved
8 RESERVED R/W 0h Reserved
7-3 RESERVED R 0h Reserved
2 RESERVED R/W 0h Reserved
1 RESERVED R/W 0h Reserved
0 RESERVED R/W 0h Reserved

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3.16.11.33 MSGxACCPROT2 Register (Offset = 6Ch) [Reset = 0h]

MSGxACCPROT2 is shown in Figure 3-266 and described in Table 3-282.
Return to the Summary Table.
Message RAM Access Protection Register 2
Figure 3-266. MSGxACCPROT2 Register
31 30 29 28 27 26 25 24
RESERVED RESERVED RESERVED RESERVED
R-0h R/W-0h R/W-0h R/W-0h

23 22 21 20 19 18 17 16
RESERVED RESERVED RESERVED RESERVED
R-0h R/W-0h R/W-0h R/W-0h

15 14 13 12 11 10 9 8
RESERVED DMAWRPROT_ CPUWRPROT_ RESERVED
CPUTOCM_MS CPUTOCM_MS
GRAM1 GRAM1
R-0h R/W-0h R/W-0h R/W-0h

7 6 5 4 3 2 1 0
RESERVED DMAWRPROT_ CPUWRPROT_ RESERVED
CPUTOCM_MS CPUTOCM_MS
GRAM0 GRAM0
R-0h R/W-0h R/W-0h R/W-0h

Table 3-282. MSGxACCPROT2 Register Field Descriptions

Bit Field Type Reset Description
31-27 RESERVED R 0h Reserved
26 RESERVED R/W 0h Reserved
25 RESERVED R/W 0h Reserved
24 RESERVED R/W 0h Reserved
23-19 RESERVED R 0h Reserved
18 RESERVED R/W 0h Reserved
17 RESERVED R/W 0h Reserved
16 RESERVED R/W 0h Reserved
15-11 RESERVED R 0h Reserved
10 DMAWRPROT_CPUTOC R/W 0h DMA WR Protection For CPUTOCM_MSGRAM1 RAM:
M_MSGRAM1 0: DMA Writes are allowed.
1: DMA Writes are blocked.
Reset type: SYSRSn
9 CPUWRPROT_CPUTOC R/W 0h CPU WR Protection For CPUTOCM_MSGRAM1 RAM:
M_MSGRAM1 0: CPU Writes are allowed.
1: CPU Writes are blocked.
Reset type: SYSRSn
8 RESERVED R/W 0h Reserved
7-3 RESERVED R 0h Reserved
2 DMAWRPROT_CPUTOC R/W 0h DMA WR Protection For CPUTOCM_MSGRAM0 RAM:
M_MSGRAM0 0: DMA Writes are allowed.
1: DMA Writes are blocked.
Reset type: SYSRSn

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Table 3-282. MSGxACCPROT2 Register Field Descriptions (continued)

Bit Field Type Reset Description
1 CPUWRPROT_CPUTOC R/W 0h CPU WR Protection For CPUTOCM_MSGRAM0 RAM:
M_MSGRAM0 0: CPU Writes are allowed.
1: CPU Writes are blocked.
Reset type: SYSRSn
0 RESERVED R/W 0h Reserved

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3.16.11.34 MSGxTEST Register (Offset = 70h) [Reset = 0h]

MSGxTEST is shown in Figure 3-267 and described in Table 3-283.
Return to the Summary Table.
Message RAM TEST Register
Figure 3-267. MSGxTEST Register
31 30 29 28 27 26 25 24
RESERVED
R-0h

23 22 21 20 19 18 17 16
RESERVED RESERVED TEST_CPUTOCM_MSGRAM1 TEST_CPUTOCM_MSGRAM0
R/W-0h R/W-0h R/W-0h R/W-0h

15 14 13 12 11 10 9 8
TEST_CPUTOCPU_MSGRAM1 TEST_DMATOCLA1 TEST_CLA1TODMA RESERVED
R/W-0h R/W-0h R/W-0h R/W-0h

7 6 5 4 3 2 1 0
RESERVED TEST_CLA1TOCPU TEST_CPUTOCLA1 TEST_CPUTOCPU_MSGRAM0
R/W-0h R/W-0h R/W-0h R/W-0h

Table 3-283. MSGxTEST Register Field Descriptions

Bit Field Type Reset Description
31-24 RESERVED R 0h Reserved
23-22 RESERVED R/W 0h Reserved
21-20 RESERVED R/W 0h Reserved
19-18 TEST_CPUTOCM_MSGR R/W 0h Selects the defferent modes for CPUTOCM MSG RAM1:
AM1 00: Functional Mode.
01: Writes are allowed to data bits only. No write to parity bits.
10: Writes are allowed to parity bits only. No write to data bits.
11: Same as functional mode, but interrupt/nmi is not generated on
error.
Note: Any non zero value would enable CPU writes over-riding write
access protection if any and will not generate a access protection
violation.
Reset type: SYSRSn
17-16 TEST_CPUTOCM_MSGR R/W 0h Selects the defferent modes for CPUTOCM MSG RAM0:
AM0 00: Functional Mode.
01: Writes are allowed to data bits only. No write to parity bits.
10: Writes are allowed to parity bits only. No write to data bits.
11: Same as functional mode, but interrupt/nmi is not generated on
error.
Note: Any non zero value would enable CPU writes over-riding write
access protection if any and will not generate a access protection
violation.
Reset type: SYSRSn
15-14 TEST_CPUTOCPU_MSG R/W 0h Selects the defferent modes for CPUTOCPU MSG RAM0:
RAM1 00: Functional Mode.
01: Writes are allowed to data bits only. No write to parity bits.
10: Writes are allowed to parity bits only. No write to data bits.
11: Same as functional mode, but interrupt/nmi is not generated on
error.
Note: Any non zero value would enable CPU writes over-riding write
access protection if any and will not generate a access protection
violation.
Reset type: SYSRSn

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Table 3-283. MSGxTEST Register Field Descriptions (continued)

Bit Field Type Reset Description
13-12 TEST_DMATOCLA1 R/W 0h Selects the defferent modes for DMATOCLA1 MSG RAM:
00: Functional Mode.
01: Writes are allowed to data bits only. No write to parity bits.
10: Writes are allowed to parity bits only. No write to data bits.
11: Same as functional mode, but interrupt/nmi is not generated on
error.
Note: Any non zero value would enable CPU writes over-riding write
access protection if any and will not generate a access protection
violation.
Reset type: SYSRSn
11-10 TEST_CLA1TODMA R/W 0h Selects the defferent modes for CLA1TODMA MSG RAM:
00: Functional Mode.
01: Writes are allowed to data bits only. No write to parity bits.
10: Writes are allowed to parity bits only. No write to data bits.
11: Same as functional mode, but interrupt/nmi is not generated on
error.
Note: Any non zero value would enable CPU writes over-riding write
access protection if any and will not generate a access protection
violation.
Reset type: SYSRSn
9-8 RESERVED R/W 0h Reserved
7-6 RESERVED R/W 0h Reserved
5-4 TEST_CLA1TOCPU R/W 0h Selects the defferent modes for CLA1TOCPU MSG RAM:
00: Functional Mode.
01: Writes are allowed to data bits only. No write to parity bits.
10: Writes are allowed to parity bits only. No write to data bits.
11: Same as functional mode, but interrupt/nmi is not generated on
error.
Note: Any non zero value would enable CPU writes over-riding write
access protection if any and will not generate a access protection
violation.
Reset type: SYSRSn
3-2 TEST_CPUTOCLA1 R/W 0h Selects the defferent modes for CPUTOCLA1 MSG RAM:
00: Functional Mode.
01: Writes are allowed to data bits only. No write to parity bits.
10: Writes are allowed to parity bits only. No write to data bits.
11: Same as functional mode, but interrupt/nmi is not generated on
error.
Note: Any non zero value would enable CPU writes over-riding write
access protection if any and will not generate a access protection
violation.
Reset type: SYSRSn
1-0 TEST_CPUTOCPU_MSG R/W 0h Selects the defferent modes for CPUTOCPU MSG RAM0:
RAM0 00: Functional Mode.
01: Writes are allowed to data bits only. No write to parity bits.
10: Writes are allowed to parity bits only. No write to data bits.
11: Same as functional mode, but interrupt/nmi is not generated on
error.
Note: Any non zero value would enable CPU writes over-riding write
access protection if any and will not generate a access protection
violation.
Reset type: SYSRSn

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3.16.11.35 MSGxINIT Register (Offset = 72h) [Reset = 0h]

MSGxINIT is shown in Figure 3-268 and described in Table 3-284.
Return to the Summary Table.
Message RAM Init Register
Figure 3-268. MSGxINIT Register
31 30 29 28 27 26 25 24
RESERVED
R-0h

23 22 21 20 19 18 17 16
RESERVED
R-0h

15 14 13 12 11 10 9 8
RESERVED RESERVED RESERVED INIT_CPUTOC INIT_CPUTOC
M_MSGRAM1 M_MSGRAM0
R-0h R-0/W1S-0h R-0/W1S-0h R-0/W1S-0h R-0/W1S-0h

7 6 5 4 3 2 1 0
INIT_CPUTOC INIT_DMATOCL INIT_CLA1TOD RESERVED RESERVED INIT_CLA1TOC INIT_CPUTOCL INIT_CPUTOC
PU_MSGRAM1 A1 MA PU A1 PU_MSGRAM0
R-0/W1S-0h R-0/W1S-0h R-0/W1S-0h R-0/W1S-0h R-0/W1S-0h R-0/W1S-0h R-0/W1S-0h R-0/W1S-0h

Table 3-284. MSGxINIT Register Field Descriptions

Bit Field Type Reset Description
31-12 RESERVED R 0h Reserved
11 RESERVED R-0/W1S 0h Reserved
10 RESERVED R-0/W1S 0h Reserved
9 INIT_CPUTOCM_MSGRA R-0/W1S 0h RAM Initialization control for CPUTOCM MSG RAM1:
M1 0: None.
1: Start RAM Initialization.
Reset type: SYSRSn
8 INIT_CPUTOCM_MSGRA R-0/W1S 0h RAM Initialization control for CPUTOCM MSG RAM0:
M0 0: None.
1: Start RAM Initialization.
Reset type: SYSRSn
7 INIT_CPUTOCPU_MSGR R-0/W1S 0h RAM Initialization control for CPUTOCPU MSG RAM1:
AM1 0: None.
1: Start RAM Initialization.
Reset type: SYSRSn
6 INIT_DMATOCLA1 R-0/W1S 0h RAM Initialization control for DMATOCLA1 MSG RAM:
0: None.
1: Start RAM Initialization.
Reset type: SYSRSn
5 INIT_CLA1TODMA R-0/W1S 0h RAM Initialization control for CLA1TODMA MSG RAM:
0: None.
1: Start RAM Initialization.
Reset type: SYSRSn
4 RESERVED R-0/W1S 0h Reserved
3 RESERVED R-0/W1S 0h Reserved
2 INIT_CLA1TOCPU R-0/W1S 0h RAM Initialization control for CLA1TOCPU MSG RAM:
0: None.
1: Start RAM Initialization.
Reset type: SYSRSn

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Table 3-284. MSGxINIT Register Field Descriptions (continued)

Bit Field Type Reset Description
1 INIT_CPUTOCLA1 R-0/W1S 0h RAM Initialization control for CPUTOCLA1 MSG RAM:
0: None.
1: Start RAM Initialization.
Reset type: SYSRSn
0 INIT_CPUTOCPU_MSGR R-0/W1S 0h RAM Initialization control for CPUTOCPU MSG RAM0:
AM0 0: None.
1: Start RAM Initialization.
Reset type: SYSRSn

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3.16.11.36 MSGxINITDONE Register (Offset = 74h) [Reset = 0h]

MSGxINITDONE is shown in Figure 3-269 and described in Table 3-285.
Return to the Summary Table.
Message RAM InitDone Status Register
Figure 3-269. MSGxINITDONE Register
31 30 29 28 27 26 25 24
RESERVED
R-0h

23 22 21 20 19 18 17 16
RESERVED
R-0h

15 14 13 12 11 10 9 8
RESERVED RESERVED RESERVED INITDONE_CP INITDONE_CP
UTOCM_MSGR UTOCM_MSGR
AM1 AM0
R-0h R-0h R-0h R-0h R-0h

7 6 5 4 3 2 1 0
INITDONE_CP INITDONE_DM INITDONE_CL RESERVED RESERVED INITDONE_CL INITDONE_CP INITDONE_CP
UTOCPU_MSG ATOCLA1 A1TODMA A1TOCPU UTOCLA1 UTOCPU_MSG
RAM1 RAM0
R-0h R-0h R-0h R-0h R-0h R-0h R-0h R-0h

Table 3-285. MSGxINITDONE Register Field Descriptions

Bit Field Type Reset Description
31-12 RESERVED R 0h Reserved
11 RESERVED R 0h Reserved
10 RESERVED R 0h Reserved
9 INITDONE_CPUTOCM_M R 0h RAM Initialization status for CPUTOCM MSG RAM1:
SGRAM1 0: None.
1: Start RAM Initialization.
Reset type: SYSRSn
8 INITDONE_CPUTOCM_M R 0h RAM Initialization status for CPUTOCM MSG RAM0:
SGRAM0 0: None.
1: Start RAM Initialization.
Reset type: SYSRSn
7 INITDONE_CPUTOCPU_ R 0h RAM Initialization status for CPUTOCPU MSG RAM1:
MSGRAM1 0: None.
1: Start RAM Initialization.
Reset type: SYSRSn
6 INITDONE_DMATOCLA1 R 0h RAM Initialization status for DMATOCLA1 MSG RAM:
0: RAM Initialization is not done.
1: RAM Initialization is done.
Reset type: SYSRSn
5 INITDONE_CLA1TODMA R 0h RAM Initialization status for CLA1TODMA MSG RAM:
0: RAM Initialization is not done.
1: RAM Initialization is done.
Reset type: SYSRSn
4 RESERVED R 0h Reserved
3 RESERVED R 0h Reserved

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Table 3-285. MSGxINITDONE Register Field Descriptions (continued)

Bit Field Type Reset Description
2 INITDONE_CLA1TOCPU R 0h RAM Initialization status for CLA1TOCPU MSG RAM:
0: RAM Initialization is not done.
1: RAM Initialization is done.
Reset type: SYSRSn
1 INITDONE_CPUTOCLA1 R 0h RAM Initialization status for CPUTOCLA1 MSG RAM:
0: RAM Initialization is not done.
1: RAM Initialization is done.
Reset type: SYSRSn
0 INITDONE_CPUTOCPU_ R 0h RAM Initialization status for CPUTOCPU MSG RAM:
MSGRAM0 0: RAM Initialization is not done.
1: RAM Initialization is done.
Reset type: SYSRSn

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3.16.11.37 MSGxRAMTEST_LOCK Register (Offset = 76h) [Reset = 0h]

MSGxRAMTEST_LOCK is shown in Figure 3-270 and described in Table 3-286.
Return to the Summary Table.
Lock register to MSGx RAM TEST registers
Figure 3-270. MSGxRAMTEST_LOCK Register
31 30 29 28 27 26 25 24
KEY
R-0/W-0h

23 22 21 20 19 18 17 16
KEY
R-0/W-0h

15 14 13 12 11 10 9 8
RESERVED DMATOCLA2 CLA2TODMA CPUTOCM_MS CPUTOCM_MS
GRAM1 GRAM0
R-0h R/W-0h R/W-0h R/W-0h R/W-0h

7 6 5 4 3 2 1 0
CPUTOCPU_M DMATOCLA1 CLA1TODMA CLA2TOCPU CPUTOCLA2 CLA1TOCPU CPUTOCLA1 CPUTOCPU_M
SGRAM1 SGRAM0
R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h

Table 3-286. MSGxRAMTEST_LOCK Register Field Descriptions

Bit Field Type Reset Description
31-16 KEY R-0/W 0h A value of 0xa5a5 to this field is simultaneously required for the
writes to the rest of the fields of this register to succeed,
Reset type: SYSRSn
15-12 RESERVED R 0h Reserved
11 DMATOCLA2 R/W 0h 0: Allows writes to MSGxTEST.TEST_DMATOCLA2 field.
1: Blocks writes to MSGxTEST.TEST_DMATOCLA2 field.
Reset type: SYSRSn
10 CLA2TODMA R/W 0h 0: Allows writes to MSGxTEST.TEST_CLA2TODMA field.
1: Blocks writes to MSGxTEST.TEST_CLA2TODMA field.
Reset type: SYSRSn
9 CPUTOCM_MSGRAM1 R/W 0h 0: Allows writes to MSGxTEST.TEST_CPUTOCM_MSGRAM1 field.
1: Blocks writes to MSGxTEST.TEST_CPUTOCM_MSGRAM1 field.
Reset type: SYSRSn
8 CPUTOCM_MSGRAM0 R/W 0h 0: Allows writes to MSGxTEST.TEST_CPUTOCM_MSGRAM0 field.
1: Blocks writes to MSGxTEST.TEST_CPUTOCM_MSGRAM0 field.
Reset type: SYSRSn
7 CPUTOCPU_MSGRAM1 R/W 0h 0: Allows writes to MSGxTEST.TEST_CPUTOCPU_MSGRAM1 field.
1: Blocks writes to MSGxTEST.TEST_CPUTOCPU_MSGRAM1 field.
Reset type: SYSRSn
6 DMATOCLA1 R/W 0h 0: Allows writes to MSGxTEST.TEST_DMATOCLA1 field.
1: Blocks writes to MSGxTEST.TEST_DMATOCLA1 field.
Reset type: SYSRSn
5 CLA1TODMA R/W 0h 0: Allows writes to MSGxTEST.TEST_CLA1TODMA field.
1: Blocks writes to MSGxTEST.TEST_CLA1TODMA field.
Reset type: SYSRSn
4 CLA2TOCPU R/W 0h 0: Allows writes to MSGxTEST.TEST_CLA2TOCPU field.
1: Blocks writes to MSGxTEST.TEST_CLA2TOCPU field.
Reset type: SYSRSn

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Table 3-286. MSGxRAMTEST_LOCK Register Field Descriptions (continued)

Bit Field Type Reset Description
3 CPUTOCLA2 R/W 0h 0: Allows writes to MSGxTEST.TEST_CPUTOCLA2 field.
1: Blocks writes to MSGxTEST.TEST_CPUTOCLA2 field.
Reset type: SYSRSn
2 CLA1TOCPU R/W 0h 0: Allows writes to MSGxTEST.TEST_CLA1TOCPU field.
1: Blocks writes to MSGxTEST.TEST_CLA1TOCPU field.
Reset type: SYSRSn
1 CPUTOCLA1 R/W 0h 0: Allows writes to MSGxTEST.TEST_CPUTOCLA1 field.
1: Blocks writes to MSGxTEST.TEST_CPUTOCLA1 field.
Reset type: SYSRSn
0 CPUTOCPU_MSGRAM0 R/W 0h 0: Allows writes to MSGxTEST.TEST_CPUTOCPU_MSGRAM0 field.
1: Blocks writes to MSGxTEST.TEST_CPUTOCPU_MSGRAM0 field.
Reset type: SYSRSn

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3.16.11.38 ROM_LOCK Register (Offset = A0h) [Reset = 0h]

ROM_LOCK is shown in Figure 3-271 and described in Table 3-287.
Return to the Summary Table.
ROM Config Lock Register
Figure 3-271. ROM_LOCK Register
31 30 29 28 27 26 25 24
KEY
R-0/W-0h

23 22 21 20 19 18 17 16
KEY
R-0/W-0h

15 14 13 12 11 10 9 8
RESERVED
R-0h

7 6 5 4 3 2 1 0
RESERVED LOCK_CLADAT LOCK_SECUR LOCK_BOOTR
AROM EROM OM
R-0h R/W-0h R/W-0h R/W-0h

Table 3-287. ROM_LOCK Register Field Descriptions

Bit Field Type Reset Description
31-16 KEY R-0/W 0h A value of 0xa5a5 to this field is simultaneously required for the
writes to the rest of the fields of this register to succeed,
Reset type: SYSRSn
15-3 RESERVED R 0h Reserved
2 LOCK_CLADATAROM R/W 0h Locks write access to test control fields (TEST and
FORCE_ERROR) of CLADATAROM
0: Write access allowed
1: Write access blocked
Reset type: SYSRSn
1 LOCK_SECUREROM R/W 0h Locks write access to test control fields (TEST and
FORCE_ERROR) of SECUREROM
0: Write access allowed
1: Write access blocked
Reset type: SYSRSn
0 LOCK_BOOTROM R/W 0h Locks write access to test control fields (TEST and
FORCE_ERROR) of BOOTROM
0: Write access allowed
1: Write access blocked
Reset type: SYSRSn

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3.16.11.39 ROM_TEST Register (Offset = A2h) [Reset = 0h]

ROM_TEST is shown in Figure 3-272 and described in Table 3-288.
Return to the Summary Table.
ROM TEST Register
Figure 3-272. ROM_TEST Register
31 30 29 28 27 26 25 24
RESERVED
R-0h

23 22 21 20 19 18 17 16
RESERVED
R-0h

15 14 13 12 11 10 9 8
RESERVED
R-0h

7 6 5 4 3 2 1 0
RESERVED TEST_CLADATAROM TEST_SECUREROM TEST_BOOTROM
R-0h R/W-0h R/W-0h R/W-0h

Table 3-288. ROM_TEST Register Field Descriptions

Bit Field Type Reset Description
31-6 RESERVED R 0h Reserved
5-4 TEST_CLADATAROM R/W 0h Selects the different modes for CLADATAROM:
00: Functional Mode.
01: same as "00" but Parity check on data read is disabled (for
debug)
10: Parity Bits are visible on memory map (for debug)
11: Same as "00" but NMI is not generated on errors, used for
diagnostics. (for diagnostics)
Reset type: SYSRSn
3-2 TEST_SECUREROM R/W 0h Selects the different modes for SECUREROM:
00: Functional Mode.
01: same as "00" but Parity check on data read is disabled (for
debug)
10: Parity Bits are visible on memory map (for debug)
11: Same as "00" but NMI is not generated on errors, used for
diagnostics. (for diagnostics)
Reset type: SYSRSn
1-0 TEST_BOOTROM R/W 0h Selects the different modes for BOOTROM:
00: Functional Mode.
01: same as "00" but Parity check on data read is disabled (for
debug)
10: Parity Bits are visible on memory map (for debug)
11: Same as "00" but NMI is not generated on errors, used for
diagnostics. (for diagnostics)
Reset type: SYSRSn

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3.16.11.40 ROM_FORCE_ERROR Register (Offset = A4h) [Reset = 0h]

ROM_FORCE_ERROR is shown in Figure 3-273 and described in Table 3-289.
Return to the Summary Table.
ROM Force Error register
Figure 3-273. ROM_FORCE_ERROR Register
31 30 29 28 27 26 25 24
RESERVED
R-0h

23 22 21 20 19 18 17 16
RESERVED
R-0h

15 14 13 12 11 10 9 8
RESERVED
R-0h

7 6 5 4 3 2 1 0
RESERVED FORCE_CLAD FORCE_SECU FORCE_BOOT
ATAROM_ERR REROM_ERRO ROM_ERROR
OR R
R-0h R/W-0h R/W-0h R/W-0h

Table 3-289. ROM_FORCE_ERROR Register Field Descriptions

Bit Field Type Reset Description
31-16 RESERVED R 0h Reserved
15-3 RESERVED R 0h Reserved
2 FORCE_CLADATAROM_ R/W 0h Force parity error by feeding inverted Parity bit to Parity checking
ERROR logic.
Reset type: SYSRSn
1 FORCE_SECUREROM_E R/W 0h Force parity error by feeding inverted Parity bit to Parity checking
RROR logic.
Reset type: SYSRSn
0 FORCE_BOOTROM_ERR R/W 0h Force parity error by feeding inverted Parity bit to Parity checking
OR logic.
Reset type: SYSRSn

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3.16.11.41 PERI_MEM_TEST_LOCK Register (Offset = AAh) [Reset = 0h]

PERI_MEM_TEST_LOCK is shown in Figure 3-274 and described in Table 3-290.
Return to the Summary Table.
Peripheral Memory Test Lock Register
Figure 3-274. PERI_MEM_TEST_LOCK Register
31 30 29 28 27 26 25 24
KEY
R-0/W-0h

23 22 21 20 19 18 17 16
KEY
R-0/W-0h

15 14 13 12 11 10 9 8
RESERVED
R-0h

7 6 5 4 3 2 1 0
RESERVED LOCK_PERI_M
EM_TEST_CO
NTROL
R-0h R/W-0h

Table 3-290. PERI_MEM_TEST_LOCK Register Field Descriptions

Bit Field Type Reset Description
31-16 KEY R-0/W 0h A value of 0xa5a5 to this field is simultaneously required for the
writes to the rest of the fields of this register to succeed,
Reset type: SYSRSn
15-1 RESERVED R 0h Reserved
0 LOCK_PERI_MEM_TEST R/W 0h Locks write access to register PERI_MEM_TEST_CONTROL
_CONTROL 0: Write access allowed
1: Write access blocked
Reset type: SYSRSn

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3.16.11.42 PERI_MEM_TEST_CONTROL Register (Offset = ACh) [Reset = 0h]

PERI_MEM_TEST_CONTROL is shown in Figure 3-275 and described in Table 3-291.
Return to the Summary Table.
Peripheral Memory Test control Register
Figure 3-275. PERI_MEM_TEST_CONTROL Register
31 30 29 28 27 26 25 24
RESERVED
R-0h

23 22 21 20 19 18 17 16
RESERVED
R-0h

15 14 13 12 11 10 9 8
RESERVED
R-0h

7 6 5 4 3 2 1 0
RESERVED EtherCAT_MEM EtherCAT_TES RESERVED RESERVED RESERVED RESERVED
_FORCE_ERR T_ENABLE
OR
R-0h R/W-0h R/W-0h R-0h R-0h R-0h R-0h

Table 3-291. PERI_MEM_TEST_CONTROL Register Field Descriptions

Bit Field Type Reset Description
31-6 RESERVED R 0h Reserved
5 EtherCAT_MEM_FORCE_ R/W 0h Force error bit
ERROR 0 : No effect
1 : Parity bit going to Parity checker module of EtherCAT is inverted
to introduce parity Error
Reset type: SYSRSn
4 EtherCAT_TEST_ENABL R/W 0h Selects EtherCAT test mode
E 0 : EtherCAT test mode disabled, Error on EtherCAT memory read
access will generate NMI
1 : EtherCAT test mode enabled, Error on EtherCAT memory read
access will NOT generate NMI, used for diagnostics
Reset type: SYSRSn
3 RESERVED R 0h Reserved
2 RESERVED R 0h Reserved
1 RESERVED R 0h Reserved
0 RESERVED R 0h Reserved

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3.16.12 MEMORY_ERROR_REGS Registers

Table 3-292 lists the memory-mapped registers for the MEMORY_ERROR_REGS registers. All register offset
addresses not listed in Table 3-292 should be considered as reserved locations and the register contents should
not be modified.
Table 3-292. MEMORY_ERROR_REGS Registers
Offset Acronym Register Name Write Protection Section
0h UCERRFLG Uncorrectable Error Flag Register Go
2h UCERRSET Uncorrectable Error Flag Set Register EALLOW Go
4h UCERRCLR Uncorrectable Error Flag Clear Register EALLOW Go
6h UCCPUREADDR Uncorrectable CPU Read Error Address Go
8h UCDMAREADDR Uncorrectable DMA Read Error Address Go
Ah UCCLA1READDR Uncorrectable CLA1 Read Error Address Go
Eh UCECATRAMADDR Uncorrectable etherCAT RAM Read Error Go
Address
20h CERRFLG Correctable Error Flag Register Go
22h CERRSET Correctable Error Flag Set Register EALLOW Go
24h CERRCLR Correctable Error Flag Clear Register EALLOW Go
26h CCPUREADDR Correctable CPU Read Error Address Go
2Ah CCLA1READDR Correctable CLA1 Read Error Address Go
2Eh CERRCNT Correctable Error Count Register Go
30h CERRTHRES Correctable Error Threshold Value Register EALLOW Go
32h CEINTFLG Correctable Error Interrupt Flag Status Register Go
34h CEINTCLR Correctable Error Interrupt Flag Clear Register EALLOW Go
36h CEINTSET Correctable Error Interrupt Flag Set Register EALLOW Go
38h CEINTEN Correctable Error Interrupt Enable Register EALLOW Go

Complex bit access types are encoded to fit into small table cells. Table 3-293 shows the codes that are used for
access types in this section.
Table 3-293. MEMORY_ERROR_REGS Access Type
Codes
Access Type Code Description
Read Type
R R Read
R-0 R Read
-0 Returns 0s
Write Type
W W Write
W1S W Write
1S 1 to set
Reset or Default Value
-n Value after reset or the default
value
Register Array Variables

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Table 3-293. MEMORY_ERROR_REGS Access Type

Codes (continued)
Access Type Code Description
i,j,k,l,m,n When these variables are used in
a register name, an offset, or an
address, they refer to the value of
a register array where the register
is part of a group of repeating
registers. The register groups
form a hierarchical structure and
the array is represented with a
formula.
y When this variable is used in a
register name, an offset, or an
address it refers to the value of
a register array.

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3.16.12.1 UCERRFLG Register (Offset = 0h) [Reset = 0h]

UCERRFLG is shown in Figure 3-276 and described in Table 3-294.
Return to the Summary Table.
Uncorrectable Error Flag Register
Figure 3-276. UCERRFLG Register
31 30 29 28 27 26 25 24
RESERVED
R-0h

23 22 21 20 19 18 17 16
RESERVED
R-0h

15 14 13 12 11 10 9 8
RESERVED
R-0h

7 6 5 4 3 2 1 0
RESERVED ECATRAMRDE RESERVED CLA1RDERR DMARDERR CPURDERR
RR
R-0h R-0h R-0h R-0h R-0h R-0h

Table 3-294. UCERRFLG Register Field Descriptions

Bit Field Type Reset Description
31-16 RESERVED R 0h Reserved
15-5 RESERVED R 0h Reserved
4 ECATRAMRDERR R 0h ECAT RAM Read Error Flag
0: No Error.
1: Uncorrectable error occurred on etherCAT RAM.
Reset type: SYSRSn
3 RESERVED R 0h Reserved
2 CLA1RDERR R 0h CLA1 Uncorrectable Read Error Flag
0: No Error.
1: Uncorrectable error occurred during CLA1 read.
Reset type: SYSRSn
1 DMARDERR R 0h DMA Uncorrectable Read Error Flag
0: No Error.
1: Uncorrectable error occurred during DMA read.
Reset type: SYSRSn
0 CPURDERR R 0h CPU Uncorrectable Read Error Flag
0: No Error.
1: Uncorrectable error occurred during CPU read.
Reset type: SYSRSn

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3.16.12.2 UCERRSET Register (Offset = 2h) [Reset = 0h]

UCERRSET is shown in Figure 3-277 and described in Table 3-295.
Return to the Summary Table.
Uncorrectable Error Flag Set Register
Figure 3-277. UCERRSET Register
31 30 29 28 27 26 25 24
RESERVED
R-0h

23 22 21 20 19 18 17 16
RESERVED
R-0h

15 14 13 12 11 10 9 8
RESERVED
R-0h

7 6 5 4 3 2 1 0
RESERVED ECATRAMRDE RESERVED CLA1RDERR DMARDERR CPURDERR
RR
R-0h R-0/W1S-0h R-0/W1S-0h R-0/W1S-0h R-0/W1S-0h R-0/W1S-0h

Table 3-295. UCERRSET Register Field Descriptions

Bit Field Type Reset Description
31-16 RESERVED R 0h Reserved
15-5 RESERVED R 0h Reserved
4 ECATRAMRDERR R-0/W1S 0h ECAT RAM Read Error Flag
0: No Action.
1: ECATRAMRDERR Flag in UCERRFLG register will be set and
interrupt will be generated if enabled.
Reset type: SYSRSn
3 RESERVED R-0/W1S 0h Reserved
2 CLA1RDERR R-0/W1S 0h 0: No action.
1: CLA1 Read Error Flag in UCERRFLG register will be set and
interrupt will be generated if enabled..
Reset type: SYSRSn
1 DMARDERR R-0/W1S 0h 0: No action.
1: DMA Read Error Flag in UCERRFLG register will be set and
interrupt will be generated if enabled..
Reset type: SYSRSn
0 CPURDERR R-0/W1S 0h 0: No action.
1: CPU Read Error Flag in UCERRFLG register will be set and
interrupt will be generated if enabled..
Reset type: SYSRSn

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3.16.12.3 UCERRCLR Register (Offset = 4h) [Reset = 0h]

UCERRCLR is shown in Figure 3-278 and described in Table 3-296.
Return to the Summary Table.
Uncorrectable Error Flag Clear Register
Figure 3-278. UCERRCLR Register
31 30 29 28 27 26 25 24
RESERVED
R-0h

23 22 21 20 19 18 17 16
RESERVED
R-0h

15 14 13 12 11 10 9 8
RESERVED
R-0h

7 6 5 4 3 2 1 0
RESERVED ECATRAMRDE RESERVED CLA1RDERR DMARDERR CPURDERR
RR
R-0h R-0/W1S-0h R-0/W1S-0h R-0/W1S-0h R-0/W1S-0h R-0/W1S-0h

Table 3-296. UCERRCLR Register Field Descriptions

Bit Field Type Reset Description
31-16 RESERVED R 0h Reserved
15-5 RESERVED R 0h Reserved
4 ECATRAMRDERR R-0/W1S 0h ECAT RAM Read Error Flag
0: No action.
1: ECATRAMRDERR Flag in UCERRFLG register will be cleared.
Reset type: SYSRSn
3 RESERVED R-0/W1S 0h Reserved
2 CLA1RDERR R-0/W1S 0h 0: No action.
1: CLA1 Read Error Flag in UCERRFLG register will be cleared.
Reset type: SYSRSn
1 DMARDERR R-0/W1S 0h 0: No action.
1: DMA Read Error Flag in UCERRFLG register will be cleared .
Reset type: SYSRSn
0 CPURDERR R-0/W1S 0h 0: No action.
1: CPU Read Error Flag in UCERRFLG register will be cleared.
Reset type: SYSRSn

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3.16.12.4 UCCPUREADDR Register (Offset = 6h) [Reset = 0h]

UCCPUREADDR is shown in Figure 3-279 and described in Table 3-297.
Return to the Summary Table.
Uncorrectable CPU Read Error Address
Figure 3-279. UCCPUREADDR Register
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
UCCPUREADDR
R-0h

Table 3-297. UCCPUREADDR Register Field Descriptions

Bit Field Type Reset Description
31-0 UCCPUREADDR R 0h This register captures the address location for which CPU read/fetch
access resulted in uncorrectable ECC/Parity error.
Reset type: SYSRSn

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3.16.12.5 UCDMAREADDR Register (Offset = 8h) [Reset = 0h]

UCDMAREADDR is shown in Figure 3-280 and described in Table 3-298.
Return to the Summary Table.
Uncorrectable DMA Read Error Address
Figure 3-280. UCDMAREADDR Register
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
UCDMAREADDR
R-0h

Table 3-298. UCDMAREADDR Register Field Descriptions

Bit Field Type Reset Description
31-0 UCDMAREADDR R 0h This register captures the address location for which DMA read
access resulted in uncorrectable Parity error.
Reset type: SYSRSn

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3.16.12.6 UCCLA1READDR Register (Offset = Ah) [Reset = 0h]

UCCLA1READDR is shown in Figure 3-281 and described in Table 3-299.
Return to the Summary Table.
Uncorrectable CLA1 Read Error Address
Figure 3-281. UCCLA1READDR Register
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
UCCLA1READDR
R-0h

Table 3-299. UCCLA1READDR Register Field Descriptions

Bit Field Type Reset Description
31-0 UCCLA1READDR R 0h This register captures the address location for which CLA1 read/
fetch access resulted in uncorrectable Parity error.
Reset type: SYSRSn

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3.16.12.7 UCECATRAMADDR Register (Offset = Eh) [Reset = 0h]

UCECATRAMADDR is shown in Figure 3-282 and described in Table 3-300.
Return to the Summary Table.
Uncorrectable etherCAT RAM Read Error Address
Figure 3-282. UCECATRAMADDR Register
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
UCECATRAMADDR
R-0h

Table 3-300. UCECATRAMADDR Register Field Descriptions

Bit Field Type Reset Description
31-0 UCECATRAMADDR R 0h This register captures the address offset of the etherCAT RAM
location for which read access (access could be from etherCAT
master or from CPU/DMA) resulted in uncorrectable Parity error.
Reset type: SYSRSn

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3.16.12.8 CERRFLG Register (Offset = 20h) [Reset = 0h]

CERRFLG is shown in Figure 3-283 and described in Table 3-301.
Return to the Summary Table.
Correctable Error Flag Register
Figure 3-283. CERRFLG Register
31 30 29 28 27 26 25 24
RESERVED
R-0h

23 22 21 20 19 18 17 16
RESERVED
R-0h

15 14 13 12 11 10 9 8
RESERVED
R-0h

7 6 5 4 3 2 1 0
RESERVED RESERVED CLA1RDERR DMARDERR CPURDERR
R-0h R-0h R-0h R-0h R-0h

Table 3-301. CERRFLG Register Field Descriptions

Bit Field Type Reset Description
31-16 RESERVED R 0h Reserved
15-4 RESERVED R 0h Reserved
3 RESERVED R 0h Reserved
2 CLA1RDERR R 0h CLA1 Correctable Read Error Flag
0: No Error.
1: Correctable error occurred during CLA1 read.
Reset type: SYSRSn
1 DMARDERR R 0h DMA Correctable Read Error Flag
0: No Error.
1: Correctable error occurred during DMA read.
Reset type: SYSRSn
0 CPURDERR R 0h CPU Correctable Read Error Flag
0: No Error.
1: Correctable error occurred during CPU read.
Reset type: SYSRSn

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3.16.12.9 CERRSET Register (Offset = 22h) [Reset = 0h]

CERRSET is shown in Figure 3-284 and described in Table 3-302.
Return to the Summary Table.
Correctable Error Flag Set Register
Figure 3-284. CERRSET Register
31 30 29 28 27 26 25 24
RESERVED
R-0h

23 22 21 20 19 18 17 16
RESERVED
R-0h

15 14 13 12 11 10 9 8
RESERVED
R-0h

7 6 5 4 3 2 1 0
RESERVED RESERVED CLA1RDERR DMARDERR CPURDERR
R-0h R-0/W1S-0h R-0/W1S-0h R-0/W1S-0h R-0/W1S-0h

Table 3-302. CERRSET Register Field Descriptions

Bit Field Type Reset Description
31-16 RESERVED R 0h Reserved
15-4 RESERVED R 0h Reserved
3 RESERVED R-0/W1S 0h Reserved
2 CLA1RDERR R-0/W1S 0h 0: No action.
1: CLA1 Read Error Flag in CERRFLG register will be set and
interrupt will be generated if enabled..
Reset type: SYSRSn
1 DMARDERR R-0/W1S 0h 0: No action.
1: DMA Read Error Flag in CERRFLG register will be set and
interrupt will be generated if enabled..
Reset type: SYSRSn
0 CPURDERR R-0/W1S 0h 0: No action.
1: CPU Read Error Flag in CERRFLG register will be set and
interrupt will be generated if enabled..
Reset type: SYSRSn

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3.16.12.10 CERRCLR Register (Offset = 24h) [Reset = 0h]

CERRCLR is shown in Figure 3-285 and described in Table 3-303.
Return to the Summary Table.
Correctable Error Flag Clear Register
Figure 3-285. CERRCLR Register
31 30 29 28 27 26 25 24
RESERVED
R-0h

23 22 21 20 19 18 17 16
RESERVED
R-0h

15 14 13 12 11 10 9 8
RESERVED
R-0h

7 6 5 4 3 2 1 0
RESERVED RESERVED CLA1RDERR DMARDERR CPURDERR
R-0h R-0/W1S-0h R-0/W1S-0h R-0/W1S-0h R-0/W1S-0h

Table 3-303. CERRCLR Register Field Descriptions

Bit Field Type Reset Description
31-16 RESERVED R 0h Reserved
15-4 RESERVED R 0h Reserved
3 RESERVED R-0/W1S 0h Reserved
2 CLA1RDERR R-0/W1S 0h 0: No action.
1: CLA1 Read Error Flag in CERRFLG register will be cleared.
Reset type: SYSRSn
1 DMARDERR R-0/W1S 0h 0: No action.
1: DMA Read Error Flag in CERRFLG register will be cleared .
Reset type: SYSRSn
0 CPURDERR R-0/W1S 0h 0: No action.
1: CPU Read Error Flag in CERRFLG register will be cleared.
Reset type: SYSRSn

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3.16.12.11 CCPUREADDR Register (Offset = 26h) [Reset = 0h]

CCPUREADDR is shown in Figure 3-286 and described in Table 3-304.
Return to the Summary Table.
Correctable CPU Read Error Address
Figure 3-286. CCPUREADDR Register
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CCPUREADDR
R-0h

Table 3-304. CCPUREADDR Register Field Descriptions

Bit Field Type Reset Description
31-0 CCPUREADDR R 0h This register captures the address location for which CPU read/fetch
access resulted in correctable ECC error.
Reset type: SYSRSn

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3.16.12.12 CCLA1READDR Register (Offset = 2Ah) [Reset = 0h]

CCLA1READDR is shown in Figure 3-287 and described in Table 3-305.
Return to the Summary Table.
Correctable CLA1 Read Error Address
Figure 3-287. CCLA1READDR Register
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CCLA1READDR
R-0h

Table 3-305. CCLA1READDR Register Field Descriptions

Bit Field Type Reset Description
31-0 CCLA1READDR R 0h This register captures the address location for which CLA1 read/
fetch access resulted in correctable ECC error.
Reset type: SYSRSn

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3.16.12.13 CERRCNT Register (Offset = 2Eh) [Reset = 0h]

CERRCNT is shown in Figure 3-288 and described in Table 3-306.
Return to the Summary Table.
Correctable Error Count Register
Figure 3-288. CERRCNT Register
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RESERVED CERRCNT
R-0h R/W-0h

Table 3-306. CERRCNT Register Field Descriptions

Bit Field Type Reset Description
31-16 RESERVED R 0h Reserved
15-0 CERRCNT R/W 0h This register holds the count of how many times correctable error
occurred.
Reset type: SYSRSn

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3.16.12.14 CERRTHRES Register (Offset = 30h) [Reset = 0h]

CERRTHRES is shown in Figure 3-289 and described in Table 3-307.
Return to the Summary Table.
Correctable Error Threshold Value Register
Figure 3-289. CERRTHRES Register
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RESERVED CERRTHRES
R-0h R/W-0h

Table 3-307. CERRTHRES Register Field Descriptions

Bit Field Type Reset Description
31-16 RESERVED R 0h Reserved
15-0 CERRTHRES R/W 0h When value in CERRCNT register is greater than value configured in
this register, corretable interrupt gets generated, if enabled.
Reset type: SYSRSn

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3.16.12.15 CEINTFLG Register (Offset = 32h) [Reset = 0h]

CEINTFLG is shown in Figure 3-290 and described in Table 3-308.
Return to the Summary Table.
Correctable Error Interrupt Flag Status Register
Figure 3-290. CEINTFLG Register
31 30 29 28 27 26 25 24
RESERVED
R-0h

23 22 21 20 19 18 17 16
RESERVED
R-0h

15 14 13 12 11 10 9 8
RESERVED
R-0h

7 6 5 4 3 2 1 0
RESERVED CEINTFLAG
R-0h R-0h

Table 3-308. CEINTFLG Register Field Descriptions

Bit Field Type Reset Description
31-16 RESERVED R 0h Reserved
15-1 RESERVED R 0h Reserved
0 CEINTFLAG R 0h Total corrected error count exceeded threshold Flag
0: Total correctable errors < Threshold value configured in
CERRTHRES register.
1: Total correctable errors >= Threshold value configured in
CERRTHRES register.
Reset type: SYSRSn

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3.16.12.16 CEINTCLR Register (Offset = 34h) [Reset = 0h]

CEINTCLR is shown in Figure 3-291 and described in Table 3-309.
Return to the Summary Table.
Correctable Error Interrupt Flag Clear Register
Figure 3-291. CEINTCLR Register
31 30 29 28 27 26 25 24
RESERVED
R-0h

23 22 21 20 19 18 17 16
RESERVED
R-0h

15 14 13 12 11 10 9 8
RESERVED
R-0h

7 6 5 4 3 2 1 0
RESERVED CEINTCLR
R-0h R-0/W1S-0h

Table 3-309. CEINTCLR Register Field Descriptions

Bit Field Type Reset Description
31-16 RESERVED R 0h Reserved
15-1 RESERVED R 0h Reserved
0 CEINTCLR R-0/W1S 0h 0: No action.
1: Total corrected error count exceeded flag in CEINTFLG register
will be cleared.
Reset type: SYSRSn

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3.16.12.17 CEINTSET Register (Offset = 36h) [Reset = 0h]

CEINTSET is shown in Figure 3-292 and described in Table 3-310.
Return to the Summary Table.
Correctable Error Interrupt Flag Set Register
Figure 3-292. CEINTSET Register
31 30 29 28 27 26 25 24
RESERVED
R-0h

23 22 21 20 19 18 17 16
RESERVED
R-0h

15 14 13 12 11 10 9 8
RESERVED
R-0h

7 6 5 4 3 2 1 0
RESERVED CEINTSET
R-0h R-0/W1S-0h

Table 3-310. CEINTSET Register Field Descriptions

Bit Field Type Reset Description
31-16 RESERVED R 0h Reserved
15-1 RESERVED R 0h Reserved
0 CEINTSET R-0/W1S 0h 0: No action.
1: Total corrected error count exceeded flag in CEINTFLG register
will be set and interrupt will be generated if enabled.
Reset type: SYSRSn

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3.16.12.18 CEINTEN Register (Offset = 38h) [Reset = 0h]

CEINTEN is shown in Figure 3-293 and described in Table 3-311.
Return to the Summary Table.
Correctable Error Interrupt Enable Register
Figure 3-293. CEINTEN Register
31 30 29 28 27 26 25 24
RESERVED
R-0h

23 22 21 20 19 18 17 16
RESERVED
R-0h

15 14 13 12 11 10 9 8
RESERVED
R-0h

7 6 5 4 3 2 1 0
RESERVED CEINTEN
R-0h R/W-0h

Table 3-311. CEINTEN Register Field Descriptions

Bit Field Type Reset Description
31-16 RESERVED R 0h Reserved
15-1 RESERVED R 0h Reserved
0 CEINTEN R/W 0h 0: Correctable Error Interrupt is disabled.
1: Correctable Error Interrupt is enabled.
Reset type: SYSRSn

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3.16.13 NMI_INTRUPT_REGS Registers

Table 3-312 lists the memory-mapped registers for the NMI_INTRUPT_REGS registers. All register offset
addresses not listed in Table 3-312 should be considered as reserved locations and the register contents should
not be modified.
Table 3-312. NMI_INTRUPT_REGS Registers
Offset Acronym Register Name Write Protection Section
0h NMICFG NMI Configuration Register EALLOW Go
1h NMIFLG NMI Flag Register (SYSRsn Clear) Go
2h NMIFLGCLR NMI Flag Clear Register EALLOW Go
3h NMIFLGFRC NMI Flag Force Register EALLOW Go
4h NMIWDCNT NMI Watchdog Counter Register Go
5h NMIWDPRD NMI Watchdog Period Register EALLOW Go
6h NMISHDFLG NMI Shadow Flag Register Go
7h ERRORSTS Error pin status Go
8h ERRORSTSCLR ERRORSTS clear register EALLOW Go
9h ERRORSTSFRC ERRORSTS force register EALLOW Go
Ah ERRORCTL Error pin control register EALLOW Go
Bh ERRORLOCK Lock register to Error pin registers. EALLOW Go

Complex bit access types are encoded to fit into small table cells. Table 3-313 shows the codes that are used for
access types in this section.
Table 3-313. NMI_INTRUPT_REGS Access Type
Codes
Access Type Code Description
Read Type
R R Read
R-0 R Read
-0 Returns 0s
Write Type
W W Write
W1S W Write
1S 1 to set
WSonce W Write
Sonce Set once
Reset or Default Value
-n Value after reset or the default
value
Register Array Variables
i,j,k,l,m,n When these variables are used in
a register name, an offset, or an
address, they refer to the value of
a register array where the register
is part of a group of repeating
registers. The register groups
form a hierarchical structure and
the array is represented with a
formula.
y When this variable is used in a
register name, an offset, or an
address it refers to the value of
a register array.

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3.16.13.1 NMICFG Register (Offset = 0h) [Reset = 0h]

NMICFG is shown in Figure 3-294 and described in Table 3-314.
Return to the Summary Table.
NMI Configuration Register
Figure 3-294. NMICFG Register
15 14 13 12 11 10 9 8
RESERVED
R-0-0h

7 6 5 4 3 2 1 0
RESERVED NMIE
R-0-0h R/W1S-0h

Table 3-314. NMICFG Register Field Descriptions

Bit Field Type Reset Description
15-1 RESERVED R-0 0h Reserved
0 NMIE R/W1S 0h When set to 1 any condition will generate an NMI interrupt to the
C28 CPU and kick off the NMI watchdog counter. As part of boot
sequence this bit should be set after the device security related
initialization is complete.
0 NMI disabled
1 NMI enabled
Reset type: SYSRSn

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3.16.13.2 NMIFLG Register (Offset = 1h) [Reset = 0h]

NMIFLG is shown in Figure 3-295 and described in Table 3-315.
Return to the Summary Table.
NMI Flag Register (SYSRsn Clear)
Figure 3-295. NMIFLG Register
15 14 13 12 11 10 9 8
MCAN_ERR CRC_FAIL ECATNMIn CMNMIWDRSn RESERVED CPU2NMIWDR CPU2WDRSn CLBNMI
Sn
R-0h R-0h R-0h R-0h R-0h R-0h R-0h R-0h

7 6 5 4 3 2 1 0
ERADNMI PIEVECTERR CPU2HWBISTE CPU1HWBISTE FLUNCERR RAMUNCERR CLOCKFAIL NMIINT
RR RR
R-0h R-0h R-0h R-0h R-0h R-0h R-0h R-0h

Table 3-315. NMIFLG Register Field Descriptions

Bit Field Type Reset Description
15 MCAN_ERR R 0h 0 MCAN module has not generated an ECC error.
1 MCAN module has generated an ECC error.
[1] This bit is reserved for CPU2.NMIFLG register
Reset type: SYSRSn
14 CRC_FAIL R 0h 0 CPUCRC and CLACRC check has not failed.
1 CPUCRC or CLACRC check has failed.
Reset type: SYSRSn
13 ECATNMIn R 0h 0 No reset request from EtherCAT IP.
1 NMI generated from EtherCAT IP.
No further NMI pulses are generated until this flag is cleared by the
user.
[1] This bit is reserved for CPU2.NMIFLG register
Reset type: SYSRSn
12 CMNMIWDRSn R 0h CM NMIWDRSn Reset Indication Flag: This bit indicates if CM's
NMIWDRSn was fired or not.
0 No CM.NMIWDRsn was fired
1 CM.NMIWDRSn was fired to CM
[1] This bit is reserved for CPU2.NMIFLG register
Reset type: SYSRSn
11 RESERVED R 0h Reserved
10 CPU2NMIWDRSn R 0h CPU2 NMIWDRSn Reset Indication Flag: This bit indicates if CPU2's
NMIWDRSn was fired or not.
0 No CPU2.NMIWDRsn was fired
1 CPU2.NMIWDRSn was fired to CPU2
Note:
[1] This bit is reserved for CPU2.NMIFLG register
Reset type: SYSRSn
9 CPU2WDRSn R 0h CPU2 WDRSn Reset Indication Flag: This bit indicates if CPU2's
WDRSn was fired or not.
0 No CPU2.WDRsn was fired
1 CPU2.WDRSn was fired to CPU2
Note:
[1] This bit is reserved for CPU2.NMIFLG register
Reset type: SYSRSn
8 CLBNMI R 0h Configurable Logic Block NMI Flag: This bit indicates if an NMI
was generated by the Configurable Logic Block. This bit can only
be cleared by the user writing to the corresponding clear bit in the
NMIFLGCLR register or by an SYSRSn reset:
0,No Configurable Logic Block NMI pending
1,Configurable Logic Block NMI generated
Reset type: SYSRSn

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Table 3-315. NMIFLG Register Field Descriptions (continued)

Bit Field Type Reset Description
7 ERADNMI R 0h ERAD Module NMI Flag: This bit indicates if an NMI was generated
by the ERAD Module. This bit can only be cleared by the user writing
to the corresponding clear bit in the NMIFLGCLR register or by an
SYSRSn reset:
0,No ERAD NMI pending
1,ERAD NMI generated
Reset type: SYSRSn
6 PIEVECTERR R 0h PIE Vector Fetch Error Flag: This bit indicates if an error occurred on
an Vector Fecth by the CPU in the device.
In Dual core system CPU1.NMIWD gets an NMI on an Vector fetch
Error on CPU2. This bit can only be cleared by the user writing
to the corresponding clear bit in the NMIFLGCLR register or by an
SYSRSn reset:
0,No Vector Fetch Error condition (on the other CPU) pending
1,Vector Fetch error condition (on the other CPU) generated
Reset type: SYSRSn
5 CPU2HWBISTERR R 0h HW BIST Error NMI Flag: This bit indicates if the time out error or
a signature mismatch error condition during hardware BIST of C28
CPU2 occurred. This bit can only be cleared by the user writing
to the corresponding clear bit in the NMIFLGCLR register or by an
SYSRSn reset:
0,No C28 HWBIST error condition pending
1,C28 BIST error condition generated
Reset type: SYSRSn
4 CPU1HWBISTERR R 0h HW BIST Error NMI Flag: This bit indicates if the time out error or
a signature mismatch error condition during hardware BIST of C28
CPU1 occurred. This bit can only be cleared by the user writing
to the corresponding clear bit in the NMIFLGCLR register or by an
SYSRSn reset:
0,No C28 HWBIST error condition pending
1,C28 BIST error condition generated
Reset type: SYSRSn
3 FLUNCERR R 0h Flash Uncorrectable Error NMI Flag: This bit indicates if an
uncorrectable error occurred on a C28 Flash access and that
condition is latched. This bit can only be cleared by the user writing
to the corresponding clear bit in the NMIFLGCLR register or by an
SYSRSn reset:
0,No C28 Flash uncorrectable error condition pending
1,C28 Flash uncorrectable error condition generated
Reset type: SYSRSn
2 RAMUNCERR R 0h RAM Uncorrectable Error NMI Flag: This bit indicates if an
uncorrectable error occurred on a RAM access (by any master) and
that condition is latched. This bit can only be cleared by the user
writing to the corresponding clear bit in the NMIFLGCLR register or
by an SYSRSn reset:
0,No RAM uncorrectable error condition pending
1,RAM uncorrectable error condition generated
Note: This nmi is a combination of uncorrectable error in RAMs and
ROMs. ROM parity error would also set this flag.
Reset type: SYSRSn
1 CLOCKFAIL R 0h Clock Fail Interrupt Flag: These bits indicates if the CLOCKFAIL
condition is latched. These bits can only be cleared by the user
writing to the respective bit in the NMIFLGCLR register or by an
SYSRSn reset:
0,No CLOCKFAIL Condition Pending
1,CLOCKFAIL Condition Generated
Reset type: SYSRSn

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Table 3-315. NMIFLG Register Field Descriptions (continued)

Bit Field Type Reset Description
0 NMIINT R 0h NMI Interrupt Flag: This bit indicates if an NMI interrupt was
generated. This bit can only be cleared by the user writing to the
respective bit in the NMIFLGCLR register or by an SYSRSn reset:
0 No NMI Interrupt Generated
1 NMI Interrupt Generated
No further NMI interrupts pulses are generated until this flag is
cleared by the user.
Reset type: SYSRSn

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3.16.13.3 NMIFLGCLR Register (Offset = 2h) [Reset = 0h]

NMIFLGCLR is shown in Figure 3-296 and described in Table 3-316.
Return to the Summary Table.
NMI Flag Clear Register
Figure 3-296. NMIFLGCLR Register
15 14 13 12 11 10 9 8
MCAN_ERR CRC_FAIL ECATNMIn CMNMIWDRSn RESERVED CPU2NMIWDR CPU2WDRSn CLBNMI
Sn
R-0/W1S-0h R-0/W1S-0h R-0/W1S-0h R-0/W1S-0h R-0/W1S-0h R-0/W1S-0h R-0/W1S-0h R-0/W1S-0h

7 6 5 4 3 2 1 0
ERADNMI PIEVECTERR CPU2HWBISTE CPU1HWBISTE FLUNCERR RAMUNCERR CLOCKFAIL NMIINT
RR RR
R-0/W1S-0h R-0/W1S-0h R-0/W1S-0h R-0/W1S-0h R-0/W1S-0h R-0/W1S-0h R-0/W1S-0h R-0/W1S-0h

Table 3-316. NMIFLGCLR Register Field Descriptions

Bit Field Type Reset Description
15 MCAN_ERR R-0/W1S 0h Writing a 1 to the respective bit clears the corresponding flag bit in
the NMIFLG and NMISHDFLG registers. Writes of 0 are ignored.
Always reads back 0.
Notes:
[1] If hardware is trying to set a bit to 1 while software is trying to
clear a bit to 0 on the same cycle, hardware has priority.
[2] Users should clear the pending FAIL flag first and then clear the
NMIINT flag.
Reset type: SYSRSn
14 CRC_FAIL R-0/W1S 0h Writing a 1 to the respective bit clears the corresponding flag bit in
the NMIFLG and NMISHDFLG registers. Writes of 0 are ignored.
Always reads back 0.
Notes:
[1] If hardware is trying to set a bit to 1 while software is trying to
clear a bit to 0 on the same cycle, hardware has priority.
[2] Users should clear the pending FAIL flag first and then clear the
NMIINT flag.
Reset type: SYSRSn
13 ECATNMIn R-0/W1S 0h Writing a 1 to the respective bit clears the corresponding flag bit in
the NMIFLG and NMISHDFLG registers. Writes of 0 are ignored.
Always reads back 0.
Notes:
[1] If hardware is trying to set a bit to 1 while software is trying to
clear a bit to 0 on the same cycle, hardware has priority.
[2] Users should clear the pending FAIL flag first and then clear the
NMIINT flag.
[3] This bit is reserved for CPU2.NMIFLG register
Reset type: SYSRSn
12 CMNMIWDRSn R-0/W1S 0h Writing a 1 to the respective bit clears the corresponding flag bit in
the NMIFLG and NMISHDFLG registers. Writes of 0 are ignored.
Always reads back 0.
Notes:
[1] If hardware is trying to set a bit to 1 while software is trying to
clear a bit to 0 on the same cycle, hardware has priority.
[2] Users should clear the pending FAIL flag first and then clear the
NMIINT flag.
[3] This bit is reserved for CPU2.NMIFLG register
Reset type: SYSRSn
11 RESERVED R-0/W1S 0h Reserved

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Table 3-316. NMIFLGCLR Register Field Descriptions (continued)

Bit Field Type Reset Description
10 CPU2NMIWDRSn R-0/W1S 0h Writing a 1 to the respective bit clears the corresponding flag bit in
the NMIFLG and NMISHDFLG registers. Writes of 0 are ignored.
Always reads back 0.
Notes:
[1] If hardware is trying to set a bit to 1 while software is trying to
clear a bit to 0 on the same cycle, hardware has priority.
[2] Users should clear the pending FAIL flag first and then clear the
NMIINT flag.
Reset type: SYSRSn
9 CPU2WDRSn R-0/W1S 0h Writing a 1 to the respective bit clears the corresponding flag bit in
the NMIFLG and NMISHDFLG registers. Writes of 0 are ignored.
Always reads back 0.
Notes:
[1] If hardware is trying to set a bit to 1 while software is trying to
clear a bit to 0 on the same cycle, hardware has priority.
[2] Users should clear the pending FAIL flag first and then clear the
NMIINT flag.
[3] CPU2WDRSn and CPU2NMIWDRSn bits are reserved for
CPU2.NMIFLGCLR registers
Reset type: SYSRSn
8 CLBNMI R-0/W1S 0h Writing a 1 to the respective bit clears the corresponding flag bit in
the NMIFLG and NMISHDFLG registers. Writes of 0 are ignored.
Always reads back 0.
Notes:
[1] If hardware is trying to set a bit to 1 while software is trying to
clear a bit to 0 on the same cycle, hardware has priority.
[2] Users should clear the pending FAIL flag first and then clear the
NMIINT flag.
Reset type: SYSRSn
7 ERADNMI R-0/W1S 0h Writing a 1 to the respective bit clears the corresponding flag bit in
the NMIFLG and NMISHDFLG registers. Writes of 0 are ignored.
Always reads back 0.
Notes:
[1] If hardware is trying to set a bit to 1 while software is trying to
clear a bit to 0 on the same cycle, hardware has priority.
[2] Users should clear the pending FAIL flag first and then clear the
NMIINT flag.
Reset type: SYSRSn
6 PIEVECTERR R-0/W1S 0h Writing a 1 to the respective bit clears the corresponding flag bit in
the NMIFLG and NMISHDFLG registers. Writes of 0 are ignored.
Always reads back 0.
Notes:
[1] If hardware is trying to set a bit to 1 while software is trying to
clear a bit to 0 on the same cycle, hardware has priority.
[2] Users should clear the pending FAIL flag first and then clear the
NMIINT flag.
Reset type: SYSRSn
5 CPU2HWBISTERR R-0/W1S 0h Writing a 1 to the respective bit clears the corresponding flag bit in
the NMIFLG and NMISHDFLG registers. Writes of 0 are ignored.
Always reads back 0.
Notes:
[1] If hardware is trying to set a bit to 1 while software is trying to
clear a bit to 0 on the same cycle, hardware has priority.
[2] Users should clear the pending FAIL flag first and then clear the
NMIINT flag.
Reset type: SYSRSn

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Table 3-316. NMIFLGCLR Register Field Descriptions (continued)

Bit Field Type Reset Description
4 CPU1HWBISTERR R-0/W1S 0h Writing a 1 to the respective bit clears the corresponding flag bit in
the NMIFLG and NMISHDFLG registers. Writes of 0 are ignored.
Always reads back 0.
Notes:
[1] If hardware is trying to set a bit to 1 while software is trying to
clear a bit to 0 on the same cycle, hardware has priority.
[2] Users should clear the pending FAIL flag first and then clear the
NMIINT flag.
Reset type: SYSRSn
3 FLUNCERR R-0/W1S 0h Writing a 1 to the respective bit clears the corresponding flag bit in
the NMIFLG and NMISHDFLG registers. Writes of 0 are ignored.
Always reads back 0.
Notes:
[1] If hardware is trying to set a bit to 1 while software is trying to
clear a bit to 0 on the same cycle, hardware has priority.
[2] Users should clear the pending FAIL flag first and then clear the
NMIINT flag.
Reset type: SYSRSn
2 RAMUNCERR R-0/W1S 0h Writing a 1 to the respective bit clears the corresponding flag bit in
the NMIFLG and NMISHDFLG registers. Writes of 0 are ignored.
Always reads back 0.
Notes:
[1] If hardware is trying to set a bit to 1 while software is trying to
clear a bit to 0 on the same cycle, hardware has priority.
[2] Users should clear the pending FAIL flag first and then clear the
NMIINT flag.
Reset type: SYSRSn
1 CLOCKFAIL R-0/W1S 0h Writing a 1 to the respective bit clears the corresponding flag bit in
the NMIFLG and NMISHDFLG registers. Writes of 0 are ignored.
Always reads back 0.
Notes:
[1] If hardware is trying to set a bit to 1 while software is trying to
clear a bit to 0 on the same cycle, hardware has priority.
[2] Users should clear the pending FAIL flag first and then clear the
NMIINT flag.
Reset type: SYSRSn
0 NMIINT R-0/W1S 0h Writing a 1 to the respective bit clears the corresponding flag bit in
the NMIFLG and NMISHDFLG registers. Writes of 0 are ignored.
Always reads back 0.
Notes:
[1] If hardware is trying to set a bit to 1 while software is trying to
clear a bit to 0 on the same cycle, hardware has priority.
[2] Users should clear the pending FAIL flag first and then clear the
NMIINT flag.
Reset type: SYSRSn

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3.16.13.4 NMIFLGFRC Register (Offset = 3h) [Reset = 0h]

NMIFLGFRC is shown in Figure 3-297 and described in Table 3-317.
Return to the Summary Table.
NMI Flag Force Register
Figure 3-297. NMIFLGFRC Register
15 14 13 12 11 10 9 8
MCAN_ERR CRC_FAIL ECATNMIn CMNMIWDRSn RESERVED CPU2NMIWDR CPU2WDRSn CLBNMI
Sn
R-0/W1S-0h R-0/W1S-0h R-0/W1S-0h R-0/W1S-0h R-0/W1S-0h R-0/W1S-0h R-0/W1S-0h R-0/W1S-0h

7 6 5 4 3 2 1 0
ERADNMI PIEVECTERR CPU2HWBISTE CPU1HWBISTE FLUNCERR RAMUNCERR CLOCKFAIL RESERVED
RR RR
R-0/W1S-0h R-0/W1S-0h R-0/W1S-0h R-0/W1S-0h R-0/W1S-0h R-0/W1S-0h R-0/W1S-0h R-0-0h

Table 3-317. NMIFLGFRC Register Field Descriptions

Bit Field Type Reset Description
15 MCAN_ERR R-0/W1S 0h Writing a 1 to these bits will set the respective FAIL flag in the
NMIFLG and NMISHDFLG registers. Writes of 0 are ignored. Always
reads back 0. This can be used as a means to test the NMI
mechanisms.
[1] This bit is reserved for CPU2.NMIFLG register
Reset type: SYSRSn
14 CRC_FAIL R-0/W1S 0h Writing a 1 to these bits will set the respective FAIL flag in the
NMIFLG and NMISHDFLG registers. Writes of 0 are ignored. Always
reads back 0. This can be used as a means to test the NMI
mechanisms.
Reset type: SYSRSn
13 ECATNMIn R-0/W1S 0h Writing a 1 to these bits will set the respective FAIL flag in the
NMIFLG and NMISHDFLG registers. Writes of 0 are ignored. Always
reads back 0. This can be used as a means to test the NMI
mechanisms.
[1] This bit is reserved for CPU2.NMIFLG register
Reset type: SYSRSn
12 CMNMIWDRSn R-0/W1S 0h Writing a 1 to these bits will set the respective FAIL flag in the
NMIFLG and NMISHDFLG registers. Writes of 0 are ignored. Always
reads back 0. This can be used as a means to test the NMI
mechanisms.
[1] This bit is reserved for CPU2.NMIFLG register
Reset type: SYSRSn
11 RESERVED R-0/W1S 0h Reserved
10 CPU2NMIWDRSn R-0/W1S 0h Writing a 1 to these bits will set the respective FAIL flag in the
NMIFLG and NMISHDFLG registers. Writes of 0 are ignored. Always
reads back 0. This can be used as a means to test the NMI
mechanisms.
Note:
[1] CPU2WDRSn and CPU2NMIWDRSn bits are reserved for
CPU2.NMIFLGCLR registers
Reset type: SYSRSn
9 CPU2WDRSn R-0/W1S 0h Writing a 1 to these bits will set the respective FAIL flag in the
NMIFLG and NMISHDFLG registers. Writes of 0 are ignored. Always
reads back 0. This can be used as a means to test the NMI
mechanisms.
Note:
[1] CPU2WDRSn and CPU2NMIWDRSn bits are reserved for
CPU2.NMIFLGCLR registers
Reset type: SYSRSn

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Table 3-317. NMIFLGFRC Register Field Descriptions (continued)

Bit Field Type Reset Description
8 CLBNMI R-0/W1S 0h Writing a 1 to these bits will set the respective FAIL flag in the
NMIFLG and NMISHDFLG registers. Writes of 0 are ignored. Always
reads back 0. This can be used as a means to test the NMI
mechanisms.
Reset type: SYSRSn
7 ERADNMI R-0/W1S 0h Writing a 1 to these bits will set the respective FAIL flag in the
NMIFLG and NMISHDFLG registers. Writes of 0 are ignored. Always
reads back 0. This can be used as a means to test the NMI
mechanisms.
Reset type: SYSRSn
6 PIEVECTERR R-0/W1S 0h Writing a 1 to these bits will set the respective FAIL flag in the
NMIFLG and NMISHDFLG registers. Writes of 0 are ignored. Always
reads back 0. This can be used as a means to test the NMI
mechanisms.
Reset type: SYSRSn
5 CPU2HWBISTERR R-0/W1S 0h Writing a 1 to these bits will set the respective FAIL flag in the
NMIFLG and NMISHDFLG registers. Writes of 0 are ignored. Always
reads back 0. This can be used as a means to test the NMI
mechanisms.
Reset type: SYSRSn
4 CPU1HWBISTERR R-0/W1S 0h Writing a 1 to these bits will set the respective FAIL flag in the
NMIFLG and NMISHDFLG registers. Writes of 0 are ignored. Always
reads back 0. This can be used as a means to test the NMI
mechanisms.
Reset type: SYSRSn
3 FLUNCERR R-0/W1S 0h Writing a 1 to these bits will set the respective FAIL flag in the
NMIFLG and NMISHDFLG registers. Writes of 0 are ignored. Always
reads back 0. This can be used as a means to test the NMI
mechanisms.
Reset type: SYSRSn
2 RAMUNCERR R-0/W1S 0h Writing a 1 to these bits will set the respective FAIL flag in the
NMIFLG and NMISHDFLG registers. Writes of 0 are ignored. Always
reads back 0. This can be used as a means to test the NMI
mechanisms.
Reset type: SYSRSn
1 CLOCKFAIL R-0/W1S 0h Writing a 1 to these bits will set the respective FAIL flag in the
NMIFLG and NMISHDFLG registers. Writes of 0 are ignored. Always
reads back 0. This can be used as a means to test the NMI
mechanisms.
Reset type: SYSRSn
0 RESERVED R-0 0h Reserved

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3.16.13.5 NMIWDCNT Register (Offset = 4h) [Reset = 0h]

NMIWDCNT is shown in Figure 3-298 and described in Table 3-318.
Return to the Summary Table.
NMI Watchdog Counter Register
Figure 3-298. NMIWDCNT Register
15 14 13 12 11 10 9 8
NMIWDCNT
R-0h

7 6 5 4 3 2 1 0
NMIWDCNT
R-0h

Table 3-318. NMIWDCNT Register Field Descriptions

Bit Field Type Reset Description
15-0 NMIWDCNT R 0h NMI Watchdog Counter: This 16-bit incremental counter will start
incrementing whenever any one of the enabled FAIL flags are set.
If the counter reaches the period value, an NMIRSn signal is fired
which will then resets the system. The counter will reset to zero
when it reaches the period value and will then restart counting if any
of the enabled FAIL flags are set.
If no enabled FAIL flag is set, then the counter will reset to zero and
remain at zero until an enabled FAIL flag is set.
Normally, the software would respond to the NMI interrupt generated
and clear the offending FLAG(s) before the NMI watchdog triggers
a reset. In some situations, the software may decide to allow the
watchdog to reset the device anyway.
The counter is clocked at the SYSCLKOUT rate.
Reset type: SYSRSn

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3.16.13.6 NMIWDPRD Register (Offset = 5h) [Reset = FFFFh]

NMIWDPRD is shown in Figure 3-299 and described in Table 3-319.
Return to the Summary Table.
NMI Watchdog Period Register
Figure 3-299. NMIWDPRD Register
15 14 13 12 11 10 9 8
NMIWDPRD
R/W-FFFFh

7 6 5 4 3 2 1 0
NMIWDPRD
R/W-FFFFh

Table 3-319. NMIWDPRD Register Field Descriptions

Bit Field Type Reset Description
15-0 NMIWDPRD R/W FFFFh NMI Watchdog Period: This 16-bit value contains the period value at
which a reset is generated when the watchdog counter matches. At
reset this value is set at the maximum. The software can decrease
the period value at initialization time.
Reset type: SYSRSn

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3.16.13.7 NMISHDFLG Register (Offset = 6h) [Reset = 0h]

NMISHDFLG is shown in Figure 3-300 and described in Table 3-320.
Return to the Summary Table.
NMI Shadow Flag Register
Figure 3-300. NMISHDFLG Register
15 14 13 12 11 10 9 8
MCAN_ERR CRC_FAIL ECATNMIn CMNMIWDRSn RESERVED CPU2NMIWDR CPU2WDRSn CLBNMI
Sn
R-0h R-0h R-0h R-0h R-0h R-0h R-0h R-0h

7 6 5 4 3 2 1 0
ERADNMI PIEVECTERR CPU2HWBISTE CPU1HWBISTE FLUNCERR RAMUNCERR CLOCKFAIL RESERVED
RR RR
R-0h R-0h R-0h R-0h R-0h R-0h R-0h R-0-0h

Table 3-320. NMISHDFLG Register Field Descriptions

Bit Field Type Reset Description
15 MCAN_ERR R 0h Shadow NMI Flags: When an NMIFLG bit is set due to any of the
possible NMI source in the device, the corresponding bit in this
register is also set. Note that NMIFLGFRC and NMIFLGCLR register
also affects the bits of this register in the same way as they do for the
NMIFLG register. This register is reset only by PORESETn.
Notes:
[1] This register is added to keep the definition of System Control
Reset Cause Register Clean.
[2] This bit is reserved for CPU2.NMIFLG register
Reset type: SYSRSn
14 CRC_FAIL R 0h Shadow NMI Flags: When an NMIFLG bit is set due to any of the
possible NMI source in the device, the corresponding bit in this
register is also set. Note that NMIFLGFRC and NMIFLGCLR register
also affects the bits of this register in the same way as they do for the
NMIFLG register. This register is reset only by PORESETn.
Notes:
[1] This register is added to keep the definition of System Control
Reset Cause Register Clean.
Reset type: SYSRSn
13 ECATNMIn R 0h Shadow NMI Flags: When an NMIFLG bit is set due to any of the
possible NMI source in the device, the corresponding bit in this
register is also set. Note that NMIFLGFRC and NMIFLGCLR register
also affects the bits of this register in the same way as they do for the
NMIFLG register. This register is reset only by PORESETn.
Notes:
[1] This register is added to keep the definition of System Control
Reset Cause Register Clean.
[2] This bit is reserved for CPU2.NMIFLG register
Reset type: SYSRSn
12 CMNMIWDRSn R 0h Shadow NMI Flags: When an NMIFLG bit is set due to any of the
possible NMI source in the device, the corresponding bit in this
register is also set. Note that NMIFLGFRC and NMIFLGCLR register
also affects the bits of this register in the same way as they do for the
NMIFLG register. This register is reset only by PORESETn.
Notes:
[1] This register is added to keep the definition of System Control
Reset Cause Register Clean.
[2] This bit is reserved for CPU2.NMIFLG register
Reset type: PORESETn
11 RESERVED R 0h Reserved

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Table 3-320. NMISHDFLG Register Field Descriptions (continued)

Bit Field Type Reset Description
10 CPU2NMIWDRSn R 0h Shadow NMI Flags: When an NMIFLG bit is set due to any of the
possible NMI source in the device, the corresponding bit in this
register is also set. Note that NMIFLGFRC and NMIFLGCLR register
also affects the bits of this register in the same way as they do for the
NMIFLG register. This register is reset only by PORESETn.
Notes:
[1] This register is added to keep the definition of System Control
Reset Cause Register Clean.
Reset type: PORESETn
9 CPU2WDRSn R 0h Shadow NMI Flags: When an NMIFLG bit is set due to any of the
possible NMI source in the device, the corresponding bit in this
register is also set. Note that NMIFLGFRC and NMIFLGCLR register
also affects the bits of this register in the same way as they do for the
NMIFLG register. This register is reset only by PORESETn.
Notes:
[1] This register is added to keep the definition of System Control
Reset Cause Register Clean.
[2] CPU2WDRSn and CPU2NMIWDRSn bits are reserved for
CPU2.NMIFLGCLR registers
Reset type: PORESETn
8 CLBNMI R 0h Shadow NMI Flags: When an NMIFLG bit is set due to any of the
possible NMI source in the device, the corresponding bit in this
register is also set. Note that NMIFLGFRC and NMIFLGCLR register
also affects the bits of this register in the same way as they do for the
NMIFLG register. This register is reset only by PORESETn.
Notes:
[1] This register is added to keep the definition of System Control
Reset Cause Register Clean.
Reset type: PORESETn
7 ERADNMI R 0h Shadow NMI Flags: When an NMIFLG bit is set due to any of the
possible NMI source in the device, the corresponding bit in this
register is also set. Note that NMIFLGFRC and NMIFLGCLR register
also affects the bits of this register in the same way as they do for the
NMIFLG register. This register is reset only by PORESETn.
Notes:
[1] This register is added to keep the definition of System Control
Reset Cause Register Clean.
Reset type: PORESETn
6 PIEVECTERR R 0h Shadow NMI Flags: When an NMIFLG bit is set due to any of the
possible NMI source in the device, the corresponding bit in this
register is also set. Note that NMIFLGFRC and NMIFLGCLR register
also affects the bits of this register in the same way as they do for the
NMIFLG register. This register is reset only by PORESETn.
Notes:
[1] This register is added to keep the definition of System Control
Reset Cause Register Clean.
Reset type: PORESETn
5 CPU2HWBISTERR R 0h Shadow NMI Flags: When an NMIFLG bit is set due to any of the
possible NMI source in the device, the corresponding bit in this
register is also set. Note that NMIFLGFRC and NMIFLGCLR register
also affects the bits of this register in the same way as they do for the
NMIFLG register. This register is reset only by PORESETn.
Notes:
[1] This register is added to keep the definition of System Control
Reset Cause Register Clean.
Reset type: PORESETn

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Table 3-320. NMISHDFLG Register Field Descriptions (continued)

Bit Field Type Reset Description
4 CPU1HWBISTERR R 0h Shadow NMI Flags: When an NMIFLG bit is set due to any of the
possible NMI source in the device, the corresponding bit in this
register is also set. Note that NMIFLGFRC and NMIFLGCLR register
also affects the bits of this register in the same way as they do for the
NMIFLG register. This register is reset only by PORESETn.
Notes:
[1] This register is added to keep the definition of System Control
Reset Cause Register Clean.
Reset type: PORESETn
3 FLUNCERR R 0h Shadow NMI Flags: When an NMIFLG bit is set due to any of the
possible NMI source in the device, the corresponding bit in this
register is also set. Note that NMIFLGFRC and NMIFLGCLR register
also affects the bits of this register in the same way as they do for the
NMIFLG register. This register is reset only by PORESETn.
Notes:
[1] This register is added to keep the definition of System Control
Reset Cause Register Clean.
Reset type: PORESETn
2 RAMUNCERR R 0h Shadow NMI Flags: When an NMIFLG bit is set due to any of the
possible NMI source in the device, the corresponding bit in this
register is also set. Note that NMIFLGFRC and NMIFLGCLR register
also affects the bits of this register in the same way as they do for the
NMIFLG register. This register is reset only by PORESETn.
Notes:
[1] This register is added to keep the definition of System Control
Reset Cause Register Clean.
Reset type: PORESETn
1 CLOCKFAIL R 0h Shadow NMI Flags: When an NMIFLG bit is set due to any of the
possible NMI source in the device, the corresponding bit in this
register is also set. Note that NMIFLGFRC and NMIFLGCLR register
also affects the bits of this register in the same way as they do for the
NMIFLG register. This register is reset only by PORESETn.
Notes:
[1] This register is added to keep the definition of System Control
Reset Cause Register Clean.
Reset type: PORESETn
0 RESERVED R-0 0h Reserved

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3.16.13.8 ERRORSTS Register (Offset = 7h) [Reset = 2h]

ERRORSTS is shown in Figure 3-301 and described in Table 3-321.
Return to the Summary Table.
Error pin status
Figure 3-301. ERRORSTS Register
15 14 13 12 11 10 9 8
RESERVED
R-0-0h

7 6 5 4 3 2 1 0
RESERVED PINSTS ERROR
R-0-0h R-1h R-0h

Table 3-321. ERRORSTS Register Field Descriptions

Bit Field Type Reset Description
15-2 RESERVED R-0 0h Reserved
1 PINSTS R 1h 0, Error Pin is 0
1, Error Pin is 1
Note: ERRORSTS register can be read by CPU2 but cannot be
cleared by CPU2.
Reset type: PORESETn
0 ERROR R 0h 0,None of the error sources were triggered.
1, One or more of the error sources triggered, or
ERRORSTS.ERROR was set by a write of 1 to
ERRORSTSFRC.ERROR bit. Once set, the ERROR flag can be
cleared by writing 1 to ERRORSTSCLR.ERROR bit. Following are
the events/triggers which can set this bit:
1. If any of flags in NMISHDFLG register is set on CPU1/CPU2
2. Watchdog reset
3. Error on a Pie vector fetch
4. Efuse error
5. If any of flags in NMISHDFLG register is set on CM
On a read of this bit, the pin Error pin state will be returned.
Note: ERRORSTS register can be read by CPU2 but cannot be
cleared by CPU2.
Reset type: PORESETn

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3.16.13.9 ERRORSTSCLR Register (Offset = 8h) [Reset = 0h]

ERRORSTSCLR is shown in Figure 3-302 and described in Table 3-322.
Return to the Summary Table.
ERRORSTS clear register
Figure 3-302. ERRORSTSCLR Register
15 14 13 12 11 10 9 8
RESERVED
R-0-0h

7 6 5 4 3 2 1 0
RESERVED ERROR
R-0-0h R-0/W1S-0h

Table 3-322. ERRORSTSCLR Register Field Descriptions

Bit Field Type Reset Description
15-1 RESERVED R-0 0h Reserved
0 ERROR R-0/W1S 0h 0,No effect
1, ERRORSTS.ERROR is cleared to 0
Note:This register is available only on CPU1
Reset type: PORESETn

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3.16.13.10 ERRORSTSFRC Register (Offset = 9h) [Reset = 0h]

ERRORSTSFRC is shown in Figure 3-303 and described in Table 3-323.
Return to the Summary Table.
ERRORSTS force register
Figure 3-303. ERRORSTSFRC Register
15 14 13 12 11 10 9 8
RESERVED
R-0-0h

7 6 5 4 3 2 1 0
RESERVED ERROR
R-0-0h R-0/W1S-0h

Table 3-323. ERRORSTSFRC Register Field Descriptions

Bit Field Type Reset Description
15-1 RESERVED R-0 0h Reserved
0 ERROR R-0/W1S 0h 0,No effect
1, ERRORSTS.ERROR is set to 1
Note:This register is available only on CPU1
Reset type: PORESETn

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3.16.13.11 ERRORCTL Register (Offset = Ah) [Reset = 0h]

ERRORCTL is shown in Figure 3-304 and described in Table 3-324.
Return to the Summary Table.
Error pin control register
Figure 3-304. ERRORCTL Register
15 14 13 12 11 10 9 8
RESERVED
R-0-0h

7 6 5 4 3 2 1 0
RESERVED ERRORPOLSE
L
R-0-0h R/W-0h

Table 3-324. ERRORCTL Register Field Descriptions

Bit Field Type Reset Description
15-1 RESERVED R-0 0h Reserved
0 ERRORPOLSEL R/W 0h 0, If ERRORSTS.ERROR is 1, Error pin will be driven with a value of
0, else 1.
1, If ERRORSTS.ERROR is 1, Error pin will be driven with a value of
1, else 0.
Note:This register is available only on CPU1
Reset type: PORESETn

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3.16.13.12 ERRORLOCK Register (Offset = Bh) [Reset = 0h]

ERRORLOCK is shown in Figure 3-305 and described in Table 3-325.
Return to the Summary Table.
Lock register to Error pin registers.
Figure 3-305. ERRORLOCK Register
15 14 13 12 11 10 9 8
RESERVED
R-0-0h

7 6 5 4 3 2 1 0
RESERVED ERRORCTL
R-0-0h R/WSonce-0h

Table 3-325. ERRORLOCK Register Field Descriptions

Bit Field Type Reset Description
15-1 RESERVED R-0 0h Reserved
0 ERRORCTL R/WSonce 0h 0, Writes to ERRORCTL register allowed.
1, Writes to ERRORCTL register is blocked.
Writes of 0 to this bit has no effect. Write of 1 will set this bit, cleared
only on a SYSRSn.
Note:This register is available only on CPU1
Reset type: SYSRSn

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3.16.14 PIE_CTRL_REGS Registers

Table 3-326 lists the memory-mapped registers for the PIE_CTRL_REGS registers. All register offset addresses
not listed in Table 3-326 should be considered as reserved locations and the register contents should not be
modified.
Table 3-326. PIE_CTRL_REGS Registers
Offset Acronym Register Name Write Protection Section
0h PIECTRL ePIE Control Register Go
1h PIEACK Interrupt Acknowledge Register Go
2h PIEIER1 Interrupt Group 1 Enable Register Go
3h PIEIFR1 Interrupt Group 1 Flag Register Go
4h PIEIER2 Interrupt Group 2 Enable Register Go
5h PIEIFR2 Interrupt Group 2 Flag Register Go
6h PIEIER3 Interrupt Group 3 Enable Register Go
7h PIEIFR3 Interrupt Group 3 Flag Register Go
8h PIEIER4 Interrupt Group 4 Enable Register Go
9h PIEIFR4 Interrupt Group 4 Flag Register Go
Ah PIEIER5 Interrupt Group 5 Enable Register Go
Bh PIEIFR5 Interrupt Group 5 Flag Register Go
Ch PIEIER6 Interrupt Group 6 Enable Register Go
Dh PIEIFR6 Interrupt Group 6 Flag Register Go
Eh PIEIER7 Interrupt Group 7 Enable Register Go
Fh PIEIFR7 Interrupt Group 7 Flag Register Go
10h PIEIER8 Interrupt Group 8 Enable Register Go
11h PIEIFR8 Interrupt Group 8 Flag Register Go
12h PIEIER9 Interrupt Group 9 Enable Register Go
13h PIEIFR9 Interrupt Group 9 Flag Register Go
14h PIEIER10 Interrupt Group 10 Enable Register Go
15h PIEIFR10 Interrupt Group 10 Flag Register Go
16h PIEIER11 Interrupt Group 11 Enable Register Go
17h PIEIFR11 Interrupt Group 11 Flag Register Go
18h PIEIER12 Interrupt Group 12 Enable Register Go
19h PIEIFR12 Interrupt Group 12 Flag Register Go

Complex bit access types are encoded to fit into small table cells. Table 3-327 shows the codes that are used for
access types in this section.
Table 3-327. PIE_CTRL_REGS Access Type Codes
Access Type Code Description
Read Type
R R Read
R-0 R Read
-0 Returns 0s
Write Type
W W Write
W1S W Write
1S 1 to set
Reset or Default Value

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Table 3-327. PIE_CTRL_REGS Access Type Codes

(continued)
Access Type Code Description
-n Value after reset or the default
value
Register Array Variables
i,j,k,l,m,n When these variables are used in
a register name, an offset, or an
address, they refer to the value of
a register array where the register
is part of a group of repeating
registers. The register groups
form a hierarchical structure and
the array is represented with a
formula.
y When this variable is used in a
register name, an offset, or an
address it refers to the value of
a register array.

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3.16.14.1 PIECTRL Register (Offset = 0h) [Reset = 0h]

PIECTRL is shown in Figure 3-306 and described in Table 3-328.
Return to the Summary Table.
ePIE Control Register
Figure 3-306. PIECTRL Register
15 14 13 12 11 10 9 8
PIEVECT
R-0h

7 6 5 4 3 2 1 0
PIEVECT ENPIE
R-0h R/W-0h

Table 3-328. PIECTRL Register Field Descriptions

Bit Field Type Reset Description
15-1 PIEVECT R 0h These bits indicate the vector address of the vector fetched from the
ePIE vector table. The least significant bit of the address is ignored
and only bits 1 to 15 of the address are shown. The vector value
can be read by the user to determine which interrupt generated the
vector fetch.
Note: When a NMI is serviced, the PIEVECT bit-field does not reflect
the vector as it does for other interrupts.
Reset type: SYSRSn
0 ENPIE R/W 0h Enable vector fetching from ePIE block. This bit must be set to 1
for peripheral interrupts to work. All ePIE registers (PIEACK, PIEIFR,
PIEIER) can be accessed even when the ePIE block is disabled.
Reset type: SYSRSn

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3.16.14.2 PIEACK Register (Offset = 1h) [Reset = 0h]

PIEACK is shown in Figure 3-307 and described in Table 3-329.
Return to the Summary Table.
Acknowledge Register
When an interrupt propagates from the ePIE to a CPU interrupt line, the interrupt group's PIEACK bit is set. This
prevents other interrupts in that group from propagating to the CPU while the first interrupt is handled. Writing a
1 to a PIEACK bit clears it and allows another interrupt from the corresponding group to propagate. ISRs for PIE
interrupts should clear the group's PIEACK bit before returning from the interrupt.
Writes of 0 are ignored.
Figure 3-307. PIEACK Register
15 14 13 12 11 10 9 8
RESERVED ACK12 ACK11 ACK10 ACK9
R-0-0h R/W1S-0h R/W1S-0h R/W1S-0h R/W1S-0h

7 6 5 4 3 2 1 0
ACK8 ACK7 ACK6 ACK5 ACK4 ACK3 ACK2 ACK1
R/W1S-0h R/W1S-0h R/W1S-0h R/W1S-0h R/W1S-0h R/W1S-0h R/W1S-0h R/W1S-0h

Table 3-329. PIEACK Register Field Descriptions

Bit Field Type Reset Description
15-12 RESERVED R-0 0h Reserved
11 ACK12 R/W1S 0h Acknowledge PIE Interrupt Group 12
Reset type: SYSRSn
10 ACK11 R/W1S 0h Acknowledge PIE Interrupt Group 11
Reset type: SYSRSn
9 ACK10 R/W1S 0h Acknowledge PIE Interrupt Group 10
Reset type: SYSRSn
8 ACK9 R/W1S 0h Acknowledge PIE Interrupt Group 9
Reset type: SYSRSn
7 ACK8 R/W1S 0h Acknowledge PIE Interrupt Group 8
Reset type: SYSRSn
6 ACK7 R/W1S 0h Acknowledge PIE Interrupt Group 7
Reset type: SYSRSn
5 ACK6 R/W1S 0h Acknowledge PIE Interrupt Group 6
Reset type: SYSRSn
4 ACK5 R/W1S 0h Acknowledge PIE Interrupt Group 5
Reset type: SYSRSn
3 ACK4 R/W1S 0h Acknowledge PIE Interrupt Group 4
Reset type: SYSRSn
2 ACK3 R/W1S 0h Acknowledge PIE Interrupt Group 3
Reset type: SYSRSn
1 ACK2 R/W1S 0h Acknowledge PIE Interrupt Group 2
Reset type: SYSRSn
0 ACK1 R/W1S 0h Acknowledge PIE Interrupt Group 1
Reset type: SYSRSn

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3.16.14.3 PIEIER1 Register (Offset = 2h) [Reset = 0h]

PIEIER1 is shown in Figure 3-308 and described in Table 3-330.
Return to the Summary Table.
Interrupt Group 1 Enable Register
These register bits individually enable an interrupt within a group. They behave very much like the bits in the
CPU interrupt enable register (IER).
Setting a bit to 1 allows the corresponding interrupt to propagate to the CPU.
Setting a bit to 0 prevents the corresponding interrupt from propagating. Note that a peripheral interrupt signal
can still set the PIEIFR bit for the disabled interrupt.
Figure 3-308. PIEIER1 Register
15 14 13 12 11 10 9 8
INTx16 INTx15 INTx14 INTx13 INTx12 INTx11 INTx10 INTx9
R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h

7 6 5 4 3 2 1 0
INTx8 INTx7 INTx6 INTx5 INTx4 INTx3 INTx2 INTx1
R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h

Table 3-330. PIEIER1 Register Field Descriptions

Bit Field Type Reset Description
15 INTx16 R/W 0h Enable for Interrupt 1.16
Reset type: SYSRSn
14 INTx15 R/W 0h Enable for Interrupt 1.15
Reset type: SYSRSn
13 INTx14 R/W 0h Enable for Interrupt 1.14
Reset type: SYSRSn
12 INTx13 R/W 0h Enable for Interrupt 1.13
Reset type: SYSRSn
11 INTx12 R/W 0h Enable for Interrupt 1.12
Reset type: SYSRSn
10 INTx11 R/W 0h Enable for Interrupt 1.11
Reset type: SYSRSn
9 INTx10 R/W 0h Enable for Interrupt 1.10
Reset type: SYSRSn
8 INTx9 R/W 0h Enable for Interrupt 1.9
Reset type: SYSRSn
7 INTx8 R/W 0h Enable for Interrupt 1.8
Reset type: SYSRSn
6 INTx7 R/W 0h Enable for Interrupt 1.7
Reset type: SYSRSn
5 INTx6 R/W 0h Enable for Interrupt 1.6
Reset type: SYSRSn
4 INTx5 R/W 0h Enable for Interrupt 1.5
Reset type: SYSRSn
3 INTx4 R/W 0h Enable for Interrupt 1.4
Reset type: SYSRSn
2 INTx3 R/W 0h Enable for Interrupt 1.3
Reset type: SYSRSn
1 INTx2 R/W 0h Enable for Interrupt 1.2
Reset type: SYSRSn
0 INTx1 R/W 0h Enable for Interrupt 1.1
Reset type: SYSRSn

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3.16.14.4 PIEIFR1 Register (Offset = 3h) [Reset = 0h]

PIEIFR1 is shown in Figure 3-309 and described in Table 3-331.
Return to the Summary Table.
Interrupt Group 1 Flag Register
These register bits indicate whether each interrupt in the group is currently pending. They behave very much like
the bits in the CPU interrupt flag register (IFR).
When a peripheral sends an interrupt, the corresponding bit is set. This bit is cleared when the interrupt
propagates to the CPU, at which point PIEACK is set.
NOTE: PIE IFR flags can be written to create software interrupts.
The IFR flag will be cleared on a write of zero. Hence, when the intent is to fire an interrupt it may cause
inadvertent cancellation of other interrupts. It is recommended to use this only for testing or with extreme caution
in the application code. Reading the PIE IFR registers is safe.
Figure 3-309. PIEIFR1 Register
15 14 13 12 11 10 9 8
INTx16 INTx15 INTx14 INTx13 INTx12 INTx11 INTx10 INTx9
R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h

7 6 5 4 3 2 1 0
INTx8 INTx7 INTx6 INTx5 INTx4 INTx3 INTx2 INTx1
R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h

Table 3-331. PIEIFR1 Register Field Descriptions

Bit Field Type Reset Description
15 INTx16 R/W 0h Flag for Interrupt 1.16
Reset type: SYSRSn
14 INTx15 R/W 0h Flag for Interrupt 1.15
Reset type: SYSRSn
13 INTx14 R/W 0h Flag for Interrupt 1.14
Reset type: SYSRSn
12 INTx13 R/W 0h Flag for Interrupt 1.13
Reset type: SYSRSn
11 INTx12 R/W 0h Flag for Interrupt 1.12
Reset type: SYSRSn
10 INTx11 R/W 0h Flag for Interrupt 1.11
Reset type: SYSRSn
9 INTx10 R/W 0h Flag for Interrupt 1.10
Reset type: SYSRSn
8 INTx9 R/W 0h Flag for Interrupt 1.9
Reset type: SYSRSn
7 INTx8 R/W 0h Flag for Interrupt 1.8
Reset type: SYSRSn
6 INTx7 R/W 0h Flag for Interrupt 1.7
Reset type: SYSRSn
5 INTx6 R/W 0h Flag for Interrupt 1.6
Reset type: SYSRSn
4 INTx5 R/W 0h Flag for Interrupt 1.5
Reset type: SYSRSn
3 INTx4 R/W 0h Flag for Interrupt 1.4
Reset type: SYSRSn
2 INTx3 R/W 0h Flag for Interrupt 1.3
Reset type: SYSRSn
1 INTx2 R/W 0h Flag for Interrupt 1.2
Reset type: SYSRSn

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Table 3-331. PIEIFR1 Register Field Descriptions (continued)

Bit Field Type Reset Description
0 INTx1 R/W 0h Flag for Interrupt 1.1
Reset type: SYSRSn

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3.16.14.5 PIEIER2 Register (Offset = 4h) [Reset = 0h]

PIEIER2 is shown in Figure 3-310 and described in Table 3-332.
Return to the Summary Table.
Interrupt Group 2 Enable Register
These register bits individually enable an interrupt within a group. They behave very much like the bits in the
CPU interrupt enable register (IER).
Setting a bit to 1 allows the corresponding interrupt to propagate to the CPU.
Setting a bit to 0 prevents the corresponding interrupt from propagating. Note that a peripheral interrupt signal
can still set the PIEIFR bit for the disabled interrupt.
Figure 3-310. PIEIER2 Register
15 14 13 12 11 10 9 8
INTx16 INTx15 INTx14 INTx13 INTx12 INTx11 INTx10 INTx9
R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h

7 6 5 4 3 2 1 0
INTx8 INTx7 INTx6 INTx5 INTx4 INTx3 INTx2 INTx1
R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h

Table 3-332. PIEIER2 Register Field Descriptions

Bit Field Type Reset Description
15 INTx16 R/W 0h Enable for Interrupt 2.16
Reset type: SYSRSn
14 INTx15 R/W 0h Enable for Interrupt 2.15
Reset type: SYSRSn
13 INTx14 R/W 0h Enable for Interrupt 2.14
Reset type: SYSRSn
12 INTx13 R/W 0h Enable for Interrupt 2.13
Reset type: SYSRSn
11 INTx12 R/W 0h Enable for Interrupt 2.12
Reset type: SYSRSn
10 INTx11 R/W 0h Enable for Interrupt 2.11
Reset type: SYSRSn
9 INTx10 R/W 0h Enable for Interrupt 2.10
Reset type: SYSRSn
8 INTx9 R/W 0h Enable for Interrupt 2.9
Reset type: SYSRSn
7 INTx8 R/W 0h Enable for Interrupt 2.8
Reset type: SYSRSn
6 INTx7 R/W 0h Enable for Interrupt 2.7
Reset type: SYSRSn
5 INTx6 R/W 0h Enable for Interrupt 2.6
Reset type: SYSRSn
4 INTx5 R/W 0h Enable for Interrupt 2.5
Reset type: SYSRSn
3 INTx4 R/W 0h Enable for Interrupt 2.4
Reset type: SYSRSn
2 INTx3 R/W 0h Enable for Interrupt 2.3
Reset type: SYSRSn
1 INTx2 R/W 0h Enable for Interrupt 2.2
Reset type: SYSRSn
0 INTx1 R/W 0h Enable for Interrupt 2.1
Reset type: SYSRSn

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3.16.14.6 PIEIFR2 Register (Offset = 5h) [Reset = 0h]

PIEIFR2 is shown in Figure 3-311 and described in Table 3-333.
Return to the Summary Table.
Interrupt Group 2 Flag Register
These register bits indicate whether each interrupt in the group is currently pending. They behave very much like
the bits in the CPU interrupt flag register (IFR).
When a peripheral sends an interrupt, the corresponding bit is set. This bit is cleared when the interrupt
propagates to the CPU, at which point PIEACK is set.
NOTE: PIE IFR flags can be written to create software interrupts.
The IFR flag will be cleared on a write of zero. Hence, when the intent is to fire an interrupt it may cause
inadvertent cancellation of other interrupts. It is recommended to use this only for testing or with extreme caution
in the application code. Reading the PIE IFR registers is safe.
Figure 3-311. PIEIFR2 Register
15 14 13 12 11 10 9 8
INTx16 INTx15 INTx14 INTx13 INTx12 INTx11 INTx10 INTx9
R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h

7 6 5 4 3 2 1 0
INTx8 INTx7 INTx6 INTx5 INTx4 INTx3 INTx2 INTx1
R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h

Table 3-333. PIEIFR2 Register Field Descriptions

Bit Field Type Reset Description
15 INTx16 R/W 0h Flag for Interrupt 2.16
Reset type: SYSRSn
14 INTx15 R/W 0h Flag for Interrupt 2.15
Reset type: SYSRSn
13 INTx14 R/W 0h Flag for Interrupt 2.14
Reset type: SYSRSn
12 INTx13 R/W 0h Flag for Interrupt 2.13
Reset type: SYSRSn
11 INTx12 R/W 0h Flag for Interrupt 2.12
Reset type: SYSRSn
10 INTx11 R/W 0h Flag for Interrupt 2.11
Reset type: SYSRSn
9 INTx10 R/W 0h Flag for Interrupt 2.10
Reset type: SYSRSn
8 INTx9 R/W 0h Flag for Interrupt 2.9
Reset type: SYSRSn
7 INTx8 R/W 0h Flag for Interrupt 2.8
Reset type: SYSRSn
6 INTx7 R/W 0h Flag for Interrupt 2.7
Reset type: SYSRSn
5 INTx6 R/W 0h Flag for Interrupt 2.6
Reset type: SYSRSn
4 INTx5 R/W 0h Flag for Interrupt 2.5
Reset type: SYSRSn
3 INTx4 R/W 0h Flag for Interrupt 2.4
Reset type: SYSRSn
2 INTx3 R/W 0h Flag for Interrupt 2.3
Reset type: SYSRSn
1 INTx2 R/W 0h Flag for Interrupt 2.2
Reset type: SYSRSn

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Table 3-333. PIEIFR2 Register Field Descriptions (continued)

Bit Field Type Reset Description
0 INTx1 R/W 0h Flag for Interrupt 2.1
Reset type: SYSRSn

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3.16.14.7 PIEIER3 Register (Offset = 6h) [Reset = 0h]

PIEIER3 is shown in Figure 3-312 and described in Table 3-334.
Return to the Summary Table.
Interrupt Group 3 Enable Register
These register bits individually enable an interrupt within a group. They behave very much like the bits in the
CPU interrupt enable register (IER).
Setting a bit to 1 allows the corresponding interrupt to propagate to the CPU.
Setting a bit to 0 prevents the corresponding interrupt from propagating. Note that a peripheral interrupt signal
can still set the PIEIFR bit for the disabled interrupt.
Figure 3-312. PIEIER3 Register
15 14 13 12 11 10 9 8
INTx16 INTx15 INTx14 INTx13 INTx12 INTx11 INTx10 INTx9
R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h

7 6 5 4 3 2 1 0
INTx8 INTx7 INTx6 INTx5 INTx4 INTx3 INTx2 INTx1
R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h

Table 3-334. PIEIER3 Register Field Descriptions

Bit Field Type Reset Description
15 INTx16 R/W 0h Enable for Interrupt 3.16
Reset type: SYSRSn
14 INTx15 R/W 0h Enable for Interrupt 3.15
Reset type: SYSRSn
13 INTx14 R/W 0h Enable for Interrupt 3.14
Reset type: SYSRSn
12 INTx13 R/W 0h Enable for Interrupt 3.13
Reset type: SYSRSn
11 INTx12 R/W 0h Enable for Interrupt 3.12
Reset type: SYSRSn
10 INTx11 R/W 0h Enable for Interrupt 3.11
Reset type: SYSRSn
9 INTx10 R/W 0h Enable for Interrupt 3.10
Reset type: SYSRSn
8 INTx9 R/W 0h Enable for Interrupt 3.9
Reset type: SYSRSn
7 INTx8 R/W 0h Enable for Interrupt 3.8
Reset type: SYSRSn
6 INTx7 R/W 0h Enable for Interrupt 3.7
Reset type: SYSRSn
5 INTx6 R/W 0h Enable for Interrupt 3.6
Reset type: SYSRSn
4 INTx5 R/W 0h Enable for Interrupt 3.5
Reset type: SYSRSn
3 INTx4 R/W 0h Enable for Interrupt 3.4
Reset type: SYSRSn
2 INTx3 R/W 0h Enable for Interrupt 3.3
Reset type: SYSRSn
1 INTx2 R/W 0h Enable for Interrupt 3.2
Reset type: SYSRSn
0 INTx1 R/W 0h Enable for Interrupt 3.1
Reset type: SYSRSn

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3.16.14.8 PIEIFR3 Register (Offset = 7h) [Reset = 0h]

PIEIFR3 is shown in Figure 3-313 and described in Table 3-335.
Return to the Summary Table.
Interrupt Group 3 Flag Register
These register bits indicate whether each interrupt in the group is currently pending. They behave very much like
the bits in the CPU interrupt flag register (IFR).
When a peripheral sends an interrupt, the corresponding bit is set. This bit is cleared when the interrupt
propagates to the CPU, at which point PIEACK is set.
NOTE: PIE IFR flags can be written to create software interrupts.
The IFR flag will be cleared on a write of zero. Hence, when the intent is to fire an interrupt it may cause
inadvertent cancellation of other interrupts. It is recommended to use this only for testing or with extreme caution
in the application code. Reading the PIE IFR registers is safe.
Figure 3-313. PIEIFR3 Register
15 14 13 12 11 10 9 8
INTx16 INTx15 INTx14 INTx13 INTx12 INTx11 INTx10 INTx9
R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h

7 6 5 4 3 2 1 0
INTx8 INTx7 INTx6 INTx5 INTx4 INTx3 INTx2 INTx1
R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h

Table 3-335. PIEIFR3 Register Field Descriptions

Bit Field Type Reset Description
15 INTx16 R/W 0h Flag for Interrupt 3.16
Reset type: SYSRSn
14 INTx15 R/W 0h Flag for Interrupt 3.15
Reset type: SYSRSn
13 INTx14 R/W 0h Flag for Interrupt 3.14
Reset type: SYSRSn
12 INTx13 R/W 0h Flag for Interrupt 3.13
Reset type: SYSRSn
11 INTx12 R/W 0h Flag for Interrupt 3.12
Reset type: SYSRSn
10 INTx11 R/W 0h Flag for Interrupt 3.11
Reset type: SYSRSn
9 INTx10 R/W 0h Flag for Interrupt 3.10
Reset type: SYSRSn
8 INTx9 R/W 0h Flag for Interrupt 3.9
Reset type: SYSRSn
7 INTx8 R/W 0h Flag for Interrupt 3.8
Reset type: SYSRSn
6 INTx7 R/W 0h Flag for Interrupt 3.7
Reset type: SYSRSn
5 INTx6 R/W 0h Flag for Interrupt 3.6
Reset type: SYSRSn
4 INTx5 R/W 0h Flag for Interrupt 3.5
Reset type: SYSRSn
3 INTx4 R/W 0h Flag for Interrupt 3.4
Reset type: SYSRSn
2 INTx3 R/W 0h Flag for Interrupt 3.3
Reset type: SYSRSn
1 INTx2 R/W 0h Flag for Interrupt 3.2
Reset type: SYSRSn

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Table 3-335. PIEIFR3 Register Field Descriptions (continued)

Bit Field Type Reset Description
0 INTx1 R/W 0h Flag for Interrupt 3.1
Reset type: SYSRSn

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3.16.14.9 PIEIER4 Register (Offset = 8h) [Reset = 0h]

PIEIER4 is shown in Figure 3-314 and described in Table 3-336.
Return to the Summary Table.
Interrupt Group 4 Enable Register
These register bits individually enable an interrupt within a group. They behave very much like the bits in the
CPU interrupt enable register (IER).
Setting a bit to 1 allows the corresponding interrupt to propagate to the CPU.
Setting a bit to 0 prevents the corresponding interrupt from propagating. Note that a peripheral interrupt signal
can still set the PIEIFR bit for the disabled interrupt.
Figure 3-314. PIEIER4 Register
15 14 13 12 11 10 9 8
INTx16 INTx15 INTx14 INTx13 INTx12 INTx11 INTx10 INTx9
R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h

7 6 5 4 3 2 1 0
INTx8 INTx7 INTx6 INTx5 INTx4 INTx3 INTx2 INTx1
R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h

Table 3-336. PIEIER4 Register Field Descriptions

Bit Field Type Reset Description
15 INTx16 R/W 0h Enable for Interrupt 4.16
Reset type: SYSRSn
14 INTx15 R/W 0h Enable for Interrupt 4.15
Reset type: SYSRSn
13 INTx14 R/W 0h Enable for Interrupt 4.14
Reset type: SYSRSn
12 INTx13 R/W 0h Enable for Interrupt 4.13
Reset type: SYSRSn
11 INTx12 R/W 0h Enable for Interrupt 4.12
Reset type: SYSRSn
10 INTx11 R/W 0h Enable for Interrupt 4.11
Reset type: SYSRSn
9 INTx10 R/W 0h Enable for Interrupt 4.10
Reset type: SYSRSn
8 INTx9 R/W 0h Enable for Interrupt 4.9
Reset type: SYSRSn
7 INTx8 R/W 0h Enable for Interrupt 4.8
Reset type: SYSRSn
6 INTx7 R/W 0h Enable for Interrupt 4.7
Reset type: SYSRSn
5 INTx6 R/W 0h Enable for Interrupt 4.6
Reset type: SYSRSn
4 INTx5 R/W 0h Enable for Interrupt 4.5
Reset type: SYSRSn
3 INTx4 R/W 0h Enable for Interrupt 4.4
Reset type: SYSRSn
2 INTx3 R/W 0h Enable for Interrupt 4.3
Reset type: SYSRSn
1 INTx2 R/W 0h Enable for Interrupt 4.2
Reset type: SYSRSn
0 INTx1 R/W 0h Enable for Interrupt 4.1
Reset type: SYSRSn

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3.16.14.10 PIEIFR4 Register (Offset = 9h) [Reset = 0h]

PIEIFR4 is shown in Figure 3-315 and described in Table 3-337.
Return to the Summary Table.
Interrupt Group 4 Flag Register
These register bits indicate whether each interrupt in the group is currently pending. They behave very much like
the bits in the CPU interrupt flag register (IFR).
When a peripheral sends an interrupt, the corresponding bit is set. This bit is cleared when the interrupt
propagates to the CPU, at which point PIEACK is set.
NOTE: PIE IFR flags can be written to create software interrupts.
The IFR flag will be cleared on a write of zero. Hence, when the intent is to fire an interrupt it may cause
inadvertent cancellation of other interrupts. It is recommended to use this only for testing or with extreme caution
in the application code. Reading the PIE IFR registers is safe.
Figure 3-315. PIEIFR4 Register
15 14 13 12 11 10 9 8
INTx16 INTx15 INTx14 INTx13 INTx12 INTx11 INTx10 INTx9
R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h

7 6 5 4 3 2 1 0
INTx8 INTx7 INTx6 INTx5 INTx4 INTx3 INTx2 INTx1
R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h

Table 3-337. PIEIFR4 Register Field Descriptions

Bit Field Type Reset Description
15 INTx16 R/W 0h Flag for Interrupt 4.16
Reset type: SYSRSn
14 INTx15 R/W 0h Flag for Interrupt 4.15
Reset type: SYSRSn
13 INTx14 R/W 0h Flag for Interrupt 4.14
Reset type: SYSRSn
12 INTx13 R/W 0h Flag for Interrupt 4.13
Reset type: SYSRSn
11 INTx12 R/W 0h Flag for Interrupt 4.12
Reset type: SYSRSn
10 INTx11 R/W 0h Flag for Interrupt 4.11
Reset type: SYSRSn
9 INTx10 R/W 0h Flag for Interrupt 4.10
Reset type: SYSRSn
8 INTx9 R/W 0h Flag for Interrupt 4.9
Reset type: SYSRSn
7 INTx8 R/W 0h Flag for Interrupt 4.8
Reset type: SYSRSn
6 INTx7 R/W 0h Flag for Interrupt 4.7
Reset type: SYSRSn
5 INTx6 R/W 0h Flag for Interrupt 4.6
Reset type: SYSRSn
4 INTx5 R/W 0h Flag for Interrupt 4.5
Reset type: SYSRSn
3 INTx4 R/W 0h Flag for Interrupt 4.4
Reset type: SYSRSn
2 INTx3 R/W 0h Flag for Interrupt 4.3
Reset type: SYSRSn
1 INTx2 R/W 0h Flag for Interrupt 4.2
Reset type: SYSRSn

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Table 3-337. PIEIFR4 Register Field Descriptions (continued)

Bit Field Type Reset Description
0 INTx1 R/W 0h Flag for Interrupt 4.1
Reset type: SYSRSn

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3.16.14.11 PIEIER5 Register (Offset = Ah) [Reset = 0h]

PIEIER5 is shown in Figure 3-316 and described in Table 3-338.
Return to the Summary Table.
Interrupt Group 5 Enable Register
These register bits individually enable an interrupt within a group. They behave very much like the bits in the
CPU interrupt enable register (IER).
Setting a bit to 1 allows the corresponding interrupt to propagate to the CPU.
Setting a bit to 0 prevents the corresponding interrupt from propagating. Note that a peripheral interrupt signal
can still set the PIEIFR bit for the disabled interrupt.
Figure 3-316. PIEIER5 Register
15 14 13 12 11 10 9 8
INTx16 INTx15 INTx14 INTx13 INTx12 INTx11 INTx10 INTx9
R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h

7 6 5 4 3 2 1 0
INTx8 INTx7 INTx6 INTx5 INTx4 INTx3 INTx2 INTx1
R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h

Table 3-338. PIEIER5 Register Field Descriptions

Bit Field Type Reset Description
15 INTx16 R/W 0h Enable for Interrupt 5.16
Reset type: SYSRSn
14 INTx15 R/W 0h Enable for Interrupt 5.15
Reset type: SYSRSn
13 INTx14 R/W 0h Enable for Interrupt 5.14
Reset type: SYSRSn
12 INTx13 R/W 0h Enable for Interrupt 5.13
Reset type: SYSRSn
11 INTx12 R/W 0h Enable for Interrupt 5.12
Reset type: SYSRSn
10 INTx11 R/W 0h Enable for Interrupt 5.11
Reset type: SYSRSn
9 INTx10 R/W 0h Enable for Interrupt 5.10
Reset type: SYSRSn
8 INTx9 R/W 0h Enable for Interrupt 5.9
Reset type: SYSRSn
7 INTx8 R/W 0h Enable for Interrupt 5.8
Reset type: SYSRSn
6 INTx7 R/W 0h Enable for Interrupt 5.7
Reset type: SYSRSn
5 INTx6 R/W 0h Enable for Interrupt 5.6
Reset type: SYSRSn
4 INTx5 R/W 0h Enable for Interrupt 5.5
Reset type: SYSRSn
3 INTx4 R/W 0h Enable for Interrupt 5.4
Reset type: SYSRSn
2 INTx3 R/W 0h Enable for Interrupt 5.3
Reset type: SYSRSn
1 INTx2 R/W 0h Enable for Interrupt 5.2
Reset type: SYSRSn
0 INTx1 R/W 0h Enable for Interrupt 5.1
Reset type: SYSRSn

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3.16.14.12 PIEIFR5 Register (Offset = Bh) [Reset = 0h]

PIEIFR5 is shown in Figure 3-317 and described in Table 3-339.
Return to the Summary Table.
Interrupt Group 5 Flag Register
These register bits indicate whether each interrupt in the group is currently pending. They behave very much like
the bits in the CPU interrupt flag register (IFR).
When a peripheral sends an interrupt, the corresponding bit is set. This bit is cleared when the interrupt
propagates to the CPU, at which point PIEACK is set.
NOTE: PIE IFR flags can be written to create software interrupts.
The IFR flag will be cleared on a write of zero. Hence, when the intent is to fire an interrupt it may cause
inadvertent cancellation of other interrupts. It is recommended to use this only for testing or with extreme caution
in the application code. Reading the PIE IFR registers is safe.
Figure 3-317. PIEIFR5 Register
15 14 13 12 11 10 9 8
INTx16 INTx15 INTx14 INTx13 INTx12 INTx11 INTx10 INTx9
R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h

7 6 5 4 3 2 1 0
INTx8 INTx7 INTx6 INTx5 INTx4 INTx3 INTx2 INTx1
R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h

Table 3-339. PIEIFR5 Register Field Descriptions

Bit Field Type Reset Description
15 INTx16 R/W 0h Flag for Interrupt 5.16
Reset type: SYSRSn
14 INTx15 R/W 0h Flag for Interrupt 5.15
Reset type: SYSRSn
13 INTx14 R/W 0h Flag for Interrupt 5.14
Reset type: SYSRSn
12 INTx13 R/W 0h Flag for Interrupt 5.13
Reset type: SYSRSn
11 INTx12 R/W 0h Flag for Interrupt 5.12
Reset type: SYSRSn
10 INTx11 R/W 0h Flag for Interrupt 5.11
Reset type: SYSRSn
9 INTx10 R/W 0h Flag for Interrupt 5.10
Reset type: SYSRSn
8 INTx9 R/W 0h Flag for Interrupt 5.9
Reset type: SYSRSn
7 INTx8 R/W 0h Flag for Interrupt 5.8
Reset type: SYSRSn
6 INTx7 R/W 0h Flag for Interrupt 5.7
Reset type: SYSRSn
5 INTx6 R/W 0h Flag for Interrupt 5.6
Reset type: SYSRSn
4 INTx5 R/W 0h Flag for Interrupt 5.5
Reset type: SYSRSn
3 INTx4 R/W 0h Flag for Interrupt 5.4
Reset type: SYSRSn
2 INTx3 R/W 0h Flag for Interrupt 5.3
Reset type: SYSRSn
1 INTx2 R/W 0h Flag for Interrupt 5.2
Reset type: SYSRSn

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Table 3-339. PIEIFR5 Register Field Descriptions (continued)

Bit Field Type Reset Description
0 INTx1 R/W 0h Flag for Interrupt 5.1
Reset type: SYSRSn

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3.16.14.13 PIEIER6 Register (Offset = Ch) [Reset = 0h]

PIEIER6 is shown in Figure 3-318 and described in Table 3-340.
Return to the Summary Table.
Interrupt Group 6 Enable Register
These register bits individually enable an interrupt within a group. They behave very much like the bits in the
CPU interrupt enable register (IER).
Setting a bit to 1 allows the corresponding interrupt to propagate to the CPU.
Setting a bit to 0 prevents the corresponding interrupt from propagating. Note that a peripheral interrupt signal
can still set the PIEIFR bit for the disabled interrupt.
Figure 3-318. PIEIER6 Register
15 14 13 12 11 10 9 8
INTx16 INTx15 INTx14 INTx13 INTx12 INTx11 INTx10 INTx9
R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h

7 6 5 4 3 2 1 0
INTx8 INTx7 INTx6 INTx5 INTx4 INTx3 INTx2 INTx1
R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h

Table 3-340. PIEIER6 Register Field Descriptions

Bit Field Type Reset Description
15 INTx16 R/W 0h Enable for Interrupt 6.16
Reset type: SYSRSn
14 INTx15 R/W 0h Enable for Interrupt 6.15
Reset type: SYSRSn
13 INTx14 R/W 0h Enable for Interrupt 6.14
Reset type: SYSRSn
12 INTx13 R/W 0h Enable for Interrupt 6.13
Reset type: SYSRSn
11 INTx12 R/W 0h Enable for Interrupt 6.12
Reset type: SYSRSn
10 INTx11 R/W 0h Enable for Interrupt 6.11
Reset type: SYSRSn
9 INTx10 R/W 0h Enable for Interrupt 6.10
Reset type: SYSRSn
8 INTx9 R/W 0h Enable for Interrupt 6.9
Reset type: SYSRSn
7 INTx8 R/W 0h Enable for Interrupt 6.8
Reset type: SYSRSn
6 INTx7 R/W 0h Enable for Interrupt 6.7
Reset type: SYSRSn
5 INTx6 R/W 0h Enable for Interrupt 6.6
Reset type: SYSRSn
4 INTx5 R/W 0h Enable for Interrupt 6.5
Reset type: SYSRSn
3 INTx4 R/W 0h Enable for Interrupt 6.4
Reset type: SYSRSn
2 INTx3 R/W 0h Enable for Interrupt 6.3
Reset type: SYSRSn
1 INTx2 R/W 0h Enable for Interrupt 6.2
Reset type: SYSRSn
0 INTx1 R/W 0h Enable for Interrupt 6.1
Reset type: SYSRSn

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3.16.14.14 PIEIFR6 Register (Offset = Dh) [Reset = 0h]

PIEIFR6 is shown in Figure 3-319 and described in Table 3-341.
Return to the Summary Table.
Interrupt Group 6 Flag Register
These register bits indicate whether each interrupt in the group is currently pending. They behave very much like
the bits in the CPU interrupt flag register (IFR).
When a peripheral sends an interrupt, the corresponding bit is set. This bit is cleared when the interrupt
propagates to the CPU, at which point PIEACK is set.
NOTE: PIE IFR flags can be written to create software interrupts.
The IFR flag will be cleared on a write of zero. Hence, when the intent is to fire an interrupt it may cause
inadvertent cancellation of other interrupts. It is recommended to use this only for testing or with extreme caution
in the application code. Reading the PIE IFR registers is safe.
Figure 3-319. PIEIFR6 Register
15 14 13 12 11 10 9 8
INTx16 INTx15 INTx14 INTx13 INTx12 INTx11 INTx10 INTx9
R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h

7 6 5 4 3 2 1 0
INTx8 INTx7 INTx6 INTx5 INTx4 INTx3 INTx2 INTx1
R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h

Table 3-341. PIEIFR6 Register Field Descriptions

Bit Field Type Reset Description
15 INTx16 R/W 0h Flag for Interrupt 6.16
Reset type: SYSRSn
14 INTx15 R/W 0h Flag for Interrupt 6.15
Reset type: SYSRSn
13 INTx14 R/W 0h Flag for Interrupt 6.14
Reset type: SYSRSn
12 INTx13 R/W 0h Flag for Interrupt 6.13
Reset type: SYSRSn
11 INTx12 R/W 0h Flag for Interrupt 6.12
Reset type: SYSRSn
10 INTx11 R/W 0h Flag for Interrupt 6.11
Reset type: SYSRSn
9 INTx10 R/W 0h Flag for Interrupt 6.10
Reset type: SYSRSn
8 INTx9 R/W 0h Flag for Interrupt 6.9
Reset type: SYSRSn
7 INTx8 R/W 0h Flag for Interrupt 6.8
Reset type: SYSRSn
6 INTx7 R/W 0h Flag for Interrupt 6.7
Reset type: SYSRSn
5 INTx6 R/W 0h Flag for Interrupt 6.6
Reset type: SYSRSn
4 INTx5 R/W 0h Flag for Interrupt 6.5
Reset type: SYSRSn
3 INTx4 R/W 0h Flag for Interrupt 6.4
Reset type: SYSRSn
2 INTx3 R/W 0h Flag for Interrupt 6.3
Reset type: SYSRSn
1 INTx2 R/W 0h Flag for Interrupt 6.2
Reset type: SYSRSn

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Table 3-341. PIEIFR6 Register Field Descriptions (continued)

Bit Field Type Reset Description
0 INTx1 R/W 0h Flag for Interrupt 6.1
Reset type: SYSRSn

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3.16.14.15 PIEIER7 Register (Offset = Eh) [Reset = 0h]

PIEIER7 is shown in Figure 3-320 and described in Table 3-342.
Return to the Summary Table.
Interrupt Group 7 Enable Register
These register bits individually enable an interrupt within a group. They behave very much like the bits in the
CPU interrupt enable register (IER).
Setting a bit to 1 allows the corresponding interrupt to propagate to the CPU.
Setting a bit to 0 prevents the corresponding interrupt from propagating. Note that a peripheral interrupt signal
can still set the PIEIFR bit for the disabled interrupt.
Figure 3-320. PIEIER7 Register
15 14 13 12 11 10 9 8
INTx16 INTx15 INTx14 INTx13 INTx12 INTx11 INTx10 INTx9
R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h

7 6 5 4 3 2 1 0
INTx8 INTx7 INTx6 INTx5 INTx4 INTx3 INTx2 INTx1
R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h

Table 3-342. PIEIER7 Register Field Descriptions

Bit Field Type Reset Description
15 INTx16 R/W 0h Enable for Interrupt 7.16
Reset type: SYSRSn
14 INTx15 R/W 0h Enable for Interrupt 7.15
Reset type: SYSRSn
13 INTx14 R/W 0h Enable for Interrupt 7.14
Reset type: SYSRSn
12 INTx13 R/W 0h Enable for Interrupt 7.13
Reset type: SYSRSn
11 INTx12 R/W 0h Enable for Interrupt 7.12
Reset type: SYSRSn
10 INTx11 R/W 0h Enable for Interrupt 7.11
Reset type: SYSRSn
9 INTx10 R/W 0h Enable for Interrupt 7.10
Reset type: SYSRSn
8 INTx9 R/W 0h Enable for Interrupt 7.9
Reset type: SYSRSn
7 INTx8 R/W 0h Enable for Interrupt 7.8
Reset type: SYSRSn
6 INTx7 R/W 0h Enable for Interrupt 7.7
Reset type: SYSRSn
5 INTx6 R/W 0h Enable for Interrupt 7.6
Reset type: SYSRSn
4 INTx5 R/W 0h Enable for Interrupt 7.5
Reset type: SYSRSn
3 INTx4 R/W 0h Enable for Interrupt 7.4
Reset type: SYSRSn
2 INTx3 R/W 0h Enable for Interrupt 7.3
Reset type: SYSRSn
1 INTx2 R/W 0h Enable for Interrupt 7.2
Reset type: SYSRSn
0 INTx1 R/W 0h Enable for Interrupt 7.1
Reset type: SYSRSn

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3.16.14.16 PIEIFR7 Register (Offset = Fh) [Reset = 0h]

PIEIFR7 is shown in Figure 3-321 and described in Table 3-343.
Return to the Summary Table.
Interrupt Group 7 Flag Register
These register bits indicate whether each interrupt in the group is currently pending. They behave very much like
the bits in the CPU interrupt flag register (IFR).
When a peripheral sends an interrupt, the corresponding bit is set. This bit is cleared when the interrupt
propagates to the CPU, at which point PIEACK is set.
NOTE: PIE IFR flags can be written to create software interrupts.
The IFR flag will be cleared on a write of zero. Hence, when the intent is to fire an interrupt it may cause
inadvertent cancellation of other interrupts. It is recommended to use this only for testing or with extreme caution
in the application code. Reading the PIE IFR registers is safe.
Figure 3-321. PIEIFR7 Register
15 14 13 12 11 10 9 8
INTx16 INTx15 INTx14 INTx13 INTx12 INTx11 INTx10 INTx9
R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h

7 6 5 4 3 2 1 0
INTx8 INTx7 INTx6 INTx5 INTx4 INTx3 INTx2 INTx1
R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h

Table 3-343. PIEIFR7 Register Field Descriptions

Bit Field Type Reset Description
15 INTx16 R/W 0h Flag for Interrupt 7.16
Reset type: SYSRSn
14 INTx15 R/W 0h Flag for Interrupt 7.15
Reset type: SYSRSn
13 INTx14 R/W 0h Flag for Interrupt 7.14
Reset type: SYSRSn
12 INTx13 R/W 0h Flag for Interrupt 7.13
Reset type: SYSRSn
11 INTx12 R/W 0h Flag for Interrupt 7.12
Reset type: SYSRSn
10 INTx11 R/W 0h Flag for Interrupt 7.11
Reset type: SYSRSn
9 INTx10 R/W 0h Flag for Interrupt 7.10
Reset type: SYSRSn
8 INTx9 R/W 0h Flag for Interrupt 7.9
Reset type: SYSRSn
7 INTx8 R/W 0h Flag for Interrupt 7.8
Reset type: SYSRSn
6 INTx7 R/W 0h Flag for Interrupt 7.7
Reset type: SYSRSn
5 INTx6 R/W 0h Flag for Interrupt 7.6
Reset type: SYSRSn
4 INTx5 R/W 0h Flag for Interrupt 7.5
Reset type: SYSRSn
3 INTx4 R/W 0h Flag for Interrupt 7.4
Reset type: SYSRSn
2 INTx3 R/W 0h Flag for Interrupt 7.3
Reset type: SYSRSn
1 INTx2 R/W 0h Flag for Interrupt 7.2
Reset type: SYSRSn

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Table 3-343. PIEIFR7 Register Field Descriptions (continued)

Bit Field Type Reset Description
0 INTx1 R/W 0h Flag for Interrupt 7.1
Reset type: SYSRSn

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3.16.14.17 PIEIER8 Register (Offset = 10h) [Reset = 0h]

PIEIER8 is shown in Figure 3-322 and described in Table 3-344.
Return to the Summary Table.
Interrupt Group 8 Enable Register
These register bits individually enable an interrupt within a group. They behave very much like the bits in the
CPU interrupt enable register (IER).
Setting a bit to 1 allows the corresponding interrupt to propagate to the CPU.
Setting a bit to 0 prevents the corresponding interrupt from propagating. Note that a peripheral interrupt signal
can still set the PIEIFR bit for the disabled interrupt.
Figure 3-322. PIEIER8 Register
15 14 13 12 11 10 9 8
INTx16 INTx15 INTx14 INTx13 INTx12 INTx11 INTx10 INTx9
R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h

7 6 5 4 3 2 1 0
INTx8 INTx7 INTx6 INTx5 INTx4 INTx3 INTx2 INTx1
R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h

Table 3-344. PIEIER8 Register Field Descriptions

Bit Field Type Reset Description
15 INTx16 R/W 0h Enable for Interrupt 8.16
Reset type: SYSRSn
14 INTx15 R/W 0h Enable for Interrupt 8.15
Reset type: SYSRSn
13 INTx14 R/W 0h Enable for Interrupt 8.14
Reset type: SYSRSn
12 INTx13 R/W 0h Enable for Interrupt 8.13
Reset type: SYSRSn
11 INTx12 R/W 0h Enable for Interrupt 8.12
Reset type: SYSRSn
10 INTx11 R/W 0h Enable for Interrupt 8.11
Reset type: SYSRSn
9 INTx10 R/W 0h Enable for Interrupt 8.10
Reset type: SYSRSn
8 INTx9 R/W 0h Enable for Interrupt 8.9
Reset type: SYSRSn
7 INTx8 R/W 0h Enable for Interrupt 8.8
Reset type: SYSRSn
6 INTx7 R/W 0h Enable for Interrupt 8.7
Reset type: SYSRSn
5 INTx6 R/W 0h Enable for Interrupt 8.6
Reset type: SYSRSn
4 INTx5 R/W 0h Enable for Interrupt 8.5
Reset type: SYSRSn
3 INTx4 R/W 0h Enable for Interrupt 8.4
Reset type: SYSRSn
2 INTx3 R/W 0h Enable for Interrupt 8.3
Reset type: SYSRSn
1 INTx2 R/W 0h Enable for Interrupt 8.2
Reset type: SYSRSn
0 INTx1 R/W 0h Enable for Interrupt 8.1
Reset type: SYSRSn

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3.16.14.18 PIEIFR8 Register (Offset = 11h) [Reset = 0h]

PIEIFR8 is shown in Figure 3-323 and described in Table 3-345.
Return to the Summary Table.
Interrupt Group 8 Flag Register
These register bits indicate whether each interrupt in the group is currently pending. They behave very much like
the bits in the CPU interrupt flag register (IFR).
When a peripheral sends an interrupt, the corresponding bit is set. This bit is cleared when the interrupt
propagates to the CPU, at which point PIEACK is set.
NOTE: PIE IFR flags can be written to create software interrupts.
The IFR flag will be cleared on a write of zero. Hence, when the intent is to fire an interrupt it may cause
inadvertent cancellation of other interrupts. It is recommended to use this only for testing or with extreme caution
in the application code. Reading the PIE IFR registers is safe.
Figure 3-323. PIEIFR8 Register
15 14 13 12 11 10 9 8
INTx16 INTx15 INTx14 INTx13 INTx12 INTx11 INTx10 INTx9
R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h

7 6 5 4 3 2 1 0
INTx8 INTx7 INTx6 INTx5 INTx4 INTx3 INTx2 INTx1
R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h

Table 3-345. PIEIFR8 Register Field Descriptions

Bit Field Type Reset Description
15 INTx16 R/W 0h Flag for Interrupt 8.16
Reset type: SYSRSn
14 INTx15 R/W 0h Flag for Interrupt 8.15
Reset type: SYSRSn
13 INTx14 R/W 0h Flag for Interrupt 8.14
Reset type: SYSRSn
12 INTx13 R/W 0h Flag for Interrupt 8.13
Reset type: SYSRSn
11 INTx12 R/W 0h Flag for Interrupt 8.12
Reset type: SYSRSn
10 INTx11 R/W 0h Flag for Interrupt 8.11
Reset type: SYSRSn
9 INTx10 R/W 0h Flag for Interrupt 8.10
Reset type: SYSRSn
8 INTx9 R/W 0h Flag for Interrupt 8.9
Reset type: SYSRSn
7 INTx8 R/W 0h Flag for Interrupt 8.8
Reset type: SYSRSn
6 INTx7 R/W 0h Flag for Interrupt 8.7
Reset type: SYSRSn
5 INTx6 R/W 0h Flag for Interrupt 8.6
Reset type: SYSRSn
4 INTx5 R/W 0h Flag for Interrupt 8.5
Reset type: SYSRSn
3 INTx4 R/W 0h Flag for Interrupt 8.4
Reset type: SYSRSn
2 INTx3 R/W 0h Flag for Interrupt 8.3
Reset type: SYSRSn
1 INTx2 R/W 0h Flag for Interrupt 8.2
Reset type: SYSRSn

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Table 3-345. PIEIFR8 Register Field Descriptions (continued)

Bit Field Type Reset Description
0 INTx1 R/W 0h Flag for Interrupt 8.1
Reset type: SYSRSn

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3.16.14.19 PIEIER9 Register (Offset = 12h) [Reset = 0h]

PIEIER9 is shown in Figure 3-324 and described in Table 3-346.
Return to the Summary Table.
Interrupt Group 9 Enable Register
These register bits individually enable an interrupt within a group. They behave very much like the bits in the
CPU interrupt enable register (IER).
Setting a bit to 1 allows the corresponding interrupt to propagate to the CPU.
Setting a bit to 0 prevents the corresponding interrupt from propagating. Note that a peripheral interrupt signal
can still set the PIEIFR bit for the disabled interrupt.
Figure 3-324. PIEIER9 Register
15 14 13 12 11 10 9 8
INTx16 INTx15 INTx14 INTx13 INTx12 INTx11 INTx10 INTx9
R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h

7 6 5 4 3 2 1 0
INTx8 INTx7 INTx6 INTx5 INTx4 INTx3 INTx2 INTx1
R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h

Table 3-346. PIEIER9 Register Field Descriptions

Bit Field Type Reset Description
15 INTx16 R/W 0h Enable for Interrupt 9.16
Reset type: SYSRSn
14 INTx15 R/W 0h Enable for Interrupt 9.15
Reset type: SYSRSn
13 INTx14 R/W 0h Enable for Interrupt 9.14
Reset type: SYSRSn
12 INTx13 R/W 0h Enable for Interrupt 9.13
Reset type: SYSRSn
11 INTx12 R/W 0h Enable for Interrupt 9.12
Reset type: SYSRSn
10 INTx11 R/W 0h Enable for Interrupt 9.11
Reset type: SYSRSn
9 INTx10 R/W 0h Enable for Interrupt 9.10
Reset type: SYSRSn
8 INTx9 R/W 0h Enable for Interrupt 9.9
Reset type: SYSRSn
7 INTx8 R/W 0h Enable for Interrupt 9.8
Reset type: SYSRSn
6 INTx7 R/W 0h Enable for Interrupt 9.7
Reset type: SYSRSn
5 INTx6 R/W 0h Enable for Interrupt 9.6
Reset type: SYSRSn
4 INTx5 R/W 0h Enable for Interrupt 9.5
Reset type: SYSRSn
3 INTx4 R/W 0h Enable for Interrupt 9.4
Reset type: SYSRSn
2 INTx3 R/W 0h Enable for Interrupt 9.3
Reset type: SYSRSn
1 INTx2 R/W 0h Enable for Interrupt 9.2
Reset type: SYSRSn
0 INTx1 R/W 0h Enable for Interrupt 9.1
Reset type: SYSRSn

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3.16.14.20 PIEIFR9 Register (Offset = 13h) [Reset = 0h]

PIEIFR9 is shown in Figure 3-325 and described in Table 3-347.
Return to the Summary Table.
Interrupt Group 9 Flag Register
These register bits indicate whether each interrupt in the group is currently pending. They behave very much like
the bits in the CPU interrupt flag register (IFR).
When a peripheral sends an interrupt, the corresponding bit is set. This bit is cleared when the interrupt
propagates to the CPU, at which point PIEACK is set.
NOTE: PIE IFR flags can be written to create software interrupts.
The IFR flag will be cleared on a write of zero. Hence, when the intent is to fire an interrupt it may cause
inadvertent cancellation of other interrupts. It is recommended to use this only for testing or with extreme caution
in the application code. Reading the PIE IFR registers is safe.
Figure 3-325. PIEIFR9 Register
15 14 13 12 11 10 9 8
INTx16 INTx15 INTx14 INTx13 INTx12 INTx11 INTx10 INTx9
R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h

7 6 5 4 3 2 1 0
INTx8 INTx7 INTx6 INTx5 INTx4 INTx3 INTx2 INTx1
R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h

Table 3-347. PIEIFR9 Register Field Descriptions

Bit Field Type Reset Description
15 INTx16 R/W 0h Flag for Interrupt 9.16
Reset type: SYSRSn
14 INTx15 R/W 0h Flag for Interrupt 9.15
Reset type: SYSRSn
13 INTx14 R/W 0h Flag for Interrupt 9.14
Reset type: SYSRSn
12 INTx13 R/W 0h Flag for Interrupt 9.13
Reset type: SYSRSn
11 INTx12 R/W 0h Flag for Interrupt 9.12
Reset type: SYSRSn
10 INTx11 R/W 0h Flag for Interrupt 9.11
Reset type: SYSRSn
9 INTx10 R/W 0h Flag for Interrupt 9.10
Reset type: SYSRSn
8 INTx9 R/W 0h Flag for Interrupt 9.9
Reset type: SYSRSn
7 INTx8 R/W 0h Flag for Interrupt 9.8
Reset type: SYSRSn
6 INTx7 R/W 0h Flag for Interrupt 9.7
Reset type: SYSRSn
5 INTx6 R/W 0h Flag for Interrupt 9.6
Reset type: SYSRSn
4 INTx5 R/W 0h Flag for Interrupt 9.5
Reset type: SYSRSn
3 INTx4 R/W 0h Flag for Interrupt 9.4
Reset type: SYSRSn
2 INTx3 R/W 0h Flag for Interrupt 9.3
Reset type: SYSRSn
1 INTx2 R/W 0h Flag for Interrupt 9.2
Reset type: SYSRSn

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Table 3-347. PIEIFR9 Register Field Descriptions (continued)

Bit Field Type Reset Description
0 INTx1 R/W 0h Flag for Interrupt 9.1
Reset type: SYSRSn

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3.16.14.21 PIEIER10 Register (Offset = 14h) [Reset = 0h]

PIEIER10 is shown in Figure 3-326 and described in Table 3-348.
Return to the Summary Table.
Interrupt Group 10 Enable Register
These register bits individually enable an interrupt within a group. They behave very much like the bits in the
CPU interrupt enable register (IER).
Setting a bit to 1 allows the corresponding interrupt to propagate to the CPU.
Setting a bit to 0 prevents the corresponding interrupt from propagating. Note that a peripheral interrupt signal
can still set the PIEIFR bit for the disabled interrupt.
Figure 3-326. PIEIER10 Register
15 14 13 12 11 10 9 8
INTx16 INTx15 INTx14 INTx13 INTx12 INTx11 INTx10 INTx9
R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h

7 6 5 4 3 2 1 0
INTx8 INTx7 INTx6 INTx5 INTx4 INTx3 INTx2 INTx1
R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h

Table 3-348. PIEIER10 Register Field Descriptions

Bit Field Type Reset Description
15 INTx16 R/W 0h Enable for Interrupt 10.16
Reset type: SYSRSn
14 INTx15 R/W 0h Enable for Interrupt 10.15
Reset type: SYSRSn
13 INTx14 R/W 0h Enable for Interrupt 10.14
Reset type: SYSRSn
12 INTx13 R/W 0h Enable for Interrupt 10.13
Reset type: SYSRSn
11 INTx12 R/W 0h Enable for Interrupt 10.12
Reset type: SYSRSn
10 INTx11 R/W 0h Enable for Interrupt 10.11
Reset type: SYSRSn
9 INTx10 R/W 0h Enable for Interrupt 10.10
Reset type: SYSRSn
8 INTx9 R/W 0h Enable for Interrupt 10.9
Reset type: SYSRSn
7 INTx8 R/W 0h Enable for Interrupt 10.8
Reset type: SYSRSn
6 INTx7 R/W 0h Enable for Interrupt 10.7
Reset type: SYSRSn
5 INTx6 R/W 0h Enable for Interrupt 10.6
Reset type: SYSRSn
4 INTx5 R/W 0h Enable for Interrupt 10.5
Reset type: SYSRSn
3 INTx4 R/W 0h Enable for Interrupt 10.4
Reset type: SYSRSn
2 INTx3 R/W 0h Enable for Interrupt 10.3
Reset type: SYSRSn
1 INTx2 R/W 0h Enable for Interrupt 10.2
Reset type: SYSRSn
0 INTx1 R/W 0h Enable for Interrupt 10.1
Reset type: SYSRSn

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3.16.14.22 PIEIFR10 Register (Offset = 15h) [Reset = 0h]

PIEIFR10 is shown in Figure 3-327 and described in Table 3-349.
Return to the Summary Table.
Interrupt Group 10 Flag Register
These register bits indicate whether each interrupt in the group is currently pending. They behave very much like
the bits in the CPU interrupt flag register (IFR).
When a peripheral sends an interrupt, the corresponding bit is set. This bit is cleared when the interrupt
propagates to the CPU, at which point PIEACK is set.
NOTE: PIE IFR flags can be written to create software interrupts.
The IFR flag will be cleared on a write of zero. Hence, when the intent is to fire an interrupt it may cause
inadvertent cancellation of other interrupts. It is recommended to use this only for testing or with extreme caution
in the application code. Reading the PIE IFR registers is safe.
Figure 3-327. PIEIFR10 Register
15 14 13 12 11 10 9 8
INTx16 INTx15 INTx14 INTx13 INTx12 INTx11 INTx10 INTx9
R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h

7 6 5 4 3 2 1 0
INTx8 INTx7 INTx6 INTx5 INTx4 INTx3 INTx2 INTx1
R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h

Table 3-349. PIEIFR10 Register Field Descriptions

Bit Field Type Reset Description
15 INTx16 R/W 0h Flag for Interrupt 10.16
Reset type: SYSRSn
14 INTx15 R/W 0h Flag for Interrupt 10.15
Reset type: SYSRSn
13 INTx14 R/W 0h Flag for Interrupt 10.14
Reset type: SYSRSn
12 INTx13 R/W 0h Flag for Interrupt 10.13
Reset type: SYSRSn
11 INTx12 R/W 0h Flag for Interrupt 10.12
Reset type: SYSRSn
10 INTx11 R/W 0h Flag for Interrupt 10.11
Reset type: SYSRSn
9 INTx10 R/W 0h Flag for Interrupt 10.10
Reset type: SYSRSn
8 INTx9 R/W 0h Flag for Interrupt 10.9
Reset type: SYSRSn
7 INTx8 R/W 0h Flag for Interrupt 10.8
Reset type: SYSRSn
6 INTx7 R/W 0h Flag for Interrupt 10.7
Reset type: SYSRSn
5 INTx6 R/W 0h Flag for Interrupt 10.6
Reset type: SYSRSn
4 INTx5 R/W 0h Flag for Interrupt 10.5
Reset type: SYSRSn
3 INTx4 R/W 0h Flag for Interrupt 10.4
Reset type: SYSRSn
2 INTx3 R/W 0h Flag for Interrupt 10.3
Reset type: SYSRSn
1 INTx2 R/W 0h Flag for Interrupt 10.2
Reset type: SYSRSn

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Table 3-349. PIEIFR10 Register Field Descriptions (continued)

Bit Field Type Reset Description
0 INTx1 R/W 0h Flag for Interrupt 10.1
Reset type: SYSRSn

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3.16.14.23 PIEIER11 Register (Offset = 16h) [Reset = 0h]

PIEIER11 is shown in Figure 3-328 and described in Table 3-350.
Return to the Summary Table.
Interrupt Group 11 Enable Register
These register bits individually enable an interrupt within a group. They behave very much like the bits in the
CPU interrupt enable register (IER).
Setting a bit to 1 allows the corresponding interrupt to propagate to the CPU.
Setting a bit to 0 prevents the corresponding interrupt from propagating. Note that a peripheral interrupt signal
can still set the PIEIFR bit for the disabled interrupt.
Figure 3-328. PIEIER11 Register
15 14 13 12 11 10 9 8
INTx16 INTx15 INTx14 INTx13 INTx12 INTx11 INTx10 INTx9
R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h

7 6 5 4 3 2 1 0
INTx8 INTx7 INTx6 INTx5 INTx4 INTx3 INTx2 INTx1
R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h

Table 3-350. PIEIER11 Register Field Descriptions

Bit Field Type Reset Description
15 INTx16 R/W 0h Enable for Interrupt 11.16
Reset type: SYSRSn
14 INTx15 R/W 0h Enable for Interrupt 11.15
Reset type: SYSRSn
13 INTx14 R/W 0h Enable for Interrupt 11.14
Reset type: SYSRSn
12 INTx13 R/W 0h Enable for Interrupt 11.13
Reset type: SYSRSn
11 INTx12 R/W 0h Enable for Interrupt 11.12
Reset type: SYSRSn
10 INTx11 R/W 0h Enable for Interrupt 11.11
Reset type: SYSRSn
9 INTx10 R/W 0h Enable for Interrupt 11.10
Reset type: SYSRSn
8 INTx9 R/W 0h Enable for Interrupt 11.9
Reset type: SYSRSn
7 INTx8 R/W 0h Enable for Interrupt 11.8
Reset type: SYSRSn
6 INTx7 R/W 0h Enable for Interrupt 11.7
Reset type: SYSRSn
5 INTx6 R/W 0h Enable for Interrupt 11.6
Reset type: SYSRSn
4 INTx5 R/W 0h Enable for Interrupt 11.5
Reset type: SYSRSn
3 INTx4 R/W 0h Enable for Interrupt 11.4
Reset type: SYSRSn
2 INTx3 R/W 0h Enable for Interrupt 11.3
Reset type: SYSRSn
1 INTx2 R/W 0h Enable for Interrupt 11.2
Reset type: SYSRSn
0 INTx1 R/W 0h Enable for Interrupt 11.1
Reset type: SYSRSn

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3.16.14.24 PIEIFR11 Register (Offset = 17h) [Reset = 0h]

PIEIFR11 is shown in Figure 3-329 and described in Table 3-351.
Return to the Summary Table.
Interrupt Group 11 Flag Register
These register bits indicate whether each interrupt in the group is currently pending. They behave very much like
the bits in the CPU interrupt flag register (IFR).
When a peripheral sends an interrupt, the corresponding bit is set. This bit is cleared when the interrupt
propagates to the CPU, at which point PIEACK is set.
NOTE: PIE IFR flags can be written to create software interrupts.
The IFR flag will be cleared on a write of zero. Hence, when the intent is to fire an interrupt it may cause
inadvertent cancellation of other interrupts. It is recommended to use this only for testing or with extreme caution
in the application code. Reading the PIE IFR registers is safe.
Figure 3-329. PIEIFR11 Register
15 14 13 12 11 10 9 8
INTx16 INTx15 INTx14 INTx13 INTx12 INTx11 INTx10 INTx9
R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h

7 6 5 4 3 2 1 0
INTx8 INTx7 INTx6 INTx5 INTx4 INTx3 INTx2 INTx1
R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h

Table 3-351. PIEIFR11 Register Field Descriptions

Bit Field Type Reset Description
15 INTx16 R/W 0h Flag for Interrupt 11.16
Reset type: SYSRSn
14 INTx15 R/W 0h Flag for Interrupt 11.15
Reset type: SYSRSn
13 INTx14 R/W 0h Flag for Interrupt 11.14
Reset type: SYSRSn
12 INTx13 R/W 0h Flag for Interrupt 11.13
Reset type: SYSRSn
11 INTx12 R/W 0h Flag for Interrupt 11.12
Reset type: SYSRSn
10 INTx11 R/W 0h Flag for Interrupt 11.11
Reset type: SYSRSn
9 INTx10 R/W 0h Flag for Interrupt 11.10
Reset type: SYSRSn
8 INTx9 R/W 0h Flag for Interrupt 11.9
Reset type: SYSRSn
7 INTx8 R/W 0h Flag for Interrupt 11.8
Reset type: SYSRSn
6 INTx7 R/W 0h Flag for Interrupt 11.7
Reset type: SYSRSn
5 INTx6 R/W 0h Flag for Interrupt 11.6
Reset type: SYSRSn
4 INTx5 R/W 0h Flag for Interrupt 11.5
Reset type: SYSRSn
3 INTx4 R/W 0h Flag for Interrupt 11.4
Reset type: SYSRSn
2 INTx3 R/W 0h Flag for Interrupt 11.3
Reset type: SYSRSn
1 INTx2 R/W 0h Flag for Interrupt 11.2
Reset type: SYSRSn

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Table 3-351. PIEIFR11 Register Field Descriptions (continued)

Bit Field Type Reset Description
0 INTx1 R/W 0h Flag for Interrupt 11.1
Reset type: SYSRSn

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3.16.14.25 PIEIER12 Register (Offset = 18h) [Reset = 0h]

PIEIER12 is shown in Figure 3-330 and described in Table 3-352.
Return to the Summary Table.
Interrupt Group 12 Enable Register
These register bits individually enable an interrupt within a group. They behave very much like the bits in the
CPU interrupt enable register (IER).
Setting a bit to 1 allows the corresponding interrupt to propagate to the CPU.
Setting a bit to 0 prevents the corresponding interrupt from propagating. Note that a peripheral interrupt signal
can still set the PIEIFR bit for the disabled interrupt.
Figure 3-330. PIEIER12 Register
15 14 13 12 11 10 9 8
INTx16 INTx15 INTx14 INTx13 INTx12 INTx11 INTx10 INTx9
R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h

7 6 5 4 3 2 1 0
INTx8 INTx7 INTx6 INTx5 INTx4 INTx3 INTx2 INTx1
R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h

Table 3-352. PIEIER12 Register Field Descriptions

Bit Field Type Reset Description
15 INTx16 R/W 0h Enable for Interrupt 12.16
Reset type: SYSRSn
14 INTx15 R/W 0h Enable for Interrupt 12.15
Reset type: SYSRSn
13 INTx14 R/W 0h Enable for Interrupt 12.14
Reset type: SYSRSn
12 INTx13 R/W 0h Enable for Interrupt 12.13
Reset type: SYSRSn
11 INTx12 R/W 0h Enable for Interrupt 12.12
Reset type: SYSRSn
10 INTx11 R/W 0h Enable for Interrupt 12.11
Reset type: SYSRSn
9 INTx10 R/W 0h Enable for Interrupt 12.10
Reset type: SYSRSn
8 INTx9 R/W 0h Enable for Interrupt 12.9
Reset type: SYSRSn
7 INTx8 R/W 0h Enable for Interrupt 12.8
Reset type: SYSRSn
6 INTx7 R/W 0h Enable for Interrupt 12.7
Reset type: SYSRSn
5 INTx6 R/W 0h Enable for Interrupt 12.6
Reset type: SYSRSn
4 INTx5 R/W 0h Enable for Interrupt 12.5
Reset type: SYSRSn
3 INTx4 R/W 0h Enable for Interrupt 12.4
Reset type: SYSRSn
2 INTx3 R/W 0h Enable for Interrupt 12.3
Reset type: SYSRSn
1 INTx2 R/W 0h Enable for Interrupt 12.2
Reset type: SYSRSn
0 INTx1 R/W 0h Enable for Interrupt 12.1
Reset type: SYSRSn

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3.16.14.26 PIEIFR12 Register (Offset = 19h) [Reset = 0h]

PIEIFR12 is shown in Figure 3-331 and described in Table 3-353.
Return to the Summary Table.
Interrupt Group 12 Flag Register
These register bits indicate whether each interrupt in the group is currently pending. They behave very much like
the bits in the CPU interrupt flag register (IFR).
When a peripheral sends an interrupt, the corresponding bit is set. This bit is cleared when the interrupt
propagates to the CPU, at which point PIEACK is set.
NOTE: PIE IFR flags can be written to create software interrupts.
The IFR flag will be cleared on a write of zero. Hence, when the intent is to fire an interrupt it may cause
inadvertent cancellation of other interrupts. It is recommended to use this only for testing or with extreme caution
in the application code. Reading the PIE IFR registers is safe.
Figure 3-331. PIEIFR12 Register
15 14 13 12 11 10 9 8
INTx16 INTx15 INTx14 INTx13 INTx12 INTx11 INTx10 INTx9
R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h

7 6 5 4 3 2 1 0
INTx8 INTx7 INTx6 INTx5 INTx4 INTx3 INTx2 INTx1
R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h

Table 3-353. PIEIFR12 Register Field Descriptions

Bit Field Type Reset Description
15 INTx16 R/W 0h Flag for Interrupt 12.16
Reset type: SYSRSn
14 INTx15 R/W 0h Flag for Interrupt 12.15
Reset type: SYSRSn
13 INTx14 R/W 0h Flag for Interrupt 12.14
Reset type: SYSRSn
12 INTx13 R/W 0h Flag for Interrupt 12.13
Reset type: SYSRSn
11 INTx12 R/W 0h Flag for Interrupt 12.12
Reset type: SYSRSn
10 INTx11 R/W 0h Flag for Interrupt 12.11
Reset type: SYSRSn
9 INTx10 R/W 0h Flag for Interrupt 12.10
Reset type: SYSRSn
8 INTx9 R/W 0h Flag for Interrupt 12.9
Reset type: SYSRSn
7 INTx8 R/W 0h Flag for Interrupt 12.8
Reset type: SYSRSn
6 INTx7 R/W 0h Flag for Interrupt 12.7
Reset type: SYSRSn
5 INTx6 R/W 0h Flag for Interrupt 12.6
Reset type: SYSRSn
4 INTx5 R/W 0h Flag for Interrupt 12.5
Reset type: SYSRSn
3 INTx4 R/W 0h Flag for Interrupt 12.4
Reset type: SYSRSn
2 INTx3 R/W 0h Flag for Interrupt 12.3
Reset type: SYSRSn
1 INTx2 R/W 0h Flag for Interrupt 12.2
Reset type: SYSRSn

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Table 3-353. PIEIFR12 Register Field Descriptions (continued)

Bit Field Type Reset Description
0 INTx1 R/W 0h Flag for Interrupt 12.1
Reset type: SYSRSn

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3.16.15 ROM_PREFETCH_REGS Registers

Table 3-354 lists the memory-mapped registers for the ROM_PREFETCH_REGS registers. All register offset
addresses not listed in Table 3-354 should be considered as reserved locations and the register contents should
not be modified.
Table 3-354. ROM_PREFETCH_REGS Registers
Offset Acronym Register Name Write Protection Section
0h ROMPREFETCH ROM Prefetch Configuration Register EALLOW Go

Complex bit access types are encoded to fit into small table cells. Table 3-355 shows the codes that are used for
access types in this section.
Table 3-355. ROM_PREFETCH_REGS Access Type
Codes
Access Type Code Description
Read Type
R R Read
Write Type
W W Write
Reset or Default Value
-n Value after reset or the default
value
Register Array Variables
i,j,k,l,m,n When these variables are used in
a register name, an offset, or an
address, they refer to the value of
a register array where the register
is part of a group of repeating
registers. The register groups
form a hierarchical structure and
the array is represented with a
formula.
y When this variable is used in a
register name, an offset, or an
address it refers to the value of
a register array.

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3.16.15.1 ROMPREFETCH Register (Offset = 0h) [Reset = 1h]

ROMPREFETCH is shown in Figure 3-332 and described in Table 3-356.
Return to the Summary Table.
ROM Prefetch Configuration Register
Figure 3-332. ROMPREFETCH Register
31 30 29 28 27 26 25 24
RESERVED
R-0h

23 22 21 20 19 18 17 16
RESERVED
R-0h

15 14 13 12 11 10 9 8
RESERVED
R-0h

7 6 5 4 3 2 1 0
RESERVED PFENABLE
R-0h R/W-1h

Table 3-356. ROMPREFETCH Register Field Descriptions

Bit Field Type Reset Description
31-16 RESERVED R 0h Reserved
15-1 RESERVED R 0h Reserved
0 PFENABLE R/W 1h 0: Prefetch is disabled for secure ROM and boot ROM.
1: Prefetch is enabled for secure ROM and boot ROM.
Reset type: SYSRSn

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3.16.16 ROM_WAIT_STATE_REGS Registers

Table 3-357 lists the memory-mapped registers for the ROM_WAIT_STATE_REGS registers. All register offset
addresses not listed in Table 3-357 should be considered as reserved locations and the register contents should
not be modified.
Table 3-357. ROM_WAIT_STATE_REGS Registers
Offset Acronym Register Name Write Protection Section
0h ROMWAITSTATE ROM Wait State Configuration Register EALLOW Go

Complex bit access types are encoded to fit into small table cells. Table 3-358 shows the codes that are used for
access types in this section.
Table 3-358. ROM_WAIT_STATE_REGS Access Type
Codes
Access Type Code Description
Read Type
R R Read
Write Type
W W Write
Reset or Default Value
-n Value after reset or the default
value
Register Array Variables
i,j,k,l,m,n When these variables are used in
a register name, an offset, or an
address, they refer to the value of
a register array where the register
is part of a group of repeating
registers. The register groups
form a hierarchical structure and
the array is represented with a
formula.
y When this variable is used in a
register name, an offset, or an
address it refers to the value of
a register array.

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3.16.16.1 ROMWAITSTATE Register (Offset = 0h) [Reset = 0h]

ROMWAITSTATE is shown in Figure 3-333 and described in Table 3-359.
Return to the Summary Table.
ROM Wait State Configuration Register
Figure 3-333. ROMWAITSTATE Register
31 30 29 28 27 26 25 24
RESERVED
R-0h

23 22 21 20 19 18 17 16
RESERVED
R-0h

15 14 13 12 11 10 9 8
RESERVED
R-0h

7 6 5 4 3 2 1 0
RESERVED WSDISABLE
R-0h R/W-0h

Table 3-359. ROMWAITSTATE Register Field Descriptions

Bit Field Type Reset Description
31-16 RESERVED R 0h Reserved
15-1 RESERVED R 0h Reserved
0 WSDISABLE R/W 0h 0: ROM Wait State is enabled. CPU accesses to secure ROM and
boot ROM are are 1-wait.
1: ROM Wait State is disabled. CPU accesses to secure ROM and
boot ROM are 0-wait.
Reset type: SYSRSn

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3.16.17 SYNC_SOC_REGS Registers

Table 3-360 lists the memory-mapped registers for the SYNC_SOC_REGS registers. All register offset
addresses not listed in Table 3-360 should be considered as reserved locations and the register contents should
not be modified.
Table 3-360. SYNC_SOC_REGS Registers
Offset Acronym Register Name Write Protection Section
0h SYNCSELECT Sync Input and Output Select Register EALLOW Go
2h ADCSOCOUTSELECT External ADC (Off Chip) SOC Select Register EALLOW Go
4h SYNCSOCLOCK SYNCSEL and EXTADCSOC Select Lock register EALLOW Go

Complex bit access types are encoded to fit into small table cells. Table 3-361 shows the codes that are used for
access types in this section.
Table 3-361. SYNC_SOC_REGS Access Type Codes
Access Type Code Description
Read Type
R R Read
R-0 R Read
-0 Returns 0s
Write Type
W W Write
WSonce W Write
Sonce Set once
Reset or Default Value
-n Value after reset or the default
value
Register Array Variables
i,j,k,l,m,n When these variables are used in
a register name, an offset, or an
address, they refer to the value of
a register array where the register
is part of a group of repeating
registers. The register groups
form a hierarchical structure and
the array is represented with a
formula.
y When this variable is used in a
register name, an offset, or an
address it refers to the value of
a register array.

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3.16.17.1 SYNCSELECT Register (Offset = 0h) [Reset = 0h]

SYNCSELECT is shown in Figure 3-334 and described in Table 3-362.
Return to the Summary Table.
Sync Input and Output Select Register
Figure 3-334. SYNCSELECT Register
31 30 29 28 27 26 25 24
RESERVED SYNCOUT
R/W-0h R/W-0h

23 22 21 20 19 18 17 16
RESERVED RESERVED
R/W-0h R/W-0h

15 14 13 12 11 10 9 8
RESERVED RESERVED RESERVED RESERVED
R-0-0h R/W-0h R/W-0h R/W-0h

7 6 5 4 3 2 1 0
RESERVED RESERVED RESERVED
R/W-0h R/W-0h R/W-0h

Table 3-362. SYNCSELECT Register Field Descriptions

Bit Field Type Reset Description
31-29 RESERVED R/W 0h Reserved

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Table 3-362. SYNCSELECT Register Field Descriptions (continued)

Bit Field Type Reset Description
28-24 SYNCOUT R/W 0h Select Syncout Source:
00000: EPWM1SYNCOUT selected to drive the SYNCOUT pin.
00001: EPWM2SYNCOUT selected to drive the SYNCOUT pin.
00010: EPWM3SYNCOUT selected to drive the SYNCOUT pin.
00011: EPWM4SYNCOUT selected to drive the SYNCOUT pin.
00100: EPWM5SYNCOUT selected to drive the SYNCOUT pin.
00101: EPWM6SYNCOUT selected to drive the SYNCOUT pin.
00110: EPWM7SYNCOUT selected to drive the SYNCOUT pin.
00111: EPWM8SYNCOUT selected to drive the SYNCOUT pin.
01000: EPWM9SYNCOUT selected to drive the SYNCOUT pin.
01001: EPWM10SYNCOUT selected to drive the SYNCOUT pin.
01010: EPWM11SYNCOUT selected to drive the SYNCOUT pin.
01011: EPWM12SYNCOUT selected to drive the SYNCOUT pin.
01100: EPWM13SYNCOUT selected to drive the SYNCOUT pin.
01101: EPWM14SYNCOUT selected to drive the SYNCOUT pin.
01110: EPWM15SYNCOUT selected to drive the SYNCOUT pin.
01111: EPWM16SYNCOUT selected to drive the SYNCOUT pin.
10000: Reserved
10001: Reserved
10010: Reserved
10011: Reserved
10100: Reserved
10101: Reserved
10110: Reserved
10111: Reserved
11000: ECAP1SYNCOUT selected to drive the SYNCOUT pin.
11001: ECAP2SYNCOUT selected to drive the SYNCOUT pin.
11010: ECAP3SYNCOUT selected to drive the SYNCOUT pin.
11011: ECAP4SYNCOUT selected to drive the SYNCOUT pin.
11100: ECAP5SYNCOUT selected to drive the SYNCOUT pin.
11101: ECAP6SYNCOUT selected to drive the SYNCOUT pin.
11110: ECAP7SYNCOUT selected to drive the SYNCOUT pin.
11111: Reserved
Notes:
[1] Reserved position defaults to 00 selection
Reset type: CPU1.SYSRSn
23-20 RESERVED R/W 0h Reserved
19-16 RESERVED R/W 0h Reserved
15 RESERVED R-0 0h Reserved
14-12 RESERVED R/W 0h Reserved
11-9 RESERVED R/W 0h Reserved
8-6 RESERVED R/W 0h Reserved
5-3 RESERVED R/W 0h Reserved
2-0 RESERVED R/W 0h Reserved

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3.16.17.2 ADCSOCOUTSELECT Register (Offset = 2h) [Reset = 0h]

ADCSOCOUTSELECT is shown in Figure 3-335 and described in Table 3-363.
Return to the Summary Table.
External ADC (Off Chip) SOC Select Register
Figure 3-335. ADCSOCOUTSELECT Register
31 30 29 28 27 26 25 24
PWM16SOCBE PWM15SOCBE PWM14SOCBE PWM13SOCBE PWM12SOCBE PWM11SOCBE PWM10SOCBE PWM9SOCBEN
N N N N N N N
R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h

23 22 21 20 19 18 17 16
PWM8SOCBEN PWM7SOCBEN PWM6SOCBEN PWM5SOCBEN PWM4SOCBEN PWM3SOCBEN PWM2SOCBEN PWM1SOCBEN
R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h

15 14 13 12 11 10 9 8
PWM16SOCAE PWM15SOCAE PWM14SOCAE PWM13SOCAE PWM12SOCAE PWM11SOCAE PWM10SOCAE PWM9SOCAEN
N N N N N N N
R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h

7 6 5 4 3 2 1 0
PWM8SOCAEN PWM7SOCAEN PWM6SOCAEN PWM5SOCAEN PWM4SOCAEN PWM3SOCAEN PWM2SOCAEN PWM1SOCAEN
R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h

Table 3-363. ADCSOCOUTSELECT Register Field Descriptions

Bit Field Type Reset Description
31 PWM16SOCBEN R/W 0h ADCSOCBOn source select:
0: Respective EPWM SOCB output is not selected
1: Respective EPWM SOCB output is selected
Reset type: CPU1.SYSRSn
30 PWM15SOCBEN R/W 0h ADCSOCBOn source select:
0: Respective EPWM SOCB output is not selected
1: Respective EPWM SOCB output is selected
Reset type: CPU1.SYSRSn
29 PWM14SOCBEN R/W 0h ADCSOCBOn source select:
0: Respective EPWM SOCB output is not selected
1: Respective EPWM SOCB output is selected
Reset type: CPU1.SYSRSn
28 PWM13SOCBEN R/W 0h ADCSOCBOn source select:
0: Respective EPWM SOCB output is not selected
1: Respective EPWM SOCB output is selected
Reset type: CPU1.SYSRSn
27 PWM12SOCBEN R/W 0h ADCSOCBOn source select:
0: Respective EPWM SOCB output is not selected
1: Respective EPWM SOCB output is selected
Reset type: CPU1.SYSRSn
26 PWM11SOCBEN R/W 0h ADCSOCBOn source select:
0: Respective EPWM SOCB output is not selected
1: Respective EPWM SOCB output is selected
Reset type: CPU1.SYSRSn
25 PWM10SOCBEN R/W 0h ADCSOCBOn source select:
0: Respective EPWM SOCB output is not selected
1: Respective EPWM SOCB output is selected
Reset type: CPU1.SYSRSn

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Table 3-363. ADCSOCOUTSELECT Register Field Descriptions (continued)

Bit Field Type Reset Description
24 PWM9SOCBEN R/W 0h ADCSOCBOn source select:
0: Respective EPWM SOCB output is not selected
1: Respective EPWM SOCB output is selected
Reset type: CPU1.SYSRSn
23 PWM8SOCBEN R/W 0h ADCSOCBOn source select:
0: Respective EPWM SOCB output is not selected
1: Respective EPWM SOCB output is selected
Reset type: CPU1.SYSRSn
22 PWM7SOCBEN R/W 0h ADCSOCBOn source select:
0: Respective EPWM SOCB output is not selected
1: Respective EPWM SOCB output is selected
Reset type: CPU1.SYSRSn
21 PWM6SOCBEN R/W 0h ADCSOCBOn source select:
0: Respective EPWM SOCB output is not selected
1: Respective EPWM SOCB output is selected
Reset type: CPU1.SYSRSn
20 PWM5SOCBEN R/W 0h ADCSOCBOn source select:
0: Respective EPWM SOCB output is not selected
1: Respective EPWM SOCB output is selected
Reset type: CPU1.SYSRSn
19 PWM4SOCBEN R/W 0h ADCSOCBOn source select:
0: Respective EPWM SOCB output is not selected
1: Respective EPWM SOCB output is selected
Reset type: CPU1.SYSRSn
18 PWM3SOCBEN R/W 0h ADCSOCBOn source select:
0: Respective EPWM SOCB output is not selected
1: Respective EPWM SOCB output is selected
Reset type: CPU1.SYSRSn
17 PWM2SOCBEN R/W 0h ADCSOCBOn source select:
0: Respective EPWM SOCB output is not selected
1: Respective EPWM SOCB output is selected
Reset type: CPU1.SYSRSn
16 PWM1SOCBEN R/W 0h ADCSOCBOn source select:
0: Respective EPWM SOCB output is not selected
1: Respective EPWM SOCB output is selected
Reset type: CPU1.SYSRSn
15 PWM16SOCAEN R/W 0h ADCSOCAOn source select:
0: Respective EPWM SOCA output is not selected
1: Respective EPWM SOCA output is selected
Reset type: CPU1.SYSRSn
14 PWM15SOCAEN R/W 0h ADCSOCAOn source select:
0: Respective EPWM SOCA output is not selected
1: Respective EPWM SOCA output is selected
Reset type: CPU1.SYSRSn
13 PWM14SOCAEN R/W 0h ADCSOCAOn source select:
0: Respective EPWM SOCA output is not selected
1: Respective EPWM SOCA output is selected
Reset type: CPU1.SYSRSn
12 PWM13SOCAEN R/W 0h ADCSOCAOn source select:
0: Respective EPWM SOCA output is not selected
1: Respective EPWM SOCA output is selected
Reset type: CPU1.SYSRSn
11 PWM12SOCAEN R/W 0h ADCSOCAOn source select:
0: Respective EPWM SOCA output is not selected
1: Respective EPWM SOCA output is selected
Reset type: CPU1.SYSRSn

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Table 3-363. ADCSOCOUTSELECT Register Field Descriptions (continued)

Bit Field Type Reset Description
10 PWM11SOCAEN R/W 0h ADCSOCAOn source select:
0: Respective EPWM SOCA output is not selected
1: Respective EPWM SOCA output is selected
Reset type: CPU1.SYSRSn
9 PWM10SOCAEN R/W 0h ADCSOCAOn source select:
0: Respective EPWM SOCA output is not selected
1: Respective EPWM SOCA output is selected
Reset type: CPU1.SYSRSn
8 PWM9SOCAEN R/W 0h ADCSOCAOn source select:
0: Respective EPWM SOCA output is not selected
1: Respective EPWM SOCA output is selected
Reset type: CPU1.SYSRSn
7 PWM8SOCAEN R/W 0h ADCSOCAOn source select:
0: Respective EPWM SOCA output is not selected
1: Respective EPWM SOCA output is selected
Reset type: CPU1.SYSRSn
6 PWM7SOCAEN R/W 0h ADCSOCAOn source select:
0: Respective EPWM SOCA output is not selected
1: Respective EPWM SOCA output is selected
Reset type: CPU1.SYSRSn
5 PWM6SOCAEN R/W 0h ADCSOCAOn source select:
0: Respective EPWM SOCA output is not selected
1: Respective EPWM SOCA output is selected
Reset type: CPU1.SYSRSn
4 PWM5SOCAEN R/W 0h ADCSOCAOn source select:
0: Respective EPWM SOCA output is not selected
1: Respective EPWM SOCA output is selected
Reset type: CPU1.SYSRSn
3 PWM4SOCAEN R/W 0h ADCSOCAOn source select:
0: Respective EPWM SOCA output is not selected
1: Respective EPWM SOCA output is selected
Reset type: CPU1.SYSRSn
2 PWM3SOCAEN R/W 0h ADCSOCAOn source select:
0: Respective EPWM SOCA output is not selected
1: Respective EPWM SOCA output is selected
Reset type: CPU1.SYSRSn
1 PWM2SOCAEN R/W 0h ADCSOCAOn source select:
0: Respective EPWM SOCA output is not selected
1: Respective EPWM SOCA output is selected
Reset type: CPU1.SYSRSn
0 PWM1SOCAEN R/W 0h ADCSOCAOn source select:
0: Respective EPWM SOCA output is not selected
1: Respective EPWM SOCA output is selected
Reset type: CPU1.SYSRSn

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3.16.17.3 SYNCSOCLOCK Register (Offset = 4h) [Reset = 0h]

SYNCSOCLOCK is shown in Figure 3-336 and described in Table 3-364.
Return to the Summary Table.
SYNCSEL and EXTADCSOC Select Lock register
Figure 3-336. SYNCSOCLOCK Register
31 30 29 28 27 26 25 24
RESERVED
R-0-0h

23 22 21 20 19 18 17 16
RESERVED
R-0-0h

15 14 13 12 11 10 9 8
RESERVED
R-0-0h

7 6 5 4 3 2 1 0
RESERVED ADCSOCOUTS SYNCSELECT
ELECT
R-0-0h R/WSonce-0h R/WSonce-0h

Table 3-364. SYNCSOCLOCK Register Field Descriptions

Bit Field Type Reset Description
31-16 RESERVED R-0 0h Reserved
15-2 RESERVED R-0 0h Reserved
1 ADCSOCOUTSELECT R/WSonce 0h ADCSOCOUTSELECT Register Lock bit:
0: Respective register is not locked
1: Respective register is locked.
Notes:
[1] Any bit in this register, once set can only be creaed through a
CPU1.SYSRSn. Write of 0 to any bit of this regtister has no effect
[2] The locking mechanism applies to only writes. Reads to the
registers which have LOCK protection are always allowed
Reset type: CPU1.SYSRSn
0 SYNCSELECT R/WSonce 0h SYNCSELECT Register Lock bit:
0: Respective register is not locked
1: Respective register is locked.
Notes:
[1] Any bit in this register, once set can only be creaed through a
CPU1.SYSRSn. Write of 0 to any bit of this regtister has no effect
[2] The locking mechanism applies to only writes. Reads to the
registers which have LOCK protection are always allowed
Reset type: CPU1.SYSRSn

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3.16.18 SYS_STATUS_REGS Registers

Table 3-365 lists the memory-mapped registers for the SYS_STATUS_REGS registers. All register offset
addresses not listed in Table 3-365 should be considered as reserved locations and the register contents should
not be modified.
Table 3-365. SYS_STATUS_REGS Registers
Offset Acronym Register Name Write Protection Section
0h CM_STATUS_INT_FLG Status of interrupts due to multiple sources of Go
Cortex-M4 reset.
2h CM_STATUS_INT_CLR CM_STATUS_INT_FLG clear register Go
4h CM_STATUS_INT_SET CM_STATUS_INT_FLG set register EALLOW Go
6h CM_STATUS_MASK CM_STATUS_MASK register EALLOW Go
10h SYS_ERR_INT_FLG Status of interrupts due to multiple different errors Go
in the system.
12h SYS_ERR_INT_CLR SYS_ERR_INT_FLG clear register Go
14h SYS_ERR_INT_SET SYS_ERR_INT_FLG set register EALLOW Go
16h SYS_ERR_MASK SYS_ERR_MASK register EALLOW Go

Complex bit access types are encoded to fit into small table cells. Table 3-366 shows the codes that are used for
access types in this section.
Table 3-366. SYS_STATUS_REGS Access Type
Codes
Access Type Code Description
Read Type
R R Read
R-0 R Read
-0 Returns 0s
Write Type
W W Write
W1S W Write
1S 1 to set
Reset or Default Value
-n Value after reset or the default
value
Register Array Variables
i,j,k,l,m,n When these variables are used in
a register name, an offset, or an
address, they refer to the value of
a register array where the register
is part of a group of repeating
registers. The register groups
form a hierarchical structure and
the array is represented with a
formula.
y When this variable is used in a
register name, an offset, or an
address it refers to the value of
a register array.

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3.16.18.1 CM_STATUS_INT_FLG Register (Offset = 0h) [Reset = 0h]

CM_STATUS_INT_FLG is shown in Figure 3-337 and described in Table 3-367.
Return to the Summary Table.
Status of interrupts due to multiple sources of Cortex-M4 reset.
Note: This register is present only on CPU1.
Figure 3-337. CM_STATUS_INT_FLG Register
31 30 29 28 27 26 25 24
RESERVED
R-0h

23 22 21 20 19 18 17 16
RESERVED
R-0h

15 14 13 12 11 10 9 8
RESERVED
R-0h

7 6 5 4 3 2 1 0
RESERVED CMVECTRESE CMSYSRESET CMNMIWDRST GINT
T REQ
R-0h R-0h R-0h R-0h R-0h

Table 3-367. CM_STATUS_INT_FLG Register Field Descriptions

Bit Field Type Reset Description
31-4 RESERVED R 0h Reserved
3 CMVECTRESET R 0h 0:CMVECTRESET has not caused a reset of CM
1:CMVECTRESET had caused a reset of CM, an interrupt will be
fired if GINT flag is not set.
Reset type: SYSRSn
2 CMSYSRESETREQ R 0h 0:CMSYSRESETREQ has not caused a reset of CM
1:CMSYSRESETREQ had caused a reset of CM, an interrupt will be
fired if GINT flag is not set.
Reset type: SYSRSn
1 CMNMIWDRST R 0h 0:CMNMIWDRST has not caused a reset of CM
1:CMNMIWDRST had caused a reset of CM, an interrupt will be fired
if GINT flag is not set.
Reset type: SYSRSn
0 GINT R 0h Global Interrupt flag:
0: On any of the flags of CM_STATUS_INT_FLG register being set,
CM_STATUS_INT is pulsed and GINT flag would be set
1: No further interrupts would be fired until GINT flag is cleared
Reset type: SYSRSn

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3.16.18.2 CM_STATUS_INT_CLR Register (Offset = 2h) [Reset = 0h]

CM_STATUS_INT_CLR is shown in Figure 3-338 and described in Table 3-368.
Return to the Summary Table.
CM_STATUS_INT_FLG clear register
Note: This register is present only on CPU1.
Figure 3-338. CM_STATUS_INT_CLR Register
31 30 29 28 27 26 25 24
RESERVED
R-0h

23 22 21 20 19 18 17 16
RESERVED
R-0h

15 14 13 12 11 10 9 8
RESERVED
R-0h

7 6 5 4 3 2 1 0
RESERVED CMVECTRESE CMSYSRESET CMNMIWDRST GINT
T REQ
R-0h R-0/W1S-0h R-0/W1S-0h R-0/W1S-0h R-0/W1S-0h

Table 3-368. CM_STATUS_INT_CLR Register Field Descriptions

Bit Field Type Reset Description
31-4 RESERVED R 0h Reserved
3 CMVECTRESET R-0/W1S 0h 0: No effect
1: CMVECTRESET flag of CM_STATUS_INT_FLG reister will be
cleared.
Reset type: SYSRSn
2 CMSYSRESETREQ R-0/W1S 0h 0: No effect
1: CMSYSRESETREQ flag of CM_STATUS_INT_FLG reister will be
cleared.
Reset type: SYSRSn
1 CMNMIWDRST R-0/W1S 0h 0: No effect
1: CMNMIWDRST flag of CM_STATUS_INT_FLG reister will be
cleared.
Reset type: SYSRSn
0 GINT R-0/W1S 0h 0: No effect
1: GINT flag of CM_STATUS_INT_FLG reister will be cleared.
Reset type: SYSRSn

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3.16.18.3 CM_STATUS_INT_SET Register (Offset = 4h) [Reset = 0h]

CM_STATUS_INT_SET is shown in Figure 3-339 and described in Table 3-369.
Return to the Summary Table.
CM_STATUS_INT_FLG set register
Note: This register is present only on CPU1.
Figure 3-339. CM_STATUS_INT_SET Register
31 30 29 28 27 26 25 24
KEY
R-0/W-0h

23 22 21 20 19 18 17 16
KEY
R-0/W-0h

15 14 13 12 11 10 9 8
RESERVED
R-0h

7 6 5 4 3 2 1 0
RESERVED CMVECTRESE CMSYSRESET CMNMIWDRST RESERVED
T REQ
R-0h R-0/W1S-0h R-0/W1S-0h R-0/W1S-0h R-0h

Table 3-369. CM_STATUS_INT_SET Register Field Descriptions

Bit Field Type Reset Description
31-16 KEY R-0/W 0h A value of 0xa5a5 to this field would enable write to the other bit
fields of this register. Any other value written to KEY field would block
the write to the other fields of this register.
Note: Only a 32 bit write to this register will succeed in updating the
fields of this rigister, provided the correct value written to the KEY
field simultaneously
Reset type: SYSRSn
15-4 RESERVED R 0h Reserved
3 CMVECTRESET R-0/W1S 0h 0: No effect
1: CMVECTRESET flag of CM_STATUS_INT_FLG reister will be set.
Reset type: SYSRSn
2 CMSYSRESETREQ R-0/W1S 0h 0: No effect
1: CMSYSRESETREQ flag of CM_STATUS_INT_FLG reister will be
set.
Reset type: SYSRSn
1 CMNMIWDRST R-0/W1S 0h 0: No effect
1: CMNMIWDRST flag of CM_STATUS_INT_FLG reister will be set.
Reset type: SYSRSn
0 RESERVED R 0h Reserved

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3.16.18.4 CM_STATUS_MASK Register (Offset = 6h) [Reset = 0h]

CM_STATUS_MASK is shown in Figure 3-340 and described in Table 3-370.
Return to the Summary Table.
CM_STATUS_MASK register
Note: This register is present only on CPU1.
Figure 3-340. CM_STATUS_MASK Register
31 30 29 28 27 26 25 24
KEY
R-0/W-0h

23 22 21 20 19 18 17 16
KEY
R-0/W-0h

15 14 13 12 11 10 9 8
RESERVED
R-0h

7 6 5 4 3 2 1 0
RESERVED CMVECTRESE CMSYSRESET CMNMIWDRST RESERVED
T REQ
R-0h R/W-0h R/W-0h R/W-0h R-0h

Table 3-370. CM_STATUS_MASK Register Field Descriptions

Bit Field Type Reset Description
31-16 KEY R-0/W 0h A value of 0xa5a5 to this field would enable write to the other bit
fields of this register. Any other value written to KEY field would block
the write to the other fields of this register.
Note: Only a 32 bit write to this register will succeed in updating the
fields of this rigister, provided the correct value written to the KEY
field simultaneously
Reset type: SYSRSn
15-4 RESERVED R 0h Reserved
3 CMVECTRESET R/W 0h 0: CMVECTRESET flag of CM_STATUS_INT_FLG reister will be set
on a hardware event.
1: CMVECTRESET flag of CM_STATUS_INT_FLG reister will not be
set on a hardware event.
Reset type: SYSRSn
2 CMSYSRESETREQ R/W 0h 0: CMSYSRESETREQ flag of CM_STATUS_INT_FLG reister will be
set on a hardware event.
1: CMSYSRESETREQ flag of CM_STATUS_INT_FLG reister will not
be set on a hardware event.
Reset type: SYSRSn
1 CMNMIWDRST R/W 0h 0: CMNMIWDRST flag of CM_STATUS_INT_FLG reister will be set
on a hardware event.
1: CMNMIWDRST flag of CM_STATUS_INT_FLG reister will not be
set on a hardware event.
Reset type: SYSRSn
0 RESERVED R 0h Reserved

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3.16.18.5 SYS_ERR_INT_FLG Register (Offset = 10h) [Reset = 0h]

SYS_ERR_INT_FLG is shown in Figure 3-341 and described in Table 3-371.
Return to the Summary Table.
Status of interrupts due to multiple different errors in the system.
Figure 3-341. SYS_ERR_INT_FLG Register
31 30 29 28 27 26 25 24
RESERVED
R-0h

23 22 21 20 19 18 17 16
RESERVED
R-0h

15 14 13 12 11 10 9 8
RESERVED DCC2 DCC1
R-0h R-0h R-0h

7 6 5 4 3 2 1 0
DCC0 AUX_PLL_SLIP SYS_PLL_SLIP RAM_ACC_VIO FLASH_CORR RAM_CORREC EMIF_ERR GINT
_NOTSUPPOR _NOTSUPPOR L ECTABLE_ERR TABLE_ERR
TED TED
R-0h R-0h R-0h R-0h R-0h R-0h R-0h R-0h

Table 3-371. SYS_ERR_INT_FLG Register Field Descriptions

Bit Field Type Reset Description
31-10 RESERVED R 0h Reserved
9 DCC2 R 0h 0: DCC2 has not fired an interrupt.
1: DCC2 has fired an interrupt
Reset type: SYSRSn
8 DCC1 R 0h 0: DCC1 has not fired an interrupt.
1: DCC1 has fired an interrupt
Reset type: SYSRSn
7 DCC0 R 0h 0: DCC0 has not fired an interrupt.
1: DCC0 has fired an interrupt
Reset type: SYSRSn
6 AUX_PLL_SLIP_NOTSUP R 0h RESERVED: This bit is reserved and the value read should be
PORTED ignored.
Reset type: SYSRSn
5 SYS_PLL_SLIP_NOTSUP R 0h RESERVED: This bit is reserved and the value read should be
PORTED ignored.
Reset type: SYSRSn
4 RAM_ACC_VIOL R 0h 0: None of the Masters have violated the set protection rules
1: At least one of the master accesses has violated one or more of
the access protection rules
Reset type: SYSRSn
3 FLASH_CORRECTABLE_ R 0h 0: Number of correctable errors detected has not exceeded the set
ERR threshold in FLASH.
1:Number of correctable errors detected has exceeded the set
threshold in FLASH.
Reset type: SYSRSn
2 RAM_CORRECTABLE_E R 0h 0: Number of correctable errors detected has not exceeded the set
RR threshold in any of the RAMs.
1:Number of correctable errors detected has exceeded the set
threshold in atleast one of the RAMs.
Reset type: SYSRSn

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Table 3-371. SYS_ERR_INT_FLG Register Field Descriptions (continued)

Bit Field Type Reset Description
1 EMIF_ERR R 0h 0: EMIF error has not occurred.
1: EMIF error has occurred.
Reset type: SYSRSn
0 GINT R 0h Global Interrupt flag:
0: On any of the flags of SYS_ERR_INT_FLG register being set,
SYS_ERR_INT is pulsed and GINT flag would be set
1: No further interrupts would be fired until GINT flag is cleared
Reset type: SYSRSn

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3.16.18.6 SYS_ERR_INT_CLR Register (Offset = 12h) [Reset = 0h]

SYS_ERR_INT_CLR is shown in Figure 3-342 and described in Table 3-372.
Return to the Summary Table.
SYS_ERR_INT_FLG clear register
Figure 3-342. SYS_ERR_INT_CLR Register
31 30 29 28 27 26 25 24
RESERVED
R-0h

23 22 21 20 19 18 17 16
RESERVED
R-0h

15 14 13 12 11 10 9 8
RESERVED DCC2 DCC1
R-0h R-0/W1S-0h R-0/W1S-0h

7 6 5 4 3 2 1 0
DCC0 AUX_PLL_SLIP SYS_PLL_SLIP RAM_ACC_VIO FLASH_CORR RAM_CORREC EMIF_ERR GINT
_NOTSUPPOR _NOTSUPPOR L ECTABLE_ERR TABLE_ERR
TED TED
R-0/W1S-0h R-0/W1S-0h R-0/W1S-0h R-0/W1S-0h R-0/W1S-0h R-0/W1S-0h R-0/W1S-0h R-0/W1S-0h

Table 3-372. SYS_ERR_INT_CLR Register Field Descriptions

Bit Field Type Reset Description
31-10 RESERVED R 0h Reserved
9 DCC2 R-0/W1S 0h 0: No effect
1: DCC2 flag of SYS_ERR_INT_FLG reister will be cleared.
Reset type: SYSRSn
8 DCC1 R-0/W1S 0h 0: No effect
1: DCC1 flag of SYS_ERR_INT_FLG reister will be cleared.
Reset type: SYSRSn
7 DCC0 R-0/W1S 0h 0: No effect
1: DCC0 flag of SYS_ERR_INT_FLG reister will be cleared.
Reset type: SYSRSn
6 AUX_PLL_SLIP_NOTSUP R-0/W1S 0h RESERVED: This bit is reserved and the value set should always be
PORTED "0"
Reset type: SYSRSn
5 SYS_PLL_SLIP_NOTSUP R-0/W1S 0h RESERVED: This bit is reserved and the value set should always be
PORTED "0"
Reset type: SYSRSn
4 RAM_ACC_VIOL R-0/W1S 0h 0: No effect
1: RAM_ACC_VIOL flag of SYS_ERR_INT_FLG reister will be
cleared.
Reset type: SYSRSn
3 FLASH_CORRECTABLE_ R-0/W1S 0h 0: No effect
ERR 1: FLASH_CORRECTABLE_ERR flag of SYS_ERR_INT_FLG
reister will be cleared.
Reset type: SYSRSn
2 RAM_CORRECTABLE_E R-0/W1S 0h 0: No effect
RR 1: RAM_CORRECTABLE_ERR flag of SYS_ERR_INT_FLG reister
will be cleared.
Reset type: SYSRSn
1 EMIF_ERR R-0/W1S 0h 0: No effect
1: EMIF_ERR flag of SYS_ERR_INT_FLG reister will be cleared.
Reset type: SYSRSn

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Table 3-372. SYS_ERR_INT_CLR Register Field Descriptions (continued)

Bit Field Type Reset Description
0 GINT R-0/W1S 0h 0: No effect
1: GINT flag of SYS_ERR_INT_FLG reister will be cleared.
Reset type: SYSRSn

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3.16.18.7 SYS_ERR_INT_SET Register (Offset = 14h) [Reset = 0h]

SYS_ERR_INT_SET is shown in Figure 3-343 and described in Table 3-373.
Return to the Summary Table.
SYS_ERR_INT_FLG set register
Figure 3-343. SYS_ERR_INT_SET Register
31 30 29 28 27 26 25 24
KEY
R-0/W-0h

23 22 21 20 19 18 17 16
KEY
R-0/W-0h

15 14 13 12 11 10 9 8
RESERVED DCC2 DCC1
R-0h R-0/W1S-0h R-0/W1S-0h

7 6 5 4 3 2 1 0
DCC0 AUX_PLL_SLIP SYS_PLL_SLIP RAM_ACC_VIO FLASH_CORR RAM_CORREC EMIF_ERR RESERVED
_NOTSUPPOR _NOTSUPPOR L ECTABLE_ERR TABLE_ERR
TED TED
R-0/W1S-0h R-0/W1S-0h R-0/W1S-0h R-0/W1S-0h R-0/W1S-0h R-0/W1S-0h R-0/W1S-0h R-0h

Table 3-373. SYS_ERR_INT_SET Register Field Descriptions

Bit Field Type Reset Description
31-16 KEY R-0/W 0h A value of 0xa5a5 to this field would enable write to the other bit
fields of this register. Any other value written to KEY field would block
the write to the other fields of this register.
Note: Only a 32 bit write to this register will succeed in updating the
fields of this rigister, provided the correct value written to the KEY
field simultaneously
Reset type: SYSRSn
15-10 RESERVED R 0h Reserved
9 DCC2 R-0/W1S 0h 0: No effect
1: DCC2 flag of SYS_ERR_INT_FLG reister will be set.
Reset type: SYSRSn
8 DCC1 R-0/W1S 0h 0: No effect
1: DCC1 flag of SYS_ERR_INT_FLG reister will be set.
Reset type: SYSRSn
7 DCC0 R-0/W1S 0h 0: No effect
1: DCC0 flag of SYS_ERR_INT_FLG reister will be set.
Reset type: SYSRSn
6 AUX_PLL_SLIP_NOTSUP R-0/W1S 0h RESERVED: This bit is reserved and the value set should always be
PORTED "0"
Reset type: SYSRSn
5 SYS_PLL_SLIP_NOTSUP R-0/W1S 0h RESERVED: This bit is reserved and the value set should always be
PORTED "0"
Reset type: SYSRSn
4 RAM_ACC_VIOL R-0/W1S 0h 0: No effect
1: RAM_ACC_VIOL flag of SYS_ERR_INT_FLG reister will be set.
Reset type: SYSRSn
3 FLASH_CORRECTABLE_ R-0/W1S 0h 0: No effect
ERR 1: FLASH_CORRECTABLE_ERR flag of SYS_ERR_INT_FLG
reister will be set.
Reset type: SYSRSn

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Table 3-373. SYS_ERR_INT_SET Register Field Descriptions (continued)

Bit Field Type Reset Description
2 RAM_CORRECTABLE_E R-0/W1S 0h 0: No effect
RR 1: RAM_CORRECTABLE_ERR flag of SYS_ERR_INT_FLG reister
will be set.
Reset type: SYSRSn
1 EMIF_ERR R-0/W1S 0h 0: No effect
1: EMIF_ERR flag of SYS_ERR_INT_FLG reister will be set.
Reset type: SYSRSn
0 RESERVED R 0h Reserved

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3.16.18.8 SYS_ERR_MASK Register (Offset = 16h) [Reset = 60h]

SYS_ERR_MASK is shown in Figure 3-344 and described in Table 3-374.
Return to the Summary Table.
SYS_ERR_MASK register
Figure 3-344. SYS_ERR_MASK Register
31 30 29 28 27 26 25 24
KEY
R/W-0h

23 22 21 20 19 18 17 16
KEY
R/W-0h

15 14 13 12 11 10 9 8
RESERVED DCC2 DCC1
R-0h R/W-0h R/W-0h

7 6 5 4 3 2 1 0
DCC0 AUX_PLL_SLIP SYS_PLL_SLIP RAM_ACC_VIO FLASH_CORR RAM_CORREC EMIF_ERR RESERVED
L ECTABLE_ERR TABLE_ERR
R/W-0h R/W-1h R/W-1h R/W-0h R/W-0h R/W-0h R/W-0h R-0h

Table 3-374. SYS_ERR_MASK Register Field Descriptions

Bit Field Type Reset Description
31-16 KEY R/W 0h A value of 0xa5a5 to this field would enable write to the other bit
fields of this register. Any other value written to KEY field would block
the write to the other fields of this register.
Note: Only a 32 bit write to this register will succeed in updating the
fields of this rigister, provided the correct value written to the KEY
field simultaneously
Reset type: SYSRSn
15-10 RESERVED R 0h Reserved
9 DCC2 R/W 0h 0: DCC2 flag of SYS_ERR_INT_FLG reister will be set on a
hardware event.
1: DCC2 flag of SYS_ERR_INT_FLG reister will not be set on a
hardware event.
Reset type: SYSRSn
8 DCC1 R/W 0h 0: DCC1 flag of SYS_ERR_INT_FLG reister will be set on a
hardware event.
1: DCC1 flag of SYS_ERR_INT_FLG reister will not be set on a
hardware event.
Reset type: SYSRSn
7 DCC0 R/W 0h 0: DCC0 flag of SYS_ERR_INT_FLG reister will be set on a
hardware event.
1: DCC0 flag of SYS_ERR_INT_FLG reister will not be set on a
hardware event.
Reset type: SYSRSn
6 AUX_PLL_SLIP R/W 1h RESERVED: This bit is reserved and the value set should always be
"1"
Note: This bit must always be set to 1.
Reset type: SYSRSn
5 SYS_PLL_SLIP R/W 1h RESERVED: This bit is reserved and the value set should always be
"1"
Note: This bit must always be set to 1.
Reset type: SYSRSn

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Table 3-374. SYS_ERR_MASK Register Field Descriptions (continued)

Bit Field Type Reset Description
4 RAM_ACC_VIOL R/W 0h 0: RAM_ACC_VIOL flag of SYS_ERR_INT_FLG reister will be set on
a hardware event.
1: RAM_ACC_VIOL flag of SYS_ERR_INT_FLG reister will not be
set on a hardware event.
Reset type: SYSRSn
3 FLASH_CORRECTABLE_ R/W 0h 0: FLASH_CORRECTABLE_ERR flag of SYS_ERR_INT_FLG
ERR reister will be set on a hardware event.
1: FLASH_CORRECTABLE_ERR flag of SYS_ERR_INT_FLG
reister will not be set on a hardware event.
Reset type: SYSRSn
2 RAM_CORRECTABLE_E R/W 0h 0: RAM_CORRECTABLE_ERR flag of SYS_ERR_INT_FLG reister
RR will be set on a hardware event.
1: RAM_CORRECTABLE_ERR flag of SYS_ERR_INT_FLG reister
will not be set on a hardware event.
Reset type: SYSRSn
1 EMIF_ERR R/W 0h 0: EMIF_ERR flag of SYS_ERR_INT_FLG reister will be set on a
hardware event.
1: EMIF_ERR flag of SYS_ERR_INT_FLG reister will not be set on a
hardware event.
Reset type: SYSRSn
0 RESERVED R 0h Reserved

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3.16.19 TEST_ERROR_REGS Registers

Table 3-375 lists the memory-mapped registers for the TEST_ERROR_REGS registers. All register offset
addresses not listed in Table 3-375 should be considered as reserved locations and the register contents should
not be modified.
Table 3-375. TEST_ERROR_REGS Registers
Offset Acronym Register Name Write Protection Section
0h CPU_RAM_TEST_ERROR_STS Ram Test: Error Status Register Go
2h CPU_RAM_TEST_ERROR_STS_C Ram Test: Error Status Clear Register Go
LR
4h CPU_RAM_TEST_ERROR_ADDR Ram Test: Error address register Go

Complex bit access types are encoded to fit into small table cells. Table 3-376 shows the codes that are used for
access types in this section.
Table 3-376. TEST_ERROR_REGS Access Type
Codes
Access Type Code Description
Read Type
R R Read
R-0 R Read
-0 Returns 0s
Write Type
W1S W Write
1S 1 to set
Reset or Default Value
-n Value after reset or the default
value
Register Array Variables
i,j,k,l,m,n When these variables are used in
a register name, an offset, or an
address, they refer to the value of
a register array where the register
is part of a group of repeating
registers. The register groups
form a hierarchical structure and
the array is represented with a
formula.
y When this variable is used in a
register name, an offset, or an
address it refers to the value of
a register array.

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3.16.19.1 CPU_RAM_TEST_ERROR_STS Register (Offset = 0h) [Reset = 0h]

CPU_RAM_TEST_ERROR_STS is shown in Figure 3-345 and described in Table 3-377.
Return to the Summary Table.
Ram Test: Error Status Register
Figure 3-345. CPU_RAM_TEST_ERROR_STS Register
31 30 29 28 27 26 25 24
RESERVED
R-0h

23 22 21 20 19 18 17 16
RESERVED
R-0h

15 14 13 12 11 10 9 8
RESERVED
R-0h

7 6 5 4 3 2 1 0
RESERVED UNC_ERROR COR_ERROR
R-0h R-0h R-0h

Table 3-377. CPU_RAM_TEST_ERROR_STS Register Field Descriptions

Bit Field Type Reset Description
31-2 RESERVED R 0h Reserved
1 UNC_ERROR R 0h 0: Indicates that there were no "un-correctable errors" generated in
the RAM/ROM test mode.
1: Indicates that "un-correctable errors" wer generated in the
RAM/ROM test mode.
Reset type: SYSRSn
0 COR_ERROR R 0h 0: Indicates that there were no "correctable errors" generated in the
RAM/ROM test mode.
1: Indicates that "correctable errors" wer generated in the RAM/ROM
test mode.
Reset type: SYSRSn

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3.16.19.2 CPU_RAM_TEST_ERROR_STS_CLR Register (Offset = 2h) [Reset = 0h]

CPU_RAM_TEST_ERROR_STS_CLR is shown in Figure 3-346 and described in Table 3-378.
Return to the Summary Table.
Ram Test: Error Status Clear Register
Figure 3-346. CPU_RAM_TEST_ERROR_STS_CLR Register
31 30 29 28 27 26 25 24
RESERVED
R-0h

23 22 21 20 19 18 17 16
RESERVED
R-0h

15 14 13 12 11 10 9 8
RESERVED
R-0h

7 6 5 4 3 2 1 0
RESERVED UNC_ERROR COR_ERROR
R-0h R-0/W1S-0h R-0/W1S-0h

Table 3-378. CPU_RAM_TEST_ERROR_STS_CLR Register Field Descriptions

Bit Field Type Reset Description
31-2 RESERVED R 0h Reserved
1 UNC_ERROR R-0/W1S 0h 0: No effect.
1: Clears the corresponding bit in CPU_RAM_TEST_ERROR_STS
register.
Reset type: SYSRSn
0 COR_ERROR R-0/W1S 0h 0: No effect.
1: Clears the corresponding bit in CPU_RAM_TEST_ERROR_STS
register.
Reset type: SYSRSn

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3.16.19.3 CPU_RAM_TEST_ERROR_ADDR Register (Offset = 4h) [Reset = 0h]

CPU_RAM_TEST_ERROR_ADDR is shown in Figure 3-347 and described in Table 3-379.
Return to the Summary Table.
Ram Test: Error address register
Figure 3-347. CPU_RAM_TEST_ERROR_ADDR Register
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ADDR
R-0h

Table 3-379. CPU_RAM_TEST_ERROR_ADDR Register Field Descriptions

Bit Field Type Reset Description
31-0 ADDR R 0h Address of the location where error was detected in RAM/ROM test
modes.
Reset type: SYSRSn

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3.16.20 UID_REGS Registers

Table 3-380 lists the memory-mapped registers for the UID_REGS registers. All register offset addresses not
listed in Table 3-380 should be considered as reserved locations and the register contents should not be
modified.
Table 3-380. UID_REGS Registers
Offset Acronym Register Name Write Protection Section
0h UID_PSRAND0 UID Psuedo-random 192 bit number Go
2h UID_PSRAND1 UID Psuedo-random 192 bit number Go
4h UID_PSRAND2 UID Psuedo-random 192 bit number Go
6h UID_PSRAND3 UID Psuedo-random 192 bit number Go
8h UID_PSRAND4 UID Psuedo-random 192 bit number Go
Ah UID_PSRAND5 UID Psuedo-random 192 bit number Go
Ch UID_UNIQUE UID Unique 32 bit number Go
Eh UID_CHECKSUM UID Checksum Go

Complex bit access types are encoded to fit into small table cells. Table 3-381 shows the codes that are used for
access types in this section.
Table 3-381. UID_REGS Access Type Codes
Access Type Code Description
Read Type
R R Read
Reset or Default Value
-n Value after reset or the default
value
Register Array Variables
i,j,k,l,m,n When these variables are used in
a register name, an offset, or an
address, they refer to the value of
a register array where the register
is part of a group of repeating
registers. The register groups
form a hierarchical structure and
the array is represented with a
formula.
y When this variable is used in a
register name, an offset, or an
address it refers to the value of
a register array.

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3.16.20.1 UID_PSRAND0 Register (Offset = 0h) [Reset = X]

UID_PSRAND0 is shown in Figure 3-348 and described in Table 3-382.
Return to the Summary Table.
UID Psuedo-random 192 bit number
Figure 3-348. UID_PSRAND0 Register
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RandomID
R-X

Table 3-382. UID_PSRAND0 Register Field Descriptions

Bit Field Type Reset Description
31-0 RandomID R X Psuedorandom portion of the UID
Reset type: N/A

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3.16.20.2 UID_PSRAND1 Register (Offset = 2h) [Reset = X]

UID_PSRAND1 is shown in Figure 3-349 and described in Table 3-383.
Return to the Summary Table.
UID Psuedo-random 192 bit number
Figure 3-349. UID_PSRAND1 Register
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RandomID
R-X

Table 3-383. UID_PSRAND1 Register Field Descriptions

Bit Field Type Reset Description
31-0 RandomID R X Psuedorandom portion of the UID
Reset type: N/A

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3.16.20.3 UID_PSRAND2 Register (Offset = 4h) [Reset = X]

UID_PSRAND2 is shown in Figure 3-350 and described in Table 3-384.
Return to the Summary Table.
UID Psuedo-random 192 bit number
Figure 3-350. UID_PSRAND2 Register
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RandomID
R-X

Table 3-384. UID_PSRAND2 Register Field Descriptions

Bit Field Type Reset Description
31-0 RandomID R X Psuedorandom portion of the UID
Reset type: N/A

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3.16.20.4 UID_PSRAND3 Register (Offset = 6h) [Reset = X]

UID_PSRAND3 is shown in Figure 3-351 and described in Table 3-385.
Return to the Summary Table.
UID Psuedo-random 192 bit number
Figure 3-351. UID_PSRAND3 Register
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RandomID
R-X

Table 3-385. UID_PSRAND3 Register Field Descriptions

Bit Field Type Reset Description
31-0 RandomID R X Psuedorandom portion of the UID
Reset type: N/A

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3.16.20.5 UID_PSRAND4 Register (Offset = 8h) [Reset = X]

UID_PSRAND4 is shown in Figure 3-352 and described in Table 3-386.
Return to the Summary Table.
UID Psuedo-random 192 bit number
Figure 3-352. UID_PSRAND4 Register
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RandomID
R-X

Table 3-386. UID_PSRAND4 Register Field Descriptions

Bit Field Type Reset Description
31-0 RandomID R X Psuedorandom portion of the UID
Reset type: N/A

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3.16.20.6 UID_PSRAND5 Register (Offset = Ah) [Reset = X]

UID_PSRAND5 is shown in Figure 3-353 and described in Table 3-387.
Return to the Summary Table.
UID Psuedo-random 192 bit number
Figure 3-353. UID_PSRAND5 Register
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RandomID
R-X

Table 3-387. UID_PSRAND5 Register Field Descriptions

Bit Field Type Reset Description
31-0 RandomID R X Psuedorandom portion of the UID
Reset type: N/A

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3.16.20.7 UID_UNIQUE Register (Offset = Ch) [Reset = X]

UID_UNIQUE is shown in Figure 3-354 and described in Table 3-388.
Return to the Summary Table.
UID Unique 32 bit number
Figure 3-354. UID_UNIQUE Register
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
UniqueID
R-X

Table 3-388. UID_UNIQUE Register Field Descriptions

Bit Field Type Reset Description
31-0 UniqueID R X Unique portion of the UID. This identifier will be unique across all
devices with the same PARTIDH.
Reset type: N/A

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3.16.20.8 UID_CHECKSUM Register (Offset = Eh) [Reset = X]

UID_CHECKSUM is shown in Figure 3-355 and described in Table 3-389.
Return to the Summary Table.
Fletcher checksum of UID_PSRAND and UID_UNIQUE registers
Figure 3-355. UID_CHECKSUM Register
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Checksum
R-X

Table 3-389. UID_CHECKSUM Register Field Descriptions

Bit Field Type Reset Description
31-0 Checksum R X Fletcher checksum of UID_PSRANDx and UID_UINIQUE
Reset type: N/A

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3.16.21 WD_REGS Registers

Table 3-390 lists the memory-mapped registers for the WD_REGS registers. All register offset addresses not
listed in Table 3-390 should be considered as reserved locations and the register contents should not be
modified.
Table 3-390. WD_REGS Registers
Offset Acronym Register Name Write Protection Section
22h SCSR System Control & Status Register EALLOW Go
23h WDCNTR Watchdog Counter Register EALLOW Go
25h WDKEY Watchdog Reset Key Register EALLOW Go
29h WDCR Watchdog Control Register EALLOW Go
2Ah WDWCR Watchdog Windowed Control Register EALLOW Go

Complex bit access types are encoded to fit into small table cells. Table 3-391 shows the codes that are used for
access types in this section.
Table 3-391. WD_REGS Access Type Codes
Access Type Code Description
Read Type
R R Read
R-0 R Read
-0 Returns 0s
Write Type
W W Write
W1C W Write
1C 1 to clear
W1S W Write
1S 1 to set
Reset or Default Value
-n Value after reset or the default
value
Register Array Variables
i,j,k,l,m,n When these variables are used in
a register name, an offset, or an
address, they refer to the value of
a register array where the register
is part of a group of repeating
registers. The register groups
form a hierarchical structure and
the array is represented with a
formula.
y When this variable is used in a
register name, an offset, or an
address it refers to the value of
a register array.

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3.16.21.1 SCSR Register (Offset = 22h) [Reset = 5h]

SCSR is shown in Figure 3-356 and described in Table 3-392.
Return to the Summary Table.
System Control & Status Register
It is recommended to only use 16 bit accesses to write to this register. Use a read-modify-write instruction may
inadvertently clear other bits.
Figure 3-356. SCSR Register
15 14 13 12 11 10 9 8
RESERVED
R-0-0h

7 6 5 4 3 2 1 0
RESERVED WDINTS WDENINT WDOVERRIDE
R-0-0h R-1h R/W-0h R/W1C-1h

Table 3-392. SCSR Register Field Descriptions

Bit Field Type Reset Description
15-3 RESERVED R-0 0h Reserved
2 WDINTS R 1h Watchdog Interrupt Status
This bit indicates the state of the active-low watchdog interrupt signal
(synchronized to SYSCLK). If the watchdog interrupt is used to wake
the system from a low-power mode, then that mode should only be
entered while this bit is high. Likewise, this bit must go high before
the watchdog can be safely disabled and re-enabled.
Reset type: SYSRSn
0h (R/W) = The watchdog interrupt signal is active.
1h (R/W) = The watchdog interrupt signal is inactive.
1 WDENINT R/W 0h Watchdog Interrupt Enable/Reset Disable
This bit determines whether the watchdog triggers an interrupt
(WAKE/WDOG) or a reset (WDRS) when the counter expires.
Reset type: SYSRSn
0h (R/W) = Counter expiration triggers a reset. This is the default
state on power-up and after any system reset.
1h (R/W) = Counter expiration triggers an interrupt.
0 WDOVERRIDE R/W1C 1h If this bit is set to 1, the user is allowed to change the state of the
Watchdog disable (WDDIS) bit in the Watchdog Control (WDCR)
register. If the WDOVERRIDE bit is cleared, by writing a 1 the
WDDIS bit cannot be modified by the user. Writing a 0 will have
no effect. If this bit is cleared, then it will remain in this state until a
reset occurs. The current state of this bit is readable by the user.
Reset type: SYSRSn

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3.16.21.2 WDCNTR Register (Offset = 23h) [Reset = 0h]

WDCNTR is shown in Figure 3-357 and described in Table 3-393.
Return to the Summary Table.
Watchdog Counter Register
Figure 3-357. WDCNTR Register
15 14 13 12 11 10 9 8
RESERVED
R-0-0h

7 6 5 4 3 2 1 0
WDCNTR
R-0h

Table 3-393. WDCNTR Register Field Descriptions

Bit Field Type Reset Description
15-8 RESERVED R-0 0h Reserved
7-0 WDCNTR R 0h Watchdog Counter
These bits contain the current value of the watchdog counter. This
counter increments with each WDCLK (INTOSC1) cycle. If the
counter overflows, either an interrupt or a reset is generated based
on the value of the WDINTEN bit in the SCSR register. If the correct
value is written to the WDKEY register, this counter is reset to zero.
Reset type: IORSn

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3.16.21.3 WDKEY Register (Offset = 25h) [Reset = 0h]

WDKEY is shown in Figure 3-358 and described in Table 3-394.
Return to the Summary Table.
Watchdog Reset Key Register
Figure 3-358. WDKEY Register
15 14 13 12 11 10 9 8
RESERVED
R-0-0h

7 6 5 4 3 2 1 0
WDKEY
R/W-0h

Table 3-394. WDKEY Register Field Descriptions

Bit Field Type Reset Description
15-8 RESERVED R-0 0h Reserved
7-0 WDKEY R/W 0h Watchdog Counter Reset
Writing 0x55 followed by 0xAA will cause the watchdog counter to
reset to zero, preventing an overflow. Writing other values has no
effect. Reads of this register return the value of the WDCR register.
Reset type: IORSn

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3.16.21.4 WDCR Register (Offset = 29h) [Reset = 0h]

WDCR is shown in Figure 3-359 and described in Table 3-395.
Return to the Summary Table.
Watchdog Control Register
This memory mapped register requires a delay between subsequent writes to the register, otherwise a second
write can be lost. The required delay is 69 SYSCLK cycles for a 200 MHz device, 45 SYSCLK cycles for a
120 MHz device, and 39 SYSCLK cycles for a 100 MHz device. This delay can be realized by adding NOP
instructions corresponding to the required delay cycles.
Figure 3-359. WDCR Register
15 14 13 12 11 10 9 8
RESERVED WDPRECLKDIV
R-0-0h R/W-0h

7 6 5 4 3 2 1 0
WDFLG WDDIS WDCHK WDPS
R/W1S-0h R/W-0h R-0/W-0h R/W-0h

Table 3-395. WDCR Register Field Descriptions

Bit Field Type Reset Description
15-12 RESERVED R-0 0h Reserved
11-8 WDPRECLKDIV R/W 0h Watchdog Clock Pre-divider
These bits determine the watchdog clock pre-divider, which is the
first of the two dividers between INTOSC1 and the watchdog counter
clock (WDCLK). The frequency of WDCLK is given by the formulas:
PREDIVCLK = INTOSC1 / Pre-divider
WDCLK = PREDIVCLK / Prescaler
Reset type: IORSn
0h (R/W) = PREDIVCLK = INTOSC1 / 512
1h (R/W) = PREDIVCLK = INTOSC1 / 1024
2h (R/W) = PREDIVCLK = INTOSC1 / 2048
3h (R/W) = PREDIVCLK = INTOSC1 / 4096
4h (R/W) = Reserved
5h (R/W) = Reserved
6h (R/W) = Reserved
7h (R/W) = Reserved
8h (R/W) = PREDIVCLK = INTOSC1 / 2
9h (R/W) = PREDIVCLK = INTOSC1 / 4
Ah (R/W) = PREDIVCLK = INTOSC1 / 8
Bh (R/W) = PREDIVCLK = INTOSC1 / 16
Ch (R/W) = PREDIVCLK = INTOSC1 / 32
Dh (R/W) = PREDIVCLK = INTOSC1 / 64
Eh (R/W) = PREDIVCLK = INTOSC1 / 128
Fh (R/W) = PREDIVCLK = INTOSC1 / 256
7 WDFLG R/W1S 0h Watchdog reset status flag bit. This bit, if set, indicates a watchdog
reset (WDRSTn) generated the reset condition. If 0, then it was en
external device or power-up reset condition. This bit remains latched
until the user writes a 1 to clear the condition. Writes of 0 will be
ignored.
Reset type: IORSn
6 WDDIS R/W 0h Watchdog Disable
Setting this bit disables the watchdog module. Clearing this bit
enables the watchdog module. This bit can be locked by the
WDOVERRIDE bit in the SCSR register. The watchdog is enabled
on reset.
Reset type: IORSn

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Table 3-395. WDCR Register Field Descriptions (continued)

Bit Field Type Reset Description
5-3 WDCHK R-0/W 0h Watchdog Check Bits
During any write to this register, these bits must be written with the
value 101 (binary). Writing any other value will immediately trigger
the watchdog reset or interrupt.
Reset type: IORSn
2-0 WDPS R/W 0h Watchdog Clock Prescaler
These bits determine the watchdog clock prescaler, which is the
second of the two dividers between INTOSC1 and the watchdog
counter clock (WDCLK). The frequency of WDCLK is given by the
formulas:
PREDIVCLK = INTOSC1 / Pre-divider
WDCLK = PREDIVCLK / Prescaler
The watchdog reset or interrupt pulse is 512 INTOSC1 cycles long,
so the counter period must be longer. To guarantee this, the product
of the prescaler and pre-divider must be greater than or equal to four.
The default prescaler value is 1.
Reset type: IORSn
0h (R/W) = WDCLK = PREDIVCLK / 1
1h (R/W) = WDCLK = PREDIVCLK / 1
2h (R/W) = WDCLK = PREDIVCLK / 2
3h (R/W) = WDCLK = PREDIVCLK / 4
4h (R/W) = WDCLK = PREDIVCLK / 8
5h (R/W) = WDCLK = PREDIVCLK / 16
6h (R/W) = WDCLK = PREDIVCLK / 32
7h (R/W) = WDCLK = PREDIVCLK / 64

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3.16.21.5 WDWCR Register (Offset = 2Ah) [Reset = 0h]

WDWCR is shown in Figure 3-360 and described in Table 3-396.
Return to the Summary Table.
Watchdog Windowed Control Register
Figure 3-360. WDWCR Register
15 14 13 12 11 10 9 8
RESERVED FIRSTKEY
R-0-0h R-0h

7 6 5 4 3 2 1 0
MIN
R/W-0h

Table 3-396. WDWCR Register Field Descriptions

Bit Field Type Reset Description
15-9 RESERVED R-0 0h Reserved
8 FIRSTKEY R 0h This bit indicates if the 1st valid WDKEY (0x55 + 0xAA) got detected
after MIN was configured to a non-zero value
0: First Valid Key after non-zero MIN configuration has not happened
yet
1: First Valid key after non-zero MIN configuration got detected
Notes:
[1] If MIN = 0, this bit is never set
[2] If MIN is changed back to 0x0 from a non-zero value, this bit is
auto-cleared
[3] This bit is added for debug purposes only
Reset type: IORSn
7-0 MIN R/W 0h Watchdog Window Threshold
These bits specify the lower limit of the watchdog counter reset
window. If the counter is reset via the WDKEY register before
the counter value reaches the value in this register, the watchdog
immediately triggers a reset or interrupt.
Reset type: IORSn

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3.16.22 XINT_REGS Registers

Table 3-397 lists the memory-mapped registers for the XINT_REGS registers. All register offset addresses
not listed in Table 3-397 should be considered as reserved locations and the register contents should not be
modified.
Table 3-397. XINT_REGS Registers
Offset Acronym Register Name Write Protection Section
0h XINT1CR XINT1 configuration register Go
1h XINT2CR XINT2 configuration register Go
2h XINT3CR XINT3 configuration register Go
3h XINT4CR XINT4 configuration register Go
4h XINT5CR XINT5 configuration register Go
8h XINT1CTR XINT1 counter register Go
9h XINT2CTR XINT2 counter register Go
Ah XINT3CTR XINT3 counter register Go

Complex bit access types are encoded to fit into small table cells. Table 3-398 shows the codes that are used for
access types in this section.
Table 3-398. XINT_REGS Access Type Codes
Access Type Code Description
Read Type
R R Read
R-0 R Read
-0 Returns 0s
Write Type
W W Write
Reset or Default Value
-n Value after reset or the default
value
Register Array Variables
i,j,k,l,m,n When these variables are used in
a register name, an offset, or an
address, they refer to the value of
a register array where the register
is part of a group of repeating
registers. The register groups
form a hierarchical structure and
the array is represented with a
formula.
y When this variable is used in a
register name, an offset, or an
address it refers to the value of
a register array.

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3.16.22.1 XINT1CR Register (Offset = 0h) [Reset = 0h]

XINT1CR is shown in Figure 3-361 and described in Table 3-399.
Return to the Summary Table.
XINT1 configuration register
Figure 3-361. XINT1CR Register
15 14 13 12 11 10 9 8
RESERVED
R-0-0h

7 6 5 4 3 2 1 0
RESERVED POLARITY RESERVED ENABLE
R-0-0h R/W-0h R-0-0h R/W-0h

Table 3-399. XINT1CR Register Field Descriptions

Bit Field Type Reset Description
15-4 RESERVED R-0 0h Reserved
3-2 POLARITY R/W 0h 00: Interrupt is selected as negative edge triggered
01: Interrupt is selected as positive edge triggered
10: Interrupt is selected as negative edge triggered
11: Interrupt is selected as positive or negative edge triggered
Reset type: SYSRSn
1 RESERVED R-0 0h Reserved
0 ENABLE R/W 0h 0: Interrupt Disabled
1: Interrupt Enabled
Reset type: SYSRSn

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3.16.22.2 XINT2CR Register (Offset = 1h) [Reset = 0h]

XINT2CR is shown in Figure 3-362 and described in Table 3-400.
Return to the Summary Table.
XINT2 configuration register
Figure 3-362. XINT2CR Register
15 14 13 12 11 10 9 8
RESERVED
R-0-0h

7 6 5 4 3 2 1 0
RESERVED POLARITY RESERVED ENABLE
R-0-0h R/W-0h R-0-0h R/W-0h

Table 3-400. XINT2CR Register Field Descriptions

Bit Field Type Reset Description
15-4 RESERVED R-0 0h Reserved
3-2 POLARITY R/W 0h 00: Interrupt is selected as negative edge triggered
01: Interrupt is selected as positive edge triggered
10: Interrupt is selected as negative edge triggered
11: Interrupt is selected as positive or negative edge triggered
Reset type: SYSRSn
1 RESERVED R-0 0h Reserved
0 ENABLE R/W 0h 0: Interrupt Disabled
1: Interrupt Enabled
Reset type: SYSRSn

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3.16.22.3 XINT3CR Register (Offset = 2h) [Reset = 0h]

XINT3CR is shown in Figure 3-363 and described in Table 3-401.
Return to the Summary Table.
XINT3 configuration register
Figure 3-363. XINT3CR Register
15 14 13 12 11 10 9 8
RESERVED
R-0-0h

7 6 5 4 3 2 1 0
RESERVED POLARITY RESERVED ENABLE
R-0-0h R/W-0h R-0-0h R/W-0h

Table 3-401. XINT3CR Register Field Descriptions

Bit Field Type Reset Description
15-4 RESERVED R-0 0h Reserved
3-2 POLARITY R/W 0h 00: Interrupt is selected as negative edge triggered
01: Interrupt is selected as positive edge triggered
10: Interrupt is selected as negative edge triggered
11: Interrupt is selected as positive or negative edge triggered
Reset type: SYSRSn
1 RESERVED R-0 0h Reserved
0 ENABLE R/W 0h 0: Interrupt Disabled
1: Interrupt Enabled
Reset type: SYSRSn

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3.16.22.4 XINT4CR Register (Offset = 3h) [Reset = 0h]

XINT4CR is shown in Figure 3-364 and described in Table 3-402.
Return to the Summary Table.
XINT4 configuration register
Figure 3-364. XINT4CR Register
15 14 13 12 11 10 9 8
RESERVED
R-0-0h

7 6 5 4 3 2 1 0
RESERVED POLARITY RESERVED ENABLE
R-0-0h R/W-0h R-0-0h R/W-0h

Table 3-402. XINT4CR Register Field Descriptions

Bit Field Type Reset Description
15-4 RESERVED R-0 0h Reserved
3-2 POLARITY R/W 0h 00: Interrupt is selected as negative edge triggered
01: Interrupt is selected as positive edge triggered
10: Interrupt is selected as negative edge triggered
11: Interrupt is selected as positive or negative edge triggered
Reset type: SYSRSn
1 RESERVED R-0 0h Reserved
0 ENABLE R/W 0h 0: Interrupt Disabled
1: Interrupt Enabled
Reset type: SYSRSn

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3.16.22.5 XINT5CR Register (Offset = 4h) [Reset = 0h]

XINT5CR is shown in Figure 3-365 and described in Table 3-403.
Return to the Summary Table.
XINT5 configuration register
Figure 3-365. XINT5CR Register
15 14 13 12 11 10 9 8
RESERVED
R-0-0h

7 6 5 4 3 2 1 0
RESERVED POLARITY RESERVED ENABLE
R-0-0h R/W-0h R-0-0h R/W-0h

Table 3-403. XINT5CR Register Field Descriptions

Bit Field Type Reset Description
15-4 RESERVED R-0 0h Reserved
3-2 POLARITY R/W 0h 00: Interrupt is selected as negative edge triggered
01: Interrupt is selected as positive edge triggered
10: Interrupt is selected as negative edge triggered
11: Interrupt is selected as positive or negative edge triggered
Reset type: SYSRSn
1 RESERVED R-0 0h Reserved
0 ENABLE R/W 0h 0: Interrupt Disabled
1: Interrupt Enabled
Reset type: SYSRSn

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3.16.22.6 XINT1CTR Register (Offset = 8h) [Reset = 0h]

XINT1CTR is shown in Figure 3-366 and described in Table 3-404.
Return to the Summary Table.
XINT1 counter register
Figure 3-366. XINT1CTR Register
15 14 13 12 11 10 9 8
INTCTR
R-0h

7 6 5 4 3 2 1 0
INTCTR
R-0h

Table 3-404. XINT1CTR Register Field Descriptions

Bit Field Type Reset Description
15-0 INTCTR R 0h This is a free running 16-bit up-counter that is clocked at the
SYSCLKOUT rate. The counter value is reset to 0x0000 when a
valid interrupt edge is detected and then continues counting until
the next valid interrupt edge is detected. The counter must only be
reset by the selected POLARITY edge as selected in the respective
interrupt control register. When the interrupt is disabled, the counter
will stop. The counter is a free-running counter and will wrap around
to zero when the max value is reached. The counter is a read only
register and can only be reset to zero by a valid interrupt edge or by
reset.
Reset type: SYSRSn

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3.16.22.7 XINT2CTR Register (Offset = 9h) [Reset = 0h]

XINT2CTR is shown in Figure 3-367 and described in Table 3-405.
Return to the Summary Table.
XINT2 counter register
Figure 3-367. XINT2CTR Register
15 14 13 12 11 10 9 8
INTCTR
R-0h

7 6 5 4 3 2 1 0
INTCTR
R-0h

Table 3-405. XINT2CTR Register Field Descriptions

Bit Field Type Reset Description
15-0 INTCTR R 0h This is a free running 16-bit up-counter that is clocked at the
SYSCLKOUT rate. The counter value is reset to 0x0000 when a
valid interrupt edge is detected and then continues counting until
the next valid interrupt edge is detected. The counter must only be
reset by the selected POLARITY edge as selected in the respective
interrupt control register. When the interrupt is disabled, the counter
will stop. The counter is a free-running counter and will wrap around
to zero when the max value is reached. The counter is a read only
register and can only be reset to zero by a valid interrupt edge or by
reset.
Reset type: SYSRSn

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3.16.22.8 XINT3CTR Register (Offset = Ah) [Reset = 0h]

XINT3CTR is shown in Figure 3-368 and described in Table 3-406.
Return to the Summary Table.
XINT3 counter register
Figure 3-368. XINT3CTR Register
15 14 13 12 11 10 9 8
INTCTR
R-0h

7 6 5 4 3 2 1 0
INTCTR
R-0h

Table 3-406. XINT3CTR Register Field Descriptions

Bit Field Type Reset Description
15-0 INTCTR R 0h This is a free running 16-bit up-counter that is clocked at the
SYSCLKOUT rate. The counter value is reset to 0x0000 when a
valid interrupt edge is detected and then continues counting until
the next valid interrupt edge is detected. The counter must only be
reset by the selected POLARITY edge as selected in the respective
interrupt control register. When the interrupt is disabled, the counter
will stop. The counter is a free-running counter and will wrap around
to zero when the max value is reached. The counter is a read only
register and can only be reset to zero by a valid interrupt edge or by
reset.
Reset type: SYSRSn

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3.16.23 Register to Driverlib Function Mapping

3.16.23.1 ASYSCTL Registers to Driverlib Functions

Table 3-407. ASYSCTL Registers to Driverlib Functions
File Driverlib Function
INTOSC1TRIM
-
INTOSC2TRIM
-
TSNSCTL
asysctl.h ASysCtl_enableTemperatureSensor
asysctl.h ASysCtl_disableTemperatureSensor
LOCK
asysctl.h ASysCtl_lockTemperatureSensor
ANAREFTRIMA
-
ANAREFTRIMB
-
ANAREFTRIMC
-
ANAREFTRIMD
-

3.16.23.2 CPUTIMER Registers to Driverlib Functions

Table 3-408. CPUTIMER Registers to Driverlib Functions
File Driverlib Function
TIM
cputimer.h CPUTimer_getTimerCount
PRD
cputimer.h CPUTimer_setPeriod
TCR
cputimer.c CPUTimer_setEmulationMode
cputimer.h CPUTimer_clearOverflowFlag
cputimer.h CPUTimer_disableInterrupt
cputimer.h CPUTimer_enableInterrupt
cputimer.h CPUTimer_reloadTimerCounter
cputimer.h CPUTimer_stopTimer
cputimer.h CPUTimer_resumeTimer
cputimer.h CPUTimer_startTimer
cputimer.h CPUTimer_getTimerOverflowStatus
TPR
cputimer.h CPUTimer_setPreScaler
TPRH
cputimer.h CPUTimer_setPreScaler

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3.16.23.3 DCSM Registers to Driverlib Functions

Table 3-409. DCSM Registers to Driverlib Functions
File Driverlib Function
Z1OTP_LINKPOINTER1
-
Z1OTP_LINKPOINTER2
-
Z1OTP_LINKPOINTER3
-
Z1OTP_JLM_ENABLE
-
Z1OTP_GPREG1
-
Z1OTP_GPREG2
-
Z1OTP_GPREG3
-
Z1OTP_GPREG4
-
Z1OTP_PSWDLOCK
-
Z1OTP_CRCLOCK
-
Z1OTP_JTAGPSWDH0
-
Z1OTP_JTAGPSWDH1
-
Z1OTP_CMACKEY0
-
Z1OTP_CMACKEY1
-
Z1OTP_CMACKEY2
-
Z1OTP_CMACKEY3
-
Z2OTP_LINKPOINTER1
-
Z2OTP_LINKPOINTER2
-
Z2OTP_LINKPOINTER3
-
Z2OTP_GPREG1
-
Z2OTP_GPREG2
-
Z2OTP_GPREG3
-

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Table 3-409. DCSM Registers to Driverlib Functions (continued)

File Driverlib Function
Z2OTP_GPREG4
-
Z2OTP_PSWDLOCK
-
Z2OTP_CRCLOCK
-
Z1_LINKPOINTER
dcsm.c DCSM_unlockZone1CSM
dcsm.c DCSM_readZone1CSMPwd
dcsm.h DCSM_getZone1LinkPointerError
Z1_OTPSECLOCK
dcsm.h DCSM_getZone1OTPSecureLockStatus
Z1_JLM_ENABLE
-
Z1_LINKPOINTERERR
dcsm.h DCSM_getZone1LinkPointerError
Z1_GPREG1
-
Z1_GPREG2
-
Z1_GPREG3
-
Z1_GPREG4
-
Z1_CSMKEY0
dcsm.c DCSM_unlockZone1CSM
dcsm.c DCSM_writeZone1CSM
Z1_CSMKEY1
dcsm.c DCSM_unlockZone1CSM
dcsm.c DCSM_writeZone1CSM
Z1_CSMKEY2
dcsm.c DCSM_unlockZone1CSM
dcsm.c DCSM_writeZone1CSM
Z1_CSMKEY3
dcsm.c DCSM_unlockZone1CSM
dcsm.c DCSM_writeZone1CSM
Z1_CR
dcsm.h DCSM_secureZone1
dcsm.h DCSM_getZone1CSMSecurityStatus
dcsm.h DCSM_getZone1ControlStatus
Z1_GRABSECT1R
-
Z1_GRABSECT2R
-
Z1_GRABSECT3R

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Table 3-409. DCSM Registers to Driverlib Functions (continued)

File Driverlib Function
-
Z1_GRABRAM1R
-
Z1_GRABRAM2R
-
Z1_GRABRAM3R
-
Z1_EXEONLYSECT1R
dcsm.c DCSM_getZone1FlashEXEStatus
Z1_EXEONLYSECT2R
dcsm.c DCSM_getZone1FlashEXEStatus
Z1_EXEONLYRAM1R
dcsm.c DCSM_getZone1RAMEXEStatus
Z1_JTAGKEY0
-
Z1_JTAGKEY1
-
Z1_JTAGKEY2
-
Z1_JTAGKEY3
-
Z1_CMACKEY0
-
Z1_CMACKEY1
-
Z1_CMACKEY2
-
Z1_CMACKEY3
-
Z2_LINKPOINTER
dcsm.c DCSM_unlockZone2CSM
dcsm.c DCSM_readZone2CSMPwd
dcsm.h DCSM_getZone2LinkPointerError
Z2_OTPSECLOCK
dcsm.h DCSM_getZone2OTPSecureLockStatus
Z2_LINKPOINTERERR
dcsm.h DCSM_getZone2LinkPointerError
Z2_GPREG1
-
Z2_GPREG2
-
Z2_GPREG3
-
Z2_GPREG4
-

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Table 3-409. DCSM Registers to Driverlib Functions (continued)

File Driverlib Function
Z2_CSMKEY0
dcsm.c DCSM_unlockZone2CSM
dcsm.c DCSM_writeZone2CSM
Z2_CSMKEY1
dcsm.c DCSM_unlockZone2CSM
dcsm.c DCSM_writeZone2CSM
Z2_CSMKEY2
dcsm.c DCSM_unlockZone2CSM
dcsm.c DCSM_writeZone2CSM
Z2_CSMKEY3
dcsm.c DCSM_unlockZone2CSM
dcsm.c DCSM_writeZone2CSM
Z2_CR
dcsm.h DCSM_secureZone2
dcsm.h DCSM_getZone2CSMSecurityStatus
dcsm.h DCSM_getZone2ControlStatus
Z2_GRABSECT1R
-
Z2_GRABSECT2R
-
Z2_GRABSECT3R
-
Z2_GRABRAM1R
-
Z2_GRABRAM2R
-
Z2_GRABRAM3R
-
Z2_EXEONLYSECT1R
dcsm.c DCSM_getZone2FlashEXEStatus
Z2_EXEONLYSECT2R
dcsm.c DCSM_getZone2FlashEXEStatus
Z2_EXEONLYRAM1R
dcsm.c DCSM_getZone2RAMEXEStatus
FLSEM
dcsm.c DCSM_claimZoneSemaphore
dcsm.c DCSM_releaseZoneSemaphore
SECTSTAT1
dcsm.h DCSM_getFlashSectorZone
SECTSTAT2
-
SECTSTAT3
-
RAMSTAT1
dcsm.h DCSM_getRAMZone

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Table 3-409. DCSM Registers to Driverlib Functions (continued)

File Driverlib Function
RAMSTAT2
-
RAMSTAT3
-
SECERRSTAT
dcsm.h DCSM_getFlashErrorStatus
SECERRCLR
dcsm.h DCSM_clearFlashErrorStatus
SECERRFRC
dcsm.h DCSM_forceFlashErrorStatus

3.16.23.4 MEMCFG Registers to Driverlib Functions

Table 3-410. MEMCFG Registers to Driverlib Functions
File Driverlib Function
DXLOCK
memcfg.c MemCfg_lockConfig
memcfg.c MemCfg_unlockConfig
DXCOMMIT
memcfg.c MemCfg_commitConfig
DXACCPROT0
memcfg.c MemCfg_setProtection
DXTEST
memcfg.c MemCfg_setTestMode
DXINIT
memcfg.c MemCfg_initSections
memcfg.c MemCfg_getInitStatus
DXINITDONE
memcfg.c MemCfg_getInitStatus
DXRAMTEST_LOCK
memcfg.c MemCfg_lockTestConfig
memcfg.c MemCfg_unlockTestConfig
LSXLOCK
memcfg.c MemCfg_lockConfig
memcfg.c MemCfg_unlockConfig
LSXCOMMIT
memcfg.c MemCfg_commitConfig
LSXMSEL
memcfg.c MemCfg_setLSRAMControllerSel
LSXCLAPGM
memcfg.h MemCfg_setCLAMemType
LSXACCPROT0
memcfg.c MemCfg_setProtection
LSXACCPROT1
-
LSXTEST

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Table 3-410. MEMCFG Registers to Driverlib Functions (continued)

File Driverlib Function
memcfg.c MemCfg_setTestMode
LSXINIT
memcfg.c MemCfg_initSections
memcfg.c MemCfg_getInitStatus
LSXINITDONE
memcfg.c MemCfg_getInitStatus
LSXRAMTEST_LOCK
memcfg.c MemCfg_lockTestConfig
memcfg.c MemCfg_unlockTestConfig
GSXLOCK
memcfg.c MemCfg_lockConfig
memcfg.c MemCfg_unlockConfig
GSXCOMMIT
memcfg.c MemCfg_commitConfig
GSXMSEL
memcfg.c MemCfg_setGSRAMControllerSel
GSXACCPROT0
memcfg.c MemCfg_setProtection
GSXACCPROT1
- See GSXACCPROT0
GSXACCPROT2
- See GSXACCPROT0
GSXACCPROT3
- See GSXACCPROT0
GSXTEST
memcfg.c MemCfg_setTestMode
GSXINIT
memcfg.c MemCfg_initSections
memcfg.c MemCfg_getInitStatus
GSXINITDONE
memcfg.c MemCfg_getInitStatus
GSXRAMTEST_LOCK
memcfg.c MemCfg_lockTestConfig
memcfg.c MemCfg_unlockTestConfig
MSGXLOCK
memcfg.c MemCfg_lockConfig
memcfg.c MemCfg_unlockConfig
MSGXCOMMIT
memcfg.c MemCfg_commitConfig
MSGXACCPROT0
memcfg.c MemCfg_setProtection
MSGXACCPROT1
-
MSGXACCPROT2
-

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Table 3-410. MEMCFG Registers to Driverlib Functions (continued)

File Driverlib Function
MSGXTEST
memcfg.c MemCfg_setTestMode
MSGXINIT
memcfg.c MemCfg_initSections
memcfg.c MemCfg_getInitStatus
MSGXINITDONE
memcfg.c MemCfg_getInitStatus
MSGXRAMTEST_LOCK
memcfg.c MemCfg_lockTestConfig
memcfg.c MemCfg_unlockTestConfig
ROM_LOCK
memcfg.c MemCfg_lockTestConfig
memcfg.c MemCfg_unlockTestConfig
ROM_TEST
memcfg.c MemCfg_setTestMode
ROM_FORCE_ERROR
memcfg.c MemCfg_forceMemError
PERI_MEM_TEST_LOCK
memcfg.c MemCfg_lockTestConfig
memcfg.c MemCfg_unlockTestConfig
PERI_MEM_TEST_CONTROL
memcfg.c MemCfg_forceMemError
memcfg.c MemCfg_enablePeriMemTestMode
memcfg.c MemCfg_disablePeriMemTestMode
EMIF1LOCK
emif.h EMIF_lockAccessConfig
emif.h EMIF_unlockAccessConfig
EMIF1COMMIT
emif.h EMIF_commitAccessConfig
EMIF1MSEL
emif.h EMIF_selectController
EMIF1ACCPROT0
emif.h EMIF_setAccessProtection
EMIF2LOCK
-
EMIF2COMMIT
-
EMIF2ACCPROT0
-
NMAVFLG
memcfg.h MemCfg_getViolationInterruptStatus
NMAVSET
memcfg.h MemCfg_forceViolationInterrupt
NMAVCLR
memcfg.h MemCfg_clearViolationInterruptStatus

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Table 3-410. MEMCFG Registers to Driverlib Functions (continued)

File Driverlib Function
NMAVINTEN
memcfg.h MemCfg_enableViolationInterrupt
memcfg.h MemCfg_disableViolationInterrupt
NMCPURDAVADDR
memcfg.c MemCfg_getViolationAddress
NMCPUWRAVADDR
memcfg.c MemCfg_getViolationAddress
NMCPUFAVADDR
-
NMDMAWRAVADDR
-
NMCLA1RDAVADDR
-
NMCLA1WRAVADDR
-
NMCLA1FAVADDR
-
NMDMARDAVADDR
-
MAVFLG
memcfg.h MemCfg_getViolationInterruptStatus
MAVSET
memcfg.h MemCfg_forceViolationInterrupt
MAVCLR
memcfg.h MemCfg_clearViolationInterruptStatus
MAVINTEN
memcfg.h MemCfg_enableViolationInterrupt
memcfg.h MemCfg_disableViolationInterrupt
MCPUFAVADDR
memcfg.c MemCfg_getViolationAddress
MCPUWRAVADDR
-
MDMAWRAVADDR
-
UCERRFLG
memcfg.h MemCfg_getUncorrErrorStatus
UCERRSET
memcfg.h MemCfg_forceUncorrErrorStatus
UCERRCLR
memcfg.h MemCfg_clearUncorrErrorStatus
UCCPUREADDR
memcfg.c MemCfg_getUncorrErrorAddress
UCDMAREADDR
memcfg.c MemCfg_getUncorrErrorAddress
UCCLA1READDR

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Table 3-410. MEMCFG Registers to Driverlib Functions (continued)

File Driverlib Function
-
UCECATRAMADDR
-
CERRFLG
memcfg.h MemCfg_getCorrErrorStatus
CERRSET
memcfg.c MemCfg_getCorrErrorAddress
memcfg.h MemCfg_forceCorrErrorStatus
CERRCLR
memcfg.c MemCfg_getCorrErrorAddress
memcfg.h MemCfg_clearCorrErrorStatus
CCPUREADDR
memcfg.c MemCfg_getCorrErrorAddress
CCLA1READDR
-
CERRCNT
memcfg.h MemCfg_getCorrErrorCount
CERRTHRES
memcfg.h MemCfg_setCorrErrorThreshold
CEINTFLG
memcfg.h MemCfg_getCorrErrorInterruptStatus
CEINTCLR
memcfg.h MemCfg_clearCorrErrorInterruptStatus
CEINTSET
memcfg.h MemCfg_forceCorrErrorInterrupt
CEINTEN
memcfg.h MemCfg_enableCorrErrorInterrupt
memcfg.h MemCfg_disableCorrErrorInterrupt
ROMWAITSTATE
memcfg.h MemCfg_enableROMWaitState
memcfg.h MemCfg_disableROMWaitState
ROMPREFETCH
memcfg.h MemCfg_enableROMPrefetch
memcfg.h MemCfg_disableROMPrefetch
CPU_RAM_TEST_ERROR_STS
memcfg.h MemCfg_getDiagErrorStatus
memcfg.h MemCfg_clearDiagErrorStatus
CPU_RAM_TEST_ERROR_STS_CLR
memcfg.h MemCfg_clearDiagErrorStatus
CPU_RAM_TEST_ERROR_ADDR
memcfg.h MemCfg_getDiagErrorAddress

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3.16.23.5 NMI Registers to Driverlib Functions

Table 3-411. NMI Registers to Driverlib Functions
File Driverlib Function
CFG
sysctl.h SysCtl_enableNMIGlobalInterrupt
FLG
sysctl.h SysCtl_getNMIStatus
sysctl.h SysCtl_getNMIFlagStatus
sysctl.h SysCtl_isNMIFlagSet
sysctl.h SysCtl_clearNMIStatus
sysctl.h SysCtl_clearAllNMIFlags
sysctl.h SysCtl_forceNMIFlags
FLGCLR
sysctl.h SysCtl_clearNMIStatus
sysctl.h SysCtl_clearAllNMIFlags
FLGFRC
sysctl.h SysCtl_forceNMIFlags
WDCNT
sysctl.h SysCtl_getNMIWatchdogCounter
WDPRD
sysctl.h SysCtl_setNMIWatchdogPeriod
sysctl.h SysCtl_getNMIWatchdogPeriod
SHDFLG
sysctl.h SysCtl_getNMIShadowFlagStatus
sysctl.h SysCtl_isNMIShadowFlagSet
ERRORSTS
sysctl.h SysCtl_isErrorTriggered
sysctl.h SysCtl_getErrorPinStatus
sysctl.h SysCtl_forceError
sysctl.h SysCtl_clearError
ERRORSTSCLR
sysctl.h SysCtl_clearError
ERRORSTSFRC
sysctl.h SysCtl_forceError
ERRORCTL
sysctl.h SysCtl_selectErrPinPolarity
ERRORLOCK
sysctl.h SysCtl_lockErrControl

3.16.23.6 PIE Registers to Driverlib Functions

Table 3-412. PIE Registers to Driverlib Functions
File Driverlib Function
CTRL
interrupt.c Interrupt_initModule
interrupt.c Interrupt_defaultHandler
interrupt.h Interrupt_enablePIE
interrupt.h Interrupt_disablePIE

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Table 3-412. PIE Registers to Driverlib Functions (continued)

File Driverlib Function
ACK
interrupt.c Interrupt_disable
interrupt.h Interrupt_clearACKGroup
IER1
interrupt.c Interrupt_initModule
interrupt.c Interrupt_enable
interrupt.c Interrupt_disable
IFR1
interrupt.c Interrupt_initModule
IER2
interrupt.c Interrupt_initModule
IFR2
interrupt.c Interrupt_initModule
IER3
interrupt.c Interrupt_initModule
IFR3
interrupt.c Interrupt_initModule
IER4
interrupt.c Interrupt_initModule
IFR4
interrupt.c Interrupt_initModule
IER5
interrupt.c Interrupt_initModule
IFR5
interrupt.c Interrupt_initModule
IER6
interrupt.c Interrupt_initModule
IFR6
interrupt.c Interrupt_initModule
IER7
interrupt.c Interrupt_initModule
IFR7
interrupt.c Interrupt_initModule
IER8
interrupt.c Interrupt_initModule
IFR8
interrupt.c Interrupt_initModule
IER9
interrupt.c Interrupt_initModule
IFR9
interrupt.c Interrupt_initModule
IER10
interrupt.c Interrupt_initModule
IFR10
interrupt.c Interrupt_initModule

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Table 3-412. PIE Registers to Driverlib Functions (continued)

File Driverlib Function
IER11
interrupt.c Interrupt_initModule
IFR11
interrupt.c Interrupt_initModule
IER12
interrupt.c Interrupt_initModule
IFR12
interrupt.c Interrupt_initModule

3.16.23.7 SYSCTL Registers to Driverlib Functions

Table 3-413. SYSCTL Registers to Driverlib Functions
File Driverlib Function
CLKSEM
sysctl.c SysCtl_setSemOwner
sysctl.h SysCtl_getSemOwner
CLKCFGLOCK1
sysctl.c SysCtl_lockClkConfig
CLKSRCCTL1
sysctl.c SysCtl_getClock
sysctl.c SysCtl_setClock
sysctl.c SysCtl_selectXTAL
sysctl.c SysCtl_selectXTALSingleEnded
sysctl.c SysCtl_selectOscSource
sysctl.c SysCtl_selectOscSourceAuxPLL
sysctl.h SysCtl_turnOnOsc
sysctl.h SysCtl_turnOffOsc
CLKSRCCTL2
can.h CAN_selectClockSource
sysctl.c SysCtl_getAuxClock
sysctl.c SysCtl_setAuxClock
sysctl.c SysCtl_selectOscSourceAuxPLL
CLKSRCCTL3
sysctl.h SysCtl_selectClockOutSource
SYSPLLCTL1
sysctl.c SysCtl_getClock
sysctl.c SysCtl_setClock
SYSPLLMULT
sysctl.c SysCtl_getClock
sysctl.c SysCtl_setClock
SYSPLLSTS
sysctl.c SysCtl_setClock
AUXPLLCTL1
sysctl.c SysCtl_getAuxClock
sysctl.c SysCtl_setAuxClock
AUXPLLMULT

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Table 3-413. SYSCTL Registers to Driverlib Functions (continued)

File Driverlib Function
sysctl.c SysCtl_getAuxClock
sysctl.c SysCtl_setAuxClock
AUXPLLSTS
sysctl.c SysCtl_setAuxClock
SYSCLKDIVSEL
sysctl.c SysCtl_getClock
sysctl.c SysCtl_setClock
sysctl.h SysCtl_setPLLSysClk
AUXCLKDIVSEL
sysctl.c SysCtl_getAuxClock
sysctl.c SysCtl_setAuxClock
sysctl.h SysCtl_setAuxPLLClk
sysctl.h SysCtl_setMCANClk
PERCLKDIVSEL
sysctl.h SysCtl_setEPWMClockDivider
sysctl.h SysCtl_setEMIF1ClockDivider
sysctl.h SysCtl_setEMIF2ClockDivider
XCLKOUTDIVSEL
sysctl.h SysCtl_setXClk
CLBCLKCTL
sysctl.h SysCtl_setCLBClk
sysctl.h SysCtl_setCLBClkDivider
sysctl.h SysCtl_CLBClkConfig
LOSPCP
sysctl.c SysCtl_getLowSpeedClock
sysctl.h SysCtl_setLowSpeedClock
MCDCR
sysctl.h SysCtl_enableMCD
sysctl.h SysCtl_disableMCD
sysctl.h SysCtl_isMCDClockFailureDetected
sysctl.h SysCtl_resetMCD
sysctl.h SysCtl_connectMCDClockSource
sysctl.h SysCtl_disconnectMCDClockSource
X1CNT
sysctl.c SysCtl_pollX1Counter
sysctl.h SysCtl_getExternalOscCounterValue
sysctl.h SysCtl_clearExternalOscCounterValue
XTALCR
sysctl.c SysCtl_setClock
sysctl.c SysCtl_setAuxClock
sysctl.c SysCtl_selectXTAL
sysctl.c SysCtl_selectXTALSingleEnded
sysctl.c SysCtl_selectOscSourceAuxPLL
sysctl.h SysCtl_setExternalOscMode
sysctl.h SysCtl_turnOnOsc

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Table 3-413. SYSCTL Registers to Driverlib Functions (continued)

File Driverlib Function
ETHERCATCLKCTL
sysctl.h SysCtl_setECatClk
CMCLKCTL
sysctl.h SysCtl_setCMClk
sysctl.h SysCtl_setEnetClk
CPUSYSLOCK1
sysctl.c SysCtl_lockSysConfig
CPUSYSLOCK2
-
PIEVERRADDR
sysctl.h SysCtl_getPIEVErrAddr
PCLKCR0
sysctl.h SysCtl_enablePeripheral
sysctl.h SysCtl_disablePeripheral
PCLKCR1
- See PCLKCR0
PCLKCR2
- See PCLKCR0
PCLKCR3
- See PCLKCR0
PCLKCR4
- See PCLKCR0
PCLKCR6
- See PCLKCR0
PCLKCR7
- See PCLKCR0
PCLKCR8
- See PCLKCR0
PCLKCR9
- See PCLKCR0
PCLKCR10
- See PCLKCR0
PCLKCR11
- See PCLKCR0
PCLKCR13
- See PCLKCR0
PCLKCR14
- See PCLKCR0
PCLKCR16
- See PCLKCR0
PCLKCR17
-
PCLKCR18
-
PCLKCR20

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Table 3-413. SYSCTL Registers to Driverlib Functions (continued)

File Driverlib Function
-
PCLKCR21
-
PCLKCR22
-
PCLKCR23
-
SIMRESET
sysctl.h SysCtl_simulateReset
LPMCR
sysctl.h SysCtl_enterIdleMode
sysctl.h SysCtl_enterStandbyMode
sysctl.h SysCtl_setStandbyQualificationPeriod
sysctl.h SysCtl_enableWatchdogStandbyWakeup
sysctl.h SysCtl_disableWatchdogStandbyWakeup
GPIOLPMSEL0
sysctl.h SysCtl_enableLPMWakeupPin
sysctl.h SysCtl_disableLPMWakeupPin
GPIOLPMSEL1
sysctl.h SysCtl_enableLPMWakeupPin
sysctl.h SysCtl_disableLPMWakeupPin
TMR2CLKCTL
cputimer.h CPUTimer_selectClockSource
sysctl.h SysCtl_setCputimer2Clk
RESCCLR
sysctl.h SysCtl_clearWatchdogResetStatus
RESC
sysctl.h SysCtl_getResetCause
sysctl.h SysCtl_clearResetCause
sysctl.h SysCtl_getWatchdogResetStatus
sysctl.h SysCtl_clearWatchdogResetStatus
MCANWAKESTATUS
sysctl.h SysCtl_isMCANWakeStatusSet
sysctl.h SysCtl_clearMCANWakeStatus
MCANWAKESTATUSCLR
sysctl.h SysCtl_clearMCANWakeStatus
CLA1TASKSRCSELLOCK
-
DMACHSRCSELLOCK
-
CLA1TASKSRCSEL1
cla.c CLA_setTriggerSource
CLA1TASKSRCSEL2
cla.c CLA_setTriggerSource
DMACHSRCSEL1

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Table 3-413. SYSCTL Registers to Driverlib Functions (continued)

File Driverlib Function
dma.c DMA_configMode
DMACHSRCSEL2
dma.c DMA_configMode
DEVCFGLOCK1
sysctl.h SysCtl_lockCPUSelectRegs
PARTIDL
sysctl.c SysCtl_getDeviceParametric
PARTIDH
sysctl.c SysCtl_getDeviceParametric
REVID
sysctl.h SysCtl_getDeviceRevision
PERCNF1
sysctl.h SysCtl_readADCWrapper
sysctl.h SysCtl_isPresentUSBPHY
FUSEERR
sysctl.h SysCtl_getEfuseError
SOFTPRES0
sysctl.h SysCtl_resetPeripheral
SOFTPRES1
- See SOFTPRES0
SOFTPRES2
- See SOFTPRES0
SOFTPRES3
- See SOFTPRES0
SOFTPRES4
- See SOFTPRES0
SOFTPRES6
- See SOFTPRES0
SOFTPRES7
- See SOFTPRES0
SOFTPRES8
- See SOFTPRES0
SOFTPRES9
- See SOFTPRES0
SOFTPRES10
- See SOFTPRES0
SOFTPRES11
- See SOFTPRES0
SOFTPRES13
- See SOFTPRES0
SOFTPRES14
- See SOFTPRES0
SOFTPRES16
- See SOFTPRES0
SOFTPRES17

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Table 3-413. SYSCTL Registers to Driverlib Functions (continued)

File Driverlib Function
-
SOFTPRES18
-
SOFTPRES20
-
SOFTPRES21
-
SOFTPRES23
-
CPUSEL0
sysctl.h SysCtl_selectCPUForPeripheralInstance
sysctl.h SysCtl_selectCPUForPeripheral
CPUSEL1
- See CPUSEL0
CPUSEL2
- See CPUSEL0
CPUSEL4
- See CPUSEL0
CPUSEL5
- See CPUSEL0
CPUSEL6
- See CPUSEL0
CPUSEL7
- See CPUSEL0
CPUSEL8
- See CPUSEL0
CPUSEL9
- See CPUSEL0
CPUSEL11
- See CPUSEL0
CPUSEL12
- See CPUSEL0
CPUSEL14
- See CPUSEL0
CPUSEL15
- See CPUSEL0
CPUSEL16
- See CPUSEL0
CPUSEL18
-
CPUSEL25
-
CPU2RESCTL
sysctl.c SysCtl_controlCPU2Reset
RSTSTAT

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Table 3-413. SYSCTL Registers to Driverlib Functions (continued)

File Driverlib Function
sysctl.h SysCtl_isCPU2Reset
sysctl.h SysCtl_getCPU2ResetStatus
sysctl.h SysCtl_clearCPU2ResetStatus
LPMSTAT
sysctl.h SysCtl_getCPU2LPMStatus
USBTYPE
sysctl.c SysCtl_configureType
sysctl.c SysCtl_isConfigTypeLocked
ECAPTYPE
sysctl.c SysCtl_configureType
sysctl.c SysCtl_isConfigTypeLocked
SDFMTYPE
sysctl.c SysCtl_configureType
sysctl.c SysCtl_isConfigTypeLocked
MEMMAPTYPE
sysctl.c SysCtl_configureType
sysctl.c SysCtl_isConfigTypeLocked
ADCA_AC
-
ADCB_AC
-
ADCC_AC
-
ADCD_AC
-
CMPSS1_AC
-
CMPSS2_AC
-
CMPSS3_AC
-
CMPSS4_AC
-
CMPSS5_AC
-
CMPSS6_AC
-
CMPSS7_AC
-
CMPSS8_AC
-
DACA_AC
-
DACB_AC
-

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Table 3-413. SYSCTL Registers to Driverlib Functions (continued)

File Driverlib Function
DACC_AC
-
EPWM1_AC
-
EPWM2_AC
-
EPWM3_AC
-
EPWM4_AC
-
EPWM5_AC
-
EPWM6_AC
-
EPWM7_AC
-
EPWM8_AC
-
EPWM9_AC
-
EPWM10_AC
-
EPWM11_AC
-
EPWM12_AC
-
EPWM13_AC
-
EPWM14_AC
-
EPWM15_AC
-
EPWM16_AC
-
EQEP1_AC
-
EQEP2_AC
-
EQEP3_AC
-
ECAP1_AC
-
ECAP2_AC
-
ECAP3_AC

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Table 3-413. SYSCTL Registers to Driverlib Functions (continued)

File Driverlib Function
-
ECAP4_AC
-
ECAP5_AC
-
ECAP6_AC
-
ECAP7_AC
-
SDFM1_AC
-
SDFM2_AC
-
CLB1_AC
-
CLB2_AC
-
CLB3_AC
-
CLB4_AC
-
CLB5_AC
-
CLB6_AC
-
CLB7_AC
-
CLB8_AC
-
SPIA_AC
-
SPIB_AC
-
SPIC_AC
-
SPID_AC
-
PMBUS_A_AC
-
CAN_A_AC
-
CAN_B_AC
-
MCBSPA_AC
-

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Table 3-413. SYSCTL Registers to Driverlib Functions (continued)

File Driverlib Function
MCBSPB_AC
-
USBA_AC
-
HRPWM_AC
-
ETHERCAT_AC
-
FSIATX_AC
-
FSIARX_AC
-
FSIBTX_AC
-
FSIBRX_AC
-
FSICRX_AC
-
FSIDRX_AC
-
FSIERX_AC
-
FSIFRX_AC
-
FSIGRX_AC
-
FSIHRX_AC
-
MCANA_AC
-
PERIPH_AC_LOCK
sysctl.h SysCtl_lockAccessControlRegs
CMRESCTL
sysctl.c SysCtl_controlCMReset
sysctl.h SysCtl_isCMReset
CMTOCPU1NMICTL
sysctl.h SysCtl_enableCMtoCPUNMI
sysctl.h SysCtl_disableCMtoCPUNMI
sysctl.h SysCtl_getCMtoCPUNMI
CMTOCPU1INTCTL
sysctl.h SysCtl_enableCMtoCPUInterrupt
sysctl.h SysCtl_disableCMtoCPUInterrupt
sysctl.h SysCtl_getCMtoCPUInterrupt
PALLOCATE0
sysctl.h SysCtl_allocateSharedPeripheral

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Table 3-413. SYSCTL Registers to Driverlib Functions (continued)

File Driverlib Function
CM_CONF_REGS_LOCK
sysctl.h SysCtl_lockCMConfig
CM_STATUS_INT_FLG
sysctl.h SysCtl_getCMInterruptStatus
CM_STATUS_INT_CLR
sysctl.h SysCtl_clearCMInterruptStatus
CM_STATUS_INT_SET
sysctl.h SysCtl_setCMInterruptStatus
CM_STATUS_MASK
sysctl.h SysCtl_getCMInterruptStatusMask
sysctl.h SysCtl_setCMInterruptStatusMask
SYS_ERR_INT_FLG
sysctl.h SysCtl_getInterruptStatus
SYS_ERR_INT_CLR
sysctl.h SysCtl_clearInterruptStatus
SYS_ERR_INT_SET
sysctl.h SysCtl_setInterruptStatus
SYS_ERR_MASK
sysctl.h SysCtl_getInterruptStatusMask
sysctl.h SysCtl_setInterruptStatusMask
SYNCSELECT
sysctl.h SysCtl_setSyncOutputConfig
ADCSOCOUTSELECT
sysctl.h SysCtl_enableExtADCSOCSource
sysctl.h SysCtl_disableExtADCSOCSource
SYNCSOCLOCK
sysctl.h SysCtl_lockExtADCSOCSelect
sysctl.h SysCtl_lockSyncSelect

3.16.23.8 WWD Registers to Driverlib Functions

Table 3-414. WWD Registers to Driverlib Functions
File Driverlib Function
SCSR
sysctl.h SysCtl_setWatchdogMode
sysctl.h SysCtl_isWatchdogInterruptActive
sysctl.h SysCtl_clearWatchdogOverride
WDCNTR
sysctl.h SysCtl_getWatchdogCounterValue
WDKEY
sysctl.h SysCtl_serviceWatchdog
sysctl.h SysCtl_enableWatchdogReset
sysctl.h SysCtl_resetWatchdog
WDCR
sysctl.h SysCtl_resetDevice
sysctl.h SysCtl_disableWatchdog

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Table 3-414. WWD Registers to Driverlib Functions (continued)

File Driverlib Function
sysctl.h SysCtl_enableWatchdog
sysctl.h SysCtl_setWatchdogPredivider
sysctl.h SysCtl_setWatchdogPrescaler
WDWCR
sysctl.h SysCtl_setWatchdogWindowValue

3.16.23.9 XINT Registers to Driverlib Functions

Table 3-415. XINT Registers to Driverlib Functions
File Driverlib Function
1CR
gpio.c GPIO_setInterruptPin
gpio.h GPIO_setInterruptType
gpio.h GPIO_getInterruptType
gpio.h GPIO_enableInterrupt
gpio.h GPIO_disableInterrupt
gpio.h GPIO_getInterruptCounter
2CR
- See 1CR
3CR
- See 1CR
4CR
- See 1CR
5CR
- See 1CR
1CTR
gpio.h GPIO_getInterruptCounter
2CTR
-
3CTR
-

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www.ti.com C28x Processor

Chapter 4
C28x Processor

This chapter contains a short description of the C28x processor and extended instruction sets.
Further information can be found in the following documents:
• TMS320C28x CPU and Instruction Set Reference Guide
• TMS320C28x Extended Instruction Sets Technical Reference Manual
• Accelerators: Enhancing the Capabilities of the C2000 MCU Family Technical Brief
• TMS320C28x FPU Primer Application Report

4.1 Introduction...............................................................................................................................................................698
4.2 C28X Related Collateral........................................................................................................................................... 698
4.3 Features.....................................................................................................................................................................698
4.4 Floating-Point Unit....................................................................................................................................................698
4.5 Trigonometric Math Unit (TMU)............................................................................................................................... 699
4.6 VCRC Unit..................................................................................................................................................................699

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4.1 Introduction
The C28x CPU is a 32-bit fixed-point processor. This device draws from the best features of digital signal
processing, reduced instruction set computing (RISC), microcontroller architectures, firmware, and tool sets.
For more information on CPU architecture and instruction set, see the TMS320C28x CPU and Instruction Set
Reference Guide.
4.2 C28X Related Collateral

Foundational Materials
• C2000 Academy - C28x
• C2000 C28x Optimization Guide
• C2000 Software Guide
• Enhancing the Computational Performance of the C2000™ Microcontroller Family Application Report

Getting Started Materials

• C2000 Multicore Development User Guide
• C2000Ware - CLAMath
• C2000Ware - FPU Fast RTS
• C2000Ware - FPU Library
• C2000Ware - Fast Integer Division
• C2000Ware - Fixed Point Library
• C2000Ware - IQMath
• C2000Ware - VCU Library
• C2000Ware Libraries Overview
• CRC Engines in C2000 Devices Application Report
• TMS320C28x Extended Instruction Sets Application Report
• TMS320C28x FPU Primer Application Report

Expert Materials
• Fast Integer Division - A Differentiated Offering From C2000 Product Family Application Report
4.3 Features
The CPU features include a modified Harvard architecture and circular addressing. The RISC features
are single-cycle instruction execution, register-to-register operations, and modified Harvard architecture. The
microcontroller features include ease of use through an intuitive instruction set, byte packing and unpacking,
and bit manipulation. The modified Harvard architecture of the CPU enables instruction and data fetches to be
performed in parallel. The CPU can read instructions and data while it writes data simultaneously to maintain the
single-cycle instruction operation across the pipeline.
4.4 Floating-Point Unit
The C28x plus floating-point (C28x+FPU64) processor extends the capabilities of the C28x fixed-point CPU by
adding registers and instructions to support IEEE single-precision and double-precision floating point operations.
Devices with the C28x+FPU64 include the standard C28x register set plus an additional set of floating-point unit
registers. The additional floating-point unit registers are the following:
• Eight floating-point result registers, RnH (where n = 0–7)
• Floating-point Status Register (STF)
• Repeat Block Register (RB)
All of the floating-point registers, except the repeat block register, are shadowed. This shadowing can be used in
high-priority interrupts for fast context save and restore of the floating-point registers.
For more information, see the TMS320C28x Extended Instruction Sets Technical Reference Manual.

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4.5 Trigonometric Math Unit (TMU)

The trigonometric math unit (TMU) extends the capabilities of a C28x+FPU64 by adding instructions and
leveraging existing FPU64 instructions to speed up the execution of common trigonometric and arithmetic
operations listed in Table 4-1.
Table 4-1. TMU Supported Instructions
Instructions C Equivalent Operation Pipeline Cycles
MPY2PIF32/64 RaH,RbH a = b * 2pi 2/3
DIV2PIF32/64 RaH,RbH a = b / 2pi 2/3
DIVF32/64 RaH,RbH,RcH a = b/c 5
SQRTF32/64 RaH,RbH a = sqrt(b) 5
SINPUF32/64 RaH,RbH a = sin(b*2pi) 4
COSPUF32/64 RaH,RbH a = cos(b*2pi) 4
ATANPUF32/64 RaH,RbH a = atan(b)/2pi 4
QUADF32/64 RaH,RbH,RcH,RdH Operation to assist in calculating ATANPU2 5

No changes have been made to existing instructions, pipeline or memory bus architecture. All TMU instructions
use the existing FPU register set (R0H to R7H) to carry out their operations.
For more information, see the TMS320C28x Extended Instruction Sets Technical Reference Manual.
4.6 VCRC Unit
Cyclic redundancy check (CRC) algorithms provide a straightforward method for verifying data integrity over
large data blocks, communication packets, or code sections. The C28x+VCRC can perform 8-bit, 16-bit, 24-bit,
and 32-bit CRCs. A CRC result register contains the current CRC, which is updated whenever a CRC instruction
is executed.
The following are the CRC polynomials used by the CRC calculation logic of VCRC:
• CRC8 polynomial = 0x07
• CRC16 polynomial1 = 0x8005
• CRC16 polynomial2 = 0x1021
• CRC24 polynomial = 0x5d6dcb
• CRC32 polynomial1 = 0x04c11db7
• CRC32 polynomial2 = 0x1edc6f41
This module can calculate CRCs for a byte of data in a single cycle. The CRC calculation for CRC8, CRC16,
CRC24 and CRC32 is done byte-wise (instead of computing on a complete 16-bit or 32-bit data read by the
C28x core) to match the byte-wise computation requirement mandated by various standards.
The VCRC Unit also allows the user to provide the size (1b-32b) and value of any polynomial to fit custom CRC
requirements. The CRC execution time increases to 3 cycles when using a custom polynomial.
For more information, see the TMS320C28x Extended Instruction Sets Technical Reference Manual.

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www.ti.com ROM Code and Peripheral Booting

Chapter 5
ROM Code and Peripheral Booting

This chapter describes the boot flow and functionality of the CPU1, CPU2, and Connectivity Manager (CM)
subsystems.

5.1 Introduction...............................................................................................................................................................702
5.2 Device Boot Sequence.............................................................................................................................................703
5.3 Device Boot Modes.................................................................................................................................................. 704
5.4 Device Boot Configurations.................................................................................................................................... 705
5.5 Device Boot Flow Diagrams.....................................................................................................................................711
5.6 Device Reset and Exception Handling................................................................................................................... 716
5.7 Boot ROM Description............................................................................................................................................. 718
5.8 Application Notes for Using the Bootloaders........................................................................................................758
5.9 Software.................................................................................................................................................................... 762

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5.1 Introduction
The purpose of this chapter is to explain the boot read-only memory (ROM) code functionality for CPU1, CPU2,
and CM cores, including the boot procedure. It also discusses the functions and features of the boot ROM
code, and provides details about the ROM memory map contents. On every reset, the device executes a boot
sequence in the ROM depending on the reset type and boot configuration. This sequence will initialize the
device to run the application code. For CPU1, the boot ROM also contains peripheral bootloaders which can be
used to load an application into RAM. These bootloaders can be disabled for safety or security purposes.
Refer to Table 5-1 for details on available boot features across CPU1, CPU2, and CM. Additionally, Table 5-2
shows the sizes of the various ROMs on the device.
Table 5-1. Boot System Overview
Boot Feature CPU1 (Master) CPU2 CM
Initiate boot process Device Reset CPU1 Application CPU1 Application
Boot mode selection GPIOs IPC Register IPC Register
Supported boot modes:
• Flash boot
• Secure Flash boot Yes Yes Yes
• RAM boot

Boot to User OTP No Yes Yes

Copy from IPC Message RAM and boot to RAM No Yes Yes
Peripheral boot loader support Yes No No

Table 5-2. ROM Memory

ROM CPU1 Size CPU2 Size CM Size
Unsecure boot ROM 192 KB 64 KB 64 KB
Secure ROM 64 KB 64 KB 32 KB
CLA data ROM 8 KB 8 KB N/A

5.1.1 ROM Related Collateral

Foundational Materials
• Bootloading 101 (Video)

Getting Started Materials

• Secure BOOT On C2000 Device Application Report

Expert Materials
• C2000 Software Controlled Firmware Update Process Application Report

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5.2 Device Boot Sequence

The boot sequence describes the general boot ROM procedure each time a CPU core is reset. CPU1 is the
master and always boots first. Once CPU1 boots to the application, then the user's application code in CPU1
can configure CPU2/CM boot IPC registers and release CPU2/CM from reset to boot. Table 5-3, Table 5-4, and
Table 5-5 detail the general overview of the boot-up procedures for each core.
During boot, each CPU's boot ROM code updates a boot status location in RAM that details the actions taken
during this process. Additionally, CPU2 writes the boot status to the CPU2TOCPU1IPCBOOTSTS register and
CM writes to CMTOCPU1IPCBOOTSTS to communicate the statuses to CPU1.
Refer to Section 5.7.11 for more details.
Table 5-3. CPU1 Boot ROM Sequence
Step CPU1 Action
After reset, check for HWBIST reset. If it is a HWBIST reset, immediately branch and return to the user application. If it
1
is not a HWBIST reset, then continue boot and check the FUSE error register for any errors and handle accordingly.
2 Clock configuration and Flash power-up
3 Peripheral trimming and device configuration registers are loaded from OTP.
4 On power-on reset (POR), all CPU1 RAMs are initialized.
5 Non-maskable interrupt (NMI) handling is enabled and DCSM initialization is performed.
6 Device calibration is performed; trimming the specified peripherals with set OTP values.
7 Determine if polling the GPIO pins are needed for determining the boot mode and, if so, read the boot mode GPIO pins
to determine the boot mode to run.
Based on the boot mode and options, the appropriate boot sequence is executed. Refer to Section 5.5.1 for a flow chart
8
of the CPU1 boot sequences.

Table 5-4. CPU2 Boot ROM Sequence

Step CPU2 Action
1 CPU2 is released from reset by CPU1 application.
Once CPU1TOCPU2IPCFLG0 is set, read the CPU1TOCPU2IPCBOOTMODE register. If it is not set correctly or has
2 an invalid value, the IPC error command is sent to CPU1 and the CPU2 core will enter an infinite loop and will not
continue booting until the user corrects the register values and reset the CPU2.
3 Flash power-up
4 On POR, all CPU2 RAMs are initialized.
5 NMI handling is enabled.
Based on the boot mode set in CPU1TOCPU2IPCBOOTMODE register, CPU2 either enters "wait for command" mode
6 to wait for a future CPU1 boot mode command or CPU2 executes the requested boot sequence. Refer to Section 5.5.2
for a flow chart of the CPU2 boot sequences.

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Table 5-5. CM Boot ROM Sequence

Step CM Action
1 CM is released from reset by the CPU1 application.
Once CPU1TOCMIPCFLG0 is set, read the CPU1TOCMIPCBOOTMODE register.If it is not set correctly or has an
2 invalid value, the IPC error command is sent to CPU1 and the CM will enter an infinite loop and will not continue
booting until the user corrects the register values and reset the CM.
3 Flash power-up
4 On POR, all CM RAMs are initialized.
5 NMI handling is enabled.
Based on the boot mode set in CPU1TOCPU2IPCBOOTMODE register, CM either enters "wait for command" mode to
6 wait for a future CPU1 boot mode command or CM executes the requested boot sequence. Refer to Section 5.5.3 for a
flow chart of the CM boot sequences.

5.3 Device Boot Modes

This section explains the default boot modes, as well as all the available boot modes supported on this device.
The CPU1 boot ROM uses the boot mode select, general purpose input/output (GPIO) pins to determine the
boot mode configuration. CPU2 boot ROM uses the CPU1TOCPU2IPCBOOTMODE register to determine the
boot mode configuration and CM boot ROM uses the CPU1TOCMIPCBOOTMODE register to determine the
boot mode configuration.
Table 5-6 shows the CPU1 boot mode options available for selection by the default boot mode select pins. Users
have the option to program the device to customize the boot modes selectable in the boot-up table as well as the
boot mode select pin GPIOs used.
All the available boot modes on the device are described in Table 5-8.
Table 5-6. Device Default Boot Modes for CPU1
GPIO72 GPIO84
Boot Mode
(Default boot mode select pin 1) (Default boot mode select pin 0)
Parallel IO 0 0
SCI / Wait Boot(1) 0 1
CAN 1 0
Flash / USB(2) 1 1

(1) SCI boot mode can be used as a wait boot mode as long as SCI continues to wait for an 'A' or 'a' during the SCI autobaud lock
process.
(2) On an unprogrammed device, selecting Flash boot when the default Flash entry address is unprogrammed switches the boot mode
from Flash boot to USB boot. See Table 5-7 for more details.

Table 5-7. CPU1 Flash-to-USB Boot Decision Table

Value at Flash Entry Point Address Reason for Value Realized Boot Mode
0x00000000 Flash is locked/secured Boot to Flash
0xFFFFFFFF Flash is not programmed USB Boot
Any other value Flash is programmed Boot to Flash

Note
The switch of Flash boot mode to USB boot mode when Flash is not programmed is only available
as part of the default boot mode table on an unprogrammed device. Once a custom boot table is
programmed in OTP or RAM, a selection of Flash boot mode does not switch to USB boot even when
Flash is unprogrammed.

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Table 5-8. All Available Boot Modes

Boot Mode CPU Support Details
Parallel IO CPU1
SCI / Wait CPU1
CAN CPU1
Flash CPU1, CPU2, CM
Wait CPU1, CPU2, CM Refer to Section 5.7.7 for functional details of the boot modes.
RAM CPU1, CPU2, CM
SPI CPU1 Refer to Section 5.7.8 for boot table values and GPIOs for the boot modes.
I2C CPU1
USB CPU1
Secure Flash CPU1, CPU2, CM
User OTP CPU2, CM
IPC Message Copy to RAM CPU2, CM

Note
All the peripheral boot modes that are supported use the first instance of the peripheral module (SCIA,
SPIA, I2CA, CANA, and so forth). Whenever these boot modes are referred to in this chapter, such as
SCI boot, it is actually referring to the first module instance, which means the SCI boot on the SCIA
port. The same applies to the other peripheral boots.

5.4 Device Boot Configurations

This section details what boot configurations are available and how to configure them. This device supports
from 0 boot mode select pins up to 3 boot mode select pins as well as from 1 configured boot mode up to 8
configured boot modes.
To change and configure the device from the default settings to custom settings for your application, use the
following process:
1. Determine all the various ways you want application to be able to boot. (For example: Primary boot option of
Flash boot for your main application, secondary boot option of CAN boot for firmware updates, tertiary boot
option of SCI boot for debugging, etc)
2. Based on the number of boot modes needed, determine how many boot mode select pins (BMSPs) are
required to select between your selected boot modes. (For example: 2 BMSPs are required to select
between 3 boot mode options)
3. Assign the required BMSPs to a physical GPIO pin. (For example, BMSP0 to GPIO50, BMSP1 to GPIO51,
and BMSP2 left as default which is disabled). Refer to Section 5.4.1 for all the details on performing these
configurations.
4. Assign the determined boot mode definitions to indexes in your custom boot table that correlate to
the decoded value of the BMSPs. For example, BOOTDEF0=Boot to Flash, BOOTDEF1=CAN Boot,
BOOTDEF2=SCI Boot; all other BOOTDEFx are left as default/nothing). Refer to Section 5.4.2 for all the
details on setting up and configuring the custom boot mode table.
Additionally, Section 5.4.3 provides some example use cases on how to configure the BMSPs and custom boot
tables.

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5.4.1 Configuring Boot Mode Pins for CPU1

This section explains how the boot mode select pins can be customized by the user, by programming the
BOOTPINCONFIG location (refer to Table 5-9) in the user-configurable dual-zone security module (DCSM)
OTP. The location in the DCSM OTP is Z1-BOOTPINCONFIG or Z2-BOOTPINCONFIG. When debugging,
EMUBOOTPINCONFIG is the emulation equivalent of Z1-BOOTPINCONFIG/Z2-BOOTPINCONFIG, and can be
programmed to experiment with different boot modes without writing to OTP. The device can be programmed to
use 0, 1, 2, or 3 boot mode select pins as needed.

Note
When using Z2-BOOTPINCONFIG, the configurations programmed in this location will take priority
over the configurations in Z1-BOOTPINCONFIG. It is recommended to use Z1-BOOTPINCONFIG
first and then if OTP configurations need to be altered, switch to using Z2-BOOTPINCONFIG.

Table 5-9. CPU1 BOOTPINCONFIG Bit Fields

Bit Name Description
Write 0x5A to these 8-bits to tell the boot ROM code that the bits in this register are
valid
31:24 Key
For EMUBOOTPINCONFIG only, write 0xA5 to emulate the standalone boot flow and
use the BMSPs/OTP BOOTDEF table
23:16 Boot Mode Select Pin 2 (BMSP2) Refer to BMSP0 description except for BMSP2
15:8 Boot Mode Select Pin 1 (BMSP1) Refer to BMSP0 description except for BMSP1
Set to the GPIO pin to be used during boot (up to 255).
7:0 Boot Mode Select Pin 0 (BMSP0) 0x0 = GPIO0; 0x01 = GPIO1 and so on
Writing 0xFF disables BMSP0 and this pin is no longer used to select the boot mode.

Note
The following GPIOs cannot be used as a BMSP. If selected for a particular BMSP, the boot ROM
automatically selects the factory default GPIO (the factory default for BMSP2 is 0xFF, which disables
the BMSP).
• GPIO 42 and GPIO 43
• GPIO 169 to 255

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Table 5-10. CPU1 Standalone Boot Mode Select Pin Decoding

BOOTPIN_CONFIG
BMSP0 BMSP1 BMSP2 Realized Boot Mode
Key
!= 0x5A Don’t Care Don’t Care Don’t Care Boot as defined by the factory default BMSPs
Boot as defined in the boot table for boot mode 0
0xFF 0xFF 0xFF
(All BMSPs disabled)
Boot as defined by the value of BMSP0
Valid GPIO 0xFF 0xFF
(BMSP1 and BMSP2 disabled)
Boot as defined by the value of BMSP1
0xFF Valid GPIO 0xFF
(BMSP0 and BMSP2 disabled)
Boot as defined by the value of BMSP2
0xFF 0xFF Valid GPIO
(BMSP0 and BMSP1 disabled)
Boot as defined by the values of BMSP0 and
Valid GPIO Valid GPIO 0xFF BMSP1
(BMSP2 disabled)
Boot as defined by the values of BMSP0 and
Valid GPIO 0xFF Valid GPIO BMSP2
(BMSP1 disabled)
= 0x5A
Boot as defined by the values of BMSP1 and
0xFF Valid GPIO Valid GPIO BMSP2
(BMSP0 disabled)
Boot as defined by the values of BMSP0, BMSP1,
Valid GPIO Valid GPIO Valid GPIO
and BMSP2
BMSP0 is reset to the factory default BMSP0 GPIO
Invalid GPIO Valid GPIO Valid GPIO Boot as defined by the values of BMSP0, BMSP1,
and BMSP2
BMSP1 is reset to the factory default BMSP1 GPIO
Valid GPIO Invalid GPIO Valid GPIO Boot as defined by the values of BMSP0, BMSP1,
and BMSP2
BMSP2 is reset to the factory default state, which is
disabled
Valid GPIO Valid GPIO Invalid GPIO
Boot as defined by the values of BMSP0 and
BMSP1

Note
When decoding the boot mode, BMSP0 is the least-significant-bit and BMSP2 is the most-significant-
bit of the boot table index value. It is recommended when disabling BMSPs to start with disabling
BMSP2. For example, in an instance when only using BMSP2 (BMSP1 and BMSP0 are disabled),
then only the boot table indexes of 0 and 4 will be selectable. In the instance when using only BMSP0,
then the selectable boot table indexes are 0 and 1.

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5.4.2 Configuring Boot Mode Table Options for CPU1

This section explains how to configure the boot definition table, BOOTDEF, for CPU1. The 64-bit location is
located in user-configurable DCSM OTP in the Z1-BOOTDEF-LOW and Z1-BOOTDEF-HIGH locations. When
debugging, EMUBOOTDEF-LOW and EMUBOOTDEF-HIGH are the emulation equivalents of Z1-BOOTDEF-
LOW and Z1-BOOTDEF-HIGH, and can be programmed to experiment with different boot mode options without
writing to OTP. The range of customization to the boot definition table depends on how many boot mode select
pins (BMSP) are being used. For example, 0 BMSPs equals to 1 table entry, 1 BMSP equals to 2 table entries, 2
BMSPs equals to 4 table entries, and 3 BMSPs equals to 8 table entries. Refer to Section 5.4.3 for examples on
how to setup the BOOTPIN_CONFIG and BOOTDEF values.

Note
The locations Z2-BOOTDEF-LOW and Z2-BOOTDEF-HIGH will be used instead of Z1-BOOTDEF-
LOW and Z1-BOOTDEF-HIGH locations when Z2-BOOTPINCONFIG is configured. Refer to Section
5.4.1 for more details on BOOTPIN_CONFIG usage.

Table 5-11. CPU1 BOOTDEF Bit Fields

BOOTDEF Name Byte Position Name Description
Set the boot mode for index 0 of the boot table.

Different boot modes and their options can include, for

example, a boot mode that uses different GPIOs for
a specific bootloader or a different Flash entry point
BOOT_DEF0 7:0 BOOT_DEF0 Mode/Options address. Any unsupported boot mode will cause the
device to either go to wait boot or boot to Flash.

Refer to Section 5.7.8 for valid BOOTDEF values to set

in the table.
BOOT_DEF1 15:8 BOOT_DEF1 Mode/Options
BOOT_DEF2 23:16 BOOT_DEF2 Mode/Options
BOOT_DEF3 31:24 BOOT_DEF3 Mode/Options
BOOT_DEF4 39:32 BOOT_DEF4 Mode/Options Refer to BOOT_DEF0 description
BOOT_DEF5 47:40 BOOT_DEF5 Mode/Options
BOOT_DEF6 55:48 BOOT_DEF6 Mode/Options
BOOT_DEF7 63:56 BOOT_DEF7 Mode/Options

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5.4.3 Boot Mode Example Use Cases

This section demonstrates some use cases for configuring the boot mode select pins and boot modes.
5.4.3.1 Zero Boot Mode Select Pins
This use case demonstrates a scenario for an application that does not use any boot mode select pins and
always has the device boot to Flash.
1. Program the BOOTPIN_CONFIG location in OTP as follows:
• Set BOOTPIN_CONFIG.BMSP0 to 0xFF
• Set BOOTPIN_CONFIG.BMSP1 to 0xFF
• Set BOOTPIN_CONFIG.BMSP2 to 0xFF
• Set BOOTPIN_CONFIG.KEY to 0x5A for boot ROM to treat these register bits as valid and use the
custom boot table.
2. Program the BOOTDEF location options for the device. This essentially sets up a device-specific boot mode
table. Refer to Section 5.7.8 for valid BOOTDEF values to set in the table.
• Set BOOTDEF.BOOTDEF0 to 0x03 for booting to Flash (entry address option 0). This sets Flash boot to
boot table index 0.
• Refer to Section 5.7.3 for the available Flash entry points.
Table 5-12. Zero Boot Pin Boot Table Result
Boot Mode Table Number Boot Mode

0 Flash Boot (0x03)

5.4.3.2 One Boot Mode Select Pin

This use case demonstrates a scenario for an application using one boot mode select pin to select between
booting to Flash or using CAN boot.
1. Program the BOOTPIN_CONFIG location in OTP as follows:
• Set BOOTPIN_CONFIG.BMSP0 to a user specified GPIO, such as 0x0 for GPIO0
• Set BOOTPIN_CONFIG.BMSP1 to 0xFF
• Set BOOTPIN_CONFIG.BMSP2 to 0xFF
• Set BOOTPIN_CONFIG.KEY to 0x5A for boot ROM to treat these register bits as valid and use the
custom boot table.
2. Program the BOOTDEF location options for the device. This essentially sets up a device-specific boot mode
table. Refer to Section 5.7.8 for valid BOOTDEF values to set in the table.
• Set BOOTDEF.BOOTDEF0 to 0x02 for CAN booting. This sets CAN boot to boot table index 0.
• Set BOOTDEF.BOOTDEF1 to 0x03 for booting to Flash (entry address option 0). This sets Flash boot to
boot table index 1.
Table 5-13. One Boot Pin Boot Table Result
Boot Mode Table Number Boot Mode

0 CAN Boot (0x02)

1 Flash Boot (0x03)

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5.4.3.3 Three Boot Mode Select Pins

This use case demonstrates a scenario for an application using three boot mode select pins to select between
various boot modes in the custom boot table.
1. Program the BOOTPIN_CONFIG location in OTP as follows:
• Set BOOTPIN_CONFIG.BMSP0 to a user specified GPIO, such as 0x0 for GPIO0
• Set BOOTPIN_CONFIG.BMSP1 to a user specified GPIO, such as 0x1 for GPIO1
• Set BOOTPIN_CONFIG.BMSP2 to a user specified GPIO, such as 0x2 for GPIO2
• Set BOOTPIN_CONFIG.KEY to 0x5A for boot ROM to treat these register bits as valid and use the
custom boot table.
2. Program the BOOTDEF location options for the device. This essentially sets up a device-specific boot mode
table. Refer to Section 5.7.8 for valid BOOTDEF values to set in the table.
• Set BOOTDEF.BOOTDEF0 to 0x02 for CAN booting. This sets CAN boot to boot table index 0.
• Set BOOTDEF.BOOTDEF1 to 0x03 for booting to Flash (entry address option 0). This sets Flash boot to
boot table index 1.
• Set BOOTDEF.BOOTDEF2 to 0x24 for booting to wait boot (alternate option). This sets wait boot to boot
table index 2.
• Set BOOTDEF.BOOTDEF3 to 0x66 for SPI booting (alternate GPIO option 3). This sets SPI boot to boot
table index 3.
• Set BOOTDEF.BOOTDEF4 to 0x43 for booting to Flash (entry address option 2). This sets Flash boot to
boot table index 4.
• Set BOOTDEF.BOOTDEF5 to 0x09 for USB booting. This sets USB boot to boot table index 5.
Table 5-14. Three Boot Pins Boot Table Result
Boot Mode Table Number Boot Mode

0 CAN Boot (0x02)

1 Flash Boot (0x03)

2 Wait Boot - Alt (0x24)

3 SPI - Alt3 (0x66)

4 Flash Boot - Alt2 (0x43)

5 USB Boot (0x09)

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5.5 Device Boot Flow Diagrams

This section details the boot flow diagrams for CPU1, CPU2, and CM.
5.5.1 CPU1 Boot Flow
Upon reset, CPU1 follows the boot flow shown in Figure 5-1. Depending on whether a JTAG debugger is
connected to the device, CPU1 will either continue booting following the emulation boot flow or standalone
boot flow. Figure 5-2 shows the emulation boot flow when JTAG debugger is connected. Figure 5-3 shows the
standalone boot flow when no JTAG debugger is connected to the device.
Reset

CPU1 Boot Start

HWBIST
Branch to Application Reset Cause

All Other
Resets

Disable Watchdog

Configure Clock Divider

Any other resets POR or XRS
Reset Cause Power up Flash
Device Configuration

XRS
Clear boot ROM Stack to zero Reset Cause

POR

RAM Initialization
Enable NMI
(all CPU1 RAMS)

DCSM Initialization

POR Configure If set, Enable

Check Z2/Z1
Reset Cause SYSPLL and switch
GPREG2
to PLL

All other Not

Resets Configured
PLL Failed
To Lock PLL Locked
PLL Run Memory Power On Self-Test

Disable SYSPLL and RAM Initialization

Enable pull ups on unbonded IOs
switch to INTOSC (all CPU1 RAMs)

Device
Calibration

Clear POR/XRS reset

causes

No Yes
Is Debugger
Standalone Boot Emulation Boot
Connected?

Figure 5-1. CPU1 Device Boot Flow

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Emulation Boot Mode Start

Read EMU boot locations:

EMUBOOTPINCONFIG
EMUBOOTDEF

Unsupported
(=0xA5) Check Key
Emulate Wait
EMU_BOOTPIN_
Standalone Boot Boot
CONFIG_KEY

(=0x5A)

Get EMU Configurable user boot

mode options

Use BOOTPINCONFIG to determine

boot mode select GPIOs and read
those pins

Supported Unsupported
Boot Mode Decode Boot Mode
BOOTDEF options for Wait Boot
boot mode

Is Yes Run Failed

Secure Flash secure flash Halt Debugger
Boot? calculation

No

Start the peripheral loader process or

set memory address to branch Passed

Enable
Watchdog

Branch to Application
Code

Figure 5-2. CPU1 Emulation Boot Flow

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Standalone Boot Mode Start

Read OTP loaded registers:

Z2-BOOTPINCONFIG

Any Other
Check Z2 Value Read OTP loaded registers:
OTP_BOOTPIN_
Z1-BOOTPINCONFIG
CONFIG_KEY

Any Other
Check Z1 Value Read factory default two boot mode
OTP_BOOTPIN_
select GPIO pins
(=0x5A) CONFIG_KEY

(=0x5A) Decode boot mode from pins

Use Z2 registers: Use Z1 registers:

Z2-BOOTPINCONFIG Z1-BOOTPINCONFIG
Z2-BOOTDEF Z1-BOOTDEF

Yes
Is flash boot?

Use BOOTPINCONFIG to determine

boot mode select GPIOs and read
those pins Is flash entry No
Yes
address
programmed?

No
Unsupported Boot
Mode Decode
BOOTDEF table
for boot mode Set boot mode to USB boot

Start the peripheral loader process or

Flash Boot set address to branch
Supported Boot
Mode

Enable
Watchdog

No Is Yes Run Failed Enable Watchdog

Secure Flash secure flash
and reset Branch to Application
Boot? calculation
Code

Start the peripheral loader process or Passed

set address to branch

Enable
Watchdog

Branch to Application
Code

Figure 5-3. CPU1 Standalone Boot Flow

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5.5.2 CPU2 Boot Flow

Upon reset, CPU2 follows the boot flow shown in Figure 5-4. CPU2 only boots once configured and released
from reset by CPU1. Refer to Section 5.7.2 for more details.
XRS

POR CPU1 SYSRSn

Security (SCC)

CPU2
HWBIST Held in Reset
Reset
Software Release Request
Application Releases from CPU1
CPU2 from Reset
Debugger
CPU2 Boot Start
Reset

All other
Brand to HWBIST resets
Reset Cause
Application

Disable Watchdog

Wait for CPU1 to set IPCFLG0

Send IPC command No Is register Read

to CPU1 and wait. configured CPU1TOCPU2IPCBOOTMODE
(CPU1 must reset CPU2) correctly? Register

Yes

POR or
XRS
Reset Cause Flash Power Up

All other resets

XRS
Clear boot ROM Stack to zero Reset Cause

POR

RAM Initialization
Clear POR reset cause Enable NMI
(CPU2 RAMs)

CPU1 set IPCFLG0

Wait mode Wait in loop

Read boot mode
for IPC Flag

Other boot
Failed
mode Send IPC notification to CPU1

Is Yes Run Passed

Secure Flash secure flash
Boot? calculation

No

Is Yes No
Copy length
IPC RAM Copy
Is valid?
Boot?

No Yes

Run specified boot mode

Enable Watchdog Branch to Application

Figure 5-4. CPU2 Boot Flow

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5.5.3 Connectivity Manager (CM) Boot Flow

Upon reset, CM follows the boot flow shown in Figure 5-5. CM only boots once configured and released from
reset by CPU1. Refer to Section 5.7.2 for more details.
SCC Reset

POR CPU1 SYSRSn

VECTRESET
Reset

CM
CM NMI Watchdog Held in Reset
Reset (XRS)
Software Release Request
Application Releases from CPU1
CM from Reset
CM Software Reset
CM Boot Start
(SYSRESETREQ)

Disable Watchdog

Wait for CPU1 to set IPCFLG0

Read
CPU1TOCMIPCBOOTMODE
Register

Send IPC command No Is register

to CPU1 and wait. configured
(CPU1 must reset CM) correctly?

Yes

All other
resets
Reset Cause Flash Power Up

VECTRESET
All other
resets
Clear boot ROM Stack to zero Reset Cause

POR

RAM Initialization
Clear POR reset cause Enable NMI
(all CM RAMS)

CPU1 set IPCFLG0

Wait mode Wait in loop

Read boot mode
for IPC Flag

Other boot
Failed
mode Send IPC notification to CPU1

Is Yes Run Passed

Secure Flash secure flash
Boot? calculation

No

Is Yes No
Copy length
IPC RAM Copy
Is valid?
Boot?

No Yes

Run specified boot mode

Branch to Application

Figure 5-5. CM Boot Flow

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5.6 Device Reset and Exception Handling

5.6.1 Reset Causes and Handling
Table 5-15 explains the actions each boot ROM performs upon reset for a specific reset cause.
Table 5-15. Boot ROM Reset Causes and Actions
Reset Source CPU1 Boot ROM Action CPU2 Boot ROM Action CM Boot ROM Action
1. Configure Clock Divider
2. Flash Power Up 1. Flash Power Up 1. Flash Power Up
3. Device configuration and 2. RAM Initialization 2. RAM Initialization
Power on Reset (POR)
trimming
4. RAM Initialization 3. Continue default boot flow 3. Continue default boot flow
5. Continue default boot flow
External Reset (XRS) 1. Configure Clock Divider
For CPU1, XRS triggers include: 2. Flash Power Up 1. Flash Power Up 1. Flash Power Up
• Watchdog Reset
3. Device configuration and 2. Clear RAM for boot stack 2. Clear RAM for boot stack
• NMI Watchdog Reset trimming
• EtherCAT Reset
4. Clear RAM for boot stack 3. Continue default boot flow 3. Continue default boot flow
• SIMRESET XRS
5. Continue default boot flow
1. Read HWBIST return address 1. Read HWBIST return address
2. If set, branch to address 2. If set, branch to address Not Applicable
Hardware Built-In Self Test
(HWBIST) 3. If not set, continue boot 3. If not set, continue boot
following "Debugger Reset" boot following "Debugger Reset" boot
flow actions flow actions
Secure Copy Code (SCC) Reset 1. Clear RAM for boot stack 1. Clear RAM for boot stack 1. Flash Power Up
(CPU1, CPU2)
2. Continue default boot flow 2. Continue default boot flow 2. Clear RAM for boot stack
Watchdog Reset (CPU2)
NMI Watchdog Reset (CPU2) 3. Continue default boot flow
Execute Override Logic (EOL)
Reset (CM)
1. Clear RAM for boot stack
SIMRESET_CPU1 Not Applicable Not Applicable
2. Continue default boot flow
Debugger Reset (CPU1, CPU2) 1. Clear RAM for boot stack 1. Clear RAM for boot stack 1. Clear RAM for boot stack
VECTRESET (CM) 2. Continue default boot flow 2. Continue default boot flow 2. Continue default boot flow

5.6.2 Exceptions and Interrupts Handling

Table 5-16 explains the actions each boot ROM performs if any exceptions that can occur happen during boot.
The exception handling philosophy for CPU1, in most cases, is to log the error and continue booting to reach the
application. The exception handling philosophy for CPU2 and CM is to log the error, notify CPU1, and let CPU1
handle the action.
For any CPU2 NMI event sources, CPU2 NMI handler will clear the NMI flag to stop the NMI watchdog counter
and prevent CPU2 from resetting. The error pin will go low or high (depending on the polarity configuration on
the error pin and the reset type) temporarily before the NMI flag is cleared. Therefore, a shorter pulse width of
the error pin signal means CPU2 (or CM) is the source of the error. Following this, CPU2 sends an error IPC
message to CPU1 in order for CPU1 to handle the error and reset CPU2.
For any CM NMI event sources, the CM NMI handler will clear the NMI flag to stop the NMI watchdog counter
and prevent CM from resetting. The error pin will go low or high (depending on the polarity configuration on
the error pin and the reset type) temporarily before the NMI flag is cleared. Therefore, a shorter pulse width of
the error pin signal means CM (or CPU2) is the source of the error. Following this, the CM sends an error IPC
message to CPU1 in order for CPU1 to handle the error and reset CM.

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Table 5-16. Boot ROM Exceptions and Actions

Exception Event Source CPU1 Boot ROM Action CPU2 Boot ROM Action CM Boot ROM Action Event Logged
Single-bit error in Ignore and continue to boot No action No action No
FUSEERR
Multi-bit error in FUSEERR Reset the device No action No action No
Clock Fail Clear the NMI flag and Clear NMI flag, update boot Clear NMI flag, update boot Yes
continue to boot status to CPU1, send error status to CPU1, send error
IPC to CPU1, and wait in IPC to CPU1, and wait in
loop loop
RAM Uncorrectable Error Perform RAM initialization Clear NMI flag, update boot Clear NMI flag, update boot Yes(1)
ROM Parity Error and reset the device status to CPU1, send error status to CPU1, send error
IPC to CPU1, and wait in IPC to CPU1, and wait in
loop loop
Flash Uncorrectable Error Reset the device Clear NMI flag, update boot Clear NMI flag, update boot Yes
status to CPU1, send error status to CPU1, send error
IPC to CPU1, and wait in IPC to CPU1, and wait in
loop loop
HWBIST Error Clear the NMI flag and Clear NMI flag, update boot No action Yes
continue to boot status to CPU1, send error
IPC to CPU1, and wait in
loop
PIE Vector Mismatch(2) Fetch error handler Fetch error handler No action Yes
address, if address is address, if address is
configured, call handler, configured, call handler,
else reset the device else clear NMI flag, update
boot status to CPU1, send
error IPC to CPU1, and wait
in loop
Embedded Real-time Clear the NMI flag and Clear NMI flag, update boot No action Yes
Analysis and Diagnostic continue to boot status to CPU1, send error
(ERAD) NMI IPC to CPU1, and wait in
loop
MCAN Uncorrectable Error Clear the NMI flag and No action Clear NMI flag, update boot Yes
continue to boot status to CPU1, send error
IPC to CPU1, and wait in
loop
EtherCAT NMI Clear the NMI flag and No action Clear NMI flag, update boot Yes
continue to boot status to CPU1, send error
IPC to CPU1, and wait in
loop
ITRAP Exception Record memory address of Send IPC to CPU1 with No action Yes
where the illegal instruction memory address of the
was executed and let device illegal instruction and wait in
reset loop
Invalid IPCBOOTMODE No action Send IPC to CPU1 and wait Send IPC to CPU1 and wait Yes
Value upon Reset in loop in loop
Secure Flash Boot Failure Enable watchdog and let Send IPC to CPU1 and Send IPC to CPU1 and Yes
device reset return to wait boot mode return to wait boot mode
Hard Fault Exception No action No action Update boot status to Yes
CPU1, send error IPC to
CPU1, and wait in loop
Any Unsupported Interrupt Ignore and continue to boot Ignore and continue to boot Update boot status to Yes (CM Only)
CPU1, send error IPC to
CPU1 with the interrupt
exception number, and wait
in loop

(1) For CPU1, a RAM uncorrectable error or ROM parity error will clear the boot status information stored in RAM because a RAM
initialization is performed to attempt to correct the error. Since the boot status information is erased, this exception can be identified in
that a NMIWD reset occurred and all the RAMs are erased.
(2) A PIE vector mismatch in one core (such as CPU1 or CPU2) will trigger the PIE vector mismatch interrupt in other cores.

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5.7 Boot ROM Description

This section explains the details regarding the device boot ROMs.
5.7.1 CPU1 Boot ROM Configuration Registers
CPU1 boot ROM code involves several memory addresses and registers used during execution. There are two
sets of configurations; one for emulation and one for standalone boot flow. The emulation locations located in
RAM emulate the OTP configurations and can be written to as many times as needed. The user configurable
DCSM OTP locations used in the standalone boot flow program the device OTP and hence can only be written
once. For bit field configuration details for BOOTPIN-CONFIG and BOOTDEF, see Section 5.4.1 and Section
5.4.2.
Additionally, the CPU1 boot ROM supports boot configurations from DCSM zone 1 and zone 2 registers. Zone 2
configurations will supercede zone 1 configurations, so it is recommended to use zone 1 configurations and use
zone 2 as a secondary option.

Note
All boot configurations for CPU2 and CM are set through CPU1TOCPU2IPCBOOTMODE and
CPU1TOCMIPCBOOTMODE registers. See more details in Section 5.7.2.

Table 5-17. CPU1 Boot ROM Registers

Boot Flow Register Name Boot ROM Name Register Address User OTP Address
- EMUBOOTPINCONFIG 0x0000 0D00 -
Emulation - EMUBOOTDEF-LOW 0x0000 0D04 -
- EMUBOOTDEF-HIGH 0x0000 0D06 -
Z1-GPREG1 Z1-BOOTPINCONFIG 0x0005 F008 0x0007 8008

Standalone Z1-GPREG2 Z1-BOOT-GPREG2 0x0005 F00A 0x0007 800A

(Using Z1) Z1-GPREG3 Z1-BOOTDEF-LOW 0x0005 F00C 0x0007 800C
Z1-GPREG4 Z1-BOOTDEF-HIGH 0x0005 F00E 0x0007 800E
Z2-GPREG1 Z2-BOOTPINCONFIG 0x0005 F088 0x0007 8208

Standalone Z2-GPREG2 Z2-BOOT-GPREG2 0x0005 F08A 0x0007 820A

(Using Z2) Z2-GPREG3 Z2-BOOTDEF-LOW 0x0005 F08C 0x0007 820C
Z2-GPREG4 Z2-BOOTDEF-HIGH 0x0005 F08E 0x0007 820E

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5.7.1.1 GPREG2 Usage and MPOST Configuration

Table 5-18 explains how the bit field values from the user configurable DCSM OTP location, Z1-BOOT-GPREG2
or Z2-BOOT-GPREG2, are decoded by CPU1 boot ROM. For more information, see C2000™ Memory Power-
On Self-Test (M-POST) .
Table 5-18. CPU1 DCSM Z1/Z2 GPREG2 Bit Fields
Bit Name Description Boot ROM Action
Write 0x5A to these 8 bits to
indicate to the boot ROM code If set to 0x5A, boot ROM uses the values in this register. If set to any other
31:24 Key
that the bits in this register are value, boot ROM ignores values in this register.
valid
23:8 Reserved Reserved No Action
0x0 = MPOST is run with PLL enabled for high speed (110 MHz).
When configured to a valid
0xC = MPOST is run with PLL enabled for medium speed (80 MHz).
Run value, MPOST (Memory Power
7:4 0x3 = MPOST is run with PLL enabled for low speed (60 MHz).
MPOST(1) (2) on Self-Test) is run on all device
0x9 = MPOST is run using INTOSC2 with PLL disabled (10 MHz).
memories
Any other value = MPOST does not run.
3:0 Reserved Reserved No Action

(1) If MPOST is configured to run with PLL enabled and the PLL fails to lock, then the MPOST run is skipped. This does not apply if
MPOST is configured to use INTOSC2 with PLL disabled.
(2) Note that EtherCAT gets de-asserted and released from reset using the EtherCATs peripheral software reset register during MPOST.
The EtherCAT state is not restored back into the reset state.

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5.7.2 Booting CPU2 and CM

This section details the boot up flow for CPU2 and CM. This includes the process, how to configure
IPCBOOTMODE, and the error IPC commands that CPU2/CM report to CPU1.
5.7.2.1 Boot Up Procedure
The boot configurations for CPU2 and CM are set by the CPU1 application. The CPU1 application configures the
clocks for CPU2/CM, sets the boot mode and other parameters in the IPCBOOTMODE register, and releases
CPU2/CM from reset to boot.
CPU2 and CM have two states where CPU1 can configure their boot mode. The first state occurs before
CPU2/CM boot and when they are still in reset. The second state occurs after CPU2/CM have been released
from reset to wait boot mode where the cores wait for an IPC flag to be set by CPU1 to indicate that a boot mode
has been set in the IPCBOOTMODE register. The procedures that CPU1 must follow are detailed in Table 5-19
and Table 5-20.

Note
Regardless of reset source, CPU2 and CM each require their respective IPCFLG0 to be set by CPU1
on every reset in order to confirm the contents of IPCBOOTMODE are valid and continue their boot
process.

Table 5-19. CPU2 Boot Procedure

CPU2 State CPU1 Application Actions
1. Configures CPU2 clocks
2. Configures the CPU1TOCPU2IPCBOOTMODE register
Held in Reset (Refer to Section 5.7.2.2 for configuration details)
3. Sets CPU1TOCPU2IPCFLG0(1)
4. Releases CPU2 from being held in reset
1. Configures the CPU1TOCPU2IPCBOOTMODE register
In Wait Boot Mode waiting for the IPC Flag (Refer to Section 5.7.2.2 for configuration details)
2. Sets CPU1TOCPU2IPCFLG0(1)

(1) CPU2 will ACK and clear this IPC flag during boot up.

Table 5-20. CM Boot Procedure

CM State CPU1 Application Actions
1. Configures CM clocks
2. Configures the CPU1TOCMIPCBOOTMODE register
Held in Reset (Refer to Section 5.7.2.2 for configuration details)
3. Sets CPU1TOCMIPCFLG0(1)
4. Releases CM from being held in reset
1. Configures the CPU1TOCMIPCBOOTMODE register
In Wait Boot Mode waiting for IPC Flag (Refer to Section 5.7.2.2 for configuration details)
2. Sets CPU1TOCMIPCFLG0(1)

(1) CM will ACK and clear this IPC flag during boot up.

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5.7.2.2 IPCBOOTMODE Details

This section details the CPU1TOCPU2IPCBOOTMODE and CPU1TOCMIPCBOOTMODE register bit-field
configurations and requirements for booting CPU2/CM.

Note
If any of the bit-fields of CPU1TOCPU2IPCBOOTMODE or CPU1TOCMIPCBOOTMODE registers are
set with invalid values, an error IPC command is sent to CPU1. CPU2/CM then enter a wait loop
where CPU2/CM wait for CPU1 to re-configure the IPCBOOTMODE register correctly and issue a
reset to the respective core.

Table 5-21. CPU1TOCPU2IPCBOOTMODE Register Details

Bit Name Valid Values Description
Key must be set for this register to
31:24 Key 0x5A
be considered valid.
23:20 Reserved - Reserved
Sets the data length (in
words) for the "Copy from IPC
0x0 = 0 words (Boot mode not used) Message RAM and Boot to
0x1 = 100 words M1RAM" boot mode. This is
IPC Message RAM Copy 0x2 = 200 words the number words to be copied
19:16
Length ... from CPU1TOCPU2MSGRAM1 to
0x9 = 900 words CPU2 M1RAM.
0xA = 1000 words(1)
If not using this boot mode, set
value to 0x0.
0xA = 10 MHz(2)
0xB = 11 MHz Sets the clock frequency (in MHz)
15:8 CPU2 Device Frequency
... that CPU2 is configured at.
0xC8 = 200 MHz(2)
0x0 = None/Wait Boot
0x03 = Flash Boot Option 0 (Sector 0)
0x23 = Flash Boot Option 1 (Sector 4)
0x43 = Flash Boot Option 2 (Sector 8)
0x63 = Flash Boot Option 3 (Sector 13)
0x0A = Secure Flash Boot Option 0 (Sector 0)
7:0 CPU2 Boot Mode Sets the boot mode for CPU2
0x2A = Secure Flash Boot Option 1 (Sector 4)
0x4A = Secure Flash Boot Option 2 (Sector 8)
0x6A = Secure Flash Boot Option 3 (Sector 13)
0x0C = IPC Message RAM copy and boot to M1RAM
0x05 = Boot to M0RAM
0x0B = Boot to User OTP

(1) Values greater than 0xA are invalid.

(2) Values less than 0xA (10 MHz) or greater than 0xC8 (200 MHz) are invalid.

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Table 5-22. CPU1TOCMIPCBOOTMODE Register Details

Bit Name Valid Values Description
Key must be set for this register to
31:24 Key 0x5A
be considered valid.
23:20 Reserved - Reserved
Sets the data length (in words)
for the "Copy from IPC Message
0x0 = 0 words / 0 bytes (Boot mode not used) RAM and Boot to S0RAM"
0x1 = 100 words / 200 bytes boot mode. This is the number
IPC Message RAM Copy 0x2 = 200 words / 400 bytes words to be copied from
19:16
Length ... CPU1TOCMMSGRAM1 to CM
0x9 = 900 words / 1800 bytes S0RAM.
0xA = 1000 words / 2000 bytes(1)
If not using this boot mode, set
value to 0x0.
0xA = 10 MHz(2)
0xB = 11 MHz Sets the clock frequency (in MHz)
15:8 CM Device Frequency
... that CM is configured at.
0x7D = 125 MHz(2)
0x0 = None/Wait Boot
0x03 = Flash Boot Option 0 (Sector 0)
0x23 = Flash Boot Option 1 (Sector 4)
0x43 = Flash Boot Option 2 (Sector 8)
0x63 = Flash Boot Option 3 (Sector 13)
0x0A = Secure Flash Boot Option 0 (Sector 0)
7:0 CM Boot Mode Sets the boot mode for CM
0x2A = Secure Flash Boot Option 1 (Sector 4)
0x4A = Secure Flash Boot Option 2 (Sector 8)
0x6A = Secure Flash Boot Option 3 (Sector 13)
0x0C = IPC Message RAM copy and boot to S0RAM
0x05 = Boot to S0RAM
0x0B = Boot to User OTP

(1) Values greater than 0xA are invalid.

(2) Values less than 0xA (10 MHz) or greater than 0x7D (125 MHz) are invalid.

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5.7.2.3 Error IPC Command Table

This section details the IPC commands that CPU2 or CM can send to CPU1 to notify CPU1 regarding an error
that occurred.

Note
After CPU2 or CM sends the error IPC command to CPU1, CPU2/CM will set
CPU2TOCPU1IPCFLG0/CMTOCPU1IPCFLG0.

Table 5-23. CPU2 to CPU1 Error IPC Commands

Description IPCSENDCOM Value IPCSENDADDR Value
No Command 0x0000 0000 Not Used
IPCBOOTMODE Value(s)
0xFFFF FFFF Not Used
Incorrect
If RAM is accessible, the address for the source of the ITRAP will be
CPU2 in ITRAP 0xFFFF FFFE
provided
CPU2 got NMI 0xFFFF FFFA Not Used
CPU2 Secure Flash CMAC
0xFFFF FFF9 Not Used
Calculation Failed

Table 5-24. CM to CPU1 Error IPC Commands

Description IPCSENDCOM Value IPCSENDADDR Value
No Command 0x0000 0000 Not Used
IPCBOOTMODE Value(s)
0xFFFF FFFF Not Used
Incorrect
CM got Hard Fault Exception 0xFFFF FFFE Not Used
CM got Unsupported Interrupt 0xFFFF FFFB Active Exception Number
CM got NMI 0xFFFF FFFA Not Used
CM Secure Flash CMAC
0xFFFF FFF9 Not Used
Calculation Failed

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5.7.3 Entry Points

This section gives details about the entry point addresses for various boot modes. These entry points direct the
boot ROM what address to branch to at the end of booting as per the selected boot mode.
Table 5-25. Entry Point Addresses for CPU1
Entry Point Details Address
Flash / Secure Flash (Option 0) Flash Sector 0 0x0008 0000
Flash / Secure Flash (Option 1) Flash Sector 4 0x0008 8000
Flash / Secure Flash (Option 2) Flash Sector 8 0x000A 8000
Flash / Secure Flash (Option 3) Flash Sector 13 0x000B E000
RAM M0RAM 0x0000 0000

Table 5-26. Entry Point Addresses for CPU2

Entry Point Details Address
Flash / Secure Flash (Option 0) Flash Sector 0 0x0008 0000
Flash / Secure Flash (Option 1) Flash Sector 4 0x0008 8000
Flash / Secure Flash (Option 2) Flash Sector 8 0x000A 8000
Flash / Secure Flash (Option 3) Flash Sector 13 0x000B E000
RAM M0RAM 0x0000 0000
CPU1 IPC Message RAM Copy to CPU2 RAM M1RAM 0x0000 0400
User OTP CPU2 User OTP 0x0007 8000

Table 5-27. Entry Point Addresses for CM

Entry Point Details Address
Flash / Secure Flash (Option 0) Flash Sector 0 0x0020 0000
Flash / Secure Flash (Option 1) Flash Sector 4 0x0021 0000
Flash / Secure Flash (Option 2) Flash Sector 8 0x0025 0000
Flash / Secure Flash (Option 3) Flash Sector 13 0x0027 C000
RAM S0RAM 0x2000 0800
CPU1 IPC Message RAM Copy to CM RAM S0RAM 0x2000 0800
User OTP CM User OTP 0x003C 0000

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5.7.4 Wait Points

During boot ROM execution, there are situations where the CPU may enter a wait loop in the code. This state
can occur for a variety of reasons. Table 5-28, Table 5-29, and Table 5-30 detail the address ranges that the
CPU PC register for each core will fall between if boot has entered one of these instances.
Table 5-28. Wait Point Addresses for CPU1
Silicon Rev0 Address Range Silicon RevA Address Range Description
0x3FB100 – 0x3FB106 0x3FB112 – 0x3FB117 In Wait Boot Mode
0x3FBEE2 – 0x3FBF09 0x3FBEEB – 0x3FBF12 In SCI Boot waiting on autobaud lock
0x3FE839 – 0x3FE92D 0x3FE839 – 0x3FE92D In NMI Handler
0x3FE7F1 – 0x3FE823 0x3FE7F1 – 0x3FE823 In PIE Vector Mismatch Handler
0x3FE944 – 0x3FE970 0x3FE944 – 0x3FE970 In ITRAP ISR
0x3FB12A – 0x3FB12E 0x3FB13C – 0x3FB142 Failed secure Flash CMAC verification loop

Table 5-29. Wait Point Addresses for CPU2

Silicon Rev0,A Address Range Description
0x3FB41D – 0x3FB42B In Wait Boot Mode waiting for boot command
0x3FB459 – 0x3FB503 In NMI Handler
0x3FB504 – 0x3FB559 In ITRAP ISR
0x3FB173 – 0x3FB1B7 In loop due to invalid CPU1TOCPU2IPCBOOTMODE value(s) and/or CPU1TOCPU2IPCFLG0 is
not set

Table 5-30. Wait Point Addresses for CM

Silicon Rev0,A Address Range Description
0x180C – 0x1818 In Wait Boot Mode waiting for boot command
0x4018 – 0x41C2 In NMI Handler
0x41C4 – 0x41E8 In Hard Fault Handler
0x41EA – 0x421A In Default Interrupt Handler
0x1618 – 0x16C4 In loop due to invalid CPU1TOCMIPCBOOTMODE value(s) and/or CPU1TOCMIPCFLG0 is not set

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5.7.5 Memory Maps

This section details the ROM memory maps.
5.7.5.1 Boot ROM Memory Maps
Table 5-31. CPU1 Boot ROM Memory Map
Memory Origin Address Length (Words)
ROM Signature 0x003E 8000 0x0002
AES Tables 0x003E 8002 0x1400
IQmath Tables 0x003E 9402 0x166D
FPU32 Fast Tables 0x003F 6946 0x081A
FPU64 Fast Tables 0x003F 7160 0x0D30
FPU32 Twiddle Tables 0x003F 7E90 0x0DF8
FPU64 Twiddle Tables 0x003F 8DD0 0x1BF0
Boot 0x003F A9C0 0x3E00
Interrupt Handlers 0x003F E7C0 0x01B1
CPU Fast Data(1) 0x003F EA22 0x0100
Boot Checksum 0x003F FE40 0x0042
Full ROM Checksum 0x003F FEC0 0x0042
CRC Table 0x003F FF32 0x0008
Version 0x003F FF7A 0x0002
Vector Table 0x003F FFBE 0x0042

(1) Check the data manual to determine if these are available for your device part number. If not available, treat these sections as
reserved.

Table 5-32. CPU2 Boot ROM Memory Map

Memory Origin Address Length (Words)
ROM Signature 0x003E 8000 0x0002
AES Tables 0x003E 8002 0x1400
IQmath Tables 0x003E 9402 0x166D
FPU32 Fast Tables 0x003F 6946 0x081A
FPU64 Fast Tables 0x003F 7160 0x0D30
FPU32 Twiddle Tables 0x003F 7E90 0x0DF8
FPU64 Twiddle Tables 0x003F 8DD0 0x1BF0
Boot 0x003F A9C0 0x3E00
Interrupt Handlers 0x003F E7C0 0x0173
CPU Fast Data(1) 0x003F EA22 0x0100
Boot Checksum 0x003F FE40 0x0042
Full ROM Checksum 0x003F FEC0 0x0042
CRC Table 0x003F FF32 0x0008
Version 0x003F FF7A 0x0002
Vector Table 0x003F FFBE 0x0042

(1) Check the data manual to determine if these are available for your device part number. If not available, treat these sections as
reserved.

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Table 5-33. CM Boot ROM Memory Map

Memory Origin Address Length (Bytes)
Vector Table 0x0000 0000 0x0140
Version 0x0000 0140 0x0004
Boot Checksum 0x0000 0144 0x0084
Full ROM Checksum 0x0000 01C8 0x0084
Boot 0x0000 024C 0x3DCC
Interrupt Handlers 0x0000 4018 0x0204
CRC Table 0x0000 FBFC 0x0400
ROM Signature 0x0000 FFFC 0x0004

5.7.5.2 CLA Data ROM Memory Maps

Note
Load refers to the memory addresses where the C28x CPU can view the data. Run refers to the CLA
memory addresses that the CLA uses to access the data.

Table 5-34. CPU1 CLA Data ROM Memory Map

Memory Origin Address Length (Words)
FFT Tables (Load) 0x0100 1070 0x0800
Data (Load) 0x0100 1870 0x078A
Version (Load) 0x0100 1FFA 0x0006
FFT Tables (Run) 0x0000 F070 0x0800
Data (Run) 0x0000 F870 0x078A
Version (Run) 0x0000 FFFA 0x0006

Table 5-35. CPU2 CLA Data ROM Memory Map

Memory Origin Address Length (Words)
FFT Tables (Load) 0x0100 1070 0x0800
Data (Load) 0x0100 1870 0x078A
Version (Load) 0x0100 1FFA 0x0006
FFT Tables (Run) 0x0000 F070 0x0800
Data (Run) 0x0000 F870 0x078A
Version (Run) 0x0000 FFFA 0x0006

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5.7.5.3 Reserved RAM Memory Maps

This section details memory usage in RAM that is reserved for boot ROM to use. These memory sections must
be reserved in the user application.
Table 5-36. CPU1 Reserved RAM Memory Map
Memory Description Origin Address End Address Length (Words)
Boot Status, Boot Mode,
RAM 0x0000 0002 0x0000 01B0 0x01AF
MPOST Status, Boot Stack

Table 5-37. CPU2 Reserved RAM Memory Map

Memory Description Origin Address End Address Length (Words)
Boot Status, Boot Mode, Boot
RAM 0x0000 0002 0x0000 01A8 0x01A7
Stack

Table 5-38. CM Reserved RAM Memory Map

Memory Description Origin Address End Address Length (Bytes)
Boot Status, Boot Mode, Boot
RAM 0x2000 0000 0x2000 07FF 0x0800
Stack

5.7.6 ROM Tables

Table 5-39 details the boot ROM and CLA ROM symbol libraries that can be integrated into an application to use
the available ROM functions and tables.
Table 5-39. ROM Symbol Tables
ROM Symbols Library Name Location
ROM Bootloaders and Functions F2838xCPU1_BootROM_Symbols
F2838xCPU1_BootROM_Symbols
FPU32 and FPU64 Tables
F2838xCPU2_BootROM_Symbols
F2838xCPU1_BootROM_Symbols
AES Tables
F2838xCPU2_BootROM_Symbols
F2838xCPU1_CLADATAROM_Symbols Under /libraries/boot_rom in C2000Ware
CLA Data ROM
F2838xCPU2_CLADATAROM_Symbols
F2838xCPU1_IQMathROM_Symbols
IQmath
F2838xCPU2_IQMathROM_Symbols
F2838xCPU1_SecureZoneCode_Symbols
Secure Zone Functions F2838xCPU2_SecureZoneCode_Symbols
F2838xCM_SecureZoneCode_Symbols

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5.7.7 Boot Modes and Loaders

The available boot modes and bootloaders supported on this device are detailed in this section.
5.7.7.1 Boot Modes
Table 5-40 details the available boot modes that do not involve a peripheral boot loader.
Table 5-40. Boot Mode Availability
Boot Mode CPU Support
Wait Boot CPU1, CPU2, CM
Flash Boot CPU1, CPU2, CM
Secure Flash Boot CPU1, CPU2, CM
RAM Boot CPU1, CPU2, CM
User OTP Boot CPU2, CM
IPC Message Copy to RAM Boot CPU2, CM

5.7.7.1.1 Wait Boot

The wait boot mode puts the CPU in a loop and does not branch to the user application code. The device can
either enter wait boot mode through configuration or because an error occurred during boot up. TI recommends
using wait boot when using a debugger to avoid any JTAG complications. CPU2 and CM can exit wait boot
mode and run a different boot mode when CPU1 sets the respective CPU IPCFLG0. More information regarding
this can found at Section 5.7.2.
Table 5-41. Reasons for Entering Wait Boot
CPU Actions Resulting in Wait Boot
• Wait boot is selected by user configuration
CPU1 • Decoded boot mode is unrecognized/invalid when a debugger is connected to the device
• The emulation BOOTPIN_CONFIG key is not set to 0xA5 or 0x5A

• Wait boot is selected by user configuration

• Decoded boot mode is unrecognized/invalid when a debugger is connected to the device
CPU2 • Secure Flash boot CMAC calculation returns failure
• IPC Message copy to RAM length specified is invalid (out of range) when trying to use this boot mode

• Wait boot is selected by user configuration

• Decoded boot mode is unrecognized/invalid when a debugger is connected to the device
CM • Secure Flash boot CMAC calculation returns failure
• IPC Message copy to RAM length specified is invalid (out of range) when trying to use this boot mode

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5.7.7.1.2 Flash Boot

Flash boot mode branches to the configured memory address in Flash. Refer to Section 5.7.3 for all the
available Flash address options.
For CPU1, on an unprogrammed device, Flash boot can be switched to USB boot. See more details in Section
5.3.
5.7.7.1.3 Secure Flash Boot
Secure Flash boot mode is similar to Flash boot mode in that the boot flow branches to the configured
memory address in Flash except only after the Flash memory contents have been authenticated. The Flash
authentication uses a Cipher-based Message Authentication Protocol (CMAC) to authenticate 16-KB of Flash
starting from the configured Flash entry point address. The CMAC calculation requires a user-defined 128-bit
key programmed in the CPU1 User OTP Zone 1 Header OTP CMACKEY bit field. Additionally, the user must
calculate the golden CMAC tag based on the 16-KB Flash memory range and store it along with the user code
at a hardcoded address in Flash. During secure Flash boot, the calculated CMAC tag is compared to the user
golden CMAC tag in Flash to determine the pass/fail status of the CMAC authentication. When authentication
passes, boot flow continues and branches to Flash to begin executing the application. When authentication fails,
the boot flow actions performed vary by core. Refer to Table 5-43 for details on failure actions for each core.
For the available secure Flash boot entry address options, refer to Section 5.7.3.
For generating the secure Flash golden CMAC tag for CPU1 or CPU2, refer to the section “Using Secure Flash
Boot on TMS320F2838x Devices” in the TMS320C28x Assembly Language Tools User’s Guide for instructions.
For generating the secure Flash golden CMAC tag for CM, refer to the ARM Assembly Language Tools
v19.6.0.STS, within section “Using Secure Flash Boot on TMS320F2838x Devices” for instructions.

Note
• User must make sure that the Flash sector that encompasses the configured Flash entry point and
the first 16KB of Flash is assigned to Zone 1 for any cores setup to use secure Flash boot.
• Recommended to use device JTAGLOCK when using secure Flash boot.
• If only using secure Flash boot for CPU2/CM, then the CPU1 application must first dummy load
the Z1 OTP CMACKEY before releasing CPU2/CM from reset. When dummy loading, CPU1
application must first disable Flash data caching, then perform the dummy load, and then the
application can re-enable Flash data caching.

Table 5-42. Secure Flash Tag and Key Details

Name Address Details
Located in Flash, offset from the entry point address, by 2 words
(CPU1/CPU2) or 4 bytes (CM).
When CMAC calculations are performed, the golden tag location
in memory is considered all 0xFs. Refer to Example 5-1 for an
example regarding linker configuration on CPU1.
Lower memory contains the tag's MSW and higher memory
CMAC Golden
CPU1/CPU2: Flash Entry Point Address + 0x2 contains the LSW
Tag
CM: Flash Entry Point Address + 0x4
(128-bit)
Example (on CPU1):
Tag = 0x00112233 44556677 8899AABB CCDDEEFF
Address 0x0 = 0x00112233
Address 0x2 = 0x44556677
Address 0x4 = 0x8899AABB
Address 0x6 = 0xCCDDEEFF

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Table 5-42. Secure Flash Tag and Key Details (continued)

Name Address Details
Located in CPU1 Zone 1 User Header OTP
(CMACKEY0, CMACKEY1, CMACKEY2, CMACKEY3)
CMACKEY0 contains the key's MSW and CMACKEY3 contains
the LSW
CMAC 128-Bit
0x0007 8018 Example:
Key Key = 0x00112233 44556677 8899AABB CCDDEEFF
CMACKEY0 = 0x00112233
CMACKEY1 = 0x44556677
CMACKEY2 = 0x8899AABB
CMACKEY3 = 0xCCDDEEFF

Table 5-43. Secure Flash Authentication Failure Actions

CPU Action on Failed Authentication
CPU1 Reset the device (If using debugger, device halts)
CPU2 Send IPC message to CPU1, update CPU2 boot status to indicate failure, and return to wait boot
CM Send IPC message to CPU1, update CM boot status to indicate failure, and return to wait boot

Table 5-44. Secure Flash on all CPUs Recommended Flow

Step Action
1 Secure Flash boot CPU1
2 CPU1 application configures CPU2 and CM to boot using Secure Flash Boot and releases CPU2/CM from reset
3 CPU2 and CM perform secure Flash boot
4 CPU2 and CM applications signal to CPU1 using IPC that booting is complete
For CPU1/CPU2/CM, any Flash beyond the first 16KB from the entry point that is planned for use must be
5 authenticated by the user using a different CMAC golden tag embedded at an address somewhere within the already
authenticated 16KB of Flash

Example 5-1. Secure Flash CPU1 Linker File Example

MEMORY
{
/* Code Start branch to _c_int00 */
BEGIN : origin = 0x80000, length = 0x0002
/* User calculated golden CMAC tag for Flash Sector 0 */
GOLDEN_CMAC_TAG : origin = 0x80002, length = 0x0008
/* Flash Sector 0 containing application code */
FLASH_SECTOR_0 : origin = 0x8000A, length = 0x1FF6
.
.
.
}

5.7.7.1.4 RAM Boot

RAM boot mode branches to the configured memory address in RAM. Refer to Section 5.7.3 for all the available
RAM address options.

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5.7.7.1.5 User OTP Boot

User OTP boot mode branches to the configured memory address in User OTP. Refer to Section 5.7.3 for all the
available user OTP address options.
5.7.7.1.6 IPC Message Copy to RAM Boot
IPC message copy to RAM involves copying application code from CPU1 IPC message RAM 1 to CPU2/CM
destination RAM for execution. The maximum copy length size is 1000 words (2000 bytes) and the minimum is
100 words (200 bytes). Refer to Table 5-45 for details regarding configuration and execution flow of this boot
mode.
Table 5-45. IPC Message Copy Steps
Step Action
1 CPU1 application links CPU2/CM code to copy in either CPU1TOCPU2MSGRAM1 or CPU1TOCMMSGRAM1.
CPU1 application configures CPU2/CM IPCBOOTMODE with the copy length and IPC message copy as the boot
2
mode. See Section 5.7.2.2 for more IPCBOOTMODE details.
Once CPU2/CM is released from reset to boot, CPU2/CM begins copying from CPU1TOCPU2MSGRAM1/
3
CPU1TOCMMSGRAM1 to their destination RAM. Refer to Table 5-46 for destination RAM details.
Once the copying is complete, CPU2/CM boot branches to the entry address of the destination RAM and begins
4
executing the application.

Table 5-46. IPC Message Copy Destination Address

Destination Address Range(1)
CPU RAM
(For maximum copy length of 1000 words)
CPU2 M1RAM 0x0000 0400 to 0x0000 07E6
CM S0RAM 0x2000 0800 to 0x2000 0FCC

(1) This memory must be allocated and reserved in the CPU2/CM application linker command file when using this boot mode.

5.7.7.2 Bootloaders
This section details the available boot modes that use a peripheral boot loader. For more specific details on the
supported data stream structure used by the following bootloaders, refer to Section 5.8.1.

Note
These are only available on CPU1.

5.7.7.2.1 SCI Boot Mode

The SCI boot mode asynchronously transfers code from SCI-A to internal memory. This boot mode only
supports an incoming 8-bit data stream and follows the data flow as outlined in Example 5-2.

SCIRXDA
Control Host
Subsystem (Data and program
boot ROM SCITXDA source)

Figure 5-6. Overview of SCI Bootloader Operation

The device communicates with the external host by communication through the SCI-A peripheral. The autobaud
feature of the SCI port is used to lock baud rates with the host. For this reason the SCI loader is very flexible and
you can use a number of different baud rates to communicate with the device.
After each data transfer, the bootloader echoes back the 8-bit character received to the host. This allows the
host to check that each character was received by the bootloader.

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At higher baud rates, the slew rate of the incoming data bits can be affected by transceiver and connector
performance. While normal serial communications can work well, this slew rate can limit reliable auto-baud
detection at higher baud rates (typically beyond 100 kbaud) and cause the auto-baud lock feature to fail. To
avoid this, the following is recommended:
1. Achieve a baud-lock between the host and SCI bootloader using a lower baud rate.
2. Load the incoming application or custom loader at this lower baud rate.
3. The host can then handshake with the loaded application to set the SCI baud rate register to the desired
high baud rate.

SCI_Boot

Enable the SCI-A clock Echo autobaud character

set the LSPCLK to /4

Enable the SCIA TX and RX pin Read KeyValue

functionality and pullups on
TX and RX

Valid No
Setup SCI-A for KeyValue Jump to Flash
1 stop, 8-bit character, (0x08AA)
no parity, use internal ?
SC clock, no loopback,
disable Rx/Tx interrupts
Yes

Read and discard 8

Disable SCI FIFOs reserved words

Prime SCI-A baud register Read EntryPoint address

Enable autobaud detection Read data in the standard

boot stream format

No Autobaud
lock
?

Return
Yes EntryPoint

Figure 5-7. Overview of SCI Boot Function

5.7.7.2.2 SPI Boot Mode

The SPI loader expects an SPI-compatible 16-bit or 24-bit addressable serial EEPROM or serial Flash device to
be present on the SPI-A pins as indicated in Figure 5-8. The SPI bootloader supports an 8-bit data stream and
does not support a 16-bit data stream.

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Serial SPI
EEPROM
SPIA_SIMO
DIN
Control SPIA_SOMI
DOUT
subsystem SPIA_CLK CLK
SPIA_STE CS

Figure 5-8. SPI Loader

The SPI boot ROM loader initializes the SPI module to interface to a serial SPI EEPROM or Flash. Devices
of this type include, but are not limited to, the Xicor X25320 (4Kx8) and Xicor X25256 (32Kx8) SPI serial SPI
EEPROMs and the Atmel AT25F1024A serial Flash.
The SPI boot ROM loader initializes the SPI with the following settings: FIFO enabled, 8-bit character, internal
SPICLK master mode and talk mode, clock phase = 1, polarity = 0, using the slowest baud rate.
If the download is to be performed from an SPI port on another device, then that device must be set up to
operate in the slave mode and mimic a serial SPI EEPROM. Immediately after entering the SPI_Boot function,
the pin functions for the SPI pins are set to primary and the SPI is initialized. The initialization is done at the
slowest speed possible. Once the SPI is initialized and the key value read, specify a change in baud rate or
low-speed peripheral clock.
Table 5-47. SPI 8-Bit Data Stream
Byte Contents
1 LSB: AA (KeyValue for memory width = 8-bits)
2 MSB: 08h (KeyValue for memory width = 8-bits)
3 LSB: LOSPCP
4 MSB: SPIBRR
5 LSB: reserved for future use
6 MSB: reserved for future use
... ...
... Reserved
...
17 LSB: reserved for future use
18 MSB: reserved for future use
19 LSB: Upper half (MSW) of Entry point PC[23:16]
20 MSB: Upper half (MSW) of Entry point PC[31:24] (Note: Always 0x00)
21 LSB: Lower half (LSW) of Entry point PC[7:0]
22 MSB: Lower half (LSW) of Entry point PC[15:8]
... ....
... Data for this section.
...
... Blocks of data in the format size/destination address/data as shown in the generic
data stream description
... ...
... Data for this section.
...
n LSB: 00h
n+1 MSB: 00h - indicates the end of the source

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The data transfer is done in "burst" mode from the serial SPI EEPROM. The transfer is carried out entirely in
byte mode (SPI at 8 bits/character). A step-by-step description of the sequence follows:
1. The SPI-A port is initialized.
2. The GPIO pin, as defined by SPI option configured from Table 5-61, is used as a chip-select for the serial
SPI EEPROM or Flash.
3. The SPI-A outputs a read command for the serial SPI EEPROM or Flash.
4. The SPI-A sends the serial SPI EEPROM an address 0x0000; that is, the host requires that the EEPROM or
Flash must have the downloadable packet starting at address 0x0000 in the EEPROM or Flash. The loader
is compatible with both 16-bit addresses and 24-bit addresses.
5. The next word fetched must match the key value for an 8-bit data stream (0x08AA). The least significant
byte of this word is the byte read first and the most significant byte is the next byte fetched. This is true of
all word transfers on the SPI. If the key value does not match, then the load is aborted and the bootloader
jumps to Flash.
6. The next two bytes fetched can be used to change the value of the low speed peripheral clock register
(LOSPCP) and the SPI baud rate register (SPIBRR). The first byte read is the LOSPCP value and the
second byte read is the SPIBRR value. The next seven words are reserved for future enhancements. The
SPI bootloader reads these seven words and discards them.
7. The next two words makeup the 32-bit entry point address where execution continues after the boot load
process is complete. This is typically the entry point for the program being downloaded through the SPI port.
8. Multiple blocks of code and data are then copied into memory from the external serial SPI EEPROM through
the SPI port. The blocks of code are organized in the standard data stream structure presented earlier. This
is done until a block size of 0x0000 is encountered. At that point in time the entry point address is returned to
the calling routine that then exits the bootloader and resumes execution at the address specified.

SPI_Boot

Enable the SPI-A clock

Set the LSPCLK to 4 Valid No
KeyValue Jump to Flash
(0x08AA)
?
Enable SPISIMOA,
SPISOMI and SPICLKA
pin functionality and enable Yes
pullups on those pins
Read LOSPCP value Change LOSPCP

Set up SPI-A for

8-bit character,
Use internal SPI clock,
master mode
Use slowest baud rate (0x7F)
Relinquish SPI-A from reset

Read SPIBRR value Change SPIBRR

Set chip enable high

Enable EEPROM
Send read command and Read and discard 7
start at EEPROM address reserved words
0x0000

Read EntryPoint Return

Read KeyValue address Call CopyData EntryPoint

Figure 5-9. Data Transfer From EEPROM Flow

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5.7.7.2.3 I2C Boot Mode

The I2C bootloader expects an 8-bit wide I2C-compatible EEPROM device to be present at address 0x50 on the
I2C-A bus as indicated in Figure 5-10. The EEPROM must adhere to conventional I2C EEPROM protocol, as
described in this section, with a 16-bit base address architecture.
SDA SCL

I2CA_SDA
Control
subsystem
I2CA_SCL
I2C
SDA EEPROM

SCL Slave Address

0x50

Figure 5-10. EEPROM Device at Address 0x50

If the download is to be performed from a device other than an EEPROM, then that device must be set up to
operate in the slave mode and mimic the I2C EEPROM. Immediately after entering the I2C boot function, the
GPIO pins are configured for I2C-A operation and the I2C is initialized. The following requirements must be met
when booting from the I2C module:
• The input frequency to the device must be in the appropriate range.
• The EEPROM must be at slave address 0x50.
The bit-period prescalers (I2CCLKH and I2CCLKL) are configured by the bootloader to run the I2C at a 50
percent duty cycle at 100-kHz bit rate (standard I2C mode) when the system clock is 10 MHz. These registers
can be modified after receiving the first few bytes from the EEPROM. This allows the communication to be
increased up to a 400-kHz bit rate (fast I2C mode) during the remaining data reads.
Arbitration, bus busy, and slave signals are not checked. Therefore, no other master is allowed to control the bus
during this initialization phase. If the application requires another master during I2C boot mode, that master must
be configured to hold off sending any I2C messages until the application software signals that the application is
past the bootloader portion of initialization.
The non-acknowledgment bit is checked only during the first message sent to initialize the EEPROM base
address. This is to make sure that an EEPROM is present at address 0x50 before continuing. If an EEPROM is
not present, the non-acknowledgment bit is not checked during the address phase of the data read messages
(I2C_Get Word). If a non-acknowledgment is received during the data read messages, the I2C bus hangs. Table
5-48 shows the 8-bit data stream used by the I2C.

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NACK Yes
I2C_Boot
received Jump to Flash
?
Enable I2CA_SDA and
I2CA_SCL pins No
Enable pullups on
I2CA_SDA and I2CA_SCL Read KeyValue

Enable I2C-A clock

Valid No
KeyValue Jump to Flash
(0x08AA)
Set slave address 0x50
?
I2C prescaler I2CPSC = or 0
Yes
100-kHz bit rate Put 12c-A in Reset
Read I2CPSC value Set I2CPSC value
Enable TX/RX FIFOs to Read I2CCLKH value Set I2CCLKH value
receive 2 bytes. Read 12CCLKL value Set I2CCLKL value
Bring I2C-A out of Reset

Place I2C in master

transmitter mode
Set EEPROM address
pointer to 0x0000 Read and discard 5
reserved words

Read EntryPoint
address

Read data in standard

boot stream format

Return
EntryPoint

Figure 5-11. Overview of I2C Boot Function

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Table 5-48. I2C 8-Bit Data Stream

Byte Contents
1 LSB: AA (KeyValue for memory width = 8 bits)
2 MSB: 08h (KeyValue for memory width = 8 bits)
3 LSB: I2CPSC[7:0]
4 reserved
5 LSB: I2CCLKH[7:0]
6 MSB: I2CCLKH[15:8]
7 LSB: I2CCLKL[7:0]
8 MSB: I2CCLKL[15:8]
... ...
... Data for this section.
...
17 LSB: Reserved for future use
18 MSB: Reserved for future use
19 LSB: Upper half of entry point PC
20 MSB: Upper half of entry point PC[22:16] (Note: Always 0x00)
21 LSB: Lower half of entry point PC[15:8]
22 MSB: Lower half of entry point PC[7:0]
... ...
... Data for this section.
...
Blocks of data in the format size/destination address/data as shown in the generic data stream description.
... ...
... Data for this section.
...
n LSB: 00h
n+1 MSB: 00h - indicates the end of the source

The I2C EEPROM protocol required by the I2C bootloader is shown in Figure 5-12 and Figure 5-13. The first
communication, which sets the EEPROM address pointer to 0x0000 and reads the KeyValue (0x08AA), is shown
in Figure 5-12. All subsequent reads are shown in Figure 5-13 and are read two bytes at a time.
RESTART

NO ACK
START

WRITE

READ

STOP
MSB

MSB

ACK
ACK

ACK

ACK
ACK
LSB

LSB

SDA LINE
1 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 00 1 01 0 0 0 0 1 0

Device Address Address Device DATA BYTE 1 DATA BYTE 2

Address Pointer, MSB Pointer, LSB Address

Figure 5-12. Random Read

NO ACK
START

READ

STOP
ACK

ACK

SDA LINE
1 01 0 0 0 0 1 0

Device DATA BYTE n DATA BYTE n+1

Address

Figure 5-13. Sequential Read

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5.7.7.2.4 Parallel Boot Mode

The parallel general purpose I/O (GPIO) boot mode asynchronously transfers code from GPIO88,
GPIO62:GPIO58, GPIO90:GPIO89 to internal memory. Each value is eight bits long and follows the same data
flow as outlined in Figure 5-14.
28x control − GPIO91
Host control − GPIO92 Host
boot ROM (data and program
8 source)

Data GP I/O port GPIO[88, 62:58, 90:89]

Figure 5-14. Overview of Parallel GPIO Bootloader Operation

The control subsystem communicates with the external host device by polling/driving the GPIO92 and GPIO91
lines. The handshake protocol shown in Figure 5-15 must be used to successfully transfer each word using
GPIO[88, 62:58, 90:89]. This protocol is very robust and allows for a slower or faster host to communicate with
the master subsystem.
Two consecutive 8-bit words are read to form a single 16-bit word. The least significant byte (LSB) is read first
followed by the most significant byte (MSB). In this case, data is read from GPIO[88, 62:58, 90:89].
The 8-bit data stream is shown in Table 5-49.
Table 5-49. Parallel GPIO Boot 8-Bit Data Stream
Bytes GPIO[88,62:58,90:89] GPIO[88,62:58,90:89] Description
(Byte 1 of 2) (Byte 2 of 2)
1 2 AA 08 0x08AA (KeyValue for memory width = 16 bits)
3 4 00 00 8 reserved words (words 2 - 9)
... ... ... ... ...
17 18 00 00 Last reserved word
19 20 BB 00 Entry point PC[22:16]
21 22 DD CC Entry point PC[15:0] (PC = 0x00BBCCDD)
23 24 NN MM Block size of the first block of data to load = 0xMMNN words
25 26 BB AA Destination address of first block Addr[31:16]
27 28 DD CC Destination address of first block Addr[15:0] (Addr = 0xAABBCCDD)
29 30 BB AA First word of the first block in the source being loaded = 0xAABB
... ...
... Data for this section.
...
. BB AA Last word of the first block of the source being loaded = 0xAABB
. NN MM Block size of the 2nd block to load = 0xMMNN words
. BB AA Destination address of second block Addr[31:16]
. DD CC Destination address of second block Addr[15:0]
. BB AA First word of the second block in the source being loaded
. …
n n+1 BB AA Last word of the last block of the source being loaded
(More sections if required)
n+2 n+3 00 00 Block size of 0000h - indicates end of the source program

The device first signals the host that the device is ready to begin data transfer by pulling the GPIO91 pin low.
The host load then initiates the data transfer by pulling the GPIO92 pin low. The complete protocol is shown in
Figure 5-15.

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1 2 3 4 5 6

Host control
GPIO92

Device control
GPIO91

Figure 5-15. Parallel GPIO Bootloader Handshake Protocol

1. The device indicates the device is ready to start receiving data by pulling the GPIO91 pin low.
2. The bootloader waits until the host puts data on GPIO [88,62:58,90:89]. The host signals to the device that
data is ready by pulling the GPIO92 pin low.
3. The device reads the data and signals the host that the read is complete by pulling GPIO91 high.
4. The bootloader waits until the host acknowledges the device by pulling GPIO92 high.
5. The device again indicates the device is ready for more data by pulling the GPIO91 pin low.
This process is repeated for each data value to be sent.
Figure 5-16 shows an overview of the Parallel GPIO bootloader flow.
Figure 5-17 shows the transfer flow from the host side. The operating speed of the CPU and host are not critical
in this mode, as the host waits for the device and the device waits for the host. In this manner, the protocol works
with both a host running faster and a host running slower than the device.

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Parallel_Boot

Initialize GP I/O MUX Read and discard 8

and Dir registers reserved words
GPIO[88,62:58,90:89] = input
GPIO92 = input
GPIO91 = output
Enable pullups on Read EntryPoint
address
GPIO[88,62:58,90:89]

Call
CopyData

Valid
No KeyValue
Return Flash EntryPoint (0x08AA)
?
Return
Yes EntryPoint

Figure 5-16. Parallel GPIO Mode Overview

Start transfer

No Device ready
(GPIO91=0)
?

Yes No Device ack

(GPIO91=1)
Load GPIO[88,62:58,90:89] with data ?

Yes
Signal that data
is ready Acknowledge device
(GPIO92=0) (GPIO92=1)

More Yes
data
?

No

End transfer

Figure 5-17. Parallel GPIO Mode - Host Transfer Flow

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Figure 5-18 shows the flow used to read a single word of data from the parallel port.
• 8-bit data stream
The 8-bit routine, shown in Figure 5-18, discards the upper eight bits of the first read from the port and treats
the lower eight bits masked with GPIO89 in bit position 7 and GPIO90 in bit position 6 as the least-significant
byte (LSB) of the word to be fetched. The routine then performs a second read to fetch the most-significant
byte (MSB). The routine then combines the MSB and LSB into a single 16-bit value to be passed back to the
calling routine.

Parallel_GetWordData A
8 bit

Signal host that device is ready Signal host that device

is ready to read MSB
(GPIO91 = 0) (GPIO91 = 0)

Data Data
ready No ready No
(GPIO92 = 0) (GPIO92 = 0)
? ?

Yes Yes

Read word of data

from GPIO[88,62:58,90:89] Read GPIO for LSB and
MSB of 16-bit data

Device ack read complete

(GPIO91 = 1)

Device ack read complete

(GPIO91 = 1)

Host
ack No
(GPIO92 = 1)
? Host
ack No
Yes (GPIO92 = 1)
?

Yes

WordData = MSB:LSB

A
Return WordData

Figure 5-18. 8-Bit Parallel GetWord Function

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5.7.7.2.5 CAN Boot Mode

The CAN bootloader asynchronously transfers code from CAN-A to internal memory. The host can be any CAN
node. The communication is first done with 11-bit standard identifiers (with a MSGID of 0x1) using two bytes per
data frame. The host can download a kernel to reconfigure the CAN if higher data throughput is desired.

28x

CAN bus
CAN
host

28x

Figure 5-19. Overview of CAN-A Bootloader Operation

The bit timing registers are programmed in such a way that a 100-kbps bit rate is achieved with a 20-MHz
external oscillator, a shown in Table 5-50.
Table 5-50. Bit-Rate Value for Internal Oscillators
OSCCLK SYSCLK Bit Rate
20 MHz 10 MHz 100 kbps

The SYSCLKOUT values shown are the reset values with the default PLL setting. The BRP and bit-time values
are hard-coded to 10 and 20, respectively.

Note
The CPU1 CAN boot loader uses XTAL as the bit clock source and INTOSC2 as the system clock
source.

Mailbox 1 is programmed with a standard MSGID of 0x1 for boot-loader communication. The CAN host must
transmit only two bytes at a time, LSB first and MSB next. For example, to transmit the word 0x08AA to
the device, transmit AA first, followed by 08. The program flow of the CAN bootloader is identical to the SCI
bootloader. The data sequence for the CAN bootloader is shown in Table 5-51.

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Table 5-51. CAN 8-Bit Data Stream

Bytes Byte 1 of 2 Byte 2 of 2 Description
1 2 AA 08 0x08AA (KeyValue for memory width = 16 bits)
3 4 00 00 reserved
5 6 00 00 reserved
7 8 00 00 reserved
9 10 00 00 reserved
11 12 00 00 reserved
13 14 00 00 reserved
15 16 00 00 reserved
17 18 00 00 reserved
19 20 BB AA Entry point PC[22:16]
21 22 DD CC Entry point PC[15:0] (PC = 0xAABBCCDD)
23 24 NN MM Block size of the first block of data to load = 0xMMNN words
25 26 BB AA Destination address of first block Addr[31:16]
27 28 DD CC Destination address of the first block Addr[15:0] (Addr = 0xAABBCCDD)
29 30 BB AA First word of the first block in the source being loaded = 0xAABB
... ....
... Data for this section.
...
. BB AA Last word of the first block of the source being loaded = 0xAABB
. NN MM Block size of the second block to load = 0xMMNN words
. BB AA Destination address of the second block Addr[31:16]
. DD CC Destination address of the second block Addr[15:0]
. BB AA First word of the second block in the source being loaded
. …
n n+1 BB AA Last word of the last block of the source being loaded
(More sections if required)
n+2 n+3 00 00 Block size of 0000h - indicates end of the source program

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5.7.7.2.6 USB Boot Mode

In USB boot mode, the device enumerates with vendor ID 0x1CBE and product ID 0x00FF. The device
descriptor and interface descriptor both show the class as 0xFF (vendor-specific), the subclass as 0x00, and
the protocol as 0x00. After enumeration, the device waits for data. Data must be sent using bulk OUT transfers
to endpoint 1. The data is interpreted as a series of 8-bit bytes in the standard data stream format described
in Section 5.8.1, shown here in Table 5-52. No reserved bytes are used. Once the data transfer is complete
(block size of 0x0000 sent), the device disconnects from the USB bus, allowing other software to make use of
the module if desired. Figure 5-20 illustrates the flow for USB boot mode.
USB_Boot

Host sends boot

loader data in the
Wait for standard stream
connection format via bulk OUT
transfers to
endpoint 1

Enumerate to host
PC with ID 1cbe:00ff Valid key
Jump to flash
(0x08AA)?

Host PC installs
drivers
MCU loads data into
RAM

MCU waits
for data MCU disconnects
from the USB bus

Return EntryPoint

Figure 5-20. USB Boot Flow

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Table 5-52. USB 8-Bit Data Stream

Bytes First Byte Second Byte Description
(LSB) (MSB)
1 2 AA 08 0x08AA (KeyValue for memory width = 16bits)
3 4 00 00 reserved
5 6 00 00 reserved
7 8 00 00 reserved
9 10 00 00 reserved
11 12 00 00 reserved
13 14 00 00 reserved
15 16 00 00 reserved
17 18 00 00 reserved
19 20 BB AA Entry point PC[22:16]
21 22 DD CC Entry point PC[15:0] (PC = 0xAABBCCDD)
23 24 NN MM Block size of the first block of data to load = 0xMMNN words
25 26 BB AA Destination address of the first block Addr[31:16]
27 28 DD CC Destination address of the first block Addr[15:0] (Addr = 0xAABBCCDD)
29 30 BB AA First word of the first block in the source being loaded = 0xAABB
... ....
... Data for this section.
...
. BB AA Last word of the first block of the source being loaded = 0xAABB
. NN MM Block size of the 2nd block to load = 0xMMNN words
. BB AA Destination address of the second block Addr[31:16]
. DD CC Destination address of the second block Addr[15:0]
. BB AA First word of the second block in the source being loaded
. …
n n+1 BB AA Last word of the last block of the source being loaded
(More sections if required)
n+2 n+3 00 00 Block size of 0000h - indicates end of the source program

Implementing PC-side USB software is not trivial. It is recommended to use the TI-provided tools and drivers to
load data in USB boot mode. Hex and binary files for loader tools can be generated from COFF (.out) files using
the hex2000 tool. To produce a plain binary file in the boot loader format, use the following command line:
hex2000 -boot -b Program_to_Load.out -o Binary_Loader_Data.dat
For more information on hex2000, see the TMS320C28x Assembly Language Tools User's Guide.

Note
INTOSC2 must be enabled before invoking the USB boot loader. If INTOSC2 is not enabled, the
boot loader hangs. A debugger reset or SCC reset does not enable INTOSC2, if INTOSC2 has been
disabled by the application.

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5.7.8 GPIO Assignments for CPU1

This section details the GPIOs and boot option values used for each CPU1 boot mode set in the BOOT_DEF
memory location located at Z1-BOOTDEF-LOW/ Z2-BOOTDEF-LOW and Z1-BOOTDEF-HIGH/ Z2-BOOTDEF-
HIGH. Refer to Section 5.4.2 on how to configure BOOT_DEF. When selecting a boot mode option, make sure to
verify that the necessary pins are available in the pin mux options for the specific device package being used.

Note
These configurations only apply to CPU1. Refer to Section 5.7.2 for details on configuring CPU2 and
CM boot modes.

Table 5-53. SCI Boot Options

Option BOOTDEF Value SCITXDA GPIO SCIRXDA GPIO
0 (default) 0x01 GPIO29 GPIO28
1 0x21 GPIO84 GPIO85
2 0x41 GPIO36 GPIO35
3 0x61 GPIO42 GPIO43
4 0x81 GPIO65 GPIO64
5 0xA1 GPIO135 GPIO136
6 0xC1 GPIO8 GPIO9

Table 5-54. CAN Boot Options

Option BOOTDEF Value CANTXA GPIO CANRXA GPIO
0 (default) 0x02 GPIO37 GPIO36
1 0x22 GPIO71 GPIO70
2 0x42 GPIO63 GPIO62
3 0x62 GPIO19 GPIO18
4 0x82 GPIO4 GPIO5
5 0xA2 GPIO31 GPIO30

Table 5-55. I2C Boot Options

Option BOOTDEF Value SDAA GPIO SCLA GPIO
0 0x07 GPIO91 GPIO92
1 0x27 GPIO32 GPIO33
2 0x47 GPIO42 GPIO43
3 0x67 GPIO0 GPIO1
4 0x87 GPIO104 GPIO105

Table 5-56. USB Boot Options

Option BOOTDEF Value USBDM GPIO USBDP GPIO
0 (default) 0x09 GPIO42 GPIO43

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Table 5-57. RAM Boot Options

Option BOOTDEF Value RAM Entry Point
(Address)
0 0x05 0x0000 0000

Table 5-58. Flash Boot Options

Option BOOTDEF Value Flash Entry Point Flash Sector
(Address)
0 (default) 0x03 0x0008 0000 CPU1 Bank0 Sector 0
1 0x23 0x0008 8000 CPU1 Bank 0 Sector 4
2 0x43 0x000A 8000 CPU1 Bank 0 Sector 8
3 0x63 0x000B E000 CPU1 Bank 0 Sector 13

Table 5-59. Secure Flash Boot Options

Option BOOTDEF Value Flash Entry Point Flash Sector
(Address)
0 0x0A 0x0008 0000 CPU1 Bank0 Sector 0
1 0x2A 0x0008 8000 CPU1 Bank 0 Sector 4
2 0x4A 0x000A 8000 CPU1 Bank 0 Sector 8
3 0x6A 0x000B E000 CPU1 Bank 0 Sector 13

Table 5-60. Wait Boot Options

Option BOOTDEF Value Watchdog
0 0x04 Enabled
1 0x24 Disabled

Table 5-61. SPI Boot Options

Option BOOTDEF Value SPISIMOA SPISOMIA SPICLKA SPISTEA
0 0x06 GPIO58 GPIO59 GPIO60 GPIO61
1 0x26 GPIO16 GPIO17 GPIO18 GPIO19
2 0x46 GPIO32 GPIO33 GPIO34 GPIO35
3 0x66 GPIO16 GPIO17 GPIO56 GPIO57
4 0x86 GPIO54 GPIO55 GPIO56 GPIO57

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Table 5-62. Parallel Boot Options

Option BOOTDEF Value D0-D7 GPIO DSP Control GPIO Host Control GPIO
0 (default) 0x0 D0 - GPIO89 GPIO91 GPIO92
D1 - GPIO90
D2 - GPIO58
D3 - GPIO59
D4 - GPIO60
D5 - GPIO61
D6 - GPIO62
D7 - GPIO88

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5.7.9 Secure ROM Function APIs

Within secure ROM of each core, functions are available to be called by the application to perform EXEONLY
Flash/RAM tasks in a secure manner.

Note
The application must disable interrupts before calling one of the EXEONLY function APIs.
If a vector fetch request is given by the CPU (C28 or CM, depending on the subsystem) while the
corresponding program counter (PC) is within the EXEONLY function API code of the Secure ROM,
a reset occurs (RSN, if from C28; SYSRESETn, if from CM). The consequence of this is if an NMI,
ITRAP, or Bus Fault occurs while the PC is executing one of the EXEONLY API functions, the NMI/
ITRAP/Fault cannot be serviced because a reset occurs to that subsystem.

The secure copy code zone 1 and zone 2 functions allow EXEONLY Flash to be copied to EXEONLY RAM
in a secure manner. The source must be from EXEONLY Flash and the destination to EXEONLY RAM. There is
no support to copy EXEONLY ROM or EXEONLY RAM to RAM. Both Flash and RAM must be set to EXEONLY
and configured for the same zone. Additionally, the copy size must not cross over the Flash sector boundary.
Any violations of these requirements results in a failure status returned. Upon successful copy of the data, the
number of 16-bit words copied is returned.
Table 5-63. Secure Copy Code Function
CPU Function Prototype Function Parameters Function Return Value

Uint16 SecureCopyCodeZ1(Uint32 size : The number of 16-bit words to 0xXXXX : Returns the number of 16-
size, Uint16 *dst, Uint16 *src) copy bit words copied

dst : The destination memory address 0x0000 : Indicates one of the

CPU1, CPU2, CM in EXEONLY RAM following: Copy length is zero; Copy
size crosses over Flash sector
src : The source memory address in boundary; Flash and RAM do not
Uint16 SecureCopyCodeZ2(Uint32 EXEONLY Flash belong to the same zone; Flash or
size, Uint16 *dst, Uint16 *src) RAM are not set to EXEONLY; Error
occurred during data copy

The secure CRC calculation zone 1 and zone 2 functions allow a safety CRC check of EXEONLY memory
in a secure manner. The CRC length provided must be a value from 1 to 8 where 1 represents a CRC size
of 32 16-bit words and 8 represents a CRC size of 4096 16-bit words. The source address specifies the
starting address for the CRC and the destination address is the location that the resulting CRC value is stored.
The source and destination memories must be configured for the same zone. Additionally, the CRC length
must not cross over the Flash sector or RAM block boundary. On the CM, there is an additional requirement
that CRCLOCK is not enabled. Any violations of these requirements results in a failure status returned. Upon
successful CRC, the number of 16-bit words CRC'd is returned.
Table 5-64. Secure CRC Calculation Function
CPU Function Prototype Function Parameters Function Return Value

len_id : A number from 1 to 8 which

Uint16 SecureCRCCalcZ1(Uint16 corresponds to length options of 32, 0xXXXX : Returns the number of 16-
len_id, Uint16 *dst, Uint16 *src) 64, 128, 256, 512, 1024, 2048, or bit words CRC'd
4096 16-bit words

dst : The destination memory address 0x0000 : Indicates one of the

CPU1, CPU2, CM for resulting CRC following: Invalid length option; Source
address is not modulo of length value;
src : The source memory address to Destination address is not within
begin CRC calculation secure RAM; CRC size crosses over
Uint16 SecureCRCCalcZ2(Uint16 Flash sector or RAM block boundary;
size, Uint16 *dst, Uint16 *src) The source and destination memory
do not belong to the same zone; On
CM, CRCLOCK is enabled

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The calculate CMAC (Cipher-based Message Authentication Code) function calculates a CMAC tag for a
specified memory range using the user-set CMAC key in OTP and returns pass or failure depending if the
calculated tag matches the golden tag. The memory address range provided must align to a 128-bit boundary
(split evenly into 128-bit blocks). If this requirement is not met, the function returns a status indicating a boundary
violation. When using the CM CMAC function, there is an additional requirement that the CM must be running in
privileged mode.
For generating the secure Flash golden CMAC tag for CPU1 or CPU2, refer to the section "Using Secure Flash
Boot on TMS320F2838x Devices" in the TMS320C28x Assembly Language Tools User’s Guide for instructions.
For generating the secure Flash golden CMAC tag for CM, refer to the ARM Assembly Language Tools
v19.6.0.STS, within section "Using Secure Flash Boot on TMS320F2838x Devices" for instructions.
The 128-bit golden CMAC tag:
• Must be stored inside of the memory address range that the calculation is performed on.
• Another golden CMAC tag (from a different memory address range that is being authenticated) can not be
nested inside a different CMAC authentication memory address range. (For example, a CMAC on addresses
0x1000 to 0x2000 can not contain the golden CMAC tag for memory address ranges 0x4000 to 0x5000).
• The starting address of the golden CMAC tag must align to a 32-bit boundary, such as 0x80002 on CPU1/
CPU2 or 0x200004 on the CM.
• The CMAC calculation treats the memory addresses containing the golden tag as all ones.

Note
If calling this function, without running the secure Flash boot mode, then a dummy load must
be performed for the Z1 OTP CMACKEY before calling the function. Additionally, the Flash data
caching can be disabled before performing the dummy load and then the Flash data caching can be
re-enabled after the dummy load.

Table 5-65. Secure Flash CMAC Calculation Function

CPU Function Prototype Function Parameters Function Return Value
startAddress : The starting memory 0xFFFFFFFF : The calculated CMAC
address for the calculation (Example: tag does not match the golden tag
0x80000) (failure)
uint32_t
endAddress : The ending memory 0xA5A5A5A5 : The memory address
CPU1BROM_calculateCMAC(uint32_t
CPU1 address for the calculation (Example: range is not aligned to a 128-bit
startAddress, uint32_t endAddress, uint32_t
0x82000) boundary or length is zero
tagAddress)
tagAddress : The starting memory
0x00000000 : The calculated CMAC
address of where the golden CMAC
tag matches the golden tag (pass)
tag is stored. (Example: 0x80002)
startAddress : The starting memory 0xFFFFFFFF : The calculated CMAC
address for the calculation (Example: tag does not match the golden tag
0x80000) (failure)
uint32_t
endAddress : The ending memory 0xA5A5A5A5 : The memory address
CPU2BROM_calculateCMAC(uint32_t
CPU2 address for the calculation (Example: range is not aligned to a 128-bit
startAddress, uint32_t endAddress, uint32_t
0x82000) boundary or length is zero
tagAddress)
tagAddress : The starting memory
0x00000000 : The calculated CMAC
address of where the golden CMAC
tag matches the golden tag (pass)
tag is stored. (Example: 0x80002)

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Table 5-65. Secure Flash CMAC Calculation Function (continued)

CPU Function Prototype Function Parameters Function Return Value
0xFFFFFFFF : The calculated CMAC
tag does not match the golden tag
(failure)
startAddress : The starting memory
address for the calculation (Example:
0x200000)
0xA5A5A5A5 : The memory address
range is not aligned to a 128-bit
boundary or length is zero
endAddress : The ending memory
uint32_t
address for the calculation (Example:
CMBROM_calculateCMAC(uint32_t
CM
startAddress, uint32_t endAddress, uint32_t 0x200000)
tagAddress) 0x5A5A5A5A : The CM is not running
in privileged mode
tagAddress : The starting memory
address of where the golden CMAC
tag is stored. (Example: 0x200004)
0xE1E1E1E1: The CM AES engine
timed out. AES engine can not be
working as expected.

0x00000000 : The calculated CMAC

tag matches the golden tag (pass)

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5.7.10 Clock Initializations

During boot-up, the boot ROM initializes the device clocking, depending upon the reset source, to assist in faster
boot time response. Clock configurations are performed by the boot ROM code only for POR and XRS reset
types. For all other resets, the boot ROM starts executing with the clocks that were already set up before reset.

Note
Only CPU1 performs clock configurations during boot up. CPU1 application configures clocks for
CPU2 and CM before releasing them from reset. Refer to Section 5.7.2 for more details.
If the PLL is used during the CPU1 boot process, it will be bypassed by the boot ROM code before
branching to the user application.

Table 5-66. CPU1 Boot Clock Sources

Source Frequency Description
INTOSC2 10 MHz Default clock source
Set as clock source if missing clock is detected at power up or right
INTOSC1 10 MHz
after device reset
Enabled only as part of MPOST boot flow. PLL is bypassed
SYSPLL 110 MHz, 80 MHz, or 60 MHz and disabled after memory test has completed. See more details
regarding enabling MPOST in Section 5.7.1.1.
SYSPLL = 180 MHz Enabled only as part of USB Bootloader. Both PLLs are bypassed
SYSPLL and AUXPLL
AUXPLL = 60 MHz and disabled after the bootloader actions complete.

Table 5-67. CPU1 Clock State After Boot

Reset Source Clock State
1. Using INTOSC2
POR/XRS
2. System clock divider set to /1
All other Resets Maintain clocks setup before device reset.

5.7.11 Boot Status information

Boot ROM keeps a record of the various actions and events that occur during boot ROM execution. The
reason for this is because NMI and other exceptions are enabled by default in the device and must be handled
accordingly. Boot ROM stores the boot status information in a RAM location so that the user application can read
this boot status and take the necessary actions per application’s needs to handle these events.

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5.7.11.1 CPU1 Booting Status

CPU1 boot ROM health and booting status is written to a 32-bit address in M0RAM. This status is cleared on
a POR or XRS reset. The previous status is retained on any other reset. For example, a user should clear the
status before performing a debugger device reset in order to view the latest boot ROM actions reflected in the
status.
Table 5-68. CPU1 Boot Status Address
Description Address
CPU1 Boot ROM Status 0x0000 0002

Table 5-69. CPU1 Boot Status Bit Fields

Bit Description
31 CPU1 Boot ROM has finished running
30 Missing clock NMI occurred
29 RAM Uncorrectable Error NMI or ROM Parity Error occurred
28 Flash Uncorrectable Error NMI occurred
27 HWBIST NMI occurred
26 PIE Vector NMI occurred
25 RL NMI occurred
24 PIE Mismatch occurred
23 ITRAP occurred
22 ERAD NMI occurred
21 EtherCAT NMI occurred
20 MCAN NMI occurred
19 SYSPLL or AUXPLL failed to enable
18 MPOST (Memory Power On Self-Test) Complete
17 RAM Initialization Complete
16 DCSM Initialization Complete
15 HWBIST Reset Handled
14 POR Reset Handled
13 XRS Reset Handled
12 All Resets Handled
11:8 Not Used
0x0 = Invalid / No Status set yet
0x1 = CPU1 Boot ROM has started running
0x2 = Running Flash Boot
0x3 = Running Secure Flash Boot
0x4 = Running Parallel Boot
0x5 = Running RAM Boot
7:0
0x6 = Running SCI Boot
0x7 = Running SPI Boot
0x8 = Running I2C Boot
0x9 = Running CAN Boot
0xA = Running USB Boot
0xB = Running Wait Boot

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5.7.11.2 CPU2 Booting Status

CPU2 boot ROM health and booting status is written to a 32-bit address in M0RAM. This status is cleared on
every CPU2 reset. Additionally, a copy of the status is written to CPU2TOCPU1IPCBOOTSTS for CPU1 to have
access to CPU2's boot status.
Table 5-70. CPU2 Boot ROM Status Address
Description Address
CPU2 Boot ROM Status 0x0000 0002

Table 5-71. CPU2 Boot Status Bit Fields

Bit Description
31 CPU2 Boot ROM has finished running
30 Missing clock NMI occurred
29 RAM Uncorrectable Error NMI or ROM Parity Error occurred
28 Flash Uncorrectable Error NMI occurred
27 HWBIST NMI occurred
26 PIE Vector NMI occurred
25 RL NMI occurred
24 PIE Mismatch occurred
23 ITRAP occurred
22 ERAD NMI occurred
21 Secure Flash Boot CMAC returned failure
20 Not Used
Invalid length specified in CPU1TOCPU2IPCBOOTMODE for IPC message RAM copy
19
length
18 Invalid (or missing configuration) in CPU1TOCPU2IPCBOOTMODE
17 RAM Initialization Complete
16 Not Used
15 HWBIST Reset Handled
14 POR Reset Handled
13 XRS Reset Handled
12 All Resets Handled
11:8 Not Used
0x0 = Invalid / No Status set yet
0x1 = CPU2 Boot ROM has started running
0x2 = Running Flash Boot
0x3 = Running Secure Flash Boot
7:0 0x4 = Running IPC Message Copy to RAM Boot
0x5 = Running RAM Boot
0x6 = Running User OTP Boot
0x7 = Running Wait Boot
0x8 = Waiting for CPU1 to set CPU1TOCPU2IPCFLG0 to allow CPU2 to start booting

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5.7.11.3 CM Booting Status

CM boot ROM health and booting status is written to a 32-bit address in S0RAM. This status is cleared on every
CM reset. Additionally, a copy of the status is written to CMTOCPU1IPCBOOTSTS for CPU1 to have access to
the CM's boot status.
Table 5-72. CM Boot ROM Status Address
Description Address
CM Boot ROM Status 0x2000 0000

Table 5-73. CM Boot Status Bit Fields

Bit Description
31 CM Boot ROM has finished running
30 Missing clock NMI occurred
29 RAM Uncorrectable Error NMI or ROM Parity Error occurred
28 Flash Uncorrectable Error NMI occurred
27 MCAN NMI occurred
26 Windowed Watchdog NMI occurred
25 An EtherCAT NMI occurred
24 Not Used
23 Hard Fault occurred
22 Unassigned interrupt occurred
21 Secure Flash Boot CMAC returned failure
20 Not Used
19 Invalid length specified in CPU1TOCMIPCBOOTMODE for IPC message RAM copy length
18 Invalid (or missing configuration) in CPU1TOCMIPCBOOTMODE
17 RAM Initialization Complete
16:15 Not Used
14 POR Reset Handled
13 Not Used
12 All Resets Handled
11:8 Not Used
0x0 = Invalid / No Status set yet
0x1 = CM Boot ROM has started running
0x2 = Running Flash Boot
0x3 = Running Secure Flash Boot
7:0 0x4 = Running IPC Message Copy to RAM Boot
0x5 = Running RAM Boot
0x6 = Running User OTP Boot
0x7 = Running Wait Boot
0x8 = Waiting for CPU1 to set CPU1TOCMIPCFLG0 to allow CM to start booting

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5.7.11.4 Boot Mode and MPOST (Memory Power On Self-Test) Status

Once the boot mode is decoded during the boot flow for each core, the boot mode value is written to RAM.
Additionally, on CPU1, when running the MPOST POR memory test, the test result is written to RAM.
For more information, see the C2000™ Memory Power-On Self-Test (M-POST) Application Report.
Table 5-74. Boot Mode and MPOST Status Addresses
Description Address
CPU1 Boot Mode 0x0000 0004
CPU2 Boot Mode 0x0000 0004
CM Boot Mode 0x2000 0004
MPOST Result
0x0000 0006
(CPU1 Only)

5.7.12 ROM Version

The ROM revision and release date information is stored at the ROM locations specified in this section. Reading
a revision number value of “0x100” represents version “1.0”, “0x101” represents version “1.1”, and so on.
Reading a revision date value of “0x0916” represents “09/16” or “September 2016”.
Table 5-75. Boot ROM Version Information for CPU1
Start Address End Address Contents Silicon Revision 0 Values Silicon Revision A Values
0x003F FF7A 0x003F FF7A Revision Number 0x0100 0x0200
0x003F FF7B 0x003F FF7B Revision Date 0x0418 0x0819

Table 5-76. Boot ROM Version Information for CPU2

Start Address End Address Contents Silicon Revision 0 Values Silicon Revision A Values
0x003F FF7A 0x003F FF7A Revision Number 0x0100 0x0100
0x003F FF7B 0x003F FF7B Revision Date 0x0418 0x0418

Table 5-77. Boot ROM Version Information for CM

Start Address End Address Contents Silicon Revision 0 Values Silicon Revision A Values
0x0000 0140 0x0000 0141 Revision Number 0x0100 0x0200
0x0000 0142 0x0000 0143 Revision Date 0x0418 0x0819

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5.8 Application Notes for Using the Bootloaders

5.8.1 Boot Data Stream Structure
This section details the data transfer protocols or stream structures that allow boot data transfer between boot
ROM and host device. This data transfer protocol is compatible to the respective bootloaders on C2000 devices.
5.8.1.1 Bootloader Data Stream Structure
The following table and associated examples show the structure of the data stream incoming to the bootloader.
The basic structure is the same for all the bootloaders and is based on the C54x source data stream generated
by the C54x hex utility. The C28x hex utility (hex2000.exe) has been updated to support this structure. The
hex2000.exe utility is included with the C2000 code generation tools. All values in the data stream structure are
in hex. Refer to The C2000 Hex Utility for more details on using the C28x hex utility to convert a project to this
format.
The first 16-bit word in the data stream is known as the key value. The key value is used to tell the bootloader
the width of the incoming stream: 8 or 16 bits. Note that not all bootloaders accept both 8- and 16-bit streams.
Refer to the detailed information on each loader for the valid data stream width. For an 8-bit data stream, the key
value is 0x08AA and for a 16-bit stream the key value is 0x10AA. If a bootloader receives an invalid key value,
then the load is aborted.
The next eight words are used to initialize register values or otherwise enhance the bootloader by passing
values to the bootloader. If a bootloader does not use these values, then the values are reserved for future use
and the bootloader simply reads the value and then discards the value. Currently only the SPI and I2C and
parallel bootloaders use these words to initialize registers.
The tenth and eleventh words comprise the 22-bit entry point address. This address is used to initialize the PC
after the boot load is complete. This address is most likely the entry point of the program downloaded by the
bootloader.
The twelfth word in the data stream is the size of the first data block to be transferred. The size of the block is
defined as 8-bit data stream format. For example, to transfer a block of 20 8-bit data values from an 8-bit data
stream, the block size is 0x000A to indicate 10 16-bit words.
The next two words indicate to the loader the destination address of the block of data. Following the size and
address is the 16-bit words that makeup that block of data.
This pattern of block size/destination address repeats for each block of data to be transferred. Once all the
blocks have been transferred, a block size of 0x0000 signals to the loader that the transfer is complete. At this
point, the loader returns the entry point address to the calling routine that exits. Execution continues at the entry
point address as determined by the input data stream contents.

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Table 5-78. LSB/MSB Loading Sequence in 8-Bit Data Stream

Byte Contents
LSB (First Byte of 2) MSB (Second Byte of 2)
1 2 LSB: AA (KeyValue for memory width = 8 bits) MSB: 08h (KeyValue for memory width = 8 bits)
3 4 LSB: Register initialization value or reserved MSB: Register initialization value or reserved
5 6 LSB: Register initialization value or reserved MSB: Register initialization value or reserved
7 8 LSB: Register initialization value or reserved MSB: Register initialization value or reserved
... ... ... ...
... ... ... ...
17 18 LSB: Register initialization value or reserved MSB: Register initialization value or reserved
19 20 LSB: Upper half of Entry point PC[23:16] MSB: Upper half of entry point PC[31:24] (Always 0x00)
21 22 LSB: Lower half of Entry point PC[7:0] MSB: Lower half of Entry point PC[15:8]
23 24 LSB: Block size in words of the first block to load. If the MSB: block size
block size is 0, this indicates the end of the source program;
otherwise, another block follows. For example, a block size of
0x000A indicates 10 words or 20 bytes in the block.
25 26 LSB: MSW destination address, first block Addr[23:16] MSB: MSW destination address, first block Addr[31:24]
27 28 LSB: LSW destination address, first block Addr[7:0] MSB: LSW destination address, first block Addr[15:8]
29 30 LSB: First word of the first block being loaded MSB: First word of the first block being loaded
... ... ... ...
... ... ... ...
. . LSB: Last word of the first block to load MSB: Last word of the first block to load
. . LSB: Block size of the second block MSB: Block size of the second block
. . LSB: MSW destination address, second block Addr[23:16] MSB: MSW destination address, second block Addr[31:24]
. . LSB: LSW destination address, second block Addr[7:0] MSB: LSW destination address, second block Addr[15:8]
. . LSB: First word of the second block being loaded MSB: First word of the second block being loaded
... ... ... ...
... ... ... ...
. . LSB: Last word of the second block MSB: Last word of the second block
. . LSB: Block size of the last block MSB: Block size of the last block
. . LSB: MSW of destination address of last block Addr[23:16] MSB: MSW destination address, last block Addr[31:24]
. . LSB: LSW destination address, last block Addr[7:0] MSB: LSW destination address, last block Addr[15:8]
. . LSB: First word of the last block being loaded MSB: First word of the last block being loaded
... ... ... ...
... ... ... ...
. . LSB: Last word of the last block MSB: Last word of the last block
n n+1 LSB: 00h MSB: 00h - indicates the end of the source

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Example 5-2. Data Stream Structure 8-bit

AA 08 ; 0x08AA 8-bit key value

00 00 00 00 ; 8 reserved words
00 00 00 00
00 00 00 00
00 00 00 00
3F 00 00 80 ; 0x003F8000 EntryAddr, starting point after boot load completes
05 00 ; 0x0005 - First block consists of 5 16-bit words
3F 00 10 90 ; 0x003F9010 - First block will be loaded starting at 0x3F9010
01 00 ; Data loaded = 0x0001 0x0002 0x0003 0x0004 0x0005
02 00
03 00
04 00
05 00
02 00 ; 0x0002 - 2nd block consists of 2 16-bit words
3F 00 00 80 ; 0x003F8000 - 2nd block will be loaded starting at 0x3F8000
00 77 ; Data loaded = 0x7700 0x7625
25 76
00 00 ; 0x0000 - Size of 0 indicates end of data stream
After load has completed the following memory values will have been initialized as follows:
Location Value
0x3F9010 0x0001
0x3F9011 0x0002
0x3F9012 0x0003
0x3F9013 0x0004
0x3F9014 0x0005
0x3F8000 0x7700
0x3F8001 0x7625
PC Begins execution at 0x3F8000

5.8.2 The C2000 Hex Utility

To use the features of the bootloader, you must generate a data stream and boot table as described in Section
5.8.1.1. The hex conversion utility tool, included with the 28x code generation tools, can generate the required
data stream including the required boot table. This section describes the hex2000 utility. An example of a file
conversion performed by hex2000 is described in Example 5-3.
The hex utility supports creation of the boot table required for the SCI, SPI, I2C, CAN, and parallel I/O loaders.
That is, the hex utility adds the required information to the file such as the key value, reserved bits, entry point,
address, block start address, block length and terminating value. The contents of the boot table vary slightly
depending on the boot mode and the options selected when running the hex conversion utility. The actual file
format required by the host (ASCII, binary, hex, and so on) differs from one specific application to another and
some additional conversion may be required.
To build the boot table, follow these steps:
1. Assemble or compile the code.
This creates the object files that then is used by the linker to create a single output file.
2. Link the file.
The linker combines all of the object files into a single output file in common object file format (ELF). The
specified linker command file is used by the linker to allocate the code sections to different memory blocks.
Each block of the boot table data corresponds to an initialized section in the ELF file. Uninitialized sections
are not converted by the hex conversion utility. The following options can be useful:

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The linker -m option can be used to generate a map file. This map file shows all of the sections that were
created, their location in memory, and their length. It can be useful to check this file to make sure that the
initialized sections are where you expect them to be.
The linker -w option configures the linker to show if the linker assigned a section to a memory region
automatically. For example, if you have a section in your code called .TI.ramfunc.
3. Run the hex conversion utility.
Choose the appropriate options for the desired boot mode and run the hex conversion utility to convert the
ELF file produced by the linker to a boot table.
See the TMS320C28x Assembly Language Tools User's Guide and the TMS320C28x Optimizing C/C++
Compiler User's Guide for more information on the compiling and linking process.
Table 5-79 summarizes the hex conversion utility options available for the bootloader. See the TMS320C28x
Assembly Language Tools User's Guide for a detailed description of the hex2000 operations used to generate a
boot table. Updates are made to support the I2C boot. See the Codegen release notes for the latest information.
Table 5-79. Boot Loader Options
Option Description
-boot Convert all sections into bootable form (use instead of a SECTIONS directive)
-sci8 Specify the source of the bootloader table as the SCI-A port, 8-bit mode
-spi8 Specify the source of the bootloader table as the SPI-A port, 8-bit mode
-gpio8 Specify the source of the bootloader table as the GPIO port, 8-bit mode
-bootorg value Specify the source address of the bootloader table
-lospcp value Specify the initial value for the LOSPCP register. This value is used only for the spi8 boot table format and
ignored for all other formats. If the value is greater than 0x7F, the value is truncated to 0x7F.
-spibrr value Specify the initial value for the SPIBRR register. This value is used only for the spi8 boot table format and
ignored for all other formats. If the value is greater than 0x7F, the value is truncated to 0x7F.
-e value Specify the entry point at which to begin execution after boot loading. The value can be an address or a global
symbol. This value is optional. The entry point can be defined at compile time using the linker -e option to assign
the entry point to a global symbol. The entry point for a C program is normally _c_int00 unless defined otherwise
by the -e linker option.
-i2c8 Specify the source of the bootloader table as the I2C-A port, 8-bit
-i2cpsc value Specify the value for the I2CPSC register. This value is loaded and takes effect after all I2C options are loaded,
prior to reading data from the EEPROM. This value is truncated to the least-significant eight bits and must be set
to maintain an I2C module clock of 7-12 MHz.
-i2cclkh value Specify the value for the I2CCLKH register. This value is loaded and takes effect after all I2C options are loaded,
prior to reading data from the EEPROM.
-i2cclkl value Specify the value for the I2CCLKL register. This value is loaded and takes effect after all I2C options are loaded,
prior to reading data from the EEPROM.

Example 5-3. HEX2000.exe Command Syntax

C: HEX2000 GPIO34TOG.OUT -boot -gpio8 -a

Where:
- boot Convert all sections into bootable form.
- gpio8 Use the GPIO in 8-bit mode data format. The eCAN uses the same data format as the GPIO in
8-bit mode.
- a Select ASCII-Hex as the output format.

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5.9 Software
5.9.1 BOOT Examples
NOTE: These examples are located in the C2000Ware installation at the following location:
C2000Ware_VERSION#/driverlib/DEVICE_GPN/examples/CORE_IF_MULTICORE/boot
Cloud access to these examples is available at the following link: dev.ti.com C2000Ware Examples.
5.9.1.1 CM Secure Flash Boot
FILE: boot_ex1_cpu1_cpu2_cm_secure_flash_cm.c
This example demonstrates how to use the secure flash boot mode for CM. (Requires CPU1 example
application)
Secure flash boot performs a CMAC authentication on the entry sector of flash upon device boot up. If
authentication passes, the application will begin execution. Learn more on the secure flash boot mode in the
device technical reference manual.
This project shows how to use the C2000 HEX Utility to generate a CMAC Tag based on a user CMAC key and
embed the value into the flash application. Additionally, the example details the method to call the CMAC API
from the user application to calculate CMAC on other flash sectors beyond the the application entry flash sector.
Determining Pass/Fail without debugger connected: CM - ControlCARD LED3.
• LED off = Secure Boot failed
• LED On (Solid) = Secure Boot Passed, Full Flash CMAC failed
• LED Blinking = Secure Boot Passed and Full Flash CMAC passed
External Connections
• None.
Watch Variables
• None.
5.9.1.2 CPU1 Secure Flash Boot
FILE: boot_ex1_cpu1_cpu2_cm_secure_flash_cpu1.c
This example demonstrates how to use the secure flash boot mode for CPU1 as well as release CPU2 and CM
for secure flash boot.
Secure flash boot performs a CMAC authentication on the entry sector of flash upon device boot up. If
authentication passes, the application will begin execution. Learn more on the secure flash boot mode in the
device technical reference manual.
This project shows how to use the C2000 HEX Utility to generate a CMAC Tag based on a user CMAC key and
embed the value into the flash application. Additionally, the example details the method to call the CMAC API
from the user application to calculate CMAC on other flash sectors beyond the the application entry flash sector.
How to Run:
• Load application into CPU1 flash (as well as CPU2 and CM applications)
• Disconnect and reconnect to only CPU1
• In memory window, set address 0xD00/D01 to 0x5AFFFFFF and address 0xD04 to 0x000A (This sets
emulation boot to secure flash boot)
• Reset CPU1 via CCS and click resume
• Observe the LEDs
Determining Pass/Fail without debugger connected: CPU1 - ControlCARD LED1.
• LED off = Secure Boot failed
• LED On (Solid) = Secure Boot Passed, Full Flash CMAC failed
• LED Blinking = Secure Boot Passed and Full Flash CMAC passed CPU2 - ControlCARD LED2.
• LED off = Secure Boot failed

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• LED On (Solid) = Secure Boot Passed, Full Flash CMAC failed

• LED Blinking = Secure Boot Passed and Full Flash CMAC passed CM - ControlCARD LED3.
• LED off = Secure Boot failed
• LED On (Solid) = Secure Boot Passed, Full Flash CMAC failed
• LED Blinking = Secure Boot Passed and Full Flash CMAC passed
External Connections
• None.
Watch Variables
• cpu1_SuccessfullyBooted - True when CPU1 full flash CMAC authentication passes. Otherwise, false.
• cpu2_SuccessfullyBooted - True when CPU2 full flash CMAC authentication passes and CPU1 receives IPC.
Otherwise, false.
• cm_SuccessfullyBooted - True when CM full flash CMAC authentication passes and CPU1 receives IPC.
Otherwise, false.
5.9.1.3 CPU2 Secure Flash Boot
FILE: boot_ex1_cpu1_cpu2_cm_secure_flash_cpu2.c
This example demonstrates how to use the secure flash boot mode for CPU2. (Requires CPU1 example
application)
Secure flash boot performs a CMAC authentication on the entry sector of flash upon device boot up. If
authentication passes, the application will begin execution. Learn more on the secure flash boot mode in the
device technical reference manual.
This project shows how to use the C2000 HEX Utility to generate a CMAC Tag based on a user CMAC key and
embed the value into the flash application. Additionally, the example details the method to call the CMAC API
from the user application to calculate CMAC on other flash sectors beyond the the application entry flash sector.
Determining Pass/Fail without debugger connected: CPU2 - ControlCARD LED2.
• LED off = Secure Boot failed
• LED On (Solid) = Secure Boot Passed, Full Flash CMAC failed
• LED Blinking = Secure Boot Passed and Full Flash CMAC passed
External Connections
• None.
Watch Variables
• None.

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www.ti.com Dual Code Security Module (DCSM)

Chapter 6
Dual Code Security Module (DCSM)

This chapter explains the dual code security module.

6.1 Introduction...............................................................................................................................................................766
6.2 Functional Description.............................................................................................................................................766
6.3 Flash and OTP Erase/Program................................................................................................................................774
6.4 Secure Copy Code....................................................................................................................................................774
6.5 SecureCRC................................................................................................................................................................775
6.6 CSM Impact on Other On-Chip Resources.............................................................................................................775
6.7 Incorporating Code Security in User Applications................................................................................................777
6.8 Software.................................................................................................................................................................... 782
6.9 DCSM Registers........................................................................................................................................................784

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6.1 Introduction
The dual code security module (DCSM) is a security feature incorporated in this device. It prevents access and
visibility to on-chip secure memories (and other secure resources) by unauthorized persons. It also prevents
duplication and reverse-engineering of proprietary code. The term “secure” means that access to on-chip secure
memories and resources is blocked. The term “unsecure” means that access is allowed; that is, the contents
of the memory could be read by any means (for example, through a debugging tool such as Code Composer
Studio™ IDE.
There are two security zones, Zone1 (Z1) and Zone2 (Z2). Unlike earlier C2000 devices where each CPU
subsystem had two security zones, on this device, both security zones are shared by each CPU subsystem.
This means secure resources from each CPU subsystem are allocated to Zone1 or Zone2. All the security
configurations are controlled by the CPU1 subsystem only (programmed in CPU1 USER OTP). Other CPU
subsystems have only read access to these configurations via their own memory map registers.
6.1.1 DCSM Related Collateral

Getting Started Materials

• C2000 DCSM Security Tool Application Report
• C2000 Unique Device Number Application Report
• Enhancing Device Security by Using JTAGLOCK Feature Application Report
• Secure BOOT On C2000 Device Application Report
6.2 Functional Description
The security module restricts the CPU access to on-chip secure memory and resources without interrupting
or stalling CPU execution. When a read occurs to a secure memory location, the read returns a zero value
and CPU execution continues with the next instruction. This, in effect, blocks read and write access to secure
memories through the JTAG port or external peripherals.
The code security mechanism offers protection for two zones, Zone1 (Z1) and Zone2 (Z2). The security
mechanism for both the zones is identical. Each zone has its own dedicated secure resource and allocated
secure resource. The following are different secure resources available on this device:
• OTP: Each zone has its own dedicated secure OTP (USER OTP) on CPU1 subsystem. This contains the
security configurations for the individual zone. If a zone is secure, its USER OTP content (including CSM
passwords) can be read (execution not allowed) only if the zone is unlocked using the password match flow
(PMF).
• RAM: All Dx and LSx RAMs on C28x and C0/C1 RAMs on the Connectivity Manager(CM) can be secure
RAM on this device. On this device IPC MSG RAMs between different subsystems can also be configured
to be secure RAM. This enables secure message exchange between CPU subsystems. These RAMs can be
allocated to either zone by configuring the respective GRABRAM locations in the CPU1 USER OTP.
• Flash Sectors: Flash sectors of each CPU subsystems can be made secure on this device. Each Flash
sector can be allocated to either zone by configuring the respective GRABSECT locations in the CPU1 USER
OTP.
• Secure ROM: This device also has secure ROM on each CPU subsystem which is EXEONLY-protected.
These ROM contains specific function for the user, provided by TI.
Table 6-1 shows the status of a RAM block/Flash sector based on the configuration in the GRABRAM/
GRABSECT register.
The security of each zone is ensured by its own 128-bit (four 32-bit words) password (CSM password). The
password for each zone is stored in CPU1 USER OTP. A zone can be unsecured by executing the password
match flow (PMF), described in Section 6.7.4.

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Table 6-1. RAM/Flash Status

Zone 1 Zone 2
GRAMRAMx/GRABSECTx Bits GRAMRAMx/GRABSECT Bits Ownership and Accessibility
01 10 RAM block/Flash Sector belongs to Zone1
01 11(2) RAM block/Flash Sector belongs to Zone1
10 01 RAM block/Flash Sector belongs to Zone2
11(1) 01 RAM block/Flash Sector belongs to Zone2
10 10 RAM block/Flash Sector is unsecure
11 11 If both zones are unsecure, then RAM block/Flash is
unsecure. RAM block/Flash Sector inaccessible if either
of the zone is secure (CSM passwords are programmed).
User should never leave these values default (11) if CSM
passwords are programmed for even one zone.

(1) Zone1 must be unsecure. Assumption in this case is that user is not using Zone1 so none of the fields, including passwords, in Zone1
USER OTP are programmed by user hence Zone1 will always be unsecure.
(2) Zone2 must be unsecure. Assumption in this case is that user is not using Zone2 so none of the fields, including passwords, in Zone2
USER OTP are programmed by user hence Zone2 will always be unsecure.

Note
You should never program any other values in these fields. Failing any these conditions for a RAM
block/Flash sector will make that RAM block/Flash sector inaccessible.

There are three types of accesses:

• Data/program reads: Data reads to a secure memory are always blocked unless the program is executing
from a memory that belongs to the same zone. Data reads to unsecure memory are always allowed.
• JTAG access: JTAG accesses are always blocked when a memory is secure.
• Instruction fetches (calls, jumps, code executions, ISRs): Instruction fetches are never blocked.
Table 6-2 shows the levels of security.
Table 6-2. Security Levels
PMF Executed With Correct
Password? Operating Mode of the Zone Program Fetch Location Security Description
No Secure Outside secure memory Only instruction fetches by the CPU are
allowed to secure memory. In other words,
code can still be executed, but not read.
No Secure Inside secure memory CPU has full access (except for EXEONLY
memories where read is not allowed). JTAG
port cannot read the secured memory
contents.
Yes Unsecure Anywhere Full access for CPU and JTAG port to secure
memory of that zone.

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6.2.1 CSM Passwords

Unlike earlier C2000™ devices, on this device ALL_1 value
(0xFFFFFFFF,0xFFFFFFFF,0xFFFFFFFF,0xFFFFFFFF) for CSM password for a zone does not unsecure the
zone. Instead, if for any zone the CSM password values get loaded as ALL_1 from USER OTP, the device
will be in BLOCKED state. Due to this reason TI will program a few bits in the second 32-bit password
value (ZxOTP_CSMPSWD1) in every zone select block of each zone with value ‘0’. The default value
for this password location is chosen in a manner that the respective ECC value remains ALL_1. Due to
this, the CSMPSWD1 value programmed by TI for every zone select block is different. See Table 6-3 for
ZxOTP_CSMPSWD1 value, programmed by TI on every device. Since ECC is not programmed, the user will
be able to change this value by flipping the bits which are ‘1’ to ‘0’ but leaving the ones which are already
programmed by TI as ‘0’. BOOTROM code will write the default password value into the KEYx register to unlock
the device as part of device initialization sequence.
If the password locations of a zone have all 128 bits as zeros (ALL_0), that zone becomes permanently
secure (LOCKED state), regardless of the contents of the CSMKEYx registers which means the zone cannot
be unlocked using PMF, the password match flow described in Section 6.7.4. Therefore, the user should never
use ALL_0 as password. A password of ALL_0 will prevent debug of secure code or reprogramming the Flash
sectors. CSMKEYx registers are user-accessible registers that are used to unsecure the zones.

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Table 6-3. Default Value of ZxOTP (Programmed by TI)

Zone Select Block Zone1 USER OTP Zone2 USER OTP
Address Value Address Value
JLM_ENABLE 0x00078006 0xffff000f NA NA
(JTAGLOCK)
PSWDLOCK 0x00078010 0xfb7fffff 0x00078210 0x1f7fffff
CRCLOCK 0x00078012 0x7fffffff 0x00078212 0x3fffffff
JTAGPSWDH0 0x00078014 0x4bffffff NA NA
JTAGPSWDH1 0x00078016 0x3fffffff NA NA
Zone_Select_Block0 0x00078022 (CSMPSWD1) 0x4d7fffff 0x00078222 (CSMPSWD1) 0x1f7fffff
Zone_Select_Block0 0x0007803e (JTAGPSWDL1) 0x2bffffff NA NA
Zone_Select_Block1 0x00078042 (CSMPSWD1) 0x5f7fffff 0x00078242 (CSMPSWD1) 0xe57fffff
Zone_Select_Block1 0x0007805e (JTAGPSWDL1) 0x27ffffff NA NA
Zone_Select_Block2 0x00078062 (CSMPSWD1) 0x1dffffff 0x00078262 (CSMPSWD1) 0x4fffffff
Zone_Select_Block2 0x0007807e (JTAGPSWDL1) 0x7b7fffff NA NA
Zone_Select_Block3 0x00078082 (CSMPSWD1) 0xaf7fffff 0x00078282 (CSMPSWD1) 0xe37fffff
Zone_Select_Block3 0x0007809e (JTAGPSWDL1) 0xc9ffffff NA NA
Zone_Select_Block4 0x000780a2 (CSMPSWD1) 0x1bffffff 0x000782a2 (CSMPSWD1) 0x57ffffff
Zone_Select_Block4 0x000780be (JTAGPSWDL1) 0x7d7fffff NA NA
Zone_Select_Block5 0x000780c2 (CSMPSWD1) 0x17ffffff 0x000782c2 (CSMPSWD1) 0x5bffffff
Zone_Select_Block5 0x000780de (JTAGPSWDL1) 0x6f7fffff NA NA
Zone_Select_Block6 0x000780e2 (CSMPSWD1) 0xbd7fffff 0x000782e2 (CSMPSWD1) 0xf17fffff
Zone_Select_Block6 0x000780fe (JTAGPSWDL1) 0x33ffffff NA NA
Zone_Select_Block7 0x00078102 (CSMPSWD1) 0x9f7fffff 0x00078302 (CSMPSWD1) 0x3b7fffff
Zone_Select_Block7 0x0007811e (JTAGPSWDL1) 0x0fffffff NA NA
Zone_Select_Block8 0x00078122 (CSMPSWD1) 0x2bffffff 0x00078322 (CSMPSWD1) 0x8fffffff
Zone_Select_Block8 0x0007813e (JTAGPSWDL1) 0xbb7fffff NA NA
Zone_Select_Block9 0x00078142 (CSMPSWD1) 0x27ffffff 0x00078342 (CSMPSWD1) 0x6bffffff
Zone_Select_Block9 0x0007815e (JTAGPSWDL1) 0x5f7fffff NA NA
Zone_Select_Block10 0x00078162 (CSMPSWD1) 0x7b7fffff 0x00078362 (CSMPSWD1) 0x377fffff
Zone_Select_Block10 0x0007817e (JTAGPSWDL1) 0x1dffffff NA NA
Zone_Select_Block11 0x00078182 (CSMPSWD1) 0xc9ffffff 0x00078382 (CSMPSWD1) 0x9bffffff
Zone_Select_Block11 0x0007819e (JTAGPSWDL1) 0xaf7fffff NA NA
Zone_Select_Block12 0x000781a2 (CSMPSWD1) 0x7d7fffff 0x000783a2 (CSMPSWD1) 0x2f7fffff
Zone_Select_Block12 0x000781be (JTAGPSWDL1) 0x1bffffff NA NA
Zone_Select_Block13 0x000781c2 (CSMPSWD1) 0x6f7fffff 0x000783c2 (CSMPSWD1) 0xcb7fffff
Zone_Select_Block13 0x000781de (JTAGPSWDL1) 0x17ffffff NA NA
Zone_Select_Block14 0x000781e2 (CSMPSWD1) 0x33ffffff 0x000783e2 (CSMPSWD1) 0x97ffffff
Zone_Select_Block14 0x000781fe (JTAGPSWDL1) 0xbd7fffff NA NA

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6.2.2 Emulation Code Security Logic (ECSL)

In addition to the CSM, the emulation code security logic (ECSL) has been implemented using a 64-bit password
(part of existing CSM password) for each zone to prevent unauthorized users from stepping through secure
code. A halt in secure code while the emulator is connected will trip the ECSL and break the emulation
connection. To allow emulation of secure code, while maintaining the CSM protection against secure memory
reads, the user must write the correct 64-bit password into the CSMKEY (0/1) registers, which matches the
password value stored in the USER OTP of that zone. This will disable the ECSL for the specific zone.
When initially debugging a device with the password locations in OTP programmed (secured), the emulator
takes some time to take control of the CPU. During this time, the CPU will start running and may execute an
instruction that performs an access to a protected ECSL area and if the CPU is halted when the program counter
(PC) is pointing to a secure location, the ECSL will trip and cause the emulator connection to be broken.
The solution to this problem is:
• Use the Wait Boot Mode boot option. In this mode, the CPU will be in a loop and hence will not jump to the
user application code. Using this BOOTMODE, the user can connect to CCS and debug the code.
6.2.3 CPU Secure Logic
The CPU Secure Logic (CPUSL) on this device prevents a hacker from reading the CPU registers in a watch
window while code is running in a secure zone. All accesses to CPU registers when the PC points to a secure
location are blocked by this logic. The only exception to this is read access to the PC. It is highly recommended
not to write into the CPU register in this case, because proper code execution may get affected. If the CSM is
unlocked using the CSM password match flow, the CPUSL logic also gets disabled.
6.2.4 Execute-Only Protection
To achieve a higher level of security on secure Flash sectors and RAM blocks that store critical user code
(instruction opcodes), the Execute-Only protection feature is provided. When the Execute-Only protection is
turned on for any secure Flash sector or RAM block, data reads to that Flash sector or RAM block are disallowed
from any code (even from secure code). Execute-only protection for a Flash sector and RAM block can be
turned on by configuring the bit field associated for that particular sector/RAM block in the zone's (which has
ownership of that sector/RAM block) EXEONLYSECT and EXEONLYRAM register, respectively.
6.2.5 Password Lock
The password locations in USER OTP for each zone can be locked by programming the zone’s PSWDLOCK
field with any value other than “1111” (0xF) at the PSWDLOCK location in OTP. Until the passwords of a
zone are locked, password locations will not be secure and can be read from the debugger as well as code
running from non-secure memory. This feature can be used by the user to avoid accidental locking of the zone
while programming the Flash sectors during the software development phase. On a fresh device the value for
password lock fields for all zones at the PSWDLOCK location in OTP will be “1111” which means the password
for all zones will be unlocked.

Note
Password unlock only makes password locations non-secure. All other secure memories remains
secure as per security settings. Since password locations are non-secure, anyone can read the
password and make the zone un-secure by running through PMF, user must program PSWDLOCK
locations to lock the password before sending the device in field.

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6.2.6 JTAGLOCK
Sometimes you want to disable the JTAG access on a device to avoid any debug access to it. This can be done
by using the JTAGLOCK feature on this device. You need to follow a two step process to enable the JTAGLOCK
feature (both steps can be performed at the same time).
1. Program the JTAG passwords. This device has a 128-bit JTAG password that needs to be programmed
in Z1 USER OTP of CPU1. JTAG passwords are split into two parts, JTAGPSWDH and JTAGPSWDL.
JTAGPSWDH is part of the Z1 USER OTP header and JTAGPSWDL is part of the Z1 Zone Select Block
(ZSB). What this means is program JTAGPSWDH once and change the JTAGPSWDL multiple times, if
needed. The Code Composer Studio™ IDE has an integrated tool that you need to use to unlock the
JTAGLOCK on the device.
2. After programming the JTAG passwords, you need to enable the JTAGLOCK module (JLM) by programming
bit [3:0] of Z1OTP_JLM_ENABLE with any value other than 0xF. It is recommended to program all four bits
with a value 0x0.
For more details on how to enable and disable the JTAGLOCK feature, refer to the Enhancing Device Security
by Using JTAGLOCK Feature Application Report.
6.2.7 Link Pointer and Zone Select
For each of the two security zones, a dedicated OTP block exists on CPU1 that holds the configuration related to
zone’s security. The following are user programmable configurations:
• ZxOTP_LINKPOINTER1 • ZxOTP_CSMPSWD1
• ZxOTP_LINKPOINTER2 • ZxOTP_CSMPSWD2
• ZxOTP_LINKPOINTER3 • ZxOTP_CSMPSWD3
• Z1OTP_JLM_ENABLE • ZxOTP_GRABSECT1
• ZxOTP_GPREG1 • ZxOTP_GRABSECT2
• ZxOTP_GPREG2 • ZxOTP_GRABSECT3
• ZxOTP_GPREG3 • ZxOTP_GRABRAM1
• ZxOTP_GPREG4 • ZxOTP_GRABRAM2
• ZxOTP_PSWDLOCK • ZxOTP_GRABRAM3
• ZxOTP_CRCLOCK • ZxOTP_EXEONLYSECT1
• Z1OTP_JTAGPSWDH • ZxOTP_EXEONLYSECT2
• Z1OTP_CMACKEY • ZxOTP_EXEONLYRAM1
• ZxOTP_CSMPSWD0 • Z1OTP_JTAGPSWDL

Since OTP cannot be erased, the following configurations are placed in zone select blocks of each zone’s OTP
Flash of both the banks:
• ZxOTP_CSMPSWD0 • ZxOTP_GRABRAM1
• ZxOTP_CSMPSWD1 • ZxOTP_GRABRAM2
• ZxOTP_CSMPSWD2 • ZxOTP_GRABRAM3
• ZxOTP_CSMPSWD3 • ZxOTP_EXEONLYSECT1
• ZxOTP_GRABSECT1 • ZxOTP_EXEONLYSECT2
• ZxOTP_GRABSECT2 • ZxOTP_EXEONLYRAM1
• ZxOTP_GRABSECT3 • Z1OTP_JTAGPSWDL

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The location of the valid zone select block in OTP is decided based on the value of three 14-bit link pointers
(Zx-LINKPOINTERx) programmed in the OTP of each zone. All OTP locations except link pointers and
Z1OTP_JLM_ENABLE locations are protected with ECC. Since the link pointer locations are not protected
with ECC, three link pointers are provided that need to be programmed with the same value. The final value of
the link pointer is resolved in hardware, when a dummy read is done to all the link pointers, by comparing all
the three values (bit-wise voting logic). Since in OTP, a ‘1’ can be flipped by the user to ‘0’ but ‘0’ can not be
flipped to ‘1’ (no erase operation for OTP), the most significant bit position in the resolved link pointer which is
‘0’, defines the valid base address for the zone select block. While generating the final link pointer value, if the bit
pattern is not one of those listed in Figure 6-1, the final link pointer value becomes All_1 (0xFFFF_FFFF), which
selects the Zone-Select-Block1 (also known as the default zone select block).
Selected Zone1 ZSB Zone2 ZSB
Zx-LINKPOINTER
ZSB Address Address

32xxxxxxxxxxxxxxxxxx11111111111111 ZSB1 0x78020 0x78220

32xxxxxxxxxxxxxxxxxx11111111111110 ZSB2 0x78040 0x78240

32xxxxxxxxxxxxxxxxxx11111111111100 ZSB3 0x78060 0x78260

32xxxxxxxxxxxxxxxxxx11111111111000 ZSB4 0x78080 0x78280

32xxxxxxxxxxxxxxxxxx11111111110000 ZSB5 0x780a0 0x782a0

32xxxxxxxxxxxxxxxxxx11111111100000 ZSB6 0x780c0 0x782c0

32xxxxxxxxxxxxxxxxxx11111111000000 ZSB7 0x780e0 0x782e0

32xxxxxxxxxxxxxxxxxx11111110000000 ZSB8 0x78100 0x78300

32xxxxxxxxxxxxxxxxxx11111100000000 ZSB9 0x78120 0x78320

32xxxxxxxxxxxxxxxxxx11111000000000 ZSB10 0x78140 0x78340

32xxxxxxxxxxxxxxxxxx11110000000000 ZSB11 0x78160 0x78360

32xxxxxxxxxxxxxxxxxx11100000000000 ZSB12 0x78180 0x78380

32xxxxxxxxxxxxxxxxxx11000000000000 ZSB13 0x781a0 0x783a0

32xxxxxxxxxxxxxxxxxx10000000000000 ZSB14 0x781c0 0x783c0

32xxxxxxxxxxxxxxxxxx00000000000000 ZSB15 0x781e0 0x783e0

Figure 6-1. Storage of Zone-Select Bits in OTP

Note
Address locations for other security settings that are not part of Zone Select blocks can be
programmed only once; therefore, you can program the blocks towards the end of the development
cycle.

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Zone2 OTP Flash

Zone1 OTP Flash
0x78200 Z2OTP_LINKPOINTER1
0x78000 Z1OTP_LINKPOINTER1
0x78202 Z2OTP_LINKPOINTER2
0x78002 Z1OTP_LINKPOINTER2
0x78204 Z2OTP_LINKPOINTER3
0x78004 Z1OTP_LINKPOINTER3
0x78206 Reserved
0x78006 Z1OTP_JLM_ENABLE
0x78208 Z2OTP_GPREG1
0x78008 Z1OTP_GPREG1 Zone Select Block (ZSB)
0x7820A Z2OTP_GPREG2
0x7800A Z1OTP_GPREG2
Address Offset 0x7820C Z2OTP_GPREG3
32-bit Content
0x7800C Z1OTP_GPREG3 (from ZSB Base)
0x7820E Z2OTP_GPREG4
0x7800E Z1OTP_GPREG4 0x0 ZxOTP_CSMPSWD0
0x78210 Z2OTP_PSWDLOCK
0x78010 Z1OTP_PSWDLOCK 0x2 ZxOTP_CSMPSWD1
0x78212 Z2OTP_CRCLOCK
0x78012 Z1OTP_CRCLOCK 0x4 ZxOTP_CSMPSWD2
0x78214 Reserved
0x78014 Z1OTP_JTAGPSWDH0 0x6 ZxOTP_CSMPSWD3
0x78216 Reserved
0x78016 Z1OTP_JTAGPSWDH1 0x8 ZxOTP_GRABSECT1
0x78218 Reserved
0x78018 Z1OTP_CMACKEY0 0xa ZxOTP_GRABSECT2
0x7821A Reserved
0x7801A Z1OTP_CMACKEY1 0xc ZxOTP_GRABSECT3
0x7821C Reserved
0x7801C Z1OTP_CMACKEY2 0xe ZxOTP_GRABRAM1
0x7821E Reserved
0x7801E Z1OTP_CMACKEY3 0x10 ZxOTP_GRABRAM2
Zone Select Block 1
Zone Select Block 1 0x78220
0x78020 0x12 ZxOTP_GRABRAM3 (32x16 Bits)
(32x16 Bits)
Zone Select Block 2
Zone Select Block 2 0x14 ZxOTP_EXEONLYSECT1 0x78240
0x78040 (32x16 Bits)
(32x16 Bits)
0x16 ZxOTP_EXEONLYSECT2

0x18 ZxOTP_EXEONLYRAM1
Zone Select Block 15
Zone Select Block 15 0x783E0
0x781E0 (32x16 Bits)
(32x16 Bits) 0x1a Reserved

0x1c ZxOTP_JTAGPSWDL0

0x1e ZxOTP_JTAGPSWDL1

Figure 6-2. Location of Zone-Select Block Based on Link-Pointer

CAUTION
USER OTP is ECC protected. You must program the ECC value while programming the security
setting in USER OTP. Failing to program the correct ECC value causes the device to be blocked
permanently and you have to replace the device.

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6.2.8 C Code Example to Get Zone Select Block Addr for Zone1

unsigned long LinkPointer;

unsigned long *Zone1SelBlockPtr;
int Bitpos = 13;
int ZeroFound = 0;
// Read Z1-Linkpointer register of DCSM module.
LinkPointer = *(unsigned long *)0x5F000;
// Bits 31 to 15 as most-sigificant 0 are reserved LinkPointer options
LinkPointer = LinkPointer << 18;
while ((ZeroFound == 0) && (bitpos > -1))
{
if ((LinkPointer & 0x80000000) == 0)
{
ZeroFound = 1;
Zone1SelBlockPtr = (unsigned long *)(0x78000 + ((bitpos + 2)*32));
}
else
{
bitpos--;
LinkPointer = LinkPointer << 1;
}
}
if (ZeroFound == 0)
{
//Default in case there is no zero found.
Zone1SelBlockPtr = (unsigned long *)0x78020;
}

6.3 Flash and OTP Erase/Program

On this device, OTP as well as normal Flash, are secure resources. Each zone has its own dedicated CPU1
OTP, whereas normal Flash sectors can be allocated to any zone based on the value programmed in the
GRABSECTx location in OTP. Each zone has its own 128bit CSM passwords. Read and write accesses are
not allowed to resources assigned to Z1 by code running from memory allocated to Z2 and vice versa. Before
programming any secure Flash sector the user must either unlock the zone to which that particular sector
belongs using PMF or execute the Flash programming code from secure memory which belongs to the same
zone. The same is the case for erasing any secure Flash sector. To program the security settings in CPU1 OTP
Flash, the user must unlock the CSM of the respective zone. Unless the zone is unlocked, security settings in
OTP Flash can not be updated. The OTP content cannot be erased.
A semaphore mechanism is provided to avoid the program/erase conflict between Z1 and Z2. A zone needs
to grab this semaphore to successfully complete the erase/program operation on the secure Flash sectors
allocated to that zone. A semaphore can be grabbed by a zone by writing the appropriate value in the SEM field
of the FLSEM register. For further details of this field, see the register description.
6.4 Secure Copy Code
In some applications, the user may want to copy the code from secure Flash to secure RAM for better
performance. The user cannot do this for EXEONLY Flash sectors because EXEONLY secure memories cannot
be read from anywhere. TI provides specific “Secure Copy Code” library functions for each zone to enable the
user to copy content from EXEONLY secure Flash sectors to EXEONLY RAM blocks. These functions do the
copy-code operation in a highly secure environment and allow a copy to be performed only when the following
conditions are met:
• The secure RAM block and the secure Flash sector belong to the same zone.
• Both the secure RAM block and the secure Flash sector have EXEONLY protection enabled.
For further usage of these library functions, see the device-specific Boot ROM documentation.

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6.5 SecureCRC
Since reads from EXEONLY memories are not allowed, you cannot calculate the CRC on content in EXEONLY
memories using the CRC engine available on this device (for example, VCRC, GCRC) or software. In some
safety-critical applications, the user may have to calculate the CRC even on these memories. To enable this
without compromising on security, TI provides specific “SecureCRC” library functions for each zone. These
functions do the CRC calculation in highly secure environment and allow a CRC calculation to be performed only
when the following conditions are met:
• The source address should be modulo the number of words (based on length_id) for which the CRC needs to
be calculated.
• The destination address should belong to the same zone as the source address.
For further usage of these library functions, see the device-specific Boot ROM documentation.

Note
You must disable all the interrupts before calling the secure functions in ROM. If there is a vector fetch
during secure function execution, the CPU gets reset immediately.

Disclaimer: The Code Security Module (CSM) included on this device was designed to password protect the
data stored in the associated memory and is warranted by Texas Instruments (TI), in accordance with its
standard terms and conditions, to conform to TI's published specifications for the warranty period applicable
for this device. TI DOES NOT, HOWEVER, WARRANT OR REPRESENT THAT THE CSM CANNOT BE
COMPROMISED OR BREACHED OR THAT THE DATA STORED IN THE ASSOCIATED MEMORY CANNOT
BE ACCESSED THROUGH OTHER MEANS. MOREOVER, EXCEPT AS SET FORTH ABOVE, TI MAKES
NO WARRANTIES OR REPRESENTATIONS CONCERNING THE CSM OR OPERATION OF THIS DEVICE,
INCLUDING ANY IMPLIED WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR
PURPOSE. IN NO EVENT SHALL TI BE LIABLE FOR ANY CONSEQUENTIAL, SPECIAL, INDIRECT,
INCIDENTAL, OR PUNITIVE DAMAGES, HOWEVER CAUSED, ARISING IN ANY WAY OUT OF YOUR USE
OF THE CSM OR THIS DEVICE, WHETHER OR NOT TI HAS BEEN ADVISED OF THE POSSIBILITY OF
SUCH DAMAGES. EXCLUDED DAMAGES INCLUDE, BUT ARE NOT LIMITED TO LOSS OF DATA, LOSS OF
GOODWILL, LOSS OF USE OR INTERRUPTION OF BUSINESS OR OTHER ECONOMIC LOSS.

6.6 CSM Impact on Other On-Chip Resources

On this device, some of the memories are not secure. To avoid any potential hacking when the device is
in the default state (post reset), accesses (all types) to all memories (secure as well as non-secure, except
BOOT-ROM and OTP ) are disabled until proper security initialization is done. This means that after reset none
of the memory resources except BOOT_ROM and OTP is accessible to the user.
The following steps are required by CPU1 after reset (any type of reset) to initialize the security on device.
Security Initialization
• Dummy Read to address location of SECDC (0x703F0, TI-reserved register) in TI OTP
• Dummy Read to address location of Z1OTP_LINKPOINTER1 in Z1 OTP
• Dummy Read to address location of Z1OTP_LINKPOINTER2 in Z1 OTP
• Dummy Read to address location of Z1OTP_LINKPOINTER3 in Z1 OTP
• Dummy Read to address location of Z2OTP_LINKPOINTER1 in Z2 OTP
• Dummy Read to address location of Z2OTP_LINKPOINTER2 in Z2 OTP
• Dummy Read to address location of Z2OTP_LINKPOINTER3 in Z2 OTP
• Dummy Read to address location Z1OTP_JLM_ENABLE in Z1 OTP
• Dummy Read to address location of Z1OTP_GPREG1, Z1OTP_GPREG2, Z1OTP_GPREG3,
Z1OTP_GPREG4 in Z1 OTP
• Dummy Read to address location of Z1OTP_PSWDLOCK in Z1 OTP
• Dummy Read to address location of Z1OTP_CRCLOCK in Z1 OTP

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• Dummy Read to address location of Z1OTP_JTAGPSWDH0, Z1OTP_JTAGPSWDH1 in Z1 OTP

• Dummy Read to address location of Z2OTP_GPREG1, Z2OTP_GPREG2, Z2OTP_GPREG3,
Z2OTP_GPREG4 in Z2 OTP
• Dummy Read to address location of Z2OTP_PSWDLOCK in Z2 OTP
• Dummy Read to address location of Z2OTP_CRCLOCK in Z2 OTP
• Read to memory map register of Z1_LINKPOINTER in DCSM module to calculate the address of zone select
block for Z1
• Dummy read to address location of Z1OTP_GRABSECT1, Z1OTP_GRABSECT2, Z1OTP_GRABSECT3 in
Z1 OTP
• Dummy read to address location of Z1OTP_GRABRAM1, Z1OTP_GRABRAM2, Z1OTP_GRABRAM3 in Z1
OTP
• Dummy read to address location of Z1OTP_EXEONLYSECT1, Z1OTP_EXEONLYSECT2 in Z1 OTP
• Dummy read to address location of Z1OTP_EXEONLYRAM1 in Z1 OTP
• Dummy Read to address location of Z1OTP_JTAGPSWDL0, Z1OTP_JTAGPSWDL1 in Z1 OTP
• Read to memory map register of Z2_LINKPOINTER in DCSM module to calculate the address of zone select
block for Z2
• Dummy read to address location of Z2OTP_GRABSECT1, Z2OTP_GRABSECT2, Z2OTP_GRABSECT3 in
Z2 OTP
• Dummy read to address location of Z2OTP_GRABRAM1, Z2OTP_GRABRAM2, Z2OTP_GRABRAM3 in Z2
OTP
• Dummy read to address location of Z2OTP_EXEONLYSECT1, Z2OTP_EXEONLYSECT2 in Z2 OTP
• Dummy read to address location of Z2OTP_EXEONLYRAM1 in Z2 OTP

Note
Security Initialization is done by CPU1 BOOTROM code on all the resets (as part of device
initialization) which assert CPU1 SYSRSn. This will not be part of user application code
The order of initialization matters hence if a memory watch window with the USER OTP address is
opened in the debugger (CCS) the security initialization could occur in an incorrect order, locking the
device down. To avoid this, user should not keep a memory window with USER OTP address opened
in the debugger(CCS) when performing a reset.

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6.7 Incorporating Code Security in User Applications

Code security is typically not required in the development phase of a project. However, security is needed
once a robust code is developed for a zone. Before such a code is programmed in the Flash memory, a CSM
password should be chosen to secure the zone. Once a CSM password is in place for a zone, the zone is
secured (programming a password at the appropriate locations and either performing a device reset or setting
the FORCESEC bit (Zx_CR.31) is the action that secures the device). From that time on, access to debug the
contents of secure memory by any means (via JTAG, code running off external/on-chip memory, and so forth)
requires a valid password. A password is not needed to run the code out of secure memory (such as in a typical
end-user usage); however, access to secure memory contents for debug purposes, requires a password.
6.7.1 Environments That Require Security Unlocking
The following are the typical situations under which unsecuring the zone can be required:
• Code development using debuggers (such as Code Composer Studio). This is the most common
environment during the design phase of a product.
• Flash programming using TI's Flash utilities such as Code Composer Studio On-Chip Flash Programmer
plug-in or the Uniflash tool. Flash programming is common during code development and testing. Once
the user supplies the necessary password, the Flash utilities disable the security logic before attempting to
program the Flash. In custom programming solutions that use the Flash API supplied by TI, unlocking the
CSM can be avoided by executing the Flash programming algorithms from secure memory.
• Custom environment defined by the application
In addition to the above, access to secure memory contents can be required in situations such as:
– Using the on-chip bootloader to load code or data into secure SARAM or to erase and program the Flash.
– Executing code from on-chip unsecure memory and requiring access to secure memory for the lookup
table. This is not a suggested operating condition as supplying the password from external code could
compromise code security.
The unsecuring sequence is identical in all the above situations. This sequence is referred to as the password
match flow (PMF) for simplicity. Figure 6-3 explains the sequence of operation that is required every time the
user attempts to unsecure a particular zone. A code example is listed for clarity.

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6.7.2 CSM Password Match Flow

Password match flow (PMF) is essentially a sequence of four dummy reads from password locations (PWL)
followed by four writes (32-bit writes) to CSMKEY(0/1/2/3) registers. Figure 6-3 shows how PMF helps to
initialize the security logic registers and disable security logic.

START

Zone secure after reset or

runtime

Read Linkpointer and

calculate the address of
ZoneSelectBlock

Dummy Read of CSM PWL of

the Secure Zone which
needed to be unsecure

Write the CSM Password of YES

that Zone into
CSMKEY(0/1/2/3) registers.

NO
Correct
Password ?

YES

Zone Unsecure

Figure 6-3. CSM Password Match Flow (PMF)

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6.7.3 C Code Example to Unsecure C28x Zone1

volatile long int *CSM = (volatile long int *)5F010; //CSM register file volatile
long int *CSMPWL = (volatile long int *)0x78020; //CSM Password location (assuming default Zone
select block)
volatile int tmp;
int I;
// Read the 128-bits of the CSM password locations (PWL)
//
for (I=0;I<4; I++) tmp = *CSMPWL++;
// Write the 128-bit password to the CSMKEY registers
// If this password matches that stored in the
// CSLPWL then the CSM will become unsecure. If it does not
// match, then the zone will remain secure.
// An example password of: // 0x11112222333344445555666677778888 is used.
*CSM++ = 0x22221111; // Register Z1_CSMKEY0 at 0x5F010
*CSM++ = 0x44443333; // Register Z1_CSMKEY1 at 0x5F012
*CSM++ = 0x66665555; // Register Z1_CSMKEY2 at 0x5F014
*CSM++ = 0x88887777; // Register Z1_CSMKEY3 at 0x5F016

6.7.4 C Code Example to Resecure C28x Zone1

volatile int *Z1_CR = 0x5F019; //CSMSCR register

//Set FORCESEC bit
*Z1_CR = 0x8000;

Note
User must use the FORCESEC feature to resecure the zone from same subsystem that has unlocked
the zone. For example, if CM subsystem has unlocked the Zone1 by entering the CSM password in
CSMKEYx ,then only CM subsystem should resecure the Zone1 using FORCESEC feature.

6.7.5 Environments That Require ECSL Unlocking

The following are the typical situations under which unsecuring can be required:
• The user develops some main IP, and then outsources peripheral functions to a subcontractor who must be
able to run the user code during debug and may halt while main IP code is running. If ECSL is not unlocked,
then Code Composer Studio connections will get disconnected, which can be inconvenient for the user. Note
that unlocking ECSL does not enable access to secure code but only avoids disconnection of CCS (JTAG).

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6.7.6 ECSL Password Match Flow

A password match flow (PMF) is essentially a sequence of eight dummy reads from password locations (PWL)
followed by two writes to KEY registers. Figure 6-4 shows how the PMF helps to initialize the security logic
registers and disable security logic.

START

Zone’s ECSL LOCK after

reset or runtime

Read Linkpointer and

calculate the address of
ZoneSelectBlock

Dummy Read of CSM PWL of

the Secure Zone for which
ECSL need to be unlock

Write the ECSL Password of YES

that Zone into CSMKEY(0/1)
registers.

NO
Correct
Password ?

YES

Zone ECSL unlock

Figure 6-4. ECSL Password Match Flow (PMF)

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6.7.7 ECSL Disable Considerations for any Zone

A zone with ECSL enabled should have a predetermined ECSL password stored in the ECSL password
locations in Flash (same as lower 64 bits of CSM passwords). The following are steps to disable the ECSL
for any particular zone:
• Perform a dummy read of CSM password locations of that Zone.
• Write the password into the CSMKEY0/1 registers, corresponding to that Zone.
• If the password is correct, the ECSL gets disabled; otherwise, it stays enabled.
6.7.7.1 C Code Example to Disable ECSL for C28x-Zone1

volatile long int *ECSL = (volatile int *)0x5F010; //ECSL register file
volatile long int *ECSLPWL = (volatile int *)0x78028; //ECSL Password location (assuming default
Zone sel block)
volatile int tmp;
int I;
// Read the 64-bits of the password locations (PWL).
for (I=0;I<2; I++) tmp = *ECSLPWL++;
// Write the 64-bit password to the CSMKEYx registers
// If this password matches that stored in the
// CSMPWL then ECSL will get disable. If it does not
// match, then the zone will remain secure.
// An example password of: // 0x1111222233334444 is used.
*ECSL++ = 0x22221111; // Register Z1_CSMKEY0 at 0x5F010
*ECSL++ = 0x44443333; // Register Z1_CSMKEY1 at 0x5F012

Note
If the CM subsystem is out of reset when ECSL is unlocked by any of the subsystem, one must reset
the CM before trying to lock the ECSL again. Unless CM is reset, ECSL can not be locked again by
entering the incorrect KEY or using the FORCESEC.

6.7.8 Device Unique ID

CPU1 TI OTP contains a 256-bit value that is made up of both random and sequential parts. This value can be
used as a seed for code encryption. The starting address of the value is 0x7020C. The first 192 bits are random,
the next 32 bits are sequential, and the last 32 bits are a checksum value.

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6.8 Software
6.8.1 DCSM Examples
NOTE: These examples are located in the C2000Ware installation at the following location:
C2000Ware_VERSION#/driverlib/DEVICE_GPN/examples/CORE_IF_MULTICORE/dcsm
Cloud access to these examples is available at the following link: dev.ti.com C2000Ware Examples.
6.8.1.1 Empty DCSM Tool Example
FILE: dcsm_security_tool.c This example is an empty project setup for DCSM Tool and Driverlib development.
For guidance refer to: C2000 DCSM Security Tool
6.8.1.2 DCSM Memory Access control by master CPU1 - C28X_CM
FILE: dcsm_ex1_cpu_access_control.c
This example demonstrates how to configure the 1st Zone Select Block in the OTP to allocate CM's C0RAM
to zone 1 & CM's C1RAM to zone 2, later accessed by CM. Zone1 | Zone2 | CM's C0RAM | CM's C1RAM
| In this example, zoning of memories is done by the OTP programming whose values are configured in
dcsm_ex1_f2838x_dcsm_zxotp.asm while the securing functionalities are done through this file. It demonstrates
how to control the access of the memories which would later be accessed by CM. This would even do a dummy
read of the password needed by CM to unsecure the memory. The communication between the 2 CPUs are
done using IPC ( Inter process communication) through a synch function. This enables the CPU Core to wait
until the expected task is completed on the other core.
External Connections
• None.
Watch Variables
• result - Status of Memory Access control by CPU1
• set_error - Count of errors occurring during the execution of the example.
Before running the example, the below configuration is expected to be done through the
dcsm_ex1_f2838x_dcsm_zxotp.asm :
• Allocate CM's C0RAM to zone 1 , C1RAM to zone 2 ZSBx_Z1_GRABRAM2R 0x0AAAAA09
ZSBx_Z2_GRABRAM2R 0x0AAAAA06
• Password of zone 1 is 0xFFFFFFFF4D7FFFFFFFFFFFFFFFFFFFFF
• Password of zone 2 is 0xFFFFFFFF1F7FFFFFFFFFFFFFFFFFFFFF
6.8.1.3 DCSM Memory Access by CPU2 - C28X_DUAL
FILE: dcsm_ex1_cpu2_memory_access.c
This example demonstrates how the access of the memory is affected when the memories are secured by
CPU1. CPU1 allocate CPU2's LS4-LS5 to zone 1 & CPU2's LS6-LS7 to zone 2 using the 1st Zone Select Block.
Zone1 | Zone2 | CPU2's LS4-LS5 | CPU2's LS6-LS7 | It writes some data in the zones and checks after the
CPU1 does a memory locking and matches with the data set . Further, once the CPU2 unlocks the memories, it
matches with the data set written before CPU1 lock. Ideally after locking, zone1 should not be readable(or reads
a 0 value) and zone2 that is not secured matches the written data set. It demonstrates how to lock and and
unlock zone by showing where to put the password and how to check if it is secured or unsecured.
The communication between the 2 CPUs are handled using IPC (Inter process communication) through a synch
function. This enables the CPU Core to wait until the expected task is completed on the other core.
External Connections
• None.
Watch Variables
• result - Status of CPU2's secure memory access

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• set_error, error_not_locked ,error_not_unlocked ,error1 - Count of errors occurring during the execution of
the example.
• Zone1_Locked_Array - Array demonstrating secured memory
• Unsecure_mem_Array - Array demonstrating Unsecured memory
6.8.1.4 DCSM Memory Access control by CPU1 - C28X_DUAL
FILE: dcsm_ex1_cpu1_access_control.c
This example demonstrates how to configure the 1st Zone Select Block in the OTP needed to allocate CPU2's
LS4-LS5 to zone 1 & CPU2's LS6-LS7 to zone 2, later accessed by CPU2. Zone1 | Zone2 | CPU2's LS4-LS5
| CPU2's LS6-LS7 | In this example, zoning of memories is done by the OTP programming whose values are
configured in dcsm_ex1_f2838x_dcsm_zxotp.asm while the securing functionalities are done through this file. It
demonstrates how to control the access of the memories which would later be accessed by CPU2. This would
even do a dummy read of the password needed by CPU2 to unsecure the memory. The communication between
the 2 CPUs are done using IPC ( Inter process communication) through a sync function. This enables the CPU
Core to wait until the expected task is completed on the other core.
External Connections
• None.
Watch Variables
• result - Status of Memory Access control by CPU1
• set_error - Count of errors occurring during the execution of the example.
Before running the example, the below configuration is expected to be done through the
dcsm_ex1_f2838x_dcsm_zxotp.asm :
• Allocate CPU2's LS4-LS5 to zone 1 , LS6-LS7 to zone 2 ZSBx_Z1_GRABRAM3R 0x0000A500
ZSBx_Z2_GRABRAM3R 0x00005A00
• Password of zone 1 is 0xFFFFFFFF4D7FFFFFFFFFFFFFFFFFFFFF
• Password of zone 2 is 0xFFFFFFFF1F7FFFFFFFFFFFFFFFFFFFFF
6.8.1.5 DCSM Memory partitioning Example
FILE: dcsm_ex1_secure_memory_partition.c
This example demonstrates how to configure and use DCSM. It configures the 1st Zone Select Block in the
OTP to change the zone passwords and allocates LS0-LS3 to zone 1 & LS4-LS7 to zone 2. Zone1 | Zone2 |
LS0-LS3 | LS4-LS7 | In this example, zoning of memories is done by the OTP programming whose values are
configured in dcsm_ex1_f2838x_dcsm_zxotp.asm while the securing functionalities are done through this file.
It writes some data in the zones and checks before locking and after locking and matches with the data set .
Ideally after locking zone1, the data set stored in zone1 should not be readable( or reads a 0 value) and
zone2 that is not secured matches the written data set. It demonstrates how to lock and and unlock zones by
showing where to put the password and how to check if it is secured or unsecured.
External Connections
• None.
Watch Variables
• result - Status of Secure memory partitioning done through OTP programming.
• set_error, error_not_locked ,error_not_unlocked ,error1 - Count of errors occurring during the execution of
the example.
• Zone1_Locked_Array - Array demonstrating secured memory
• Unsecure_mem_Array - Array demonstrating Unsecured memory
Before running the example, the below configuration is expected to be done through the
dcsm_ex1_f2838x_dcsm_zxotp.asm :
• Allocate LS0-LS3 to zone 1 , LS4-LS7 to zone 2 ZSBx_Z1_GRABRAM1R 0x000AAA55
ZSBx_Z2_GRABRAM1R 0x000A55AA
• Password of zone 1 is 0xFFFFFFFF4D7FFFFFFFFFFFFFFFFFFFFF

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• Password of zone 2 is 0xFFFFFFFF1F7FFFFFFFFFFFFFFFFFFFFF

DCSM_unlockZone*CSM function should not be called in an actual application, should only be used for once to
program the OTP memory. Ensure flash data cache is disabled before calling this function.
6.8.1.6 DCSM Memory Access by CM - C28X_CM
FILE: dcsm_ex1_cm_memory_access.c
This example demonstrates how the access of the memory is affected when the memories are secured by
CPU1. CPU1 allocate CM's C0RAM to zone 1 & CM's C1RAM to zone 2 using the 1st Zone Select Block. Zone1
| Zone2 | CM's C0RAM | CM's C1RAM | It writes some data in the zones and checks after the CPU1 does a
memory locking and matches with the data set . Further, once the CM unlocks the memories, it matches with
the data set written before CPU1 lock. Ideally after locking, zone1 should not be readable(or reads a 0 value)
and zone2 that is not secured matches the written data set. It demonstrates how to lock and and unlock zone by
showing where to put the password and how to check if it is secured or unsecured.
The communication between the 2 CPUs are handled using IPC (Inter process communication) through a sync
function. This enables the CPU Core to wait until the expected task is completed on the other core.
External Connections
• None.
Watch Variables
• result - Status of CM's secure memory access
• set_error, error_not_locked ,error_not_unlocked ,error1 - Count of errors occurring during the execution of
the example.
• Zone1_Locked_Array - Array demonstrating secured memory
• Unsecure_mem_Array - Array demonstrating Unsecured memory
6.9 DCSM Registers
This section describes the various DCSM Registers.

Note
Except for the SECERRSTAT, SECERRCLR, and SECERRFRC registers, all other registers (non-
OTP space) are mapped on all three subsystems. For the CM subsystem, a x8 offset needs to be
used.

6.9.1 DCSM Base Address Table (C28)

Table 6-4. DCSM Base Address Table (C28)
Bit Field Name Pipeline
DriverLib Name Base Address CPU1 CPU2 DMA CLA
Instance Structure Protected

DcsmZ1Regs DCSM_Z1_REGS DCSM_Z1_BASE 0x0005_F000 YES YES - - YES

DcsmZ2Regs DCSM_Z2_REGS DCSM_Z2_BASE 0x0005_F080 YES YES - - YES
DCSM_COMMON_REG
DcsmCommonRegs DCSMCOMMON_BASE 0x0005_F0C0 YES YES - - YES
S
DcsmZ1OtpRegs DCSM_Z1_OTP DCSM_Z1OTP_BASE 0x0007_8000 YES - - - -
DcsmZ2OtpRegs DCSM_Z2_OTP DCSM_Z2OTP_BASE 0x0007_8200 YES - - - -

6.9.2 CM DCSM Base Address Table (CM)

Table 6-5. CM DCSM Base Address Table (CM)
DriverLib Name Base Address μDMA Access Ethernet DMA Access
DCSM_Z1_BASE 0x4008_5000 - -
DCSM_Z2_BASE 0x4008_5100 - -
DCSMCOMMON_BASE 0x4008_5180 - -

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6.9.3 DCSM_Z1_REGS Registers

Table 6-6 lists the memory-mapped registers for the DCSM_Z1_REGS registers. All register offset addresses not
listed in Table 6-6 should be considered as reserved locations and the register contents should not be modified.
Table 6-6. DCSM_Z1_REGS Registers
Offset Offset Acronym Register Name Write Section
(x8) (x16) Protection
0h 0h Z1_LINKPOINTER Zone 1 Link Pointer Go
4h 2h Z1_OTPSECLOCK Zone 1 OTP Secure Lock Go
8h 4h Z1_JLM_ENABLE Zone 1 JTAGLOCK Enable Register Go
Ch 6h Z1_LINKPOINTERERR Link Pointer Error Go
10h 8h Z1_GPREG1 Zone 1 General Purpose Register-1 Go
14h Ah Z1_GPREG2 Zone 1 General Purpose Register-2 Go
18h Ch Z1_GPREG3 Zone 1 General Purpose Register-3 Go
1Ch Eh Z1_GPREG4 Zone 1 General Purpose Register-4 Go
20h 10h Z1_CSMKEY0 Zone 1 CSM Key 0 Go
24h 12h Z1_CSMKEY1 Zone 1 CSM Key 1 Go
28h 14h Z1_CSMKEY2 Zone 1 CSM Key 2 Go
2Ch 16h Z1_CSMKEY3 Zone 1 CSM Key 3 Go
30h 18h Z1_CR Zone 1 CSM Control Register Go
34h 1Ah Z1_GRABSECT1R Zone 1 Grab Flash Status Register 1 Go
38h 1Ch Z1_GRABSECT2R Zone 1 Grab Flash Status Register 2 Go
3Ch 1Eh Z1_GRABSECT3R Zone 1 Grab Flash Status Register 3 Go
40h 20h Z1_GRABRAM1R Zone 1 Grab RAM Status Register 1 Go
44h 22h Z1_GRABRAM2R Zone 1 Grab RAM Status Register 2 Go
48h 24h Z1_GRABRAM3R Zone 1 Grab RAM Status Register 3 Go
4Ch 26h Z1_EXEONLYSECT1R Zone 1 Execute Only Flash Status Register 1 Go
50h 28h Z1_EXEONLYSECT2R Zone 1 Execute Only Flash Status Register 2 Go
54h 2Ah Z1_EXEONLYRAM1R Zone 1 Execute Only RAM Status Register 1 Go
5Ch 2Eh Z1_JTAGKEY0 JTAG Unlock Key Register 0 Go
60h 30h Z1_JTAGKEY1 JTAG Unlock Key Register 1 Go
64h 32h Z1_JTAGKEY2 JTAG Unlock Key Register 2 Go
68h 34h Z1_JTAGKEY3 JTAG Unlock Key Register 3 Go
6Ch 36h Z1_CMACKEY0 Secure Boot CMAC Key Status Register 0 Go
70h 38h Z1_CMACKEY1 Secure Boot CMAC Key Status Register 1 Go
74h 3Ah Z1_CMACKEY2 Secure Boot CMAC Key Status Register 2 Go
78h 3Ch Z1_CMACKEY3 Secure Boot CMAC Key Status Register 3 Go

Complex bit access types are encoded to fit into small table cells. Table 6-7 shows the codes that are used for
access types in this section.
Table 6-7. DCSM_Z1_REGS Access Type Codes
Access Type Code Description
Read Type
R R Read
R-0 R Read
-0 Returns 0s
Write Type
W W Write

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Table 6-7. DCSM_Z1_REGS Access Type Codes

(continued)
Access Type Code Description
Reset or Default Value
-n Value after reset or the default
value
Register Array Variables
i,j,k,l,m,n When these variables are used in
a register name, an offset, or an
address, they refer to the value of
a register array where the register
is part of a group of repeating
registers. The register groups
form a hierarchical structure and
the array is represented with a
formula.
y When this variable is used in a
register name, an offset, or an
address it refers to the value of
a register array.

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6.9.3.1 Z1_LINKPOINTER Register (Offset (x8) = 0h, Offset (x16) = 0h) [Reset = FFFFC000h]
Z1_LINKPOINTER is shown in Figure 6-5 and described in Table 6-8.
Return to the Summary Table.
Zone 1 Link Pointer
Figure 6-5. Z1_LINKPOINTER Register
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RESERVED LINKPOINTER
R-0h R-0h

Table 6-8. Z1_LINKPOINTER Register Field Descriptions

Bit Field Type Reset Description
31-14 RESERVED R 0h Reserved
13-0 LINKPOINTER R 0h This is resolved Link-Pointer value which is generated by looking at
the three physical Link-Pointer values loaded from OTP
Reset type: SYSRSn

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6.9.3.2 Z1_OTPSECLOCK Register (Offset (x8) = 4h, Offset (x16) = 2h) [Reset = 1h]
Z1_OTPSECLOCK is shown in Figure 6-6 and described in Table 6-9.
Return to the Summary Table.
Zone 1 OTP Secure Lock
Figure 6-6. Z1_OTPSECLOCK Register
31 30 29 28 27 26 25 24
RESERVED
R-0h

23 22 21 20 19 18 17 16
RESERVED
R-0h

15 14 13 12 11 10 9 8
RESERVED CRCLOCK
R-0h R-0h

7 6 5 4 3 2 1 0
PSWDLOCK RESERVED JTAGLOCK
R-0h R-0h R-1h

Table 6-9. Z1_OTPSECLOCK Register Field Descriptions

Bit Field Type Reset Description
31-16 RESERVED R 0h Reserved
15-12 RESERVED R 0h Reserved
11-8 CRCLOCK R 0h Value in this field gets loaded from Z1_CRCLOCK[3:0] when a read
is issued to address location of Z1_CRCLOCK in OTP.
1111 : VCU has ability to calculate CRC on secure memories.
Other Value : VCU doesn't have ability to calculate CRC on secure
memories.
Reset type: XRSn
7-4 PSWDLOCK R 0h Value in this field gets loaded from Z1_PSWDLOCK[3:0] when a
read is issued to address location of Z1_PSWDLOCK in OTP.
1111 : CSM password locations in OTP are not protected and can be
read from debugger as well as code running from anywhere.
Other Value : CSM password locations in OTP are protected and
can't be read without unlocking CSM of that zone.
Reset type: XRSn
3-1 RESERVED R 0h Reserved
0 JTAGLOCK R 1h Reflects the state of the JTAGLOCK feature.
0 : JTAG is not locked
1 : JTAG is locked
Reset type: PORESETn

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6.9.3.3 Z1_JLM_ENABLE Register (Offset (x8) = 8h, Offset (x16) = 4h) [Reset = Fh]
Z1_JLM_ENABLE is shown in Figure 6-7 and described in Table 6-10.
Return to the Summary Table.
Zone 1 JTAGLOCK Enable Register
Figure 6-7. Z1_JLM_ENABLE Register
31 30 29 28 27 26 25 24
RESERVED
R-0h

23 22 21 20 19 18 17 16
RESERVED
R-0h

15 14 13 12 11 10 9 8
RESERVED
R-0h

7 6 5 4 3 2 1 0
RESERVED Z1_JLM_ENABLE
R-0h R-Fh

Table 6-10. Z1_JLM_ENABLE Register Field Descriptions

Bit Field Type Reset Description
31-4 RESERVED R 0h Reserved
3-0 Z1_JLM_ENABLE R Fh Zone1 JLM_ENABLE register. The value in this field gets
loaded from Z1OTP_JLM_ENABLE[3:0] when a read is issued
to address location of Z1OTP_JLM_ENABLE in OTP. If
Z1OTP_JLM_ENABLE[31:0] is equal to all ones during the load,
the JTAGLOCK is not bypassed (is enabled). If the value of
Z1OTP_JLM_ENABLE[31:0] is not all ones during the load, the
JTAGLOCK is governed as follows by the Z1_JLM_ENABLE bits:
1111 : JTAG/Emulation access is allowed (JTAGLOCK is not
enabled)
Other values: JTAGLOCK is governed by the
JTAGKEY==JTAGPSWD match condition
Reset type: PORESETn

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6.9.3.4 Z1_LINKPOINTERERR Register (Offset (x8) = Ch, Offset (x16) = 6h) [Reset = 0h]
Z1_LINKPOINTERERR is shown in Figure 6-8 and described in Table 6-11.
Return to the Summary Table.
Link Pointer Error
Figure 6-8. Z1_LINKPOINTERERR Register
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
RESERVED
R-0h

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RESERVED Z1_LINKPOINTERERR
R-0h R-0h

Table 6-11. Z1_LINKPOINTERERR Register Field Descriptions

Bit Field Type Reset Description
31-14 RESERVED R 0h Reserved
13-0 Z1_LINKPOINTERERR R 0h These bits indicate errors during formation of the resolved Link-
Pointer value after the three physical Link-Pointer values loaded of
OTP in flash.
0 : No Error.
Other : Error on bit positions which is set to 1.
Reset type: SYSRSn

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6.9.3.5 Z1_GPREG1 Register (Offset (x8) = 10h, Offset (x16) = 8h) [Reset = 0h]
Z1_GPREG1 is shown in Figure 6-9 and described in Table 6-12.
Return to the Summary Table.
Zone 1 General Purpose Register-1
Figure 6-9. Z1_GPREG1 Register
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
GPREG1
R-0h

Table 6-12. Z1_GPREG1 Register Field Descriptions

Bit Field Type Reset Description
31-0 GPREG1 R 0h This field gets loaded with the contents of Z1OTP_GPREG1
locations in Zone-1-USER-OTP when a dummy read is issued to
that address. Users can use this register to load any general purpose
non-voliate content from USER-OTP of Zone-1
Reset type: SYSRSn

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6.9.3.6 Z1_GPREG2 Register (Offset (x8) = 14h, Offset (x16) = Ah) [Reset = 0h]
Z1_GPREG2 is shown in Figure 6-10 and described in Table 6-13.
Return to the Summary Table.
Zone 1 General Purpose Register-2
Figure 6-10. Z1_GPREG2 Register
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
GPREG2
R-0h

Table 6-13. Z1_GPREG2 Register Field Descriptions

Bit Field Type Reset Description
31-0 GPREG2 R 0h This field gets loaded with the contents of Z1OTP_GPREG2
locations in Zone-1-USER-OTP when a dummy read is issued to
that address. Users can use this register to load any general purpose
non-voliate content from USER-OTP of Zone-1
Reset type: SYSRSn

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6.9.3.7 Z1_GPREG3 Register (Offset (x8) = 18h, Offset (x16) = Ch) [Reset = 0h]
Z1_GPREG3 is shown in Figure 6-11 and described in Table 6-14.
Return to the Summary Table.
Zone 1 General Purpose Register-3
Figure 6-11. Z1_GPREG3 Register
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
GPREG3
R-0h

Table 6-14. Z1_GPREG3 Register Field Descriptions

Bit Field Type Reset Description
31-0 GPREG3 R 0h This field gets loaded with the contents of Z1OTP_GPREG3
locations in Zone-1-USER-OTP when a dummy read is issued to
that address. Users can use this register to load any general purpose
non-voliate content from USER-OTP of Zone-1
Reset type: SYSRSn

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6.9.3.8 Z1_GPREG4 Register (Offset (x8) = 1Ch, Offset (x16) = Eh) [Reset = 0h]
Z1_GPREG4 is shown in Figure 6-12 and described in Table 6-15.
Return to the Summary Table.
Zone 1 General Purpose Register-4
Figure 6-12. Z1_GPREG4 Register
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
GPREG4
R-0h

Table 6-15. Z1_GPREG4 Register Field Descriptions

Bit Field Type Reset Description
31-0 GPREG4 R 0h This field gets loaded with the contents of Z1OTP_GPREG4
locations in Zone-1-USER-OTP when a dummy read is issued to
that address. Users can use this register to load any general purpose
non-voliate content from USER-OTP of Zone-1
Reset type: SYSRSn

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6.9.3.9 Z1_CSMKEY0 Register (Offset (x8) = 20h, Offset (x16) = 10h) [Reset = 0h]
Z1_CSMKEY0 is shown in Figure 6-13 and described in Table 6-16.
Return to the Summary Table.
Zone 1 CSM Key 0
Figure 6-13. Z1_CSMKEY0 Register
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Z1_CSMKEY0
R/W-0h

Table 6-16. Z1_CSMKEY0 Register Field Descriptions

Bit Field Type Reset Description
31-0 Z1_CSMKEY0 R/W 0h To unlock Zone1, user needs to write this regsiter with exact value
as Z1_CSMPSWD0, programmed in OTP (zone gets unlock only if
128 bit password in OTP match with value written in four CSMKEY
registers.)
Reset type: SYSRSn

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6.9.3.10 Z1_CSMKEY1 Register (Offset (x8) = 24h, Offset (x16) = 12h) [Reset = 0h]
Z1_CSMKEY1 is shown in Figure 6-14 and described in Table 6-17.
Return to the Summary Table.
Zone 1 CSM Key 1
Figure 6-14. Z1_CSMKEY1 Register
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Z1_CSMKEY1
R/W-0h

Table 6-17. Z1_CSMKEY1 Register Field Descriptions

Bit Field Type Reset Description
31-0 Z1_CSMKEY1 R/W 0h To unlock Zone1, user needs to write this regsiter with exact value
as Z1_CSMPSWD1, programmed in OTP (zone gets unlock only if
128 bit password in OTP match with value written in four CSMKEY
registers.)
Reset type: SYSRSn

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6.9.3.11 Z1_CSMKEY2 Register (Offset (x8) = 28h, Offset (x16) = 14h) [Reset = 0h]
Z1_CSMKEY2 is shown in Figure 6-15 and described in Table 6-18.
Return to the Summary Table.
Zone 1 CSM Key 2
Figure 6-15. Z1_CSMKEY2 Register
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Z1_CSMKEY2
R/W-0h

Table 6-18. Z1_CSMKEY2 Register Field Descriptions

Bit Field Type Reset Description
31-0 Z1_CSMKEY2 R/W 0h To unlock Zone1, user needs to write this regsiter with exact value
as Z1_CSMPSWD2, programmed in OTP (zone gets unlock only if
128 bit password in OTP match with value written in four CSMKEY
registers.)
Reset type: SYSRSn

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6.9.3.12 Z1_CSMKEY3 Register (Offset (x8) = 2Ch, Offset (x16) = 16h) [Reset = 0h]
Z1_CSMKEY3 is shown in Figure 6-16 and described in Table 6-19.
Return to the Summary Table.
Zone 1 CSM Key 3
Figure 6-16. Z1_CSMKEY3 Register
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Z1_CSMKEY3
R/W-0h

Table 6-19. Z1_CSMKEY3 Register Field Descriptions

Bit Field Type Reset Description
31-0 Z1_CSMKEY3 R/W 0h To unlock Zone1, user needs to write this regsiter with exact value
as Z1_CSMPSWD3, programmed in OTP (zone gets unlock only if
128 bit password in OTP match with value written in four CSMKEY
registers.)
Reset type: SYSRSn

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6.9.3.13 Z1_CR Register (Offset (x8) = 30h, Offset (x16) = 18h) [Reset = 00080000h]
Z1_CR is shown in Figure 6-17 and described in Table 6-20.
Return to the Summary Table.
Zone 1 CSM Control Register
Figure 6-17. Z1_CR Register
31 30 29 28 27 26 25 24
FORCESEC RESERVED
R-0/W-0h R-0h

23 22 21 20 19 18 17 16
RESERVED ARMED UNSECURE ALLONE ALLZERO RESERVED
R-0h R-0h R-0h R-0h R-1h R-0h

15 14 13 12 11 10 9 8
RESERVED
R-0h

7 6 5 4 3 2 1 0
RESERVED RESERVED RESERVED RESERVED RESERVED
R-0h R-0h R-0h R-0h R-0h

Table 6-20. Z1_CR Register Field Descriptions

Bit Field Type Reset Description
31 FORCESEC R-0/W 0h A write '1' to this fields resets the state of zone. If zone is unlocked,
it'll lock(secure) the zone and also resets all the bits in this register.
Reset type: SYSRSn
30-24 RESERVED R 0h Reserved
23 RESERVED R 0h Reserved
22 ARMED R 0h 0 : Dummy read to CSM Password locations in OTP hasn't been
performed.
1 : Dummy read to CSM Password locations in OTP has been
performed.
Reset type: SYSRSn
21 UNSECURE R 0h Indiacates the state of Zone.
0 : Zone is in lock(secure) state.
1 : Zone is in unlock(unsecure) state.
Reset type: SYSRSn
20 ALLONE R 0h Indicates the state of CSM passwords.
0 : Zone CSM Passwords are not all ones.
1 : Zone CSM Passwords are all ones.
Reset type: SYSRSn
19 ALLZERO R 1h Indicates the state of CSM passowrds.
0 : CSM Passwords are not all zeros.
1 : CSM Passwords are all zero and device is permanently locked.
Reset type: SYSRSn
18-16 RESERVED R 0h Reserved
15-4 RESERVED R 0h Reserved
3 RESERVED R 0h Reserved
2 RESERVED R 0h Reserved
1 RESERVED R 0h Reserved
0 RESERVED R 0h Reserved

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6.9.3.14 Z1_GRABSECT1R Register (Offset (x8) = 34h, Offset (x16) = 1Ah) [Reset = 0h]
Z1_GRABSECT1R is shown in Figure 6-18 and described in Table 6-21.
Return to the Summary Table.
Zone 1 Grab Flash Status Register 1
Figure 6-18. Z1_GRABSECT1R Register
31 30 29 28 27 26 25 24
RESERVED GRAB_SECT13 GRAB_SECT12
R-0h R-0h R-0h

23 22 21 20 19 18 17 16
GRAB_SECT11 GRAB_SECT10 GRAB_SECT9 GRAB_SECT8
R-0h R-0h R-0h R-0h

15 14 13 12 11 10 9 8
GRAB_SECT7 GRAB_SECT6 GRAB_SECT5 GRAB_SECT4
R-0h R-0h R-0h R-0h

7 6 5 4 3 2 1 0
GRAB_SECT3 GRAB_SECT2 GRAB_SECT1 GRAB_SECT0
R-0h R-0h R-0h R-0h

Table 6-21. Z1_GRABSECT1R Register Field Descriptions

Bit Field Type Reset Description
31-28 RESERVED R 0h Reserved
27-26 GRAB_SECT13 R 0h Value in this field gets loaded from Z1_GRABSECT1[27:26] when a
read is issued to address location of Z1_GRABSECT1 in OTP.
00 : Invalid. CPU1 Flash Sector 13 is inaccessible.
01 : Request to allocate CPU1 Flash Sector 13 to Zone1.
10 : No request for CPU1 Flash Sector 13
11 : No request for CPU1 Flash Sector 13 when this zone is
UNLOCKED. Else CPU1 Flash Sector 13 is inaccessible if this zone
is LOCKED.
Reset type: SYSRSn
25-24 GRAB_SECT12 R 0h Value in this field gets loaded from Z1_GRABSECT1[25:24] when a
read is issued to address location of Z1_GRABSECT1 in OTP.
00 : Invalid. CPU1 Flash Sector 12 is inaccessible.
01 : Request to allocate CPU1 Flash Sector 12 to Zone1.
10 : No request for CPU1 Flash Sector 12
11 : No request for CPU1 Flash Sector 12 when this zone is
UNLOCKED. Else CPU1 Flash Sector 12 is inaccessible if this zone
is LOCKED.
Reset type: SYSRSn
23-22 GRAB_SECT11 R 0h Value in this field gets loaded from Z1_GRABSECT1[23:22] when a
read is issued to address location of Z1_GRABSECT1 in OTP.
00 : Invalid. CPU1 Flash Sector 11 is inaccessible.
01 : Request to allocate CPU1 Flash Sector 11 to Zone1.
10 : No request for CPU1 Flash Sector 11
11 : No request for CPU1 Flash Sector 11 when this zone is
UNLOCKED. Else CPU1 Flash Sector 11 is inaccessible if this zone
is LOCKED.
Reset type: SYSRSn

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Table 6-21. Z1_GRABSECT1R Register Field Descriptions (continued)

Bit Field Type Reset Description
21-20 GRAB_SECT10 R 0h Value in this field gets loaded from Z1_GRABSECT1[21:20] when a
read is issued to address location of Z1_GRABSECT1 in OTP.
00 : Invalid. CPU1 Flash Sector 10 is inaccessible.
01 : Request to allocate CPU1 Flash Sector 10 to Zone1.
10 : No request for CPU1 Flash Sector 10
11 : No request for CPU1 Flash Sector 10 when this zone is
UNLOCKED. Else CPU1 Flash Sector 10 is inaccessible if this zone
is LOCKED.
Reset type: SYSRSn
19-18 GRAB_SECT9 R 0h Value in this field gets loaded from Z1_GRABSECT1[19:18] when a
read is issued to address location of Z1_GRABSECT1 in OTP.
00 : Invalid. CPU1 Flash Sector 9 is inaccessible.
01 : Request to allocate CPU1 Flash Sector 9 to Zone1.
10 : No request for CPU1 Flash Sector 9
11 : No request for CPU1 Flash Sector 9 when this zone is
UNLOCKED. Else CPU1 Flash Sector 9 is inaccessible if this zone is
LOCKED.
Reset type: SYSRSn
17-16 GRAB_SECT8 R 0h Value in this field gets loaded from Z1_GRABSECT1[17:16] when a
read is issued to address location of Z1_GRABSECT1 in OTP.
00 : Invalid. CPU1 Flash Sector 8 is inaccessible.
01 : Request to allocate CPU1 Flash Sector 8 to Zone1.
10 : No request for CPU1 Flash Sector 8
11 : No request for CPU1 Flash Sector 8 when this zone is
UNLOCKED. Else CPU1 Flash Sector 8 is inaccessible if this zone is
LOCKED.
Reset type: SYSRSn
15-14 GRAB_SECT7 R 0h Value in this field gets loaded from Z1_GRABSECT1[15:14] when a
read is issued to address location of Z1_GRABSECT1 in OTP.
00 : Invalid. CPU1 Flash Sector 7 is inaccessible.
01 : Request to allocate CPU1 Flash Sector 7 to Zone1.
10 : No request for CPU1 Flash Sector 7
11 : No request for CPU1 Flash Sector 7 when this zone is
UNLOCKED. Else CPU1 Flash Sector 7 is inaccessible if this zone is
LOCKED.
Reset type: SYSRSn
13-12 GRAB_SECT6 R 0h Value in this field gets loaded from Z1_GRABSECT1[13:12] when a
read is issued to address location of Z1_GRABSECT1 in OTP.
00 : Invalid. CPU1 Flash Sector 6 is inaccessible.
01 : Request to allocate CPU1 Flash Sector 6 to Zone1.
10 : No request for CPU1 Flash Sector 6
11 : No request for CPU1 Flash Sector 6 when this zone is
UNLOCKED. Else CPU1 Flash Sector 6 is inaccessible if this zone is
LOCKED.
Reset type: SYSRSn
11-10 GRAB_SECT5 R 0h Value in this field gets loaded from Z1_GRABSECT1[11:10] when a
read is issued to address location of Z1_GRABSECT1 in OTP.
00 : Invalid. CPU1 Flash Sector 5 is inaccessible.
01 : Request to allocate CPU1 Flash Sector 5 to Zone1.
10 : No request for CPU1 Flash Sector 5
11 : No request for CPU1 Flash Sector 5 when this zone is
UNLOCKED. Else CPU1 Flash Sector 5 is inaccessible if this zone is
LOCKED.
Reset type: SYSRSn
9-8 GRAB_SECT4 R 0h Value in this field gets loaded from Z1_GRABSECT1[9:8] when a
read is issued to address location of Z1_GRABSECT1 in OTP.
00 : Invalid. CPU1 Flash Sector 4 is inaccessible.
01 : Request to allocate CPU1 Flash Sector 4 to Zone1.
10 : No request for CPU1 Flash Sector 4
11 : No request for CPU1 Flash Sector 4 when this zone is
UNLOCKED. Else CPU1 Flash Sector 4 is inaccessible if this zone is
LOCKED.
Reset type: SYSRSn

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Table 6-21. Z1_GRABSECT1R Register Field Descriptions (continued)

Bit Field Type Reset Description
7-6 GRAB_SECT3 R 0h Value in this field gets loaded from Z1_GRABSECT1[7:6] when a
read is issued to address location of Z1_GRABSECT1 in OTP.
00 : Invalid. CPU1 Flash Sector 3 is inaccessible.
01 : Request to allocate CPU1 Flash Sector 3 to Zone1.
10 : No request for CPU1 Flash Sector 3
11 : No request for CPU1 Flash Sector 3 when this zone is
UNLOCKED. Else CPU1 Flash Sector 3 is inaccessible if this zone is
LOCKED.
Reset type: SYSRSn
5-4 GRAB_SECT2 R 0h Value in this field gets loaded from Z1_GRABSECT1[5:4] when a
read is issued to address location of Z1_GRABSECT1 in OTP.
00 : Invalid. CPU1 Flash Sector 2 is inaccessible.
01 : Request to allocate CPU1 Flash Sector 2 to Zone1.
10 : No request for CPU1 Flash Sector 2
11 : No request for CPU1 Flash Sector 2 when this zone is
UNLOCKED. Else CPU1 Flash Sector 2 is inaccessible if this zone is
LOCKED.
Reset type: SYSRSn
3-2 GRAB_SECT1 R 0h Value in this field gets loaded from Z1_GRABSECT1[3:2] when a
read is issued to address location of Z1_GRABSECT1 in OTP.
00 : Invalid. CPU1 Flash Sector 1 is inaccessible.
01 : Request to allocate CPU1 Flash Sector 1 to Zone1.
10 : No request for CPU1 Flash Sector 1
11 : No request for CPU1 Flash Sector 1 when this zone is
UNLOCKED. Else CPU1 Flash Sector 1 is inaccessible if this zone is
LOCKED.
Reset type: SYSRSn
1-0 GRAB_SECT0 R 0h Value in this field gets loaded from Z1_GRABSECT1[1:0] when a
read is issued to address location of Z1_GRABSECT1 in OTP.
00 : Invalid. CPU1 Flash Sector 0 is inaccessible.
01 : Request to allocate CPU1 Flash Sector 0 to Zone1.
10 : No request for CPU1 Flash Sector 0
11 : No request for CPU1 Flash Sector 0 when this zone is
UNLOCKED. Else CPU1 Flash Sector 0 is inaccessible if this zone is
LOCKED.
Reset type: SYSRSn

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6.9.3.15 Z1_GRABSECT2R Register (Offset (x8) = 38h, Offset (x16) = 1Ch) [Reset = 0h]
Z1_GRABSECT2R is shown in Figure 6-19 and described in Table 6-22.
Return to the Summary Table.
Zone 1 Grab Flash Status Register 2
Figure 6-19. Z1_GRABSECT2R Register
31 30 29 28 27 26 25 24
RESERVED GRAB_SECT13 GRAB_SECT12
R-0h R-0h R-0h

23 22 21 20 19 18 17 16
GRAB_SECT11 GRAB_SECT10 GRAB_SECT9 GRAB_SECT8
R-0h R-0h R-0h R-0h

15 14 13 12 11 10 9 8
GRAB_SECT7 GRAB_SECT6 GRAB_SECT5 GRAB_SECT4
R-0h R-0h R-0h R-0h

7 6 5 4 3 2 1 0
GRAB_SECT3 GRAB_SECT2 GRAB_SECT1 GRAB_SECT0
R-0h R-0h R-0h R-0h

Table 6-22. Z1_GRABSECT2R Register Field Descriptions

Bit Field Type Reset Description
31-28 RESERVED R 0h Reserved
27-26 GRAB_SECT13 R 0h Value in this field gets loaded from Z1_GRABSECT2[27:26] when a
read is issued to address location of Z1_GRABSECT2 in OTP.
00 : Invalid. CM Flash Sector 13 is inaccessible.
01 : Request to allocate CM Flash Sector 13 to Zone1.
10 : No request for CM Flash Sector 13
11 : No request for CM Flash Sector 13 when this zone is
UNLOCKED. Else CM Flash Sector 13 is inaccessible if this zone
is LOCKED.
Reset type: SYSRSn
25-24 GRAB_SECT12 R 0h Value in this field gets loaded from Z1_GRABSECT2[25:24] when a
read is issued to address location of Z1_GRABSECT2 in OTP.
00 : Invalid. CM Flash Sector 12 is inaccessible.
01 : Request to allocate CM Flash Sector 12 to Zone1.
10 : No request for CM Flash Sector 12
11 : No request for CM Flash Sector 12 when this zone is
UNLOCKED. Else CM Flash Sector 12 is inaccessible if this zone
is LOCKED.
Reset type: SYSRSn
23-22 GRAB_SECT11 R 0h Value in this field gets loaded from Z1_GRABSECT2[23:22] when a
read is issued to address location of Z1_GRABSECT2 in OTP.
00 : Invalid. CM Flash Sector 11 is inaccessible.
01 : Request to allocate CM Flash Sector 11 to Zone1.
10 : No request for CM Flash Sector 11
11 : No request for CM Flash Sector 11 when this zone is
UNLOCKED. Else CM Flash Sector 11 is inaccessible if this zone
is LOCKED.
Reset type: SYSRSn

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Table 6-22. Z1_GRABSECT2R Register Field Descriptions (continued)

Bit Field Type Reset Description
21-20 GRAB_SECT10 R 0h Value in this field gets loaded from Z1_GRABSECT2[21:20] when a
read is issued to address location of Z1_GRABSECT2 in OTP.
00 : Invalid. CM Flash Sector 10 is inaccessible.
01 : Request to allocate CM Flash Sector 10 to Zone1.
10 : No request for CM Flash Sector 10
11 : No request for CM Flash Sector 10 when this zone is
UNLOCKED. Else CM Flash Sector 10 is inaccessible if this zone
is LOCKED.
Reset type: SYSRSn
19-18 GRAB_SECT9 R 0h Value in this field gets loaded from Z1_GRABSECT2[19:18] when a
read is issued to address location of Z1_GRABSECT2 in OTP.
00 : Invalid. CM Flash Sector 9 is inaccessible.
01 : Request to allocate CM Flash Sector 9 to Zone1.
10 : No request for CM Flash Sector 9
11 : No request for CM Flash Sector 9 when this zone is
UNLOCKED. Else CM Flash Sector 9 is inaccessible if this zone
is LOCKED.
Reset type: SYSRSn
17-16 GRAB_SECT8 R 0h Value in this field gets loaded from Z1_GRABSECT2[17:16] when a
read is issued to address location of Z1_GRABSECT2 in OTP.
00 : Invalid. CM Flash Sector 8 is inaccessible.
01 : Request to allocate CM Flash Sector 8 to Zone1.
10 : No request for CM Flash Sector 8
11 : No request for CM Flash Sector 8 when this zone is
UNLOCKED. Else CM Flash Sector 8 is inaccessible if this zone
is LOCKED.
Reset type: SYSRSn
15-14 GRAB_SECT7 R 0h Value in this field gets loaded from Z1_GRABSECT2[15:14] when a
read is issued to address location of Z1_GRABSECT2 in OTP.
00 : Invalid. CM Flash Sector 7 is inaccessible.
01 : Request to allocate CM Flash Sector 7 to Zone1.
10 : No request for CM Flash Sector 7
11 : No request for CM Flash Sector 7 when this zone is
UNLOCKED. Else CM Flash Sector 7 is inaccessible if this zone
is LOCKED.
Reset type: SYSRSn
13-12 GRAB_SECT6 R 0h Value in this field gets loaded from Z1_GRABSECT2[13:12] when a
read is issued to address location of Z1_GRABSECT2 in OTP.
00 : Invalid. CM Flash Sector 6 is inaccessible.
01 : Request to allocate CM Flash Sector 6 to Zone1.
10 : No request for CM Flash Sector 6
11 : No request for CM Flash Sector 6 when this zone is
UNLOCKED. Else CM Flash Sector 6 is inaccessible if this zone
is LOCKED.
Reset type: SYSRSn
11-10 GRAB_SECT5 R 0h Value in this field gets loaded from Z1_GRABSECT2[11:10] when a
read is issued to address location of Z1_GRABSECT2 in OTP.
00 : Invalid. CM Flash Sector 5 is inaccessible.
01 : Request to allocate CM Flash Sector 5 to Zone1.
10 : No request for CM Flash Sector 5
11 : No request for CM Flash Sector 5 when this zone is
UNLOCKED. Else CM Flash Sector 5 is inaccessible if this zone
is LOCKED.
Reset type: SYSRSn
9-8 GRAB_SECT4 R 0h Value in this field gets loaded from Z1_GRABSECT2[9:8] when a
read is issued to address location of Z1_GRABSECT2 in OTP.
00 : Invalid. CM Flash Sector 4 is inaccessible.
01 : Request to allocate CM Flash Sector 4 to Zone1.
10 : No request for CM Flash Sector 4
11 : No request for CM Flash Sector 4 when this zone is
UNLOCKED. Else CM Flash Sector 4 is inaccessible if this zone
is LOCKED.
Reset type: SYSRSn

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Table 6-22. Z1_GRABSECT2R Register Field Descriptions (continued)

Bit Field Type Reset Description
7-6 GRAB_SECT3 R 0h Value in this field gets loaded from Z1_GRABSECT2[7:6] when a
read is issued to address location of Z1_GRABSECT2 in OTP.
00 : Invalid. CM Flash Sector 3 is inaccessible.
01 : Request to allocate CM Flash Sector 3 to Zone1.
10 : No request for CM Flash Sector 3
11 : No request for CM Flash Sector 3 when this zone is
UNLOCKED. Else CM Flash Sector 3 is inaccessible if this zone
is LOCKED.
Reset type: SYSRSn
5-4 GRAB_SECT2 R 0h Value in this field gets loaded from Z1_GRABSECT2[5:4] when a
read is issued to address location of Z1_GRABSECT2 in OTP.
00 : Invalid. CM Flash Sector 2 is inaccessible.
01 : Request to allocate CM Flash Sector 2 to Zone1.
10 : No request for CM Flash Sector 2
11 : No request for CM Flash Sector 2 when this zone is
UNLOCKED. Else CM Flash Sector 2 is inaccessible if this zone
is LOCKED.
Reset type: SYSRSn
3-2 GRAB_SECT1 R 0h Value in this field gets loaded from Z1_GRABSECT2[3:2] when a
read is issued to address location of Z1_GRABSECT2 in OTP.
00 : Invalid. CM Flash Sector 1 is inaccessible.
01 : Request to allocate CM Flash Sector 1 to Zone1.
10 : No request for CM Flash Sector 1
11 : No request for CM Flash Sector 1 when this zone is
UNLOCKED. Else CM Flash Sector 1 is inaccessible if this zone
is LOCKED.
Reset type: SYSRSn
1-0 GRAB_SECT0 R 0h Value in this field gets loaded from Z1_GRABSECT2[1:0] when a
read is issued to address location of Z1_GRABSECT2 in OTP.
00 : Invalid. CM Flash Sector 0 is inaccessible.
01 : Request to allocate CM Flash Sector 0 to Zone1.
10 : No request for CM Flash Sector 0
11 : No request for CM Flash Sector 0 when this zone is
UNLOCKED. Else CM Flash Sector 0 is inaccessible if this zone
is LOCKED.
Reset type: SYSRSn

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6.9.3.16 Z1_GRABSECT3R Register (Offset (x8) = 3Ch, Offset (x16) = 1Eh) [Reset = 0h]
Z1_GRABSECT3R is shown in Figure 6-20 and described in Table 6-23.
Return to the Summary Table.
Zone 1 Grab Flash Status Register 3
Figure 6-20. Z1_GRABSECT3R Register
31 30 29 28 27 26 25 24
RESERVED GRAB_SECT13 GRAB_SECT12
R-0h R-0h R-0h

23 22 21 20 19 18 17 16
GRAB_SECT11 GRAB_SECT10 GRAB_SECT9 GRAB_SECT8
R-0h R-0h R-0h R-0h

15 14 13 12 11 10 9 8
GRAB_SECT7 GRAB_SECT6 GRAB_SECT5 GRAB_SECT4
R-0h R-0h R-0h R-0h

7 6 5 4 3 2 1 0
GRAB_SECT3 GRAB_SECT2 GRAB_SECT1 GRAB_SECT0
R-0h R-0h R-0h R-0h

Table 6-23. Z1_GRABSECT3R Register Field Descriptions

Bit Field Type Reset Description
31-28 RESERVED R 0h Reserved
27-26 GRAB_SECT13 R 0h Value in this field gets loaded from Z1_GRABSECT3[27:26] when a
read is issued to address location of Z1_GRABSECT3 in OTP.
00 : Invalid. CPU2 Flash Sector 13 is inaccessible.
01 : Request to allocate CPU2 Flash Sector 13 to Zone1.
10 : No request for CPU2 Flash Sector 13
11 : No request for CPU2 Flash Sector 13 when this zone is
UNLOCKED. Else CPU2 Flash Sector 13 is inaccessible if this zone
is LOCKED.
Reset type: SYSRSn
25-24 GRAB_SECT12 R 0h Value in this field gets loaded from Z1_GRABSECT3[25:24] when a
read is issued to address location of Z1_GRABSECT3 in OTP.
00 : Invalid. CPU2 Flash Sector 12 is inaccessible.
01 : Request to allocate CPU2 Flash Sector 12 to Zone1.
10 : No request for CPU2 Flash Sector 12
11 : No request for CPU2 Flash Sector 12 when this zone is
UNLOCKED. Else CPU2 Flash Sector 12 is inaccessible if this zone
is LOCKED.
Reset type: SYSRSn
23-22 GRAB_SECT11 R 0h Value in this field gets loaded from Z1_GRABSECT3[23:22] when a
read is issued to address location of Z1_GRABSECT3 in OTP.
00 : Invalid. CPU2 Flash Sector 11 is inaccessible.
01 : Request to allocate CPU2 Flash Sector 11 to Zone1.
10 : No request for CPU2 Flash Sector 11
11 : No request for CPU2 Flash Sector 11 when this zone is
UNLOCKED. Else CPU2 Flash Sector 11 is inaccessible if this zone
is LOCKED.
Reset type: SYSRSn

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Table 6-23. Z1_GRABSECT3R Register Field Descriptions (continued)

Bit Field Type Reset Description
21-20 GRAB_SECT10 R 0h Value in this field gets loaded from Z1_GRABSECT3[21:20] when a
read is issued to address location of Z1_GRABSECT3 in OTP.
00 : Invalid. CPU2 Flash Sector 10 is inaccessible.
01 : Request to allocate CPU2 Flash Sector 10 to Zone1.
10 : No request for CPU2 Flash Sector 10
11 : No request for CPU2 Flash Sector 10 when this zone is
UNLOCKED. Else CPU2 Flash Sector 10 is inaccessible if this zone
is LOCKED.
Reset type: SYSRSn
19-18 GRAB_SECT9 R 0h Value in this field gets loaded from Z1_GRABSECT3[19:18] when a
read is issued to address location of Z1_GRABSECT3 in OTP.
00 : Invalid. CPU2 Flash Sector 9 is inaccessible.
01 : Request to allocate CPU2 Flash Sector 9 to Zone1.
10 : No request for CPU2 Flash Sector 9
11 : No request for CPU2 Flash Sector 9 when this zone is
UNLOCKED. Else CPU2 Flash Sector 9 is inaccessible if this zone is
LOCKED.
Reset type: SYSRSn
17-16 GRAB_SECT8 R 0h Value in this field gets loaded from Z1_GRABSECT3[17:16] when a
read is issued to address location of Z1_GRABSECT3 in OTP.
00 : Invalid. CPU2 Flash Sector 8 is inaccessible.
01 : Request to allocate CPU2 Flash Sector 8 to Zone1.
10 : No request for CPU2 Flash Sector 8
11 : No request for CPU2 Flash Sector 8 when this zone is
UNLOCKED. Else CPU2 Flash Sector 8 is inaccessible if this zone is
LOCKED.
Reset type: SYSRSn
15-14 GRAB_SECT7 R 0h Value in this field gets loaded from Z1_GRABSECT3[15:14] when a
read is issued to address location of Z1_GRABSECT3 in OTP.
00 : Invalid. CPU2 Flash Sector 7 is inaccessible.
01 : Request to allocate CPU2 Flash Sector 7 to Zone1.
10 : No request for CPU2 Flash Sector 7
11 : No request for CPU2 Flash Sector 7 when this zone is
UNLOCKED. Else CPU2 Flash Sector 7 is inaccessible if this zone is
LOCKED.
Reset type: SYSRSn
13-12 GRAB_SECT6 R 0h Value in this field gets loaded from Z1_GRABSECT3[13:12] when a
read is issued to address location of Z1_GRABSECT3 in OTP.
00 : Invalid. CPU2 Flash Sector 6 is inaccessible.
01 : Request to allocate CPU2 Flash Sector 6 to Zone1.
10 : No request for CPU2 Flash Sector 6
11 : No request for CPU2 Flash Sector 6 when this zone is
UNLOCKED. Else CPU2 Flash Sector 6 is inaccessible if this zone is
LOCKED.
Reset type: SYSRSn
11-10 GRAB_SECT5 R 0h Value in this field gets loaded from Z1_GRABSECT3[11:10] when a
read is issued to address location of Z1_GRABSECT3 in OTP.
00 : Invalid. CPU2 Flash Sector 5 is inaccessible.
01 : Request to allocate CPU2 Flash Sector 5 to Zone1.
10 : No request for CPU2 Flash Sector 5
11 : No request for CPU2 Flash Sector 5 when this zone is
UNLOCKED. Else CPU2 Flash Sector 5 is inaccessible if this zone is
LOCKED.
Reset type: SYSRSn
9-8 GRAB_SECT4 R 0h Value in this field gets loaded from Z1_GRABSECT3[9:8] when a
read is issued to address location of Z1_GRABSECT3 in OTP.
00 : Invalid. CPU2 Flash Sector 4 is inaccessible.
01 : Request to allocate CPU2 Flash Sector 4 to Zone1.
10 : No request for CPU2 Flash Sector 4
11 : No request for CPU2 Flash Sector 4 when this zone is
UNLOCKED. Else CPU2 Flash Sector 4 is inaccessible if this zone is
LOCKED.
Reset type: SYSRSn

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Table 6-23. Z1_GRABSECT3R Register Field Descriptions (continued)

Bit Field Type Reset Description
7-6 GRAB_SECT3 R 0h Value in this field gets loaded from Z1_GRABSECT3[7:6] when a
read is issued to address location of Z1_GRABSECT3 in OTP.
00 : Invalid. CPU2 Flash Sector 3 is inaccessible.
01 : Request to allocate CPU2 Flash Sector 3 to Zone1.
10 : No request for CPU2 Flash Sector 3
11 : No request for CPU2 Flash Sector 3 when this zone is
UNLOCKED. Else CPU2 Flash Sector 3 is inaccessible if this zone is
LOCKED.
Reset type: SYSRSn
5-4 GRAB_SECT2 R 0h Value in this field gets loaded from Z1_GRABSECT3[5:4] when a
read is issued to address location of Z1_GRABSECT3 in OTP.
00 : Invalid. CPU2 Flash Sector 2 is inaccessible.
01 : Request to allocate CPU2 Flash Sector 2 to Zone1.
10 : No request for CPU2 Flash Sector 2
11 : No request for CPU2 Flash Sector 2 when this zone is
UNLOCKED. Else CPU2 Flash Sector 2 is inaccessible if this zone is
LOCKED.
Reset type: SYSRSn
3-2 GRAB_SECT1 R 0h Value in this field gets loaded from Z1_GRABSECT3[3:2] when a
read is issued to address location of Z1_GRABSECT3 in OTP.
00 : Invalid. CPU2 Flash Sector 1 is inaccessible.
01 : Request to allocate CPU2 Flash Sector 1 to Zone1.
10 : No request for CPU2 Flash Sector 1
11 : No request for CPU2 Flash Sector 1 when this zone is
UNLOCKED. Else CPU2 Flash Sector 1 is inaccessible if this zone is
LOCKED.
Reset type: SYSRSn
1-0 GRAB_SECT0 R 0h Value in this field gets loaded from Z1_GRABSECT3[1:0] when a
read is issued to address location of Z1_GRABSECT3 in OTP.
00 : Invalid. CPU2 Flash Sector 0 is inaccessible.
01 : Request to allocate CPU2 Flash Sector 0 to Zone1.
10 : No request for CPU2 Flash Sector 0
11 : No request for CPU2 Flash Sector 0 when this zone is
UNLOCKED. Else CPU2 Flash Sector 0 is inaccessible if this zone is
LOCKED.
Reset type: SYSRSn

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6.9.3.17 Z1_GRABRAM1R Register (Offset (x8) = 40h, Offset (x16) = 20h) [Reset = 0h]
Z1_GRABRAM1R is shown in Figure 6-21 and described in Table 6-24.
Return to the Summary Table.
Zone 1 Grab RAM Status Register 1
Figure 6-21. Z1_GRABRAM1R Register
31 30 29 28 27 26 25 24
RESERVED
R-0h

23 22 21 20 19 18 17 16
RESERVED GRAB_RAM9 GRAB_RAM8
R-0h R-0h R-0h

15 14 13 12 11 10 9 8
GRAB_RAM7 GRAB_RAM6 GRAB_RAM5 GRAB_RAM4
R-0h R-0h R-0h R-0h

7 6 5 4 3 2 1 0
GRAB_RAM3 GRAB_RAM2 GRAB_RAM1 GRAB_RAM0
R-0h R-0h R-0h R-0h

Table 6-24. Z1_GRABRAM1R Register Field Descriptions

Bit Field Type Reset Description
31-20 RESERVED R 0h Reserved
19-18 GRAB_RAM9 R 0h Value in this field gets loaded from Z1_GRABRAM1[19:18] when a
read is issued to address location of Z1_GRABRAM1 in OTP.
00 : Invalid. CPU1 D1 RAM is inaccessible.
01 : Request to allocate CPU1 D1 RAM to Zone1.
10 : No request for CPU1 D1 RAM
11 : No request for CPU1 D1 RAM when this zone is UNLOCKED.
Else CPU1 D1 RAM is inaccessible if this zone is LOCKED.
Reset type: SYSRSn
17-16 GRAB_RAM8 R 0h Value in this field gets loaded from Z1_GRABRAM1[17:16] when a
read is issued to address location of Z1_GRABRAM1 in OTP.
00 : Invalid. CPU1 D0 RAM is inaccessible.
01 : Request to allocate CPU1 D0 RAM to Zone1.
10 : No request for CPU1 D0 RAM
11 : No request for CPU1 D0 RAM when this zone is UNLOCKED.
Else CPU1 D0 RAM is inaccessible if this zone is LOCKED.
Reset type: SYSRSn
15-14 GRAB_RAM7 R 0h Value in this field gets loaded from Z1_GRABRAM1[15:14] when a
read is issued to address location of Z1_GRABRAM1 in OTP.
00 : Invalid. CPU1 LS7 RAM is inaccessible.
01 : Request to allocate CPU1 LS7 RAM to Zone1.
10 : No request for CPU1 LS7 RAM
11 : No request for CPU1 LS7 RAM when this zone is UNLOCKED.
Else CPU1 LS7 RAM is inaccessible if this zone is LOCKED.
Reset type: SYSRSn
13-12 GRAB_RAM6 R 0h Value in this field gets loaded from Z1_GRABRAM1[13:12] when a
read is issued to address location of Z1_GRABRAM1 in OTP.
00 : Invalid. CPU1 LS6 RAM is inaccessible.
01 : Request to allocate CPU1 LS6 RAM to Zone1.
10 : No request for CPU1 LS6 RAM
11 : No request for CPU1 LS6 RAM when this zone is UNLOCKED.
Else CPU1 LS6 RAM is inaccessible if this zone is LOCKED.
Reset type: SYSRSn

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Table 6-24. Z1_GRABRAM1R Register Field Descriptions (continued)

Bit Field Type Reset Description
11-10 GRAB_RAM5 R 0h Value in this field gets loaded from Z1_GRABRAM1[11:10] when a
read is issued to address location of Z1_GRABRAM1 in OTP.
00 : Invalid. CPU1 LS5 RAM is inaccessible.
01 : Request to allocate CPU1 LS5 RAM to Zone1.
10 : No request for CPU1 LS5 RAM
11 : No request for CPU1 LS5 RAM when this zone is UNLOCKED.
Else CPU1 LS5 RAM is inaccessible if this zone is LOCKED.
Reset type: SYSRSn
9-8 GRAB_RAM4 R 0h Value in this field gets loaded from Z1_GRABRAM1[9:8] when a read
is issued to address location of Z1_GRABRAM1 in OTP.
00 : Invalid. CPU1 LS4 RAM is inaccessible.
01 : Request to allocate CPU1 LS4 RAM to Zone1.
10 : No request for CPU1 LS4 RAM
11 : No request for CPU1 LS4 RAM when this zone is UNLOCKED.
Else CPU1 LS4 RAM is inaccessible if this zone is LOCKED.
Reset type: SYSRSn
7-6 GRAB_RAM3 R 0h Value in this field gets loaded from Z1_GRABRAM1[7:6] when a read
is issued to address location of Z1_GRABRAM1 in OTP.
00 : Invalid. CPU1 LS3 RAM is inaccessible.
01 : Request to allocate CPU1 LS3 RAM to Zone1.
10 : No request for CPU1 LS3 RAM
11 : No request for CPU1 LS3 RAM when this zone is UNLOCKED.
Else CPU1 LS3 RAM is inaccessible if this zone is LOCKED.
Reset type: SYSRSn
5-4 GRAB_RAM2 R 0h Value in this field gets loaded from Z1_GRABRAM1[5:4] when a read
is issued to address location of Z1_GRABRAM1 in OTP.
00 : Invalid. CPU1 LS2 RAM is inaccessible.
01 : Request to allocate CPU1 LS2 RAM to Zone1.
10 : No request for CPU1 LS2 RAM
11 : No request for CPU1 LS2 RAM when this zone is UNLOCKED.
Else CPU1 LS2 RAM is inaccessible if this zone is LOCKED.
Reset type: SYSRSn
3-2 GRAB_RAM1 R 0h Value in this field gets loaded from Z1_GRABRAM1[3:2] when a read
is issued to address location of Z1_GRABRAM1 in OTP.
00 : Invalid. CPU1 LS1 RAM is inaccessible.
01 : Request to allocate CPU1 LS1 RAM to Zone1.
10 : No request for CPU1 LS1 RAM
11 : No request for CPU1 LS1 RAM when this zone is UNLOCKED.
Else CPU1 LS1 RAM is inaccessible if this zone is LOCKED.
Reset type: SYSRSn
1-0 GRAB_RAM0 R 0h Value in this field gets loaded from Z1_GRABRAM1[1:0] when a read
is issued to address location of Z1_GRABRAM1 in OTP.
00 : Invalid. CPU1 LS0 RAM is inaccessible.
01 : Request to allocate CPU1 LS0 RAM to Zone1.
10 : No request for CPU1 LS0 RAM
11 : No request for CPU1 LS0 RAM when this zone is UNLOCKED.
Else CPU1 LS0 RAM is inaccessible if this zone is LOCKED.
Reset type: SYSRSn

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6.9.3.18 Z1_GRABRAM2R Register (Offset (x8) = 44h, Offset (x16) = 22h) [Reset = 0h]
Z1_GRABRAM2R is shown in Figure 6-22 and described in Table 6-25.
Return to the Summary Table.
Zone 1 Grab RAM Status Register 2
Figure 6-22. Z1_GRABRAM2R Register
31 30 29 28 27 26 25 24
GRAB_RAM15 GRAB_RAM14 GRAB_RAM13 GRAB_RAM12
R-0h R-0h R-0h R-0h

23 22 21 20 19 18 17 16
GRAB_RAM11 GRAB_RAM10 GRAB_RAM9 GRAB_RAM8
R-0h R-0h R-0h R-0h

15 14 13 12 11 10 9 8
GRAB_RAM7 GRAB_RAM6 GRAB_RAM5 GRAB_RAM4
R-0h R-0h R-0h R-0h

7 6 5 4 3 2 1 0
RESERVED GRAB_RAM1 GRAB_RAM0
R-0h R-0h R-0h

Table 6-25. Z1_GRABRAM2R Register Field Descriptions

Bit Field Type Reset Description
31-30 GRAB_RAM15 R 0h Value in this field gets loaded from Z1_GRABRAM2[31:30] when a
read is issued to address location of Z1_GRABRAM2 in OTP.
Defines Zone 1's grab request of the higher addressed half of
CPU2TOCPU1MSGRAM0.
00 : Invalid. MSG RAM is inaccessible.
01 : Request to allocate MSG RAM to Zone1.
10 : No request for MSG RAM
11 : No request for MSG RAM when this zone is UNLOCKED. Else
MSG RAM is inaccessible if this zone is LOCKED.
Reset type: SYSRSn
29-28 GRAB_RAM14 R 0h Value in this field gets loaded from Z1_GRABRAM2[29:28] when a
read is issued to address location of Z1_GRABRAM2 in OTP.
Defines Zone 1's grab request of the lower addressed half of
CPU2TOCPU1MSGRAM0.
00 : Invalid. MSG RAM is inaccessible.
01 : Request to allocate MSG RAM to Zone1.
10 : No request for MSG RAM
11 : No request for MSG RAM when this zone is UNLOCKED. Else
MSG RAM is inaccessible if this zone is LOCKED.
Reset type: SYSRSn
27-26 GRAB_RAM13 R 0h Value in this field gets loaded from Z1_GRABRAM2[27:26] when a
read is issued to address location of Z1_GRABRAM2 in OTP.
Defines Zone 1's grab request of the higher addressed half of
CPU1TOCPU2MSGRAM0.
00 : Invalid. MSG RAM is inaccessible.
01 : Request to allocate MSG RAM to Zone1.
10 : No request for MSG RAM
11 : No request for MSG RAM when this zone is UNLOCKED. Else
MSG RAM is inaccessible if this zone is LOCKED.
Reset type: SYSRSn

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Table 6-25. Z1_GRABRAM2R Register Field Descriptions (continued)

Bit Field Type Reset Description
25-24 GRAB_RAM12 R 0h Value in this field gets loaded from Z1_GRABRAM2[25:24] when a
read is issued to address location of Z1_GRABRAM2 in OTP.
Defines Zone 1's grab request of the lower addressed half of
CPU1TOCPU2MSGRAM0.
00 : Invalid. MSG RAM is inaccessible.
01 : Request to allocate MSG RAM to Zone1.
10 : No request for MSG RAM
11 : No request for MSG RAM when this zone is UNLOCKED. Else
MSG RAM is inaccessible if this zone is LOCKED.
Reset type: SYSRSn
23-22 GRAB_RAM11 R 0h Value in this field gets loaded from Z1_GRABRAM2[23:22] when a
read is issued to address location of Z1_GRABRAM2 in OTP.
Defines Zone 1's grab request of the higher addressed half of
CMTOCPU2MSGRAM0.
00 : Invalid. MSG RAM is inaccessible.
01 : Request to allocate MSG RAM to Zone1.
10 : No request for MSG RAM
11 : No request for MSG RAM when this zone is UNLOCKED. Else
MSG RAM is inaccessible if this zone is LOCKED.
Reset type: SYSRSn
21-20 GRAB_RAM10 R 0h Value in this field gets loaded from Z1_GRABRAM2[21:20] when a
read is issued to address location of Z1_GRABRAM2 in OTP.
Defines Zone 1's grab request of the lower addressed half of
CMTOCPU2MSGRAM0.
00 : Invalid. MSG RAM is inaccessible.
01 : Request to allocate MSG RAM to Zone1.
10 : No request for MSG RAM
11 : No request for MSG RAM when this zone is UNLOCKED. Else
MSG RAM is inaccessible if this zone is LOCKED.
Reset type: SYSRSn
19-18 GRAB_RAM9 R 0h Value in this field gets loaded from Z1_GRABRAM2[19:18] when a
read is issued to address location of Z1_GRABRAM2 in OTP.
Defines Zone 1's grab request of the higher addressed half of
CPU2TOCMMSGRAM0.
00 : Invalid. MSG RAM is inaccessible.
01 : Request to allocate MSG RAM to Zone1.
10 : No request for MSG RAM
11 : No request for MSG RAM when this zone is UNLOCKED. Else
MSG RAM is inaccessible if this zone is LOCKED.
Reset type: SYSRSn
17-16 GRAB_RAM8 R 0h Value in this field gets loaded from Z1_GRABRAM2[17:16] when a
read is issued to address location of Z1_GRABRAM2 in OTP.
Defines Zone 1's grab request of the lower addressed half of
CPU2TOCMMSGRAM0.
00 : Invalid. MSG RAM is inaccessible.
01 : Request to allocate MSG RAM to Zone1.
10 : No request for MSG RAM
11 : No request for MSG RAM when this zone is UNLOCKED. Else
MSG RAM is inaccessible if this zone is LOCKED.
Reset type: SYSRSn
15-14 GRAB_RAM7 R 0h Value in this field gets loaded from Z1_GRABRAM2[15:14] when a
read is issued to address location of Z1_GRABRAM2 in OTP.
Defines Zone 1's grab request of the higher addressed half of
CMTOCPU1MSGRAM0.
00 : Invalid. MSG RAM is inaccessible.
01 : Request to allocate MSG RAM to Zone1.
10 : No request for MSG RAM
11 : No request for MSG RAM when this zone is UNLOCKED. Else
MSG RAM is inaccessible if this zone is LOCKED.
Reset type: SYSRSn

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Table 6-25. Z1_GRABRAM2R Register Field Descriptions (continued)

Bit Field Type Reset Description
13-12 GRAB_RAM6 R 0h Value in this field gets loaded from Z1_GRABRAM2[13:12] when a
read is issued to address location of Z1_GRABRAM2 in OTP.
Defines Zone 1's grab request of the lower addressed half of
CMTOCPU1MSGRAM0.
00 : Invalid. MSG RAM is inaccessible.
01 : Request to allocate MSG RAM to Zone1.
10 : No request for MSG RAM
11 : No request for MSG RAM when this zone is UNLOCKED. Else
MSG RAM is inaccessible if this zone is LOCKED.
Reset type: SYSRSn
11-10 GRAB_RAM5 R 0h Value in this field gets loaded from Z1_GRABRAM2[11:10] when a
read is issued to address location of Z1_GRABRAM2 in OTP.
Defines Zone 1's grab request of the higher addressed half of
CPU1TOCMMSGRAM0.
00 : Invalid. MSG RAM is inaccessible.
01 : Request to allocate MSG RAM to Zone1.
10 : No request for MSG RAM
11 : No request for MSG RAM when this zone is UNLOCKED. Else
MSG RAM is inaccessible if this zone is LOCKED.
Reset type: SYSRSn
9-8 GRAB_RAM4 R 0h Value in this field gets loaded from Z1_GRABRAM2[9:8] when a read
is issued to address location of Z1_GRABRAM2 in OTP.
Defines Zone 1's grab request of the lower addressed half of
CPU1TOCMMSGRAM0.
00 : Invalid. MSG RAM is inaccessible.
01 : Request to allocate MSG RAM to Zone1.
10 : No request for MSG RAM
11 : No request for MSG RAM when this zone is UNLOCKED. Else
MSG RAM is inaccessible if this zone is LOCKED.
Reset type: SYSRSn
7-4 RESERVED R 0h Reserved
3-2 GRAB_RAM1 R 0h Value in this field gets loaded from Z1_GRABRAM2[3:2] when a read
is issued to address location of Z1_GRABRAM2 in OTP.
00 : Invalid. CM C1 RAM is inaccessible.
01 : Request to allocate CM C1 RAM to Zone1.
10 : No request for CM C1 RAM
11 : No request for CM C1 RAM when this zone is UNLOCKED. Else
CM C1 RAM is inaccessible if this zone is LOCKED.
Reset type: SYSRSn
1-0 GRAB_RAM0 R 0h Value in this field gets loaded from Z1_GRABRAM2[1:0] when a read
is issued to address location of Z1_GRABRAM2 in OTP.
00 : Invalid. CM C0 RAM is inaccessible.
01 : Request to allocate CM C0 RAM to Zone1.
10 : No request for CM C0 RAM
11 : No request for CM C0 RAM when this zone is UNLOCKED. Else
CM C0 RAM is inaccessible if this zone is LOCKED.
Reset type: SYSRSn

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6.9.3.19 Z1_GRABRAM3R Register (Offset (x8) = 48h, Offset (x16) = 24h) [Reset = 0h]
Z1_GRABRAM3R is shown in Figure 6-23 and described in Table 6-26.
Return to the Summary Table.
Zone 1 Grab RAM Status Register 3
Figure 6-23. Z1_GRABRAM3R Register
31 30 29 28 27 26 25 24
RESERVED
R-0h

23 22 21 20 19 18 17 16
RESERVED GRAB_RAM9 GRAB_RAM8
R-0h R-0h R-0h

15 14 13 12 11 10 9 8
GRAB_RAM7 GRAB_RAM6 GRAB_RAM5 GRAB_RAM4
R-0h R-0h R-0h R-0h

7 6 5 4 3 2 1 0
GRAB_RAM3 GRAB_RAM2 GRAB_RAM1 GRAB_RAM0
R-0h R-0h R-0h R-0h

Table 6-26. Z1_GRABRAM3R Register Field Descriptions

Bit Field Type Reset Description
31-20 RESERVED R 0h Reserved
19-18 GRAB_RAM9 R 0h Value in this field gets loaded from Z1_GRABRAM3[19:18] when a
read is issued to address location of Z1_GRABRAM3 in OTP.
00 : Invalid. CPU2 D1 RAM is inaccessible.
01 : Request to allocate CPU2 D1 RAM to Zone1.
10 : No request for CPU2 D1 RAM
11 : No request for CPU2 D1 RAM when this zone is UNLOCKED.
Else CPU2 D1 RAM is inaccessible if this zone is LOCKED.
Reset type: SYSRSn
17-16 GRAB_RAM8 R 0h Value in this field gets loaded from Z1_GRABRAM3[17:16] when a
read is issued to address location of Z1_GRABRAM3 in OTP.
00 : Invalid. CPU2 D0 RAM is inaccessible.
01 : Request to allocate CPU2 D0 RAM to Zone1.
10 : No request for CPU2 D0 RAM
11 : No request for CPU2 D0 RAM when this zone is UNLOCKED.
Else CPU2 D0 RAM is inaccessible if this zone is LOCKED.
Reset type: SYSRSn
15-14 GRAB_RAM7 R 0h Value in this field gets loaded from Z1_GRABRAM3[15:14] when a
read is issued to address location of Z1_GRABRAM3 in OTP.
00 : Invalid. CPU2 LS7 RAM is inaccessible.
01 : Request to allocate CPU2 LS7 RAM to Zone1.
10 : No request for CPU2 LS7 RAM
11 : No request for CPU2 LS7 RAM when this zone is UNLOCKED.
Else CPU2 LS7 RAM is inaccessible if this zone is LOCKED.
Reset type: SYSRSn
13-12 GRAB_RAM6 R 0h Value in this field gets loaded from Z1_GRABRAM3[13:12] when a
read is issued to address location of Z1_GRABRAM3 in OTP.
00 : Invalid. CPU2 LS6 RAM is inaccessible.
01 : Request to allocate CPU2 LS6 RAM to Zone1.
10 : No request for CPU2 LS6 RAM
11 : No request for CPU2 LS6 RAM when this zone is UNLOCKED.
Else CPU2 LS6 RAM is inaccessible if this zone is LOCKED.
Reset type: SYSRSn

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Table 6-26. Z1_GRABRAM3R Register Field Descriptions (continued)

Bit Field Type Reset Description
11-10 GRAB_RAM5 R 0h Value in this field gets loaded from Z1_GRABRAM3[11:10] when a
read is issued to address location of Z1_GRABRAM3 in OTP.
00 : Invalid. CPU2 LS5 RAM is inaccessible.
01 : Request to allocate CPU2 LS5 RAM to Zone1.
10 : No request for CPU2 LS5 RAM
11 : No request for CPU2 LS5 RAM when this zone is UNLOCKED.
Else CPU2 LS5 RAM is inaccessible if this zone is LOCKED.
Reset type: SYSRSn
9-8 GRAB_RAM4 R 0h Value in this field gets loaded from Z1_GRABRAM3[9:8] when a read
is issued to address location of Z1_GRABRAM3 in OTP.
00 : Invalid. CPU2 LS4 RAM is inaccessible.
01 : Request to allocate CPU2 LS4 RAM to Zone1.
10 : No request for CPU2 LS4 RAM
11 : No request for CPU2 LS4 RAM when this zone is UNLOCKED.
Else CPU2 LS4 RAM is inaccessible if this zone is LOCKED.
Reset type: SYSRSn
7-6 GRAB_RAM3 R 0h Value in this field gets loaded from Z1_GRABRAM3[7:6] when a read
is issued to address location of Z1_GRABRAM3 in OTP.
00 : Invalid. CPU2 LS3 RAM is inaccessible.
01 : Request to allocate CPU2 LS3 RAM to Zone1.
10 : No request for CPU2 LS3 RAM
11 : No request for CPU2 LS3 RAM when this zone is UNLOCKED.
Else CPU2 LS3 RAM is inaccessible if this zone is LOCKED.
Reset type: SYSRSn
5-4 GRAB_RAM2 R 0h Value in this field gets loaded from Z1_GRABRAM3[5:4] when a read
is issued to address location of Z1_GRABRAM3 in OTP.
00 : Invalid. CPU2 LS2 RAM is inaccessible.
01 : Request to allocate CPU2 LS2 RAM to Zone1.
10 : No request for CPU2 LS2 RAM
11 : No request for CPU2 LS2 RAM when this zone is UNLOCKED.
Else CPU2 LS2 RAM is inaccessible if this zone is LOCKED.
Reset type: SYSRSn
3-2 GRAB_RAM1 R 0h Value in this field gets loaded from Z1_GRABRAM3[3:2] when a read
is issued to address location of Z1_GRABRAM3 in OTP.
00 : Invalid. CPU2 LS1 RAM is inaccessible.
01 : Request to allocate CPU2 LS1 RAM to Zone1.
10 : No request for CPU2 LS1 RAM
11 : No request for CPU2 LS1 RAM when this zone is UNLOCKED.
Else CPU2 LS1 RAM is inaccessible if this zone is LOCKED.
Reset type: SYSRSn
1-0 GRAB_RAM0 R 0h Value in this field gets loaded from Z1_GRABRAM3[1:0] when a read
is issued to address location of Z1_GRABRAM3 in OTP.
00 : Invalid. CPU2 LS0 RAM is inaccessible.
01 : Request to allocate CPU2 LS0 RAM to Zone1.
10 : No request for CPU2 LS0 RAM
11 : No request for CPU2 LS0 RAM when this zone is UNLOCKED.
Else CPU2 LS0 RAM is inaccessible if this zone is LOCKED.
Reset type: SYSRSn

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6.9.3.20 Z1_EXEONLYSECT1R Register (Offset (x8) = 4Ch, Offset (x16) = 26h) [Reset = 0h]
Z1_EXEONLYSECT1R is shown in Figure 6-24 and described in Table 6-27.
Return to the Summary Table.
Zone 1 Execute Only Flash Status Register 1
Figure 6-24. Z1_EXEONLYSECT1R Register
31 30 29 28 27 26 25 24
RESERVED EXEONLY_CM EXEONLY_CM EXEONLY_CM EXEONLY_CM EXEONLY_CM EXEONLY_CM
_SECT13 _SECT12 _SECT11 _SECT10 _SECT9 _SECT8
R-0h R-0h R-0h R-0h R-0h R-0h R-0h

23 22 21 20 19 18 17 16
EXEONLY_CM EXEONLY_CM EXEONLY_CM EXEONLY_CM EXEONLY_CM EXEONLY_CM EXEONLY_CM EXEONLY_CM
_SECT7 _SECT6 _SECT5 _SECT4 _SECT3 _SECT2 _SECT1 _SECT0
R-0h R-0h R-0h R-0h R-0h R-0h R-0h R-0h

15 14 13 12 11 10 9 8
RESERVED EXEONLY_CP EXEONLY_CP EXEONLY_CP EXEONLY_CP EXEONLY_CP EXEONLY_CP
U1_SECT13 U1_SECT12 U1_SECT11 U1_SECT10 U1_SECT9 U1_SECT8
R-0h R-0h R-0h R-0h R-0h R-0h R-0h

7 6 5 4 3 2 1 0
EXEONLY_CP EXEONLY_CP EXEONLY_CP EXEONLY_CP EXEONLY_CP EXEONLY_CP EXEONLY_CP EXEONLY_CP
U1_SECT7 U1_SECT6 U1_SECT5 U1_SECT4 U1_SECT3 U1_SECT2 U1_SECT1 U1_SECT0
R-0h R-0h R-0h R-0h R-0h R-0h R-0h R-0h

Table 6-27. Z1_EXEONLYSECT1R Register Field Descriptions

Bit Field Type Reset Description
31-30 RESERVED R 0h Reserved
29 EXEONLY_CM_SECT13 R 0h Value in this field gets loaded from Z1_EXEONLYSECT1[29] when a
read is issued to Z1_EXEONLYSECT1 address location in OTP.
0 : Execute-Only protection is enabled for CM Flash Sector 13 (only
if it's allocated to Zone1)
1 : Execute-Only protection is disabled for CM Flash Sector 13 (only
if it's allocated to Zone1)
Reset type: SYSRSn
28 EXEONLY_CM_SECT12 R 0h Value in this field gets loaded from Z1_EXEONLYSECT1[28] when a
read is issued to Z1_EXEONLYSECT1 address location in OTP.
0 : Execute-Only protection is enabled for CM Flash Sector 12 (only
if it's allocated to Zone1)
1 : Execute-Only protection is disabled for CM Flash Sector 12 (only
if it's allocated to Zone1)
Reset type: SYSRSn
27 EXEONLY_CM_SECT11 R 0h Value in this field gets loaded from Z1_EXEONLYSECT1[27] when a
read is issued to Z1_EXEONLYSECT1 address location in OTP.
0 : Execute-Only protection is enabled for CM Flash Sector 11 (only if
it's allocated to Zone1)
1 : Execute-Only protection is disabled for CM Flash Sector 11 (only
if it's allocated to Zone1)
Reset type: SYSRSn
26 EXEONLY_CM_SECT10 R 0h Value in this field gets loaded from Z1_EXEONLYSECT1[26] when a
read is issued to Z1_EXEONLYSECT1 address location in OTP.
0 : Execute-Only protection is enabled for CM Flash Sector 10 (only
if it's allocated to Zone1)
1 : Execute-Only protection is disabled for CM Flash Sector 10 (only
if it's allocated to Zone1)
Reset type: SYSRSn

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Table 6-27. Z1_EXEONLYSECT1R Register Field Descriptions (continued)

Bit Field Type Reset Description
25 EXEONLY_CM_SECT9 R 0h Value in this field gets loaded from Z1_EXEONLYSECT1[25] when a
read is issued to Z1_EXEONLYSECT1 address location in OTP.
0 : Execute-Only protection is enabled for CM Flash Sector 9 (only if
it's allocated to Zone1)
1 : Execute-Only protection is disabled for CM Flash Sector 9 (only if
it's allocated to Zone1)
Reset type: SYSRSn
24 EXEONLY_CM_SECT8 R 0h Value in this field gets loaded from Z1_EXEONLYSECT1[24] when a
read is issued to Z1_EXEONLYSECT1 address location in OTP.
0 : Execute-Only protection is enabled for CM Flash Sector 8 (only if
it's allocated to Zone1)
1 : Execute-Only protection is disabled for CM Flash Sector 8 (only if
it's allocated to Zone1)
Reset type: SYSRSn
23 EXEONLY_CM_SECT7 R 0h Value in this field gets loaded from Z1_EXEONLYSECT1[23] when a
read is issued to Z1_EXEONLYSECT1 address location in OTP.
0 : Execute-Only protection is enabled for CM Flash Sector 7 (only if
it's allocated to Zone1)
1 : Execute-Only protection is disabled for CM Flash Sector 7 (only if
it's allocated to Zone1)
Reset type: SYSRSn
22 EXEONLY_CM_SECT6 R 0h Value in this field gets loaded from Z1_EXEONLYSECT1[22] when a
read is issued to Z1_EXEONLYSECT1 address location in OTP.
0 : Execute-Only protection is enabled for CM Flash Sector 6 (only if
it's allocated to Zone1)
1 : Execute-Only protection is disabled for CM Flash Sector 6 (only if
it's allocated to Zone1)
Reset type: SYSRSn
21 EXEONLY_CM_SECT5 R 0h Value in this field gets loaded from Z1_EXEONLYSECT1[21] when a
read is issued to Z1_EXEONLYSECT1 address location in OTP.
0 : Execute-Only protection is enabled for CM Flash Sector 5 (only if
it's allocated to Zone1)
1 : Execute-Only protection is disabled for CM Flash Sector 5 (only if
it's allocated to Zone1)
Reset type: SYSRSn
20 EXEONLY_CM_SECT4 R 0h Value in this field gets loaded from Z1_EXEONLYSECT1[20] when a
read is issued to Z1_EXEONLYSECT1 address location in OTP.
0 : Execute-Only protection is enabled for CM Flash Sector 4 (only if
it's allocated to Zone1)
1 : Execute-Only protection is disabled for CM Flash Sector 4 (only if
it's allocated to Zone1)
Reset type: SYSRSn
19 EXEONLY_CM_SECT3 R 0h Value in this field gets loaded from Z1_EXEONLYSECT1[19] when a
read is issued to Z1_EXEONLYSECT1 address location in OTP.
0 : Execute-Only protection is enabled for CM Flash Sector 3 (only if
it's allocated to Zone1)
1 : Execute-Only protection is disabled for CM Flash Sector 3 (only if
it's allocated to Zone1)
Reset type: SYSRSn
18 EXEONLY_CM_SECT2 R 0h Value in this field gets loaded from Z1_EXEONLYSECT1[18] when a
read is issued to Z1_EXEONLYSECT1 address location in OTP.
0 : Execute-Only protection is enabled for CM Flash Sector 2 (only if
it's allocated to Zone1)
1 : Execute-Only protection is disabled for CM Flash Sector 2 (only if
it's allocated to Zone1)
Reset type: SYSRSn

SPRUII0E – MAY 2019 – REVISED SEPTEMBER 2023 TMS320F2838x Real-Time Microcontrollers With Connectivity Manager 817
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Table 6-27. Z1_EXEONLYSECT1R Register Field Descriptions (continued)

Bit Field Type Reset Description
17 EXEONLY_CM_SECT1 R 0h Value in this field gets loaded from Z1_EXEONLYSECT1[17] when a
read is issued to Z1_EXEONLYSECT1 address location in OTP.
0 : Execute-Only protection is enabled for CM Flash Sector 1 (only if
it's allocated to Zone1)
1 : Execute-Only protection is disabled for CM Flash Sector 1 (only if
it's allocated to Zone1)
Reset type: SYSRSn
16 EXEONLY_CM_SECT0 R 0h Value in this field gets loaded from Z1_EXEONLYSECT1[16] when a
read is issued to Z1_EXEONLYSECT1 address location in OTP.
0 : Execute-Only protection is enabled for CM Flash Sector 0 (only if
it's allocated to Zone1)
1 : Execute-Only protection is disabled for CM Flash Sector 0 (only if
it's allocated to Zone1)
Reset type: SYSRSn
15-14 RESERVED R 0h Reserved
13 EXEONLY_CPU1_SECT1 R 0h Value in this field gets loaded from Z1_EXEONLYSECT1[13] when a
3 read is issued to Z1_EXEONLYSECT1 address location in OTP.
0 : Execute-Only protection is enabled for CPU1 Flash Sector 13
(only if it's allocated to Zone1)
1 : Execute-Only protection is disabled for CPU1 Flash Sector 13
(only if it's allocated to Zone1)
Reset type: SYSRSn
12 EXEONLY_CPU1_SECT1 R 0h Value in this field gets loaded from Z1_EXEONLYSECT1[12] when a
2 read is issued to Z1_EXEONLYSECT1 address location in OTP.
0 : Execute-Only protection is enabled for CPU1 Flash Sector 12
(only if it's allocated to Zone1)
1 : Execute-Only protection is disabled for CPU1 Flash Sector 12
(only if it's allocated to Zone1)
Reset type: SYSRSn
11 EXEONLY_CPU1_SECT1 R 0h Value in this field gets loaded from Z1_EXEONLYSECT1[11] when a
1 read is issued to Z1_EXEONLYSECT1 address location in OTP.
0 : Execute-Only protection is enabled for CPU1 Flash Sector 11
(only if it's allocated to Zone1)
1 : Execute-Only protection is disabled for CPU1 Flash Sector 11
(only if it's allocated to Zone1)
Reset type: SYSRSn
10 EXEONLY_CPU1_SECT1 R 0h Value in this field gets loaded from Z1_EXEONLYSECT1[10] when a
0 read is issued to Z1_EXEONLYSECT1 address location in OTP.
0 : Execute-Only protection is enabled for CPU1 Flash Sector 10
(only if it's allocated to Zone1)
1 : Execute-Only protection is disabled for CPU1 Flash Sector 10
(only if it's allocated to Zone1)
Reset type: SYSRSn
9 EXEONLY_CPU1_SECT9 R 0h Value in this field gets loaded from Z1_EXEONLYSECT1[9] when a
read is issued to Z1_EXEONLYSECT1 address location in OTP.
0 : Execute-Only protection is enabled for CPU1 Flash Sector 9 (only
if it's allocated to Zone1)
1 : Execute-Only protection is disabled for CPU1 Flash Sector 9
(only if it's allocated to Zone1)
Reset type: SYSRSn
8 EXEONLY_CPU1_SECT8 R 0h Value in this field gets loaded from Z1_EXEONLYSECT1[8] when a
read is issued to Z1_EXEONLYSECT1 address location in OTP.
0 : Execute-Only protection is enabled for CPU1 Flash Sector 8 (only
if it's allocated to Zone1)
1 : Execute-Only protection is disabled for CPU1 Flash Sector 8
(only if it's allocated to Zone1)
Reset type: SYSRSn

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Table 6-27. Z1_EXEONLYSECT1R Register Field Descriptions (continued)

Bit Field Type Reset Description
7 EXEONLY_CPU1_SECT7 R 0h Value in this field gets loaded from Z1_EXEONLYSECT1[7] when a
read is issued to Z1_EXEONLYSECT1 address location in OTP.
0 : Execute-Only protection is enabled for CPU1 Flash Sector 7 (only
if it's allocated to Zone1)
1 : Execute-Only protection is disabled for CPU1 Flash Sector 7
(only if it's allocated to Zone1)
Reset type: SYSRSn
6 EXEONLY_CPU1_SECT6 R 0h Value in this field gets loaded from Z1_EXEONLYSECT1[6] when a
read is issued to Z1_EXEONLYSECT1 address location in OTP.
0 : Execute-Only protection is enabled for CPU1 Flash Sector 6 (only
if it's allocated to Zone1)
1 : Execute-Only protection is disabled for CPU1 Flash Sector 6
(only if it's allocated to Zone1)
Reset type: SYSRSn
5 EXEONLY_CPU1_SECT5 R 0h Value in this field gets loaded from Z1_EXEONLYSECT1[5] when a
read is issued to Z1_EXEONLYSECT1 address location in OTP.
0 : Execute-Only protection is enabled for CPU1 Flash Sector 5 (only
if it's allocated to Zone1)
1 : Execute-Only protection is disabled for CPU1 Flash Sector 5
(only if it's allocated to Zone1)
Reset type: SYSRSn
4 EXEONLY_CPU1_SECT4 R 0h Value in this field gets loaded from Z1_EXEONLYSECT1[4] when a
read is issued to Z1_EXEONLYSECT1 address location in OTP.
0 : Execute-Only protection is enabled for CPU1 Flash Sector 4 (only
if it's allocated to Zone1)
1 : Execute-Only protection is disabled for CPU1 Flash Sector 4
(only if it's allocated to Zone1)
Reset type: SYSRSn
3 EXEONLY_CPU1_SECT3 R 0h Value in this field gets loaded from Z1_EXEONLYSECT1[3] when a
read is issued to Z1_EXEONLYSECT1 address location in OTP.
0 : Execute-Only protection is enabled for CPU1 Flash Sector 3 (only
if it's allocated to Zone1)
1 : Execute-Only protection is disabled for CPU1 Flash Sector 3
(only if it's allocated to Zone1)
Reset type: SYSRSn
2 EXEONLY_CPU1_SECT2 R 0h Value in this field gets loaded from Z1_EXEONLYSECT1[2] when a
read is issued to Z1_EXEONLYSECT1 address location in OTP.
0 : Execute-Only protection is enabled for CPU1 Flash Sector 2 (only
if it's allocated to Zone1)
1 : Execute-Only protection is disabled for CPU1 Flash Sector 2
(only if it's allocated to Zone1)
Reset type: SYSRSn
1 EXEONLY_CPU1_SECT1 R 0h Value in this field gets loaded from Z1_EXEONLYSECT1[1] when a
read is issued to Z1_EXEONLYSECT1 address location in OTP.
0 : Execute-Only protection is enabled for CPU1 Flash Sector 1 (only
if it's allocated to Zone1)
1 : Execute-Only protection is disabled for CPU1 Flash Sector 1
(only if it's allocated to Zone1)
Reset type: SYSRSn
0 EXEONLY_CPU1_SECT0 R 0h Value in this field gets loaded from Z1_EXEONLYSECT1[0] when a
read is issued to Z1_EXEONLYSECT1 address location in OTP.
0 : Execute-Only protection is enabled for CPU1 Flash Sector 0 (only
if it's allocated to Zone1)
1 : Execute-Only protection is disabled for CPU1 Flash Sector 0
(only if it's allocated to Zone1)
Reset type: SYSRSn

SPRUII0E – MAY 2019 – REVISED SEPTEMBER 2023 TMS320F2838x Real-Time Microcontrollers With Connectivity Manager 819
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6.9.3.21 Z1_EXEONLYSECT2R Register (Offset (x8) = 50h, Offset (x16) = 28h) [Reset = 0h]
Z1_EXEONLYSECT2R is shown in Figure 6-25 and described in Table 6-28.
Return to the Summary Table.
Zone 1 Execute Only Flash Status Register 2
Figure 6-25. Z1_EXEONLYSECT2R Register
31 30 29 28 27 26 25 24
RESERVED
R-0h

23 22 21 20 19 18 17 16
RESERVED
R-0h

15 14 13 12 11 10 9 8
RESERVED EXEONLY_CP EXEONLY_CP EXEONLY_CP EXEONLY_CP EXEONLY_CP EXEONLY_CP
U2_SECT13 U2_SECT12 U2_SECT11 U2_SECT10 U2_SECT9 U2_SECT8
R-0h R-0h R-0h R-0h R-0h R-0h R-0h

7 6 5 4 3 2 1 0
EXEONLY_CP EXEONLY_CP EXEONLY_CP EXEONLY_CP EXEONLY_CP EXEONLY_CP EXEONLY_CP EXEONLY_CP
U2_SECT7 U2_SECT6 U2_SECT5 U2_SECT4 U2_SECT3 U2_SECT2 U2_SECT1 U2_SECT0
R-0h R-0h R-0h R-0h R-0h R-0h R-0h R-0h

Table 6-28. Z1_EXEONLYSECT2R Register Field Descriptions

Bit Field Type Reset Description
31-14 RESERVED R 0h Reserved
13 EXEONLY_CPU2_SECT1 R 0h Value in this field gets loaded from Z1_EXEONLYSECT2[13] when a
3 read is issued to Z1_EXEONLYSECT2 address location in OTP.
0 : Execute-Only protection is enabled for CPU2 Flash Sector 13
(only if it's allocated to Zone1)
1 : Execute-Only protection is disabled for CPU2 Flash Sector 13
(only if it's allocated to Zone1)
Reset type: SYSRSn
12 EXEONLY_CPU2_SECT1 R 0h Value in this field gets loaded from Z1_EXEONLYSECT2[12] when a
2 read is issued to Z1_EXEONLYSECT2 address location in OTP.
0 : Execute-Only protection is enabled for CPU2 Flash Sector 12
(only if it's allocated to Zone1)
1 : Execute-Only protection is disabled for CPU2 Flash Sector 12
(only if it's allocated to Zone1)
Reset type: SYSRSn
11 EXEONLY_CPU2_SECT1 R 0h Value in this field gets loaded from Z1_EXEONLYSECT2[11] when a
1 read is issued to Z1_EXEONLYSECT2 address location in OTP.
0 : Execute-Only protection is enabled for CPU2 Flash Sector 11
(only if it's allocated to Zone1)
1 : Execute-Only protection is disabled for CPU2 Flash Sector 11
(only if it's allocated to Zone1)
Reset type: SYSRSn
10 EXEONLY_CPU2_SECT1 R 0h Value in this field gets loaded from Z1_EXEONLYSECT2[10] when a
0 read is issued to Z1_EXEONLYSECT2 address location in OTP.
0 : Execute-Only protection is enabled for CPU2 Flash Sector 10
(only if it's allocated to Zone1)
1 : Execute-Only protection is disabled for CPU2 Flash Sector 10
(only if it's allocated to Zone1)
Reset type: SYSRSn

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Table 6-28. Z1_EXEONLYSECT2R Register Field Descriptions (continued)

Bit Field Type Reset Description
9 EXEONLY_CPU2_SECT9 R 0h Value in this field gets loaded from Z1_EXEONLYSECT2[9] when a
read is issued to Z1_EXEONLYSECT2 address location in OTP.
0 : Execute-Only protection is enabled for CPU2 Flash Sector 9 (only
if it's allocated to Zone1)
1 : Execute-Only protection is disabled for CPU2 Flash Sector 9
(only if it's allocated to Zone1)
Reset type: SYSRSn
8 EXEONLY_CPU2_SECT8 R 0h Value in this field gets loaded from Z1_EXEONLYSECT2[8] when a
read is issued to Z1_EXEONLYSECT2 address location in OTP.
0 : Execute-Only protection is enabled for CPU2 Flash Sector 8 (only
if it's allocated to Zone1)
1 : Execute-Only protection is disabled for CPU2 Flash Sector 8
(only if it's allocated to Zone1)
Reset type: SYSRSn
7 EXEONLY_CPU2_SECT7 R 0h Value in this field gets loaded from Z1_EXEONLYSECT2[7] when a
read is issued to Z1_EXEONLYSECT2 address location in OTP.
0 : Execute-Only protection is enabled for CPU2 Flash Sector 7 (only
if it's allocated to Zone1)
1 : Execute-Only protection is disabled for CPU2 Flash Sector 7
(only if it's allocated to Zone1)
Reset type: SYSRSn
6 EXEONLY_CPU2_SECT6 R 0h Value in this field gets loaded from Z1_EXEONLYSECT2[6] when a
read is issued to Z1_EXEONLYSECT2 address location in OTP.
0 : Execute-Only protection is enabled for CPU2 Flash Sector 6 (only
if it's allocated to Zone1)
1 : Execute-Only protection is disabled for CPU2 Flash Sector 6
(only if it's allocated to Zone1)
Reset type: SYSRSn
5 EXEONLY_CPU2_SECT5 R 0h Value in this field gets loaded from Z1_EXEONLYSECT2[5] when a
read is issued to Z1_EXEONLYSECT2 address location in OTP.
0 : Execute-Only protection is enabled for CPU2 Flash Sector 5 (only
if it's allocated to Zone1)
1 : Execute-Only protection is disabled for CPU2 Flash Sector 5
(only if it's allocated to Zone1)
Reset type: SYSRSn
4 EXEONLY_CPU2_SECT4 R 0h Value in this field gets loaded from Z1_EXEONLYSECT2[4] when a
read is issued to Z1_EXEONLYSECT2 address location in OTP.
0 : Execute-Only protection is enabled for CPU2 Flash Sector 4 (only
if it's allocated to Zone1)
1 : Execute-Only protection is disabled for CPU2 Flash Sector 4
(only if it's allocated to Zone1)
Reset type: SYSRSn
3 EXEONLY_CPU2_SECT3 R 0h Value in this field gets loaded from Z1_EXEONLYSECT2[3] when a
read is issued to Z1_EXEONLYSECT2 address location in OTP.
0 : Execute-Only protection is enabled for CPU2 Flash Sector 3 (only
if it's allocated to Zone1)
1 : Execute-Only protection is disabled for CPU2 Flash Sector 3
(only if it's allocated to Zone1)
Reset type: SYSRSn
2 EXEONLY_CPU2_SECT2 R 0h Value in this field gets loaded from Z1_EXEONLYSECT2[2] when a
read is issued to Z1_EXEONLYSECT2 address location in OTP.
0 : Execute-Only protection is enabled for CPU2 Flash Sector 2 (only
if it's allocated to Zone1)
1 : Execute-Only protection is disabled for CPU2 Flash Sector 2
(only if it's allocated to Zone1)
Reset type: SYSRSn

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Table 6-28. Z1_EXEONLYSECT2R Register Field Descriptions (continued)

Bit Field Type Reset Description
1 EXEONLY_CPU2_SECT1 R 0h Value in this field gets loaded from Z1_EXEONLYSECT2[1] when a
read is issued to Z1_EXEONLYSECT2 address location in OTP.
0 : Execute-Only protection is enabled for CPU2 Flash Sector 1 (only
if it's allocated to Zone1)
1 : Execute-Only protection is disabled for CPU2 Flash Sector 1
(only if it's allocated to Zone1)
Reset type: SYSRSn
0 EXEONLY_CPU2_SECT0 R 0h Value in this field gets loaded from Z1_EXEONLYSECT2[0] when a
read is issued to Z1_EXEONLYSECT2 address location in OTP.
0 : Execute-Only protection is enabled for CPU2 Flash Sector 0 (only
if it's allocated to Zone1)
1 : Execute-Only protection is disabled for CPU2 Flash Sector 0
(only if it's allocated to Zone1)
Reset type: SYSRSn

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6.9.3.22 Z1_EXEONLYRAM1R Register (Offset (x8) = 54h, Offset (x16) = 2Ah) [Reset = 0h]
Z1_EXEONLYRAM1R is shown in Figure 6-26 and described in Table 6-29.
Return to the Summary Table.
Zone 1 Execute Only RAM Status Register 1
Figure 6-26. Z1_EXEONLYRAM1R Register
31 30 29 28 27 26 25 24
EXEONLY_RA EXEONLY_RA EXEONLY_RA EXEONLY_RA EXEONLY_RA EXEONLY_RA EXEONLY_RA EXEONLY_RA
M31 M30 M29 M28 M27 M26 M25 M24
R-0h R-0h R-0h R-0h R-0h R-0h R-0h R-0h

23 22 21 20 19 18 17 16
EXEONLY_RA EXEONLY_RA RESERVED EXEONLY_RA EXEONLY_RA
M23 M22 M17 M16
R-0h R-0h R-0h R-0h R-0h

15 14 13 12 11 10 9 8
RESERVED EXEONLY_RA EXEONLY_RA
M9 M8
R-0h R-0h R-0h

7 6 5 4 3 2 1 0
EXEONLY_RA EXEONLY_RA EXEONLY_RA EXEONLY_RA EXEONLY_RA EXEONLY_RA EXEONLY_RA EXEONLY_RA
M7 M6 M5 M4 M3 M2 M1 M0
R-0h R-0h R-0h R-0h R-0h R-0h R-0h R-0h

Table 6-29. Z1_EXEONLYRAM1R Register Field Descriptions

Bit Field Type Reset Description
31 EXEONLY_RAM31 R 0h Value in this field gets loaded from Z1_EXEONLYRAM1[31] when a
read is issued to Z1_EXEONLYRAM address location in OTP.
0 : Execute-Only protection is enabled for CPU2 LS0 RAM (only if it's
allocated to Zone1)
1 : Execute-Only protection is disabled for CPU2 LS0 RAM (only if
it's allocated to Zone1)
Reset type: SYSRSn
30 EXEONLY_RAM30 R 0h Value in this field gets loaded from Z1_EXEONLYRAM1[30] when a
read is issued to Z1_EXEONLYRAM address location in OTP.
0 : Execute-Only protection is enabled for CPU2 LS1 RAM (only if it's
allocated to Zone1)
1 : Execute-Only protection is disabled for CPU2 LS1 RAM (only if
it's allocated to Zone1)
Reset type: SYSRSn
29 EXEONLY_RAM29 R 0h Value in this field gets loaded from Z1_EXEONLYRAM1[29] when a
read is issued to Z1_EXEONLYRAM address location in OTP.
0 : Execute-Only protection is enabled for CPU2 LS2 RAM (only if it's
allocated to Zone1)
1 : Execute-Only protection is disabled for CPU2 LS2 RAM (only if
it's allocated to Zone1)
Reset type: SYSRSn
28 EXEONLY_RAM28 R 0h Value in this field gets loaded from Z1_EXEONLYRAM1[28] when a
read is issued to Z1_EXEONLYRAM1 address location in OTP.
0 : Execute-Only protection is enabled for CPU2 LS3 RAM (only if it's
allocated to Zone1)
1 : Execute-Only protection is disabled for CPU2 LS3 RAM (only if
it's allocated to Zone1)
Reset type: SYSRSn

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Table 6-29. Z1_EXEONLYRAM1R Register Field Descriptions (continued)

Bit Field Type Reset Description
27 EXEONLY_RAM27 R 0h Value in this field gets loaded from Z1_EXEONLYRAM1[27] when a
read is issued to Z1_EXEONLYRAM1 address location in OTP.
0 : Execute-Only protection is enabled for CPU2 LS4 RAM (only if it's
allocated to Zone1)
1 : Execute-Only protection is disabled for CPU2 LS4 RAM (only if
it's allocated to Zone1)
Reset type: SYSRSn
26 EXEONLY_RAM26 R 0h Value in this field gets loaded from Z1_EXEONLYRAM1[26] when a
read is issued to Z1_EXEONLYRAM1 address location in OTP.
0 : Execute-Only protection is enabled for CPU2 LS5 RAM (only if it's
allocated to Zone1)
1 : Execute-Only protection is disabled for CPU2 LS5 RAM (only if
it's allocated to Zone1)
Reset type: SYSRSn
25 EXEONLY_RAM25 R 0h Value in this field gets loaded from Z1_EXEONLYRAM1[25] when a
read is issued to Z1_EXEONLYRAM1 address location in OTP.
0 : Execute-Only protection is enabled for CPU2 LS6 RAM (only if it's
allocated to Zone1)
1 : Execute-Only protection is disabled for CPU2 LS6 RAM (only if
it's allocated to Zone1)
Reset type: SYSRSn
24 EXEONLY_RAM24 R 0h Value in this field gets loaded from Z1_EXEONLYRAM1[24] when a
read is issued to Z1_EXEONLYRAM1 address location in OTP.
0 : Execute-Only protection is enabled for CPU2 LS7 RAM (only if it's
allocated to Zone1)
1 : Execute-Only protection is disabled for CPU2 LS7 RAM (only if
it's allocated to Zone1)
Reset type: SYSRSn
23 EXEONLY_RAM23 R 0h Value in this field gets loaded from Z1_EXEONLYRAM1[23] when a
read is issued to Z1_EXEONLYRAM address location in OTP.
0 : Execute-Only protection is enabled for CPU2 D0 RAM (only if it's
allocated to Zone1)
1 : Execute-Only protection is disabled for CPU2 D0 RAM (only if it's
allocated to Zone1)
Reset type: SYSRSn
22 EXEONLY_RAM22 R 0h Value in this field gets loaded from Z1_EXEONLYRAM1[22] when a
read is issued to Z1_EXEONLYRAM address location in OTP.
0 : Execute-Only protection is enabled for CPU2 D1 RAM (only if it's
allocated to Zone1)
1 : Execute-Only protection is disabled for CPU2 D1 RAM (only if it's
allocated to Zone1)
Reset type: SYSRSn
21-18 RESERVED R 0h Reserved
17 EXEONLY_RAM17 R 0h Value in this field gets loaded from Z1_EXEONLYRAM1[17] when a
read is issued to Z1_EXEONLYRAM address location in OTP.
0 : Execute-Only protection is enabled for CM C1 RAM (only if it's
allocated to Zone1)
1 : Execute-Only protection is disabled for CM C1 RAM (only if it's
allocated to Zone1)
Reset type: SYSRSn
16 EXEONLY_RAM16 R 0h Value in this field gets loaded from Z1_EXEONLYRAM1[16] when a
read is issued to Z1_EXEONLYRAM address location in OTP.
0 : Execute-Only protection is enabled for CM C0 RAM (only if it's
allocated to Zone1)
1 : Execute-Only protection is disabled for CM C0 RAM (only if it's
allocated to Zone1)
Reset type: SYSRSn
15-10 RESERVED R 0h Reserved

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Table 6-29. Z1_EXEONLYRAM1R Register Field Descriptions (continued)

Bit Field Type Reset Description
9 EXEONLY_RAM9 R 0h Value in this field gets loaded from Z1_EXEONLYRAM1[9] when a
read is issued to Z1_EXEONLYRAM address location in OTP.
0 : Execute-Only protection is enabled for CPU1 D1 RAM (only if it's
allocated to Zone1)
1 : Execute-Only protection is disabled for CPU1 D1 RAM (only if it's
allocated to Zone1)
Reset type: SYSRSn
8 EXEONLY_RAM8 R 0h Value in this field gets loaded from Z1_EXEONLYRAM1[8] when a
read is issued to Z1_EXEONLYRAM address location in OTP.
0 : Execute-Only protection is enabled for CPU1 D0 RAM (only if it's
allocated to Zone1)
1 : Execute-Only protection is disabled for CPU1 D0 RAM (only if it's
allocated to Zone1)
Reset type: SYSRSn
7 EXEONLY_RAM7 R 0h Value in this field gets loaded from Z1_EXEONLYRAM1[7] when a
read is issued to Z1_EXEONLYRAM address location in OTP.
0 : Execute-Only protection is enabled for CPU1 LS7 RAM (only if it's
allocated to Zone1)
1 : Execute-Only protection is disabled for CPU1 LS7 RAM (only if
it's allocated to Zone1)
Reset type: SYSRSn
6 EXEONLY_RAM6 R 0h Value in this field gets loaded from Z1_EXEONLYRAM1[6] when a
read is issued to Z1_EXEONLYRAM1 address location in OTP.
0 : Execute-Only protection is enabled for CPU1 LS6 RAM (only if it's
allocated to Zone1)
1 : Execute-Only protection is disabled for CPU1 LS6 RAM (only if
it's allocated to Zone1)
Reset type: SYSRSn
5 EXEONLY_RAM5 R 0h Value in this field gets loaded from Z1_EXEONLYRAM1[5] when a
read is issued to Z1_EXEONLYRAM1 address location in OTP.
0 : Execute-Only protection is enabled for CPU1 LS5 RAM (only if it's
allocated to Zone1)
1 : Execute-Only protection is disabled for CPU1 LS5 RAM (only if
it's allocated to Zone1)
Reset type: SYSRSn
4 EXEONLY_RAM4 R 0h Value in this field gets loaded from Z1_EXEONLYRAM1[4] when a
read is issued to Z1_EXEONLYRAM1 address location in OTP.
0 : Execute-Only protection is enabled for CPU1 LS4 RAM (only if it's
allocated to Zone1)
1 : Execute-Only protection is disabled for CPU1 LS4 RAM (only if
it's allocated to Zone1)
Reset type: SYSRSn
3 EXEONLY_RAM3 R 0h Value in this field gets loaded from Z1_EXEONLYRAM1[3] when a
read is issued to Z1_EXEONLYRAM1 address location in OTP.
0 : Execute-Only protection is enabled for CPU1 LS3 RAM (only if it's
allocated to Zone1)
1 : Execute-Only protection is disabled for CPU1 LS3 RAM (only if
it's allocated to Zone1)
Reset type: SYSRSn
2 EXEONLY_RAM2 R 0h Value in this field gets loaded from Z1_EXEONLYRAM1[2] when a
read is issued to Z1_EXEONLYRAM1 address location in OTP.
0 : Execute-Only protection is enabled for CPU1 LS2 RAM (only if it's
allocated to Zone1)
1 : Execute-Only protection is disabled for CPU1 LS2 RAM (only if
it's allocated to Zone1)
Reset type: SYSRSn

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Table 6-29. Z1_EXEONLYRAM1R Register Field Descriptions (continued)

Bit Field Type Reset Description
1 EXEONLY_RAM1 R 0h Value in this field gets loaded from Z1_EXEONLYRAM1[1] when a
read is issued to Z1_EXEONLYRAM1 address location in OTP.
0 : Execute-Only protection is enabled for CPU1 LS1 RAM (only if it's
allocated to Zone1)
1 : Execute-Only protection is disabled for CPU1 LS1 RAM (only if
it's allocated to Zone1)
Reset type: SYSRSn
0 EXEONLY_RAM0 R 0h Value in this field gets loaded from Z1_EXEONLYRAM1[0] when a
read is issued to Z1_EXEONLYRAM1 address location in OTP.
0 : Execute-Only protection is enabled for CPU1 LS0 RAM (only if it's
allocated to Zone1)
1 : Execute-Only protection is disabled for CPU1 LS0 RAM (only if
it's allocated to Zone1)
Reset type: SYSRSn

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6.9.3.23 Z1_JTAGKEY0 Register (Offset (x8) = 5Ch, Offset (x16) = 2Eh) [Reset = 0h]
Z1_JTAGKEY0 is shown in Figure 6-27 and described in Table 6-30.
Return to the Summary Table.
JTAG Unlock Key Register 0
Figure 6-27. Z1_JTAGKEY0 Register
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
KEY0
R-0h

Table 6-30. Z1_JTAGKEY0 Register Field Descriptions

Bit Field Type Reset Description
31-0 KEY0 R 0h Value in this field is scanned in via the JLM scan chain. JTAGKEY is
compared to a hidden register that gets dummy loaded when a read
is issued to the JTAGPSWD locations in OTP.
Reset type: PORESETn

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6.9.3.24 Z1_JTAGKEY1 Register (Offset (x8) = 60h, Offset (x16) = 30h) [Reset = 0h]
Z1_JTAGKEY1 is shown in Figure 6-28 and described in Table 6-31.
Return to the Summary Table.
JTAG Unlock Key Register 1
Figure 6-28. Z1_JTAGKEY1 Register
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
KEY1
R-0h

Table 6-31. Z1_JTAGKEY1 Register Field Descriptions

Bit Field Type Reset Description
31-0 KEY1 R 0h Value in this field is scanned in via the JLM scan chain. JTAGKEY is
compared to a hidden register that gets dummy loaded when a read
is issued to the JTAGPSWD locations in OTP.
Reset type: PORESETn

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6.9.3.25 Z1_JTAGKEY2 Register (Offset (x8) = 64h, Offset (x16) = 32h) [Reset = 0h]
Z1_JTAGKEY2 is shown in Figure 6-29 and described in Table 6-32.
Return to the Summary Table.
JTAG Unlock Key Register 2
Figure 6-29. Z1_JTAGKEY2 Register
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
KEY2
R-0h

Table 6-32. Z1_JTAGKEY2 Register Field Descriptions

Bit Field Type Reset Description
31-0 KEY2 R 0h Value in this field is scanned in via the JLM scan chain. JTAGKEY is
compared to a hidden register that gets dummy loaded when a read
is issued to the JTAGPSWD locations in OTP.
Reset type: PORESETn

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6.9.3.26 Z1_JTAGKEY3 Register (Offset (x8) = 68h, Offset (x16) = 34h) [Reset = 0h]
Z1_JTAGKEY3 is shown in Figure 6-30 and described in Table 6-33.
Return to the Summary Table.
JTAG Unlock Key Register 3
Figure 6-30. Z1_JTAGKEY3 Register
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
KEY3
R-0h

Table 6-33. Z1_JTAGKEY3 Register Field Descriptions

Bit Field Type Reset Description
31-0 KEY3 R 0h Value in this field is scanned in via the JLM scan chain. JTAGKEY is
compared to a hidden register that gets dummy loaded when a read
is issued to the JTAGPSWD locations in OTP.
Reset type: PORESETn

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6.9.3.27 Z1_CMACKEY0 Register (Offset (x8) = 6Ch, Offset (x16) = 36h) [Reset = 0h]
Z1_CMACKEY0 is shown in Figure 6-31 and described in Table 6-34.
Return to the Summary Table.
Secure Boot CMAC Key Status Register 0
Figure 6-31. Z1_CMACKEY0 Register
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
KEY0
R-0h

Table 6-34. Z1_CMACKEY0 Register Field Descriptions

Bit Field Type Reset Description
31-0 KEY0 R 0h Value in this field gets loaded from CMACKEY0 when a read is
issued to its address in OTP.
Reset type: SYSRSn

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6.9.3.28 Z1_CMACKEY1 Register (Offset (x8) = 70h, Offset (x16) = 38h) [Reset = 0h]
Z1_CMACKEY1 is shown in Figure 6-32 and described in Table 6-35.
Return to the Summary Table.
Secure Boot CMAC Key Status Register 1
Figure 6-32. Z1_CMACKEY1 Register
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
KEY1
R-0h

Table 6-35. Z1_CMACKEY1 Register Field Descriptions

Bit Field Type Reset Description
31-0 KEY1 R 0h Value in this field gets loaded from CMACKEY1 when a read is
issued to its address in OTP.
Reset type: SYSRSn

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6.9.3.29 Z1_CMACKEY2 Register (Offset (x8) = 74h, Offset (x16) = 3Ah) [Reset = 0h]
Z1_CMACKEY2 is shown in Figure 6-33 and described in Table 6-36.
Return to the Summary Table.
Secure Boot CMAC Key Status Register 2
Figure 6-33. Z1_CMACKEY2 Register
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
KEY2
R-0h

Table 6-36. Z1_CMACKEY2 Register Field Descriptions

Bit Field Type Reset Description
31-0 KEY2 R 0h Value in this field gets loaded from CMACKEY2 when a read is
issued to its address in OTP.
Reset type: SYSRSn

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6.9.3.30 Z1_CMACKEY3 Register (Offset (x8) = 78h, Offset (x16) = 3Ch) [Reset = 0h]
Z1_CMACKEY3 is shown in Figure 6-34 and described in Table 6-37.
Return to the Summary Table.
Secure Boot CMAC Key Status Register 3
Figure 6-34. Z1_CMACKEY3 Register
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
KEY3
R-0h

Table 6-37. Z1_CMACKEY3 Register Field Descriptions

Bit Field Type Reset Description
31-0 KEY3 R 0h Value in this field gets loaded from CMACKEY3 when a read is
issued to its address in OTP.
Reset type: SYSRSn

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6.9.4 DCSM_Z2_REGS Registers

Table 6-38 lists the memory-mapped registers for the DCSM_Z2_REGS registers. All register offset addresses
not listed in Table 6-38 should be considered as reserved locations and the register contents should not be
modified.
Table 6-38. DCSM_Z2_REGS Registers
Offset Offset Acronym Register Name Write Section
(x8) (x16) Protection
0h 0h Z2_LINKPOINTER Zone 2 Link Pointer Go
4h 2h Z2_OTPSECLOCK Zone 2 OTP Secure Lock Go
Ch 6h Z2_LINKPOINTERERR Link Pointer Error Go
10h 8h Z2_GPREG1 Zone 2 General Purpose Register-1 Go
14h Ah Z2_GPREG2 Zone 2 General Purpose Register-2 Go
18h Ch Z2_GPREG3 Zone 2 General Purpose Register-3 Go
1Ch Eh Z2_GPREG4 Zone 2 General Purpose Register-4 Go
20h 10h Z2_CSMKEY0 Zone 2 CSM Key 0 Go
24h 12h Z2_CSMKEY1 Zone 2 CSM Key 1 Go
28h 14h Z2_CSMKEY2 Zone 2 CSM Key 2 Go
2Ch 16h Z2_CSMKEY3 Zone 2 CSM Key 3 Go
30h 18h Z2_CR Zone 2 CSM Control Register Go
34h 1Ah Z2_GRABSECT1R Zone 2 Grab Flash Status Register 1 Go
38h 1Ch Z2_GRABSECT2R Zone 2 Grab Flash Status Register 2 Go
3Ch 1Eh Z2_GRABSECT3R Zone 2 Grab Flash Status Register 3 Go
40h 20h Z2_GRABRAM1R Zone 2 Grab RAM Status Register 1 Go
44h 22h Z2_GRABRAM2R Zone 2 Grab RAM Status Register 2 Go
48h 24h Z2_GRABRAM3R Zone 2 Grab RAM Status Register 3 Go
4Ch 26h Z2_EXEONLYSECT1R Zone 2 Execute Only Flash Status Register 1 Go
50h 28h Z2_EXEONLYSECT2R Zone 2 Execute Only Flash Status Register 2 Go
54h 2Ah Z2_EXEONLYRAM1R Zone 2 Execute Only RAM Status Register 1 Go

Complex bit access types are encoded to fit into small table cells. Table 6-39 shows the codes that are used for
access types in this section.
Table 6-39. DCSM_Z2_REGS Access Type Codes
Access Type Code Description
Read Type
R R Read
R-0 R Read
-0 Returns 0s
Write Type
W W Write
Reset or Default Value
-n Value after reset or the default
value
Register Array Variables

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Table 6-39. DCSM_Z2_REGS Access Type Codes

(continued)
Access Type Code Description
i,j,k,l,m,n When these variables are used in
a register name, an offset, or an
address, they refer to the value of
a register array where the register
is part of a group of repeating
registers. The register groups
form a hierarchical structure and
the array is represented with a
formula.
y When this variable is used in a
register name, an offset, or an
address it refers to the value of
a register array.

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6.9.4.1 Z2_LINKPOINTER Register (Offset (x8) = 0h, Offset (x16) = 0h) [Reset = FFFFC000h]
Z2_LINKPOINTER is shown in Figure 6-35 and described in Table 6-40.
Return to the Summary Table.
Zone 2 Link Pointer
Figure 6-35. Z2_LINKPOINTER Register
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RESERVED LINKPOINTER
R-0h R-0h

Table 6-40. Z2_LINKPOINTER Register Field Descriptions

Bit Field Type Reset Description
31-14 RESERVED R 0h Reserved
13-0 LINKPOINTER R 0h This is resolved Link-Pointer value which is generated by looking at
the three physical Link-Pointer values loaded from OTP
Reset type: SYSRSn

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6.9.4.2 Z2_OTPSECLOCK Register (Offset (x8) = 4h, Offset (x16) = 2h) [Reset = 1h]
Z2_OTPSECLOCK is shown in Figure 6-36 and described in Table 6-41.
Return to the Summary Table.
Zone 2 OTP Secure Lock
Figure 6-36. Z2_OTPSECLOCK Register
31 30 29 28 27 26 25 24
RESERVED
R-0h

23 22 21 20 19 18 17 16
RESERVED
R-0h

15 14 13 12 11 10 9 8
RESERVED CRCLOCK
R-0h R-0h

7 6 5 4 3 2 1 0
PSWDLOCK RESERVED JTAGLOCK
R-0h R-0h R-1h

Table 6-41. Z2_OTPSECLOCK Register Field Descriptions

Bit Field Type Reset Description
31-16 RESERVED R 0h Reserved
15-12 RESERVED R 0h Reserved
11-8 CRCLOCK R 0h Value in this field gets loaded from Z2_CRCLOCK[3:0] when a read
is issued to address location of Z2_CRCLOCK in OTP.
1111 : VCU has ability to calculate CRC on secure memories.
Other Value : VCU doesn't have ability to calculate CRC on secure
memories.
Reset type: XRSn
7-4 PSWDLOCK R 0h Value in this field gets loaded from Z2_PSWDLOCK[3:0] when a
read is issued to address location of Z1_PSWDLOCK in OTP.
1111 : CSM password locations in OTP are not protected and can be
read from debugger as well as code running from anywhere.
Other Value : CSM password locations in OTP are protected and
can't be read without unlocking CSM of that zone.
Reset type: XRSn
3-1 RESERVED R 0h Reserved
0 JTAGLOCK R 1h Reflects the state of the JTAGLOCK feature.
0 : JTAG is not locked
1 : JTAG is locked
This bit is a copy of the Z1_OTPSECLOCK.JTAGLOCK bit.
Reset type: PORESETn

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6.9.4.3 Z2_LINKPOINTERERR Register (Offset (x8) = Ch, Offset (x16) = 6h) [Reset = 0h]
Z2_LINKPOINTERERR is shown in Figure 6-37 and described in Table 6-42.
Return to the Summary Table.
Link Pointer Error
Figure 6-37. Z2_LINKPOINTERERR Register
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
RESERVED
R-0h

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RESERVED Z2_LINKPOINTERERR
R-0h R-0h

Table 6-42. Z2_LINKPOINTERERR Register Field Descriptions

Bit Field Type Reset Description
31-14 RESERVED R 0h Reserved
13-0 Z2_LINKPOINTERERR R 0h These bits indicate errors during formation of the resolved Link-
Pointer value after the three physical Link-Pointer values loaded of
OTP in flash.
0 : No Error.
Other : Error on bit positions which is set to 1.
Reset type: SYSRSn

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6.9.4.4 Z2_GPREG1 Register (Offset (x8) = 10h, Offset (x16) = 8h) [Reset = 0h]
Z2_GPREG1 is shown in Figure 6-38 and described in Table 6-43.
Return to the Summary Table.
Zone 2 General Purpose Register-1
Figure 6-38. Z2_GPREG1 Register
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
GPREG1
R-0h

Table 6-43. Z2_GPREG1 Register Field Descriptions

Bit Field Type Reset Description
31-0 GPREG1 R 0h This field gets loaded with the contents of Z2OTP_GPREG1
locations in Zone-2-USER-OTP when a dummy read is issued to
that address. Users can use this register to load any general purpose
non-voliate content from USER-OTP of Zone-2
Reset type: SYSRSn

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6.9.4.5 Z2_GPREG2 Register (Offset (x8) = 14h, Offset (x16) = Ah) [Reset = 0h]
Z2_GPREG2 is shown in Figure 6-39 and described in Table 6-44.
Return to the Summary Table.
Zone 2 General Purpose Register-2
Figure 6-39. Z2_GPREG2 Register
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
GPREG2
R-0h

Table 6-44. Z2_GPREG2 Register Field Descriptions

Bit Field Type Reset Description
31-0 GPREG2 R 0h This field gets loaded with the contents of Z2OTP_GPREG2
locations in Zone-2-USER-OTP when a dummy read is issued to
that address. Users can use this register to load any general purpose
non-voliate content from USER-OTP of Zone-2
Reset type: SYSRSn

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6.9.4.6 Z2_GPREG3 Register (Offset (x8) = 18h, Offset (x16) = Ch) [Reset = 0h]
Z2_GPREG3 is shown in Figure 6-40 and described in Table 6-45.
Return to the Summary Table.
Zone 2 General Purpose Register-3
Figure 6-40. Z2_GPREG3 Register
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
GPREG3
R-0h

Table 6-45. Z2_GPREG3 Register Field Descriptions

Bit Field Type Reset Description
31-0 GPREG3 R 0h This field gets loaded with the contents of Z2OTP_GPREG3
locations in Zone-2-USER-OTP when a dummy read is issued to
that address. Users can use this register to load any general purpose
non-voliate content from USER-OTP of Zone-2
Reset type: SYSRSn

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6.9.4.7 Z2_GPREG4 Register (Offset (x8) = 1Ch, Offset (x16) = Eh) [Reset = 0h]
Z2_GPREG4 is shown in Figure 6-41 and described in Table 6-46.
Return to the Summary Table.
Zone 2 General Purpose Register-4
Figure 6-41. Z2_GPREG4 Register
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
GPREG4
R-0h

Table 6-46. Z2_GPREG4 Register Field Descriptions

Bit Field Type Reset Description
31-0 GPREG4 R 0h This field gets loaded with the contents of Z2OTP_GPREG4
locations in Zone-2-USER-OTP when a dummy read is issued to
that address. Users can use this register to load any general purpose
non-voliate content from USER-OTP of Zone-2
Reset type: SYSRSn

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6.9.4.8 Z2_CSMKEY0 Register (Offset (x8) = 20h, Offset (x16) = 10h) [Reset = 0h]
Z2_CSMKEY0 is shown in Figure 6-42 and described in Table 6-47.
Return to the Summary Table.
Zone 2 CSM Key 0
Figure 6-42. Z2_CSMKEY0 Register
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Z2_CSMKEY0
R/W-0h

Table 6-47. Z2_CSMKEY0 Register Field Descriptions

Bit Field Type Reset Description
31-0 Z2_CSMKEY0 R/W 0h To unlock Zone2, user needs to write this regsiter with exact value
as Z2_CSMPSWD0, programmed in OTP (zone gets unlock only if
128 bit password in OTP match with value written in four CSMKEY
registers.)
Reset type: SYSRSn

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6.9.4.9 Z2_CSMKEY1 Register (Offset (x8) = 24h, Offset (x16) = 12h) [Reset = 0h]
Z2_CSMKEY1 is shown in Figure 6-43 and described in Table 6-48.
Return to the Summary Table.
Zone 2 CSM Key 1
Figure 6-43. Z2_CSMKEY1 Register
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Z2_CSMKEY1
R/W-0h

Table 6-48. Z2_CSMKEY1 Register Field Descriptions

Bit Field Type Reset Description
31-0 Z2_CSMKEY1 R/W 0h To unlock Zone2, user needs to write this regsiter with exact value
as Z2_CSMPSWD1, programmed in OTP (zone gets unlock only if
128 bit password in OTP match with value written in four CSMKEY
registers.)
Reset type: SYSRSn

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6.9.4.10 Z2_CSMKEY2 Register (Offset (x8) = 28h, Offset (x16) = 14h) [Reset = 0h]
Z2_CSMKEY2 is shown in Figure 6-44 and described in Table 6-49.
Return to the Summary Table.
Zone 2 CSM Key 2
Figure 6-44. Z2_CSMKEY2 Register
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Z2_CSMKEY2
R/W-0h

Table 6-49. Z2_CSMKEY2 Register Field Descriptions

Bit Field Type Reset Description
31-0 Z2_CSMKEY2 R/W 0h To unlock Zone2, user needs to write this regsiter with exact value
as Z2_CSMPSWD2, programmed in OTP (zone gets unlock only if
128 bit password in OTP match with value written in four CSMKEY
registers.)
Reset type: SYSRSn

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6.9.4.11 Z2_CSMKEY3 Register (Offset (x8) = 2Ch, Offset (x16) = 16h) [Reset = 0h]
Z2_CSMKEY3 is shown in Figure 6-45 and described in Table 6-50.
Return to the Summary Table.
Zone 2 CSM Key 3
Figure 6-45. Z2_CSMKEY3 Register
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Z2_CSMKEY3
R/W-0h

Table 6-50. Z2_CSMKEY3 Register Field Descriptions

Bit Field Type Reset Description
31-0 Z2_CSMKEY3 R/W 0h To unlock Zone2, user needs to write this regsiter with exact value
as Z2_CSMPSWD3, programmed in OTP (zone gets unlock only if
128 bit password in OTP match with value written in four CSMKEY
registers.)
Reset type: SYSRSn

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6.9.4.12 Z2_CR Register (Offset (x8) = 30h, Offset (x16) = 18h) [Reset = 00080000h]
Z2_CR is shown in Figure 6-46 and described in Table 6-51.
Return to the Summary Table.
Zone 2 CSM Control Register
Figure 6-46. Z2_CR Register
31 30 29 28 27 26 25 24
FORCESEC RESERVED
R-0/W-0h R-0h

23 22 21 20 19 18 17 16
RESERVED ARMED UNSECURE ALLONE ALLZERO RESERVED
R-0h R-0h R-0h R-0h R-1h R-0h

15 14 13 12 11 10 9 8
RESERVED
R-0h

7 6 5 4 3 2 1 0
RESERVED RESERVED RESERVED RESERVED RESERVED
R-0h R-0h R-0h R-0h R-0h

Table 6-51. Z2_CR Register Field Descriptions

Bit Field Type Reset Description
31 FORCESEC R-0/W 0h A write '1' to this fields resets the state of zone. If zone is unlocked,
it'll lock(secure) the zone and also resets all the bits in this register.
Reset type: SYSRSn
30-24 RESERVED R 0h Reserved
23 RESERVED R 0h Reserved
22 ARMED R 0h 0 : Dummy read to CSM Password locations in OTP hasn't been
performed.
1 : Dummy read to CSM Password locations in OTP has been
performed.
Reset type: SYSRSn
21 UNSECURE R 0h Indiacates the state of Zone.
0 : Zone is in lock(secure) state.
1 : Zone is in unlock(unsecure) state.
Reset type: SYSRSn
20 ALLONE R 0h Indicates the state of CSM passwords.
0 : Zone CSM Passwords are not all ones.
1 : Zone CSM Passwords are all ones.
Reset type: SYSRSn
19 ALLZERO R 1h Indicates the state of CSM passowrds.
0 : CSM Passwords are not all zeros.
1 : CSM Passwords are all zero and device is permanently locked.
Reset type: SYSRSn
18-16 RESERVED R 0h Reserved
15-4 RESERVED R 0h Reserved
3 RESERVED R 0h Reserved
2 RESERVED R 0h Reserved
1 RESERVED R 0h Reserved
0 RESERVED R 0h Reserved

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6.9.4.13 Z2_GRABSECT1R Register (Offset (x8) = 34h, Offset (x16) = 1Ah) [Reset = 0h]
Z2_GRABSECT1R is shown in Figure 6-47 and described in Table 6-52.
Return to the Summary Table.
Zone 2 Grab Flash Status Register 1
Figure 6-47. Z2_GRABSECT1R Register
31 30 29 28 27 26 25 24
RESERVED GRAB_SECT13 GRAB_SECT12
R-0h R-0h R-0h

23 22 21 20 19 18 17 16
GRAB_SECT11 GRAB_SECT10 GRAB_SECT9 GRAB_SECT8
R-0h R-0h R-0h R-0h

15 14 13 12 11 10 9 8
GRAB_SECT7 GRAB_SECT6 GRAB_SECT5 GRAB_SECT4
R-0h R-0h R-0h R-0h

7 6 5 4 3 2 1 0
GRAB_SECT3 GRAB_SECT2 GRAB_SECT1 GRAB_SECT0
R-0h R-0h R-0h R-0h

Table 6-52. Z2_GRABSECT1R Register Field Descriptions

Bit Field Type Reset Description
31-28 RESERVED R 0h Reserved
27-26 GRAB_SECT13 R 0h Value in this field gets loaded from Z2_GRABSECT1[27:26] when a
read is issued to address location of Z2_GRABSECT1 in OTP.
00 : Invalid. CPU1 Flash Sector 13 is inaccessible.
01 : Request to allocate CPU1 Flash Sector 13 to Zone2.
10 : No request for CPU1 Flash Sector 13
11 : No request for CPU1 Flash Sector 13 when this zone is
UNLOCKED. Else CPU1 Flash Sector 13 is inaccessible if this zone
is LOCKED.
Reset type: SYSRSn
25-24 GRAB_SECT12 R 0h Value in this field gets loaded from Z2_GRABSECT1[25:24] when a
read is issued to address location of Z2_GRABSECT1 in OTP.
00 : Invalid. CPU1 Flash Sector 12 is inaccessible.
01 : Request to allocate CPU1 Flash Sector 12 to Zone2.
10 : No request for CPU1 Flash Sector 12
11 : No request for CPU1 Flash Sector 12 when this zone is
UNLOCKED. Else CPU1 Flash Sector 12 is inaccessible if this zone
is LOCKED.
Reset type: SYSRSn
23-22 GRAB_SECT11 R 0h Value in this field gets loaded from Z2_GRABSECT1[23:22] when a
read is issued to address location of Z2_GRABSECT1 in OTP.
00 : Invalid. CPU1 Flash Sector 11 is inaccessible.
01 : Request to allocate CPU1 Flash Sector 11 to Zone2.
10 : No request for CPU1 Flash Sector 11
11 : No request for CPU1 Flash Sector 11 when this zone is
UNLOCKED. Else CPU1 Flash Sector 11 is inaccessible if this zone
is LOCKED.
Reset type: SYSRSn

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Table 6-52. Z2_GRABSECT1R Register Field Descriptions (continued)

Bit Field Type Reset Description
21-20 GRAB_SECT10 R 0h Value in this field gets loaded from Z2_GRABSECT1[21:20] when a
read is issued to address location of Z2_GRABSECT1 in OTP.
00 : Invalid. CPU1 Flash Sector 10 is inaccessible.
01 : Request to allocate CPU1 Flash Sector 10 to Zone2.
10 : No request for CPU1 Flash Sector 10
11 : No request for CPU1 Flash Sector 10 when this zone is
UNLOCKED. Else CPU1 Flash Sector 10 is inaccessible if this zone
is LOCKED.
Reset type: SYSRSn
19-18 GRAB_SECT9 R 0h Value in this field gets loaded from Z2_GRABSECT1[19:18] when a
read is issued to address location of Z2_GRABSECT1 in OTP.
00 : Invalid. CPU1 Flash Sector 9 is inaccessible.
01 : Request to allocate CPU1 Flash Sector 9 to Zone2.
10 : No request for CPU1 Flash Sector 9
11 : No request for CPU1 Flash Sector 9 when this zone is
UNLOCKED. Else CPU1 Flash Sector 9 is inaccessible if this zone is
LOCKED.
Reset type: SYSRSn
17-16 GRAB_SECT8 R 0h Value in this field gets loaded from Z2_GRABSECT1[17:16] when a
read is issued to address location of Z2_GRABSECT1 in OTP.
00 : Invalid. CPU1 Flash Sector 8 is inaccessible.
01 : Request to allocate CPU1 Flash Sector 8 to Zone2.
10 : No request for CPU1 Flash Sector 8
11 : No request for CPU1 Flash Sector 8 when this zone is
UNLOCKED. Else CPU1 Flash Sector 8 is inaccessible if this zone is
LOCKED.
Reset type: SYSRSn
15-14 GRAB_SECT7 R 0h Value in this field gets loaded from Z2_GRABSECT1[15:14] when a
read is issued to address location of Z2_GRABSECT1 in OTP.
00 : Invalid. CPU1 Flash Sector 7 is inaccessible.
01 : Request to allocate CPU1 Flash Sector 7 to Zone2.
10 : No request for CPU1 Flash Sector 7
11 : No request for CPU1 Flash Sector 7 when this zone is
UNLOCKED. Else CPU1 Flash Sector 7 is inaccessible if this zone is
LOCKED.
Reset type: SYSRSn
13-12 GRAB_SECT6 R 0h Value in this field gets loaded from Z2_GRABSECT1[13:12] when a
read is issued to address location of Z2_GRABSECT1 in OTP.
00 : Invalid. CPU1 Flash Sector 6 is inaccessible.
01 : Request to allocate CPU1 Flash Sector 6 to Zone2.
10 : No request for CPU1 Flash Sector 6
11 : No request for CPU1 Flash Sector 6 when this zone is
UNLOCKED. Else CPU1 Flash Sector 6 is inaccessible if this zone is
LOCKED.
Reset type: SYSRSn
11-10 GRAB_SECT5 R 0h Value in this field gets loaded from Z2_GRABSECT1[11:10] when a
read is issued to address location of Z2_GRABSECT1 in OTP.
00 : Invalid. CPU1 Flash Sector 5 is inaccessible.
01 : Request to allocate CPU1 Flash Sector 5 to Zone2.
10 : No request for CPU1 Flash Sector 5
11 : No request for CPU1 Flash Sector 5 when this zone is
UNLOCKED. Else CPU1 Flash Sector 5 is inaccessible if this zone is
LOCKED.
Reset type: SYSRSn
9-8 GRAB_SECT4 R 0h Value in this field gets loaded from Z2_GRABSECT1[9:8] when a
read is issued to address location of Z2_GRABSECT1 in OTP.
00 : Invalid. CPU1 Flash Sector 4 is inaccessible.
01 : Request to allocate CPU1 Flash Sector 4 to Zone2.
10 : No request for CPU1 Flash Sector 4
11 : No request for CPU1 Flash Sector 4 when this zone is
UNLOCKED. Else CPU1 Flash Sector 4 is inaccessible if this zone is
LOCKED.
Reset type: SYSRSn

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Table 6-52. Z2_GRABSECT1R Register Field Descriptions (continued)

Bit Field Type Reset Description
7-6 GRAB_SECT3 R 0h Value in this field gets loaded from Z2_GRABSECT1[7:6] when a
read is issued to address location of Z2_GRABSECT1 in OTP.
00 : Invalid. CPU1 Flash Sector 3 is inaccessible.
01 : Request to allocate CPU1 Flash Sector 3 to Zone2.
10 : No request for CPU1 Flash Sector 3
11 : No request for CPU1 Flash Sector 3 when this zone is
UNLOCKED. Else CPU1 Flash Sector 3 is inaccessible if this zone is
LOCKED.
Reset type: SYSRSn
5-4 GRAB_SECT2 R 0h Value in this field gets loaded from Z2_GRABSECT1[5:4] when a
read is issued to address location of Z2_GRABSECT1 in OTP.
00 : Invalid. CPU1 Flash Sector 2 is inaccessible.
01 : Request to allocate CPU1 Flash Sector 2 to Zone2.
10 : No request for CPU1 Flash Sector 2
11 : No request for CPU1 Flash Sector 2 when this zone is
UNLOCKED. Else CPU1 Flash Sector 2 is inaccessible if this zone is
LOCKED.
Reset type: SYSRSn
3-2 GRAB_SECT1 R 0h Value in this field gets loaded from Z2_GRABSECT1[3:2] when a
read is issued to address location of Z2_GRABSECT1 in OTP.
00 : Invalid. CPU1 Flash Sector 1 is inaccessible.
01 : Request to allocate CPU1 Flash Sector 1 to Zone2.
10 : No request for CPU1 Flash Sector 1
11 : No request for CPU1 Flash Sector 1 when this zone is
UNLOCKED. Else CPU1 Flash Sector 1 is inaccessible if this zone is
LOCKED.
Reset type: SYSRSn
1-0 GRAB_SECT0 R 0h Value in this field gets loaded from Z2_GRABSECT1[1:0] when a
read is issued to address location of Z2_GRABSECT1 in OTP.
00 : Invalid. CPU1 Flash Sector 0 is inaccessible.
01 : Request to allocate CPU1 Flash Sector 0 to Zone2.
10 : No request for CPU1 Flash Sector 0
11 : No request for CPU1 Flash Sector 0 when this zone is
UNLOCKED. Else CPU1 Flash Sector 0 is inaccessible if this zone is
LOCKED.
Reset type: SYSRSn

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6.9.4.14 Z2_GRABSECT2R Register (Offset (x8) = 38h, Offset (x16) = 1Ch) [Reset = 0h]
Z2_GRABSECT2R is shown in Figure 6-48 and described in Table 6-53.
Return to the Summary Table.
Zone 2 Grab Flash Status Register 2
Figure 6-48. Z2_GRABSECT2R Register
31 30 29 28 27 26 25 24
RESERVED GRAB_SECT13 GRAB_SECT12
R-0h R-0h R-0h

23 22 21 20 19 18 17 16
GRAB_SECT11 GRAB_SECT10 GRAB_SECT9 GRAB_SECT8
R-0h R-0h R-0h R-0h

15 14 13 12 11 10 9 8
GRAB_SECT7 GRAB_SECT6 GRAB_SECT5 GRAB_SECT4
R-0h R-0h R-0h R-0h

7 6 5 4 3 2 1 0
GRAB_SECT3 GRAB_SECT2 GRAB_SECT1 GRAB_SECT0
R-0h R-0h R-0h R-0h

Table 6-53. Z2_GRABSECT2R Register Field Descriptions

Bit Field Type Reset Description
31-28 RESERVED R 0h Reserved
27-26 GRAB_SECT13 R 0h Value in this field gets loaded from Z2_GRABSECT2[27:26] when a
read is issued to address location of Z2_GRABSECT2 in OTP.
00 : Invalid. CM Flash Sector 13 is inaccessible.
01 : Request to allocate CM Flash Sector 13 to Zone2.
10 : No request for CM Flash Sector 13
11 : No request for CM Flash Sector 13 when this zone is
UNLOCKED. Else CM Flash Sector 13 is inaccessible if this zone
is LOCKED.
Reset type: SYSRSn
25-24 GRAB_SECT12 R 0h Value in this field gets loaded from Z2_GRABSECT2[25:24] when a
read is issued to address location of Z2_GRABSECT2 in OTP.
00 : Invalid. CM Flash Sector 12 is inaccessible.
01 : Request to allocate CM Flash Sector 12 to Zone2.
10 : No request for CM Flash Sector 12
11 : No request for CM Flash Sector 12 when this zone is
UNLOCKED. Else CM Flash Sector 12 is inaccessible if this zone
is LOCKED.
Reset type: SYSRSn
23-22 GRAB_SECT11 R 0h Value in this field gets loaded from Z2_GRABSECT2[23:22] when a
read is issued to address location of Z2_GRABSECT2 in OTP.
00 : Invalid. CM Flash Sector 11 is inaccessible.
01 : Request to allocate CM Flash Sector 11 to Zone2.
10 : No request for CM Flash Sector 11
11 : No request for CM Flash Sector 11 when this zone is
UNLOCKED. Else CM Flash Sector 11 is inaccessible if this zone
is LOCKED.
Reset type: SYSRSn

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Table 6-53. Z2_GRABSECT2R Register Field Descriptions (continued)

Bit Field Type Reset Description
21-20 GRAB_SECT10 R 0h Value in this field gets loaded from Z2_GRABSECT2[21:20] when a
read is issued to address location of Z2_GRABSECT2 in OTP.
00 : Invalid. CM Flash Sector 10 is inaccessible.
01 : Request to allocate CM Flash Sector 10 to Zone2.
10 : No request for CM Flash Sector 10
11 : No request for CM Flash Sector 10 when this zone is
UNLOCKED. Else CM Flash Sector 10 is inaccessible if this zone
is LOCKED.
Reset type: SYSRSn
19-18 GRAB_SECT9 R 0h Value in this field gets loaded from Z2_GRABSECT2[19:18] when a
read is issued to address location of Z2_GRABSECT2 in OTP.
00 : Invalid. CM Flash Sector 9 is inaccessible.
01 : Request to allocate CM Flash Sector 9 to Zone2.
10 : No request for CM Flash Sector 9
11 : No request for CM Flash Sector 9 when this zone is
UNLOCKED. Else CM Flash Sector 9 is inaccessible if this zone
is LOCKED.
Reset type: SYSRSn
17-16 GRAB_SECT8 R 0h Value in this field gets loaded from Z2_GRABSECT2[17:16] when a
read is issued to address location of Z2_GRABSECT2 in OTP.
00 : Invalid. CM Flash Sector 8 is inaccessible.
01 : Request to allocate CM Flash Sector 8 to Zone2.
10 : No request for CM Flash Sector 8
11 : No request for CM Flash Sector 8 when this zone is
UNLOCKED. Else CM Flash Sector 8 is inaccessible if this zone
is LOCKED.
Reset type: SYSRSn
15-14 GRAB_SECT7 R 0h Value in this field gets loaded from Z2_GRABSECT2[15:14] when a
read is issued to address location of Z2_GRABSECT2 in OTP.
00 : Invalid. CM Flash Sector 7 is inaccessible.
01 : Request to allocate CM Flash Sector 7 to Zone2.
10 : No request for CM Flash Sector 7
11 : No request for CM Flash Sector 7 when this zone is
UNLOCKED. Else CM Flash Sector 7 is inaccessible if this zone
is LOCKED.
Reset type: SYSRSn
13-12 GRAB_SECT6 R 0h Value in this field gets loaded from Z2_GRABSECT2[13:12] when a
read is issued to address location of Z2_GRABSECT2 in OTP.
00 : Invalid. CM Flash Sector 6 is inaccessible.
01 : Request to allocate CM Flash Sector 6 to Zone2.
10 : No request for CM Flash Sector 6
11 : No request for CM Flash Sector 6 when this zone is
UNLOCKED. Else CM Flash Sector 6 is inaccessible if this zone
is LOCKED.
Reset type: SYSRSn
11-10 GRAB_SECT5 R 0h Value in this field gets loaded from Z2_GRABSECT2[11:10] when a
read is issued to address location of Z2_GRABSECT2 in OTP.
00 : Invalid. CM Flash Sector 5 is inaccessible.
01 : Request to allocate CM Flash Sector 5 to Zone2.
10 : No request for CM Flash Sector 5
11 : No request for CM Flash Sector 5 when this zone is
UNLOCKED. Else CM Flash Sector 5 is inaccessible if this zone
is LOCKED.
Reset type: SYSRSn
9-8 GRAB_SECT4 R 0h Value in this field gets loaded from Z2_GRABSECT2[9:8] when a
read is issued to address location of Z2_GRABSECT2 in OTP.
00 : Invalid. CM Flash Sector 4 is inaccessible.
01 : Request to allocate CM Flash Sector 4 to Zone2.
10 : No request for CM Flash Sector 4
11 : No request for CM Flash Sector 4 when this zone is
UNLOCKED. Else CM Flash Sector 4 is inaccessible if this zone
is LOCKED.
Reset type: SYSRSn

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Table 6-53. Z2_GRABSECT2R Register Field Descriptions (continued)

Bit Field Type Reset Description
7-6 GRAB_SECT3 R 0h Value in this field gets loaded from Z2_GRABSECT2[7:6] when a
read is issued to address location of Z2_GRABSECT2 in OTP.
00 : Invalid. CM Flash Sector 3 is inaccessible.
01 : Request to allocate CM Flash Sector 3 to Zone2.
10 : No request for CM Flash Sector 3
11 : No request for CM Flash Sector 3 when this zone is
UNLOCKED. Else CM Flash Sector 3 is inaccessible if this zone
is LOCKED.
Reset type: SYSRSn
5-4 GRAB_SECT2 R 0h Value in this field gets loaded from Z2_GRABSECT2[5:4] when a
read is issued to address location of Z2_GRABSECT2 in OTP.
00 : Invalid. CM Flash Sector 2 is inaccessible.
01 : Request to allocate CM Flash Sector 2 to Zone2.
10 : No request for CM Flash Sector 2
11 : No request for CM Flash Sector 2 when this zone is
UNLOCKED. Else CM Flash Sector 2 is inaccessible if this zone
is LOCKED.
Reset type: SYSRSn
3-2 GRAB_SECT1 R 0h Value in this field gets loaded from Z2_GRABSECT2[3:2] when a
read is issued to address location of Z2_GRABSECT2 in OTP.
00 : Invalid. CM Flash Sector 1 is inaccessible.
01 : Request to allocate CM Flash Sector 1 to Zone2.
10 : No request for CM Flash Sector 1
11 : No request for CM Flash Sector 1 when this zone is
UNLOCKED. Else CM Flash Sector 1 is inaccessible if this zone
is LOCKED.
Reset type: SYSRSn
1-0 GRAB_SECT0 R 0h Value in this field gets loaded from Z2_GRABSECT2[1:0] when a
read is issued to address location of Z2_GRABSECT2 in OTP.
00 : Invalid. CM Flash Sector 0 is inaccessible.
01 : Request to allocate CM Flash Sector 0 to Zone2.
10 : No request for CM Flash Sector 0
11 : No request for CM Flash Sector 0 when this zone is
UNLOCKED. Else CM Flash Sector 0 is inaccessible if this zone
is LOCKED.
Reset type: SYSRSn

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6.9.4.15 Z2_GRABSECT3R Register (Offset (x8) = 3Ch, Offset (x16) = 1Eh) [Reset = 0h]
Z2_GRABSECT3R is shown in Figure 6-49 and described in Table 6-54.
Return to the Summary Table.
Zone 2 Grab Flash Status Register 3
Figure 6-49. Z2_GRABSECT3R Register
31 30 29 28 27 26 25 24
RESERVED GRAB_SECT13 GRAB_SECT12
R-0h R-0h R-0h

23 22 21 20 19 18 17 16
GRAB_SECT11 GRAB_SECT10 GRAB_SECT9 GRAB_SECT8
R-0h R-0h R-0h R-0h

15 14 13 12 11 10 9 8
GRAB_SECT7 GRAB_SECT6 GRAB_SECT5 GRAB_SECT4
R-0h R-0h R-0h R-0h

7 6 5 4 3 2 1 0
GRAB_SECT3 GRAB_SECT2 GRAB_SECT1 GRAB_SECT0
R-0h R-0h R-0h R-0h

Table 6-54. Z2_GRABSECT3R Register Field Descriptions

Bit Field Type Reset Description
31-28 RESERVED R 0h Reserved
27-26 GRAB_SECT13 R 0h Value in this field gets loaded from Z2_GRABSECT3[27:26] when a
read is issued to address location of Z2_GRABSECT3 in OTP.
00 : Invalid. CPU2 Flash Sector 13 is inaccessible.
01 : Request to allocate CPU2 Flash Sector 13 to Zone2.
10 : No request for CPU2 Flash Sector 13
11 : No request for CPU2 Flash Sector 13 when this zone is
UNLOCKED. Else CPU2 Flash Sector 13 is inaccessible if this zone
is LOCKED.
Reset type: SYSRSn
25-24 GRAB_SECT12 R 0h Value in this field gets loaded from Z2_GRABSECT3[25:24] when a
read is issued to address location of Z2_GRABSECT3 in OTP.
00 : Invalid. CPU2 Flash Sector 12 is inaccessible.
01 : Request to allocate CPU2 Flash Sector 12 to Zone2.
10 : No request for CPU2 Flash Sector 12
11 : No request for CPU2 Flash Sector 12 when this zone is
UNLOCKED. Else CPU2 Flash Sector 12 is inaccessible if this zone
is LOCKED.
Reset type: SYSRSn
23-22 GRAB_SECT11 R 0h Value in this field gets loaded from Z2_GRABSECT3[23:22] when a
read is issued to address location of Z2_GRABSECT3 in OTP.
00 : Invalid. CPU2 Flash Sector 11 is inaccessible.
01 : Request to allocate CPU2 Flash Sector 11 to Zone2.
10 : No request for CPU2 Flash Sector 11
11 : No request for CPU2 Flash Sector 11 when this zone is
UNLOCKED. Else CPU2 Flash Sector 11 is inaccessible if this zone
is LOCKED.
Reset type: SYSRSn

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Table 6-54. Z2_GRABSECT3R Register Field Descriptions (continued)

Bit Field Type Reset Description
21-20 GRAB_SECT10 R 0h Value in this field gets loaded from Z2_GRABSECT3[21:20] when a
read is issued to address location of Z2_GRABSECT3 in OTP.
00 : Invalid. CPU2 Flash Sector 10 is inaccessible.
01 : Request to allocate CPU2 Flash Sector 10 to Zone2.
10 : No request for CPU2 Flash Sector 10
11 : No request for CPU2 Flash Sector 10 when this zone is
UNLOCKED. Else CPU2 Flash Sector 10 is inaccessible if this zone
is LOCKED.
Reset type: SYSRSn
19-18 GRAB_SECT9 R 0h Value in this field gets loaded from Z2_GRABSECT3[19:18] when a
read is issued to address location of Z2_GRABSECT3 in OTP.
00 : Invalid. CPU2 Flash Sector 9 is inaccessible.
01 : Request to allocate CPU2 Flash Sector 9 to Zone2.
10 : No request for CPU2 Flash Sector 9
11 : No request for CPU2 Flash Sector 9 when this zone is
UNLOCKED. Else CPU2 Flash Sector 9 is inaccessible if this zone is
LOCKED.
Reset type: SYSRSn
17-16 GRAB_SECT8 R 0h Value in this field gets loaded from Z2_GRABSECT3[17:16] when a
read is issued to address location of Z2_GRABSECT3 in OTP.
00 : Invalid. CPU2 Flash Sector 8 is inaccessible.
01 : Request to allocate CPU2 Flash Sector 8 to Zone2.
10 : No request for CPU2 Flash Sector 8
11 : No request for CPU2 Flash Sector 8 when this zone is
UNLOCKED. Else CPU2 Flash Sector 8 is inaccessible if this zone is
LOCKED.
Reset type: SYSRSn
15-14 GRAB_SECT7 R 0h Value in this field gets loaded from Z2_GRABSECT3[15:14] when a
read is issued to address location of Z2_GRABSECT3 in OTP.
00 : Invalid. CPU2 Flash Sector 7 is inaccessible.
01 : Request to allocate CPU2 Flash Sector 7 to Zone2.
10 : No request for CPU2 Flash Sector 7
11 : No request for CPU2 Flash Sector 7 when this zone is
UNLOCKED. Else CPU2 Flash Sector 7 is inaccessible if this zone is
LOCKED.
Reset type: SYSRSn
13-12 GRAB_SECT6 R 0h Value in this field gets loaded from Z2_GRABSECT3[13:12] when a
read is issued to address location of Z2_GRABSECT3 in OTP.
00 : Invalid. CPU2 Flash Sector 6 is inaccessible.
01 : Request to allocate CPU2 Flash Sector 6 to Zone2.
10 : No request for CPU2 Flash Sector 6
11 : No request for CPU2 Flash Sector 6 when this zone is
UNLOCKED. Else CPU2 Flash Sector 6 is inaccessible if this zone is
LOCKED.
Reset type: SYSRSn
11-10 GRAB_SECT5 R 0h Value in this field gets loaded from Z2_GRABSECT3[11:10] when a
read is issued to address location of Z2_GRABSECT3 in OTP.
00 : Invalid. CPU2 Flash Sector 5 is inaccessible.
01 : Request to allocate CPU2 Flash Sector 5 to Zone2.
10 : No request for CPU2 Flash Sector 5
11 : No request for CPU2 Flash Sector 5 when this zone is
UNLOCKED. Else CPU2 Flash Sector 5 is inaccessible if this zone is
LOCKED.
Reset type: SYSRSn
9-8 GRAB_SECT4 R 0h Value in this field gets loaded from Z2_GRABSECT3[9:8] when a
read is issued to address location of Z2_GRABSECT3 in OTP.
00 : Invalid. CPU2 Flash Sector 4 is inaccessible.
01 : Request to allocate CPU2 Flash Sector 4 to Zone2.
10 : No request for CPU2 Flash Sector 4
11 : No request for CPU2 Flash Sector 4 when this zone is
UNLOCKED. Else CPU2 Flash Sector 4 is inaccessible if this zone is
LOCKED.
Reset type: SYSRSn

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Table 6-54. Z2_GRABSECT3R Register Field Descriptions (continued)

Bit Field Type Reset Description
7-6 GRAB_SECT3 R 0h Value in this field gets loaded from Z2_GRABSECT3[7:6] when a
read is issued to address location of Z2_GRABSECT3 in OTP.
00 : Invalid. CPU2 Flash Sector 3 is inaccessible.
01 : Request to allocate CPU2 Flash Sector 3 to Zone2.
10 : No request for CPU2 Flash Sector 3
11 : No request for CPU2 Flash Sector 3 when this zone is
UNLOCKED. Else CPU2 Flash Sector 3 is inaccessible if this zone is
LOCKED.
Reset type: SYSRSn
5-4 GRAB_SECT2 R 0h Value in this field gets loaded from Z2_GRABSECT3[5:4] when a
read is issued to address location of Z2_GRABSECT3 in OTP.
00 : Invalid. CPU2 Flash Sector 2 is inaccessible.
01 : Request to allocate CPU2 Flash Sector 2 to Zone2.
10 : No request for CPU2 Flash Sector 2
11 : No request for CPU2 Flash Sector 2 when this zone is
UNLOCKED. Else CPU2 Flash Sector 2 is inaccessible if this zone is
LOCKED.
Reset type: SYSRSn
3-2 GRAB_SECT1 R 0h Value in this field gets loaded from Z2_GRABSECT3[3:2] when a
read is issued to address location of Z2_GRABSECT3 in OTP.
00 : Invalid. CPU2 Flash Sector 1 is inaccessible.
01 : Request to allocate CPU2 Flash Sector 1 to Zone2.
10 : No request for CPU2 Flash Sector 1
11 : No request for CPU2 Flash Sector 1 when this zone is
UNLOCKED. Else CPU2 Flash Sector 1 is inaccessible if this zone is
LOCKED.
Reset type: SYSRSn
1-0 GRAB_SECT0 R 0h Value in this field gets loaded from Z2_GRABSECT3[1:0] when a
read is issued to address location of Z2_GRABSECT3 in OTP.
00 : Invalid. CPU2 Flash Sector 0 is inaccessible.
01 : Request to allocate CPU2 Flash Sector 0 to Zone2.
10 : No request for CPU2 Flash Sector 0
11 : No request for CPU2 Flash Sector 0 when this zone is
UNLOCKED. Else CPU2 Flash Sector 0 is inaccessible if this zone is
LOCKED.
Reset type: SYSRSn

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6.9.4.16 Z2_GRABRAM1R Register (Offset (x8) = 40h, Offset (x16) = 20h) [Reset = 0h]
Z2_GRABRAM1R is shown in Figure 6-50 and described in Table 6-55.
Return to the Summary Table.
Zone 2 Grab RAM Status Register 1
Figure 6-50. Z2_GRABRAM1R Register
31 30 29 28 27 26 25 24
RESERVED
R-0h

23 22 21 20 19 18 17 16
RESERVED GRAB_RAM9 GRAB_RAM8
R-0h R-0h R-0h

15 14 13 12 11 10 9 8
GRAB_RAM7 GRAB_RAM6 GRAB_RAM5 GRAB_RAM4
R-0h R-0h R-0h R-0h

7 6 5 4 3 2 1 0
GRAB_RAM3 GRAB_RAM2 GRAB_RAM1 GRAB_RAM0
R-0h R-0h R-0h R-0h

Table 6-55. Z2_GRABRAM1R Register Field Descriptions

Bit Field Type Reset Description
31-20 RESERVED R 0h Reserved
19-18 GRAB_RAM9 R 0h Value in this field gets loaded from Z2_GRABRAM1[19:18] when a
read is issued to address location of Z2_GRABRAM1 in OTP.
00 : Invalid. CPU1 D1 RAM is inaccessible.
01 : Request to allocate CPU1 D1 RAM to Zone2.
10 : No request for CPU1 D1 RAM
11 : No request for CPU1 D1 RAM when this zone is UNLOCKED.
Else CPU1 D1 RAM is inaccessible if this zone is LOCKED.
Reset type: SYSRSn
17-16 GRAB_RAM8 R 0h Value in this field gets loaded from Z2_GRABRAM1[17:16] when a
read is issued to address location of Z2_GRABRAM1 in OTP.
00 : Invalid. CPU1 D0 RAM is inaccessible.
01 : Request to allocate CPU1 D0 RAM to Zone2.
10 : No request for CPU1 D0 RAM
11 : No request for CPU1 D0 RAM when this zone is UNLOCKED.
Else CPU1 D0 RAM is inaccessible if this zone is LOCKED.
Reset type: SYSRSn
15-14 GRAB_RAM7 R 0h Value in this field gets loaded from Z2_GRABRAM1[15:14] when a
read is issued to address location of Z2_GRABRAM1 in OTP.
00 : Invalid. CPU1 LS7 RAM is inaccessible.
01 : Request to allocate CPU1 LS7 RAM to Zone2.
10 : No request for CPU1 LS7 RAM
11 : No request for CPU1 LS7 RAM when this zone is UNLOCKED.
Else CPU1 LS7 RAM is inaccessible if this zone is LOCKED.
Reset type: SYSRSn
13-12 GRAB_RAM6 R 0h Value in this field gets loaded from Z2_GRABRAM1[13:12] when a
read is issued to address location of Z2_GRABRAM1 in OTP.
00 : Invalid. CPU1 LS6 RAM is inaccessible.
01 : Request to allocate CPU1 LS6 RAM to Zone2.
10 : No request for CPU1 LS6 RAM
11 : No request for CPU1 LS6 RAM when this zone is UNLOCKED.
Else CPU1 LS6 RAM is inaccessible if this zone is LOCKED.
Reset type: SYSRSn

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Table 6-55. Z2_GRABRAM1R Register Field Descriptions (continued)

Bit Field Type Reset Description
11-10 GRAB_RAM5 R 0h Value in this field gets loaded from Z2_GRABRAM1[11:10] when a
read is issued to address location of Z2_GRABRAM1 in OTP.
00 : Invalid. CPU1 LS5 RAM is inaccessible.
01 : Request to allocate CPU1 LS5 RAM to Zone2.
10 : No request for CPU1 LS5 RAM
11 : No request for CPU1 LS5 RAM when this zone is UNLOCKED.
Else CPU1 LS5 RAM is inaccessible if this zone is LOCKED.
Reset type: SYSRSn
9-8 GRAB_RAM4 R 0h Value in this field gets loaded from Z2_GRABRAM1[9:8] when a read
is issued to address location of Z2_GRABRAM1 in OTP.
00 : Invalid. CPU1 LS4 RAM is inaccessible.
01 : Request to allocate CPU1 LS4 RAM to Zone2.
10 : No request for CPU1 LS4 RAM
11 : No request for CPU1 LS4 RAM when this zone is UNLOCKED.
Else CPU1 LS4 RAM is inaccessible if this zone is LOCKED.
Reset type: SYSRSn
7-6 GRAB_RAM3 R 0h Value in this field gets loaded from Z2_GRABRAM1[7:6] when a read
is issued to address location of Z2_GRABRAM1 in OTP.
00 : Invalid. CPU1 LS3 RAM is inaccessible.
01 : Request to allocate CPU1 LS3 RAM to Zone2.
10 : No request for CPU1 LS3 RAM
11 : No request for CPU1 LS3 RAM when this zone is UNLOCKED.
Else CPU1 LS3 RAM is inaccessible if this zone is LOCKED.
Reset type: SYSRSn
5-4 GRAB_RAM2 R 0h Value in this field gets loaded from Z2_GRABRAM1[5:4] when a read
is issued to address location of Z2_GRABRAM1 in OTP.
00 : Invalid. CPU1 LS2 RAM is inaccessible.
01 : Request to allocate CPU1 LS2 RAM to Zone2.
10 : No request for CPU1 LS2 RAM
11 : No request for CPU1 LS2 RAM when this zone is UNLOCKED.
Else CPU1 LS2 RAM is inaccessible if this zone is LOCKED.
Reset type: SYSRSn
3-2 GRAB_RAM1 R 0h Value in this field gets loaded from Z2_GRABRAM1[3:2] when a read
is issued to address location of Z2_GRABRAM1 in OTP.
00 : Invalid. CPU1 LS1 RAM is inaccessible.
01 : Request to allocate CPU1 LS1 RAM to Zone2.
10 : No request for CPU1 LS1 RAM
11 : No request for CPU1 LS1 RAM when this zone is UNLOCKED.
Else CPU1 LS1 RAM is inaccessible if this zone is LOCKED.
Reset type: SYSRSn
1-0 GRAB_RAM0 R 0h Value in this field gets loaded from Z2_GRABRAM1[1:0] when a read
is issued to address location of Z2_GRABRAM1 in OTP.
00 : Invalid. CPU1 LS0 RAM is inaccessible.
01 : Request to allocate CPU1 LS0 RAM to Zone2.
10 : No request for CPU1 LS0 RAM
11 : No request for CPU1 LS0 RAM when this zone is UNLOCKED.
Else CPU1 LS0 RAM is inaccessible if this zone is LOCKED.
Reset type: SYSRSn

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6.9.4.17 Z2_GRABRAM2R Register (Offset (x8) = 44h, Offset (x16) = 22h) [Reset = 0h]
Z2_GRABRAM2R is shown in Figure 6-51 and described in Table 6-56.
Return to the Summary Table.
Zone 2 Grab RAM Status Register 2
Figure 6-51. Z2_GRABRAM2R Register
31 30 29 28 27 26 25 24
GRAB_RAM15 GRAB_RAM14 GRAB_RAM13 GRAB_RAM12
R-0h R-0h R-0h R-0h

23 22 21 20 19 18 17 16
GRAB_RAM11 GRAB_RAM10 GRAB_RAM9 GRAB_RAM8
R-0h R-0h R-0h R-0h

15 14 13 12 11 10 9 8
GRAB_RAM7 GRAB_RAM6 GRAB_RAM5 GRAB_RAM4
R-0h R-0h R-0h R-0h

7 6 5 4 3 2 1 0
RESERVED GRAB_RAM1 GRAB_RAM0
R-0h R-0h R-0h

Table 6-56. Z2_GRABRAM2R Register Field Descriptions

Bit Field Type Reset Description
31-30 GRAB_RAM15 R 0h Value in this field gets loaded from Z2_GRABRAM2[31:30] when a
read is issued to address location of Z2_GRABRAM2 in OTP.
Defines Zone 2's grab request of the higher addressed half of
CPU2TOCPU1MSGRAM0.
00 : Invalid. MSG RAM is inaccessible.
01 : Request to allocate MSG RAM to Zone2.
10 : No request for MSG RAM
11 : No request for MSG RAM when this zone is UNLOCKED. Else
MSG RAM is inaccessible if this zone is LOCKED.
Reset type: SYSRSn
29-28 GRAB_RAM14 R 0h Value in this field gets loaded from Z2_GRABRAM2[29:28] when a
read is issued to address location of Z2_GRABRAM2 in OTP.
Defines Zone 2's grab request of the lower addressed half of
CPU2TOCPU1MSGRAM0.
00 : Invalid. MSG RAM is inaccessible.
01 : Request to allocate MSG RAM to Zone2.
10 : No request for MSG RAM
11 : No request for MSG RAM when this zone is UNLOCKED. Else
MSG RAM is inaccessible if this zone is LOCKED.
Reset type: SYSRSn
27-26 GRAB_RAM13 R 0h Value in this field gets loaded from Z2_GRABRAM2[27:26] when a
read is issued to address location of Z2_GRABRAM2 in OTP.
Defines Zone 2's grab request of the higher addressed half of
CPU1TOCPU2MSGRAM0.
00 : Invalid. MSG RAM is inaccessible.
01 : Request to allocate MSG RAM to Zone2.
10 : No request for MSG RAM
11 : No request for MSG RAM when this zone is UNLOCKED. Else
MSG RAM is inaccessible if this zone is LOCKED.
Reset type: SYSRSn

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Table 6-56. Z2_GRABRAM2R Register Field Descriptions (continued)

Bit Field Type Reset Description
25-24 GRAB_RAM12 R 0h Value in this field gets loaded from Z2_GRABRAM2[25:24] when a
read is issued to address location of Z2_GRABRAM2 in OTP.
Defines Zone 2's grab request of the lower addressed half of
CPU1TOCPU2MSGRAM0.
00 : Invalid. MSG RAM is inaccessible.
01 : Request to allocate MSG RAM to Zone2.
10 : No request for MSG RAM
11 : No request for MSG RAM when this zone is UNLOCKED. Else
MSG RAM is inaccessible if this zone is LOCKED.
Reset type: SYSRSn
23-22 GRAB_RAM11 R 0h Value in this field gets loaded from Z2_GRABRAM2[23:22] when a
read is issued to address location of Z2_GRABRAM2 in OTP.
Defines Zone 2's grab request of the higher addressed half of
CMTOCPU2MSGRAM0.
00 : Invalid. MSG RAM is inaccessible.
01 : Request to allocate MSG RAM to Zone2.
10 : No request for MSG RAM
11 : No request for MSG RAM when this zone is UNLOCKED. Else
MSG RAM is inaccessible if this zone is LOCKED.
Reset type: SYSRSn
21-20 GRAB_RAM10 R 0h Value in this field gets loaded from Z2_GRABRAM2[21:20] when a
read is issued to address location of Z2_GRABRAM2 in OTP.
Defines Zone 2's grab request of the lower addressed half of
CMTOCPU2MSGRAM0.
00 : Invalid. MSG RAM is inaccessible.
01 : Request to allocate MSG RAM to Zone2.
10 : No request for MSG RAM
11 : No request for MSG RAM when this zone is UNLOCKED. Else
MSG RAM is inaccessible if this zone is LOCKED.
Reset type: SYSRSn
19-18 GRAB_RAM9 R 0h Value in this field gets loaded from Z2_GRABRAM2[19:18] when a
read is issued to address location of Z2_GRABRAM2 in OTP.
Defines Zone 2's grab request of the higher addressed half of
CPU2TOCMMSGRAM0.
00 : Invalid. MSG RAM is inaccessible.
01 : Request to allocate MSG RAM to Zone2.
10 : No request for MSG RAM
11 : No request for MSG RAM when this zone is UNLOCKED. Else
MSG RAM is inaccessible if this zone is LOCKED.
Reset type: SYSRSn
17-16 GRAB_RAM8 R 0h Value in this field gets loaded from Z2_GRABRAM2[17:16] when a
read is issued to address location of Z2_GRABRAM2 in OTP.
Defines Zone 2's grab request of the lower addressed half of
CPU2TOCMMSGRAM0.
00 : Invalid. MSG RAM is inaccessible.
01 : Request to allocate MSG RAM to Zone2.
10 : No request for MSG RAM
11 : No request for MSG RAM when this zone is UNLOCKED. Else
MSG RAM is inaccessible if this zone is LOCKED.
Reset type: SYSRSn
15-14 GRAB_RAM7 R 0h Value in this field gets loaded from Z2_GRABRAM2[15:14] when a
read is issued to address location of Z2_GRABRAM2 in OTP.
Defines Zone 2's grab request of the higher addressed half of
CMTOCPU1MSGRAM0.
00 : Invalid. MSG RAM is inaccessible.
01 : Request to allocate MSG RAM to Zone2.
10 : No request for MSG RAM
11 : No request for MSG RAM when this zone is UNLOCKED. Else
MSG RAM is inaccessible if this zone is LOCKED.
Reset type: SYSRSn

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Table 6-56. Z2_GRABRAM2R Register Field Descriptions (continued)

Bit Field Type Reset Description
13-12 GRAB_RAM6 R 0h Value in this field gets loaded from Z2_GRABRAM2[13:12] when a
read is issued to address location of Z2_GRABRAM2 in OTP.
Defines Zone 2's grab request of the lower addressed half of
CMTOCPU1MSGRAM0.
00 : Invalid. MSG RAM is inaccessible.
01 : Request to allocate MSG RAM to Zone2.
10 : No request for MSG RAM
11 : No request for MSG RAM when this zone is UNLOCKED. Else
MSG RAM is inaccessible if this zone is LOCKED.
Reset type: SYSRSn
11-10 GRAB_RAM5 R 0h Value in this field gets loaded from Z2_GRABRAM2[11:10] when a
read is issued to address location of Z2_GRABRAM2 in OTP.
Defines Zone 2's grab request of the higher addressed half of
CPU1TOCMMSGRAM0.
00 : Invalid. MSG RAM is inaccessible.
01 : Request to allocate MSG RAM to Zone2.
10 : No request for MSG RAM
11 : No request for MSG RAM when this zone is UNLOCKED. Else
MSG RAM is inaccessible if this zone is LOCKED.
Reset type: SYSRSn
9-8 GRAB_RAM4 R 0h Value in this field gets loaded from Z2_GRABRAM2[9:8] when a read
is issued to address location of Z2_GRABRAM2 in OTP.
Defines Zone 2's grab request of the lower addressed half of
CPU1TOCMMSGRAM0.
00 : Invalid. MSG RAM is inaccessible.
01 : Request to allocate MSG RAM to Zone2.
10 : No request for MSG RAM
11 : No request for MSG RAM when this zone is UNLOCKED. Else
MSG RAM is inaccessible if this zone is LOCKED.
Reset type: SYSRSn
7-4 RESERVED R 0h Reserved
3-2 GRAB_RAM1 R 0h Value in this field gets loaded from Z2_GRABRAM2[3:2] when a read
is issued to address location of Z2_GRABRAM2 in OTP.
00 : Invalid. CM C1 RAM is inaccessible.
01 : Request to allocate CM C1 RAM to Zone2.
10 : No request for CM C1 RAM
11 : No request for CM C1 RAM when this zone is UNLOCKED. Else
CM C1 RAM is inaccessible if this zone is LOCKED.
Reset type: SYSRSn
1-0 GRAB_RAM0 R 0h Value in this field gets loaded from Z2_GRABRAM2[1:0] when a read
is issued to address location of Z2_GRABRAM2 in OTP.
00 : Invalid. CM C0 RAM is inaccessible.
01 : Request to allocate CM C0 RAM to Zone2.
10 : No request for CM C0 RAM
11 : No request for CM C0 RAM when this zone is UNLOCKED. Else
CM C0 RAM is inaccessible if this zone is LOCKED.
Reset type: SYSRSn

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6.9.4.18 Z2_GRABRAM3R Register (Offset (x8) = 48h, Offset (x16) = 24h) [Reset = 0h]
Z2_GRABRAM3R is shown in Figure 6-52 and described in Table 6-57.
Return to the Summary Table.
Zone 2 Grab RAM Status Register 3
Figure 6-52. Z2_GRABRAM3R Register
31 30 29 28 27 26 25 24
RESERVED
R-0h

23 22 21 20 19 18 17 16
RESERVED GRAB_RAM9 GRAB_RAM8
R-0h R-0h R-0h

15 14 13 12 11 10 9 8
GRAB_RAM7 GRAB_RAM6 GRAB_RAM5 GRAB_RAM4
R-0h R-0h R-0h R-0h

7 6 5 4 3 2 1 0
GRAB_RAM3 GRAB_RAM2 GRAB_RAM1 GRAB_RAM0
R-0h R-0h R-0h R-0h

Table 6-57. Z2_GRABRAM3R Register Field Descriptions

Bit Field Type Reset Description
31-20 RESERVED R 0h Reserved
19-18 GRAB_RAM9 R 0h Value in this field gets loaded from Z2_GRABRAM3[19:18] when a
read is issued to address location of Z2_GRABRAM3 in OTP.
00 : Invalid. CPU2 D1 RAM is inaccessible.
01 : Request to allocate CPU2 D1 RAM to Zone2.
10 : No request for CPU2 D1 RAM
11 : No request for CPU2 D1 RAM when this zone is UNLOCKED.
Else CPU2 D1 RAM is inaccessible if this zone is LOCKED.
Reset type: SYSRSn
17-16 GRAB_RAM8 R 0h Value in this field gets loaded from Z2_GRABRAM3[17:16] when a
read is issued to address location of Z2_GRABRAM3 in OTP.
00 : Invalid. CPU2 D0 RAM is inaccessible.
01 : Request to allocate CPU2 D0 RAM to Zone2.
10 : No request for CPU2 D0 RAM
11 : No request for CPU2 D0 RAM when this zone is UNLOCKED.
Else CPU2 D0 RAM is inaccessible if this zone is LOCKED.
Reset type: SYSRSn
15-14 GRAB_RAM7 R 0h Value in this field gets loaded from Z2_GRABRAM3[15:14] when a
read is issued to address location of Z2_GRABRAM3 in OTP.
00 : Invalid. CPU2 LS7 RAM is inaccessible.
01 : Request to allocate CPU2 LS7 RAM to Zone2.
10 : No request for CPU2 LS7 RAM
11 : No request for CPU2 LS7 RAM when this zone is UNLOCKED.
Else CPU2 LS7 RAM is inaccessible if this zone is LOCKED.
Reset type: SYSRSn
13-12 GRAB_RAM6 R 0h Value in this field gets loaded from Z2_GRABRAM3[13:12] when a
read is issued to address location of Z2_GRABRAM3 in OTP.
00 : Invalid. CPU2 LS6 RAM is inaccessible.
01 : Request to allocate CPU2 LS6 RAM to Zone2.
10 : No request for CPU2 LS6 RAM
11 : No request for CPU2 LS6 RAM when this zone is UNLOCKED.
Else CPU2 LS6 RAM is inaccessible if this zone is LOCKED.
Reset type: SYSRSn

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Table 6-57. Z2_GRABRAM3R Register Field Descriptions (continued)

Bit Field Type Reset Description
11-10 GRAB_RAM5 R 0h Value in this field gets loaded from Z2_GRABRAM3[11:10] when a
read is issued to address location of Z2_GRABRAM3 in OTP.
00 : Invalid. CPU2 LS5 RAM is inaccessible.
01 : Request to allocate CPU2 LS5 RAM to Zone2.
10 : No request for CPU2 LS5 RAM
11 : No request for CPU2 LS5 RAM when this zone is UNLOCKED.
Else CPU2 LS5 RAM is inaccessible if this zone is LOCKED.
Reset type: SYSRSn
9-8 GRAB_RAM4 R 0h Value in this field gets loaded from Z2_GRABRAM3[9:8] when a read
is issued to address location of Z2_GRABRAM3 in OTP.
00 : Invalid. CPU2 LS4 RAM is inaccessible.
01 : Request to allocate CPU2 LS4 RAM to Zone2.
10 : No request for CPU2 LS4 RAM
11 : No request for CPU2 LS4 RAM when this zone is UNLOCKED.
Else CPU2 LS4 RAM is inaccessible if this zone is LOCKED.
Reset type: SYSRSn
7-6 GRAB_RAM3 R 0h Value in this field gets loaded from Z2_GRABRAM3[7:6] when a read
is issued to address location of Z2_GRABRAM3 in OTP.
00 : Invalid. CPU2 LS3 RAM is inaccessible.
01 : Request to allocate CPU2 LS3 RAM to Zone2.
10 : No request for CPU2 LS3 RAM
11 : No request for CPU2 LS3 RAM when this zone is UNLOCKED.
Else CPU2 LS3 RAM is inaccessible if this zone is LOCKED.
Reset type: SYSRSn
5-4 GRAB_RAM2 R 0h Value in this field gets loaded from Z2_GRABRAM3[5:4] when a read
is issued to address location of Z2_GRABRAM3 in OTP.
00 : Invalid. CPU2 LS2 RAM is inaccessible.
01 : Request to allocate CPU2 LS2 RAM to Zone2.
10 : No request for CPU2 LS2 RAM
11 : No request for CPU2 LS2 RAM when this zone is UNLOCKED.
Else CPU2 LS2 RAM is inaccessible if this zone is LOCKED.
Reset type: SYSRSn
3-2 GRAB_RAM1 R 0h Value in this field gets loaded from Z2_GRABRAM3[3:2] when a read
is issued to address location of Z2_GRABRAM3 in OTP.
00 : Invalid. CPU2 LS1 RAM is inaccessible.
01 : Request to allocate CPU2 LS1 RAM to Zone2.
10 : No request for CPU2 LS1 RAM
11 : No request for CPU2 LS1 RAM when this zone is UNLOCKED.
Else CPU2 LS1 RAM is inaccessible if this zone is LOCKED.
Reset type: SYSRSn
1-0 GRAB_RAM0 R 0h Value in this field gets loaded from Z2_GRABRAM3[1:0] when a read
is issued to address location of Z2_GRABRAM3 in OTP.
00 : Invalid. CPU2 LS0 RAM is inaccessible.
01 : Request to allocate CPU2 LS0 RAM to Zone2.
10 : No request for CPU2 LS0 RAM
11 : No request for CPU2 LS0 RAM when this zone is UNLOCKED.
Else CPU2 LS0 RAM is inaccessible if this zone is LOCKED.
Reset type: SYSRSn

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6.9.4.19 Z2_EXEONLYSECT1R Register (Offset (x8) = 4Ch, Offset (x16) = 26h) [Reset = 0h]
Z2_EXEONLYSECT1R is shown in Figure 6-53 and described in Table 6-58.
Return to the Summary Table.
Zone 2 Execute Only Flash Status Register 1
Figure 6-53. Z2_EXEONLYSECT1R Register
31 30 29 28 27 26 25 24
RESERVED EXEONLY_CM EXEONLY_CM EXEONLY_CM EXEONLY_CM EXEONLY_CM EXEONLY_CM
_SECT13 _SECT12 _SECT11 _SECT10 _SECT9 _SECT8
R-0h R-0h R-0h R-0h R-0h R-0h R-0h

23 22 21 20 19 18 17 16
EXEONLY_CM EXEONLY_CM EXEONLY_CM EXEONLY_CM EXEONLY_CM EXEONLY_CM EXEONLY_CM EXEONLY_CM
_SECT7 _SECT6 _SECT5 _SECT4 _SECT3 _SECT2 _SECT1 _SECT0
R-0h R-0h R-0h R-0h R-0h R-0h R-0h R-0h

15 14 13 12 11 10 9 8
RESERVED EXEONLY_CP EXEONLY_CP EXEONLY_CP EXEONLY_CP EXEONLY_CP EXEONLY_CP
U1_SECT13 U1_SECT12 U1_SECT11 U1_SECT10 U1_SECT9 U1_SECT8
R-0h R-0h R-0h R-0h R-0h R-0h R-0h

7 6 5 4 3 2 1 0
EXEONLY_CP EXEONLY_CP EXEONLY_CP EXEONLY_CP EXEONLY_CP EXEONLY_CP EXEONLY_CP EXEONLY_CP
U1_SECT7 U1_SECT6 U1_SECT5 U1_SECT4 U1_SECT3 U1_SECT2 U1_SECT1 U1_SECT0
R-0h R-0h R-0h R-0h R-0h R-0h R-0h R-0h

Table 6-58. Z2_EXEONLYSECT1R Register Field Descriptions

Bit Field Type Reset Description
31-30 RESERVED R 0h Reserved
29 EXEONLY_CM_SECT13 R 0h Value in this field gets loaded from Z2_EXEONLYSECT1[29] when a
read is issued to Z2_EXEONLYSECT1 address location in OTP.
0 : Execute-Only protection is enabled for CM Flash Sector 13 (only
if it's allocated to Zone2)
1 : Execute-Only protection is disabled for CM Flash Sector 13 (only
if it's allocated to Zone2)
Reset type: SYSRSn
28 EXEONLY_CM_SECT12 R 0h Value in this field gets loaded from Z2_EXEONLYSECT1[28] when a
read is issued to Z2_EXEONLYSECT1 address location in OTP.
0 : Execute-Only protection is enabled for CM Flash Sector 12 (only
if it's allocated to Zone2)
1 : Execute-Only protection is disabled for CM Flash Sector 12 (only
if it's allocated to Zone2)
Reset type: SYSRSn
27 EXEONLY_CM_SECT11 R 0h Value in this field gets loaded from Z2_EXEONLYSECT1[27] when a
read is issued to Z2_EXEONLYSECT1 address location in OTP.
0 : Execute-Only protection is enabled for CM Flash Sector 11 (only if
it's allocated to Zone2)
1 : Execute-Only protection is disabled for CM Flash Sector 11 (only
if it's allocated to Zone2)
Reset type: SYSRSn
26 EXEONLY_CM_SECT10 R 0h Value in this field gets loaded from Z2_EXEONLYSECT1[26] when a
read is issued to Z2_EXEONLYSECT1 address location in OTP.
0 : Execute-Only protection is enabled for CM Flash Sector 10 (only
if it's allocated to Zone2)
1 : Execute-Only protection is disabled for CM Flash Sector 10 (only
if it's allocated to Zone2)
Reset type: SYSRSn

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Table 6-58. Z2_EXEONLYSECT1R Register Field Descriptions (continued)

Bit Field Type Reset Description
25 EXEONLY_CM_SECT9 R 0h Value in this field gets loaded from Z2_EXEONLYSECT1[25] when a
read is issued to Z2_EXEONLYSECT1 address location in OTP.
0 : Execute-Only protection is enabled for CM Flash Sector 9 (only if
it's allocated to Zone2)
1 : Execute-Only protection is disabled for CM Flash Sector 9 (only if
it's allocated to Zone2)
Reset type: SYSRSn
24 EXEONLY_CM_SECT8 R 0h Value in this field gets loaded from Z2_EXEONLYSECT1[24] when a
read is issued to Z2_EXEONLYSECT1 address location in OTP.
0 : Execute-Only protection is enabled for CM Flash Sector 8 (only if
it's allocated to Zone2)
1 : Execute-Only protection is disabled for CM Flash Sector 8 (only if
it's allocated to Zone2)
Reset type: SYSRSn
23 EXEONLY_CM_SECT7 R 0h Value in this field gets loaded from Z2_EXEONLYSECT1[23] when a
read is issued to Z2_EXEONLYSECT1 address location in OTP.
0 : Execute-Only protection is enabled for CM Flash Sector 7 (only if
it's allocated to Zone2)
1 : Execute-Only protection is disabled for CM Flash Sector 7 (only if
it's allocated to Zone2)
Reset type: SYSRSn
22 EXEONLY_CM_SECT6 R 0h Value in this field gets loaded from Z2_EXEONLYSECT1[22] when a
read is issued to Z2_EXEONLYSECT1 address location in OTP.
0 : Execute-Only protection is enabled for CM Flash Sector 6 (only if
it's allocated to Zone2)
1 : Execute-Only protection is disabled for CM Flash Sector 6 (only if
it's allocated to Zone2)
Reset type: SYSRSn
21 EXEONLY_CM_SECT5 R 0h Value in this field gets loaded from Z2_EXEONLYSECT1[21] when a
read is issued to Z2_EXEONLYSECT1 address location in OTP.
0 : Execute-Only protection is enabled for CM Flash Sector 5 (only if
it's allocated to Zone2)
1 : Execute-Only protection is disabled for CM Flash Sector 5 (only if
it's allocated to Zone2)
Reset type: SYSRSn
20 EXEONLY_CM_SECT4 R 0h Value in this field gets loaded from Z2_EXEONLYSECT1[20] when a
read is issued to Z2_EXEONLYSECT1 address location in OTP.
0 : Execute-Only protection is enabled for CM Flash Sector 4 (only if
it's allocated to Zone2)
1 : Execute-Only protection is disabled for CM Flash Sector 4 (only if
it's allocated to Zone2)
Reset type: SYSRSn
19 EXEONLY_CM_SECT3 R 0h Value in this field gets loaded from Z2_EXEONLYSECT1[19] when a
read is issued to Z2_EXEONLYSECT1 address location in OTP.
0 : Execute-Only protection is enabled for CM Flash Sector 3 (only if
it's allocated to Zone2)
1 : Execute-Only protection is disabled for CM Flash Sector 3 (only if
it's allocated to Zone2)
Reset type: SYSRSn
18 EXEONLY_CM_SECT2 R 0h Value in this field gets loaded from Z2_EXEONLYSECT1[18] when a
read is issued to Z2_EXEONLYSECT1 address location in OTP.
0 : Execute-Only protection is enabled for CM Flash Sector 2 (only if
it's allocated to Zone2)
1 : Execute-Only protection is disabled for CM Flash Sector 2 (only if
it's allocated to Zone2)
Reset type: SYSRSn

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Table 6-58. Z2_EXEONLYSECT1R Register Field Descriptions (continued)

Bit Field Type Reset Description
17 EXEONLY_CM_SECT1 R 0h Value in this field gets loaded from Z2_EXEONLYSECT1[17] when a
read is issued to Z2_EXEONLYSECT1 address location in OTP.
0 : Execute-Only protection is enabled for CM Flash Sector 1 (only if
it's allocated to Zone2)
1 : Execute-Only protection is disabled for CM Flash Sector 1 (only if
it's allocated to Zone2)
Reset type: SYSRSn
16 EXEONLY_CM_SECT0 R 0h Value in this field gets loaded from Z2_EXEONLYSECT1[16] when a
read is issued to Z2_EXEONLYSECT1 address location in OTP.
0 : Execute-Only protection is enabled for CM Flash Sector 0 (only if
it's allocated to Zone2)
1 : Execute-Only protection is disabled for CM Flash Sector 0 (only if
it's allocated to Zone2)
Reset type: SYSRSn
15-14 RESERVED R 0h Reserved
13 EXEONLY_CPU1_SECT1 R 0h Value in this field gets loaded from Z2_EXEONLYSECT1[13] when a
3 read is issued to Z2_EXEONLYSECT1 address location in OTP.
0 : Execute-Only protection is enabled for CPU1 Flash Sector 13
(only if it's allocated to Zone2)
1 : Execute-Only protection is disabled for CPU1 Flash Sector 13
(only if it's allocated to Zone2)
Reset type: SYSRSn
12 EXEONLY_CPU1_SECT1 R 0h Value in this field gets loaded from Z2_EXEONLYSECT1[12] when a
2 read is issued to Z2_EXEONLYSECT1 address location in OTP.
0 : Execute-Only protection is enabled for CPU1 Flash Sector 12
(only if it's allocated to Zone2)
1 : Execute-Only protection is disabled for CPU1 Flash Sector 12
(only if it's allocated to Zone2)
Reset type: SYSRSn
11 EXEONLY_CPU1_SECT1 R 0h Value in this field gets loaded from Z2_EXEONLYSECT1[11] when a
1 read is issued to Z2_EXEONLYSECT1 address location in OTP.
0 : Execute-Only protection is enabled for CPU1 Flash Sector 11
(only if it's allocated to Zone2)
1 : Execute-Only protection is disabled for CPU1 Flash Sector 11
(only if it's allocated to Zone2)
Reset type: SYSRSn
10 EXEONLY_CPU1_SECT1 R 0h Value in this field gets loaded from Z2_EXEONLYSECT1[10] when a
0 read is issued to Z2_EXEONLYSECT1 address location in OTP.
0 : Execute-Only protection is enabled for CPU1 Flash Sector 10
(only if it's allocated to Zone2)
1 : Execute-Only protection is disabled for CPU1 Flash Sector 10
(only if it's allocated to Zone2)
Reset type: SYSRSn
9 EXEONLY_CPU1_SECT9 R 0h Value in this field gets loaded from Z2_EXEONLYSECT1[9] when a
read is issued to Z2_EXEONLYSECT1 address location in OTP.
0 : Execute-Only protection is enabled for CPU1 Flash Sector 9 (only
if it's allocated to Zone2)
1 : Execute-Only protection is disabled for CPU1 Flash Sector 9
(only if it's allocated to Zone2)
Reset type: SYSRSn
8 EXEONLY_CPU1_SECT8 R 0h Value in this field gets loaded from Z2_EXEONLYSECT1[8] when a
read is issued to Z2_EXEONLYSECT1 address location in OTP.
0 : Execute-Only protection is enabled for CPU1 Flash Sector 8 (only
if it's allocated to Zone2)
1 : Execute-Only protection is disabled for CPU1 Flash Sector 8
(only if it's allocated to Zone2)
Reset type: SYSRSn

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Table 6-58. Z2_EXEONLYSECT1R Register Field Descriptions (continued)

Bit Field Type Reset Description
7 EXEONLY_CPU1_SECT7 R 0h Value in this field gets loaded from Z2_EXEONLYSECT1[7] when a
read is issued to Z2_EXEONLYSECT1 address location in OTP.
0 : Execute-Only protection is enabled for CPU1 Flash Sector 7 (only
if it's allocated to Zone2)
1 : Execute-Only protection is disabled for CPU1 Flash Sector 7
(only if it's allocated to Zone2)
Reset type: SYSRSn
6 EXEONLY_CPU1_SECT6 R 0h Value in this field gets loaded from Z2_EXEONLYSECT1[6] when a
read is issued to Z2_EXEONLYSECT1 address location in OTP.
0 : Execute-Only protection is enabled for CPU1 Flash Sector 6 (only
if it's allocated to Zone2)
1 : Execute-Only protection is disabled for CPU1 Flash Sector 6
(only if it's allocated to Zone2)
Reset type: SYSRSn
5 EXEONLY_CPU1_SECT5 R 0h Value in this field gets loaded from Z2_EXEONLYSECT1[5] when a
read is issued to Z2_EXEONLYSECT1 address location in OTP.
0 : Execute-Only protection is enabled for CPU1 Flash Sector 5 (only
if it's allocated to Zone2)
1 : Execute-Only protection is disabled for CPU1 Flash Sector 5
(only if it's allocated to Zone2)
Reset type: SYSRSn
4 EXEONLY_CPU1_SECT4 R 0h Value in this field gets loaded from Z2_EXEONLYSECT1[4] when a
read is issued to Z2_EXEONLYSECT1 address location in OTP.
0 : Execute-Only protection is enabled for CPU1 Flash Sector 4 (only
if it's allocated to Zone2)
1 : Execute-Only protection is disabled for CPU1 Flash Sector 4
(only if it's allocated to Zone2)
Reset type: SYSRSn
3 EXEONLY_CPU1_SECT3 R 0h Value in this field gets loaded from Z2_EXEONLYSECT1[3] when a
read is issued to Z2_EXEONLYSECT1 address location in OTP.
0 : Execute-Only protection is enabled for CPU1 Flash Sector 3 (only
if it's allocated to Zone2)
1 : Execute-Only protection is disabled for CPU1 Flash Sector 3
(only if it's allocated to Zone2)
Reset type: SYSRSn
2 EXEONLY_CPU1_SECT2 R 0h Value in this field gets loaded from Z2_EXEONLYSECT1[2] when a
read is issued to Z2_EXEONLYSECT1 address location in OTP.
0 : Execute-Only protection is enabled for CPU1 Flash Sector 2 (only
if it's allocated to Zone2)
1 : Execute-Only protection is disabled for CPU1 Flash Sector 2
(only if it's allocated to Zone2)
Reset type: SYSRSn
1 EXEONLY_CPU1_SECT1 R 0h Value in this field gets loaded from Z2_EXEONLYSECT1[1] when a
read is issued to Z2_EXEONLYSECT1 address location in OTP.
0 : Execute-Only protection is enabled for CPU1 Flash Sector 1 (only
if it's allocated to Zone2)
1 : Execute-Only protection is disabled for CPU1 Flash Sector 1
(only if it's allocated to Zone2)
Reset type: SYSRSn
0 EXEONLY_CPU1_SECT0 R 0h Value in this field gets loaded from Z2_EXEONLYSECT1[0] when a
read is issued to Z2_EXEONLYSECT1 address location in OTP.
0 : Execute-Only protection is enabled for CPU1 Flash Sector 0 (only
if it's allocated to Zone2)
1 : Execute-Only protection is disabled for CPU1 Flash Sector 0
(only if it's allocated to Zone2)
Reset type: SYSRSn

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6.9.4.20 Z2_EXEONLYSECT2R Register (Offset (x8) = 50h, Offset (x16) = 28h) [Reset = 0h]
Z2_EXEONLYSECT2R is shown in Figure 6-54 and described in Table 6-59.
Return to the Summary Table.
Zone 2 Execute Only Flash Status Register 2
Figure 6-54. Z2_EXEONLYSECT2R Register
31 30 29 28 27 26 25 24
RESERVED
R-0h

23 22 21 20 19 18 17 16
RESERVED
R-0h

15 14 13 12 11 10 9 8
RESERVED EXEONLY_CP EXEONLY_CP EXEONLY_CP EXEONLY_CP EXEONLY_CP EXEONLY_CP
U2_SECT13 U2_SECT12 U2_SECT11 U2_SECT10 U2_SECT9 U2_SECT8
R-0h R-0h R-0h R-0h R-0h R-0h R-0h

7 6 5 4 3 2 1 0
EXEONLY_CP EXEONLY_CP EXEONLY_CP EXEONLY_CP EXEONLY_CP EXEONLY_CP EXEONLY_CP EXEONLY_CP
U2_SECT7 U2_SECT6 U2_SECT5 U2_SECT4 U2_SECT3 U2_SECT2 U2_SECT1 U2_SECT0
R-0h R-0h R-0h R-0h R-0h R-0h R-0h R-0h

Table 6-59. Z2_EXEONLYSECT2R Register Field Descriptions

Bit Field Type Reset Description
31-14 RESERVED R 0h Reserved
13 EXEONLY_CPU2_SECT1 R 0h Value in this field gets loaded from Z2_EXEONLYSECT2[13] when a
3 read is issued to Z2_EXEONLYSECT2 address location in OTP.
0 : Execute-Only protection is enabled for CPU2 Flash Sector 13
(only if it's allocated to Zone2)
1 : Execute-Only protection is disabled for CPU2 Flash Sector 13
(only if it's allocated to Zone2)
Reset type: SYSRSn
12 EXEONLY_CPU2_SECT1 R 0h Value in this field gets loaded from Z2_EXEONLYSECT2[12] when a
2 read is issued to Z2_EXEONLYSECT2 address location in OTP.
0 : Execute-Only protection is enabled for CPU2 Flash Sector 12
(only if it's allocated to Zone2)
1 : Execute-Only protection is disabled for CPU2 Flash Sector 12
(only if it's allocated to Zone2)
Reset type: SYSRSn
11 EXEONLY_CPU2_SECT1 R 0h Value in this field gets loaded from Z2_EXEONLYSECT2[11] when a
1 read is issued to Z2_EXEONLYSECT2 address location in OTP.
0 : Execute-Only protection is enabled for CPU2 Flash Sector 11
(only if it's allocated to Zone2)
1 : Execute-Only protection is disabled for CPU2 Flash Sector 11
(only if it's allocated to Zone2)
Reset type: SYSRSn
10 EXEONLY_CPU2_SECT1 R 0h Value in this field gets loaded from Z2_EXEONLYSECT2[10] when a
0 read is issued to Z2_EXEONLYSECT2 address location in OTP.
0 : Execute-Only protection is enabled for CPU2 Flash Sector 10
(only if it's allocated to Zone2)
1 : Execute-Only protection is disabled for CPU2 Flash Sector 10
(only if it's allocated to Zone2)
Reset type: SYSRSn

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Table 6-59. Z2_EXEONLYSECT2R Register Field Descriptions (continued)

Bit Field Type Reset Description
9 EXEONLY_CPU2_SECT9 R 0h Value in this field gets loaded from Z2_EXEONLYSECT2[9] when a
read is issued to Z2_EXEONLYSECT2 address location in OTP.
0 : Execute-Only protection is enabled for CPU2 Flash Sector 9 (only
if it's allocated to Zone2)
1 : Execute-Only protection is disabled for CPU2 Flash Sector 9
(only if it's allocated to Zone2)
Reset type: SYSRSn
8 EXEONLY_CPU2_SECT8 R 0h Value in this field gets loaded from Z2_EXEONLYSECT2[8] when a
read is issued to Z2_EXEONLYSECT2 address location in OTP.
0 : Execute-Only protection is enabled for CPU2 Flash Sector 8 (only
if it's allocated to Zone2)
1 : Execute-Only protection is disabled for CPU2 Flash Sector 8
(only if it's allocated to Zone2)
Reset type: SYSRSn
7 EXEONLY_CPU2_SECT7 R 0h Value in this field gets loaded from Z2_EXEONLYSECT2[7] when a
read is issued to Z2_EXEONLYSECT2 address location in OTP.
0 : Execute-Only protection is enabled for CPU2 Flash Sector 7 (only
if it's allocated to Zone2)
1 : Execute-Only protection is disabled for CPU2 Flash Sector 7
(only if it's allocated to Zone2)
Reset type: SYSRSn
6 EXEONLY_CPU2_SECT6 R 0h Value in this field gets loaded from Z2_EXEONLYSECT2[6] when a
read is issued to Z2_EXEONLYSECT2 address location in OTP.
0 : Execute-Only protection is enabled for CPU2 Flash Sector 6 (only
if it's allocated to Zone2)
1 : Execute-Only protection is disabled for CPU2 Flash Sector 6
(only if it's allocated to Zone2)
Reset type: SYSRSn
5 EXEONLY_CPU2_SECT5 R 0h Value in this field gets loaded from Z2_EXEONLYSECT2[5] when a
read is issued to Z2_EXEONLYSECT2 address location in OTP.
0 : Execute-Only protection is enabled for CPU2 Flash Sector 5 (only
if it's allocated to Zone2)
1 : Execute-Only protection is disabled for CPU2 Flash Sector 5
(only if it's allocated to Zone2)
Reset type: SYSRSn
4 EXEONLY_CPU2_SECT4 R 0h Value in this field gets loaded from Z2_EXEONLYSECT2[4] when a
read is issued to Z2_EXEONLYSECT2 address location in OTP.
0 : Execute-Only protection is enabled for CPU2 Flash Sector 4 (only
if it's allocated to Zone2)
1 : Execute-Only protection is disabled for CPU2 Flash Sector 4
(only if it's allocated to Zone2)
Reset type: SYSRSn
3 EXEONLY_CPU2_SECT3 R 0h Value in this field gets loaded from Z2_EXEONLYSECT2[3] when a
read is issued to Z2_EXEONLYSECT2 address location in OTP.
0 : Execute-Only protection is enabled for CPU2 Flash Sector 3 (only
if it's allocated to Zone2)
1 : Execute-Only protection is disabled for CPU2 Flash Sector 3
(only if it's allocated to Zone2)
Reset type: SYSRSn
2 EXEONLY_CPU2_SECT2 R 0h Value in this field gets loaded from Z2_EXEONLYSECT2[2] when a
read is issued to Z2_EXEONLYSECT2 address location in OTP.
0 : Execute-Only protection is enabled for CPU2 Flash Sector 2 (only
if it's allocated to Zone2)
1 : Execute-Only protection is disabled for CPU2 Flash Sector 2
(only if it's allocated to Zone2)
Reset type: SYSRSn

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Table 6-59. Z2_EXEONLYSECT2R Register Field Descriptions (continued)

Bit Field Type Reset Description
1 EXEONLY_CPU2_SECT1 R 0h Value in this field gets loaded from Z2_EXEONLYSECT2[1] when a
read is issued to Z2_EXEONLYSECT2 address location in OTP.
0 : Execute-Only protection is enabled for CPU2 Flash Sector 1 (only
if it's allocated to Zone2)
1 : Execute-Only protection is disabled for CPU2 Flash Sector 1
(only if it's allocated to Zone2)
Reset type: SYSRSn
0 EXEONLY_CPU2_SECT0 R 0h Value in this field gets loaded from Z2_EXEONLYSECT2[0] when a
read is issued to Z2_EXEONLYSECT2 address location in OTP.
0 : Execute-Only protection is enabled for CPU2 Flash Sector 0 (only
if it's allocated to Zone2)
1 : Execute-Only protection is disabled for CPU2 Flash Sector 0
(only if it's allocated to Zone2)
Reset type: SYSRSn

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6.9.4.21 Z2_EXEONLYRAM1R Register (Offset (x8) = 54h, Offset (x16) = 2Ah) [Reset = 0h]
Z2_EXEONLYRAM1R is shown in Figure 6-55 and described in Table 6-60.
Return to the Summary Table.
Zone 2 Execute Only RAM Status Register 1
Figure 6-55. Z2_EXEONLYRAM1R Register
31 30 29 28 27 26 25 24
EXEONLY_RA EXEONLY_RA EXEONLY_RA EXEONLY_RA EXEONLY_RA EXEONLY_RA EXEONLY_RA EXEONLY_RA
M31 M30 M29 M28 M27 M26 M25 M24
R-0h R-0h R-0h R-0h R-0h R-0h R-0h R-0h

23 22 21 20 19 18 17 16
EXEONLY_RA EXEONLY_RA RESERVED EXEONLY_RA EXEONLY_RA
M23 M22 M17 M16
R-0h R-0h R-0h R-0h R-0h

15 14 13 12 11 10 9 8
RESERVED EXEONLY_RA EXEONLY_RA
M9 M8
R-0h R-0h R-0h

7 6 5 4 3 2 1 0
EXEONLY_RA EXEONLY_RA EXEONLY_RA EXEONLY_RA EXEONLY_RA EXEONLY_RA EXEONLY_RA EXEONLY_RA
M7 M6 M5 M4 M3 M2 M1 M0
R-0h R-0h R-0h R-0h R-0h R-0h R-0h R-0h

Table 6-60. Z2_EXEONLYRAM1R Register Field Descriptions

Bit Field Type Reset Description
31 EXEONLY_RAM31 R 0h Value in this field gets loaded from Z2_EXEONLYRAM1[31] when a
read is issued to Z2_EXEONLYRAM address location in OTP.
0 : Execute-Only protection is enabled for CPU2 LS0 RAM (only if it's
allocated to Zone2)
1 : Execute-Only protection is disabled for CPU2 LS0 RAM (only if
it's allocated to Zone2)
Reset type: SYSRSn
30 EXEONLY_RAM30 R 0h Value in this field gets loaded from Z2_EXEONLYRAM1[30] when a
read is issued to Z2_EXEONLYRAM address location in OTP.
0 : Execute-Only protection is enabled for CPU2 LS1 RAM (only if it's
allocated to Zone2)
1 : Execute-Only protection is disabled for CPU2 LS1 RAM (only if
it's allocated to Zone2)
Reset type: SYSRSn
29 EXEONLY_RAM29 R 0h Value in this field gets loaded from Z2_EXEONLYRAM1[29] when a
read is issued to Z2_EXEONLYRAM address location in OTP.
0 : Execute-Only protection is enabled for CPU2 LS2 RAM (only if it's
allocated to Zone2)
1 : Execute-Only protection is disabled for CPU2 LS2 RAM (only if
it's allocated to Zone2)
Reset type: SYSRSn
28 EXEONLY_RAM28 R 0h Value in this field gets loaded from Z2_EXEONLYRAM1[28] when a
read is issued to Z2_EXEONLYRAM1 address location in OTP.
0 : Execute-Only protection is enabled for CPU2 LS3 RAM (only if it's
allocated to Zone2)
1 : Execute-Only protection is disabled for CPU2 LS3 RAM (only if
it's allocated to Zone2)
Reset type: SYSRSn

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Table 6-60. Z2_EXEONLYRAM1R Register Field Descriptions (continued)

Bit Field Type Reset Description
27 EXEONLY_RAM27 R 0h Value in this field gets loaded from Z2_EXEONLYRAM1[27] when a
read is issued to Z2_EXEONLYRAM1 address location in OTP.
0 : Execute-Only protection is enabled for CPU2 LS4 RAM (only if it's
allocated to Zone2)
1 : Execute-Only protection is disabled for CPU2 LS4 RAM (only if
it's allocated to Zone2)
Reset type: SYSRSn
26 EXEONLY_RAM26 R 0h Value in this field gets loaded from Z2_EXEONLYRAM1[26] when a
read is issued to Z2_EXEONLYRAM1 address location in OTP.
0 : Execute-Only protection is enabled for CPU2 LS5 RAM (only if it's
allocated to Zone2)
1 : Execute-Only protection is disabled for CPU2 LS5 RAM (only if
it's allocated to Zone2)
Reset type: SYSRSn
25 EXEONLY_RAM25 R 0h Value in this field gets loaded from Z2_EXEONLYRAM1[25] when a
read is issued to Z2_EXEONLYRAM1 address location in OTP.
0 : Execute-Only protection is enabled for CPU2 LS6 RAM (only if it's
allocated to Zone2)
1 : Execute-Only protection is disabled for CPU2 LS6 RAM (only if
it's allocated to Zone2)
Reset type: SYSRSn
24 EXEONLY_RAM24 R 0h Value in this field gets loaded from Z2_EXEONLYRAM1[24] when a
read is issued to Z2_EXEONLYRAM1 address location in OTP.
0 : Execute-Only protection is enabled for CPU2 LS7 RAM (only if it's
allocated to Zone2)
1 : Execute-Only protection is disabled for CPU2 LS7 RAM (only if
it's allocated to Zone2)
Reset type: SYSRSn
23 EXEONLY_RAM23 R 0h Value in this field gets loaded from Z2_EXEONLYRAM1[23] when a
read is issued to Z2_EXEONLYRAM address location in OTP.
0 : Execute-Only protection is enabled for CPU2 D0 RAM (only if it's
allocated to Zone2)
1 : Execute-Only protection is disabled for CPU2 D0 RAM (only if it's
allocated to Zone2)
Reset type: SYSRSn
22 EXEONLY_RAM22 R 0h Value in this field gets loaded from Z2_EXEONLYRAM1[22] when a
read is issued to Z2_EXEONLYRAM address location in OTP.
0 : Execute-Only protection is enabled for CPU2 D1 RAM (only if it's
allocated to Zone2)
1 : Execute-Only protection is disabled for CPU2 D1 RAM (only if it's
allocated to Zone2)
Reset type: SYSRSn
21-18 RESERVED R 0h Reserved
17 EXEONLY_RAM17 R 0h Value in this field gets loaded from Z2_EXEONLYRAM1[17] when a
read is issued to Z2_EXEONLYRAM address location in OTP.
0 : Execute-Only protection is enabled for CM C1 RAM (only if it's
allocated to Zone2)
1 : Execute-Only protection is disabled for CM C1 RAM (only if it's
allocated to Zone2)
Reset type: SYSRSn
16 EXEONLY_RAM16 R 0h Value in this field gets loaded from Z2_EXEONLYRAM1[16] when a
read is issued to Z2_EXEONLYRAM address location in OTP.
0 : Execute-Only protection is enabled for CM C0 RAM (only if it's
allocated to Zone2)
1 : Execute-Only protection is disabled for CM C0 RAM (only if it's
allocated to Zone2)
Reset type: SYSRSn
15-10 RESERVED R 0h Reserved

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Table 6-60. Z2_EXEONLYRAM1R Register Field Descriptions (continued)

Bit Field Type Reset Description
9 EXEONLY_RAM9 R 0h Value in this field gets loaded from Z2_EXEONLYRAM1[9] when a
read is issued to Z2_EXEONLYRAM address location in OTP.
0 : Execute-Only protection is enabled for CPU1 D1 RAM (only if it's
allocated to Zone2)
1 : Execute-Only protection is disabled for CPU1 D1 RAM (only if it's
allocated to Zone2)
Reset type: SYSRSn
8 EXEONLY_RAM8 R 0h Value in this field gets loaded from Z2_EXEONLYRAM1[8] when a
read is issued to Z2_EXEONLYRAM address location in OTP.
0 : Execute-Only protection is enabled for CPU1 D0 RAM (only if it's
allocated to Zone2)
1 : Execute-Only protection is disabled for CPU1 D0 RAM (only if it's
allocated to Zone2)
Reset type: SYSRSn
7 EXEONLY_RAM7 R 0h Value in this field gets loaded from Z2_EXEONLYRAM1[7] when a
read is issued to Z2_EXEONLYRAM address location in OTP.
0 : Execute-Only protection is enabled for CPU1 LS7 RAM (only if it's
allocated to Zone2)
1 : Execute-Only protection is disabled for CPU1 LS7 RAM (only if
it's allocated to Zone2)
Reset type: SYSRSn
6 EXEONLY_RAM6 R 0h Value in this field gets loaded from Z2_EXEONLYRAM1[6] when a
read is issued to Z2_EXEONLYRAM1 address location in OTP.
0 : Execute-Only protection is enabled for CPU1 LS6 RAM (only if it's
allocated to Zone2)
1 : Execute-Only protection is disabled for CPU1 LS6 RAM (only if
it's allocated to Zone2)
Reset type: SYSRSn
5 EXEONLY_RAM5 R 0h Value in this field gets loaded from Z2_EXEONLYRAM1[5] when a
read is issued to Z2_EXEONLYRAM1 address location in OTP.
0 : Execute-Only protection is enabled for CPU1 LS5 RAM (only if it's
allocated to Zone2)
1 : Execute-Only protection is disabled for CPU1 LS5 RAM (only if
it's allocated to Zone2)
Reset type: SYSRSn
4 EXEONLY_RAM4 R 0h Value in this field gets loaded from Z2_EXEONLYRAM1[4] when a
read is issued to Z2_EXEONLYRAM1 address location in OTP.
0 : Execute-Only protection is enabled for CPU1 LS4 RAM (only if it's
allocated to Zone2)
1 : Execute-Only protection is disabled for CPU1 LS4 RAM (only if
it's allocated to Zone2)
Reset type: SYSRSn
3 EXEONLY_RAM3 R 0h Value in this field gets loaded from Z2_EXEONLYRAM1[3] when a
read is issued to Z2_EXEONLYRAM1 address location in OTP.
0 : Execute-Only protection is enabled for CPU1 LS3 RAM (only if it's
allocated to Zone2)
1 : Execute-Only protection is disabled for CPU1 LS3 RAM (only if
it's allocated to Zone2)
Reset type: SYSRSn
2 EXEONLY_RAM2 R 0h Value in this field gets loaded from Z2_EXEONLYRAM1[2] when a
read is issued to Z2_EXEONLYRAM1 address location in OTP.
0 : Execute-Only protection is enabled for CPU1 LS2 RAM (only if it's
allocated to Zone2)
1 : Execute-Only protection is disabled for CPU1 LS2 RAM (only if
it's allocated to Zone2)
Reset type: SYSRSn

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Table 6-60. Z2_EXEONLYRAM1R Register Field Descriptions (continued)

Bit Field Type Reset Description
1 EXEONLY_RAM1 R 0h Value in this field gets loaded from Z2_EXEONLYRAM1[1] when a
read is issued to Z2_EXEONLYRAM1 address location in OTP.
0 : Execute-Only protection is enabled for CPU1 LS1 RAM (only if it's
allocated to Zone2)
1 : Execute-Only protection is disabled for CPU1 LS1 RAM (only if
it's allocated to Zone2)
Reset type: SYSRSn
0 EXEONLY_RAM0 R 0h Value in this field gets loaded from Z2_EXEONLYRAM1[0] when a
read is issued to Z2_EXEONLYRAM1 address location in OTP.
0 : Execute-Only protection is enabled for CPU1 LS0 RAM (only if it's
allocated to Zone2)
1 : Execute-Only protection is disabled for CPU1 LS0 RAM (only if
it's allocated to Zone2)
Reset type: SYSRSn

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6.9.5 DCSM_COMMON_REGS Registers

Table 6-61 lists the memory-mapped registers for the DCSM_COMMON_REGS registers. All register offset
addresses not listed in Table 6-61 should be considered as reserved locations and the register contents should
not be modified.
Table 6-61. DCSM_COMMON_REGS Registers
Offset Offset Acronym Register Name Write Section
(x8) (x16) Protection
0h 0h FLSEM Flash Wrapper Semaphore Register EALLOW Go
10h 8h SECTSTAT1 Flash Sectors Status Register 1 Go
14h Ah SECTSTAT2 Flash Sectors Status Register 2 Go
18h Ch SECTSTAT3 Flash Sectors Status Register 3 Go
20h 10h RAMSTAT1 RAM Status Register 1 Go
24h 12h RAMSTAT2 RAM Status Register 2 Go
28h 14h RAMSTAT3 RAM Status Register 3 Go
30h 18h SECERRSTAT Security Error Status Register Go
34h 1Ah SECERRCLR Security Error Clear Register Go
38h 1Ch SECERRFRC Security Error Force Register Go

Complex bit access types are encoded to fit into small table cells. Table 6-62 shows the codes that are used for
access types in this section.
Table 6-62. DCSM_COMMON_REGS Access Type
Codes
Access Type Code Description
Read Type
R R Read
R-0 R Read
-0 Returns 0s
Write Type
W W Write
W1S W Write
1S 1 to set
Reset or Default Value
-n Value after reset or the default
value
Register Array Variables
i,j,k,l,m,n When these variables are used in
a register name, an offset, or an
address, they refer to the value of
a register array where the register
is part of a group of repeating
registers. The register groups
form a hierarchical structure and
the array is represented with a
formula.
y When this variable is used in a
register name, an offset, or an
address it refers to the value of
a register array.

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6.9.5.1 FLSEM Register (Offset (x8) = 0h, Offset (x16) = 0h) [Reset = 0h]
FLSEM is shown in Figure 6-56 and described in Table 6-63.
Return to the Summary Table.
Flash Wrapper Semaphore Register
Figure 6-56. FLSEM Register
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
RESERVED
R-0h

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
KEY RESERVED SEM
R-0/W-0h R-0h R/W-0h

Table 6-63. FLSEM Register Field Descriptions

Bit Field Type Reset Description
31-16 RESERVED R 0h Reserved
15-8 KEY R-0/W 0h Writing a value 0xA5 into this field will allow the writing of the SEM
bits, else writes are ignored. Reads will return 0.
Reset type: SYSRSn
7-2 RESERVED R 0h Reserved
1-0 SEM R/W 0h 00 : Flash Wrapper registers can be written by code running from
non-secure zone.
01 : Flash Wrapper registers can be written by code running from
Zone1 security zone.
10 : Flash Wrapper registers can be written by code running from
Zone2 security zone
11 : Flash Wrapper registers can be written by code running from
non-secure zone.
Allowed State Transitions in this field.
00 TO 11 : Not allowed.
11 TO 00 : Not allowed.
00/11 TO 01 : Code running from Zone1 only can perform this
transition.
01 TO 00/11 : Code running from Zone1 only can perform this
transition.
00/11 TO 10 : Code running from Zone2 only can perform this
transition.
10 TO 00/11 : Code running from Zone2 can perform this transition
10 TO 01 : Not allowed.
01 TO 10 : Not allowed.
Reset type: SYSRSn

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6.9.5.2 SECTSTAT1 Register (Offset (x8) = 10h, Offset (x16) = 8h) [Reset = 0h]
SECTSTAT1 is shown in Figure 6-57 and described in Table 6-64.
Return to the Summary Table.
Flash Sectors Status Register 1
Figure 6-57. SECTSTAT1 Register
31 30 29 28 27 26 25 24
RESERVED STATUS_SECT13 STATUS_SECT12
R-0h R-0h R-0h

23 22 21 20 19 18 17 16
STATUS_SECT11 STATUS_SECT10 STATUS_SECT9 STATUS_SECT8
R-0h R-0h R-0h R-0h

15 14 13 12 11 10 9 8
STATUS_SECT7 STATUS_SECT6 STATUS_SECT5 STATUS_SECT4
R-0h R-0h R-0h R-0h

7 6 5 4 3 2 1 0
STATUS_SECT3 STATUS_SECT2 STATUS_SECT1 STATUS_SECT0
R-0h R-0h R-0h R-0h

Table 6-64. SECTSTAT1 Register Field Descriptions

Bit Field Type Reset Description
31-28 RESERVED R 0h Reserved
27-26 STATUS_SECT13 R 0h Reflects the status of flash CPU1 BANK Sector 13.
00 : Sector is in-accessible
01 : Sector belongs to Zone1.
10 : Sector belongs to Zone2.
11: Sector is un-secure and code running in both zone have full
access to it.
Reset type: SYSRSn
25-24 STATUS_SECT12 R 0h Reflects the status of flash CPU1 BANK Sector 12.
00 : Sector is in-accessible
01 : Sector belongs to Zone1.
10 : Sector belongs to Zone2.
11: Sector is un-secure and code running in both zone have full
access to it.
Reset type: SYSRSn
23-22 STATUS_SECT11 R 0h Reflects the status of flash CPU1 BANK Sector 11.
00 : Sector is in-accessible
01 : Sector belongs to Zone1.
10 : Sector belongs to Zone2.
11: Sector is un-secure and code running in both zone have full
access to it.
Reset type: SYSRSn
21-20 STATUS_SECT10 R 0h Reflects the status of flash CPU1 BANK Sector 10.
00 : Sector is in-accessible
01 : Sector belongs to Zone1.
10 : Sector belongs to Zone2.
11: Sector is un-secure and code running in both zone have full
access to it.
Reset type: SYSRSn

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Table 6-64. SECTSTAT1 Register Field Descriptions (continued)

Bit Field Type Reset Description
19-18 STATUS_SECT9 R 0h Reflects the status of flash CPU1 BANK Sector 9.
00 : Sector is in-accessible
01 : Sector belongs to Zone1.
10 : Sector belongs to Zone2.
11: Sector is un-secure and code running in both zone have full
access to it.
Reset type: SYSRSn
17-16 STATUS_SECT8 R 0h Reflects the status of flash CPU1 BANK sector 8.
00 : Sector is in-accessible
01 : Sector belongs to Zone1.
10 : Sector belongs to Zone2.
11: Sector is un-secure and code running in both zone have full
access to it.
Reset type: SYSRSn
15-14 STATUS_SECT7 R 0h Reflects the status of flash CPU1 BANK Sector 7.
00 : Sector is in-accessible
01 : Sector belongs to Zone1.
10 : Sector belongs to Zone2.
11: Sector is un-secure and code running in both zone have full
access to it.
Reset type: SYSRSn
13-12 STATUS_SECT6 R 0h Reflects the status of flash CPU1 BANK Sector 6.
00 : Sector is in-accessible
01 : Sector belongs to Zone1.
10 : Sector belongs to Zone2.
11: Sector is un-secure and code running in both zone have full
access to it.
Reset type: SYSRSn
11-10 STATUS_SECT5 R 0h Reflects the status of flash CPU1 BANK Sector 5.
00 : Sector is in-accessible
01 : Sector belongs to Zone1.
10 : Sector belongs to Zone2.
11: Sector is un-secure and code running in both zone have full
access to it.
Reset type: SYSRSn
9-8 STATUS_SECT4 R 0h Reflects the status of flash CPU1 BANK Sector 4.
00 : Sector is in-accessible
01 : Sector belongs to Zone1.
10 : Sector belongs to Zone2.
11: Sector is un-secure and code running in both zone have full
access to it.
Reset type: SYSRSn
7-6 STATUS_SECT3 R 0h Reflects the status of flash CPU1 BANK Sector 3.
00 : Sector is in-accessible
01 : Sector belongs to Zone1.
10 : Sector belongs to Zone2.
11: Sector is un-secure and code running in both zone have full
access to it.
Reset type: SYSRSn
5-4 STATUS_SECT2 R 0h Reflects the status of flash CPU1 BANK Sector 2.
00 : Sector is in-accessible
01 : Sector belongs to Zone1.
10 : Sector belongs to Zone2.
11: Sector is un-secure and code running in both zone have full
access to it.
Reset type: SYSRSn

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Table 6-64. SECTSTAT1 Register Field Descriptions (continued)

Bit Field Type Reset Description
3-2 STATUS_SECT1 R 0h Reflects the status of flash CPU1 BANK sector 1.
00 : Sector is in-accessible
01 : Sector belongs to Zone1.
10 : Sector belongs to Zone2.
11: Sector is un-secure and code running in both zone have full
access to it.
Reset type: SYSRSn
1-0 STATUS_SECT0 R 0h Reflects the status of flash CPU1 BANK Sector 0.
00 : Sector is in-accessible
01 : Sector belongs to Zone1.
10 : Sector belongs to Zone2.
11: Sector is un-secure and code running in both zone have full
access to it.
Reset type: SYSRSn

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6.9.5.3 SECTSTAT2 Register (Offset (x8) = 14h, Offset (x16) = Ah) [Reset = 0h]
SECTSTAT2 is shown in Figure 6-58 and described in Table 6-65.
Return to the Summary Table.
Flash Sectors Status Register 2
Figure 6-58. SECTSTAT2 Register
31 30 29 28 27 26 25 24
RESERVED STATUS_SECT13 STATUS_SECT12
R-0h R-0h R-0h

23 22 21 20 19 18 17 16
STATUS_SECT11 STATUS_SECT10 STATUS_SECT9 STATUS_SECT8
R-0h R-0h R-0h R-0h

15 14 13 12 11 10 9 8
STATUS_SECT7 STATUS_SECT6 STATUS_SECT5 STATUS_SECT4
R-0h R-0h R-0h R-0h

7 6 5 4 3 2 1 0
STATUS_SECT3 STATUS_SECT2 STATUS_SECT1 STATUS_SECT0
R-0h R-0h R-0h R-0h

Table 6-65. SECTSTAT2 Register Field Descriptions

Bit Field Type Reset Description
31-28 RESERVED R 0h Reserved
27-26 STATUS_SECT13 R 0h Reflects the status of flash CM BANK Sector 13.
00 : Sector is in-accessible
01 : Sector belongs to Zone1.
10 : Sector belongs to Zone2.
11: Sector is un-secure and code running in both zone have full
access to it.
Reset type: SYSRSn
25-24 STATUS_SECT12 R 0h Reflects the status of flash CM BANK Sector 12.
00 : Sector is in-accessible
01 : Sector belongs to Zone1.
10 : Sector belongs to Zone2.
11: Sector is un-secure and code running in both zone have full
access to it.
Reset type: SYSRSn
23-22 STATUS_SECT11 R 0h Reflects the status of flash CM BANK Sector 11.
00 : Sector is in-accessible
01 : Sector belongs to Zone1.
10 : Sector belongs to Zone2.
11: Sector is un-secure and code running in both zone have full
access to it.
Reset type: SYSRSn
21-20 STATUS_SECT10 R 0h Reflects the status of flash CM BANK Sector 10.
00 : Sector is in-accessible
01 : Sector belongs to Zone1.
10 : Sector belongs to Zone2.
11: Sector is un-secure and code running in both zone have full
access to it.
Reset type: SYSRSn

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Table 6-65. SECTSTAT2 Register Field Descriptions (continued)

Bit Field Type Reset Description
19-18 STATUS_SECT9 R 0h Reflects the status of flash CM BANK Sector 9.
00 : Sector is in-accessible
01 : Sector belongs to Zone1.
10 : Sector belongs to Zone2.
11: Sector is un-secure and code running in both zone have full
access to it.
Reset type: SYSRSn
17-16 STATUS_SECT8 R 0h Reflects the status of flash CM BANK sector 8.
00 : Sector is in-accessible
01 : Sector belongs to Zone1.
10 : Sector belongs to Zone2.
11: Sector is un-secure and code running in both zone have full
access to it.
Reset type: SYSRSn
15-14 STATUS_SECT7 R 0h Reflects the status of flash CM BANK Sector 7.
00 : Sector is in-accessible
01 : Sector belongs to Zone1.
10 : Sector belongs to Zone2.
11: Sector is un-secure and code running in both zone have full
access to it.
Reset type: SYSRSn
13-12 STATUS_SECT6 R 0h Reflects the status of flash CM BANK Sector 6.
00 : Sector is in-accessible
01 : Sector belongs to Zone1.
10 : Sector belongs to Zone2.
11: Sector is un-secure and code running in both zone have full
access to it.
Reset type: SYSRSn
11-10 STATUS_SECT5 R 0h Reflects the status of flash CM BANK Sector 5.
00 : Sector is in-accessible
01 : Sector belongs to Zone1.
10 : Sector belongs to Zone2.
11: Sector is un-secure and code running in both zone have full
access to it.
Reset type: SYSRSn
9-8 STATUS_SECT4 R 0h Reflects the status of flash CM BANK Sector 4.
00 : Sector is in-accessible
01 : Sector belongs to Zone1.
10 : Sector belongs to Zone2.
11: Sector is un-secure and code running in both zone have full
access to it.
Reset type: SYSRSn
7-6 STATUS_SECT3 R 0h Reflects the status of flash CM BANK Sector 3.
00 : Sector is in-accessible
01 : Sector belongs to Zone1.
10 : Sector belongs to Zone2.
11: Sector is un-secure and code running in both zone have full
access to it.
Reset type: SYSRSn
5-4 STATUS_SECT2 R 0h Reflects the status of flash CM BANK Sector 2.
00 : Sector is in-accessible
01 : Sector belongs to Zone1.
10 : Sector belongs to Zone2.
11: Sector is un-secure and code running in both zone have full
access to it.
Reset type: SYSRSn

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Table 6-65. SECTSTAT2 Register Field Descriptions (continued)

Bit Field Type Reset Description
3-2 STATUS_SECT1 R 0h Reflects the status of flash CM BANK sector 1.
00 : Sector is in-accessible
01 : Sector belongs to Zone1.
10 : Sector belongs to Zone2.
11: Sector is un-secure and code running in both zone have full
access to it.
Reset type: SYSRSn
1-0 STATUS_SECT0 R 0h Reflects the status of flash CM BANK Sector 0.
00 : Sector is in-accessible
01 : Sector belongs to Zone1.
10 : Sector belongs to Zone2.
11: Sector is un-secure and code running in both zone have full
access to it.
Reset type: SYSRSn

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6.9.5.4 SECTSTAT3 Register (Offset (x8) = 18h, Offset (x16) = Ch) [Reset = 0h]
SECTSTAT3 is shown in Figure 6-59 and described in Table 6-66.
Return to the Summary Table.
Flash Sectors Status Register 3
Figure 6-59. SECTSTAT3 Register
31 30 29 28 27 26 25 24
RESERVED STATUS_SECT13 STATUS_SECT12
R-0h R-0h R-0h

23 22 21 20 19 18 17 16
STATUS_SECT11 STATUS_SECT10 STATUS_SECT9 STATUS_SECT8
R-0h R-0h R-0h R-0h

15 14 13 12 11 10 9 8
STATUS_SECT7 STATUS_SECT6 STATUS_SECT5 STATUS_SECT4
R-0h R-0h R-0h R-0h

7 6 5 4 3 2 1 0
STATUS_SECT3 STATUS_SECT2 STATUS_SECT1 STATUS_SECT0
R-0h R-0h R-0h R-0h

Table 6-66. SECTSTAT3 Register Field Descriptions

Bit Field Type Reset Description
31-28 RESERVED R 0h Reserved
27-26 STATUS_SECT13 R 0h Reflects the status of flash CPU2 BANK Sector 13.
00 : Sector is in-accessible
01 : Sector belongs to Zone1.
10 : Sector belongs to Zone2.
11: Sector is un-secure and code running in both zone have full
access to it.
Reset type: SYSRSn
25-24 STATUS_SECT12 R 0h Reflects the status of flash CPU2 BANK Sector 12.
00 : Sector is in-accessible
01 : Sector belongs to Zone1.
10 : Sector belongs to Zone2.
11: Sector is un-secure and code running in both zone have full
access to it.
Reset type: SYSRSn
23-22 STATUS_SECT11 R 0h Reflects the status of flash CPU2 BANK Sector 11.
00 : Sector is in-accessible
01 : Sector belongs to Zone1.
10 : Sector belongs to Zone2.
11: Sector is un-secure and code running in both zone have full
access to it.
Reset type: SYSRSn
21-20 STATUS_SECT10 R 0h Reflects the status of flash CPU2 BANK Sector 10.
00 : Sector is in-accessible
01 : Sector belongs to Zone1.
10 : Sector belongs to Zone2.
11: Sector is un-secure and code running in both zone have full
access to it.
Reset type: SYSRSn

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Table 6-66. SECTSTAT3 Register Field Descriptions (continued)

Bit Field Type Reset Description
19-18 STATUS_SECT9 R 0h Reflects the status of flash CPU2 BANK Sector 9.
00 : Sector is in-accessible
01 : Sector belongs to Zone1.
10 : Sector belongs to Zone2.
11: Sector is un-secure and code running in both zone have full
access to it.
Reset type: SYSRSn
17-16 STATUS_SECT8 R 0h Reflects the status of flash CPU2 BANK sector 8.
00 : Sector is in-accessible
01 : Sector belongs to Zone1.
10 : Sector belongs to Zone2.
11: Sector is un-secure and code running in both zone have full
access to it.
Reset type: SYSRSn
15-14 STATUS_SECT7 R 0h Reflects the status of flash CPU2 BANK Sector 7.
00 : Sector is in-accessible
01 : Sector belongs to Zone1.
10 : Sector belongs to Zone2.
11: Sector is un-secure and code running in both zone have full
access to it.
Reset type: SYSRSn
13-12 STATUS_SECT6 R 0h Reflects the status of flash CPU2 BANK Sector 6.
00 : Sector is in-accessible
01 : Sector belongs to Zone1.
10 : Sector belongs to Zone2.
11: Sector is un-secure and code running in both zone have full
access to it.
Reset type: SYSRSn
11-10 STATUS_SECT5 R 0h Reflects the status of flash CPU2 BANK Sector 5.
00 : Sector is in-accessible
01 : Sector belongs to Zone1.
10 : Sector belongs to Zone2.
11: Sector is un-secure and code running in both zone have full
access to it.
Reset type: SYSRSn
9-8 STATUS_SECT4 R 0h Reflects the status of flash CPU2 BANK Sector 4.
00 : Sector is in-accessible
01 : Sector belongs to Zone1.
10 : Sector belongs to Zone2.
11: Sector is un-secure and code running in both zone have full
access to it.
Reset type: SYSRSn
7-6 STATUS_SECT3 R 0h Reflects the status of flash CPU2 BANK Sector 3.
00 : Sector is in-accessible
01 : Sector belongs to Zone1.
10 : Sector belongs to Zone2.
11: Sector is un-secure and code running in both zone have full
access to it.
Reset type: SYSRSn
5-4 STATUS_SECT2 R 0h Reflects the status of flash CPU2 BANK Sector 2.
00 : Sector is in-accessible
01 : Sector belongs to Zone1.
10 : Sector belongs to Zone2.
11: Sector is un-secure and code running in both zone have full
access to it.
Reset type: SYSRSn

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Table 6-66. SECTSTAT3 Register Field Descriptions (continued)

Bit Field Type Reset Description
3-2 STATUS_SECT1 R 0h Reflects the status of flash CPU2 BANK sector 1.
00 : Sector is in-accessible
01 : Sector belongs to Zone1.
10 : Sector belongs to Zone2.
11: Sector is un-secure and code running in both zone have full
access to it.
Reset type: SYSRSn
1-0 STATUS_SECT0 R 0h Reflects the status of flash CPU2 BANK Sector 0.
00 : Sector is in-accessible
01 : Sector belongs to Zone1.
10 : Sector belongs to Zone2.
11: Sector is un-secure and code running in both zone have full
access to it.
Reset type: SYSRSn

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6.9.5.5 RAMSTAT1 Register (Offset (x8) = 20h, Offset (x16) = 10h) [Reset = 0h]
RAMSTAT1 is shown in Figure 6-60 and described in Table 6-67.
Return to the Summary Table.
RAM Status Register 1
Figure 6-60. RAMSTAT1 Register
31 30 29 28 27 26 25 24
RESERVED
R-0h

23 22 21 20 19 18 17 16
RESERVED STATUS_RAM9 STATUS_RAM8
R-0h R-0h R-0h

15 14 13 12 11 10 9 8
STATUS_RAM7 STATUS_RAM6 STATUS_RAM5 STATUS_RAM4
R-0h R-0h R-0h R-0h

7 6 5 4 3 2 1 0
STATUS_RAM3 STATUS_RAM2 STATUS_RAM1 STATUS_RAM0
R-0h R-0h R-0h R-0h

Table 6-67. RAMSTAT1 Register Field Descriptions

Bit Field Type Reset Description
31-20 RESERVED R 0h Reserved
19-18 STATUS_RAM9 R 0h Reflects the status of CPU1.D1 RAM.
00 : RAM is in-accessible
01 : RAM belongs to Zone1.
10 : RAM belongs to Zone2.
11: RAM is un-secure and code running in both zone have full
access to it.
Reset type: SYSRSn
17-16 STATUS_RAM8 R 0h Reflects the status of CPU1.D0 RAM.
00 : RAM is in-accessible
01 : RAM belongs to Zone1.
10 : RAM belongs to Zone2.
11: RAM is un-secure and code running in both zone have full
access to it.
Reset type: SYSRSn
15-14 STATUS_RAM7 R 0h Reflects the status of CPU1.LS7 RAM.
00 : RAM is in-accessible
01 : RAM belongs to Zone1.
10 : RAM belongs to Zone2.
11: RAM is un-secure and code running in both zone have full
access to it.
Reset type: SYSRSn
13-12 STATUS_RAM6 R 0h Reflects the status of CPU1.LS6 RAM.
00 : RAM is in-accessible
01 : RAM belongs to Zone1.
10 : RAM belongs to Zone2.
11: RAM is un-secure and code running in both zone have full
access to it.
Reset type: SYSRSn

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Table 6-67. RAMSTAT1 Register Field Descriptions (continued)

Bit Field Type Reset Description
11-10 STATUS_RAM5 R 0h Reflects the status of CPU1.LS5 RAM.
00 : RAM is in-accessible
01 : RAM belongs to Zone1.
10 : RAM belongs to Zone2.
11: RAM is un-secure and code running in both zone have full
access to it.
Reset type: SYSRSn
9-8 STATUS_RAM4 R 0h Reflects the status of CPU1.LS4 RAM.
00 : RAM is in-accessible
01 : RAM belongs to Zone1.
10 : RAM belongs to Zone2.
11: RAM is un-secure and code running in both zone have full
access to it.
Reset type: SYSRSn
7-6 STATUS_RAM3 R 0h Reflects the status of CPU1.LS3 RAM.
00 : RAM is in-accessible
01 : RAM belongs to Zone1.
10 : RAM belongs to Zone2.
11: RAM is un-secure and code running in both zone have full
access to it.
Reset type: SYSRSn
5-4 STATUS_RAM2 R 0h Reflects the status of CPU1.LS2 RAM.
00 : RAM is in-accessible
01 : RAM belongs to Zone1.
10 : RAM belongs to Zone2.
11: RAM is un-secure and code running in both zone have full
access to it.
Reset type: SYSRSn
3-2 STATUS_RAM1 R 0h Reflects the status of CPU1.LS1 RAM.
00 : RAM is in-accessible
01 : RAM belongs to Zone1.
10 : RAM belongs to Zone2.
11: RAM is un-secure and code running in both zone have full
access to it.
Reset type: SYSRSn
1-0 STATUS_RAM0 R 0h Reflects the status of CPU1.LS0 RAM.
00 : RAM is in-accessible
01 : RAM belongs to Zone1.
10 : RAM belongs to Zone2.
11: RAM is un-secure and code running in both zone have full
access to it.
Reset type: SYSRSn

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6.9.5.6 RAMSTAT2 Register (Offset (x8) = 24h, Offset (x16) = 12h) [Reset = 0h]
RAMSTAT2 is shown in Figure 6-61 and described in Table 6-68.
Return to the Summary Table.
RAM Status Register 2
Figure 6-61. RAMSTAT2 Register
31 30 29 28 27 26 25 24
STATUS_RAM15 STATUS_RAM14 STATUS_RAM13 STATUS_RAM12
R-0h R-0h R-0h R-0h

23 22 21 20 19 18 17 16
STATUS_RAM11 STATUS_RAM10 STATUS_RAM9 STATUS_RAM8
R-0h R-0h R-0h R-0h

15 14 13 12 11 10 9 8
STATUS_RAM7 STATUS_RAM6 STATUS_RAM5 STATUS_RAM4
R-0h R-0h R-0h R-0h

7 6 5 4 3 2 1 0
RESERVED STATUS_RAM1 STATUS_RAM0
R-0h R-0h R-0h

Table 6-68. RAMSTAT2 Register Field Descriptions

Bit Field Type Reset Description
31-30 STATUS_RAM15 R 0h Reflects the status of CM to CPU2 MSG RAM 1.
00 : RAM is in-accessible
01 : RAM belongs to Zone1.
10 : RAM belongs to Zone2.
11: RAM is un-secure and code running in both zone have full
access to it.
Reset type: SYSRSn
29-28 STATUS_RAM14 R 0h Reflects the status of MSG RAM.
00 : RAM is in-accessible
01 : RAM belongs to Zone1.
10 : RAM belongs to Zone2.
11: RAM is un-secure and code running in both zone have full
access to it.
Reset type: SYSRSn
27-26 STATUS_RAM13 R 0h Reflects the status of MSG RAM.
00 : RAM is in-accessible
01 : RAM belongs to Zone1.
10 : RAM belongs to Zone2.
11: RAM is un-secure and code running in both zone have full
access to it.
Reset type: SYSRSn
25-24 STATUS_RAM12 R 0h Reflects the status of MSG RAM.
00 : RAM is in-accessible
01 : RAM belongs to Zone1.
10 : RAM belongs to Zone2.
11: RAM is un-secure and code running in both zone have full
access to it.
Reset type: SYSRSn
23-22 STATUS_RAM11 R 0h Reflects the status of MSG RAM.
00 : RAM is in-accessible
01 : RAM belongs to Zone1.
10 : RAM belongs to Zone2.
11: RAM is un-secure and code running in both zone have full
access to it.
Reset type: SYSRSn

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Table 6-68. RAMSTAT2 Register Field Descriptions (continued)

Bit Field Type Reset Description
21-20 STATUS_RAM10 R 0h Reflects the status of CM to CPU2 MSG RAM 0.
00 : RAM is in-accessible
01 : RAM belongs to Zone1.
10 : RAM belongs to Zone2.
11: RAM is un-secure and code running in both zone have full
access to it.
Reset type: SYSRSn
19-18 STATUS_RAM9 R 0h Reflects the status of CPU2 to CM MSG RAM 1.
00 : RAM is in-accessible
01 : RAM belongs to Zone1.
10 : RAM belongs to Zone2.
11: RAM is un-secure and code running in both zone have full
access to it.
Reset type: SYSRSn
17-16 STATUS_RAM8 R 0h Reflects the status of CPU2 to CM MSG RAM 0.
00 : RAM is in-accessible
01 : RAM belongs to Zone1.
10 : RAM belongs to Zone2.
11: RAM is un-secure and code running in both zone have full
access to it.
Reset type: SYSRSn
15-14 STATUS_RAM7 R 0h Reflects the status of CM to CPU1 MSG RAM 1.
00 : RAM is in-accessible
01 : RAM belongs to Zone1.
10 : RAM belongs to Zone2.
11: RAM is un-secure and code running in both zone have full
access to it.
Reset type: SYSRSn
13-12 STATUS_RAM6 R 0h Reflects the status of CM to CPU1 MSG RAM 0.
00 : RAM is in-accessible
01 : RAM belongs to Zone1.
10 : RAM belongs to Zone2.
11: RAM is un-secure and code running in both zone have full
access to it.
Reset type: SYSRSn
11-10 STATUS_RAM5 R 0h Reflects the status of CPU1 to CM MSG RAM 1.
00 : RAM is in-accessible
01 : RAM belongs to Zone1.
10 : RAM belongs to Zone2.
11: RAM is un-secure and code running in both zone have full
access to it.
Reset type: SYSRSn
9-8 STATUS_RAM4 R 0h Reflects the status of CPU1 to CM MSG RAM 0.
00 : RAM is in-accessible
01 : RAM belongs to Zone1.
10 : RAM belongs to Zone2.
11: RAM is un-secure and code running in both zone have full
access to it.
Reset type: SYSRSn
7-4 RESERVED R 0h Reserved
3-2 STATUS_RAM1 R 0h Reflects the status of C1 RAM.
00 : RAM is in-accessible
01 : RAM belongs to Zone1.
10 : RAM belongs to Zone2.
11: RAM is un-secure and code running in both zone have full
access to it.
Reset type: SYSRSn

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Table 6-68. RAMSTAT2 Register Field Descriptions (continued)

Bit Field Type Reset Description
1-0 STATUS_RAM0 R 0h Reflects the status of C0 RAM.
00 : RAM is in-accessible
01 : RAM belongs to Zone1.
10 : RAM belongs to Zone2.
11: RAM is un-secure and code running in both zone have full
access to it.
Reset type: SYSRSn

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6.9.5.7 RAMSTAT3 Register (Offset (x8) = 28h, Offset (x16) = 14h) [Reset = 0h]
RAMSTAT3 is shown in Figure 6-62 and described in Table 6-69.
Return to the Summary Table.
RAM Status Register 3
Figure 6-62. RAMSTAT3 Register
31 30 29 28 27 26 25 24
RESERVED
R-0h

23 22 21 20 19 18 17 16
RESERVED STATUS_RAM9 STATUS_RAM8
R-0h R-0h R-0h

15 14 13 12 11 10 9 8
STATUS_RAM7 STATUS_RAM6 STATUS_RAM5 STATUS_RAM4
R-0h R-0h R-0h R-0h

7 6 5 4 3 2 1 0
STATUS_RAM3 STATUS_RAM2 STATUS_RAM1 STATUS_RAM0
R-0h R-0h R-0h R-0h

Table 6-69. RAMSTAT3 Register Field Descriptions

Bit Field Type Reset Description
31-20 RESERVED R 0h Reserved
19-18 STATUS_RAM9 R 0h Reflects the status of CPU2.D1 RAM.
00 : RAM is in-accessible
01 : RAM belongs to Zone1.
10 : RAM belongs to Zone2.
11: RAM is un-secure and code running in both zone have full
access to it.
Reset type: SYSRSn
17-16 STATUS_RAM8 R 0h Reflects the status of CPU2.D0 RAM.
00 : RAM is in-accessible
01 : RAM belongs to Zone1.
10 : RAM belongs to Zone2.
11: RAM is un-secure and code running in both zone have full
access to it.
Reset type: SYSRSn
15-14 STATUS_RAM7 R 0h Reflects the status of CPU2.LS7 RAM.
00 : RAM is in-accessible
01 : RAM belongs to Zone1.
10 : RAM belongs to Zone2.
11: RAM is un-secure and code running in both zone have full
access to it.
Reset type: SYSRSn
13-12 STATUS_RAM6 R 0h Reflects the status of CPU2.LS6 RAM.
00 : RAM is in-accessible
01 : RAM belongs to Zone1.
10 : RAM belongs to Zone2.
11: RAM is un-secure and code running in both zone have full
access to it.
Reset type: SYSRSn

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Table 6-69. RAMSTAT3 Register Field Descriptions (continued)

Bit Field Type Reset Description
11-10 STATUS_RAM5 R 0h Reflects the status of CPU2.LS5 RAM.
00 : RAM is in-accessible
01 : RAM belongs to Zone1.
10 : RAM belongs to Zone2.
11: RAM is un-secure and code running in both zone have full
access to it.
Reset type: SYSRSn
9-8 STATUS_RAM4 R 0h Reflects the status of CPU2.LS4 RAM.
00 : RAM is in-accessible
01 : RAM belongs to Zone1.
10 : RAM belongs to Zone2.
11: RAM is un-secure and code running in both zone have full
access to it.
Reset type: SYSRSn
7-6 STATUS_RAM3 R 0h Reflects the status of CPU2.LS3 RAM.
00 : RAM is in-accessible
01 : RAM belongs to Zone1.
10 : RAM belongs to Zone2.
11: RAM is un-secure and code running in both zone have full
access to it.
Reset type: SYSRSn
5-4 STATUS_RAM2 R 0h Reflects the status of CPU2.LS2 RAM.
00 : RAM is in-accessible
01 : RAM belongs to Zone1.
10 : RAM belongs to Zone2.
11: RAM is un-secure and code running in both zone have full
access to it.
Reset type: SYSRSn
3-2 STATUS_RAM1 R 0h Reflects the status of CPU2.LS1 RAM.
00 : RAM is in-accessible
01 : RAM belongs to Zone1.
10 : RAM belongs to Zone2.
11: RAM is un-secure and code running in both zone have full
access to it.
Reset type: SYSRSn
1-0 STATUS_RAM0 R 0h Reflects the status of CPU2.LS0 RAM.
00 : RAM is in-accessible
01 : RAM belongs to Zone1.
10 : RAM belongs to Zone2.
11: RAM is un-secure and code running in both zone have full
access to it.
Reset type: SYSRSn

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6.9.5.8 SECERRSTAT Register (Offset (x8) = 30h, Offset (x16) = 18h) [Reset = 0h]
SECERRSTAT is shown in Figure 6-63 and described in Table 6-70.
Return to the Summary Table.
Security Error Status Register
Figure 6-63. SECERRSTAT Register
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
RESERVED
R-0h

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RESERVED ERR
R-0h R-0h

Table 6-70. SECERRSTAT Register Field Descriptions

Bit Field Type Reset Description
31-1 RESERVED R 0h Reserved
0 ERR R 0h This bit indicates if any error has occurred in the load of any security
configuration from USER-OTP.
0: No error has occurred in the load of security information from
USER-OTP
1: Error has occurred in the load of security information from USER-
OTP
Reset type: PORESETn

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6.9.5.9 SECERRCLR Register (Offset (x8) = 34h, Offset (x16) = 1Ah) [Reset = 0h]
SECERRCLR is shown in Figure 6-64 and described in Table 6-71.
Return to the Summary Table.
Security Error Clear Register
Figure 6-64. SECERRCLR Register
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
RESERVED
R-0h

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RESERVED ERR
R-0h R-0/
W1S-0
h

Table 6-71. SECERRCLR Register Field Descriptions

Bit Field Type Reset Description
31-1 RESERVED R 0h Reserved
0 ERR R-0/W1S 0h A write of '1' clears the SECERRSTST.ERR bit. Write of '0' is
ignored. This bit always reads back '0'.
Reset type: N/A

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6.9.5.10 SECERRFRC Register (Offset (x8) = 38h, Offset (x16) = 1Ch) [Reset = 0h]
SECERRFRC is shown in Figure 6-65 and described in Table 6-72.
Return to the Summary Table.
Security Error Force Register
Figure 6-65. SECERRFRC Register
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
KEY
R-0/W-0h

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RESERVED ERR
R-0h R-0/
W1S-0
h

Table 6-72. SECERRFRC Register Field Descriptions

Bit Field Type Reset Description
31-16 KEY R-0/W 0h In order to write to the ERR bits, 0x5a5a must be written to these
key bits at the same time. Otherwise, writes are ignored. The key
is cleared immediately after writing, so it must be written again for
every write to ERR. Reads will return 0.
Reset type: N/A
15-1 RESERVED R 0h Reserved
0 ERR R-0/W1S 0h A write of '1', along with the proper KEY, sets the
SECERRSTST.ERR bit. Write of '0' is ignored. This bit always reads
back '0'.
Reset type: N/A

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6.9.6 DCSM_Z1_OTP Registers

Table 6-73 lists the memory-mapped registers for the DCSM_Z1_OTP registers. All register offset addresses not
listed in Table 6-73 should be considered as reserved locations and the register contents should not be modified.
Table 6-73. DCSM_Z1_OTP Registers
Offset Offset Acronym Register Name Write Section
(x8) (x16) Protection
0h 0h Z1OTP_LINKPOINTER1 Zone 1 Link Pointer1 Go
4h 2h Z1OTP_LINKPOINTER2 Zone 1 Link Pointer2 Go
8h 4h Z1OTP_LINKPOINTER3 Zone 1 Link Pointer3 Go
Ch 6h Z1OTP_JLM_ENABLE Zone 1 JTAGLOCK Enable Register Go
10h 8h Z1OTP_GPREG1 Zone 1 General Purpose Register 1 Go
14h Ah Z1OTP_GPREG2 Zone 1 General Purpose Register 2 Go
18h Ch Z1OTP_GPREG3 Zone 1 General Purpose Register 3 Go
1Ch Eh Z1OTP_GPREG4 Zone 1 General Purpose Register 4 Go
20h 10h Z1OTP_PSWDLOCK Secure Password Lock Go
24h 12h Z1OTP_CRCLOCK Secure CRC Lock Go
28h 14h Z1OTP_JTAGPSWDH0 JTAG Lock Permanent Password 0 Go
2Ch 16h Z1OTP_JTAGPSWDH1 JTAG Lock Permanent Password 1 Go
30h 18h Z1OTP_CMACKEY0 Secure Boot CMAC Key 0 Go
34h 1Ah Z1OTP_CMACKEY1 Secure Boot CMAC Key 1 Go
38h 1Ch Z1OTP_CMACKEY2 Secure Boot CMAC Key 2 Go
3Ch 1Eh Z1OTP_CMACKEY3 Secure Boot CMAC Key 3 Go

Complex bit access types are encoded to fit into small table cells. Table 6-74 shows the codes that are used for
access types in this section.
Table 6-74. DCSM_Z1_OTP Access Type Codes
Access Type Code Description
Read Type
R R Read
Reset or Default Value
-n Value after reset or the default
value
Register Array Variables
i,j,k,l,m,n When these variables are used in
a register name, an offset, or an
address, they refer to the value of
a register array where the register
is part of a group of repeating
registers. The register groups
form a hierarchical structure and
the array is represented with a
formula.
y When this variable is used in a
register name, an offset, or an
address it refers to the value of
a register array.

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6.9.6.1 Z1OTP_LINKPOINTER1 Register (Offset (x8) = 0h, Offset (x16) = 0h) [Reset = FFFFFFFFh]
Z1OTP_LINKPOINTER1 is shown in Figure 6-66 and described in Table 6-75.
Return to the Summary Table.
Zone 1 Link Pointer1
Figure 6-66. Z1OTP_LINKPOINTER1 Register
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Z1OTP_LINKPOINTER1
R-FFFFFFFFh

Table 6-75. Z1OTP_LINKPOINTER1 Register Field Descriptions

Bit Field Type Reset Description
31-0 Z1OTP_LINKPOINTER1 R FFFFFFFFh Zone1 Link Pointer 1 location in USER OTP.
Note:
[1] ECC comparison is disabled for this location
[2] When this value is loaded into DCSM, if the bits[31:14] !=0,
device will remain in BLOCKED state. Before shipping parts to
customers, TI would change the value of these bits to 0s.
Reset type: N/A

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6.9.6.2 Z1OTP_LINKPOINTER2 Register (Offset (x8) = 4h, Offset (x16) = 2h) [Reset = FFFFFFFFh]
Z1OTP_LINKPOINTER2 is shown in Figure 6-67 and described in Table 6-76.
Return to the Summary Table.
Zone 1 Link Pointer2
Figure 6-67. Z1OTP_LINKPOINTER2 Register
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Z1OTP_LINKPOINTER2
R-FFFFFFFFh

Table 6-76. Z1OTP_LINKPOINTER2 Register Field Descriptions

Bit Field Type Reset Description
31-0 Z1OTP_LINKPOINTER2 R FFFFFFFFh Zone1 Link Pointer 2 location in USER OTP.
Note:
[1] ECC comparison is disabled for this location
[2] When this value is loaded into DCSM, if the bits[31:14] !=0,
device will remain in BLOCKED state. Before shipping parts to
customers, TI would change the value of these bits to 0s.
Reset type: N/A

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6.9.6.3 Z1OTP_LINKPOINTER3 Register (Offset (x8) = 8h, Offset (x16) = 4h) [Reset = FFFFFFFFh]
Z1OTP_LINKPOINTER3 is shown in Figure 6-68 and described in Table 6-77.
Return to the Summary Table.
Zone 1 Link Pointer3
Figure 6-68. Z1OTP_LINKPOINTER3 Register
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Z1OTP_LINKPOINTER3
R-FFFFFFFFh

Table 6-77. Z1OTP_LINKPOINTER3 Register Field Descriptions

Bit Field Type Reset Description
31-0 Z1OTP_LINKPOINTER3 R FFFFFFFFh Zone1 Link Pointer 3 location in USER OTP.
Note:
[1] ECC comparison is disabled for this location
[2] When this value is loaded into DCSM, if the bits[31:14] !=0,
device will remain in BLOCKED state. Before shipping parts to
customers, TI would change the value of these bits to 0s.
Reset type: N/A

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6.9.6.4 Z1OTP_JLM_ENABLE Register (Offset (x8) = Ch, Offset (x16) = 6h) [Reset = FFFFFFFFh]
Z1OTP_JLM_ENABLE is shown in Figure 6-69 and described in Table 6-78.
Return to the Summary Table.
Zone 1 JTAGLOCK Enable Register
Figure 6-69. Z1OTP_JLM_ENABLE Register
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Z1OTP_JLM_ENABLE
R-FFFFFFFFh

Table 6-78. Z1OTP_JLM_ENABLE Register Field Descriptions

Bit Field Type Reset Description
31-0 Z1OTP_JLM_ENABLE R FFFFFFFFh Zone1 JLM_ENABLE register location in USER OTP.
Note: When this value is loaded into Z1_JLM_ENABLE, if the value
is 32-bit all-1s, the JTAGLOCK will be enabled. Before shipping parts
to customers, TI will program the default value to 0xFFFF_000F,
which will disable the JTAGLOCK feature. Users should program
0xFFFF_0000 to enable the JTAGLOCK feature.
Reset type: N/A

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6.9.6.5 Z1OTP_GPREG1 Register (Offset (x8) = 10h, Offset (x16) = 8h) [Reset = FFFFFFFFh]
Z1OTP_GPREG1 is shown in Figure 6-70 and described in Table 6-79.
Return to the Summary Table.
Zone 1 General Purpose Register 1
Figure 6-70. Z1OTP_GPREG1 Register
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Z1OTP_GPREG1
R-FFFFFFFFh

Table 6-79. Z1OTP_GPREG1 Register Field Descriptions

Bit Field Type Reset Description
31-0 Z1OTP_GPREG1 R FFFFFFFFh Zone1 General Purpose register location in USER OTP.
Reset type: N/A

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6.9.6.6 Z1OTP_GPREG2 Register (Offset (x8) = 14h, Offset (x16) = Ah) [Reset = FFFFFFFFh]
Z1OTP_GPREG2 is shown in Figure 6-71 and described in Table 6-80.
Return to the Summary Table.
Zone 1 General Purpose Register 2
Figure 6-71. Z1OTP_GPREG2 Register
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Z1OTP_GPREG2
R-FFFFFFFFh

Table 6-80. Z1OTP_GPREG2 Register Field Descriptions

Bit Field Type Reset Description
31-0 Z1OTP_GPREG2 R FFFFFFFFh Zone1 General Purpose register location in USER OTP.
Reset type: N/A

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6.9.6.7 Z1OTP_GPREG3 Register (Offset (x8) = 18h, Offset (x16) = Ch) [Reset = FFFFFFFFh]
Z1OTP_GPREG3 is shown in Figure 6-72 and described in Table 6-81.
Return to the Summary Table.
Zone 1 General Purpose Register 3
Figure 6-72. Z1OTP_GPREG3 Register
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Z1OTP_GPREG3
R-FFFFFFFFh

Table 6-81. Z1OTP_GPREG3 Register Field Descriptions

Bit Field Type Reset Description
31-0 Z1OTP_GPREG3 R FFFFFFFFh Zone1 General Purpose register location in USER OTP.
Reset type: N/A

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6.9.6.8 Z1OTP_GPREG4 Register (Offset (x8) = 1Ch, Offset (x16) = Eh) [Reset = FFFFFFFFh]
Z1OTP_GPREG4 is shown in Figure 6-73 and described in Table 6-82.
Return to the Summary Table.
Zone 1 General Purpose Register 4
Figure 6-73. Z1OTP_GPREG4 Register
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Z1OTP_GPREG4
R-FFFFFFFFh

Table 6-82. Z1OTP_GPREG4 Register Field Descriptions

Bit Field Type Reset Description
31-0 Z1OTP_GPREG4 R FFFFFFFFh Zone1 General Purpose register location in USER OTP.
Reset type: N/A

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6.9.6.9 Z1OTP_PSWDLOCK Register (Offset (x8) = 20h, Offset (x16) = 10h) [Reset = FFFFFFFFh]
Z1OTP_PSWDLOCK is shown in Figure 6-74 and described in Table 6-83.
Return to the Summary Table.
Secure Password Lock
Figure 6-74. Z1OTP_PSWDLOCK Register
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Z1OTP_PSWDLOCK
R-FFFFFFFFh

Table 6-83. Z1OTP_PSWDLOCK Register Field Descriptions

Bit Field Type Reset Description
31-0 Z1OTP_PSWDLOCK R FFFFFFFFh Zone1 password lock location in USER OTP.
Note: When this value is loaded into DCSM, if the value is 32-
bit all-1s, CSMPSWD will remain locked. Before shipping parts to
customers, TI would change the value of this location in such a way
that the ECC field remains all-1s and also LSB 4-bits remain 4'b1111.
Reset type: N/A

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6.9.6.10 Z1OTP_CRCLOCK Register (Offset (x8) = 24h, Offset (x16) = 12h) [Reset = FFFFFFFFh]
Z1OTP_CRCLOCK is shown in Figure 6-75 and described in Table 6-84.
Return to the Summary Table.
Secure CRC Lock
Figure 6-75. Z1OTP_CRCLOCK Register
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Z1OTP_CRCLOCK
R-FFFFFFFFh

Table 6-84. Z1OTP_CRCLOCK Register Field Descriptions

Bit Field Type Reset Description
31-0 Z1OTP_CRCLOCK R FFFFFFFFh Zone1 CRC lock location in USER OTP.
Note: When this value is loaded into DCSM, if the value is 32-bit
all-1s, VCU will not have ability to calculate CRC on secured memory
content.. Before shipping parts to customers, TI would change the
value of this location in such a way that the ECC field remains all-1s
and also LSB 4-bits remain 4'b1111.
Reset type: N/A

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6.9.6.11 Z1OTP_JTAGPSWDH0 Register (Offset (x8) = 28h, Offset (x16) = 14h) [Reset = FFFFFFFFh]
Z1OTP_JTAGPSWDH0 is shown in Figure 6-76 and described in Table 6-85.
Return to the Summary Table.
JTAG Lock Permanent Password 0
Figure 6-76. Z1OTP_JTAGPSWDH0 Register
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
JTAGPSWDH0
R-FFFFFFFFh

Table 6-85. Z1OTP_JTAGPSWDH0 Register Field Descriptions

Bit Field Type Reset Description
31-0 JTAGPSWDH0 R FFFFFFFFh JTAG Lock Password High 0 (bits 95:64) location in USER Z1 OTP.
This value is dummy loaded into the non-memory-mapped
JTAGPSWD register, bits 95:64.
TI must program a default value into this location, leaving the ECC
bits all 1's.
Reset type: N/A

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6.9.6.12 Z1OTP_JTAGPSWDH1 Register (Offset (x8) = 2Ch, Offset (x16) = 16h) [Reset = FFFFFFFFh]
Z1OTP_JTAGPSWDH1 is shown in Figure 6-77 and described in Table 6-86.
Return to the Summary Table.
JTAG Lock Permanent Password 1
Figure 6-77. Z1OTP_JTAGPSWDH1 Register
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
JTAGPSWDH1
R-FFFFFFFFh

Table 6-86. Z1OTP_JTAGPSWDH1 Register Field Descriptions

Bit Field Type Reset Description
31-0 JTAGPSWDH1 R FFFFFFFFh JTAG Lock Password High 1 (bits 127:96) location in USER Z1 OTP.
This value is dummy loaded into the non-memory-mapped
JTAGPSWD register, bits 127:96.
Reset type: N/A

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6.9.6.13 Z1OTP_CMACKEY0 Register (Offset (x8) = 30h, Offset (x16) = 18h) [Reset = FFFFFFFFh]
Z1OTP_CMACKEY0 is shown in Figure 6-78 and described in Table 6-87.
Return to the Summary Table.
Secure Boot CMAC Key 0
Figure 6-78. Z1OTP_CMACKEY0 Register
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CMACKEY0
R-FFFFFFFFh

Table 6-87. Z1OTP_CMACKEY0 Register Field Descriptions

Bit Field Type Reset Description
31-0 CMACKEY0 R FFFFFFFFh Secure Boot CMAC Key 0 (bits 31:0) location in User Z1 OTP.
This value is dummy loaded into the CMACKEY0 register.
Reset type: N/A

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6.9.6.14 Z1OTP_CMACKEY1 Register (Offset (x8) = 34h, Offset (x16) = 1Ah) [Reset = FFFFFFFFh]
Z1OTP_CMACKEY1 is shown in Figure 6-79 and described in Table 6-88.
Return to the Summary Table.
Secure Boot CMAC Key 1
Figure 6-79. Z1OTP_CMACKEY1 Register
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CMACKEY1
R-FFFFFFFFh

Table 6-88. Z1OTP_CMACKEY1 Register Field Descriptions

Bit Field Type Reset Description
31-0 CMACKEY1 R FFFFFFFFh Secure Boot CMAC Key 1 (bits 63:32) location in User Z1 OTP.
This value is dummy loaded into the CMACKEY1 register.
Reset type: N/A

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6.9.6.15 Z1OTP_CMACKEY2 Register (Offset (x8) = 38h, Offset (x16) = 1Ch) [Reset = FFFFFFFFh]
Z1OTP_CMACKEY2 is shown in Figure 6-80 and described in Table 6-89.
Return to the Summary Table.
Secure Boot CMAC Key 2
Figure 6-80. Z1OTP_CMACKEY2 Register
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CMACKEY2
R-FFFFFFFFh

Table 6-89. Z1OTP_CMACKEY2 Register Field Descriptions

Bit Field Type Reset Description
31-0 CMACKEY2 R FFFFFFFFh Secure Boot CMAC Key 2 (bits 95:64) location in User Z1 OTP.
This value is dummy loaded into the CMACKEY2 register.
Reset type: N/A

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6.9.6.16 Z1OTP_CMACKEY3 Register (Offset (x8) = 3Ch, Offset (x16) = 1Eh) [Reset = FFFFFFFFh]
Z1OTP_CMACKEY3 is shown in Figure 6-81 and described in Table 6-90.
Return to the Summary Table.
Secure Boot CMAC Key 3
Figure 6-81. Z1OTP_CMACKEY3 Register
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CMACKEY3
R-FFFFFFFFh

Table 6-90. Z1OTP_CMACKEY3 Register Field Descriptions

Bit Field Type Reset Description
31-0 CMACKEY3 R FFFFFFFFh Secure Boot CMAC Key 3 (bits 127:96) location in User Z1 OTP.
This value is dummy loaded into the CMACKEY3 register.
Reset type: N/A

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6.9.7 DCSM_Z2_OTP Registers

Table 6-91 lists the memory-mapped registers for the DCSM_Z2_OTP registers. All register offset addresses not
listed in Table 6-91 should be considered as reserved locations and the register contents should not be modified.
Table 6-91. DCSM_Z2_OTP Registers
Offset Offset Acronym Register Name Write Section
(x8) (x16) Protection
0h 0h Z2OTP_LINKPOINTER1 Zone 2 Link Pointer1 Go
4h 2h Z2OTP_LINKPOINTER2 Zone 2 Link Pointer2 Go
8h 4h Z2OTP_LINKPOINTER3 Zone 2 Link Pointer3 Go
10h 8h Z2OTP_GPREG1 Zone 2 General Purpose Register 1 Go
14h Ah Z2OTP_GPREG2 Zone 2 General Purpose Register 2 Go
18h Ch Z2OTP_GPREG3 Zone 2 General Purpose Register 3 Go
1Ch Eh Z2OTP_GPREG4 Zone 2 General Purpose Register 4 Go
20h 10h Z2OTP_PSWDLOCK Secure Password Lock Go
24h 12h Z2OTP_CRCLOCK Secure CRC Lock Go

Complex bit access types are encoded to fit into small table cells. Table 6-92 shows the codes that are used for
access types in this section.
Table 6-92. DCSM_Z2_OTP Access Type Codes
Access Type Code Description
Read Type
R R Read
Reset or Default Value
-n Value after reset or the default
value
Register Array Variables
i,j,k,l,m,n When these variables are used in
a register name, an offset, or an
address, they refer to the value of
a register array where the register
is part of a group of repeating
registers. The register groups
form a hierarchical structure and
the array is represented with a
formula.
y When this variable is used in a
register name, an offset, or an
address it refers to the value of
a register array.

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6.9.7.1 Z2OTP_LINKPOINTER1 Register (Offset (x8) = 0h, Offset (x16) = 0h) [Reset = FFFFFFFFh]
Z2OTP_LINKPOINTER1 is shown in Figure 6-82 and described in Table 6-93.
Return to the Summary Table.
Zone 2 Link Pointer1
Figure 6-82. Z2OTP_LINKPOINTER1 Register
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Z2OTP_LINKPOINTER1
R-FFFFFFFFh

Table 6-93. Z2OTP_LINKPOINTER1 Register Field Descriptions

Bit Field Type Reset Description
31-0 Z2OTP_LINKPOINTER1 R FFFFFFFFh Zone2 Link Pointer 1 location in USER OTP.
Note:
[1] ECC comparison is disabled for this location
[2] When this value is loaded into DCSM, if the bits[31:14] !=0,
device will remain in BLOCKED state. Before shipping parts to
customers, TI would change the value of these bits to 0s.
Reset type: N/A

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6.9.7.2 Z2OTP_LINKPOINTER2 Register (Offset (x8) = 4h, Offset (x16) = 2h) [Reset = FFFFFFFFh]
Z2OTP_LINKPOINTER2 is shown in Figure 6-83 and described in Table 6-94.
Return to the Summary Table.
Zone 2 Link Pointer2
Figure 6-83. Z2OTP_LINKPOINTER2 Register
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Z2OTP_LINKPOINTER2
R-FFFFFFFFh

Table 6-94. Z2OTP_LINKPOINTER2 Register Field Descriptions

Bit Field Type Reset Description
31-0 Z2OTP_LINKPOINTER2 R FFFFFFFFh Zone2 Link Pointer 2 location in USER OTP.
Note:
[1] ECC comparison is disabled for this location
[2] When this value is loaded into DCSM, if the bits[31:14] !=0,
device will remain in BLOCKED state. Before shipping parts to
customers, TI would change the value of these bits to 0s.
Reset type: N/A

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6.9.7.3 Z2OTP_LINKPOINTER3 Register (Offset (x8) = 8h, Offset (x16) = 4h) [Reset = FFFFFFFFh]
Z2OTP_LINKPOINTER3 is shown in Figure 6-84 and described in Table 6-95.
Return to the Summary Table.
Zone 2 Link Pointer3
Figure 6-84. Z2OTP_LINKPOINTER3 Register
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Z2OTP_LINKPOINTER3
R-FFFFFFFFh

Table 6-95. Z2OTP_LINKPOINTER3 Register Field Descriptions

Bit Field Type Reset Description
31-0 Z2OTP_LINKPOINTER3 R FFFFFFFFh Zone2 Link Pointer 3 location in USER OTP.
Note:
[1] ECC comparison is disabled for this location
[2] When this value is loaded into DCSM, if the bits[31:14] !=0,
device will remain in BLOCKED state. Before shipping parts to
customers, TI would change the value of these bits to 0s.
Reset type: N/A

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6.9.7.4 Z2OTP_GPREG1 Register (Offset (x8) = 10h, Offset (x16) = 8h) [Reset = FFFFFFFFh]
Z2OTP_GPREG1 is shown in Figure 6-85 and described in Table 6-96.
Return to the Summary Table.
Zone 2 General Purpose Register 1
Figure 6-85. Z2OTP_GPREG1 Register
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Z2OTP_GPREG1
R-FFFFFFFFh

Table 6-96. Z2OTP_GPREG1 Register Field Descriptions

Bit Field Type Reset Description
31-0 Z2OTP_GPREG1 R FFFFFFFFh Zone2 General Purpose register location in USER OTP.
Reset type: N/A

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6.9.7.5 Z2OTP_GPREG2 Register (Offset (x8) = 14h, Offset (x16) = Ah) [Reset = FFFFFFFFh]
Z2OTP_GPREG2 is shown in Figure 6-86 and described in Table 6-97.
Return to the Summary Table.
Zone 2 General Purpose Register 2
Figure 6-86. Z2OTP_GPREG2 Register
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Z2OTP_GPREG2
R-FFFFFFFFh

Table 6-97. Z2OTP_GPREG2 Register Field Descriptions

Bit Field Type Reset Description
31-0 Z2OTP_GPREG2 R FFFFFFFFh Zone2 General Purpose register location in USER OTP.
Reset type: N/A

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6.9.7.6 Z2OTP_GPREG3 Register (Offset (x8) = 18h, Offset (x16) = Ch) [Reset = FFFFFFFFh]
Z2OTP_GPREG3 is shown in Figure 6-87 and described in Table 6-98.
Return to the Summary Table.
Zone 2 General Purpose Register 3
Figure 6-87. Z2OTP_GPREG3 Register
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Z2OTP_GPREG3
R-FFFFFFFFh

Table 6-98. Z2OTP_GPREG3 Register Field Descriptions

Bit Field Type Reset Description
31-0 Z2OTP_GPREG3 R FFFFFFFFh Zone2 General Purpose register location in USER OTP.
Reset type: N/A

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6.9.7.7 Z2OTP_GPREG4 Register (Offset (x8) = 1Ch, Offset (x16) = Eh) [Reset = FFFFFFFFh]
Z2OTP_GPREG4 is shown in Figure 6-88 and described in Table 6-99.
Return to the Summary Table.
Zone 2 General Purpose Register 4
Figure 6-88. Z2OTP_GPREG4 Register
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Z2OTP_GPREG4
R-FFFFFFFFh

Table 6-99. Z2OTP_GPREG4 Register Field Descriptions

Bit Field Type Reset Description
31-0 Z2OTP_GPREG4 R FFFFFFFFh Zone2 General Purpose register location in USER OTP.
Reset type: N/A

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6.9.7.8 Z2OTP_PSWDLOCK Register (Offset (x8) = 20h, Offset (x16) = 10h) [Reset = FFFFFFFFh]
Z2OTP_PSWDLOCK is shown in Figure 6-89 and described in Table 6-100.
Return to the Summary Table.
Secure Password Lock
Figure 6-89. Z2OTP_PSWDLOCK Register
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Z2OTP_PSWDLOCK
R-FFFFFFFFh

Table 6-100. Z2OTP_PSWDLOCK Register Field Descriptions

Bit Field Type Reset Description
31-0 Z2OTP_PSWDLOCK R FFFFFFFFh Zone2 password lock location in USER OTP.
Note: When this value is loaded into DCSM, if the value is 32-
bit all-1s, CSMPSWD will remain locked. Before shipping parts to
customers, TI would change the value of this location in such a way
that the ECC field remains all-1s and also LSB 4-bits remain 4'b1111.
Reset type: N/A

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6.9.7.9 Z2OTP_CRCLOCK Register (Offset (x8) = 24h, Offset (x16) = 12h) [Reset = FFFFFFFFh]
Z2OTP_CRCLOCK is shown in Figure 6-90 and described in Table 6-101.
Return to the Summary Table.
Secure CRC Lock
Figure 6-90. Z2OTP_CRCLOCK Register
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Z2OTP_CRCLOCK
R-FFFFFFFFh

Table 6-101. Z2OTP_CRCLOCK Register Field Descriptions

Bit Field Type Reset Description
31-0 Z2OTP_CRCLOCK R FFFFFFFFh Zone2 CRC lock location in USER OTP.
Note: When this value is loaded into DCSM, if the value is 32-bit
all-1s, VCU will not have ability to calculate CRC on secured memory
content.. Before shipping parts to customers, TI would change the
value of this location in such a way that the ECC field remains all-1s
and also LSB 4-bits remain 4'b1111.
Reset type: N/A

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www.ti.com Background CRC-32 (BGCRC)

Chapter 7
Background CRC-32 (BGCRC)

The Background CRC (BGCRC) module that helps to identify memory faults and corruption, is discussed in this
chapter.

7.1 Introduction...............................................................................................................................................................926
7.2 Functional Description.............................................................................................................................................928
7.3 Application of the BGCRC....................................................................................................................................... 930
7.4 Software.................................................................................................................................................................... 935
7.5 BGCRC Registers..................................................................................................................................................... 936

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7.1 Introduction
The Background CRC (BGCRC) module computes a CRC-32 on a configurable block of memory. It
accomplishes this by fetching the specified block of memory during idle cycles (when the CPU, CLA, or DMA
is not accessing the memory block). The calculated CRC-32 value is compared against a golden CRC-32 value
to indicate a pass or fail. In essence, the BGCRC helps identify memory faults and corruption. There are two
BGCRC modules (CPU_CRC and CLA_CRC) per CPU subsystem. The two BGCRC modules differ only in the
memories they test.
7.1.1 BGCRC Related Collateral

Getting Started Materials

• CRC Engines in C2000 Devices Application Report
7.1.2 Features
The BGCRC module has the following features:
• One cycle CRC-32 computation on 32 bits of data
• No CPU bandwidth impact for zero wait state memory
• Minimal CPU bandwidth impact for non-zero wait state memory
• Dual operation modes (CRC-32 mode and scrub mode)
• Watchdog timer to time CRC-32 completion
• Ability to pause and resume CRC-32 computation

7.1.3 Block Diagram

Figure 7-1 shows the BGCRC block diagram.

Figure 7-1. BGCRC Block Diagram

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7.1.4 Memory Wait States and Memory Map

Figure 7-2 shows the memory map of the BGCRC module. M0, M1, D[x]RAM, MSGRAM, LS[x]RAM, and
GS[x]RAM are all zero wait-state memories. BGCRC accesses these memories with minimal impact on normal
program operation. For instance, if a BGCRC access is being made to a zero wait-state memory in the current
cycle, the earliest the operating program can make access to the same memory location is in the next cycle.
Similarly for the non-zero wait state memories SECROM, DATAROM and BOOTROM, the worst case delay for
functional access after a BGCRC access is the wait-state amount.

Figure 7-2. BGCRC Memory Map

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7.2 Functional Description

The CRC-32 calculation of the BGCRC module can be kicked off by configuring the register BGCRC_EN.START
to 1010. Once started, the module performs the background memory checks without CPU or CLA intervention.
However, on completion of the CRC-32 calculation or in the event of a failure, the CPU or CLA is notified through
an interrupt and task, respectively.
As highlighted in the overview, there are two BGCRC modules per CPU subsystem. CPU_CRC that is
configurable by the CPU can only generate an interrupt. CLA_CRC however, can be configured by both the
CPU and CLA and can generate an interrupt to the CPU or task for the CLA.
7.2.1 Data Read Unit
Once the CRC-32 calculation is started, the BGCRC module continuously reads data from memory as
a background process. These reads happen during the idle times (when the CPU, CLA or DMA is not
accessing the memory block) and so does not impact functional access. The data read unit only reads data
if there is no pending functional access. The data read unit begins operation by reading a block of data
BGCRC_CTRL2.BLOCK_SIZE from address BGCRC_START_ADDR. Note that BGCRC_START_ADDR must
be 0x80 word aligned. For a non-0x80 word aligned BGCRC_START_ADDR, the LSB bits are zeroed out to
get a 0x80 word aligned BGCRC_START_ADDR. For instance, if the programmed BGCRC_START_ADDR =
0x1AF3, the internal 0x80 word aligned start address is 0x1A80.
When the data read unit reads a block of data, ECC and parity are checked. Any ECC or parity errors that
occur during the read is indicated by setting the respective NMI and generating an interrupt if configured as
so. The BGCRC module, however, does not write back the corrected memory contents on the occurrence of a
correctable ECC error. Writing back the corrected values should be handled by software.
7.2.2 CRC-32 Compute Unit
After the data read unit reads a block of data, the data read unit feeds this data to the CRC-32 compute unit.
This unit computes the CRC-32 using the standard polynomial 0x04C11DB7 (x32 + x26 + x23 + x22 + x16 +
x12 + x11 + x10 + x8 + x7 + x5 + x4 + x2 + x + 1). The CRC-32 unit retrieves 32-bit of data at a time from the
block of data to compute the polynomial. This computation takes 1 cycle. For instance, the CRC-32 calculation
for 1KB block of data is 256 cycles, 1 cycle for each of the 256 32-bit chunks. The initial value for the CRC-32
computation can be configured using BGCRC_SEED.
After the CRC-32 calculation is complete for a data block, the final result is loaded into BGCRC_RESULT.
Note that BGCRC_RESULT only contains the final calculation for the whole data block; intermediate 32-bit
calculations do not update BGCRC_RESULT. The value in BGCRC_RESULT is compared against the value in
BGCRC_GOLDEN by hardware and the NMI/Interrupt flags are set accordingly by the CRC notification unit.
Once CRC-32 calculation is commenced, the calculation can be halted by setting BGCRC_CTRL2.TEST_HALT
to 1010. Clearing this bit resumes CRC-32 calculation from the halt point.

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7.2.3 CRC Notification Unit

After the CRC-32 compute unit completes the CRC-32 calculation for a block of data or fails to complete the
calculation within BGCRC_WD_MIN and BGCRC_WD_MAX, if configured, the CRC-32 compute unit sends out
a NMI/Interrupt on the occurrence of a pass or fail. In addition, during a data read by the data read unit, if an
ECC or parity error occurs, the CRC notification unit can send out a NMI/Interrupt. In the case of an ECC or
parity error, the BGCRC stops operation and BGCRC_CURR_ADDR contains the memory address that caused
the ECC or parity error. The contents of BGCRC_CURR_ADDR in addition to the NMI/Interrupt flags can be
used to debug a BGCRC failure.
7.2.3.1 CPU Interrupt, CLA Task and NMI
The BGCRC module has configurable interrupt and NMI lines. NMIs are enabled by default but can be disabled
by writing 0xA to BGCRC_CTRL1.NMIDIS register. Conversely, all interrupts are disabled by default but can be
enabled by writing 0x7E to BGCRC_INTEN register. When an error occurs in the BGCRC, the BGCRC can be
configured to generate an NMI or interrupt. Since NMIs are enabled by default, all BGCRC errors cause an NMI.
Figure 7-3 and Figure 7-4 show the NMI and Interrupt lines, respectively.

Figure 7-3. BGCRC NMI

Figure 7-4. BGCRC Interrupt

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7.2.4 Operating Modes

BGCRC module supports two modes of operation: CRC mode and scrub mode. The mode of operation can be
configured by clearing or setting the register BGCRC_CTRL2.SCRUB_MODE.
7.2.4.1 CRC Mode
In CRC mode, the BGCRC module operates as explained in Section 7.2.2. CRC-32 calculation is performed on
a block of data and the result compared against a golden value. ECC and parity errors are checked in this mode.
Result mismatch, ECC or parity error can trigger an NMI/Interrupt.
7.2.4.2 Scrub Mode
In scrub mode, the CRC-32 result is not compared against the golden value and BGCRC_RESULT register is
not updated. ECC and parity errors are also checked in this mode. However unlike CRC mode, NMI/Interrupt are
only from ECC or parity error. In scrub mode, Parity and ECC bits of the memory block need to be initialized by
the CPU and/or CLA.
7.2.5 BGCRC Watchdog
The BGCRC module has an embedded windowed watchdog that is used as a diagnostic to check memory
test completion within the expected time window. This can protect against hardware defects that can cause the
memory check not to complete in the allotted time, which may not be caught by the system watchdog as the
error can be due to the CLA or DMA having continuous access. Windowing also helps detect additional failure
modes in the watchdog operation, for example, stuck watchdog.
The BGCRC watchdog is enabled by default and starts when the BGCRC module begins reading from memory.
The watchdog can be disabled using the register BGCRC_WD_CFG.WDDIS. The BGCRC watchdog counter
is a 32-bit counter with the value reflected in BGCRC_WD_CNT register. The lower and upper window
settings are configured using BGCRC_WD_MIN and BGCRC_WD_MAX, respectively. BGCRC_WD_MIN and
BGCRC_WD_MAX need to be configured before the test is started and should not be changed while the
BGCRC is operating. If configured, an NMI or interrupt is triggered if the memory test fails to complete within the
configured time window. The counter stops on completion of the CRC-32 check done, CRC-32 check failure and
ECC/Parity errors. The counter is reset when the next memory check begins.
The BGCRC watchdog can be halted by configuring the BGCRC_WD_CFG.WDDIS register. After the watchdog
resumes from being halted, the counter starts counting from the previous count unless a new memory check
operation is initiated. The counter is not halted when CRC-32 computation halts but by default halts during
a debug halt. The behavior of the watchdog during emulation can be changed by configuring the appropriate
BGCRC registers. In addition, due to the changing nature of memory contents during emulation, it is not
recommended to run BGCRC during emulation. CRC-32 computation continues during a watchdog failure and
software needs to address this condition.
7.2.6 Hardware and Software Faults Protection
The configuration registers are protected using a lock and commit configuration. Each of the configuration
registers can be individually locked and committed. The register once locked, can no longer be updated until the
lock is removed. However if the register lock is committed, no further writes is permitted until the device is reset.
It is recommended to lock the registers after configuration to protect against corruption due to software faults. In
addition, registers critical to the module functionality and fault detection are implemented using multi-bit fields to
protect against hardware faults.
7.3 Application of the BGCRC
This section contains use case scenarios of how the BGCRC module can be configured to test a block of
memory. However, the use case scenarios presented are for reference only and do not cover all the possible
application scenarios. These use case scenarios could be used as a starting point to configure the BGCRC
module for specific applications.

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7.3.1 Software Configuration

The configuration registers for the BGCRC can be split into three groups (see Table 7-1):
• CFG1: Registers that determine the operating mode and configured at the beginning.
• CFG2: Registers that need to be updated during kickoff of a new test.
• CFG3: Registers used for test and error management.

CFG1 registers are expected to be locked and committed after initial configuration. It is recommended to lock the
CFG2 and CFG3 registers after configuration. Figure 7-5 shows the BGCRC execution sequence.
Table 7-1. BGCRC Register Groups
CFG1 - One Time CFG2 - Periodic CFG3 - Registers Used for Test and Error
Configuration Registers Configuration Registers Management
BGCRC_CTRL1 BGCRC_EN BGCRC_NMICLR
BGCRC_WD_CFG BGCRC_CTRL2 BGCRC_INTCLR
BGCRC_INTEN BGCRC_START_ADDR BGCRC_NMIFRC
BGCRC_SEED BGCRC_GOLDEN BGCRC_INTFRC
BGCRC_WD_MIN
BGCRC_WD_MAX

Figure 7-5. BGCRC Execution Sequence Flow

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7.3.2 Decision on Error Response Severity

The error sources for BGCRC are:
• Test completion before BGCRC_WD_MIN.
• Test completed after BGCRC_WD_MAX.
• Mismatch between the calculated CRC and golden CRC.
• Uncorrectable error during data read (single bit error for parity memory or double bit error for ECC memory).
• Correctable error during memory read (single bit error for ECC memory).
Error severity can be chosen as either NMI or interrupt. By default, error severity is set to NMI. It is not possible
to configure error response for each individual error source. The response can be chosen as either interrupt or
NMI for all error sources. When error severity is chosen as NMI, ERROR_STS pin is asserted during an error.
CPU and CLA should be assigned the same error severity.
7.3.3 Decision of Controller for CLA_CRC
CPU_CRC can only be kicked off by the CPU. However, CLA_CRC can be kicked off by the CPU or CLA. If
BGCRC error severity is chosen as NMI, it is possible to handle the background test using the CLA and error
response with the CPU. Once the controller for BGCRC is chosen, it is possible to prevent accesses from other
controllers by using the system-level access protection configuration.
7.3.4 Execution of Time Critical Code from Wait-Stated Memories
BGCRC access to functionally wait-stated memories is also wait-stated by the same number. Since it is
impossible to predict the next functional access, any ongoing BGCRC access has to complete before functional
access is granted. To mitigate delay in functional access, the BGCRC can be halted when time-critical code that
accesses the wait-stated memories is in progress. When BGCRC execution is halted, the BGCRC watchdog
is not halted. This is consistent with the safety requirement to complete the background test in a predictable
window irrespective of the user code. In such scenarios, it is recommended to adjust the upper BGCRC
watchdog window limit to account for the halt duration during functional access. However, if required, the
BGCRC watchdog can be disabled.
7.3.5 BGCRC Execution
Two notes about BGCRC execution are:
• BGCRC task can run as a background task once kicked off.
• BGCRC task does not impact functional execution for zero-wait stated memories. For memories with higher
wait-states, the BGCRC engine can be halted to make functional execution predictable.
Figure 7-6 shows a few examples of BGCRC execution sequences.

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Figure 7-6. BGCRC Execution Sequence Example

7.3.6 Debug/Error Response for BGCRC Errors

The BGCRC error severity can be decoded by reading the BGCRC_INTFLG or BGCRC_NMIFLG. The errors
can be:
• WD_OVERFLOW/WD_UNDERFLOW: The test did not complete in the programmed window. System timing
needs to be checked to understand reason for non-completion of the test. BGCRC_CURR_ADDR and
BGCRC_WD_CNT indicate how far the test progressed.
• UNCORRECTABLE_ERR: BGCRC_CURR_ADDR contains the address of the memory location causing the
error. This error is due to single bit failure for Parity SRAM or double bit failure for ECC SRAM. The memory
location can be reloaded (if possible, for cases where code is copied from Flash) to see if the problem
resolves. If the problem persists, the problem can be a permanent defect.
• CORRECTABLE_ERR: This error is due to single bit failure for ECC SRAM. If the problem location is
accessed again (execution from the location for execute only memory or reading the location in other cases),
the expectation is that the single bit error is corrected. If the single bit error is not corrected, this can be an
indication of a permanent defect.
• CRC_FAIL: This indicates a failure in the computation of the CRC-32 value. This error does not occur in
scrub mode. For SRAMs with protection, in the absence of code bugs, this error is less likely since the
error is most often manifest as a correctable/uncorrectable error. Code bugs can cause failure if the code
inadvertently writes to a wrong address thus causing a CRC-32 error.

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7.3.7 BGCRC Golden CRC-32 Value Computation

The C28x is a little-endian, 16-bit word addressable CPU. Therefore, the 32-bit value of 0x12345678 stored at
address 0x100 is stored in the C28x memory as shown in Table 7-2.
Table 7-2. Data Address Location Example 1
Address 0x100 0x101
Data 0x5678 0x1234

The BGCRC order of byte calculations of the above example is 0x78, 0x56, 0x34, 0x12 and yields 0x6A330D2D.
The 32-bit polynomial 0x04C11DB7 is used with an initialization vector of 0x00000000. The following code
snippet shows the effective bit processing. Processing for all 32-bits within a word occurs in a single cycle within
the BGCRC hardware.

seed = 0x0UL; //Initialize With Seed

poly = 0x04C11DB7UL: //32-Bit Polynomial
crc32 = seed;

for(i=0; i<dataSize; i++)

{
byteSwappedData = ((data[i] & 0x000000FF) << 24)|
= ((data[i] & 0x0000FF00) << 8) |
= ((data[i] & 0x00FF0000) >> 8) |
= ((data[i] & 0xFF000000) >> 24);

crc32 = byteSwappedData^crc32;
for(j=0; j<32; j++)
{
if(crc32 & 0x80000000) crc32 = (crc32 << 1)^poly;
else crc32 = crc32 << 1;

crc32 = crc32 & 0xFFFFFFFF;

}
}

A second example (Table 7-3) with two 32-bit words, 0x12345678 and 0x9ABCDEF0 at address 0x100 and
0x102 successively, would calculate the bytes in the order 0x78, 0x56, 0x34, 0x12, 0xDE, 0xBC, and 0x9A and
yield 0x7E0B4164.
Table 7-3. Data Address Location Example 2
Address 0x100 0x101 0x102 0x103
Data 0x5678 0x1234 0xDEF0 0x9ABC

All data input to the BGCRC must align to a 32-bit boundary, both in the starting address and the size. It
is possible to include 16-bit data within the span of data; however, when the data is read by the BGCRC, it
always assume 32-bits and conform to the above calculation order. For example, if two 16-bit words (0xA0B1
and 0xC2D3) were placed in between the previous two 32-bit words (Table 7-4), the calculations would be
performed in byte order 0x78, 0x56, 0x34, 0x12, 0xB1, 0xA0, 0xD3, 0xC2, 0xF0, 0xDE, 0xBC, and 0x9A and
yield 0x2AEFD987.
Table 7-4. Data Address Location Example 3
Address 0x100 0x101 0x102 0x103 0x104 0x105
Data 0x5678 0x1234 0xA0B1 0xC2D3 0xDEF0 0x9ABC

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7.4 Software
7.4.1 BGCRC Examples
NOTE: These examples are located in the C2000Ware installation at the following location:
C2000Ware_VERSION#/driverlib/DEVICE_GPN/examples/CORE_IF_MULTICORE/bgcrc
Cloud access to these examples is available at the following link: dev.ti.com C2000Ware Examples.
7.4.1.1 BGCRC CPU Interrupt Example
FILE: bgcrc_ex1_cpuinterrupt.c
This example demonstrates how to configure and trigger BGCRC from the CPU. BGCRC module is configured
for 1 KB of GS0 RAM which is programmed with a known data. The pre-computed CRC value is used as the
golden CRC value. Interrupt is generated once the computation is done and checks if no error flags are raised
Calculation uses the 32-bit polynomial 0x04C11DB7 and seed value 0x00000000.
External Connections
• None.
Watch Variables
• pass - This should be 1.
• runStatus - BGCRC running status. This will be BGCRC_ACTIVE if the module is running, BGCRC_IDLE if
the module is idle
7.4.1.2 BGCRC Example with Watchdog and Lock
FILE: bgcrc_ex2_cpubgcrc_basic.c
This example demonstrates how to configure and trigger BGCRC from the CPU. It also showcases how to
configure the CRC watchdog and lock the registers after configuring the module. The watchdog is used as a
diagnostic to check memory test completion within the expected time window. An error signal is generated if the
test does not complete in the specified time window.
The module is configured for 1kB of GS0 RAM which is programmed with random data. The golden CRC value
for comparison is computed using software method. Interrupt is generated once the computation is done and
checks if no error flags are raised. The NMI is enabled and is triggered if an error is detected.
External Connections
• None.
Watch Variables
• pass
• bgcrcDone
7.4.1.3 CLA-BGCRC Example in CRC mode
FILE: bgcrc_ex3_clabgcrc_crcmode.c
This example demonstrates how to configure and trigger CLABGCRC from the CPU. It also showcases how to
configure the CRC watchdog and lock the registers after configuring the module. The watchdog is used as a
diagnostic to check memory test completion within the expected time window. An error signal is generated if the
test does not complete in the specified time window.
The module is configured for 1kB of CLA ROM memory. The golden CRC value for comparison is computed
using software method. Interrupt is generated once the computation is done and checks if no error flags are
raised. The NMI is enabled and is triggered if an error is detected.
External Connections
• None.
Watch Variables

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• pass
• bgcrcDone
7.4.1.4 CLA-BGCRC Example in Scrub Mode
FILE: bgcrc_ex4_clabgcrc_scrubmode.c
This example demonstrates how to configure and trigger CLA-BGCRC in Scrub mode. In Scrub mode, CRC of
data is not compared with the golden CRC. Error check is done using the ECC/Parity logic. It also showcases
how to configure the CRC watchdog and lock the registers after configuring the module. The watchdog is used
as a diagnostic to check memory test completion within the expected time window. An error signal is generated if
the test does not complete in the specified time window.
The module is configured for 256 bytes of CLA ROM memory. Interrupt is generated once the computation is
done and checks if no error flags are raised. The NMI is enabled and is triggered if an error is detected.
External Connections
• None.
Watch Variables
• pass
• bgcrcDone
7.5 BGCRC Registers
This section describes the Background CRC registers.
7.5.1 BGCRC Base Address Table (C28)
Table 7-5. BGCRC Base Address Table (C28)
Bit Field Name Pipeline
DriverLib Name Base Address CPU1 CPU2 DMA CLA
Instance Structure Protected

BgcrcCla1Regs BGCRC_REGS BGCRC_CLA1_BASE 0x0000_6380 YES YES - YES YES

BgcrcCpuRegs BGCRC_REGS BGCRC_CPU_BASE 0x0000_6340 YES YES - - YES

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7.5.2 BGCRC_REGS Registers

Table 7-6 lists the memory-mapped registers for the BGCRC_REGS registers. All register offset addresses not
listed in Table 7-6 should be considered as reserved locations and the register contents should not be modified.
Table 7-6. BGCRC_REGS Registers
Offset Acronym Register Name Write Protection Section
0h BGCRC_EN BGCRC Enable EALLOW Go
2h BGCRC_CTRL1 BGCRC Control register 1 EALLOW Go
4h BGCRC_CTRL2 BGCRC Control register 2 EALLOW Go
6h BGCRC_START_ADDR Start address for the BGCRC check EALLOW Go
8h BGCRC_SEED Seed for CRC calculation EALLOW Go
Eh BGCRC_GOLDEN Golden CRC to be compared against EALLOW Go
10h BGCRC_RESULT CRC calculated Go
12h BGCRC_CURR_ADDR Current address regsiter Go
1Ch BGCRC_WD_CFG BGCRC windowed watchdog configuration EALLOW Go
1Eh BGCRC_WD_MIN BGCRC windowed watchdog min value EALLOW Go
20h BGCRC_WD_MAX BGCRC windowed watchdog max value EALLOW Go
22h BGCRC_WD_CNT BGCRC windowed watchdog count Go
2Ah BGCRC_NMIFLG BGCRC NMI flag register Go
2Ch BGCRC_NMICLR BGCRC NMI flag clear register EALLOW Go
2Eh BGCRC_NMIFRC BGCRC NMI flag force register EALLOW Go
34h BGCRC_INTEN Interrupt enable EALLOW Go
36h BGCRC_INTFLG Interrupt flag Go
38h BGCRC_INTCLR Interrupt flag clear EALLOW Go
3Ah BGCRC_INTFRC Interrupt flag force EALLOW Go
3Ch BGCRC_LOCK BGCRC register map lockconfiguration EALLOW Go
3Eh BGCRC_COMMIT BGCRC register map commit configuration EALLOW Go

Complex bit access types are encoded to fit into small table cells. Table 7-7 shows the codes that are used for
access types in this section.
Table 7-7. BGCRC_REGS Access Type Codes
Access Type Code Description
Read Type
R R Read
R-0 R Read
-0 Returns 0s
Write Type
W W Write
W1S W Write
1S 1 to set
WSonce W Write
Sonce Set once
Reset or Default Value
-n Value after reset or the default
value
Register Array Variables

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Table 7-7. BGCRC_REGS Access Type Codes

(continued)
Access Type Code Description
i,j,k,l,m,n When these variables are used in
a register name, an offset, or an
address, they refer to the value of
a register array where the register
is part of a group of repeating
registers. The register groups
form a hierarchical structure and
the array is represented with a
formula.
y When this variable is used in a
register name, an offset, or an
address it refers to the value of
a register array.

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7.5.2.1 BGCRC_EN Register (Offset = 0h) [Reset = 0h]

BGCRC_EN is shown in Figure 7-7 and described in Table 7-8.
Return to the Summary Table.
BGCRC Enable
Figure 7-7. BGCRC_EN Register
31 30 29 28 27 26 25 24
RUN_STS RESERVED
R-0h R-0-0h

23 22 21 20 19 18 17 16
RESERVED
R-0-0h

15 14 13 12 11 10 9 8
RESERVED
R-0-0h

7 6 5 4 3 2 1 0
RESERVED START
R-0-0h R-0/W-0h

Table 7-8. BGCRC_EN Register Field Descriptions

Bit Field Type Reset Description
31 RUN_STS R 0h Status bit:
0 : CRC module is IDLE
1 : CRC module is Active
This bit will remain set during BGCRC_CTRL2.TEST_HALT = 1
Reset type: CPUx.SYSRSn
30-16 RESERVED R-0 0h Reserved
15-4 RESERVED R-0 0h Reserved
3-0 START R-0/W 0h Start Bit:
"1010": Kick-off CRC calculations
"any other value": ignored
Notes:
BGCRC_WD_CNT regsters will be reset CRCEN.START = "1010".
BGCRC_INTFLG, BGCRC_NMIFLG will not be impacted by this
configuration.
This bit should not be set before the previous CRC computation
completes.
Reset type: CPUx.SYSRSn

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7.5.2.2 BGCRC_CTRL1 Register (Offset = 2h) [Reset = 0h]

BGCRC_CTRL1 is shown in Figure 7-8 and described in Table 7-9.
Return to the Summary Table.
BGCRC Control register 1
Figure 7-8. BGCRC_CTRL1 Register
31 30 29 28 27 26 25 24
RESERVED
R-0-0h

23 22 21 20 19 18 17 16
RESERVED NMIDIS
R-0-0h R/W-0h

15 14 13 12 11 10 9 8
RESERVED
R-0-0h

7 6 5 4 3 2 1 0
RESERVED FREE_SOFT RESERVED
R-0-0h R/W-0h R-0-0h

Table 7-9. BGCRC_CTRL1 Register Field Descriptions

Bit Field Type Reset Description
31-20 RESERVED R-0 0h Reserved
19-16 NMIDIS R/W 0h 1010 : NMI is disabled
Any other value : NMI is enabled.
Reset type: CPUx.SYSRSn
15-5 RESERVED R-0 0h Reserved
4 FREE_SOFT R/W 0h Emulation control bit : This bit controls behaviour of CRC calculation
during emulation
0 : Soft, CRC module and CRC Watchdog stops immediately on
DEBUG SUSPEND (of CRC-controller ).
1 : Free, CRC calcuation and CRC watchdog is not affected by
DEBUG HALT (of CRC-controller )
Reset type: CPUx.SYSRSn
3-0 RESERVED R-0 0h Reserved

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7.5.2.3 BGCRC_CTRL2 Register (Offset = 4h) [Reset = 0h]

BGCRC_CTRL2 is shown in Figure 7-9 and described in Table 7-10.
Return to the Summary Table.
BGCRC Control register 2
Figure 7-9. BGCRC_CTRL2 Register
31 30 29 28 27 26 25 24
RESERVED
R-0-0h

23 22 21 20 19 18 17 16
RESERVED SCRUB_MODE
R-0-0h R/W-0h

15 14 13 12 11 10 9 8
TEST_HALT RESERVED BLOCK_SIZE
R/W-0h R-0-0h R/W-0h

7 6 5 4 3 2 1 0
BLOCK_SIZE
R/W-0h

Table 7-10. BGCRC_CTRL2 Register Field Descriptions

Bit Field Type Reset Description
31-20 RESERVED R-0 0h Reserved
19-16 SCRUB_MODE R/W 0h Scrub mode configuration
1010 : Scrub mode, CRC of data is not compared with the golden
CRC. Error check is done using the ECC/Parity logic.
Any other value: CRC value is compared with golden CRC at the end
in addition to the data correctness check by ECC/Parity logic.
Notes:
1010 configuration is used for scrub mode (for data memories)
where the memory value is read and ECC/Parity logic is used for
the error detection. BGCRC_RESULT.CRC_VALUE is not updated in
this configuration.
Reset type: CPUx.SYSRSn
15-12 TEST_HALT R/W 0h Halt Bit :
1010 : Module operation is stopped
Any other value : CRC calaculation will continue/resume from where
it was halted
Notes:
BGCRC_EN.START = 1010 configuration with TEST_HALT = 1010
will halt the CRC calculation. The new check will resume when
TEST_HALT is configured to a value other than 1010
Reset type: CPUx.SYSRSn
11-10 RESERVED R-0 0h Reserved
9-0 BLOCK_SIZE R/W 0h Configures the block size for the check
0x0 : 256 Byte (default)
0x1 : 512 Byte
0x2 : 768 Byte
0x3 : 1KB
...
0x3FF : 256KB
(0xn : (n+1)*256Byte)
Reset type: CPUx.SYSRSn

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7.5.2.4 BGCRC_START_ADDR Register (Offset = 6h) [Reset = 0h]

BGCRC_START_ADDR is shown in Figure 7-10 and described in Table 7-11.
Return to the Summary Table.
Start address for the BGCRC check
Figure 7-10. BGCRC_START_ADDR Register
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
START_ADDRESS
R/W-0h

Table 7-11. BGCRC_START_ADDR Register Field Descriptions

Bit Field Type Reset Description
31-0 START_ADDRESS R/W 0h START_ADDRESS indicates the start point of the test.
(For CPU_CRC, this will be the CPU address. For CLA_CRC, this
will be the CLA address where the memory is mapped)
Reset type: CPUx.SYSRSn

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7.5.2.5 BGCRC_SEED Register (Offset = 8h) [Reset = 0h]

BGCRC_SEED is shown in Figure 7-11 and described in Table 7-12.
Return to the Summary Table.
Seed for CRC calculation
Figure 7-11. BGCRC_SEED Register
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SEED
R/W-0h

Table 7-12. BGCRC_SEED Register Field Descriptions

Bit Field Type Reset Description
31-0 SEED R/W 0h Initial value of CRC, this value is coiped to the CRC register on
triggering CRC calculation by writing to START bit.
Reset type: CPUx.SYSRSn

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7.5.2.6 BGCRC_GOLDEN Register (Offset = Eh) [Reset = 0h]

BGCRC_GOLDEN is shown in Figure 7-12 and described in Table 7-13.
Return to the Summary Table.
Golden CRC to be compared against
Figure 7-12. BGCRC_GOLDEN Register
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CRC_VALUE
R/W-0h

Table 7-13. BGCRC_GOLDEN Register Field Descriptions

Bit Field Type Reset Description
31-0 CRC_VALUE R/W 0h Golden CRC register:
If CRC check is enabled, the calcuated CRC value is compared with
golden CRC and status is updated.
Reset type: CPUx.SYSRSn

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7.5.2.7 BGCRC_RESULT Register (Offset = 10h) [Reset = 0h]

BGCRC_RESULT is shown in Figure 7-13 and described in Table 7-14.
Return to the Summary Table.
CRC calculated
Figure 7-13. BGCRC_RESULT Register
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CRC_VALUE
R-0h

Table 7-14. BGCRC_RESULT Register Field Descriptions

Bit Field Type Reset Description
31-0 CRC_VALUE R 0h CRC result register
This reister value will be updated only on the completion
of CRC check on a block of data as programmed by
BGCRC_CTRL2.BLOCK_SIZE.
Reset type: CPUx.SYSRSn

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7.5.2.8 BGCRC_CURR_ADDR Register (Offset = 12h) [Reset = 0h]

BGCRC_CURR_ADDR is shown in Figure 7-14 and described in Table 7-15.
Return to the Summary Table.
Current address regsiter
Figure 7-14. BGCRC_CURR_ADDR Register
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CURRENT_ADDR
R-0h

Table 7-15. BGCRC_CURR_ADDR Register Field Descriptions

Bit Field Type Reset Description
31-0 CURRENT_ADDR R 0h Current address from where the data is fetched.
During a failure, the CURRENT_ADDR field indicates the value from
where the last fetch happened.
Reset type: CPUx.SYSRSn

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7.5.2.9 BGCRC_WD_CFG Register (Offset = 1Ch) [Reset = 0h]

BGCRC_WD_CFG is shown in Figure 7-15 and described in Table 7-16.
Return to the Summary Table.
BGCRC windowed watchdog configuration
Figure 7-15. BGCRC_WD_CFG Register
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
RESERVED
R-0-0h

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RESERVED WDDIS
R-0-0h R/W-0h

Table 7-16. BGCRC_WD_CFG Register Field Descriptions

Bit Field Type Reset Description
31-4 RESERVED R-0 0h Reserved
3-0 WDDIS R/W 0h 1010: CRC Watchdog counter is disabled.
Any other value: CRC watchdog is enabled
Watchdog is an upcounter and starts counting when
BGCRC_EN.START is asserted. Watchdog continues to count during
TEST_HALT state also(BGCRC_CTRL2.TEST_HALT = "1010").
CRC watchdog can be disabled during TEST_HALT by explicit
configuration. (BGCRC_WD_CFG.WDDIS = 1010). Once the
watchdog is disabled and re-enabled, watchdog count resumes from
the previous disabled point.
Reset type: CPUx.SYSRSn

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7.5.2.10 BGCRC_WD_MIN Register (Offset = 1Eh) [Reset = 0h]

BGCRC_WD_MIN is shown in Figure 7-16 and described in Table 7-17.
Return to the Summary Table.
BGCRC windowed watchdog min value
Figure 7-16. BGCRC_WD_MIN Register
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
MINVAL
R/W-0h

Table 7-17. BGCRC_WD_MIN Register Field Descriptions

Bit Field Type Reset Description
31-0 MINVAL R/W 0h If the CRC computation completes before
BGCRC_WD_MIN.MINVAL FAIL_STATUS.WD_UNDERFLOW flag
gets set.
Reset type: CPUx.SYSRSn

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7.5.2.11 BGCRC_WD_MAX Register (Offset = 20h) [Reset = FFFFFFFFh]

BGCRC_WD_MAX is shown in Figure 7-17 and described in Table 7-18.
Return to the Summary Table.
BGCRC windowed watchdog max value
Figure 7-17. BGCRC_WD_MAX Register
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
MAXVAL
R/W-FFFFFFFFh

Table 7-18. BGCRC_WD_MAX Register Field Descriptions

Bit Field Type Reset Description
31-0 MAXVAL R/W FFFFFFFFh If the CRC computation doesn't complete before
BGCRC_WD_MIN.MAXVAL FAIL_STATUS.WD_OVERFLOW flag
gets set.
Reset type: CPUx.SYSRSn

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7.5.2.12 BGCRC_WD_CNT Register (Offset = 22h) [Reset = 0h]

BGCRC_WD_CNT is shown in Figure 7-18 and described in Table 7-19.
Return to the Summary Table.
BGCRC windowed watchdog count
Figure 7-18. BGCRC_WD_CNT Register
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
WD_CNT
R-0h

Table 7-19. BGCRC_WD_CNT Register Field Descriptions

Bit Field Type Reset Description
31-0 WD_CNT R 0h CRC windowed watchdog counter value
Counter value freezes at the end of CRC computation and will
be reloaded only by BGCRC_EN.START = "1010" configuration.
BGCRC_WD_CNT register freezes when a failure occurs.
Reset type: CPUx.SYSRSn

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7.5.2.13 BGCRC_NMIFLG Register (Offset = 2Ah) [Reset = 0h]

BGCRC_NMIFLG is shown in Figure 7-19 and described in Table 7-20.
Return to the Summary Table.
BGCRC NMI flag register
Figure 7-19. BGCRC_NMIFLG Register
31 30 29 28 27 26 25 24
RESERVED
R-0-0h

23 22 21 20 19 18 17 16
RESERVED
R-0-0h

15 14 13 12 11 10 9 8
RESERVED
R-0-0h

7 6 5 4 3 2 1 0
RESERVED WD_OVERFLO WD_UNDERFL CORRECTABL UNCORRECTA CRC_FAIL RESERVED RESERVED
W OW E_ERR BLE_ERR
R-0-0h R-0h R-0h R-0h R-0h R-0h R-0-0h R-0-0h

Table 7-20. BGCRC_NMIFLG Register Field Descriptions

Bit Field Type Reset Description
31-7 RESERVED R-0 0h Reserved
6 WD_OVERFLOW R 0h Windowed watchdog Overflow.
1 : Test did not complete before BGCRC_WD_MAX.MAXVAL
0 : No such errors
Reset type: CPUx.SYSRSn
5 WD_UNDERFLOW R 0h Windowed watchdog underflow.
1 : Test completed before BGCRC_WD_MIN.MINVAL
0 : No such errors
Reset type: CPUx.SYSRSn
4 CORRECTABLE_ERR R 0h Correctable error indication:
0 : No ECC correctable error during memory read
1 : Correctable ECC error during memory read
Note: ECC computation is done during every memory read.
(Correctable errors are not ignored since the module doesn't write-
back corrected value. The error remains in the memory and required
corrective action need to be taken by CPU/CLA as part of ISR)
Reset type: CPUx.SYSRSn
3 UNCORRECTABLE_ERR R 0h Uncorrectable error indication:
0 : No ECC-uncorrectable/Parity error during memory read
1 : ECC-uncorrectable/Parity error during memory read
Note: ECC/Parity check is done during every memory read.
Reset type: CPUx.SYSRSn
2 CRC_FAIL R 0h CRC FAIL interrupt
0 : No failure in CRC check.
1 : CRC check failure
Note: Comparion is enabled only after CRC calc is completed
Reset type: CPUx.SYSRSn
1 RESERVED R-0 0h Reserved
0 RESERVED R-0 0h Reserved

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7.5.2.14 BGCRC_NMICLR Register (Offset = 2Ch) [Reset = 0h]

BGCRC_NMICLR is shown in Figure 7-20 and described in Table 7-21.
Return to the Summary Table.
BGCRC NMI flag clear register
Figure 7-20. BGCRC_NMICLR Register
31 30 29 28 27 26 25 24
RESERVED
R-0-0h

23 22 21 20 19 18 17 16
RESERVED
R-0-0h

15 14 13 12 11 10 9 8
RESERVED
R-0-0h

7 6 5 4 3 2 1 0
RESERVED WD_OVERFLO WD_UNDERFL CORRECTABL UNCORRECTA CRC_FAIL RESERVED RESERVED
W OW E_ERR BLE_ERR
R-0-0h R-0/W1S-0h R-0/W1S-0h R-0/W1S-0h R-0/W1S-0h R-0/W1S-0h R-0-0h R-0-0h

Table 7-21. BGCRC_NMICLR Register Field Descriptions

Bit Field Type Reset Description
31-7 RESERVED R-0 0h Reserved
6 WD_OVERFLOW R-0/W1S 0h Clear WD_OVERFLOW NMI flag
0 No effect
1 Clears NMI flag
Reset type: CPUx.SYSRSn
5 WD_UNDERFLOW R-0/W1S 0h Clear WD_UNDERFLOW NMI flag
0 No effect
1 Clears NMI flag
Reset type: CPUx.SYSRSn
4 CORRECTABLE_ERR R-0/W1S 0h Clear CORRECTABLE_ERR NMI flag
0 No effect
1 Clears NMI flag
Reset type: CPUx.SYSRSn
3 UNCORRECTABLE_ERR R-0/W1S 0h Clear UNCORRECTABLE_ERROR NMI flag
0 No effect
1 Clears NMI flag
Reset type: CPUx.SYSRSn
2 CRC_FAIL R-0/W1S 0h Clear CRC_FAIL NMI flag
0 No effect
1 Clears NMI flag
Reset type: CPUx.SYSRSn
1 RESERVED R-0 0h Reserved
0 RESERVED R-0 0h Reserved

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7.5.2.15 BGCRC_NMIFRC Register (Offset = 2Eh) [Reset = 0h]

BGCRC_NMIFRC is shown in Figure 7-21 and described in Table 7-22.
Return to the Summary Table.
BGCRC NMI flag force register
Figure 7-21. BGCRC_NMIFRC Register
31 30 29 28 27 26 25 24
RESERVED
R-0-0h

23 22 21 20 19 18 17 16
RESERVED
R-0-0h

15 14 13 12 11 10 9 8
RESERVED
R-0-0h

7 6 5 4 3 2 1 0
RESERVED WD_OVERFLO WD_UNDERFL CORRECTABL UNCORRECTA CRC_FAIL RESERVED RESERVED
W OW E_ERR BLE_ERR
R-0-0h R-0/W1S-0h R-0/W1S-0h R-0/W1S-0h R-0/W1S-0h R-0/W1S-0h R-0-0h R-0-0h

Table 7-22. BGCRC_NMIFRC Register Field Descriptions

Bit Field Type Reset Description
31-7 RESERVED R-0 0h Reserved
6 WD_OVERFLOW R-0/W1S 0h Force WD_OVERFLOW NMI flag
0 No effect
1 force NMI flag
Reset type: CPUx.SYSRSn
5 WD_UNDERFLOW R-0/W1S 0h Force WD_UNDERFLOW NMI flag
0 No effect
1 force NMI flag
Reset type: CPUx.SYSRSn
4 CORRECTABLE_ERR R-0/W1S 0h Force CORRECTABLE_ERR NMI flag
0 No effect
1 force NMI flag
Reset type: CPUx.SYSRSn
3 UNCORRECTABLE_ERR R-0/W1S 0h Force UNCORRECTABLE_ERR NMI flag
0 No effect
1 force NMI flag
Reset type: CPUx.SYSRSn
2 CRC_FAIL R-0/W1S 0h Force CRC_FAIL NMI flag
0 No effect
1 force NMI flag
Reset type: CPUx.SYSRSn
1 RESERVED R-0 0h Reserved
0 RESERVED R-0 0h Reserved

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7.5.2.16 BGCRC_INTEN Register (Offset = 34h) [Reset = 0h]

BGCRC_INTEN is shown in Figure 7-22 and described in Table 7-23.
Return to the Summary Table.
Interrupt enable
Figure 7-22. BGCRC_INTEN Register
31 30 29 28 27 26 25 24
RESERVED
R-0h

23 22 21 20 19 18 17 16
RESERVED
R-0h

15 14 13 12 11 10 9 8
RESERVED
R-0h

7 6 5 4 3 2 1 0
RESERVED WD_OVERFLO WD_UNDERFL CORRECTABL UNCORRECTA CRC_FAIL TEST_DONE RESERVED
W OW E_ERR BLE_ERR
R-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R-0-0h

Table 7-23. BGCRC_INTEN Register Field Descriptions

Bit Field Type Reset Description
31-7 RESERVED R 0h Reserved
6 WD_OVERFLOW R/W 0h 0 WD_OVERFLOW Interrupt disabled
1 WD_OVERFLOW Interrupt enabled
Reset type: CPUx.SYSRSn
5 WD_UNDERFLOW R/W 0h 0 WD_UNDERFLOW Interrupt disabled
1 WD_UNDERFLOW Interrupt enabled
Reset type: CPUx.SYSRSn
4 CORRECTABLE_ERR R/W 0h 0 CORRECTABLE_ERR Interrupt disabled
1 CORRECTABLE_ERR Interrupt enabled
Reset type: CPUx.SYSRSn
3 UNCORRECTABLE_ERR R/W 0h 0 UNCORRECTABLE_ERR Interrupt disabled
1 UNCORRECTABLE_ERR Interrupt enabled
Reset type: CPUx.SYSRSn
2 CRC_FAIL R/W 0h 0 CRC_FAIL Interrupt disabled
1 CRC_FAIL Interrupt enabled
Reset type: CPUx.SYSRSn
1 TEST_DONE R/W 0h 0 TEST_DONE Interrupt disabled
1 TEST_DONE Interrupt enabled
Reset type: CPUx.SYSRSn
0 RESERVED R-0 0h Reserved

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7.5.2.17 BGCRC_INTFLG Register (Offset = 36h) [Reset = 0h]

BGCRC_INTFLG is shown in Figure 7-23 and described in Table 7-24.
Return to the Summary Table.
Interrupt flag
Figure 7-23. BGCRC_INTFLG Register
31 30 29 28 27 26 25 24
RESERVED
R-0-0h

23 22 21 20 19 18 17 16
RESERVED
R-0-0h

15 14 13 12 11 10 9 8
RESERVED
R-0-0h

7 6 5 4 3 2 1 0
RESERVED WD_OVERFLO WD_UNDERFL CORRECTABL UNCORRECTA CRC_FAIL TEST_DONE INT
W OW E_ERR BLE_ERR
R-0-0h R-0h R-0h R-0h R-0h R-0h R-0h R-0h

Table 7-24. BGCRC_INTFLG Register Field Descriptions

Bit Field Type Reset Description
31-7 RESERVED R-0 0h Reserved
6 WD_OVERFLOW R 0h Windowed watchdog Overflow.
1 : Test did not completed before BGCRC_WD_MAX.MAXVAL
0 : No such errors
Reset type: CPUx.SYSRSn
5 WD_UNDERFLOW R 0h Windowed watchdog underflow.
1 : Test completed before BGCRC_WD_MIN.MINVAL
0 : No such errors
Reset type: CPUx.SYSRSn
4 CORRECTABLE_ERR R 0h Correctable error indication:
0 : No ECC correctable error during memory read
1 : Correctable ECC error during memory read
Note: ECC computation is done during every memory read.
(Correctable errors are not ignored since the module doesn't write-
back corrected value. The error remains in the memory and required
corrective action need to be taken by CPU/CLA as part of ISR)
Reset type: CPUx.SYSRSn
3 UNCORRECTABLE_ERR R 0h uncorrectable error indication:
0 : No ECC-uncorrectable/Parity error during memory read
1 : ECC-uncorrectable/Parity error during memory read
Note: ECC/Parity check is done during every memory read.
Reset type: CPUx.SYSRSn
2 CRC_FAIL R 0h CRC fail interrupt
0 : No failure of CRC check
1 : CRC check failure
Note: Comparion is enabled only after CRC calc is completed
Reset type: CPUx.SYSRSn
1 TEST_DONE R 0h Done Interrupt Status flag
0 CRC calculation is in progress or CRC module is idle.
1 CRC calculation is done.
Note: TEST_DONE flag will get set on CRC calculation completion
even in case of CRC mismatch
Reset type: CPUx.SYSRSn

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Table 7-24. BGCRC_INTFLG Register Field Descriptions (continued)

Bit Field Type Reset Description
0 INT R 0h Global Interrupt Status flag
0 No interrupt generated
1 Interrupt was generated
Reset type: CPUx.SYSRSn

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7.5.2.18 BGCRC_INTCLR Register (Offset = 38h) [Reset = 0h]

BGCRC_INTCLR is shown in Figure 7-24 and described in Table 7-25.
Return to the Summary Table.
Interrupt flag clear
Figure 7-24. BGCRC_INTCLR Register
31 30 29 28 27 26 25 24
RESERVED
R-0-0h

23 22 21 20 19 18 17 16
RESERVED
R-0-0h

15 14 13 12 11 10 9 8
RESERVED
R-0-0h

7 6 5 4 3 2 1 0
RESERVED WD_OVERFLO WD_UNDERFL CORRECTABL UNCORRECTA CRC_FAIL TEST_DONE INT
W OW E_ERR BLE_ERR
R-0-0h R-0/W1S-0h R-0/W1S-0h R-0/W1S-0h R-0/W1S-0h R-0/W1S-0h R-0/W1S-0h R-0/W1S-0h

Table 7-25. BGCRC_INTCLR Register Field Descriptions

Bit Field Type Reset Description
31-7 RESERVED R-0 0h Reserved
6 WD_OVERFLOW R-0/W1S 0h Clear interrupt flag
0 No effect
1 Clears the interrupt flag
Reset type: CPUx.SYSRSn
5 WD_UNDERFLOW R-0/W1S 0h Clear interrupt flag
0 No effect
1 Clears the interrupt flag
Reset type: CPUx.SYSRSn
4 CORRECTABLE_ERR R-0/W1S 0h Clear interrupt flag
0 No effect
1 Clears the interrupt flag
Reset type: CPUx.SYSRSn
3 UNCORRECTABLE_ERR R-0/W1S 0h Clear interrupt flag
0 No effect
1 Clears the interrupt flag
Reset type: CPUx.SYSRSn
2 CRC_FAIL R-0/W1S 0h Clear interrupt flag
0 No effect
1 Clears the interrupt flag
Reset type: CPUx.SYSRSn
1 TEST_DONE R-0/W1S 0h Clear interrupt flag
0 No effect
1 Clears the interrupt flag
Reset type: CPUx.SYSRSn
0 INT R-0/W1S 0h Global Interrupt Clear
0 No effect
1 Clears the interrupt flag and enables further interrupts to be
generated if an event flags is set to 1.
Reset type: CPUx.SYSRSn

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7.5.2.19 BGCRC_INTFRC Register (Offset = 3Ah) [Reset = 0h]

BGCRC_INTFRC is shown in Figure 7-25 and described in Table 7-26.
Return to the Summary Table.
Interrupt flag force
Figure 7-25. BGCRC_INTFRC Register
31 30 29 28 27 26 25 24
RESERVED
R-0-0h

23 22 21 20 19 18 17 16
RESERVED
R-0-0h

15 14 13 12 11 10 9 8
RESERVED
R-0-0h

7 6 5 4 3 2 1 0
RESERVED WD_OVERFLO WD_UNDERFL CORRECTABL UNCORRECTA CRC_FAIL TEST_DONE RESERVED
W OW E_ERR BLE_ERR
R-0-0h R-0/W1S-0h R-0/W1S-0h R-0/W1S-0h R-0/W1S-0h R-0/W1S-0h R-0/W1S-0h R-0-0h

Table 7-26. BGCRC_INTFRC Register Field Descriptions

Bit Field Type Reset Description
31-7 RESERVED R-0 0h Reserved
6 WD_OVERFLOW R-0/W1S 0h Force interrupt flag
0 No effect
1 force the interrupt flag
Reset type: CPUx.SYSRSn
5 WD_UNDERFLOW R-0/W1S 0h Force interrupt flag
0 No effect
1 force the interrupt flag
Reset type: CPUx.SYSRSn
4 CORRECTABLE_ERR R-0/W1S 0h Force interrupt flag
0 No effect
1 force the interrupt flag
Reset type: CPUx.SYSRSn
3 UNCORRECTABLE_ERR R-0/W1S 0h Force interrupt flag
0 No effect
1 force the interrupt flag
Reset type: CPUx.SYSRSn
2 CRC_FAIL R-0/W1S 0h Force interrupt flag
0 No effect
1 force the interrupt flag
Reset type: CPUx.SYSRSn
1 TEST_DONE R-0/W1S 0h Force interrupt flag
0 No effect
1 force the interrupt flag
Reset type: CPUx.SYSRSn
0 RESERVED R-0 0h Reserved

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7.5.2.20 BGCRC_LOCK Register (Offset = 3Ch) [Reset = 0h]

BGCRC_LOCK is shown in Figure 7-26 and described in Table 7-27.
Return to the Summary Table.
BGCRC register map lockconfiguration
Figure 7-26. BGCRC_LOCK Register
31 30 29 28 27 26 25 24
RESERVED RESERVED BGCRC_INTFR RESERVED RESERVED BGCRC_INTEN RESERVED RESERVED
C
R-0-0h R-0-0h R/W-0h R-0-0h R-0-0h R/W-0h R-0-0h R-0-0h

23 22 21 20 19 18 17 16
BGCRC_NMIF RESERVED RESERVED RESERVED RESERVED RESERVED RESERVED BGCRC_WD_M
RC AX
R/W-0h R-0-0h R-0-0h R-0-0h R-0-0h R-0-0h R-0-0h R/W-0h

15 14 13 12 11 10 9 8
BGCRC_WD_M BGCRC_WD_C RESERVED RESERVED RESERVED RESERVED RESERVED RESERVED
IN FG
R/W-0h R/W-0h R-0-0h R-0-0h R-0-0h R-0-0h R-0-0h R-0-0h

7 6 5 4 3 2 1 0
BGCRC_GOLD RESERVED RESERVED BGCRC_SEED BGCRC_STAR BGCRC_CTRL BGCRC_CTRL BGCRC_EN
EN T_ADDR 2 1
R/W-0h R-0-0h R-0-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h

Table 7-27. BGCRC_LOCK Register Field Descriptions

Bit Field Type Reset Description
31 RESERVED R-0 0h Reserved
30 RESERVED R-0 0h Reserved
29 BGCRC_INTFRC R/W 0h 0: Register configuration is not locked.
1: Register configuration is locked.
Reset type: CPUx.SYSRSn
28 RESERVED R-0 0h Reserved
27 RESERVED R-0 0h Reserved
26 BGCRC_INTEN R/W 0h 0: Register configuration is not locked.
1: Register configuration is locked.
Reset type: CPUx.SYSRSn
25 RESERVED R-0 0h Reserved
24 RESERVED R-0 0h Reserved
23 BGCRC_NMIFRC R/W 0h 0: Register configuration is not locked.
1: Register configuration is locked.
Reset type: CPUx.SYSRSn
22 RESERVED R-0 0h Reserved
21 RESERVED R-0 0h Reserved
20 RESERVED R-0 0h Reserved
19 RESERVED R-0 0h Reserved
18 RESERVED R-0 0h Reserved
17 RESERVED R-0 0h Reserved
16 BGCRC_WD_MAX R/W 0h 0: Register configuration is not locked.
1: Register configuration is locked.
Reset type: CPUx.SYSRSn

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Table 7-27. BGCRC_LOCK Register Field Descriptions (continued)

Bit Field Type Reset Description
15 BGCRC_WD_MIN R/W 0h 0: Register configuration is not locked.
1: Register configuration is locked.
Reset type: CPUx.SYSRSn
14 BGCRC_WD_CFG R/W 0h 0: Register configuration is not locked.
1: Register configuration is locked.
Reset type: CPUx.SYSRSn
13 RESERVED R-0 0h Reserved
12 RESERVED R-0 0h Reserved
11 RESERVED R-0 0h Reserved
10 RESERVED R-0 0h Reserved
9 RESERVED R-0 0h Reserved
8 RESERVED R-0 0h Reserved
7 BGCRC_GOLDEN R/W 0h 0: Register configuration is not locked.
1: Register configuration is locked.
Reset type: CPUx.SYSRSn
6 RESERVED R-0 0h Reserved
5 RESERVED R-0 0h Reserved
4 BGCRC_SEED R/W 0h 0: Register configuration is not locked.
1: Register configuration is locked.
Reset type: CPUx.SYSRSn
3 BGCRC_START_ADDR R/W 0h 0: Register configuration is not locked.
1: Register configuration is locked.
Reset type: CPUx.SYSRSn
2 BGCRC_CTRL2 R/W 0h 0: Register configuration is not locked.
1: Register configuration is locked.
Reset type: CPUx.SYSRSn
1 BGCRC_CTRL1 R/W 0h 0: Register configuration is not locked.
1: Register configuration is locked.
Reset type: CPUx.SYSRSn
0 BGCRC_EN R/W 0h 0: Register configuration is not locked.
1: Register configuration is locked.
Reset type: CPUx.SYSRSn

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7.5.2.21 BGCRC_COMMIT Register (Offset = 3Eh) [Reset = 0h]

BGCRC_COMMIT is shown in Figure 7-27 and described in Table 7-28.
Return to the Summary Table.
BGCRC register map commit configuration
Figure 7-27. BGCRC_COMMIT Register
31 30 29 28 27 26 25 24
RESERVED RESERVED BGCRC_INTFR RESERVED RESERVED BGCRC_INTEN RESERVED RESERVED
C
R-0-0h R-0-0h R/WSonce-0h R-0-0h R-0-0h R/WSonce-0h R-0-0h R-0-0h

23 22 21 20 19 18 17 16
BGCRC_NMIF RESERVED RESERVED RESERVED RESERVED RESERVED RESERVED BGCRC_WD_M
RC AX
R/WSonce-0h R-0-0h R-0-0h R-0-0h R-0-0h R-0-0h R-0-0h R/WSonce-0h

15 14 13 12 11 10 9 8
BGCRC_WD_M BGCRC_WD_C RESERVED RESERVED RESERVED RESERVED RESERVED RESERVED
IN FG
R/WSonce-0h R/WSonce-0h R-0-0h R-0-0h R-0-0h R-0-0h R-0-0h R-0-0h

7 6 5 4 3 2 1 0
BGCRC_GOLD RESERVED RESERVED BGCRC_SEED BGCRC_STAR BGCRC_CTRL BGCRC_CTRL BGCRC_EN
EN T_ADDR 2 1
R/WSonce-0h R-0-0h R-0-0h R/WSonce-0h R/WSonce-0h R/WSonce-0h R/WSonce-0h R/WSonce-0h

Table 7-28. BGCRC_COMMIT Register Field Descriptions

Bit Field Type Reset Description
31 RESERVED R-0 0h Reserved
30 RESERVED R-0 0h Reserved
29 BGCRC_INTFRC R/WSonce 0h 0: Register lock configuration is not committed.
1: Register configuration is committed.
Once configuration is committed, only reset can change the
configuration.
Reset type: CPUx.SYSRSn
28 RESERVED R-0 0h Reserved
27 RESERVED R-0 0h Reserved
26 BGCRC_INTEN R/WSonce 0h 0: Register lock configuration is not committed.
1: Register configuration is committed.
Once configuration is committed, only reset can change the
configuration.
Reset type: CPUx.SYSRSn
25 RESERVED R-0 0h Reserved
24 RESERVED R-0 0h Reserved
23 BGCRC_NMIFRC R/WSonce 0h 0: Register lock configuration is not committed.
1: Register configuration is committed.
Once configuration is committed, only reset can change the
configuration.
Reset type: CPUx.SYSRSn
22 RESERVED R-0 0h Reserved
21 RESERVED R-0 0h Reserved
20 RESERVED R-0 0h Reserved
19 RESERVED R-0 0h Reserved
18 RESERVED R-0 0h Reserved

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Table 7-28. BGCRC_COMMIT Register Field Descriptions (continued)

Bit Field Type Reset Description
17 RESERVED R-0 0h Reserved
16 BGCRC_WD_MAX R/WSonce 0h 0: Register lock configuration is not committed.
1: Register configuration is committed.
Once configuration is committed, only reset can change the
configuration.
Reset type: CPUx.SYSRSn
15 BGCRC_WD_MIN R/WSonce 0h 0: Register lock configuration is not committed.
1: Register configuration is committed.
Once configuration is committed, only reset can change the
configuration.
Reset type: CPUx.SYSRSn
14 BGCRC_WD_CFG R/WSonce 0h 0: Register lock configuration is not committed.
1: Register configuration is committed.
Once configuration is committed, only reset can change the
configuration.
Reset type: CPUx.SYSRSn
13 RESERVED R-0 0h Reserved
12 RESERVED R-0 0h Reserved
11 RESERVED R-0 0h Reserved
10 RESERVED R-0 0h Reserved
9 RESERVED R-0 0h Reserved
8 RESERVED R-0 0h Reserved
7 BGCRC_GOLDEN R/WSonce 0h 0: Register lock configuration is not committed.
1: Register configuration is committed.
Once configuration is committed, only reset can change the
configuration.
Reset type: CPUx.SYSRSn
6 RESERVED R-0 0h Reserved
5 RESERVED R-0 0h Reserved
4 BGCRC_SEED R/WSonce 0h 0: Register lock configuration is not committed.
1: Register configuration is committed.
Once configuration is committed, only reset can change the
configuration.
Reset type: CPUx.SYSRSn
3 BGCRC_START_ADDR R/WSonce 0h 0: Register lock configuration is not committed.
1: Register configuration is committed.
Once configuration is committed, only reset can change the
configuration.
Reset type: CPUx.SYSRSn
2 BGCRC_CTRL2 R/WSonce 0h 0: Register lock configuration is not committed.
1: Register configuration is committed.
Once configuration is committed, only reset can change the
configuration.
Reset type: CPUx.SYSRSn
1 BGCRC_CTRL1 R/WSonce 0h 0: Register lock configuration is not committed.
1: Register configuration is committed.
Once configuration is committed, only reset can change the
configuration.
Reset type: CPUx.SYSRSn
0 BGCRC_EN R/WSonce 0h 0: Register lock configuration is not committed.
1: Register configuration is committed.
Once configuration is committed, only reset can change the
configuration.
Reset type: CPUx.SYSRSn

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7.5.3 BGCRC Registers to Driverlib Functions

Table 7-29. BGCRC Registers to Driverlib Functions
File Driverlib Function
EN
bgcrc.h BGCRC_start
bgcrc.h BGCRC_getRunStatus
CTRL1
bgcrc.h BGCRC_setConfig
CTRL2
bgcrc.h BGCRC_setRegion
bgcrc.h BGCRC_halt
bgcrc.h BGCRC_resume
START_ADDR
bgcrc.h BGCRC_setRegion
SEED
bgcrc.h BGCRC_setSeedValue
GOLDEN
bgcrc.h BGCRC_setGoldenCRCValue
RESULT
bgcrc.h BGCRC_getResult
CURR_ADDR
bgcrc.h BGCRC_getCurrentAddress
WD_CFG
bgcrc.h BGCRC_enableWatchdog
bgcrc.h BGCRC_disableWatchdog
WD_MIN
bgcrc.h BGCRC_setWatchdogWindow
WD_MAX
bgcrc.h BGCRC_setWatchdogWindow
WD_CNT
bgcrc.h BGCRC_getWatchdogCounterValue
NMIFLG
bgcrc.h BGCRC_getNMIStatus
NMICLR
bgcrc.h BGCRC_clearNMIStatus
NMIFRC
bgcrc.h BGCRC_forceNMI
INTEN
bgcrc.h BGCRC_enableInterrupt
bgcrc.h BGCRC_disableInterrupt
INTFLG
bgcrc.h BGCRC_getInterruptStatus
INTCLR
bgcrc.h BGCRC_clearInterruptStatus
INTFRC
bgcrc.h BGCRC_forceInterrupt
LOCK

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Table 7-29. BGCRC Registers to Driverlib Functions (continued)

File Driverlib Function
bgcrc.h BGCRC_lockRegister
bgcrc.h BGCRC_unlockRegister
COMMIT
bgcrc.h BGCRC_commitRegisterLock

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www.ti.com Control Law Accelerator (CLA)

Chapter 8
Control Law Accelerator (CLA)

The Control Law Accelerator (CLA) Type-2 is an independent, fully-programmable, 32-bit floating-point math
processor that brings concurrent control-loop execution to the C28x family. The low interrupt latency of the
CLA allows the CLA to read ADC samples "just-in-time." This significantly reduces the ADC sample to output
delay to enable faster system response and higher MHz control loops. By using the CLA to service time-critical
control loops, the main CPU is free to perform other system tasks such as communications and diagnostics. This
chapter provides an overview of the architectural structure and components of the control law accelerator.

8.1 Introduction...............................................................................................................................................................966
8.2 CLA Interface............................................................................................................................................................ 968
8.3 CLA, DMA, and CPU Arbitration..............................................................................................................................975
8.4 CLA Configuration and Debug................................................................................................................................ 977
8.5 Pipeline......................................................................................................................................................................982
8.6 Software.................................................................................................................................................................... 989
8.7 Instruction Set...........................................................................................................................................................994
8.8 CLA Registers......................................................................................................................................................... 1116

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8.1 Introduction
The Control Law Accelerator extends the capabilities of the C28x CPU by adding parallel processing. Time-
critical control loops serviced by the CLA can achieve low ADC sample to output delay. Thus, the CLA enables
faster system response and higher frequency control loops. Utilizing the CLA for time-critical tasks frees up the
main CPU to perform other system and communication functions concurrently.
8.1.1 Features
The following is a list of major features of the CLA:
• C compilers are available for CLA software development.
• Clocked at the same rate as the main CPU (SYSCLKOUT).
• An independent architecture allowing CLA algorithm execution independent of the main C28x CPU.
– Complete bus architecture:
• Program Address Bus (PAB) and Program Data Bus (PDB)
• Data Read Address Bus (DRAB), Data Read Data Bus (DRDB), Data Write Address Bus (DWAB), and
Data Write Data Bus (DWDB)
– Independent eight stage pipeline.
– 16-bit program counter (MPC)
– Four 32-bit result registers (MR0-MR3)
– Two 16-bit auxiliary registers (MAR0, MAR1)
– Status register (MSTF)
• Instruction set includes:
– IEEE single-precision (32-bit) floating-point math operations
– Floating-point math with parallel load or store
– Floating-point multiply with parallel add or subtract
– 1/X and 1/sqrt(X) estimations
– Data type conversions.
– Conditional branch and call
– Data load/store operations
• The CLA program code can consist of up to eight tasks or interrupt service routines, or seven tasks and a
main background task.
– The start address of each task is specified by the MVECT registers.
– No limit on task size as long as the tasks fit within the configurable CLA program memory space.
– One task is serviced at a time until completion. There is no nesting of tasks.
– Upon task completion a task-specific interrupt is flagged within the PIE.
– When a task finishes the next highest-priority pending task is automatically started.
– The Type-2 CLA can have a main task that runs continuously in the background, while other high priority
events trigger a foreground task.
• Task trigger mechanisms:
– C28x CPU using the IACK instruction
– Task1 to Task8: up to 256 possible trigger sources from peripherals connected to the shared bus on which
the CLA assumes secondary ownership.
– Task8 can be set to be the background task, while Tasks 1 through 7 take peripheral triggers.
• Memory and Shared Peripherals:
– Two dedicated message RAMs for communication between the CLA and the main CPU.
– Two dedicated message RAMs for communication between the CLA and the DMA.
– The C28x CPU can map CLA program and data memory to the main CPU space or CLA space.

8.1.2 CLA Related Collateral

Foundational Materials
• C2000 Academy - CLA

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• C2000 CLA C Compiler Series (Video)

• CLA Hands On Workshop (Video)
• CLA usage in Valley Switching Boost Power Factor Correction (PFC) Reference Design (Video)
• Enhancing the Computational Performance of the C2000™ Microcontroller Family Application Report

Getting Started Materials

• CLA Software Development Guide
• Software Examples to Showcase Unique Capabilities of TI's C2000™ CLA Application Report

Expert Materials
• Digital Control of Two Phase Interleaved PFC and Motor Drive Using MCU With CLA Application Report
• Sensorless Field Oriented Control:3-Phase Perm.Magnet Synch. Motors With CLA Application Report
8.1.3 Block Diagram
Figure 8-1 is a block diagram of the CLA.

CLA Control
Register Set

MIFR(16)
MPERINT1 MIOVF(16) CLA_INT1
From Shared to to
Peripherals MPERINT8 MICLR(16) CLA_INT8
MICLROVF(16) C28x
PIE INT11
MIFRC(16) CPU
MIER(16) INT12
MIRUN(16)
LVF
MCTLBGRND(16)
LUF
MSTSBGRND(16)
CLA1SOFTINTEN(16)
CLA1INTFRC(16)
SYSCLK
CLA Clock Enable MVECT1(16)
CPU Read/Write Data Bus
SYSRS MVECT2(16)
MVECT3(16)
MVECT4(16) CLA Program
MVECT5(16) CLA Program Bus Memory (LSx)
MVECT6(16)
MVECT7(16)
MVECT8(16) LSxMSEL[MSEL_LSx]
MVECTBGRND(16) LSxCLAPGM[CLAPGM_LSx]
MVECTBGRNDACTIVE(16)
MPSACTL(16)
MPSA1(32) CPU Data Bus
CLA Data
MPSA2(32) Memory (LSx)

MCTL(16)
CLA Data Bus

CLA Message
CLA Execution
RAMs
Register Set

MPC(16)
MSTF(32)
MR0(32)
MR1(32) Shared
MR2(32) MEALLOW Peripherals
MR3(32)
MAR0(16)
MAR1(16)
CPU Read Data Bus

Figure 8-1. CLA (Type 2) Block Diagram

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8.2 CLA Interface

This section describes how the C28x main CPU can interface to the CLA and conversely.
8.2.1 CLA Memory
The CLA can access three types of memory: program, data and message RAMs. The behavior and arbitration
for each type of memory is described in this chapter. The CLA RAMs are protected by the DCSM module. Refer
to the Dual Code Security Module (DCSM) section of the System Control and Interrupts chapter for more details
on the security scheme.
• CLA Program Memory
The CLA program can be loaded with any of the local shared memories (LSxRAM). At reset, all memory
blocks are mapped to the CPU. While mapped to the CPU space, the CPU can copy the CLA program code
into the memory. During debug, the memory can also be loaded directly by the Code Composer Studio™
IDE.
Once the memory is initialized with CLA code, the CPU maps the memory to the CLA program space by:
1. Assigning ownership of the memory block to the CLA by writing a 1 to the memory block’s
MemCfgRegs.LSxMSEL[MSEL_LSx] bit.
2. Specifying the memory block as a code block for the CLA by writing a 1 to the
MemCfgRegs.LSxCLAPGM[CLAPGM_LSx] bit.
When a memory block is configured as CLA program memory, debug accesses are allowed only on cycles
where the CLA is not fetching a new instruction. A detailed explanation of the memory configurations and
access arbitration (CPU, CLA, and DEBUG) process can be found in the Memory Controller Module section
of the System Control and Interrupts chapter.
All CLA program fetches are performed as 32-bit read operations and all opcodes must be aligned to an even
address. Since all CLA opcodes are 32-bits, this alignment occurs naturally.

• CLA Data Memory

Any of the device’s LSxRAMs can serve as data memory blocks to the CLA. At reset, all blocks are mapped
to the CPU memory space, whereby the CPU can initialize the memory with data tables, coefficients, and so
on, for the CLA to use.
Once the memory is initialized with CLA data, the CPU maps the memory to the CLA data space by:
1. Assigning ownership of the memory block to the CLA by writing a 1 to the memory block’s
MemCfgRegs.LSxMSEL[MSEL_LSx] bit.
2. Specifying the memory block as a data block for the CLA by writing a 0 to the
MemCfgRegs.LSxCLAPGM[CLAPGM_LSx] bit. The value of this bit at reset is 0.
When a memory block is configured as CLA data memory, CLA read and write accesses are arbitrated along
with CPU accesses. The user has the option of turning on CPU fetch or write protection to the memory by
writing to the appropriate bits of the MemCfgRegs.LSxACCPROTx registers. A detailed explanation of the
memory configurations and access arbitration (CPU, CLA, and DEBUG) process can be found in the Memory
Controller Module section of the System Control and Interrupts chapter.
• CLA Shared Message RAMs
There are two memory blocks for data sharing and communication between the CLA and the CPU . The
message RAMs are always mapped to both CPU and CLA memory spaces, and only data access is allowed;
no program fetches can be performed.
– CLA to CPU Message RAM: The CLA can use this block to pass data to the CPU. This block is both
readable and writable by the CLA. This block is also readable by the CPU but writes by the CPU are
ignored.
– CPU to CLA Message RAM: The CPU can use this block to pass data and messages to the CLA. This
message RAM is both readable and writable by the CPU. The CLA can perform reads but writes by the
CLA are ignored.

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8.2.2 CLA Memory Bus

The CLA has dedicated bus architecture similar to that of the C28x CPU where there are separate program read,
data read, and data write buses. Thus, there can be simultaneous instruction fetch, data read, and data write in
a single cycle. Like the C28x CPU, the CLA expects memory logic to align any 32-bit read or write to an even
address. If the address-generation logic generates an odd address, the CLA can begin reading or writing at the
previous even address. This alignment does not affect the address values generated by the address-generation
logic.
• CLA Program Bus
The CLA program bus has an access range of 32K 32-bit instructions. Since all CLA instructions are 32
bits, this bus always fetches 32 bits at a time and the opcodes must be even-word aligned. The amount of
program space available for the CLA is limited to the number of available LSxRAM blocks. This number is
device-dependent and can be described in the device-specific data manual.

• CLA Data Read Bus

The CLA data read bus has a 64K x 16 address range. The bus can perform 16 or 32-bit reads and can
automatically stall if there are memory access conflicts. The data read bus has access to both the message
RAMs, CLA data memory, and the shared peripherals.

• CLA Data Write Bus

The CLA data write bus has a 64K x 16 address range. This bus can perform 16 or 32-bit writes. The bus can
automatically stall if there are memory access conflicts. The data write bus has access to the CLA to CPU
message RAM, CLA data memory, and the shared peripherals.

8.2.3 Shared Peripherals and EALLOW Protection

For a given CPU subsystem, the CPU, CLA, and DMA can share access to some peripherals. There is a 3-way
arbitration among the different master's that is described in Section 8.3. Each peripheral has an access control
register with two bit fields, CPUnAC, CLAnAC, and DMAnAC (n being the instance) that determine what kind of
access is given to that particular master.

Note
The CLA read access time to the bus is 2-wait states while write access is 0-wait.

Refer to the device data sheet for the list of peripherals connected to the bus.
Several peripheral control registers are protected from spurious 28x CPU writes by the EALLOW protection
mechanism. These same registers are also protected from spurious CLA writes. The EALLOW bit in the CPU
status register 1 (ST1) indicates the state of protection for the CPU. Likewise, the MEALLOW bit in the CLA
status register (MSTF) indicates the state of write protection for the CLA. The MEALLOW CLA instruction
enables write access by the CLA to EALLOW protected registers. Likewise, the MEDIS CLA instruction disables
write access. This way the CLA can enable and disable write access independent of the CPU.
The ADC offers the option to generate an early interrupt pulse at the start of a sample conversion. If this option
is used to start an ADC-triggered CLA task, use the intervening cycles until the completion of the conversion
to perform preliminary calculations or loads and stores before finally reading the ADC value. The CLA pipeline
activity for this scenario is shown in Section 8.5.

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8.2.4 CLA Tasks and Interrupt Vectors

The CLA program code is divided up into tasks or interrupt service routines. Tasks do not have a fixed starting
location or length. The CLA program memory can be divided up as desired. The CLA uses the contents of the
interrupt vectors (MVECT1 to MVECT8) to determine where a task begins; tasks are terminated by the MSTOP
instruction.
The CLA supports eight tasks. Task 1 has the highest priority and task 8 has the lowest priority. The Type-2
CLA offers the option of setting the lowest priority task, for example, task 8, as a background task that, once
triggered, runs continuously until the user either terminates the task or resets the CLA or the device. The
remaining tasks, 1 through 7, maintain their priority levels and interrupt the background task when triggered.
The background task is enabled by setting the BGEN bit in the MCTLBGRND register; this causes the hardware
to disable task 8 in the MIER register. The background task derives the interrupt vector from the MVECTBGRND
register instead of MVECT8.
A task can be requested by a peripheral interrupt or by software:
• Peripheral interrupt trigger
Each task can be triggered by software-selectable interrupt sources. The trigger for each task is defined by
writing an appropriate value to the DmaClaSrcSelRegs.CLA1TASKSRCSELx[TASKx] bit field. Each option
specifies an interrupt source from a specific peripheral on the shared bus. The peripheral interrupt triggers
are listed in Table 8-1.
For example, task 1 (MVECT1) can be set to trigger on EPWMINT1 by writing 36 to
DmaClaSrcSelRegs.CLA1TASKSRCSEL1.TASK1. To disable the triggering of a task by a peripheral, set
the DmaClaSrcSelRegs.CLA1TASKSRCSELx[TASKx] bit field to 0. Note that a CLA task only triggers on a
level transition (an edge) of the configured interrupt source.
Table 8-1. Configuration Options
Select Value CLA Trigger Source

0 CLA_SOFTWARE_TRIGGER

1 ADCAINT1

2 ADCAINT2

3 ADCAINT3

4 ADCAINT4

5 ADCA_EVT_INT

6 ADCBINT1

7 ADCBINT2

8 ADCBINT3

9 ADCBINT4

10 ADCB_EVT_INT

11 ADCCINT1

12 ADCCINT2

13 ADCCINT3

14 ADCCINT4

15 ADCC_EVT_INT

16 ADCDINT1

17 ADCDINT2

18 ADCDINT3

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Table 8-1. Configuration Options (continued)

Select Value CLA Trigger Source

19 ADCDINT4

20 ADCD_EVT_INT

21-28 Reserved

29 XINT1

30 XINT2

31 XINT3

32 XINT4

33 XINT5

34-35 Reserved

36 EPWM1_INT

37 EPWM2_INT

38 EPWM3_INT

39 EPWM4_INT

40 EPWM5_INT

41 EPWM6_INT

42 EPWM7_INT

43 EPWM8_INT

44 EPWM9_INT

45 EPWM10_INT

46 EPWM11_INT

47 EPWM12_INT

48 EPWM13_INT

49 EPWM14_INT

50 EPWM15_INT

51 EPWM16_INT

52 MCANA_FEVT0

53 MCANA_FEVT1

54 MCANA_FEVT2

55-67 Reserved

68 CPU_TINT0

69 CPU_TINT1

70 CPU_TINT2

71 MCBSPA_TX

72 MCBSPA_RX

73 MCBSPB_TX

74 MCBSPB_RX

75 ECAP1_INT

76 ECAP2_INT

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Table 8-1. Configuration Options (continued)

Select Value CLA Trigger Source

77 ECAP3_INT

78 ECAP4_INT

79 ECAP5_INT

80 ECAP6_INT

81 ECAP7_INT

82 Reserved

83 EQEP1_INT

84 EQEP2_INT

85 EQEP3_INT

86-91 Reserved

92 ECAP6_INT2

93 ECAP7_INT3

94 Reserved

95 SD1FLT1_DRINT

96 SD1FLT2_DRINT

97-102 Reserved

103 ECAT_SYNC0

104 ECAT_SYNC1

105 PMBUSA_INT

106-108 Reserved

109 SPIA_TXINT

110 SPIA_RXINT

111 SPIB_TXINT

112 SPIB_RXINT

113 SPIC_TXINT

114 SPIC_RXINT

115 SPID_TXINT

116 SPID_RXINT

117 CLB5_INT

118 CLB6_INT

119 CLB7_INT

120 CLB8_INT

121 BGCRC_INT

122 Reserved

123 FSITXA_INT1

124 FSITXA_INT2

125 FSIRXA_INT1

126 FSIRXA_INT2

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Table 8-1. Configuration Options (continued)

Select Value CLA Trigger Source

127 CLB1_INT

128 CLB2_INT

129 CLB3_INT

130 CLB4_INT

131-142 Reserved

143 SD1FLT1_DRINT

144 SD1FLT2_DRINT

145 SD1FLT3_DRINT

146 SD1FLT4_DRINT

147 SD2FLT1_DRINT

148 SD2FLT2_DRINT

149 SD2FLT3_DRINT

150 SD2FLT4_DRINT

151-154 Reserved

155 FSITXB_INT1

156 FSITXB_INT2

157 FSIRXB_INT1

158 FSIRXB_INT2

159 FSIRXC_INT1

160 FSIRXC_INT2

161 FSIRXD_INT1

162 FSIRXD_INT2

163 FSIRXE_INT1

164 FSIRXE_INT2

165 FSIRXF_INT1

166 FSIRXF_INT2

167 FSIRXG_INT1

168 FSIRXG_INT2

169 FSIRXH_INT1

170 FSIRXH_INT2

171-255 Reserved

• Software Trigger
CPU software can trigger tasks by writing to the MIFRC register or by the IACK instruction. Using the
IACK instruction is more efficient because the instruction does not require the need to issue an EALLOW
to set MIFR bits. Set the MCTL[IACKE] bit to enable the IACK feature. Each bit in the operand of the IACK
instruction corresponds to a task. For example, IACK #0x0001 sets bit 0 in the MIFR register to start task 1.
Likewise, IACK #0x0003 set bits 0 and 1 in the MIFR register to start task 1 and task 2.
• Background Task

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The Type-2 CLA allows the use of Task 8 as a background task that runs continuously until Task 8 disables
the task or resets the device (or the CLA using a soft reset). The background task vector is given by the
MVECTBGRND register and the operation is controlled by the MCTLBGRND register; the task is enabled
by setting the BGEN bit to 1. Then start the task through software by writing a 1 to the BGSTART bit
(TRIGEN must be 0), or through a peripheral by setting the TRIGEN bit to 1 and then setting the trigger
source in the bit-field, DmaClaSrcSelRegs.CLA1TASKSRCSEL2.bit.TASK8. By default, the background task
is interruptible; the highest priority pending task is executed first. When a task completes and there are not
any pending tasks, the execution returns to the background task. The CLA keeps track of the branching point
by saving the return address to the MVECTBGRNDACTIVE register, and then popping this address to the
MPC when execution returns. Choose to make sections of the background task uninterruptible by possibly
doing this with the MSETC BGINTM assembly instruction.
Subsequently, enabling interrupts with the MCLRC BGINTM instruction.
The background interrupt mask bit, BGINTM, can be queried in the MSTSBGRND register. This register also
provides the current status of the background task. If the task is currently executing, the RUN bit is set to 1, if
another trigger for the background task is received while the task has already started, the overflow (BGOVF)
bit is set.
The CLA has their own fetch mechanism and can run and execute a task independently of the CPU. Only one
task is serviced at a time; there is no nesting of tasks unless the background task in enabled, then one level
of nesting is possible. The task currently running is indicated in the MIRUN register; if the background task is
enabled and running, the task is reflected in the MSTSBGRND register (the RUN bit).
Interrupts that have been received but not yet serviced are indicated in the flag register (MIFR). If an interrupt
request from a peripheral is received and that same task is already flagged, then the overflow flag bit is set.
Overflow flags remain set until the flags are cleared by the CPU. If the CLA is idle (no task is currently running)
or is executing the background task, then the highest priority interrupt request that is both flagged (MIFR) and
enabled (MIER) starts.

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The flow is as follows:

1. The associated RUN register bit is set (MIRUN) and the flag bit (MIFR) is cleared.
2. The CLA begins execution at the location indicated by the associated interrupt vector (MVECTx). MVECT
contains the absolute 16-bit address of the task in the lower 64K memory space. If a task is interrupting
the background task then the current program address is stored in the MVECTBGRNDACTIVE register
before execution jumps to the task; this saved address is restored to the MPC when the task completes and
execution returns to the background task.
3. The CLA executes instructions until the MSTOP instruction is found. This indicates the end of the task.
4. The MIRUN bit is cleared.
5. The task-specific interrupt to the PIE is issued. This informs the main CPU that the task has completed.
6. The CLA returns to idle (or to the background task, if enabled). Once a task completes the next highest-
priority pending task is automatically serviced and this sequence repeats.

8.2.5 CLA Software Interrupt to CPU

The CLA can issue a software interrupt to the C28x CPU at any point in the code through the use of the
CLA1SOFTINTEN and CLA1INTFRC registers. See Section 8.8 for a description of these registers. If a software
interrupt is selected for a CLA task, then an end-of-task interrupt is not issued to the C28x CPU when that task
completes.
8.3 CLA, DMA, and CPU Arbitration
Typically, CLA activity is independent of the CPU activity. Under the circumstance where the CLA, DMA, or
CPU attempt to concurrently access memory or a peripheral register within the same interface, an arbitration
procedure will occur. This section describes this arbitration.
The arbitration follows a fixed arbitration scheme with highest priority first:
1. DMA WRITE
2. DMA READ
3. CLA WRITE
4. CLA READ
5. CPU WRITE
6. CPU READ
Refer to the Memory Controller Module section of the System Control and Interrupts chapter.

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8.3.1 CLA Message RAM

Message RAMs consist of four blocks:
• CLA to CPU Message RAM
• CPU to CLA Message RAM
• DMA to CLA Message RAM
• CLA to DMA Message RAM
These blocks are useful for passing data between the CLA and CPU or CLA and DMA. No opcode fetches,
from either the CLA or CPU, are allowed from the message RAMs. A write protection violation is not generated
if the CLA attempts to write to the CPU to CLA or DMA to CLA message RAM, but the write is ignored. The
arbitration scheme for the message RAMs are the same as those for the shared memories, described in the
Memory Controller Module section of the System Control and Interrupts chapter.
The message RAMs have the following characteristics:
• CLA to CPU Message RAM:
The following accesses are allowed:
– CPU reads
– CLA data reads and writes
– CPU debug reads and writes
The following accesses are ignored:
– CPU writes
• CPU to CLA Message RAM:
The following accesses are allowed:
– CPU reads and writes
– CLA reads
– CPU debug reads and writes
The following accesses are ignored:
– CLA writes
8.3.2 Peripheral Registers (ePWM, HRPWM, Comparator)
Accesses to the registers follow these rules:
• If both the CPU and CLA request access at the same time, then the CLA has priority and the main CPU is
stalled.
• If a CPU access is in-progress and another CPU access is pending, then the CLA has priority over the
pending CPU access. In this case, the CLA access begins when the current CPU access completes.
• While a CPU access is in-progress, any incoming CLA access is stalled.
• While a CLA access is in-progress, any incoming CPU access is stalled.
• A CPU write operation has priority over a CPU read operation.
• A CLA write operation has priority over a CLA read operation.
• If the CPU is performing a read-modify-write operation and the CLA performs a write to the same location, the
CLA write can be lost if the operation occurs in-between the CPU read and write. For this reason, do not mix
CPU and CLA accesses to same location.

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8.4 CLA Configuration and Debug

This section discusses the steps necessary to configure and debug the CLA.
8.4.1 Building a CLA Application
The control law accelerator can be programmed in either CLA assembly code, using the instructions described
in Section 8.7, or a reduced subset of the C language. CLA assembly code resides in the same project with
C28x code. The only restriction is the CLA code must be in the assembly section. This can be easily done
using the .sect assembly directive. This does not prevent CLA and C28x code from being linked into the same
memory region in the linker command file.
System and CLA initialization are performed by the main CPU. This can typically be done in C or C++ but can
also include C28x assembly code. The main CPU also copies the CLA code to the program memory and, if
needed, initialize the CLA data RAMs. Once system initialization is complete and the application begins, the
CLA services the interrupts using the CLA assembly code (or tasks). The main CPU can perform other tasks
concurrently with CLA program execution.
The CLA Type 2 requires Codegen V16.9.1.LTS or later with the compiler switch: --cla_support=cla2.
8.4.2 Typical CLA Initialization Sequence
A typical CLA initialization sequence is performed by the main CPU as described in this section.
1. Copy CLA code into the CLA program RAM
The source for the CLA code can initially reside in the Flash or a data stream from a communications
peripheral or anywhere the main CPU can access. The debugger can also be used to load code directly to
the CLA program RAM during development.
2. Initialize CLA data RAM, if necessary
Populate the CLA data RAM with any required data coefficients or constants.
3. Configure the CLA registers
Configure the CLA registers, but keep interrupts disabled until later (leave MIER = 0):
• Enable the CLA peripheral clock using the assigned PCLKCRn register
The peripheral clock control (PCLKCRn) registers are defined in the System Control and Interrupts
chapter.
• Populate the CLA task interrupt vectors
– MVECT1 to MVECT8
Each vector needs to be initialized with the start address of the task to be executed when the CLA
receives the associated interrupt. This address is the full 16-bit starting address of the task in the
lower 64K section of memory.
– MVECT1 to MVECT7, and MVECTBGRND
When using the background task, the vector (MVECTBGRND) must be loaded with the start address
of the task in lower 64K of memory. Note that Task 8 is ignored when the background task is enabled.
• Select the task interrupt sources
For each task select the interrupt source in the CLA1TASKSRCSELx register. If a task is software
triggered, select no interrupt. Since the background task takes the place of Task 8, the task uses the
same peripheral trigger source as task 8.
• Enable IACK to start a task from software, if desired
To enable the IACK instruction to start a task set the MCTL[IACKE] bit. Using the IACK instruction avoids
having to set and clear the EALLOW bit. If the background task is enabled, the IACK bit for task 8
is ignored; the user must, instead, write to the BGSTART bit of the MCTLBGRND register to start the
background task (TRIGEN can be 0 to avoid a peripheral trigger from causing an overflow, for example,
MSTSBGRND.BGOVF is set to 1).

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• Map CLA data RAM to CLA space, if necessary

Map the data RAM to the CLA space by first, assigning ownership of the memory block to the CLA
by writing a 1 to the memory block’s MemCfgRegs.LSxMSEL[MSEL_LSx] bit, and then specifying the
memory block as a CLA data block by writing a 0 to the MemCfgRegs.LSxCLAPGM[CLAPGM_LSx] bit.
When an LSx memory is configured as a CLA data memory, the CLA read/write accesses are arbitrated
along with CPU accesses. The user has the option of turning on CPU fetch or write protection to the
memory by writing to the appropriate bits of the MemCfgRegs.LSxACCPROTx registers.
• Map CLA program RAM to CLA space
Map the CLA program RAM to CLA space by first assigning ownership of the memory block to the CLA
by writing a 1 to the memory block’s MemCfgRegs.LSxMSEL[MSEL_LSx] bit, and then specifying the
memory block as CLA code memory by writing a 1 to the MemCfgRegs.LSxCLAPGM[CLAPGM_LSx]
bit. When an LSx memory is configured as CLA program memory, only debug accesses are allowed on
cycles in which the CLA is not fetching a new instruction.
4. Initialize the PIE vector table and registers
When a CLA task completes, the associated interrupt in the PIE is flagged. The CLA overflow and underflow
flags also have associated interrupts within the PIE.
5. Enable CLA tasks/interrupts
Set appropriate bits in the interrupt enable register (MIER) to allow the CLA to service interrupts. Note that a
CLA task only triggers on a level transition (a falling edge) of the configured interrupt source. If a peripheral
is enabled and an interrupt fires before the CLA is configured, then the CLA does not recognize the interrupt
edge and does not respond. To avoid this, configure the CLA before the peripherals or clear any pending
peripheral interrupts before setting bits in the MIER register.
6. Initialize other peripherals
Initialize any peripherals (such as ePWM, ADC, and others) that generate interrupt triggers for enabled CLA
tasks.
The CLA is now ready to service interrupts and the message RAMs can be used to pass data between the
CPU and the CLA. Mapping of the CLA program and data RAMs typically occurs only during the initialization
process. If the RAM mapping needs to be changed after initialization, the CLA interrupts must be disabled
and all tasks must be completed (by checking the MIRUN register) prior to modifying the RAM ownership.

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8.4.3 Debugging CLA Code

Debugging the CLA code is a simple process that occurs independently of the main CPU. The type 2 CLA adds
a true software breakpoint feature.
8.4.3.1 Software Breakpoint Support (MDEBUGSTOP1)
The MDEBUGSTOP1 instruction is meant to be used as a software breakpoint; the instruction on which the
execution must halt is replaced with this instruction.
The MDEBUGSTOP1 and MDEBUGSTOP instructions differ in how the CLA pipeline is treated. When halted,
the MDEBUGSTOP1 instruction flushes all the instructions that have already been fetched; on a single-step or
run-free command, the CLA refetches the same instruction that it replaced. Table 8-2 illustrates the pipeline
behavior.
Table 8-2. Pipeline Behavior of the MDEBUGSTOP1 Instruction
Cycles F1 F2 D1 D2 R1 R2 E W Comments
1 i1
2 i2 i1
3 i3 i2 i1
4 i4 i3 i2 i1
5 MDEBUG i4 i3 i2 i1
STOP1
6 i6 MDEBUG i4 i3 i2 i1
STOP1
7 i7 i6 MDEBUG i4 i3 i2 i1
STOP1
9 i8 Flushed Flushed Flushed i4 i3 i2 i1 CLA
(MNOP) (MNOP) (MNOP) halted
10 i5(MDEBUGS Flushed Flushed Flushed Flushed i4 i3 i2 CLA step/run
TOP1) (MNOP) (MNOP) (MNOP) (MNOP)
11 i6 i5(MDEBUGS Flushed Flushed Flushed Flushed i4 i3 CLA step/run
TOP1) (MNOP) (MNOP) (MNOP) (MNOP)
12 i7 i6 i5(MDEBUGS Flushed Flushed Flushed Flushed i4 CLA step/run
TOP1) (MNOP) (MNOP) (MNOP) (MNOP)
13 i8 i7 i6 i5(MDEBUGS Flushed Flushed Flushed Flushed CLA step/run
TOP1) (MNOP) (MNOP) (MNOP) (MNOP)

A software breakpoint is placed at instruction i5. The instruction, i5, is then replaced with MDEBUGSTOP1. It
takes 3 cycles for the MDEBUGSTOP1 to reach the D2 phase at which point the instructions i6, i7, and i8 that
were previously fetched are now flushed from the pipeline. The instruction, i5, is then re-fetched and execution
continues as before.

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8.4.3.2 Legacy Breakpoint Support (MDEBUGSTOP)

1. Insert a breakpoint in CLA code
Insert a CLA breakpoint (MDEBUGSTOP instruction) into the code where the CLA is to halt, then rebuild
and reload the code. Because the CLA does not flush the pipeline when in single-step, the MDEBUGSTOP
instruction must be inserted as part of the code. The debugger cannot insert the MDEBUGSTOP instruction
as needed.
If CLA breakpoints are not enabled, then the MDEBUGSTOP instruction is ignored and is treated
as a MNOP. The MDEBUGSTOP instruction can be placed anywhere in the CLA code as long as
the MDEBUGSTOP instruction is not within three instructions of a MBCNDD, MCCNDD, or MRCNDD
instruction. When programming in C, the user can use the __mdebugstop() intrinsic instead; the compiler
makes sure that the placement of the MDEBUSTOP instruction in the generated assembly does not violate
any of the pipeline restrictions.
2. Enable CLA breakpoints
Enable the CLA breakpoints in the debugger. In the Code Composer Studio™ IDE, this is done by
connecting to the CLA core (or tap) from the debug perspective. Breakpoints are disabled when the core is
disconnected.
3. Start the task
There are three ways to start the task:
a. The peripheral can assert an interrupt,
b. The main CPU can execute an IACK instruction, or
c. The user can manually write to the MIFRC register in the debugger window
When the task starts, the CLA executes instructions until the MDEBUGSTOP is in the D2 phase of the
pipeline. At this point, the CLA halts and the pipeline is frozen. The MPC register reflects the address of the
MDEBUGSTOP instruction.

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4. Single-step the CLA code

Once halted, the user can single-step the CLA code. The behavior of a CLA single-step is different than the
main C28x. When issuing a CLA single-step, the pipeline is clocked only one cycle and then again frozen.
On the C28x CPU, the pipeline is flushed for each single-step.
Run to the next MDEBUGSTOP or to the end of the task. If another task is pending, the task automatically
starts when run to the end of the task.

Note
A CLA fetch has higher priority than CPU debug reads. For this reason, it is possible for the
CLA to permanently block CPU debug accesses if the CLA is executing in a loop. This can occur
when initially developing CLA code due to a bug that causes an infinite loop. To avoid locking up
the main CPU, the program memory returns all 0x0000 for CPU debug reads when the CLA is
running. When the CLA is halted or idle, then normal CPU debug read and write access to CLA
program memory can be performed.
If the CLA gets caught in an infinite loop, use a soft or hard reset to exit the condition. A debugger
reset also exits the condition.

There are special cases that can occur when single-stepping a task such that the program counter, MPC,
reaches the MSTOP instruction at the end of the task.
• MPC halts at or after the MSTOP with a task already pending
If single-stepping or halted in "task A" and "task B" comes in before the MPC reaches the MSTOP, then
"task B" starts if continuing to step through the MSTOP instruction. Basically, if "task B" is pending before
the MPC reaches MSTOP in "task A" then there is no issue in "task B" starting and no special action is
required.
• MPC halts at or after the MSTOP with no task pending
In this case, if single-stepped or halted in "task A" and the MPC has reached the MSTOP with no tasks
pending. If "task B" comes in at this point, "task B" is flagged in the MIFR register but "task B" can or
cannot start if continuing to single-step through the MSTOP instruction of "task A."
Depending on exactly when the new task comes in, to reliably start "task B", perform a soft reset and
reconfigure the MIER bits. Once this is done, start single-stepping "task B."
This case can be handled slightly differently if there is control over when "task B" comes in (for example,
using the IACK instruction to start the task). In this case, the task is single-stepped or halted in "task A"
and the MPC has reached the MSTOP with no tasks pending. Before forcing "task B," run free to force
the CLA out of the debug state. Once this is done, force "task B" and continue debugging.
5. Disable CLA breakpoints, if desired
In the Code Composer Studio™ IDE, disable the CLA breakpoints by disconnecting the CLA core in the
debug perspective. Make sure to first issue a run or reset; otherwise, the CLA is halted and no other tasks
start.

8.4.4 CLA Illegal Opcode Behavior

If the CLA fetches an opcode that does not correspond to a legal instruction, it will behave as follows:
• The CLA will halt with the illegal opcode in the D2 phase of the pipeline as if it were a breakpoint. This will
occur whether CLA breakpoints are enabled or not.
• The CLA will issue the task-specific interrupt to the PIE.
• The MIRUN bit for the task will remain set.
Further single-stepping is ignored once execution halts due to an illegal op-code. To exit this situation, issue
either a soft or hard reset of the CLA as described in Section 8.4.5.

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8.4.5 Resetting the CLA

There are times when resetting the CLA is needed. For example, during code debug the CLA can enter an
infinite loop due to a code bug. The CLA has two types of resets: hard and soft. Both of these resets can be
performed by the debugger or by the main CPU.
• Hard Reset Writing a 1 to the MCTL[HARDRESET] bit performs a hard reset of the CLA. The behavior of a
hard reset is the same as a system reset (using XRS or the debugger). In this case, all CLA configuration and
execution registers can be set to their default state and CLA execution halts.
• Soft Reset Writing a 1 to the MCTL[SOFTRESET] bit performs a soft reset of the CLA. If a task is executing,
the task halts and the associated MIRUN bit is cleared. All bits within the interrupt enable (MIER) register are
also cleared, so that no new tasks start. In addition, the background task's start bit (MCTLBGRN.BGSTART)
and trigger enable bit (MCTLBGRND.TRIGEN) are reset. The MVECTBGRNACTIVE is set to the value of
MVECTBGRND, and the status register (MSTSBGRND) is also reset.
8.5 Pipeline
This section describes the CLA pipeline stages and presents cases where pipeline alignment must be
considered.
8.5.1 Pipeline Overview
The CLA pipeline is very similar to the C28x pipeline with eight stages:
1. Fetch 1 (F1): During the F1 stage the program read address is placed on the CLA program address bus.
2. Fetch 2 (F2): During the F2 stage the instruction is read using the CLA program data bus.
3. Decode 1 (D1): During D1 the instruction is decoded.
4. Decode 2 (D2): Generate the data read address. Changes to MAR0 and MAR1 due to post-increment using
indirect addressing takes place in the D2 phase. Conditional branch decisions are also made at this stage
based on the MSTF register flags.
5. Read 1 (R1): Place the data read address on the CLA data-read address bus. If a memory conflict exists,
the R1 stage will be stalled.
6. Read 2 (R2): Read the data value using the CLA data read data bus.
7. Execute (EXE): Execute the operation. Changes to MAR0 and MAR1 due to loading an immediate value or
value from memory take place in this stage.
8. Write (W): Place the write address and write data on the CLA write data bus. If a memory conflict exists, the
W stage will be stalled.

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8.5.2 CLA Pipeline Alignment

The majority of the CLA instructions do not require any special pipeline considerations. This section lists the few
operations that do require special consideration.
• Write Followed by Read
In both the C28x pipeline and the CLA pipeline, the read operation occurs before the write. This means that
if a read operation immediately follows a write, then the read completes first as shown in Table 8-3. In most
cases this does not cause a problem since the contents of one memory location does not depend on the
state of another. For accesses to peripherals where a write to one location can affect the value in another
location, the code must wait for the write to complete before issuing the read as shown in Table 8-4.
This behavior is different for the C28x CPU. For the C28x CPU, any write followed by read to the same
location is protected by what is called write-followed-by-read protection. This protection automatically stalls
the pipeline so that the write completes before the read. In addition, some peripheral frames are protected
such that a C28x CPU write to one location within the frame always completes before a read to the frame.
The CLA does not have this protection mechanism. Instead, the code must wait to perform the read.
Table 8-3. Write Followed by Read - Read Occurs First
Instruction F1 F2 D1 D2 R1 R2 E W
I1 MMOV16 @Reg1, MR3 I1
I2 MMOV16 MR2, @Reg2 I2 I1
I2 I1
I2 I1
I2 I1
I2 I1
I2 I1
I2 I1

Table 8-4. Write Followed by Read - Write Occurs First

Instruction F1 F2 D1 D2 R1 R2 E W
I1 MMOV16 @Reg1, MR3 I1
I2 I2 I1
I3 I3 I2 I1
I4 I4 I3 I2 I1
I5 MMOV16 MR2, @Reg2 I5 I4 I3 I2 I1
I5 I4 I3 I2 I1
I5 I4 I3 I2 I1
I5 I4 I3 I2 I1
I5 I4 I3
I5 I4
I5

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• Delayed Conditional instructions: MBCNDD, MCCNDD, and MRCNDD

Referring to Example 8-1, the following applies to delayed conditional instructions:
– I1: I1 is the last instruction that can effect the CNDF flags for the branch, call, or return instruction. The
CNDF flags are tested in the D2 phase of the pipeline. That is, a decision is made whether to branch or
not when MBCNDD, MCCNDD, or MRCNDD is in the D2 phase.
– I2, I3, and I4: The three instructions preceding MBCNDD can change the MSTF flags but have no effect
on whether the MBCNDD instruction branches or not. This is because the flag modification occurs after
the D2 phase of the branch, call, or return instruction. These three instructions must not be a MSTOP,
MDEBUGSTOP, MBCNDD, MCCNDD, or MRCNDD.
– I5, I6, and I7: The three instructions following a branch, call, or return are always executed irrespective of
whether the condition is true or not. These instructions must not be MSTOP, MDEBUGSTOP, MBCNDD,
MCCNDD, or MRCNDD.
For a more detailed description, refer to the description for MBCNDD, MCCNDD, and MRCNDD.

Example 8-1. Code Fragment For MBCNDD, MCCNDD, or MRCNDD

<Instruction 1> ; I1 Last instruction that can affect flags for

; the branch, call or return operation
<Instruction 2> ; I2 Cannot be stop, branch, call or return
<Instruction 3> ; I3 Cannot be stop, branch, call or return
<Instruction 4> ; I4 Cannot be stop, branch, call or return
<branch/call/ret> ; MBCNDD, MCCNDD or MRCNDD
; I5-I7: Three instructions after are always
; executed whether the branch/call or return is
; taken or not
<Instruction 5> ; I5 Cannot be stop, branch, call or return
<Instruction 6> ; I6 Cannot be stop, branch, call or return
<Instruction 7> ; I7 Cannot be stop, branch, call or return
<Instruction 8> ; I8
<Instruction 9> ; I9
....

• Stop or Halting a Task: MSTOP and MDEBUGSTOP

The MSTOP and MDEBUGSTOP instructions cannot be placed three instructions before or after a conditional
branch, call or return instruction (MBCNDD, MCCNDD, or MRCNDD). Refer to Example 8-1. To single-step
through a branch/call or return, insert the MDEBUGSTOP at least four instructions back and step from there.

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• Loading MAR0 or MAR1

A load of auxiliary register MAR0 or MAR1 occurs in the EXE phase of the pipeline. Any post increment of
MAR0 or MAR1 using indirect addressing occurs in the D2 phase of the pipeline. Referring to Example 8-2,
the following applies when loading the auxiliary registers:
– I1 and I2
The two instructions following the load instruction use the value in MAR0 or MAR1 before the update
occurs.
– I3
Loading of an auxiliary register occurs in the EXE phase while updates due to post-increment addressing
occur in the D2 phase. Thus I3 cannot use the auxiliary register or there is a conflict. In the case of a
conflict, the update due to address-mode post increment wins and the auxiliary register is not updated with
#_X.
– I4
Starting with the 4th instruction MAR0 or MAR1 has the new value.

Example 8-2. Code Fragment for Loading MAR0 or MAR1

; Assume MAR0 is 50 and #_X is 20

MMOVI16 MAR0, #_X ; Load MAR0 with address of X (20)

<Instruction 1> ; I1 Will use the old value of MAR0 (50)
<Instruction 2> ; I2 Will use the old value of MAR0 (50)
<Instruction 3> ; I3 Cannot use MAR0
<Instruction 4> ; I4 Will use the new value of MAR0 (20)
<Instruction 5> ; I5 Will use the new value of MAR0 (20
....

• Background Task Interrupted Close to a Branch

When the background task is running, if another task request happens (and MSTSBGRND.BGINTM is not
set), then the following sequence of operations happen.
– A check is made to determine if the following instructions are not in the pipeline (D2 – R2).
• MBCNDD
• MCCNDD
• MRCNDD
If any of the above instructions are present in the pipeline, the back ground task continues to execute until
such time when the condition is satisfied. Once the condition is satisfied, the following actions are performed:
– The MPC value of the D1 phase instruction is saved to the MVECTBGRNDACTIVE register.
– The run status bit of the background task (MSTSBGRND.RUNSTS) is cleared.
– An MSTOP instruction is forced into the D2 phase of the pipeline; causing the background task to
terminate.
When the background task terminates, the CLA picks the next highest pending task and begins execution.
Note that while the background task is pending, the background task has the lowest priority and, therefore,
yields to any other pending task. Once all pending non-background tasks have completed execution, the CLA
restores the program counter (MPC), that is, loads the address from the MVECTBGRNDACTIVE register to
the MPC, sets the background status to RUN (MSTSBGRND.RUN = 1), and continues execution from that
point.

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• MSTOP in the Background Task

If an MSTOP instruction occurs in the D1 phase while the background task is running, the following sequence
of operations happens:
– The RUN bit (MSTSBGRND.RUN) is cleared.
– The address stored in MVECTBGRND is copied over to MVECTBGRNDACTIVE.
– An interrupt, signaling the background task has completed execution, is generated. This interrupt signal is
ANDed with the interrupt from Task 8 and fed to the PIE. Note that if an illegal instruction occurs inside the
background task, the interrupt for task 8 is fired.
– When the background task terminates, the CLA resumes arbitration among the pending tasks.

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8.5.2.1 ADC Early Interrupt to CLA Response

The ADC can be configured to generate an early interrupt pulse before the ADC conversion completes. If this
option is used to start a CLA task, the CLA is able to read the result as soon as the conversion result is available
in the ADC result register. This combination of just-in-time sampling along with the low interrupt response of the
CLA enable faster system response and higher frequency control loops. The CLA task trigger to first instruction
fetch interrupt latency is 4 cycles.
Timings for ADC conversions are shown in the timing diagrams of the ADC chapter. If the ADCCLK is a divided
down version of the SYSCLK, the user has to account for the conversion time in SYSCLK cycles.
For example, if using the 12-bit ADC with ADCCLK at SYSCLK / 4, the ADC can take 10.5 ADCCLK x 4
SYSCLK = 42 SYSCLK cycles to complete a conversion. If using the ADC in 16-bit mode at the same ADCCLK,
the ADC can take 29.5 ADCCLK x 4 SYSCLK = 118 SYSCLK cycles, and so on.
From a CLA perspective, the pipeline activity is shown in Table 8-5 for an N-cycle (SYSCLK) ADC conversion.
The N-2 instruction arrives in the R2 phase just in time to read the result register. While the prior instructions
enter the R2 phase of the pipeline too soon to read the conversion, the instructions can be efficiently used for
pre-processing calculations needed by the task.
Table 8-5. ADC to CLA Early Interrupt Response
ADC Activity CLA Activity F1 F2 D1 D2 R1 R2 E W
Sample
Sample
...
Sample
Conversion(Cycle 1) Interrupt Received
Conversion(Cycle 2) Task Startup
Conversion(Cycle 3) Task Startup
Conversion(Cycle 4) I(Cycle 4) I(Cycle 4)
Conversion(Cycle 5) I(Cycle 5) I(Cycle 5) I(Cycle 4)
Conversion(...) ... ... ... ... ... ... ...
Conversion(Cycle N-6) I(Cycle N-6) I(Cycle N-6) I(Cycle N-7) I(Cycle N-8) I(Cycle N-9) I(Cycle N-10) I(Cycle N-11)
Conversion(Cycle N-5) I(Cycle N-5) I(Cycle N-5) I(Cycle N-6) I(Cycle N-7) I(Cycle N-8) I(Cycle N-9) I(Cycle N-10)
Conversion(Cycle N-4) I(Cycle N-4) I(Cycle N-4) I(Cycle N-5) I(Cycle N-6) I(Cycle N-7) I(Cycle N-8) I(Cycle N-9)
Conversion(Cycle N-3) I(Cycle N-3) I(Cycle N-3) I(Cycle N-4) I(Cycle N-5) I(Cycle N-6) I(Cycle N-7) I(Cycle N-8)
Read
Conversion(Cycle N-2) Read RESULT I(Cycle N-3) I(Cycle N-4) I(Cycle N-5) I(Cycle N-6) I(Cycle N-7)
RESULT
Read
Conversion(Cycle N-1) I(Cycle N-3) I(Cycle N-4) I(Cycle N-5) I(Cycle N-6)
RESULT
Read
Conversion(Cycle N-0) I(Cycle N-3) I(Cycle N-4) I(Cycle N-5)
RESULT
Read
Conversion Complete I(Cycle N-3) I(Cycle N-4)
RESULT
Read
RESULT Latched I(Cycle N-3)
RESULT
Read
RESULT Available
RESULT

The ADCINTCYCLE register of the ADC can be programmed by the application to adjust the generation of the
interrupt pulse to align with the ADC read operation. For example, if the first instruction in the task reads the
ADC and the conversion time is N SYSCLK cycles, then the delay programmed is (N-2) - 4 = N-6.

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8.5.3 Parallel Instructions

Parallel instructions are single opcodes that perform two operations in parallel. The following types of parallel
instructions are available: math operation in parallel with a move operation, or two math operations in parallel.
Both operations complete in a single cycle and there are no special pipeline alignment requirements.
Example 8-3. Math Operation with Parallel Load

; MADDF32 || MMOV32 instruction: 32-bit floating-point add with parallel move

; MADDF32 is a 1 cycle operation
; MMOV32 is a 1 cycle operation
MADDF32 MR0, MR1, #2 ; MR0 = MR1 + 2,
|| MMOV32 MR1, @Val ; MR1 gets the contents of Val
; <-- MMOV32 completes here (MR1 is valid)
; <-- DDF32 completes here (MR0 is valid)
MMPYF32 MR0, MR0, MR1 ; Any instruction, can use MR1 and/or MR0

Example 8-4. Multiply with Parallel Add

; MMPYF32 || MADDF32 instruction: 32-bit floating-point multiply with parallel add

; MMPYF32 is a 1 cycle operation
; MADDF32 is a 1 cycle operation
MMPYF32 MR0, MR1, MR3 ; MR0 = MR1 * MR3
|| MADDF32 MR1, MR2, MR0 ; MR1 = MR2 + MR0 (Uses value of MR0 before MMPYF32)
; <-- MMPYF32 and MADDF32 complete here (MR0 and MR1 are valid)
MMPYF32 MR1, MR1, MR0 ; Any instruction, can use MR1 and/or MR0

8.5.4 CLA Task Execution Latency

The CLA task execution latency depends on the state of the system:
• CLA task trigger of new task (normal or background) without background task active:
Task takes 8 cycles from CLA task trigger to first instruction of task to reach the D2 phase of pipeline.

Note
If background task has been configured in the system, then the compiler during code compilation
adds context save instructions at the start of each regular task and restore instructions at end
of each task so that register content can be saved and restored in case a background task
is executing while the regular task is triggered. When a regular task is entered, this compiler-
generated context save instruction is the first instruction of the task.
• CLA task trigger of normal task when background task is active:
Task takes 9 cycles from CLA task trigger to first instruction of normal task to reach the D2 phase of pipeline.
There is a difference of one clock cycle to force the MSTOP in the D2 phase of the background task before
the task exits as compared to a new task trigger without the background task active.

Note
If the MBCNDD/MCCNDD/MRCNDD instructions in the background task are in the D2 phase of the
pipeline when a new task gets triggered, the task takes a minimum of 3 more cycles to complete
these uninterruptible instructions adding to the delay.
• Returning to background task from normal task:
The task takes 5 cycles to return from a normal task to resume the background task instruction at the D2
phase of the pipeline.

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8.6 Software
8.6.1 CLA Examples
NOTE: These examples are located in the C2000Ware installation at the following location:
C2000Ware_VERSION#/driverlib/DEVICE_GPN/examples/CORE_IF_MULTICORE/cla
Cloud access to these examples is available at the following link: dev.ti.com C2000Ware Examples.
8.6.1.1 CLA arcsine(x) using a lookup table (cla_asin_cpu01) - C28X_DUAL
FILE: cla_ex1_asin_cpu1.c
In this example, cpu1 will be used to initialize the clocks Task 1 of the CLA on cpu2 will calculate the arcsine of
an input argument in the range (-1.0 to 1.0) using a lookup table. It is recommended to run the c28x1 core first,
followed by the C28x2 core.
Memory Allocation
• CLA1 Math Tables (RAMLS0)
– CLAasinTable - Lookup table
• CLA1 to CPU Message RAM
– fResult - Result of the lookup algorithm
• CPU to CLA1 Message RAM
– fVal - Sample input to the lookup algorithm
Watch Variables
• fVal - Argument to task 1
• fResult - Result of arcsin(fVal)
8.6.1.2 CLA Arcsine Example. - C28X_DUAL
FILE: cla_ex1_asin_cpu2.c Dual Core arcsine example. This example demonstrates how to run CLA tasks on
cpu2.cla1 It is recommended to run the c28x1 core first, followed by the C28x2 core.
8.6.1.3 CLA arcsine(x) using a lookup table (cla_asin_cpu01)
FILE: cla_ex1_asin.c
In this example, Task 1 of the CLA will calculate the arcsine of an input argument in the range (-1.0 to 1.0) using
a lookup table.
Note that since this example does not use background CLA task, the compile flag cla_background_task is
turned off for this project. Set this flag as on to enable background CLA task. The option is available in Project
Properties -> C2000 Build -> C2000 Compiler -> Advanced Options -> Runtime Model Options.
Memory Allocation
• CLA1 Math Tables (RAMLS0)
• CLA1 to CPU Message RAM
– fResult - Result of the lookup algorithm
• CPU to CLA1 Message RAM
– fVal - Sample input to the lookup algorithm
Watch Variables
• fVal - Argument to task 1
• fResult - Result of arcsin(fVal)
8.6.1.4 CLA 2 Pole 2 Zero Infinite Impulse Response Filter (cla_iir2p2z_cpu01) - C28X_DUAL
FILE: cla_ex2_iir2p2z_cpu1.c
This example implements a Transposed Direct Form II IIR filter, commonly known as a Biquad. The input vector
is a software simulated noisy signal that is fed to the biquad one sample at a time, filtered and then stored in an
output buffer for storage. It is recommended to run the c28x1 core first, followed by the C28x2 core.

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Memory Allocation
• CLA1 Data RAM 1 (RAML2)
– S1_A - Feedback coefficients
– S1_B - Feedforward coefficients
• CLA1 to CPU Message RAM
– yn - Output of the Biquad
• CPU to CLA1 Message RAM
– xn - Sample input to the filter
Watch Variables
• fBiquadOutput
• pass
• fail
8.6.1.5 CLA 2-pole 2-zero IIR Filter Example for F2837xD. - C28X_DUAL
FILE: cla_ex2_iir2p2z_cpu2.c Dual Core iir2p2z example. This example demonstrates how to run CLA tasks on
cpu2.cla1 It is recommended to run the c28x1 core first, followed by the C28x2 core.
8.6.1.6 CLA arctangent(x) using a lookup table (cla_atan_cpu01)
FILE: cla_ex2_atan.c
In this example, Task 1 of the CLA will calculate the arctangent of an input argument using a lookup table.
Note that since this example does not use background CLA task, the compile flag cla_background_task is
turned off for this project. Set this flag as on to enable background CLA task. The option is available in Project
Properties -> C2000 Build -> C2000 Compiler -> Advanced Options -> Runtime Model Options.
Memory Allocation
• CLA1 Math Tables (RAMLS0)
• CLA1 to CPU Message RAM
– fResult - Result of the lookup algorithm
• CPU to CLA1 Message RAM
– fNum - Numerator of sample input
– fDen - Denominator of sample input
Watch Variables
• fVal - Argument to task 1
• fResult - Result of arctan(fVal)
8.6.1.7 CLA background nesting task
FILE: cla_ex3_background_nesting_task.c
This example configures CLA task 1 to be triggered by EPWM1 running at 2 Hz (period = 0.5s). A background
task is configured to be triggered by CPU timer running at .5 Hz (period = 2s). CLA task 1 toggles LED1 at the
start and end of the task and the background task toggles LED2 at the start and end of the task. Background
task will be preempted by Task1 and hence LED1 will be toggling even while LED2 is ON.
Note that the compile flag cla_background_task is turned on in this project. Enabling background task adds
additional context save/restore cycles during task switching thus increasing the overall trigger-to-task latency.
If the application does not use the background CLA task, it is recommended to turn this flag off for better
performance. The option is available in Project Properties -> C2000 Build -> C2000 Compiler -> Advanced
Options -> Runtime Model Options.
External Connections
• None
Watch Variables
• None

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8.6.1.8 Controlling PWM output using CLA

FILE: cla_ex4_pwm_control.c
This example showcases how to update PWM signal output using CLA. EPWM1 is configured to generate
complementary signals on both of its channels of fixed frequency 100 KHz. EPWM4 is configured to trigger a
periodic CLA control task of frequency 10 KHz. The CLA task implements a very simple logic to vary the duty of
the EPWM1 outputs by increasing it by 0.1 in every iteration and maintaining it in the range of 0.1-0.9. For actual
use-cases, the control logic could be modified to much more complex depending upon the application. The other
CLA task (CLA task 8) is triggered by software at beginning to initialize the CLA global variables
External Connections
• Observe GPIO0 (EPWM1A) on oscilloscope
• Observe GPIO1 (EPWM1B) on oscilloscope
Watch Variables
• duty
8.6.1.9 Just-in-time ADC sampling with CLA
FILE: cla_ex5_adc_just_in_time.c
This example showcases how to utilize early-interrupt feature of ADC in combination with the low interrupt
response of CLA to enable faster system response and achieve high frequency control loops. EPWM1 is
configured to generate a PWM output signal of frequency 1 MHz and this is also used to trigger the ADC
sampling at each cycle. ADCA is configured to sample the input on Channel 0 and to generate the early interrupt
at the end of S/H + offset cycles. This interrupt is used to trigger the CLA control task. The CLA task implements
the control logic to update the duty of the PWM output based on reading the ADC sample data just-in-time i.e.
as soon as the ADC results gets latched.The early interrupt feature and low interrupt latency of CLA allows
to do some pre-processing as well before reading the ADC data and still completes updating the PWM output
before the next interrupts comes in i.e. data read and PWM update is done within a 1 MHz cycle. For illustration
purposes, 3-point moving average filter is used to simulate some processing and few steps of the filtering code
are done before reading the ADC result which we consider as pre-processing code. The ADC interrupt offset is
programmed based on the cycles consumed by the pre-processing code.
The calculation for interrupt offset value is as follows :- -ADC acquisition cycles programmed = 10 SYSCLKS
-Conversion time for 12-bit data = 10.5 ADCCLKS = N = 42 SYSCLKS -CLA task trigger to first instruction in
Fetch delay = 4 -Let the interrupt offset value be 'x' -The code inside CLA control task before ADC read takes
below cycles : Setting up profiling gpio : 3 cycles Pre-processing : 13 cycles Total = 3 + 13 = 16 cycles
As described in device TRM, in order to read just-in-time the total delay before reading ADC should be (N-2)
cycles = 40 i.e. : x + 4 + 16 = 40 : x = 20
NOTE :- The optimization is off for this project and the cycles quoted above corresponds to that case.
GPIO2 is used for profiling purposes. GPIO2 is set at the beginning of CLA task 1 and is reset at the end of the
task. Thus ON time of GPIO2 indicates the CLA activity. In order to validate the example functionality , observe
the GPIO0 (PWM output) and GPIO2 (profiling GPIO) on CRO. The cycles difference between the rising edge of
the GPIO0 and GPIO2 indicate the total delay from the time of ADC trigger to setting up of profiling GPIO inside
CLA task which should be around 44 cycles (220 ns) based on the above calculation.
External Connections
• Provide constant DC input on ADCA0 for quick validation. GND -> Should observe PWM output duty = 0.1
3.3V -> Should observe PWM output duty = 0.9 Can also provide analog input in range 0 - 3.3V upto fs / 10 =
100 KHz for observing continuous duty variations
• Observe GPIO0 on oscilloscope
• Observe GPIO2 on oscilloscope
Watch Variables
• None

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8.6.1.10 Optimal offloading of control algorithms to CLA

FILE: cla_ex6_cpu_offloading.c
This example showcases how to optimally offload the control algorithms from CPU to CLA in order to meet the
system requirements. In this example, two control loops are simulated, the faster one (loop1) running at 200 KHz
and the slower one (loop2) running at 20 KHz. Loop1 senses the first parameter at ADCA Channel 0, runs the
PI controller to achieve the target and contributes to the duty of EPWM1A output with 80% weightage. Loop2
senses the second parameter at ADCB Channel 2, runs the PI controller and contributes to the duty of EPWM1A
output with 20% weightage. It is important to note that since these are just software simulated control loops but
there is no actual physical process involved and hence updating the duty is not going to have any affect on
sampled inputs. ADCA is configured to oversample the first parameter using SOCs 0-3 to suppress the noise
and similarly ADCB is used to oversample the second parameter. EPWM4 and EPWM5 are configured to trigger
the ADCA and ADCB sampling at loop1 and loop2 frequencies respectively. Once the conversion of all 4 SOCs
complete, a CPU ISR or a CLA task is triggered based on the user-configuration. There is also a background
task running in the main loop which disables the entire system including PWM output and the control loops
when "system_OFF" is set to 1. The system gets enabled again once "system_OFF" is restored back to 0. By
default system_OFF is set to 0 but it's value can be updated dynamically by adding it to expression window and
writing to it. DCL library is included in the project to make use of optimal PI controllers used in both the loops.
User-configurable pre-defined symbol "run_loop1_cla" has been added to the project options in order to specify
whether to run the loop1 on C28x or CLA. GPIO2 and GPIO3 are used to profile the execution of loop1 and
loop2.
For run_loop1_cla == 0 i.e. both loops running on CPU -> Loop1 Utilization = ~77.5% (measured using profiling
GPIO2) -> Loop2 Utilization = ~6% (measured using profiling GPIO3) -> Background task in a while loop ->
Total CPU utilization is greater than Utilization bound (UB) Hence the system is non-schedulable, lower priority
task (Loop2) execution never completes (no toggling observed on GPIO3) and also background task never gets
chance to execute
For run_loop1_cla == 1 i.e. high frequency control loop (loop1) is offloaded to CLA while loop2 runs on CPU ->
Loop1 Utilization (CLA) = ~73% -> Loop2 Utilization (CPU)= ~6% -> Total CPU utilization has come down to just
~6% Hence the system is perfectly schedulable, no miss happens for any of the loops and offloading of loop1 to
CLA saves CPU bandwidth to execute background tasks as well
For quick inspection of the example functionality, constant DC HIGH/LOW inputs can be provided to the analog
channels instead of varying analog voltages. The target value for both the loops are set as some intermediate
value i.e. 3500 corresponds to ~2.8V. Now since the sensed inputs are constant and not same as target so the
controller outputs will get saturated soon to either 1 or 0. Thus the "duty" variable can take only fixed values
based on the equations used in the loops. Infact the duty output would be very intutive, for instance if both inputs
are LOW(GND), the controller will try to produce the maximum duty as the target is higher than sensed value
hence the duty should be 1.0(0.2 + 0.8) but will get saturated to 0.9(the maximum value defined). Similarly if
both inputs are made HIGH, the duty will be 0.1 (the minimum saturation value defined). The final duty table is
shown below :
External Connections
• Observe GPIO2 (Loop1 Profiling) on oscilloscope
• Observe GPIO3 (Loop2 Profiling) on oscilloscope
• Observe GPIO0 (EPWM1A Output) on oscilloscope
• Provide constant HIGH(3.3V)/LOW(0V) on both ADCA Ch0 and ADCB Ch2 for quick validation, the following
duty value should be observable at EPWM1A for various combinations if the system is perfectly schedulable
i.e. both loops gets chance to execute properly :- A0 B2 duty GND GND 0.9 3.3V GND 0.2 GND 3.3V
0.8 3.3V 3.3V 0.1 Note :- The optimization is OFF for this project and all the profiling data quoted above
corresponds to this case.
8.6.1.11 Handling shared resources across C28x and CLA
FILE: cla_ex7_shared_resource_handling.c

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This example showcases how to handle shared resource challenges across C28x and CLA. As the peripherals
are shared between CLA and the CPU, overlapping read-modify-write to the registers by them can lead to data
race conditions ultimately leading to data violation or incorrect functionality. In this example, CPU ISR and CLA
tasks runs independently. CPU ISR gets triggered by EPWM4 @10KHz and toggles the EPWM1B output via
software by controlling CSFB bits of AQCSFRC. CLA task gets triggered by EPWM5 @100Khz and toggles the
EPWM1A output via software by controlling CSFA bits of AQCSFRC. Thus in this process both CPU and CLA
do read-modify -write to AQCSFRC register independently at different frequencies so there is chance of race
condition and updates due to one of them can get lost/. overwritten. This can be clearly observed by updating
"phase_shift_ON" to 0U and probing the EPWM1A and 1B outputs on a scope.
This is a standard critical section problem and can be handled by software handshaking mechanism like
mutex etc. But most of the real-time control applications are time-sensitive and cannot afford addition software
overhead hence this example suggests an alternative hardware based technique to avoid shared resource
conflicts between CPU and CLA. The phase shifting mechanism of the EPWM modules is utilized to schedule
the CLA task and CPU ISR as desired. EPWM4 generates a synchronous pulse every ZERO event and provides
a phase shift of 20 cycles to EPWM5. This way both CLA task and C28x ISR runs at original frequencies
i.e. 100KHz and 10KHz but CLA task leads with a phase offset of 20 cycles wrt CPU ISR. Hence concurrent
read-modify-writes to AQCSFRC never happens and the EPWM1A and EPWM1B outputs behave as desired
i.e. consistent 50 KHz PWM output on EPWM1A and 5 KHz PWM output on EPWM1B with a duty ~50% on
both should be generated. In order to utilize this phase shifting mechanism in this example, please make sure
"phase_shift_ON" is set to 1.
External Connections
• Observe GPIO0 (EPWM1A Output) on oscilloscope
• Observe GPIO1 (EPWM1B Output) on oscilloscope
• Observe GPIO2 (CLA Task Profiling) on oscilloscope
• Observe GPIO3 (CPU ISR Profiling) on oscilloscope
Note :- The phase offset value can easily be configured by updating TBPHS register to schedule the CLA task
and C28x ISR as desired depending upon the application need so as to avoid overlapping register writes by
CPU and CLA
Note :- The optimization is on and set to O2 for the project and all the results quoted correspond to this case.

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8.7 Instruction Set

This section describes the assembly language instructions of the control law accelerator. Also described are
parallel operations, conditional operations, resource constraints, and addressing modes. The instructions listed
here are independent from C28x and C28x+FPU instruction sets.
8.7.1 Instruction Descriptions
This section gives detailed information on the instruction set. Each instruction may present the following
information:
• Operands
• Opcode
• Description
• Exceptions
• Pipeline
• Examples
• See also
The example INSTRUCTION is shown to familiarize you with the way each instruction is described. The example
describes the kind of information you will find in each part of the individual instruction description and where to
obtain more information. CLA instructions follow the same format as the C28x; the source operand(s) are always
on the right and the destination operand(s) are on the left.
The explanations for the syntax of the operands used in the instruction descriptions for the C28x CLA are given
in Table 8-6.
Table 8-6. Operand Nomenclature
Symbol Description
#16FHi 16-bit immediate (hex or float) value that represents the upper 16-bits of an IEEE 32-bit floating-point value.
Lower 16-bits of the mantissa are assumed to be zero.
#16FHiHex 16-bit immediate hex value that represents the upper 16-bits of an IEEE 32-bit floating-point value.
Lower 16-bits of the mantissa are assumed to be zero.
#16FLoHex A 16-bit immediate hex value that represents the lower 16-bits of an IEEE 32-bit floating-point value
#32Fhex 32-bit immediate value that represents an IEEE 32-bit floating-point value
#32F Immediate float value represented in floating-point representation
#0.0 Immediate zero
#SHIFT Immediate value of 1 to 32 used for arithmetic and logical shifts.
addr Opcode field indicating the addressing mode
CNDF Condition to test the flags in the MSTF register
FLAG Selected flags from MSTF register (OR) 8 bit mask indicating which floating-point status flags to change
MAR0 auxiliary register 0
MAR1 auxiliary register 1
MARx Either MAR0 or MAR1
mem16 16-bit memory location accessed using direct, indirect, or offset addressing modes
mem32 32-bit memory location accessed using direct, indirect, or offset addressing modes
MRa MR0 to MR3 registers
MRb MR0 to MR3 registers
MRc MR0 to MR3 registers
MRd MR0 to MR3 registers
MRe MR0 to MR3 registers
MRf MR0 to MR3 registers
MSTF CLA Floating-point Status Register
shift Opcode field indicating the number of bits to shift.

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Table 8-6. Operand Nomenclature (continued)

Symbol Description
VALUE Flag value of 0 or 1 for selected flag (OR) 8 bit mask indicating the flag value; 0 or 1

Each instruction has a table that gives a list of the operands and a short description. Instructions always have
their destination operand(s) first followed by the source operand(s).
Table 8-7. INSTRUCTION dest, source1, source2 Short Description
Description
dest1 Description for the 1st operand for the instruction
source1 Description for the 2nd operand for the instruction
source2 Description for the 3rd operand for the instruction
Opcode This section shows the opcode for the instruction
Description Detailed description of the instruction execution is described. Any constraints on the operands imposed by the
processor or the assembler are discussed.
Restrictions Any constraints on the operands or use of the instruction imposed by the processor are discussed.
Pipeline This section describes the instruction in terms of pipeline cycles as described in Section 8.5
Example Examples of instruction execution. If applicable, register and memory values are given before and after instruction
execution. Some examples are code fragments while other examples are full tasks that assume the CLA is correctly
configured and the main CPU has passed it data.
Operands Each instruction has a table that gives a list of the operands and a short description. Instructions always have their
destination operand(s) first followed by the source operand(s).

8.7.2 Addressing Modes and Encoding

The CLA uses the same address to access data and registers as the main CPU. For example, if the main CPU
accesses an ePWM register at address 0x00 6800, then the CLA accesses the register using address 0x6800.
Since all CLA accessible memory and registers are within the low 64k x 16 of memory, only the low 16-bits of the
address are used by the CLA.
To address the CLA data memory, message RAMs and shared peripherals, the CLA supports two addressing
modes:
• Direct addressing mode: Uses the address of the variable or register directly.
• Indirect addressing with 16-bit post increment. This mode uses either XAR0 or XAR1.
The CLA does not use a data page pointer or a stack pointer. The two addressing modes are encoded as shown
Table 8-8.

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Table 8-8. Addressing Modes

Addressing Mode 'addr' Opcode Description
Field
Encode(1)
@dir 0000 Direct Addressing Mode
Example 1: MMOV32 MR1, @_VarA
Example 2: MMOV32 MR1, @_EPwm1Regs.CMPA.all
In this case, the 'mmmm mmmm mmmm mmmm' opcode field is populated with the 16-bit
address of the variable. This is the low 16-bits of the address to access the variable using the
main CPU.
For example, @_VarA populates the address of the variable VarA. and
@_EPwm1Regs.CMPA.all populates the address of the CMPA register.
*MAR0[#imm16]++ 0001 MAR0 Indirect Addressing with 16-bit Immediate Post Increment
*MAR1[#imm16]++ 0010 MAR1 Indirect Addressing with 16-bit Immediate Post Increment
addr = MAR0 (or MAR1) Access memory using the address stored in MAR0 (or MAR1).
MAR0 (or MAR1) += Then post increment MAR0 (or MAR1) by #imm16.
#imm16
Example 1: MMOV32 MR0, *MAR0[2]++
Example 2: MMOV32 MR1, *MAR1[-2]++
For a post increment of 0, the assembler accepts both *MAR0 and *MAR0[0]++.
The 'mmmm mmmm mmmm mmmm' opcode field is populated with the signed 16-bit pointer
offset. For example, if #imm16 is 2, then the opcode field is 0x0002. Likewise, if #imm16 is -2,
then the opcode field is 0xFFFE.
If addition of the 16-bit immediate causes overflow, then the value wraps around on a 16-bit
boundary.
*MAR0+[#imm16] 0101 MAR0 Offset Addressing with 16-bit Immediate Offset
*MAR1+[#imm16] 0110 MAR1 Offset Addressing with 16-bit Immediate Offset
addr = MAR0 Add the offset #imm16
(or MAR1) + #imm16to address stored in MAR0(MAR1) to access the desired memory
the base location
Example 1: MMOV32 MR0, *MAR0+[2]
Example 1: MMOV32 MR1, *MAR1+[-2]
The ‘mmmm mmmm mmmm mmmm’ opcode field is populated with the signed 16-bit pointer
offset. For example, if #imm16 is 2, then the opcode field is 0x0002. Likewise, if #imm16 is -2,
then the opcode field is 0xFFFE.
If the addition of the 16-bit immediate causes overflow, the value wraps around on a 16-bit
boundary.

(1) Values not shown are reserved.

Encoding for the shift fields in the MASR32, MLSR32 and MLSL32 instructions is shown in Table 8-9.
Table 8-9. Shift Field Encoding
Shift Value 'shift' Opcode
Field Encode
1 0000
2 0001
3 0010
.... ....
32 1111

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For instructions that use MRx (where x can be 'a' through 'f') as operands, the trailing alphabet appears in the
opcode as a two-bit field. For example:

MMPYF32 MRa, MRb, MRc ||

MADDF32 MRd, MRe, MRf

whose opcode is,

LSW: 0000 ffee ddcc bbaa

MSW: 0111 1010 0000 0000

The two-bit field specifies one of four working registers according to Table 8-10.
Table 8-10. Operand Encoding
Two-Bit Field Working Register
00 MR0
01 MR1
10 MR2
11 MR3

Table 8-11 shows the condition field encoding for conditional instructions such as MNEGF, MSWAPF, MBCNDD,
MCCNDD, and MRCNDD.
Table 8-11. Condition Field Encoding
Encode(1) CNDF Description MSTF Flags Tested
0000 NEQ Not equal to zero ZF == 0
0001 EQ Equal to zero ZF == 1
0010 GT Greater than zero ZF == 0 AND NF == 0
0011 GEQ Greater than or equal to zero NF == 0
0100 LT Less than zero NF == 1
0101 LEQ Less than or equal to zero ZF == 1 OR NF == 1
1010 TF Test flag set TF == 1
1011 NTF Test flag not set TF == 0
1100 LU Latched underflow LUF == 1
1101 LV Latched overflow LVF == 1
1110 UNC Unconditional None
1111 UNCF(2) Unconditional with flag modification None

(1) Values not shown are reserved.

(2) This is the default operation, if no CNDF field is specified. This condition allows the ZF and NF flags to be modified when a conditional
operation is executed. All other conditions do not modify these flags.

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8.7.3 Instructions
The instructions are listed alphabetically.

Instruction Set Summary

MABSF32 MRa, MRb — 32-Bit Floating-Point Absolute Value.........................................................................1000
MADD32 MRa, MRb, MRc — 32-Bit Integer Add..............................................................................................1001
MADDF32 MRa, #16FHi, MRb — 32-Bit Floating-Point Addition......................................................................1002
MADDF32 MRa, MRb, #16FHi — 32-Bit Floating-Point Addition......................................................................1003
MADDF32 MRa, MRb, MRc — 32-Bit Floating-Point Addition..........................................................................1005
MADDF32 MRd, MRe, MRf||MMOV32 mem32, MRa — 32-Bit Floating-Point Addition with Parallel Move.... 1006
MADDF32 MRd, MRe, MRf ||MMOV32 MRa, mem32 — 32-Bit Floating-Point Addition with Parallel Move... 1007
MAND32 MRa, MRb, MRc — Bitwise AND.......................................................................................................1009
MASR32 MRa, #SHIFT — Arithmetic Shift Right.............................................................................................. 1010
MBCNDD 16BitDest {, CNDF} — Branch Conditional Delayed........................................................................1011
MCCNDD 16BitDest {, CNDF} — Call Conditional Delayed.............................................................................1016
MCLRC BGINTM — Clear Background Task Interrupt Mask............................................................................ 1020
MCMP32 MRa, MRb — 32-Bit Integer Compare for Equal, Less Than or Greater Than..................................1021
MCMPF32 MRa, MRb — 32-Bit Floating-Point Compare for Equal, Less Than or Greater Than.....................1022
MCMPF32 MRa, #16FHi — 32-Bit Floating-Point Compare for Equal, Less Than or Greater Than.................1023
MDEBUGSTOP — Debug Stop Task................................................................................................................ 1025
MDEBUGSTOP1 — Software Breakpoint......................................................................................................... 1026
MEALLOW — Enable CLA Write Access to EALLOW Protected Registers..................................................... 1027
MEDIS — Disable CLA Write Access to EALLOW Protected Registers........................................................... 1028
MEINVF32 MRa, MRb — 32-Bit Floating-Point Reciprocal Approximation.......................................................1029
MEISQRTF32 MRa, MRb — 32-Bit Floating-Point Square-Root Reciprocal Approximation............................ 1030
MF32TOI16 MRa, MRb — Convert 32-Bit Floating-Point Value to 16-Bit Integer............................................. 1032
MF32TOI16R MRa, MRb — Convert 32-Bit Floating-Point Value to 16-Bit Integer and Round........................1033
MF32TOI32 MRa, MRb — Convert 32-Bit Floating-Point Value to 32-Bit Integer............................................. 1034
MF32TOUI16 MRa, MRb — Convert 32-Bit Floating-Point Value to 16-bit Unsigned Integer ..........................1035
MF32TOUI16R MRa, MRb — Convert 32-Bit Floating-Point Value to 16-bit Unsigned Integer and Round..... 1036
MF32TOUI32 MRa, MRb — Convert 32-Bit Floating-Point Value to 32-Bit Unsigned Integer ......................... 1037
MFRACF32 MRa, MRb — Fractional Portion of a 32-Bit Floating-Point Value................................................. 1038
MI16TOF32 MRa, MRb — Convert 16-Bit Integer to 32-Bit Floating-Point Value ............................................ 1039
MI16TOF32 MRa, mem16 — Convert 16-Bit Integer to 32-Bit Floating-Point Value ....................................... 1040
MI32TOF32 MRa, mem32 — Convert 32-Bit Integer to 32-Bit Floating-Point Value ....................................... 1041
MI32TOF32 MRa, MRb — Convert 32-Bit Integer to 32-Bit Floating-Point Value ............................................ 1042
MLSL32 MRa, #SHIFT — Logical Shift Left...................................................................................................... 1043
MLSR32 MRa, #SHIFT — Logical Shift Right................................................................................................... 1044
MMACF32 MR3, MR2, MRd, MRe, MRf ||MMOV32 MRa, mem32 — 32-Bit Floating-Point Multiply and
Accumulate with Parallel Move.......................................................................................................................... 1045
MMAXF32 MRa, MRb — 32-Bit Floating-Point Maximum.................................................................................1048
MMAXF32 MRa, #16FHi — 32-Bit Floating-Point Maximum.............................................................................1050
MMINF32 MRa, MRb — 32-Bit Floating-Point Minimum................................................................................... 1051
MMINF32 MRa, #16FHi — 32-Bit Floating-Point Minimum............................................................................... 1053
MMOV16 MARx, MRa, #16I — Load the Auxiliary Register with MRa + 16-bit Immediate Value.................... 1054
MMOV16 MARx, mem16 — Load MAR1 with 16-bit Value.............................................................................. 1057
MMOV16 mem16, MARx — Move 16-Bit Auxiliary Register Contents to Memory........................................... 1060
MMOV16 mem16, MRa — Move 16-Bit Floating-Point Register Contents to Memory..................................... 1061
MMOV32 mem32, MRa — Move 32-Bit Floating-Point Register Contents to Memory .................................... 1063
MMOV32 mem32, MSTF — Move 32-Bit MSTF Register to Memory...............................................................1064
MMOV32 MRa, mem32 {, CNDF} — Conditional 32-Bit Move......................................................................... 1065
MMOV32 MRa, MRb {, CNDF} — Conditional 32-Bit Move..............................................................................1067
MMOV32 MSTF, mem32 — Move 32-Bit Value from Memory to the MSTF Register.......................................1069

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MMOVD32 MRa, mem32 — Move 32-Bit Value from Memory with Data Copy................................................1070
MMOVF32 MRa, #32F — Load the 32-Bits of a 32-Bit Floating-Point Register................................................ 1072
MMOVI16 MARx, #16I — Load the Auxiliary Register with the 16-Bit Immediate Value.................................. 1073
MMOVI32 MRa, #32FHex — Load the 32-Bits of a 32-Bit Floating-Point Register with the Immediate........... 1075
MMOVIZ MRa, #16FHi — Load the Upper 16-Bits of a 32-Bit Floating-Point Register ....................................1077
MMOVZ16 MRa, mem16 — Load MRx with 16-Bit Value.................................................................................1078
MMOVXI MRa, #16FLoHex — Move Immediate Value to the Lower 16-Bits of a Floating-Point Register.......1079
MMPYF32 MRa, MRb, MRc — 32-Bit Floating-Point Multiply...........................................................................1080
MMPYF32 MRa, #16FHi, MRb — 32-Bit Floating-Point Multiply ..................................................................... 1081
MMPYF32 MRa, MRb, #16FHi — 32-Bit Floating-Point Multiply ..................................................................... 1083
MMPYF32 MRa, MRb, MRc||MADDF32 MRd, MRe, MRf — 32-Bit Floating-Point Multiply with Parallel Add.1085
MMPYF32 MRd, MRe, MRf ||MMOV32 MRa, mem32 — 32-Bit Floating-Point Multiply with Parallel Move.... 1087
MMPYF32 MRd, MRe, MRf ||MMOV32 mem32, MRa — 32-Bit Floating-Point Multiply with Parallel Move.... 1089
MMPYF32 MRa, MRb, MRc ||MSUBF32 MRd, MRe, MRf — 32-Bit Floating-Point Multiply with Parallel Subtract
...........................................................................................................................................................................1090
MNEGF32 MRa, MRb{, CNDF} — Conditional Negation..................................................................................1091
MNOP — No Operation..................................................................................................................................... 1093
MOR32 MRa, MRb, MRc — Bitwise OR........................................................................................................... 1094
MRCNDD {CNDF} — Return Conditional Delayed............................................................................................1095
MSETC BGINTM — Set Background Task Interrupt Mask................................................................................1098
MSETFLG FLAG, VALUE — Set or Clear Selected Floating-Point Status Flags............................................. 1099
MSTOP — Stop Task......................................................................................................................................... 1100
MSUB32 MRa, MRb, MRc — 32-Bit Integer Subtraction.................................................................................. 1102
MSUBF32 MRa, MRb, MRc — 32-Bit Floating-Point Subtraction..................................................................... 1103
MSUBF32 MRa, #16FHi, MRb — 32-Bit Floating-Point Subtraction.................................................................1104
MSUBF32 MRd, MRe, MRf ||MMOV32 MRa, mem32 — 32-Bit Floating-Point Subtraction with Parallel Move....
1106
MSUBF32 MRd, MRe, MRf ||MMOV32 mem32, MRa — 32-Bit Floating-Point Subtraction with Parallel Move....
1107
MSWAPF MRa, MRb {, CNDF} — Conditional Swap........................................................................................1108
MTESTTF CNDF — Test MSTF Register Flag Condition.................................................................................. 1110
MUI16TOF32 MRa, mem16 — Convert Unsigned 16-Bit Integer to 32-Bit Floating-Point Value...................... 1112
MUI16TOF32 MRa, MRb — Convert Unsigned 16-Bit Integer to 32-Bit Floating-Point Value...........................1113
MUI32TOF32 MRa, mem32 — Convert Unsigned 32-Bit Integer to 32-Bit Floating-Point Value...................... 1114
MUI32TOF32 MRa, MRb — Convert Unsigned 32-Bit Integer to 32-Bit Floating-Point Value...........................1115
MXOR32 MRa, MRb, MRc — Bitwise Exclusive Or.......................................................................................... 1116

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MABSF32 MRa, MRb

32-Bit Floating-Point Absolute Value

Operands MRa CLA floating-point destination register (MR0 to MR3)

MRb CLA floating-point source register (MR0 to MR3)

Opcode
LSW: 0000 0000 0000 bbaa
MSW: 0111 1110 0010 0000

Description The absolute value of MRb is loaded into MRa. Only the sign bit of the operand is
modified by the MABSF32 instruction.

if (MRb < 0) {MRa = -MRb};

else {MRa = MRb};

Flags This instruction modifies the following flags in the MSTF register:
Flag TF ZF NF LUF LVF
Modified No Yes Yes No No

The MSTF register flags are modified as follows:

NF = 0;
ZF = 0;
if ( MRa(30:23) == 0) ZF = 1;

Pipeline This is a single-cycle instruction.

Example
MMOVIZ MR0, #-2.0 ; MR0 = -2.0 (0xC0000000)
MABSF32 MR0, MR0 ; MR0 = 2.0 (0x40000000), ZF = NF = 0
MMOVIZ MR0, #5.0 ; MR0 = 5.0 (0x40A00000)
MABSF32 MR0, MR0 ; MR0 = 5.0 (0x40A00000), ZF = NF = 0
MMOVIZ MR0, #0.0 ; MR0 = 0.0
MABSF32 MR0, MR0 ; MR0 = 0.0 ZF = 1, NF = 0

See also MNEGF32 MRa, MRb {, CNDF}

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MADD32 MRa, MRb, MRc

32-Bit Integer Add

Operands MRa CLA floating-point destination register (MR0 to MR3)

MRb CLA floating-point destination register (MR0 to MR3)
MRc CLA floating-point destination register (MR0 to MR3)

Opcode
LSW: 0000 0000 000cc bbaa
MSW: 0111 1110 1100 0000

Description 32-bit integer addition of MRb and MRc.

MRa(31:0) = MRb(31:0) + MRc(31:0);

Flags This instruction modifies the following flags in the MSTF register:
Flag TF ZF NF LUF LVF
Modified No Yes Yes No No

The MSTF register flags are modified based on the integer results of the operation.

NF = MRa(31);
ZF = 0;
if(MRa(31:0) == 0) { ZF = 1; };

Pipeline This is a single-cycle instruction.

Example
; Given A = (int32)1
; B = (int32)2
; C = (int32)-7
;
; Calculate Y2 = A + B + C
;
_Cla1Task1:
MMOV32 MR0, @_A ; MR0 = 1 (0x00000001)
MMOV32 MR1, @_B ; MR1 = 2 (0x00000002)
MMOV32 MR2, @_C ; MR2 = -7 (0xFFFFFFF9)
MADD32 MR3, MR0, MR1 ; A + B
MADD32 MR3, MR2, MR3 ; A + B + C = -4 (0xFFFFFFFC)
MMOV32 @_y2, MR3 ; Store y2
MSTOP ; end of task

See also MAND32 MRa, MRb, MRc

MASR32 MRa, #SHIFT
MLSL32 MRa, #SHIFT
MLSR32 MRa, #SHIFT
MOR32 MRa, MRb, MRc
MXOR32 MRa, MRb, MRc
MSUB32 MRa, MRb, MRc

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MADDF32 MRa, #16FHi, MRb

32-Bit Floating-Point Addition

Operands MRa CLA floating-point destination register (MR0 to MR3)

#16FHi A 16-bit immediate value that represents the upper 16-bits of an
IEEE 32-bit floating-point value. The low 16-bits of the mantissa
are assumed to be all 0.
MRb CLA floating-point source register (MR0 to MR3)

Opcode
LSW: IIII IIII IIII IIII
MSW: 0111 0111 1100 bbaa

Description Add MRb to the floating-point value represented by the immediate operand. Store the
result of the addition in MRa.
#16FHi is a 16-bit immediate value that represents the upper 16-bits of an IEEE 32-bit
floating-point value. The low 16-bits of the mantissa are assumed to be all 0. #16FHi is
most useful for representing constants where the lowest 16-bits of the mantissa are 0.
Some examples are 2.0 (0x40000000), 4.0 (0x40800000), 0.5 (0x3F000000), and -1.5
(0xBFC00000). The assembler accepts either a hex or float as the immediate value. That
is, the value -1.5 can be represented as #-1.5 or #0xBFC0.

MRa = MRb + #16FHi:0;

This instruction can also be written as MADDF32 MRa, MRb, #16FHi.

Flags This instruction modifies the following flags in the MSTF register:
Flag TF ZF NF LUF LVF
Modified No No No Yes Yes

The MSTF register flags are modified as follows:

• LUF = 1 if MADDF32 generates an underflow condition.
• LVF = 1 if MADDF32 generates an overflow condition.
Pipeline This is a single-cycle instruction.

Example
; Add to MR1 the value 2.0 in 32-bit floating-point format
; Store the result in MR0
MADDF32 MR0, #2.0, MR1 ; MR0 = 2.0 + MR1
; Add to MR3 the value -2.5 in 32-bit floating-point format
; Store the result in MR2
MADDF32 MR2, #-2.5, MR3 ; MR2 = -2.5 + MR3
; Add to MR3 the value 0x3FC00000 (1.5)
; Store the result in MR3
MADDF32 MR3, #0x3FC0, MR3 ; MR3 = 1.5 + MR3

See also MADDF32 MRa, MRb, #16FHi

MADDF32 MRa, MRb, MRc
MADDF32 MRd, MRe, MRf || MMOV32 MRa, mem32
MADDF32 MRd, MRe, MRf || MMOV32 mem32, MRa
MMPYF32 MRa, MRb, MRc || MADDF32 MRd, MRe, MRf

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MADDF32 MRa, MRb, #16FHi

32-Bit Floating-Point Addition

Operands MRa CLA floating-point destination register (MR0 to MR3)

MRb CLA floating-point source register (MR0 to MR3)
#16FHi A 16-bit immediate value that represents the upper 16-bits of an
IEEE 32-bit floating-point value. The low 16-bits of the mantissa
are assumed to be all 0.

Opcode
LSW: IIII IIII IIII IIII
MSW: 0111 0111 1100 bbaa

Description Add MRb to the floating-point value represented by the immediate operand. Store the
result of the addition in MRa.
#16FHi is a 16-bit immediate value that represents the upper 16-bits of an IEEE 32-bit
floating-point value. The low 16-bits of the mantissa are assumed to be all 0. #16FHi is
most useful for representing constants where the lowest 16-bits of the mantissa are 0.
Some examples are 2.0 (0x40000000), 4.0 (0x40800000), 0.5 (0x3F000000), and -1.5
(0xBFC00000). The assembler accepts either a hex or float as the immediate value. That
is, the value -1.5 can be represented as #-1.5 or #0xBFC0.

MRa = MRb + #16FHi:0;

This instruction can also be written as MADDF32 MRa, #16FHi, MRb.

Flags This instruction modifies the following flags in the MSTF register:
Flag TF ZF NF LUF LVF
Modified No No No Yes Yes

The MSTF register flags are modified as follows:

• LUF = 1 if MADDF32 generates an underflow condition.
• LVF = 1 if MADDF32 generates an overflow condition.

Pipeline This is a single-cycle instruction.

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MADDF32 MRa, MRb, #16FHi (continued)

32-Bit Floating-Point Addition

Example 1
; X is an array of 32-bit floating-point values
; Find the maximum value in an array X
; and store the value in Result
;
_Cla1Task1:
MMOVI16 MAR1,#_X ; Start address
MUI16TOF32 MR0, @_len ; Length of the array
MNOP ; delay for MAR1 load
MNOP ; delay for MAR1 load
MMOV32 MR1, *MAR1[2]++ ; MR1 = X0
LOOP
MMOV32 MR2, *MAR1[2]++ ; MR2 = next element
MMAXF32 MR1, MR2 ; MR1 = MAX(MR1, MR2)
MADDF32 MR0, MR0, #-1.0 ; Decrement the counter
MCMPF32 MR0 #0.0 ; Set/clear flags for MBCNDD
MNOP
MNOP
MNOP
MBCNDD LOOP, NEQ ; Branch if not equal to zero
MMOV32 @_Result, MR1 ; Always executed
MNOP ; Always executed
MNOP ; Always executed
MSTOP ; End of task

Example 2
; Show the basic operation of MADDF32
;
; Add to MR1 the value 2.0 in 32-bit floating-point format
; Store the result in MR0
MADDF32 MR0, MR1, #2.0 ; MR0 = MR1 + 2.0
; Add to MR3 the value -2.5 in 32-bit floating-point format
; Store the result in MR2
MADDF32 MR2, MR3, #-2.5 ; MR2 = MR3 + (-2.5)
; Add to MR0 the value 0x3FC00000 (1.5)
; Store the result in MR0
MADDF32 MR0, MR0, #0x3FC0 ; MR0 = MR0 + 1.5

See also MADDF32 MRa, #16FHi, MRb

MADDF32 MRa, MRb, MRc
MADDF32 MRd, MRe, MRf || MMOV32 MRa, mem32
MADDF32 MRd, MRe, MRf || MMOV32 mem32, MRa
MMPYF32 MRa, MRb, MRc || MADDF32 MRd, MRe, MRf

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MADDF32 MRa, MRb, MRc

32-Bit Floating-Point Addition

Operands MRa CLA floating-point destination register (MR0 to MR3)

MRb CLA floating-point source register (MR0 to MR3)
MRc CLA floating-point source register (MR0 to MR3)

Opcode
LSW: 000 0000 00cc bbaa
MSW: 0111 1100 0010 0000

Description Add the contents of MRc to the contents of MRb and load the result into MRa.

MRa = MRb + MRc;

Flags This instruction modifies the following flags in the MSTF register:
Flag TF ZF NF LUF LVF
Modified No No No Yes Yes

The MSTF register flags are modified as follows:

• LUF = 1 if MADDF32 generates an underflow condition.
• LVF = 1 if MADDF32 generates an overflow condition.
Pipeline This is a single-cycle instruction.

Example
; Given M1, X1, and B1 are 32-bit floating-point numbers
; Calculate Y1 = M1*X1+B1
;
_Cla1Task1:
MMOV32 MR0,@M1 ; Load MR0 with M1
MMOV32 MR1,@X1 ; Load MR1 with X1
MMPYF32 MR1,MR1,MR0 ; Multiply M1*X1
|| MMOV32 MR0,@B1 ; and in parallel load MR0 with B1
MADDF32 MR1,MR1,MR0 ; Add M*X1 to B1 and store in MR1
MMOV32 @Y1,MR1 ; Store the result
MSTOP ; end of task

See also MADDF32 MRa, #16FHi, MRb

MADDF32 MRa, MRb, #16FHi
MADDF32 MRd, MRe, MRf || MMOV32 MRa, mem32
MADDF32 MRd, MRe, MRf || MMOV32 mem32, MRa
MMPYF32 MRa, MRb, MRc || MADDF32 MRd, MRe, MRf

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MADDF32 MRd, MRe, MRf||MMOV32 mem32, MRa

32-Bit Floating-Point Addition with Parallel Move

Operands MRd CLA floating-point destination register for the MADDF32 (MR0 to
MR3)
MRe CLA floating-point source register for the MADDF32 (MR0 to MR3)
MRf CLA floating-point source register for the MADDF32 (MR0 to MR3)
mem32 32-bit memory location accessed using one of the available
addressing modes. This is the destination of the MMOV32.
MRa CLA floating-point source register for the MMOV32 (MR0 to MR3)

Opcode
LSW: mmmm mmmm mmmm mmmm
MSW: 0101 ffee ddaa addr

Description Perform an MADDF32 and a MMOV32 in parallel. Add MRf to the contents of MRe
and store the result in MRd. In parallel move the contents of MRa to the 32-bit location
mem32.

MRd = MRe + MRf;

[mem32] = MRa;

Flags This instruction modifies the following flags in the MSTF register:
Flag TF ZF NF LUF LVF
Modified No No No Yes Yes

The MSTF register flags are modified as follows:

• LUF = 1 if MADDF32 generates an underflow condition.
• LVF = 1 if MADDF32 generates an overflow condition.
Pipeline Both MADDF32 and MMOV32 complete in a single cycle.

Example
; Given A, B, and C are 32-bit floating-point numbers
; Calculate Y2 = (A * B)
; Y3 = (A * B) + C
;
_Cla1Task2:
MMOV32 MR0, @_A ; Load MR0 with A
MMOV32 MR1, @_B ; Load MR1 with B
MMPYF32 MR1, MR1, MR0 ; Multiply A*B
|| MMOV32 MR0, @_C ; and in parallel load MR0 with C
MADDF32 MR1, MR1, MR0 ; Add (A*B) to C
|| MMOV32 @_Y2, MR1 ; and in parallel store A*B
MMOV32 @_Y3, MR1 ; Store the A*B + C
MSTOP ; end of task

See also MADDF32 MRa, #16FHi, MRb

MADDF32 MRa, MRb, #16FHi
MADDF32 MRa, MRb, MRc
MMPYF32 MRa, MRb, MRc || MADDF32 MRd, MRe, MRf
MADDF32 MRd, MRe, MRf || MMOV32 MRa, mem32

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MADDF32 MRd, MRe, MRf ||MMOV32 MRa, mem32

32-Bit Floating-Point Addition with Parallel Move

Operands MRd CLA floating-point destination register for the MADDF32 (MR0 to
MR3).
MRd cannot be the same register as MRa.
MRe CLA floating-point source register for the MADDF32 (MR0 to MR3)
MRf CLA floating-point source register for the MADDF32 (MR0 to MR3)
MRa CLA floating-point destination register for the MMOV32 (MR0 to
MR3).
MRa cannot be the same register as MRd.
mem32 32-bit memory location accessed using one of the available
addressing modes. This is the source for the MMOV32.

Opcode
LSW: mmmm mmmm mmmm mmmm
MSW: 0001 ffee ddaa addr

Description Perform an MADDF32 and a MMOV32 operation in parallel. Add MRf to the contents
of MRe and store the result in MRd. In parallel move the contents of the 32-bit location
mem32 to MRa.

MRd = MRe + MRf;

MRa = [mem32];

Restrictions The destination register for the MADDF32 and the MMOV32 must be unique. That is,
MRa and MRd cannot be the same register.

Flags This instruction modifies the following flags in the MSTF register:
Flag TF ZF NF LUF LVF
Modified No Yes Yes Yes Yes

The MSTF register flags are modified as follows:

• LUF = 1 if MADDF32 generates an underflow condition.
• LVF = 1 if MADDF32 generates an overflow condition.
The MMOV32 Instruction sets the NF and ZF flags as follows:

NF = MRa(31);
ZF = 0;
if(MRa(30:23) == 0) { ZF = 1; NF = 0; };

Pipeline The MADDF32 and the MMOV32 both complete in a single cycle.

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MADDF32 MRd, MRe, MRf ||MMOV32 MRa, mem32 (continued)

32-Bit Floating-Point Addition with Parallel Move

Example 1
; Given A, B, and C are 32-bit floating-point numbers
; Calculate Y1 = A + 4B
; Y2 = A + C
;
_Cla1Task1:
MMOV32 MR0, @A ; Load MR0 with A
MMOV32 MR1, @B ; Load MR1 with B
MMPYF32 MR1, MR1, #4.0 ; Multiply 4 * B
|| MMOV32 MR2, @C and in parallel load C
MADDF32 MR3, MR0, MR1 ; Add A + 4B
MADDF32 MR3, MR0, MR2 ; Add A + C
|| MMOV32 @Y1, MR3 ; and in parallel store A+4B
MMOV32 @Y2, MR3 ; store A + C MSTOP
; end of task

Example 2
; Given A, B, and C are 32-bit floating-point numbers
; Calculate Y3 = (A + B)
; Y4 = (A + B) * C
;
_Cla1Task2:
MMOV32 MR0, @A ; Load MR0 with A
MMOV32 MR1, @B ; Load MR1 with B
MADDF32 MR1, MR1, MR0 ; Add A+B
|| MMOV32 MR0, @C ; and in parallel load MR0 with C
MMPYF32 MR1, MR1, MR0 ; Multiply (A+B) by C
|| MMOV32 @Y3, MR1 ; and in parallel store A+B
MMOV32 @Y4, MR1 ; Store the (A+B) * C
MSTOP ; end of task

See also MADDF32 MRa, #16FHi, MRb

MADDF32 MRa, MRb, #16FHi
MADDF32 MRa, MRb, MRc
MADDF32 MRd, MRe, MRf || MMOV32 mem32, MRa
MMPYF32 MRa, MRb, MRc || MADDF32 MRd, MRe, MRf

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MAND32 MRa, MRb, MRc

Bitwise AND

Operands MRa CLA floating-point destination register (MR0 to MR3)

MRb CLA floating-point source register (MR0 to MR3)
MRc CLA floating-point source register (MR0 to MR3)

Opcode
LSW: 0000 0000 00cc bbaa
MSW: 0111 1100 0110 0000

Description Bitwise AND of MRb with MRc.

MRa(31:0) = MRb(31:0) AND MRc(31:0);

Flags This instruction modifies the following flags in the MSTF register:
Flag TF ZF NF LUF LVF
Modified No Yes Yes No No

The MSTF register flags are modified based on the integer results of the operation.

NF = MRa(31);
ZF = 0;
if(MRa(31:0) == 0) { ZF = 1; }

Pipeline This is a single-cycle instruction.

Example
MMOVIZ MR0, #0x5555 ; MR0 = 0x5555AAAA
MMOVXI MR0, #0xAAAA
MMOVIZ MR1, #0x5432 ; MR1 = 0x5432FEDC
MMOVXI MR1, #0xFEDC
; 0101 AND 0101 = 0101 (5)
; 0101 AND 0100 = 0100 (4)
; 0101 AND 0011 = 0001 (1)
; 0101 AND 0010 = 0000 (0)
; 1010 AND 1111 = 1010 (A)
; 1010 AND 1110 = 1010 (A)
; 1010 AND 1101 = 1000 (8)
; 1010 AND 1100 = 1000 (8)
MAND32 MR2, MR1, MR0 ; MR3 = 0x5410AA88

See also MADD32 MRa, MRb, MRc

MASR32 MRa, #SHIFT
MLSL32 MRa, #SHIFT
MLSR32 MRa, #SHIFT
MOR32 MRa, MRb, MRc
MXOR32 MRa, MRb, MRc
MSUB32 MRa, MRb, MRc

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MASR32 MRa, #SHIFT

Arithmetic Shift Right

Operands MRa CLA floating-point source/destination register (MR0 to MR3)

#SHIFT Number of bits to shift (1 to 32)

Opcode
LSW: 0000 0000 0shi ftaa
MSW: 0111 1011 0100 0000

Description Arithmetic shift right of MRa by the number of bits indicated. The number of bits can be 1
to 32.

MARa(31:0) = Arithmetic Shift(MARa(31:0) by #SHIFT bits);

Flags This instruction modifies the following flags in the MSTF register:
Flag TF ZF NF LUF LVF
Modified No Yes Yes No No

The MSTF register flags are modified based on the integer results of the operation.

NF = MRa(31);
ZF = 0;
if(MRa(31:0) == 0) { ZF = 1; }

Pipeline This is a single-cycle instruction.

Example
; Given m2 = (int32)32
; x2 = (int32)64
; b2 = (int32)-128
;
; Calculate
; m2 = m2/2
; x2 = x2/4
; b2 = b2/8
;
_Cla1Task2:
MMOV32 MR0, @_m2 ; MR0 = 32 (0x00000020)
MMOV32 MR1, @_x2 ; MR1 = 64 (0x00000040)
MMOV32 MR2, @_b2 ; MR2 = -128 (0xFFFFFF80)
MASR32 MR0, #1 ; MR0 = 16 (0x00000010)
MASR32 MR1, #2 ; MR1 = 16 (0x00000010)
MASR32 MR2, #3 ; MR2 = -16 (0xFFFFFFF0)
MMOV32 @_m2, MR0 ; store results
MMOV32 @_x2, MR1
MMOV32 @_b2, MR2
MSTOP ; end of task

See also MADD32 MRa, MRb, MRc

MAND32 MRa, MRb, MRc
MLSL32 MRa, #SHIFT
MLSR32 MRa, #SHIFT
MOR32 MRa, MRb, MRc
MXOR32 MRa, MRb, MRc
MSUB32 MRa, MRb, MRc

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MBCNDD 16BitDest {, CNDF}

Branch Conditional Delayed

Operands 16BitDest 16-bit destination if condition is true

CNDF Optional condition tested

Opcode
LSW: dest dest dest dest
MSW: 0111 1001 1000 cndf

Description If the specified condition is true, then branch by adding the signed 16BitDest value to the
MPC value. Otherwise, continue without branching. If the address overflows, the address
wraps around. Therefore, a value of "0xFFFE" puts the MPC back to the MBCNDD
instruction.
Refer to the Pipeline section for important information regarding this instruction.

if (CNDF == TRUE) MPC += 16BitDest;

CNDF is one of the following conditions:

Encode(1) CNDF Description MSTF Flags Tested
0000 NEQ Not equal to zero ZF == 0
0001 EQ Equal to zero ZF == 1
0010 GT Greater than zero ZF == 0 AND NF == 0
0011 GEQ Greater than or equal NF == 0
to zero
0100 LT Less than zero NF == 1
0101 LEQ Less than or equal to ZF == 1 OR NF == 1
zero
1010 TF Test flag set TF == 1
1011 NTF Test flag not set TF == 0
1100 LU Latched underflow LUF == 1
1101 LV Latched overflow LVF == 1
1110 UNC Unconditional None
1111 UNCF(2) Unconditional with flag None
modification

(1) Values not shown are reserved.

(2) This is the default operation, if no CNDF field is specified. This condition
allows the ZF and NF flags to be modified when a conditional operation is
executed. All other conditions do not modify these flags.

Restrictions The MBCNDD instruction is not allowed three instructions before or after a MBCNDD,
MCCNDD, or MRCNDD instruction. Refer to the Pipeline section for more information.

Flags This instruction does not modify flags in the MSTF register.
Flag TF ZF NF LUF LVF
Modified No No No No No

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MBCNDD 16BitDest {, CNDF} (continued)

Branch Conditional Delayed

Pipeline The MBCNDD instruction alone is a single-cycle instruction. As shown in Table 8-12, 6
instruction slots are executed for each branch; 3 slots before the branch instruction (I2-I4)
and 3 slots after the branch instruction (I5-I7). The total number of cycles for a branch
taken or not taken depends on the usage of these slots. That is, the number of cycles
depends on how many slots are filled with a MNOP as well as which slots are filled. The
effective number of cycles for a branch can, therefore, range from 1 to 7 cycles. The
number of cycles for a branch taken cannot be the same as for a branch not taken.
Referring to Table 8-12 and Table 8-13, the instructions before and after MBCNDD have
the following properties:
• I1
– I1 is the last instruction that can effect the CNDF flags for the MBCNDD instruction.
The CNDF flags are tested in the D2 phase of the pipeline. That is, a decision is
made whether to branch or not when MBCNDD is in the D2 phase.
– There are no restrictions on the type of instruction for I1.
• I2, I3, and I4
– The three instructions proceeding MBCNDD can change MSTF flags but have no
effect on whether the MBCNDD instruction branches or not. This is because the
flag modification occurs after the D2 phase of the MBCNDD instruction.
– These instructions must not be the following: MSTOP, MDEBUGSTOP, MBCNDD,
MCCNDD, or MRCNDD.
• I5, I6, and I7
– The three instructions following MBCNDD are always executed irrespective of
whether the branch is taken or not.
– These instructions must not be the following: MSTOP, MDEBUGSTOP, MBCNDD,
MCCNDD, or MRCNDD.

<Instruction 1> ; I1 Last instruction that can affect flags for

; the MBCNDD operation
<Instruction 2> ; I2 Cannot be stop, branch, call or return
<Instruction 3> ; I3 Cannot be stop, branch, call or return
<Instruction 4> ; I4 Cannot be stop, branch, call or return
MBCNDD _Skip, NEQ ; Branch to Skip if not eqal to zero
; Three instructions after MBCNDD are always
; executed whether the branch is taken or not
<Instruction 5> ; I5 Cannot be stop, branch, call or return
<Instruction 6> ; I6 Cannot be stop, branch, call or return
<Instruction 7> ; I7 Cannot be stop, branch, call or return
<Instruction 8> ; I8
<Instruction 9> ; I9
....
_Skip:
<Destination 1> ; d1 Can be any instruction
<Destination 2> ; d2
<Destination 3> ; d3
....
....
MSTOP
....

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MBCNDD 16BitDest {, CNDF} (continued)

Branch Conditional Delayed

Table 8-12. Pipeline Activity for MBCNDD, Branch Not Taken

Instruction F1 F2 D1 D2 R1 R2 E W
I1 I1
I2 I2 I1
I3 I3 I2 I1
I4 I4 I3 I2 I1
MBCNDD MBCNDD I4 I3 I2 I1
I5 I5 MBCNDD I4 I3 I2 I1
I6 I6 I5 MBCNDD I4 I3 I2 I1
I7 I7 I6 I5 MBCNDD I4 I3 I2
I8 I8 I7 I6 I5 - I4 I3
I9 I9 I8 I7 I6 I5 - I4
I10 I10 I9 I8 I7 I6 I5 -
I10 I9 I8 I7 I6 I5
I10 I9 I8 I7 I6
I10 I9 I8 I7
I10 I9 I8
I10 I9
I10

Table 8-13. Pipeline Activity for MBCNDD, Branch Taken

Instruction F1 F2 D1 D2 R1 R2 E W
I1 I1
I2 I2 I1
I3 I3 I2 I1
I4 I4 I3 I2 I1
MBCNDD MBCNDD I4 I3 I2 I1
I5 I5 MBCNDD I4 I3 I2 I1
I6 I6 I5 MBCNDD I4 I3 I2 I1
I7 I7 I6 I5 MBCNDD I4 I3 I2
d1 d1 I7 I6 I5 - I4 I3
d2 d2 d1 I7 I6 I5 - I4
d3 d3 d2 d1 I7 I6 I5 -
d3 d2 d1 I7 I6 I5
d3 d2 d1 I7 I6
d3 d2 d1 I7
d3 d2 d1
d3 d2
d3

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MBCNDD 16BitDest {, CNDF} (continued)

Branch Conditional Delayed

Example 1
; if (State == 0.1)
; RampState = RampState || RAMPMASK
; else if (State == 0.01)
; CoastState = CoastState || COASTMASK
; else
; SteadyState = SteadyState || STEADYMASK
;
_Cla1Task1:
MMOV32 MR0, @State
MCMPF32 MR0, #0.1 ; Affects flags for 1st MBCNDD (A)
MNOP
MNOP
MNOP
MBCNDD Skip1, NEQ ; (A) If State != 0.1, go to Skip1
MNOP ; Always executed
MNOP ; Always executed
MNOP ; Always executed
MMOV32 MR1, @RampState ; Execute if (A) branch not taken
MMOVXI MR2, #RAMPMASK ; Execute if (A) branch not taken
MOR32 MR1, MR2 ; Execute if (A) branch not taken
MMOV32 @RampState, MR1 ; Execute if (A) branch not taken
MSTOP ; end of task if (A) branch not taken
Skip1:
MCMPF32 MR0,#0.01 ; Affects flags for 2nd MBCNDD (B)
MNOP
MNOP
MNOP
MBCNDD Skip2,NEQ ; (B) If State != 0.01, go to Skip2
MNOP ; Always executed
MNOP ; Always executed
MNOP ; Always executed
MMOV32 MR1, @CoastState ; Execute if (B) branch not taken
MMOVXI MR2, #COASTMASK ; Execute if (B) branch not taken
MOR32 MR1, MR2 ; Execute if (B) branch not taken
MMOV32 @CoastState, MR1 ; Execute if (B) branch not taken
MSTOP
Skip2:
MMOV32 MR3, @SteadyState ; Executed if (B) branch taken
MMOVXI MR2, #STEADYMASK ; Executed if (B) branch taken
MOR32 MR3, MR2 ; Executed if (B) branch taken
MMOV32 @SteadyState, MR3 ; Executed if (B) branch taken
MSTOP

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MBCNDD 16BitDest {, CNDF} (continued)

Branch Conditional Delayed

Example 2
; This example is the same as Example 1, except
; the code is optimized to take advantage of delay slots
;
; if (State == 0.1)
; RampState = RampState || RAMPMASK
; else if (State == 0.01)
; CoastState = CoastState || COASTMASK
; else
; SteadyState = SteadyState || STEADYMASK
;
_Cla1Task2:
MMOV32 MR0, @State
MCMPF32 MR0, #0.1 ; Affects flags for 1st MBCNDD (A)
MCMPF32 MR0, #0.01 ; Check used by 2nd MBCNDD (B)
MTESTTF EQ ; Store EQ flag in TF for 2nd MBCNDD (B)
MNOP
MBCNDD Skip1, NEQ ; (A) If State != 0.1, go to Skip1
MMOV32 MR1, @RampState ; Always executed
MMOVXI MR2, #RAMPMASK ; Always executed
MOR32 MR1, MR2 ; Always executed
MMOV32 @RampState, MR1 ; Execute if (A) branch not taken
MSTOP ; end of task if (A) branch not taken
Skip1:
MMOV32 MR3, @SteadyState
MMOVXI MR2, #STEADYMASK
MOR32 MR3, MR2
MBCNDD Skip2, NTF ; (B) if State != .01, go to Skip2
MMOV32 MR1, @CoastState ; Always executed
MMOVXI MR2, #COASTMASK ; Always executed
MOR32 MR1, MR2 ; Always executed
MMOV32 @CoastState, MR1 ; Execute if (B) branch not taken
MSTOP ; end of task if (B) branch not taken
Skip2:
MMOV32 @SteadyState, MR3 ; Executed if (B) branch taken
MSTOP

See also MCCNDD 16BitDest, CNDF

MRCNDD CNDF

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MCCNDD 16BitDest {, CNDF}

Call Conditional Delayed

Operands 16BitDest 16-bit destination if condition is true

CNDF Optional condition to be tested

Opcode
LSW: dest dest dest dest
MSW: 0111 1001 1001 cndf

Description If the specified condition is true, then store the return address in the RPC field of MSTF
and make the call by adding the signed 16BitDest value to the MPC value. Otherwise,
continue code execution without making the call. If the address overflows, the address
wraps around. Therefore a value of "0xFFFE" puts the MPC back to the MCCNDD
instruction.
Refer to the Pipeline section for important information regarding this instruction.

if (CNDF == TRUE)
{
RPC = return address;
MPC += 16BitDest;
};

CNDF is one of the following conditions:

Encode(1) CNDF Description MSTF Flags Tested
0000 NEQ Not equal to zero ZF == 0
0001 EQ Equal to zero ZF == 1
0010 GT Greater than zero ZF == 0 AND NF == 0
0011 GEQ Greater than or equal NF == 0
to zero
0100 LT Less than zero NF == 1
0101 LEQ Less than or equal to ZF == 1 OR NF == 1
zero
1010 TF Test flag set TF == 1
1011 NTF Test flag not set TF == 0
1100 LU Latched underflow LUF == 1
1101 LV Latched overflow LVF == 1
1110 UNC Unconditional None
1111 UNCF(2) Unconditional with flag None
modification

(1) Values not shown are reserved.

(2) This is the default operation if no CNDF field is specified. This condition allows
the ZF and NF flags to be modified when a conditional operation is executed.
All other conditions do not modify these flags.

Restrictions The MCCNDD instruction is not allowed three instructions before or after a MBCNDD,
MCCNDD, or MRCNDD instruction. Refer to the Pipeline section for more details.

Flags This instruction does not modify flags in the MSTF register.
Flag TF ZF NF LUF LVF
Modified No No No No No

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MCCNDD 16BitDest {, CNDF} (continued)

Call Conditional Delayed

Pipeline The MCCNDD instruction alone is a single-cycle instruction. As shown in Table 8-14, 6
instruction slots are executed for each call; 3 before the call instruction (I2-I4) and 3 after
the call instruction (I5-I7). The total number of cycles for a call taken or not taken depends
on the usage of these slots. That is, the number of cycles depends on how many slots are
filled with a MNOP as well as which slots are filled. The effective number of cycles for a
call can, therefore, range from 1 to 7 cycles. The number of cycles for a call taken cannot
be the same as for a call not taken.
Referring to the following code fragment and the pipeline diagrams in Table 8-14 and
Table 8-15, the instructions before and after MCCNDD have the following properties:
• I1
– I1 is the last instruction that can effect the CNDF flags for the MCCNDD instruction.
The CNDF flags are tested in the D2 phase of the pipeline. That is, a decision is
made whether to branch or not when MCCNDD is in the D2 phase.
– There are no restrictions on the type of instruction for I1.
• I2, I3, and I4
– The three instructions proceeding MCCNDD can change MSTF flags but have no
effect on whether the MCCNDD instruction makes the call or not. This is because
the flag modification occurs after the D2 phase of the MCCNDD instruction.
– These instructions must not be the following: MSTOP, MDEBUGSTOP, MBCNDD,
MCCNDD, or MRCNDD.
• I5, I6, and I7
– The three instructions following MBCNDD are always executed irrespective of
whether the branch is taken or not.
– These instructions must not be the following: MSTOP, MDEBUGSTOP, MBCNDD,
MCCNDD, or MRCNDD.

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MCCNDD 16BitDest {, CNDF} (continued)

Call Conditional Delayed

<Instruction 1> ; I1 Last instruction that can affect flags for

; the MCCNDD operation
<Instruction 2> ; I2 Cannot be stop, branch, call or return
<Instruction 3> ; I3 Cannot be stop, branch, call or return
<Instruction 4> ; I4 Cannot be stop, branch, call or return
MCCNDD _func, NEQ ; Call to func if not eqal to zero
; Three instructions after MCCNDD are always
; executed whether the call is taken or not
<Instruction 5> ; I5 Cannot be stop, branch, call or return
<Instruction 6> ; I6 Cannot be stop, branch, call or return
<Instruction 7> ; I7 Cannot be stop, branch, call or return
<Instruction 8> ; I8 The address of this instruction is saved
; in the RPC field of the MSTF register.
; Upon return this value is loaded into MPC
; and fetching continues from this point.
<Instruction 9> ; I9
....
_func:
<Destination 1> ; d1 Can be any instruction
<Destination 2> ; d2
<Destination 3> ; d3
<Destination 4> ; d4 Last instruction that can affect flags for
; the MRCNDD operation
<Destination 5> ; d5 Cannot be stop, branch, call or return
<Destination 6> ; d6 Cannot be stop, branch, call or return
<Destination 7> ; d7 Cannot be stop, branch, call or return
MRCNDD UNC ; Return to <Instruction 8>, unconditional
; Three instructions after MRCNDD are always
; executed whether the return is taken or not
<Destination 8> ; d8 Cannot be stop, branch, call or return
<Destination 9> ; d9 Cannot be stop, branch, call or return
<Destination 10> ; d10 Cannot be stop, branch, call or return
<Destination 11> ; d11
....
MSTOP

Table 8-14. Pipeline Activity for MCCNDD, Call Not Taken

Instruction F1 F2 D1 D2 R1 R2 E W
I1 I1
I2 I2 I1
I3 I3 I2 I1
I4 I4 I3 I2 I1
MCCNDD MCCNDD I4 I3 I2 I1
I5 I5 MCCNDD I4 I3 I2 I1
I6 I6 I5 MCCNDD I4 I3 I2 I1
I7 I7 I6 I5 MCCNDD I4 I3 I2
I8 I8 I7 I6 I5 - I4 I3
I9 I9 I8 I7 I6 I5 - I4
I10 I10 I9 I8 I7 I6 I5 -
etc .... I10 I9 I8 I7 I6 I5
.... I10 I9 I8 I7 I6
.... I10 I9 I8 I7
.... I10 I9 I8
I10 I9
I10

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MCCNDD 16BitDest {, CNDF} (continued)

Call Conditional Delayed

Table 8-15. Pipeline Activity for MCCNDD, Call Taken

Instruction F1 F2 D1 D2 R1 R2 E W
I1 I1
I2 I2 I1
I3 I3 I2 I1
I4 I4 I3 I2 I1
MCCNDD MCCNDD I4 I3 I2 I1
I5 I5 MCCNDD I4 I3 I2 I1
I6 I6 I5 MCCNDD I4 I3 I2 I1
I7 (1) I7 I6 I5 MCCNDD I4 I3 I2
d1 d1 I7 I6 I5 - I4 I3
d2 d2 d1 I7 I6 I5 - I4
d3 d3 d2 d1 I7 I6 I5 -
etc .... d3 d2 d1 I7 I6 I5
.... d3 d2 d1 I7 I6
.... d3 d2 d1 I7
.... d3 d2 d1
d3 d2
d3

(1) The RPC value in the MSTF register points to the instruction following I7 (instruction I8).

See also MBCNDD #16BitDest, CNDF

MMOV32 mem32, MSTF
MMOV32 MSTF, mem32
MRCNDD CNDF

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MCLRC BGINTM

Clear Background Task Interrupt Mask

Operands None This instruction does not have any operands

Opcode
LSW: 0000 0000 0000 0000
MSW: 0111 1111 0111 0000

Description This instruction clears the background task interrupt mask (BGINTM) bit in the
MSTSBGRND register, allowing any code thereafter to be interrupted by a higher priority
task. This instruction clears the BGINTM bit at the end of the D2 phase.

Note
This instruction does not require the MEALLOW bit to be asserted before or
deasserted after clearing BGINTM.

Flags This instruction does not modify flags in the MSTF register:
Flag TF ZF NF LUF LVF
Modified No No No No No

Pipeline This is a single-cycle instruction.

Example
MCLRC BGINTM ; Allow the background task to be
; interrupted by clearing the
; MSTSBGRND.BGINTM bit

See also MSETC BGINTM

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MCMP32 MRa, MRb

32-Bit Integer Compare for Equal, Less Than or Greater Than

Operands MRa CLA floating-point source register (MR0 to MR3)

MRb CLA floating-point source register (MR0 to MR3)

Opcode
LSW: 0000 0000 0000 bbaa
MSW: 0111 1111 0010 0000

Description Set ZF and NF flags on the result of MRa - MRb where MRa and MRb are 32-bit integers.
For a floating-point compare, refer to MCMPF32.

Note
A known hardware issue exists in the MCMP32 instruction. Signed-integer
comparisons using MCMP32 alone set the status bits in a way that is not useful
for comparison when the difference between the two operands is too large,
such as when the inputs have opposite sign and are near the extreme 32-bit
signed values. This affects both signed and unsigned integer comparisons.
The compiler (version 18.1.5.LTS or higher) has implemented a workaround for
this issue. The compiler checks the upper bits of the operands by performing
a floating point comparison before proceeding to do the integer comparison or
subtraction.
The compiler flag --cla_signed_compare_workaround enables this workaround.

Flags This instruction modifies the following flags in the MSTF register:
Flag TF ZF NF LUF LVF
Modified No Yes Yes No No

The MSTF register flags are modified based on the integer results of the operation.

If(MRa == MRb) {ZF=1; NF=0;}

If(MRa > MRb) {ZF=0; NF=0;}
If(MRa < MRb) {ZF=0; NF=1;}

Pipeline This is a single-cycle instruction.

Example
; Behavior of ZF and NF flags for different comparisons
;
; Given A = (int32)1
; B = (int32)2
; C = (int32)-7
;
MMOV32 MR0, @_A ; MR0 = 1 (0x00000001)
MMOV32 MR1, @_B ; MR1 = 2 (0x00000002)
MMOV32 MR2, @_C ; MR2 = -7 (0xFFFFFFF9)
MCMP32 MR2, MR2 ; NF = 0, ZF = 1
MCMP32 MR0, MR1 ; NF = 1, ZF = 0
MCMP32 MR1, MR0 ; NF = 0, ZF = 0

See also MADD32 MRa, MRb, MRc

MSUB32 MRa, MRb, MRc

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MCMPF32 MRa, MRb

32-Bit Floating-Point Compare for Equal, Less Than or Greater Than

Operands MRa CLA floating-point source register (MR0 to MR3)

MRb CLA floating-point source register (MR0 to MR3)

Opcode
LSW: 0000 0000 0000 bbaa
MSW: 0111 1101 0000 0000

Description Set ZF and NF flags on the result of MRa - MRb. The MCMPF32 instruction is performed
as a logical compare operation. This is possible because of the IEEE format offsetting the
exponent. Basically the bigger the binary number, the bigger the floating-point value.
Special cases for inputs:
• Negative zero is treated as positive zero.
• A denormalized value is treated as positive zero.
• Not-a-Number (NaN) is treated as infinity.

Flags This instruction modifies the following flags in the MSTF register:
Flag TF ZF NF LUF LVF
Modified No Yes Yes No No

The MSTF register flags are modified as follows:

If(MRa == MRb) {ZF=1; NF=0;}

If(MRa > MRb) {ZF=0; NF=0;}
If(MRa < MRb) {ZF=0; NF=1;}

Pipeline This is a single-cycle instruction.

Example
; Behavior of ZF and NF flags for different comparisons
MMOVIZ MR1, #-2.0 ; MR1 = -2.0 (0xC0000000)
MMOVIZ MR0, #5.0 ; MR0 = 5.0 (0x40A00000)
MCMPF32 MR1, MR0 ; ZF = 0, NF = 1
MCMPF32 MR0, MR1 ; ZF = 0, NF = 0
MCMPF32 MR0, MR0 ; ZF = 1, NF = 0

See also MCMPF32 MRa, #16FHi

MMAXF32 MRa, #16FHi
MMAXF32 MRa, MRb
MMINF32 MRa, #16FHi
MMINF32 MRa, MRb

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MCMPF32 MRa, #16FHi

32-Bit Floating-Point Compare for Equal, Less Than or Greater Than

Operands MRa CLA floating-point source register (MR0 to MR3)

#16FHi A 16-bit immediate value that represents the upper 16-bits of an
IEEE 32-bit floating-point value. The low 16-bits of the mantissa
are assumed to be all 0.

Opcode
LSW: IIII IIII IIII IIII
MSW: 0111 1000 1100 00aa

Description Compare the value in MRa with the floating-point value represented by the immediate
operand. Set the ZF and NF flags on (MRa - #16FHi:0).
#16FHi is a 16-bit immediate value that represents the upper 16-bits of an IEEE 32-bit
floating-point value. The low 16-bits of the mantissa are assumed to be all 0. This
addressing mode is most useful for constants where the lowest 16-bits of the mantissa
are 0. Some examples are 2.0 (0x40000000), 4.0 (0x40800000), 0.5 (0x3F000000), and
-1.5 (0xBFC00000). The assembler accepts either a hex or float as the immediate value.
That is, -1.5 can be represented as #-1.5 or #0xBFC0.
The MCMPF32 instruction is performed as a logical compare operation. This is possible
because of the IEEE floating-point format offsets the exponent. Basically the bigger the
binary number, the bigger the floating-point value.
Special cases for inputs:
• Negative zero is treated as positive zero.
• Denormalized value is treated as positive zero.
• Not-a-Number (NaN) is treated as infinity.

Flags This instruction modifies the following flags in the MSTF register:
Flag TF ZF NF LUF LVF
Modified No Yes Yes No No

The MSTF register flags are modified as follows:

If(MRa == #16FHi:0) {ZF=1, NF=0;}

If(MRa > #16FHi:0) {ZF=0, NF=0;}
If(MRa < #16FHi:0) {ZF=0, NF=1;}

Pipeline This is a single-cycle instruction

Example 1
; Behavior of ZF and NF flags for different comparisons
MMOVIZ MR1, #-2.0 ; MR1 = -2.0 (0xC0000000)
MMOVIZ MR0, #5.0 ; MR0 = 5.0 (0x40A00000)
MCMPF32 MR1, #-2.2 ; ZF = 0, NF = 0
MCMPF32 MR0, #6.5 ; ZF = 0, NF = 1
MCMPF32 MR0, #5.0 ; ZF = 1, NF = 0

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MCMPF32 MRa, #16FHi (continued)

32-Bit Floating-Point Compare for Equal, Less Than or Greater Than

Example 2
; X is an array of 32-bit floating-point values
; and has length elements. Find the maximum value in
; the array and store the value in Result
;
; Note: MCMPF32 and MSWAPF can be replaced with MMAXF32
;
_Cla1Task1:
MMOVI16 MAR1,#_X ; Start address
MUI16TOF32 MR0, @_len ; Length of the array
MNOP ; delay for MAR1 load
MNOP ; delay for MAR1 load
MMOV32 MR1, *MAR1[2]++ ; MR1 = X0
LOOP
MMOV32 MR2, *MAR1[2]++ ; MR2 = next element
MCMPF32 MR2, MR1 ; Compare MR2 with MR1
MSWAPF MR1, MR2, GT ; MR1 = MAX(MR1, MR2)
MADDF32 MR0, MR0, #-1.0 ; Decrememt the counter
MCMPF32 MR0 #0.0 ; Set/clear flags for MBCNDD
MNOP
MNOP
MNOP
MBCNDD LOOP, NEQ ; Branch if not equal to zero
MMOV32 @_Result, MR1 ; Always executed
MNOP ; Always executed
MNOP ; Always executed
MSTOP ; End of task

See also MCMPF32 MRa, MRb

MMAXF32 MRa, #16FHi
MMAXF32 MRa, MRb
MMINF32 MRa, #16FHi
MMINF32 MRa, MRb

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MDEBUGSTOP

Debug Stop Task

Operands none This instruction does not have any operands

Opcode
LSW: 0000 0000 0000 0000
MSW: 0111 1111 0110 0000

Description When CLA breakpoints are enabled, the MDEBUGSTOP instruction is used to halt a task
so that the task can be debugged. That is, MDEBUGSTOP is the CLA breakpoint. If CLA
breakpoints are not enabled, the MDEBUGSTOP instruction behaves like a MNOP. Unlike
the MSTOP, the MIRUN flag is not cleared and an interrupt is not issued. A single-step or
run operation continues execution of the task.

Restrictions The MDEBUGSTOP instruction cannot be placed 3 instructions before or after a

MBCNDD, MCCNDD, or MRCNDD instruction.

Flags This instruction does not modify flags in the MSTF register.
Flag TF ZF NF LUF LVF
Modified No No No No No

Pipeline This is a single-cycle instruction.

See also MSTOP , MDEBUGSTOP1

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MDEBUGSTOP1

Software Breakpoint

Operands none This instruction does not have any operands

Opcode
LSW: 0000 0000 0000 0000
MSW: 0111 1111 0011 0000

Description The instruction at which a software breakpoint is placed is replaced by the

MDEBUGSTOP1 instruction. The instruction halts execution once the instruction reaches
the D2 phase in the pipeline; at that point, the subsequent instructions that were fetched,
after the halt, are flushed from the pipeline. The replace instruction is re-fetched after this
and execution continues normally (either in run or step mode).
See Section 8.4.3 for a detailed explanation of the operation.

Restrictions The MDEBUGSTOP1 instruction cannot be placed 3 instructions before or after a

MBCNDD, MCCNDD, or MRCNDD instruction.

Flags This instruction does not modify flags in the MSTF register.
Flag TF ZF NF LUF LVF
Modified No No No No No

Pipeline This is a single-cycle instruction.

See also MSTOP, MDEBUGSTOP

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MEALLOW

Enable CLA Write Access to EALLOW Protected Registers

Operands none This instruction does not have any operands

Opcode
LSW: 0000 0000 0000 0000
MSW: 0111 1111 1001 0000

Description This instruction sets the MEALLOW bit in the CLA status register MSTF. When this bit
is set, the CLA is allowed write access to EALLOW protected registers. To again protect
against CLA writes to protected registers, use the MEDIS instruction.
MEALLOW and MEDIS only control CLA write access; reads are allowed even if
MEALLOW has not been executed. MEALLOW and MEDIS are also independent from
the main CPU's EALLOW/EDIS. This instruction does not modify the EALLOW bit in the
main CPU's status register. The MEALLOW bit in MSTF only controls access for the CLA
while the EALLOW bit in the ST1 register only controls access for the main CPU.
As with EALLOW, the MEALLOW bit is overridden using the JTAG port, allowing full
control of register accesses during debug from Code Composer Studio.

Flags This instruction does not modify flags in the MSTF register.
Flag TF ZF NF LUF LVF
Modified No No No No No

Pipeline This is a single-cycle instruction.

Example
; C header file including definition of
; the EPwm1Regs structure
;
; The ePWM TZSEL register is EALLOW protected
;
.cdecls C,LIST,"CLAShared.h"
...
_Cla1Task1:
...
MEALLOW ; Allow CLA write access
MMOV16 @_EPwm1Regs.TZSEL.all, MR3 ; Write to TZSEL
MEDIS ; Disallow CLA write access
...
...
MSTOP

See also MEDIS

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MEDIS

Disable CLA Write Access to EALLOW Protected Registers

Operands none This instruction does not have any operands

Opcode
LSW: 0000 0000 0000 0000
MSW: 0111 1111 1011 0000

Description This instruction clears the MEALLOW bit in the CLA status register MSTF. When this bit is
clear, the CLA is not allowed write access to EALLOW-protected registers. To enable CLA
writes to protected registers, use the MEALLOW instruction.
MEALLOW and MEDIS only control CLA write access; reads are allowed even if
MEALLOW has not been executed. MEALLOW and MEDIS are also independent from
the main CPU's EALLOW/EDIS. This instruction does not modify the EALLOW bit in the
main CPU's status register. The MEALLOW bit in MSTF only controls access for the CLA
while the EALLOW bit in the ST1 register only controls access for the main CPU.
As with EALLOW, the MEALLOW bit is overridden using the JTAG port, allowing full
control of register accesses during debug from the Code Composer Studio™ IDE.

Flags This instruction does not modify flags in the MSTF register.
Flag TF ZF NF LUF LVF
Modified No No No No No

Pipeline This is a single-cycle instruction.

Example
; C header file including definition of
; the EPwm1Regs structure
;
; The ePWM TZSEL register is EALLOW protected
;
.cdecls C,LIST,"CLAShared.h"
...
_Cla1Task1:
...
MEALLOW ; Allow CLA write access
MMOV16 @_EPwm1Regs.TZSEL.all, MR3 ; Write to TZSEL
MEDIS ; Disallow CLA write access
...
...
MSTOP

See also MEALLOW

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MEINVF32 MRa, MRb

32-Bit Floating-Point Reciprocal Approximation

Operands MRa CLA floating-point destination register (MR0 to MR3)

MRb CLA floating-point source register (MR0 to MR3)

Opcode
LSW: 0000 0000 0000 bbaa
MSW: 0111 1111 0000 0000

Description This operation generates an estimate of 1/X in 32-bit floating-point format accurate to
approximately 8 bits. This value can be used in a Newton-Raphson algorithm to get a
more accurate answer. That is:

Ye = Estimate(1/X);
Ye = Ye*(2.0 - Ye*X);
Ye = Ye*(2.0 - Ye*X);

After two iterations of the Newton-Raphson algorithm, you get an exact answer
accurate to the 32-bit floating-point format. On each iteration, the mantissa bit accuracy
approximately doubles. The MEINVF32 operation does not generate a negative zero,
DeNorm, or NaN value.

MRa = Estimate of 1/MRb;

Flags This instruction modifies the following flags in the MSTF register:
Flag TF ZF NF LUF LVF
Modified No No No Yes Yes

The MSTF register flags are modified as follows:

• LUF = 1 if MEINVF32 generates an underflow condition.
• LVF = 1 if MEINVF32 generates an overflow condition.
Pipeline This is a single-cycle instruction.

Example
; Calculate Num/Den using a Newton-Raphson algorithum for 1/Den
; Ye = Estimate(1/X)
; Ye = Ye*(2.0 - Ye*X)
; Ye = Ye*(2.0 - Ye*X)
;
_Cla1Task1:
MMOV32 MR1, @_Den ; MR1 = Den
MEINVF32 MR2, MR1 ; MR2 = Ye = Estimate(1/Den)
MMPYF32 MR3, MR2, MR1 ; MR3 = Ye*Den
MSUBF32 MR3, #2.0, MR3 ; MR3 = 2.0 - Ye*Den
MMPYF32 MR2, MR2, MR3 ; MR2 = Ye = Ye*(2.0 - Ye*Den)
MMPYF32 MR3, MR2, MR1 ; MR3 = Ye*Den
|| MMOV32 MR0, @_Num ; MR0 = Num
MSUBF32 MR3, #2.0, MR3 ; MR3 = 2.0 - Ye*Den
MMPYF32 MR2, MR2, MR3 ; MR2 = Ye = Ye*(2.0 - Ye*Den)
|| MMOV32 MR1, @_Den ; Reload Den To Set Sign
MNEGF32 MR0, MR0, EQ ; if(Den == 0.0) Change Sign Of Num
MMPYF32 MR0, MR2, MR0 ; MR0 = Y = Ye*Num
MMOV32 @_Dest, MR0 ; Store result
MSTOP ; end of task

See also MEISQRTF32 MRa, MRb

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MEISQRTF32 MRa, MRb

32-Bit Floating-Point Square-Root Reciprocal Approximation

Operands MRa CLA floating-point destination register (MR0 to MR3)

MRb CLA floating-point source register (MR0 to MR3)

Opcode
LSW: 0000 0000 0000 bbaa
MSW: 0111 1110 0100 0000

Description This operation generates an estimate of 1/sqrt(X) in 32-bit floating-point format accurate
to approximately 8 bits. This value can be used in a Newton-Raphson algorithm to get a
more accurate answer. That is:

Ye = Estimate(1/sqrt(X));
Ye = Ye*(1.5 - Ye*Ye*X/2.0);
Ye = Ye*(1.5 - Ye*Ye*X/2.0);

After 2 iterations of the Newton-Raphson algorithm, you get an exact answer accurate to
the 32-bit floating-point format. On each iteration, the mantissa bit accuracy approximately
doubles. The MEISQRTF32 operation does not generate a negative zero, DeNorm, or
NaN value.

MRa = Estimate of 1/sqrt (MRb);

Flags This instruction modifies the following flags in the MSTF register:
Flag TF ZF NF LUF LVF
Modified No No No Yes Yes

The MSTF register flags are modified as follows:

• LUF = 1 if MEISQRTF32 generates an underflow condition.
• LVF = 1 if MEISQRTF32 generates an overflow condition.
Pipeline This is a single-cycle instruction.

Example
; Y = sqrt(X)
; Ye = Estimate(1/sqrt(X));
; Ye = Ye*(1.5 - Ye*Ye*X*0.5)
; Ye = Ye*(1.5 - Ye*Ye*X*0.5)
; Y = X*Ye
;
_Cla1Task3:
MMOV32 MR0, @_x ; MR0 = X
MEISQRTF32 MR1, MR0 ; MR1 = Ye = Estimate(1/sqrt(X))
MMOV32 MR1, @_x, EQ ; if(X == 0.0) Ye = 0.0
MMPYF32 MR3, MR0, #0.5 ; MR3 = X*0.5
MMPYF32 MR2, MR1, MR3 ; MR2 = Ye*X*0.5
MMPYF32 MR2, MR1, MR2 ; MR2 = Ye*Ye*X*0.5
MSUBF32 MR2, #1.5, MR2 ; MR2 = 1.5 - Ye*Ye*X*0.5
MMPYF32 MR1, MR1, MR2 ; MR1 = Ye = Ye*(1.5 - Ye*Ye*X*0.5)
MMPYF32 MR2, MR1, MR3 ; MR2 = Ye*X*0.5
MMPYF32 MR2, MR1, MR2 ; MR2 = Ye*Ye*X*0.5
MSUBF32 MR2, #1.5, MR2 ; MR2 = 1.5 - Ye*Ye*X*0.5
MMPYF32 MR1, MR1, MR2 ; MR1 = Ye = Ye*(1.5 - Ye*Ye*X*0.5)
MMPYF32 MR0, MR1, MR0 ; MR0 = Y = Ye*X
MMOV32 @_y, MR0 ; Store Y = sqrt(X)
MSTOP ; end of task

1030 TMS320F2838x Real-Time Microcontrollers With Connectivity Manager SPRUII0E – MAY 2019 – REVISED SEPTEMBER 2023
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MEISQRTF32 MRa, MRb (continued)

32-Bit Floating-Point Square-Root Reciprocal Approximation

See also MEINVF32 MRa, MRb

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MF32TOI16 MRa, MRb

Convert 32-Bit Floating-Point Value to 16-Bit Integer

Operands MRa CLA floating-point destination register (MR0 to MR3)

MRb CLA floating-point source register (MR0 to MR3)

Opcode
LSW: 0000 0000 0000 bbaa
MSW: 0111 1101 1110 0000

Description Convert a 32-bit floating point value in MRb to a 16-bit integer and truncate. The result is
stored in MRa.

MRa(15:0) = F32TOI16(MRb);
MRa(31:16) = sign extension of MRa(15);

Flags This instruction does not affect any flags:

Flag TF ZF NF LUF LVF
Modified No No No No No

Pipeline This is a single-cycle instruction.

Example
MMOVIZ MR0, #5.0 ; MR0 = 5.0 (0x40A00000)
MF32TOI16 MR1, MR0 ; MR1(15:0) = MF32TOI16(MR0) = 0x0005
; MR1(31:16) = Sign extension of MR1(15) = 0x0000
MMOVIZ MR2, #-5.0 ; MR2 = -5.0 (0xC0A00000)
MF32TOI16 MR3, MR2 ; MR3(15:0) = MF32TOI16(MR2) = -5 (0xFFFB)
; MR3(31:16) = Sign extension of MR3(15) = 0xFFFF

See also MF32TOI16R MRa, MRb

MF32TOUI16 MRa, MRb
MF32TOUI16R MRa, MRb
MI16TOF32 MRa, MRb
MI16TOF32 MRa, mem16
MUI16TOF32 MRa, mem16
MUI16TOF32 MRa, MRb

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MF32TOI16R MRa, MRb

Convert 32-Bit Floating-Point Value to 16-Bit Integer and Round

Operands MRa CLA floating-point destination register (MR0 to MR3)

MRb CLA floating-point source register (MR0 to MR3)

Opcode
LSW: 0000 0000 0000 bbaa
MSW: 0111 1110 0110 0000

Description Convert the 32-bit floating point value in MRb to a 16-bit integer and round to the nearest
even value. The result is stored in MRa.

MRa(15:0) = F32TOI16round(MRb);
MRa(31:16) = sign extension of MRa(15);

Flags This instruction does not affect any flags:

Flag TF ZF NF LUF LVF
Modified No No No No No

Pipeline This is a single-cycle instruction.

Example
MMOVIZ MR0, #0x3FD9 ; MR0(31:16) = 0x3FD9
MMOVXI MR0, #0x999A ; MR0(15:0) = 0x999A
; MR0 = 1.7 (0x3FD9999A)
MF32TOI16R MR1, MR0 ; MR1(15:0) = MF32TOI16round (MR0) = 2 (0x0002)
; MR1(31:16) = Sign extension of MR1(15) = 0x0000
MMOVF32 MR2, #-1.7 ; MR2 = -1.7 (0xBFD9999A)
MF32TOI16R MR3, MR2 ; MR3(15:0) = MF32TOI16round (MR2) = -2 (0xFFFE)
; MR3(31:16) = Sign extension of MR2(15) = 0xFFFF

See also MF32TOI16 MRa, MRb

MF32TOUI16 MRa, MRb
MF32TOUI16R MRa, MRb
MI16TOF32 MRa, MRb
MI16TOF32 MRa, mem16
MUI16TOF32 MRa, mem16
MUI16TOF32 MRa, MRb

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MF32TOI32 MRa, MRb

Convert 32-Bit Floating-Point Value to 32-Bit Integer

Operands MRa CLA floating-point destination register (MR0 to MR3)

MRb CLA floating-point source register (MR0 to MR3)

Opcode
LSW: 0000 0000 0000 bbaa
MSW: 0111 1101 0110 0000

Description Convert the 32-bit floating-point value in MRb to a 32-bit integer value and truncate. Store
the result in MRa.

MRa = F32TOI32(MRb);

Flags This instruction does not affect any flags:

Flag TF ZF NF LUF LVF
Modified No No No No No

Pipeline This is a single-cycle instruction.

Example 1
MMOVF32 MR2, #11204005.0 ; MR2 = 11204005.0 (0x4B2AF5A5)
MF32TOI32 MR3, MR2 ; MR3 = MF32TOI32(MR2) = 11204005 (0x00AAF5A5)
MMOVF32 MR0, #-11204005.0 ; MR0 = -11204005.0 (0xCB2AF5A5)
MF32TOI32 MR1, MR0 ; MR1 = MF32TOI32(MR0) = -11204005 (0xFF550A5B)

Example 2
; Given X, M and B are IQ24 numbers:
; X = IQ24(+2.5) = 0x02800000
; M = IQ24(+1.5) = 0x01800000
; B = IQ24(-0.5) = 0xFF800000
;
; Calculate Y = X * M + B
;
; Convert M, X, and B from IQ24 to float
;
_Cla1Task2:
MI32TOF32 MR0, @_M ; MR0 = 0x4BC00000
MI32TOF32 MR1, @_X ; MR1 = 0x4C200000
MI32TOF32 MR2, @_B ; MR2 = 0xCB000000
MMPYF32 MR0, MR0, #0x3380 ; M = 1/(1*2^24) * iqm = 1.5 (0x3FC00000)
MMPYF32 MR1, MR1, #0x3380 ; X = 1/(1*2^24) * iqx = 2.5 (0x40200000)
MMPYF32 MR2, MR2, #0x3380 ; B = 1/(1*2^24) * iqb = -.5 (0xBF000000)
MMPYF32 MR3, MR0, MR1 ; M*X
MADDF32 MR2, MR2, MR3 ; Y=MX+B = 3.25 (0x40500000)
; Convert Y from float32 to IQ24
MMPYF32 MR2, MR2, #0x4B80 ; Y * 1*2^24
MF32TOI32 MR2, MR2 ; IQ24(Y) = 0x03400000
MMOV32 @_Y, MR2 ; store result
MSTOP ; end of task

See also MF32TOUI32 MRa, MRb

MI32TOF32 MRa, MRb
MI32TOF32 MRa, mem32
MUI32TOF32 MRa, MRb
MUI32TOF32 MRa, mem32

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MF32TOUI16 MRa, MRb

Convert 32-Bit Floating-Point Value to 16-bit Unsigned Integer

Operands MRa CLA floating-point destination register (MR0 to MR3)

MRb CLA floating-point source register (MR0 to MR3)

Opcode
LSW: 0000 0000 0000 bbaa
MSW: 0111 1110 1010 0000

Description Convert the 32-bit floating point value in MRb to an unsigned 16-bit integer value and
truncate to zero. The result is stored in MRa. To instead round the integer to the nearest
even value, use the MF32TOUI16R instruction.

MRa(15:0) = F32TOUI16(MRb);
MRa(31:16) = 0x0000;

Flags This instruction does not affect any flags:

Flag TF ZF NF LUF LVF
Modified No No No No No

Pipeline This is a single-cycle instruction.

Example
MMOVIZ MR0, #9.0 ; MR0 = 9.0 (0x41100000)
MF32TOUI16 MR1, MR0 ; MR1(15:0) = MF32TOUI16(MR0) = 9 (0x0009)
; MR1(31:16) = 0x0000
MMOVIZ MR2, #-9.0 ; MR2 = -9.0 (0xC1100000)
MF32TOUI16 MR3, MR2 ; MR3(15:0) = MF32TOUI16(MR2) = 0 (0x0000)
; MR3(31:16) = 0x0000

See also MF32TOI16 MRa, MRb

MF32TOUI16 MRa, MRb
MF32TOUI16R MRa, MRb
MI16TOF32 MRa, MRb
MI16TOF32 MRa, mem16
MUI16TOF32 MRa, mem16
MUI16TOF32 MRa, MRb

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MF32TOUI16R MRa, MRb

Convert 32-Bit Floating-Point Value to 16-bit Unsigned Integer and Round

Operands MRa CLA floating-point destination register (MR0 to MR3)

MRb CLA floating-point source register (MR0 to MR3)

Opcode
LSW: 0000 0000 0000 bbaa
MSW: 0111 1110 1100 0000

Description Convert the 32-bit floating-point value in MRb to an unsigned 16-bit integer and round to
the closest even value. The result is stored in MRa. To instead truncate the converted
value, use the MF32TOUI16 instruction.

MRa(15:0) = MF32TOUI16round(MRb);
MRa(31:16) = 0x0000;

Flags This instruction does not affect any flags:

Flag TF ZF NF LUF LVF
Modified No No No No No

Pipeline This is a single-cycle instruction.

Example
MMOVIZ MR0, #0x412C ; MR0 = 0x412C
MMOVXI MR0, #0xCCCD ; MR0 = 0xCCCD ; MR0 = 10.8 (0x412CCCCD)
MF32TOUI16R MR1, MR0 ; MR1(15:0) = MF32TOUI16round(MR0) = 11 (0x000B)
; MR1(31:16) = 0x0000
MMOVF32 MR2, #-10.8 ; MR2 = -10.8 (0x0xC12CCCCD)
MF32TOUI16R MR3, MR2 ; MR3(15:0) = MF32TOUI16round(MR2) = 0 (0x0000)
; MR3(31:16) = 0x0000

See also MF32TOI16 MRa, MRb

MF32TOI16R MRa, MRb
MF32TOUI16 MRa, MRb
MI16TOF32 MRa, MRb
MI16TOF32 MRa, mem16
MUI16TOF32 MRa, mem16
MUI16TOF32 MRa, MRb

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MF32TOUI32 MRa, MRb

Convert 32-Bit Floating-Point Value to 32-Bit Unsigned Integer

Operands MRa CLA floating-point destination register (MR0 to MR3)

MRb CLA floating-point source register (MR0 to MR3)

Opcode
LSW: 0000 0000 0000 bbaa
MSW: 0111 1101 1010 0000

Description Convert the 32-bit floating-point value in MRb to an unsigned 32-bit integer and store the
result in MRa.

MRa = F32TOUI32(MRb);

Flags This instruction does not affect any flags:

Flag TF ZF NF LUF LVF
Modified No No No No No

Pipeline This is a single-cycle instruction.

Example
MMOVIZ MR0, #12.5 ; MR0 = 12.5 (0x41480000)
MF32TOUI32 MR0, MR0 ; MR0 = MF32TOUI32 (MR0) = 12 (0x0000000C)
MMOVIZ MR1, #-6.5 ; MR1 = -6.5 (0xC0D00000)
MF32TOUI32 MR2, MR1 ; MR2 = MF32TOUI32 (MR1) = 0.0 (0x00000000)

See also MF32TOI32 MRa, MRb

MI32TOF32 MRa, MRb
MI32TOF32 MRa, mem32
MUI32TOF32 MRa, MRb
MUI32TOF32 MRa, mem32

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MFRACF32 MRa, MRb

Fractional Portion of a 32-Bit Floating-Point Value

Operands MRa CLA floating-point destination register (MR0 to MR3)

MRb CLA floating-point source register (MR0 to MR3)

Opcode
LSW: 0000 0000 0000 bbaa
MSW: 0111 1110 0000 0000

Description Returns in MRa the fractional portion of the 32-bit floating-point value in MRb

Flags This instruction does not affect any flags:

Flag TF ZF NF LUF LVF
Modified No No No No No

Pipeline This is a single-cycle instruction.

Example
MMOVIZ MR2, #19.625 ; MR2 = 19.625 (0x419D0000)
MFRACF32 MR3, MR2 ; MR3 = MFRACF32(MR2) = 0.625 (0x3F200000)0)

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MI16TOF32 MRa, MRb

Convert 16-Bit Integer to 32-Bit Floating-Point Value

Operands MRa CLA floating-point destination register (MR0 to MR3)

MRb CLA floating-point source register (MR0 to MR3)

Opcode
LSW: 0000 0000 0000 bbaa
MSW: 0111 1110 1000 0000

Description Convert the 16-bit signed integer in MRb to a 32-bit floating-point value and store the
result in MRa.

MRa = MI16TOF32(MRb);

Flags This instruction does not affect any flags:

Flag TF ZF NF LUF LVF
Modified No No No No No

Pipeline This is a single-cycle instruction.

Example
MMOVIZ MR0, #0x0000 ; MR0(31:16) = 0.0 (0x0000)
MMOVXI MR0, #0x0004 ; MR0(15:0) = 4.0 (0x0004)
MI16TOF32 MR1, MR0 ; MR1 = MI16TOF32 (MR0) = 4.0 (0x40800000)
MMOVIZ MR2, #0x0000 ; MR2(31:16) = 0.0 (0x0000)
MMOVXI MR2, #0xFFFC ; MR2(15:0) = -4.0 (0xFFFC)
MI16TOF32 MR3, MR2 ; MR3 = MI16TOF32 (MR2) = -4.0 (0xC0800000)
MSTOP

See also MF32TOI16 MRa, MRb

MF32TOI16R MRa, MRb
MF32TOUI16 MRa, MRb
MF32TOUI16R MRa, MRb
MI16TOF32 MRa, mem16
MUI16TOF32 MRa, mem16
MUI16TOF32 MRa, MRb

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MI16TOF32 MRa, mem16

Convert 16-Bit Integer to 32-Bit Floating-Point Value

Operands MRa CLA floating-point destination register (MR0 to MR3)

mem16 16-bit source memory location to be converted

Opcode
LSW: mmmm mmmm mmmm mmmm
MSW: 0111 0101 00aa addr

Description Convert the 16-bit signed integer indicated by the mem16 pointer to a 32-bit floating-point
value and store the result in MRa.

MRa = MI16TOF32[mem16];

Flags This instruction does not affect any flags:

Flag TF ZF NF LUF LVF
Modified No No No No No

Pipeline This is a single-cycle instruction:

Example
; Assume A = 4 (0x0004)
; B = -4 (0xFFFC)
MI16TOF32 MR0, @_A ; MR0 = MI16TOF32(A) = 4.0 (0x40800000)
MI16TOF32 MR1, @_B ; MR1 = MI16TOF32(B) = -4.0 (0xC0800000

See also MF32TOI16 MRa, MRb

MF32TOI16R MRa, MRb
MF32TOUI16 MRa, MRb
MF32TOUI16R MRa, MRb
MI16TOF32 MRa, MRb
MUI16TOF32 MRa, mem16
MUI16TOF32 MRa, MRb

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MI32TOF32 MRa, mem32

Convert 32-Bit Integer to 32-Bit Floating-Point Value

Operands MRa CLA floating-point destination register (MR0 to MR3)

mem32 32-bit memory source for the MMOV32 operation.

Opcode
LSW: mmmm mmmm mmmm mmmm
MSW: 0111 0100 01aa addr

Description Convert the 32-bit signed integer indicated by mem32 to a 32-bit floating-point value and
store the result in MRa.

MRa = MI32TOF32[mem32];

Flags This instruction does not affect any flags:

Flag TF ZF NF LUF LVF
Modified No No No No No

Pipeline This is a single-cycle instruction.

Example
; Given X, M and B are IQ24 numbers:
; X = IQ24(+2.5) = 0x02800000
; M = IQ24(+1.5) = 0x01800000
; B = IQ24(-0.5) = 0xFF800000
;
; Calculate Y = X * M + B
;
; Convert M, X, and B from IQ24 to float
;
_Cla1Task3:
MI32TOF32 MR0, @_M ; MR0 = 0x4BC00000
MI32TOF32 MR1, @_X ; MR1 = 0x4C200000
MI32TOF32 MR2, @_B ; MR2 = 0xCB000000
MMPYF32 MR0, MR0, #0x3380 ; M = 1/(1*2^24) * iqm = 1.5 (0x3FC00000)
MMPYF32 MR1, MR1, #0x3380 ; X = 1/(1*2^24) * iqx = 2.5 (0x40200000)
MMPYF32 MR2, MR2, #0x3380 ; B = 1/(1*2^24) * iqb = -.5 (0xBF000000)
MMPYF32 MR3, MR0, MR1 ; M*X
MADDF32 MR2, MR2, MR3 ; Y=MX+B = 3.25 (0x40500000)
; Convert Y from float32 to IQ24
MMPYF32 MR2, MR2, #0x4B80 ; Y * 1*2^24
MF32TOI32 MR2, MR2 ; IQ24(Y) = 0x03400000
MMOV32 @_Y, MR2 ; store result
MSTOP ; end of task

See also MF32TOI32 MRa, MRb

MF32TOUI32 MRa, MRb
MI32TOF32 MRa, MRb
MUI32TOF32 MRa, MRb
MUI32TOF32 MRa, mem32

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MI32TOF32 MRa, MRb

Convert 32-Bit Integer to 32-Bit Floating-Point Value

Operands MRa CLA floating-point destination register (MR0 to MR3)

MRb CLA floating-point source register (MR0 to MR3)

Opcode
LSW: 0000 0000 0000 bbaa
MSW: 0111 1101 1000 0000

Description Convert the signed 32-bit integer in MRb to a 32-bit floating-point value and store the
result in MRa.

MRa = MI32TOF32(MRb);

Flags This instruction does not affect any flags:

Flag TF ZF NF LUF LVF
Modified No No No No No

Pipeline This is a single-cycle instruction.

Example
MMOVIZ MR2, #0x1111 ; MR2(31:16) = 4369 (0x1111)
MMOVXI MR2, #0x1111 ; MR2(15:0) = 4369 (0x1111)
; MR2 = +286331153 (0x11111111)
MI32TOF32 MR3, MR2 ; MR3 = MI32TOF32 (MR2) = 286331153.0 (0x4D888888)

See also MF32TOI32 MRa, MRb

MF32TOUI32 MRa, MRb
MI32TOF32 MRa, mem32
MUI32TOF32 MRa, MRb
MUI32TOF32 MRa, mem32

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MLSL32 MRa, #SHIFT

Logical Shift Left

Operands MRa CLA floating-point source/destination register (MR0 to MR3)

#SHIFT Number of bits to shift (1 to 32)

Opcode
LSW: 0000 0000 0shi ftaa
MSW: 0111 1011 1100 0000

Description Logical shift-left of MRa by the number of bits indicated. The number of bits can be 1 to
32.

MARa(31:0) = Logical Shift Left(MARa(31:0) by #SHIFT bits);

Flags This instruction modifies the following flags in the MSTF register:
Flag TF ZF NF LUF LVF
Modified No Yes Yes No No

The MSTF register flags are modified based on the integer results of the operation.

NF = MRa(31);
ZF = 0;
if(MRa(31:0) == 0) { ZF = 1; }

Pipeline This is a single-cycle instruction.

Example
; Given m2 = (int32)32
; x2 = (int32)64
; b2 = (int32)-128
;
; Calculate:
; m2 = m2*2
; x2 = x2*4
; b2 = b2*8
;
_Cla1Task3:
MMOV32 MR0, @_m2 ; MR0 = 32 (0x00000020)
MMOV32 MR1, @_x2 ; MR1 = 64 (0x00000040)
MMOV32 MR2, @_b2 ; MR2 = -128 (0xFFFFFF80)
MLSL32 MR0, #1 ; MR0 = 64 (0x00000040)
MLSL32 MR1, #2 ; MR1 = 256 (0x00000100)
MLSL32 MR2, #3 ; MR2 = -1024 (0xFFFFFC00)
MMOV32 @_m2, MR0 ; Store results
MMOV32 @_x2, MR1
MMOV32 @_b2, MR2
MSTOP ; end of task

See also MADD32 MRa, MRb, MRc

MASR32 MRa, #SHIFT
MAND32 MRa, MRb, MRc
MLSR32 MRa, #SHIFT
MOR32 MRa, MRb, MRc
MXOR32 MRa, MRb, MRc
MSUB32 MRa, MRb, MRc

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MLSR32 MRa, #SHIFT

Logical Shift Right

Operands MRa CLA floating-point source/destination register (MR0 to MR3)

#SHIFT Number of bits to shift (1 to 32)

Opcode
LSW: 0000 0000 0shi ftaa
MSW: 0111 1011 1000 0000

Description Logical shift-right of MRa by the number of bits indicated. The number of bits can be 1 to
32. Unlike the arithmetic shift (MASR32), the logical shift does not preserve the number's
sign bit. Every bit in the operand is moved the specified number of bit positions, and the
vacant bit positions are filled in with zeros.

MARa(31:0) = Logical Shift Right(MARa(31:0) by #SHIFT bits);

Flags This instruction modifies the following flags in the MSTF register:
Flag TF ZF NF LUF LVF
Modified No Yes Yes No No

The MSTF register flags are modified based on the integer results of the operation.

NF = MRa(31);
ZF = 0;
if(MRa(31:0) == 0) { ZF = 1;}

Pipeline This is a single-cycle instruction.

Example
; Illustrate the difference between MASR32 and MLSR32
MMOVIZ MR0, #0xAAAA ; MR0 = 0xAAAA5555
MMOVXI MR0, #0x5555
MMOV32 MR1, MR0 ; MR1 = 0xAAAA5555
MMOV32 MR2, MR0 ; MR2 = 0xAAAA5555
MASR32 MR1, #1 ; MR1 = 0xD5552AAA
MLSR32 MR2, #1 ; MR2 = 0x55552AAA
MASR32 MR1, #1 ; MR1 = 0xEAAA9555
MLSR32 MR2, #1 ; MR2 = 0x2AAA9555
MASR32 MR1, #6 ; MR1 = 0xFFAAAA55
MLSR32 MR2, #6 ; MR2 = 0x00AAAA55

See also MADD32 MRa, MRb, MRc

MASR32 MRa, #SHIFT
MAND32 MRa, MRb, MRc
MLSL32 MRa, #SHIFT
MOR32 MRa, MRb, MRc
MXOR32 MRa, MRb, MRc
MSUB32 MRa, MRb, MRc

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MMACF32 MR3, MR2, MRd, MRe, MRf ||MMOV32 MRa, mem32

32-Bit Floating-Point Multiply and Accumulate with Parallel Move

Operands MR3 floating-point destination/source register MR3 for the add

operation
MR2 CLA floating-point source register MR2 for the add operation
MRd CLA floating-point destination register (MR0 to MR3) for the
multiply operation
MRd cannot be the same register as MRa
MRe CLA floating-point source register (MR0 to MR3) for the multiply
operation
MRf CLA floating-point source register (MR0 to MR3) for the multiply
operation
MRa CLA floating-point destination register for the MMOV32 operation
(MR0 to MR3).
MRa cannot be MR3 or the same register as MRd.
mem32 32-bit source for the MMOV32 operation

Opcode
LSW: mmmm mmmm mmmm mmmm
MSW: 0011 ffee ddaa addr

Description Multiply and accumulate the contents of floating-point registers and move from register to
memory. The destination register for the MMOV32 cannot be the same as the destination
registers for the MMACF32.

MR3 = MR3 + MR2;

MRd = MRe * MRf;
MRa = [mem32];

Restrictions The destination registers for the MMACF32 and the MMOV32 must be unique. That is,
MRa cannot be MR3 and MRa cannot be the same register as MRd.

Flags This instruction modifies the following flags in the MSTF register:
Flag TF ZF NF LUF LVF
Modified No Yes Yes Yes Yes

The MSTF register flags are modified as follows:

• LUF = 1 if MMACF32 (add or multiply) generates an underflow condition.
• LVF = 1 if MMACF32 (add or multiply) generates an overflow condition.
MMOV32 sets the NF and ZF flags as follows:

NF = MRa(31);
ZF = 0;
if(MRa(30:23) == 0) { ZF = 1; NF = 0; }

Pipeline MMACF32 and MMOV32 complete in a single cycle.

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MMACF32 MR3, MR2, MRd, MRe, MRf ||MMOV32 MRa, mem32 (continued)

32-Bit Floating-Point Multiply and Accumulate with Parallel Move

Example 1
; Perform 5 multiply and accumulate operations:
;
; X and Y are 32-bit floating-point arrays
;
; 1st multiply: A = X0 * Y0
; 2nd multiply: B = X1 * Y1
; 3rd multiply: C = X2 * Y2
; 4th multiply: D = X3 * Y3
; 5th multiply: E = X3 * Y3
;
; Result = A + B + C + D + E
;
_Cla1Task1:
MMOVI16 MAR0, #_X ; MAR0 points to X array
MMOVI16 MAR1, #_Y ; MAR1 points to Y array
MNOP ; Delay for MAR0, MAR1 load
MNOP ; Delay for MAR0, MAR1 load
; <-- MAR0 valid
MMOV32 MR0, *MAR0[2]++ ; MR0 = X0, MAR0 += 2
; <-- MAR1 valid
MMOV32 MR1, *MAR1[2]++ ; MR1 = Y0, MAR1 += 2
MMPYF32 MR2, MR0, MR1 ; MR2 = A = X0 * Y0
|| MMOV32 MR0, *MAR0[2]++ ; In parallel MR0 = X1, MAR0 += 2
MMOV32 MR1, *MAR1[2]++ ; MR1 = Y1, MAR1 += 2
MMPYF32 MR3, MR0, MR1 ; MR3 = B = X1 * Y1
|| MMOV32 MR0, *MAR0[2]++ ; In parallel MR0 = X2, MAR0 += 2
MMOV32 MR1, *MAR1[2]++ ; MR1 = Y2, MAR2 += 2
MMACF32 MR3, MR2, MR2, MR0, MR1 ; MR3 = A + B, MR2 = C = X2 * Y2
|| MMOV32 MR0, *MAR0[2]++ ; In parallel MR0 = X3
MMOV32 MR1, *MAR1[2]++ ; MR1 = Y3 M
MACF32 MR3, MR2, MR2, MR0, MR1 ; MR3 = (A + B) + C, MR2 = D = X3 * Y3
|| MMOV32 MR0, *MAR0 ; In parallel MR0 = X4
MMOV32 MR1, *MAR1 ; MR1 = Y4
MMPYF32 MR2, MR0, MR1 ; MR2 = E = X4 * Y4
|| MADDF32 MR3, MR3, MR2 ; in parallel MR3 = (A + B + C) + D
MADDF32 MR3, MR3, MR2 ; MR3 = (A + B + C + D) + E
MMOV32 @_Result, MR3 ; Store the result
MSTOP ; end of task

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MMACF32 MR3, MR2, MRd, MRe, MRf ||MMOV32 MRa, mem32 (continued)

32-Bit Floating-Point Multiply and Accumulate with Parallel Move

Example 2
; sum = X0*B0 + X1*B1 + X2*B2 + Y1*A1 + Y2*B2
;
; X2 = X1
; X1 = X0
; Y2 = Y1 ; Y1 = sum
;
_ClaTask2:
MMOV32 MR0, @_B2 ; MR0 = B2
MMOV32 MR1, @_X2 ; MR1 = X2
MMPYF32 MR2, MR1, MR0 ; MR2 = X2*B2
|| MMOV32 MR0, @_B1 ; MR0 = B1
MMOVD32 MR1, @_X1 ; MR1 = X1, X2 = X1
MMPYF32 MR3, MR1, MR0 ; MR3 = X1*B1
|| MMOV32 MR0, @_B0 ; MR0 = B0
MMOVD32 MR1, @_X0 ; MR1 = X0, X1 = X0
; MR3 = X1*B1 + X2*B2, MR2 = X0*B0
; MR0 = A2
MMACF32 MR3, MR2, MR2, MR1, MR0
|| MMOV32 MR0, @_A2 M

MOV32 MR1, @_Y2 ; MR1 = Y2

; MR3 = X0*B0 + X1*B1 + X2*B2, MR2 = Y2*A2
; MR0 = A1
MMACF32 MR3, MR2, MR2, MR1, MR0
|| MMOV32 MR0, @_A1
MMOVD32 MR1,@_Y1 ; MR1 = Y1, Y2 = Y1
MADDF32 MR3, MR3, MR2 ; MR3 = Y2*A2 + X0*B0 + X1*B1 + X2*B2
|| MMPYF32 MR2, MR1, MR0 ; MR2 = Y1*A1
MADDF32 MR3, MR3, MR2 ; MR3 = Y1*A1 + Y2*A2 + X0*B0 + X1*B1 + X2*B2
MMOV32 @_Y1, MR3 ; Y1 = MR3
MSTOP ; end of task

See also MMPYF32 MRa, MRb, MRc || MADDF32 MRd, MRe, MRf

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MMAXF32 MRa, MRb

32-Bit Floating-Point Maximum

Operands MRa CLA floating-point source/destination register (MR0 to MR3)

MRb CLA floating-point source register (MR0 to MR3)

Opcode
LSW: 0000 0000 0000 bbaa
MSW: 0111 1101 0010 0000

Description
if(MRa < MRb) MRa = MRb;

Special cases for the output from the MMAXF32 operation:

• NaN output is converted to infinity
• A denormalized output is converted to positive zero.

Flags This instruction modifies the following flags in the MSTF register:
Flag TF ZF NF LUF LVF
Modified No Yes Yes No No

The ZF and NF flags are configured on the result of the operation, not the result stored in
the destination register.

if(MRa == MRb) {ZF=1; NF=0;}

if(MRa > MRb) {ZF=0; NF=0;}
if(MRa < MRb) {ZF=0; NF=1;}

Pipeline This is a single-cycle instruction.

Example 1
MMOVIZ MR0, #5.0 ; MR0 = 5.0 (0x40A00000)
MMOVIZ MR1, #-2.0 ; MR1 = -2.0 (0xC0000000)
MMOVIZ MR2, #-1.5 ; MR2 = -1.5 (0xBFC00000)
MMAXF32 MR2, MR1 ; MR2 = -1.5, ZF = NF = 0
MMAXF32 MR1, MR2 ; MR1 = -1.5, ZF = 0, NF = 1
MMAXF32 MR2, MR0 ; MR2 = 5.0, ZF = 0, NF = 1
MAXF32 MR0, MR2 ; MR2 = 5.0, ZF = 1, NF = 0

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MMAXF32 MRa, MRb (continued)

32-Bit Floating-Point Maximum

Example 2
; X is an array of 32-bit floating-point values
; Find the maximum value in an array X
; and store the value in Result
;
_Cla1Task1:
MMOVI16 MAR1,#_X ; Start address
MUI16TOF32 MR0, @_len ; Length of the array
MNOP ; delay for MAR1 load
MNOP ; delay for MAR1 load
MMOV32 MR1, *MAR1[2]++ ; MR1 = X0
LOOP
MMOV32 MR2, *MAR1[2]++ ; MR2 = next element
MMAXF32 MR1, MR2 ; MR1 = MAX(MR1, MR2)
MADDF32 MR0, MR0, #-1.0 ; Decrememt the counter
MCMPF32 MR0 #0.0 ; Set/clear flags for MBCNDD
MNOP
MNOP
MNOP
MBCNDD LOOP, NEQ ; Branch if not equal to zero
MMOV32 @_Result, MR1 ; Always executed
MNOP ; Always executed
MNOP ; Always executed
MSTOP ; End of task

See also MCMPF32 MRa, MRb

MCMPF32 MRa, #16FHi
MMAXF32 MRa, #16FHi
MMINF32 MRa, MRb
MMINF32 MRa, #16FHi

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MMAXF32 MRa, #16FHi

32-Bit Floating-Point Maximum

Operands MRa CLA floating-point source/destination register (MR0 to MR3)

#16FHi A 16-bit immediate value that represents the upper 16-bits of an
IEEE 32-bit floating-point value. The low 16-bits of the mantissa
are assumed to be all 0.

Opcode
LSW: IIII IIII IIII IIII
MSW: 0111 1001 0000 00aa

Description Compare MRa with the floating-point value represented by the immediate operand. If the
immediate value is larger, then load the value into MRa.

if(MRa < #16FHi:0) MRa = #16FHi:0;

#16FHi is a 16-bit immediate value that represents the upper 16-bits of an IEEE 32-bit
floating-point value. The low 16-bits of the mantissa are assumed to be all 0. This
addressing mode is most useful for constants where the lowest 16-bits of the mantissa
are 0. Some examples are 2.0 (0x40000000), 4.0 (0x40800000), 0.5 (0x3F000000), and
-1.5 (0xBFC00000). The assembler accepts either a hex or float as the immediate value.
That is, -1.5 can be represented as #-1.5 or #0xBFC0.
Special cases for the output from the MMAXF32 operation:
• NaN output is converted to infinity
• A denormalized output is converted to positive zero.

Flags This instruction modifies the following flags in the MSTF register:
Flag TF ZF NF LUF LVF
Modified No Yes Yes No No

The ZF and NF flags are configured on the result of the operation, not the result stored in
the destination register.

if(MRa == #16FHi:0) {ZF=1; NF=0;}

if(MRa > #16FHi:0) {ZF=0; NF=0;}
if(MRa < #16FHi:0) {ZF=0; NF=1;}

Pipeline This is a single-cycle instruction.

Example
MMOVIZ MR0, #5.0 ; MR0 = 5.0 (0x40A00000)
MMOVIZ MR1, #4.0 ; MR1 = 4.0 (0x40800000)
MMOVIZ MR2, #-1.5 ; MR2 = -1.5 (0xBFC00000)
MMAXF32 MR0, #5.5 ; MR0 = 5.5, ZF = 0, NF = 1
MMAXF32 MR1, #2.5 ; MR1 = 4.0, ZF = 0, NF = 0
MMAXF32 MR2, #-1.0 ; MR2 = -1.0, ZF = 0, NF = 1
MMAXF32 MR2, #-1.0 ; MR2 = -1.5, ZF = 1, NF = 0

See also MMAXF32 MRa, MRb

MMINF32 MRa, MRb
MMINF32 MRa, #16FHi

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MMINF32 MRa, MRb

32-Bit Floating-Point Minimum

Operands MRa CLA floating-point source/destination register (MR0 to MR3)

MRb CLA floating-point source register (MR0 to MR3)

Opcode
LSW: 0000 0000 0000 bbaa
MSW: 0111 1101 0100 0000

Description
if(MRa > MRb) MRa = MRb;

Special cases for the output from the MMINF32 operation:

• NaN output is converted to infinity
• A denormalized output is converted to positive zero.

Flags This instruction modifies the following flags in the MSTF register:
Flag TF ZF NF LUF LVF
Modified No Yes Yes No No

The ZF and NF flags are configured on the result of the operation, not the result stored in
the destination register.

if(MRa == MRb) {ZF=1; NF=0;}

if(MRa > MRb) {ZF=0; NF=0;}
if(MRa < MRb) {ZF=0; NF=1;}

Pipeline This is a single-cycle instruction.

Example 1
MMOVIZ MR0, #5.0 ; MR0 = 5.0 (0x40A00000)
MMOVIZ MR1, #4.0 ; MR1 = 4.0 (0x40800000)
MMOVIZ MR2, #-1.5 ; MR2 = -1.5 (0xBFC00000)
MMINF32 MR0, MR1 ; MR0 = 4.0, ZF = 0, NF = 0
MMINF32 MR1, MR2 ; MR1 = -1.5, ZF = 0, NF = 0
MMINF32 MR2, MR1 ; MR2 = -1.5, ZF = 1, NF = 0
MMINF32 MR1, MR0 ; MR2 = -1.5, ZF = 0, NF = 1

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MMINF32 MRa, MRb (continued)

32-Bit Floating-Point Minimum

Example 2
;
; X is an array of 32-bit floating-point values
; Find the minimum value in an array X
; and store the value in Result
;
_Cla1Task1:
MMOVI16 MAR1,#_X ; Start address
MUI16TOF32 MR0, @_len ; Length of the array
MNOP ; delay for MAR1 load
MNOP ; delay for MAR1 load
MMOV32 MR1, *MAR1[2]++ ; MR1 = X0
LOOP
MMOV32 MR2, *MAR1[2]++ ; MR2 = next element
MMINF32 MR1, MR2 ; MR1 = MAX(MR1, MR2)
MADDF32 MR0, MR0, #-1.0 ; Decrememt the counter
MCMPF32 MR0 #0.0 ; Set/clear flags for MBCNDD
MNOP
MNOP
MNOP
MBCNDD LOOP, NEQ ; Branch if not equal to zero
MMOV32 @_Result, MR1 ; Always executed
MNOP ; Always executed
MNOP ; Always executed
MSTOP ; End of task

See also MMAXF32 MRa, MRb

MMAXF32 MRa, #16FHi
MMINF32 MRa, #16FHi

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MMINF32 MRa, #16FHi

32-Bit Floating-Point Minimum

Operands MRa floating-point source/destination register (MR0 to MR3)

#16FHi A 16-bit immediate value that represents the upper 16-bits of an
IEEE 32-bit floating-point value. The low 16-bits of the mantissa
are assumed to be all 0.

Opcode
LSW: IIII IIII IIII IIII
MSW: 0111 1001 0100 00aa

Description Compare MRa with the floating-point value represented by the immediate operand. If the
immediate value is smaller, then load the value into MRa.

if(MRa > #16FHi:0) MRa = #16FHi:0;

#16FHi is a 16-bit immediate value that represents the upper 16-bits of an IEEE 32-bit
floating-point value. The low 16-bits of the mantissa are assumed to be all 0. This
addressing mode is most useful for constants where the lowest 16-bits of the mantissa
are 0. Some examples are 2.0 (0x40000000), 4.0 (0x40800000), 0.5 (0x3F000000), and
-1.5 (0xBFC00000). The assembler accepts either a hex or float as the immediate value.
That is, -1.5 can be represented as #-1.5 or #0xBFC0.
Special cases for the output from the MMINF32 operation:
• NaN output is converted to infinity
• A denormalized output is converted to positive zero.

Flags This instruction modifies the following flags in the MSTF register:
Flag TF ZF NF LUF LVF
Modified No Yes Yes No No

The ZF and NF flags are configured on the result of the operation, not the result stored in
the destination register.

if(MRa == #16FHi:0) {ZF=1; NF=0;}

if(MRa > #16FHi:0) {ZF=0; NF=0;}
if(MRa < #16FHi:0) {ZF=0; NF=1;}

Pipeline This is a single-cycle instruction.

Example
MMOVIZ MR0, #5.0 ; MR0 = 5.0 (0x40A00000)
MMOVIZ MR1, #4.0 ; MR1 = 4.0 (0x40800000)
MMOVIZ MR2, #-1.5 ; MR2 = -1.5 (0xBFC00000)
MMINF32 MR0, #5.5 ; MR0 = 5.0, ZF = 0, NF = 1
MMINF32 MR1, #2.5 ; MR1 = 2.5, ZF = 0, NF = 0
MMINF32 MR2, #-1.0 ; MR2 = -1.5, ZF = 0, NF = 1
MMINF32 MR2, #-1.5 ; MR2 = -1.5, ZF = 1, NF = 0

See also MMAXF32 MRa, #16FHi

MMAXF32 MRa, MRb
MMINF32 MRa, MRb

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MMOV16 MARx, MRa, #16I

Load the Auxiliary Register with MRa + 16-bit Immediate Value

Operands MARx Auxiliary register MAR0 or MAR1

MRa CLA Floating-point register (MR0 to MR3)
#16I 16-bit immediate value

Opcode
LSW: IIII IIII IIII IIII (opcode of MMOV16 MAR0, MRa, #16I)
MSW: 0111 1111 1101 00AA
LSW: IIII IIII IIII IIII (opcode of MMOV16 MAR1, MRa, #16I)
MSW: 0111 1111 1111 00AA

Description Load the auxiliary register, MAR0 or MAR1, with MRa(15:0) + 16-bit immediate value.
Refer to the Pipeline section for important information regarding this instruction.

MARx = MRa(15:0) + #16I;

Flags This instruction does not modify flags in the MSTF register:
Flag TF ZF NF LUF LVF
Modified No No No No No

Pipeline This is a single-cycle instruction. The load of MAR0 or MAR1 occurs in the EXE phase
of the pipeline. Any post increment of MAR0 or MAR1 using indirect addressing occurs in
the D2 phase of the pipeline. Therefore, the following applies when loading the auxiliary
registers:
• I1 and I2
The two instructions following MMOV16 use MAR0 or MAR1 before the update occurs.
Thus, these two instructions use the old value of MAR0 or MAR1.
• I3
Loading of an auxiliary register occurs in the EXE phase while updates due to post-
increment addressing occur in the D2 phase. Thus, I3 cannot use the auxiliary register
or there is a conflict. In the case of a conflict, the update due to address-mode post
increment wins and the auxiliary register is not updated with #_X.
• I4
Starting with the 4th instruction, MAR0 or MAR1 is the new value loaded with
MMOVI16.

; Assume MAR0 is 50, MR0 is 10, and #_X is 20

MMOV16 MAR0, MR0, #_X ; Load MAR0 with address of X (20) + MR0 (10)
<Instruction 1> ; I1 Uses the old value of MAR0 (50)
<Instruction 2> ; I2 Uses the old value of MAR0 (50)
<Instruction 3> ; I3 Cannot use MAR0
<Instruction 4> ; I4 Uses the new value of MAR0 (30)
<Instruction 5> ; I5

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MMOV16 MARx, MRa, #16I (continued)

Load the Auxiliary Register with MRa + 16-bit Immediate Value

Table 8-16. Pipeline Activity for MMOV16 MARx, MRa , #16I

Instruction F1 F2 D1 D2 R1 R2 E W
MMOV16 MAR0, MR0,
MMOV16
#_X
I1 I1 MMOV16
I2 I2 I1 MMOV16
I3 I3 I2 I1 MMOV16
I4 I4 I3 I2 I1 MMOV16
I5 I5 I4 I3 I2 I1 MMOV16
I6 I6 I5 I4 I3 I2 I1 MMOV16

Example 1
; Calculate an offset into a sin/cos table
;
_Cla1Task1:
MMOV32 MR0,@_rad ; MR0 = rad
MMOV32 MR1,@_TABLE_SIZEDivTwoPi ; MR1 = TABLE_SIZE/(2*Pi)
MMPYF32 MR1,MR0,MR1 ; MR1 = rad* TABLE_SIZE/(2*Pi)
|| MMOV32 MR2,@_TABLE_MASK ; MR2 = TABLE_MASK
MF32TOI32 MR3,MR1 ; MR3 = K=int(rad*TABLE_SIZE/(2*Pi))
MAND32 MR3,MR3,MR2 ; MR3 = K & TABLE_MASK
MLSL32 MR3,#1 ; MR3 = K * 2
MMOV16 MAR0,MR3,#_Cos0 ; MAR0 K*2+addr of table.Cos0
MFRACF32 MR1,MR1 ; I1
MMOV32 MR0,@_TwoPiDivTABLE_SIZE ; I2
MMPYF32 MR1,MR1,MR0 ; I3
|| MMOV32 MR0,@_Coef3
MMOV32 MR2,*MAR0[#-64]++ ; MR2 = *MAR0, MAR0 += (-64)
...
...
MSTOP ; end of task

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MMOV16 MARx, MRa, #16I (continued)

Load the Auxiliary Register with MRa + 16-bit Immediate Value

Example 2
; This task logs the last NUM_DATA_POINTS
; ADCRESULT1 values in the array VoltageCLA
;
; When the last element in the array has been
; filled, the task goes back to the
; the first element.
;
; Before starting the ADC conversions, force
; Task 8 to initialize the ConversionCount to zero
;
; The ADC is set to sample (acquire) for 15 SYSCLK cycles
; or 75ns. After the capacitor has captured the analog
; value, the ADC triggers this task early.
; It takes 10.5 ADCCLKs to complete a conversion,
; the ADCCLK being SYSCLK/4
; T_sys = 1/200MHz = 5ns
; T_adc = 4*T_sys = 20ns
; The ADC takes 10.5 * 4 or 42 SYSCLK cycles to complete
; a conversion. The ADC result register can be read on the
; 36th instruction after the task begins.
;
_Cla1Task2:
.asg 0, N
.loop
MNOP ;I1 - I28 Wait till I36 to read
result
.eval N + 1, N
.break N = 28
.endloop
MMOVZ16 MR0, @_ConversionCount ;I29 Current Conversion
MMOV16 MAR1, MR0, #_VoltageCLA ;I30 Next array location
MUI16TOF32 MR0, MR0 ;I31 Convert count to float32
MADDF32 MR0, MR0, #1.0 ;I32 Add 1 to conversion count
MCMPF32 MR0, #NUM_DATA_POINTS.0 ;I33 Compare count to max
MF32TOUI16 MR0, MR0 ;I34 Convert count to Uint16
MNOP ;I35 Wait till I36 to read
result
MMOVZ16 MR2, @_AdcaResultRegs.ADCRESULT1 ;I36 Read ADCRESULT1
MMOV16 *MAR1, MR2 ; Store ADCRESULT1
MBCNDD _RestartCount, GEQ ; If count >= NUM_DATA_POINTS
MMOVIZ MR1, #0.0 ; Always executed: MR1=0
MNOP
MNOP
MMOV16 @_ConversionCount, MR0 ; If branch not taken
MSTOP ; store current count
_RestartCount
MMOV16 @_ConversionCount, MR1 ; If branch taken, restart
count
MSTOP ; end of task
; This task initializes the ConversionCount
; to zero
;
_Cla1Task8:
MMOVIZ MR0, #0.0
MMOV16 @_ConversionCount, MR0
MSTOP
_ClaT8End:

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MMOV16 MARx, mem16

Load MAR1 with 16-bit Value

Operands MARx CLA auxiliary register MAR0 or MAR1

mem16 16-bit destination memory accessed using one of the available
addressing modes

Opcode
LSW: mmmm mmmm mmmm mmmm (Opcode for MMOV16 MAR0, mem16)
MSW: 0111 0110 0000 addr
LSW: mmmm mmmm mmmm mmmm (Opcode for MMOV16 MAR1, mem16)
MSW: 0111 0110 0100 addr

Description Load MAR0 or MAR1 with the 16-bit value pointed to by mem16. Refer to the Pipeline
section for important information regarding this instruction.

MAR1 = [mem16];

Flags No flags MSTF flags are affected.

Flag TF ZF NF LUF LVF
Modified No No No No No

Pipeline This is a single-cycle instruction. The load of MAR0 or MAR1 occurs in the EXE phase
of the pipeline. Any post increment of MAR0 or MAR1 using indirect addressing occurs in
the D2 phase of the pipeline. Therefore, the following applies when loading the auxiliary
registers:
• I1 and I2
The two instructions following MMOV16 use MAR0 or MAR1 before the update occurs.
Thus, these two instructions use the old value of MAR0 or MAR1.
• I3
Loading of an auxiliary register occurs in the EXE phase while updates due to post-
increment addressing occur in the D2 phase. Thus, I3 cannot use the auxiliary register
or there is a conflict. In the case of a conflict, the update due to address-mode post
increment, the auxiliary register is not updated with #_X.
• I4
Starting with the 4th instruction, MAR0 or MAR1 is the new value loaded with
MMOV16.

; Assume MAR0 is 50 and @_X is 20

MMOV16 MAR0, @_X ; Load MAR0 with the contents of X (20)
<Instruction 1> ; I1 Uses the old value of MAR0 (50)
<Instruction 2> ; I2 Uses the old value of MAR0 (50)
<Instruction 3> ; I3 Cannot use MAR0
<Instruction 4> ; I4 Uses the new value of MAR0 (20)
<Instruction 5> ; I5
....

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MMOV16 MARx, mem16 (continued)

Load MAR1 with 16-bit Value

Table 8-17. Pipeline Activity for MMOV16 MAR0/MAR1, mem16

Instruction F1 F2 D1 D2 R1 R2 E W
MMOV16 MAR0, @_X MMOV16
I1 I1 MMOV16
I2 I2 I1 MMOV16
I3 I3 I2 I1 MMOV16
I4 I4 I3 I2 I1 MMOV16
I5 I5 I4 I3 I2 I1 MMOV16
I6 I6 I5 I4 I3 I2 I1 MMOV16

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MMOV16 MARx, mem16 (continued)

Load MAR1 with 16-bit Value

Example
; This task logs the last NUM_DATA_POINTS
; ADCRESULT1 values in the array VoltageCLA
;
; When the last element in the array has been
; filled, the task goes back to the
; the first element.
;
; Before starting the ADC conversions, force
; Task 8 to initialize the ConversionCount to zero
;
; The ADC is set to sample (acquire) for 15 SYSCLK cycles
; or 75ns. After the capacitor has captured the analog
; value, the ADC triggers this task early.
; It takes 10.5 ADCCLKs to complete a conversion,
; the ADCCLK being SYSCLK/4
; T_sys = 1/200MHz = 5ns
; T_adc = 4*T_sys = 20ns
; The ADC takes 10.5 * 4 or 42 SYSCLK cycles to complete
; a conversion. The ADC result register can be read on the
; 36th instruction after the task begins.
;
_Cla1Task2:
.asg 0, N
.loop
MNOP
;I1 - I28 Wait till I36 to read result
.eval N + 1, N
.break N = 28
.endloop
MMOVZ16 MR0, @_ConversionCount ;I29 Current Conversion
MMOV16 MAR1, MR0, #_VoltageCLA ;I30 Next array location
MUI16TOF32 MR0, MR0 ;I31 Convert count to float32
MADDF32 MR0, MR0, #1.0 ;I32 Add 1 to conversion count
MCMPF32 MR0, #NUM_DATA_POINTS.0 ;I33 Compare count to max
MF32TOUI16 MR0, MR0 ;I34 Convert count to Uint16
MNOP ;I35 Wait until I36 to read
result
MMOVZ16 MR2, @_AdcaResultRegs.ADCRESULT1 ;I36 Read ADCRESULT1
MMOV16 *MAR1, MR2 ; Store ADCRESULT1
MBCNDD _RestartCount, GEQ ; If count >= NUM_DATA_POINTS
MMOVIZ MR1, #0.0 ; Always executed: MR1=0
MNOP
MNOP
MMOV16 @_ConversionCount, MR0 ; If branch not taken
MSTOP ; store current count
_RestartCount
MMOV16 @_ConversionCount, MR1 ; If branch taken, restart
count
MSTOP ; end of task
; This task initializes the ConversionCount
; to zero
;
_Cla1Task8:
MMOVIZ MR0, #0.0
MMOV16 @_ConversionCount, MR0
MSTOP
_ClaT8End:

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MMOV16 mem16, MARx

Move 16-Bit Auxiliary Register Contents to Memory

Operands mem16 16-bit destination memory accessed using one of the available
addressing modes
MARx CLA auxiliary register MAR0 or MAR1

Opcode
LSW: mmmm mmmm mmmm mmmm (Opcode for MMOV16 mem16, MAR0)
MSW: 0111 0110 1000 addr
LSW: mmmm mmmm mmmm mmmm (Opcode for MMOV16 mem16, MAR1)
MSW: 0111 0110 1100 addr

Description Store the contents of MAR0 or MAR1 in the 16-bit memory location pointed to by mem16.

[mem16] = MAR0;

Flags No flags MSTF flags are affected.

Flag TF ZF NF LUF LVF
Modified No No No No No

Pipeline This is a single-cycle instruction.

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MMOV16 mem16, MRa

Move 16-Bit Floating-Point Register Contents to Memory

Operands mem16 16-bit destination memory accessed using one of the available
addressing modes
MRa CLA floating-point source register (MR0 to MR3)

Opcode
LSW: mmmm mmmm mmmm mmmm
MSW: 0111 0101 11aa addr

Description Move 16-bit value from the lower 16-bits of the floating-point register (MRa(15:0)) to the
location pointed to by mem16.

[mem16] = MRa(15:0);

Flags No flags MSTF flags are affected.

Flag TF ZF NF LUF LVF
Modified No No No No No

Pipeline This is a single-cycle instruction.

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MMOV16 mem16, MRa (continued)

Move 16-Bit Floating-Point Register Contents to Memory

Example
; This task logs the last NUM_DATA_POINTS
; ADCRESULT1 values in the array VoltageCLA
;
; When the last element in the array has been
; filled, the task goes back to the
; the first element.
;
; Before starting the ADC conversions, force
; Task 8 to initialize the ConversionCount to zero
;
; The ADC is set to sample (acquire) for 15 SYSCLK cycles
; or 75ns. After the capacitor has captured the analog
; value, the ADC triggers this task early.
; It takes 10.5 ADCCLKs to complete a conversion,
; the ADCCLK being SYSCLK/4
; T_sys = 1/200MHz = 5ns
; T_adc = 4*T_sys = 20ns
; The ADC takes 10.5 * 4 or 42 SYSCLK cycles to complete
; a conversion. The ADC result register can be read on the
; 36th instruction after the task begins.
;
_Cla1Task2:
.asg 0, N
.loop
MNOP
;I1 - I28 Wait till I36 to read result
.eval N + 1, N
.break N = 28
.endloop
MMOVZ16 MR0, @_ConversionCount ;I29 Current Conversion
MMOV16 MAR1, MR0, #_VoltageCLA ;I30 Next array location
MUI16TOF32 MR0, MR0 ;I31 Convert count to float32
MADDF32 MR0, MR0, #1.0 ;I32 Add 1 to conversion count
MCMPF32 MR0, #NUM_DATA_POINTS.0 ;I33 Compare count to max
MF32TOUI16 MR0, MR0 ;I34 Convert count to Uint16
MNOP ;I35 Wait till I36 to read
result
MMOVZ16 MR2, @_AdcaResultRegs.ADCRESULT1 ;I36 Read ADCRESULT1
MMOV16 *MAR1, MR2 ; Store ADCRESULT1
MBCNDD _RestartCount, GEQ ; If count >= NUM_DATA_POINTS
MMOVIZ MR1, #0.0 ; Always executed: MR1=0
MNOP
MNOP
MMOV16 @_ConversionCount, MR0 ; If branch not taken
MSTOP ; store current count
_RestartCount
MMOV16 @_ConversionCount, MR1 ; If branch taken, restart
count
MSTOP ; end of task
; This task initializes the ConversionCount
; to zero
;
_Cla1Task8:
MMOVIZ MR0, #0.0
MMOV16 @_ConversionCount, MR0
MSTOP
_ClaT8End:

See also MMOVIZ MRa, #16FHi

MMOVXI MRa, #16FLoHex

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MMOV32 mem32, MRa

Move 32-Bit Floating-Point Register Contents to Memory

Operands MRa floating-point register (MR0 to MR3)

mem32 32-bit destination memory accessed using one of the available
addressing modes

Opcode
LSW: mmmm mmmm mmmm mmmm
MSW: 0111 0100 11aa addr

Description Move from MRa to 32-bit memory location indicated by mem32.

[mem32] = MRa;

Flags This instruction modifies the following flags in the MSTF register:
Flag TF ZF NF LUF LVF
Modified No No No No No

No flags affected.
Pipeline This is a single-cycle instruction.

Example
; Perform 5 multiply and accumulate operations:
;
; X and Y are 32-bit floating-point arrays;
; 1st multiply: A = X0 * Y0
; 2nd multiply: B = X1 * Y1
; 3rd multiply: C = X2 * Y2
; 4th multiply: D = X3 * Y3
; 5th multiply: E = X3 * Y3;
; Result = A + B + C + D + E
;
_Cla1Task1:
MMOVI16 MAR0, #_X ; MAR0 points to X array
MMOVI16 MAR1, #_Y ; MAR1 points to Y array
MNOP ; Delay for MAR0, MAR1 load
MNOP ; Delay for MAR0, MAR1 load
; <-- MAR0 valid
MMOV32 MR0, *MAR0[2]++ ; MR0 = X0, MAR0 += 2
; <-- MAR1 valid
MMOV32 MR1, *MAR1[2]++ ; MR1 = Y0, MAR1 += 2
MMPYF32 MR2, MR0, MR1 ; MR2 = A = X0 * Y0
|| MMOV32 MR0, *MAR0[2]++ ; In parallel MR0 = X1, MAR0 += 2
MMOV32 MR1, *MAR1[2]++ ; MR1 = Y1, MAR1 += 2
MMPYF32 MR3, MR0, MR1 ; MR3 = B = X1 * Y1
|| MMOV32 MR0, *MAR0[2]++ ; In parallel MR0 = X2, MAR0 += 2
MMOV32 MR1, *MAR1[2]++ ; MR1 = Y2, MAR2 += 2
MMACF32 MR3, MR2, MR2, MR0, MR1 ; MR3 = A + B, MR2 = C = X2 * Y2
|| MMOV32 MR0, *MAR0[2]++ ; In parallel MR0 = X3
MMOV32 MR1, *MAR1[2]++ ; MR1 = Y3
MMACF32 MR3, MR2, MR2, MR0, MR1 ; MR3 = (A + B) + C, MR2 = D = X3 *
Y3
|| MMOV32 MR0, *MAR0 ; In parallel MR0 = X4
MMOV32 MR1, *MAR1 ; MR1 = Y4
MMPYF32 MR2, MR0, MR1 ; MR2 = E = X4 * Y4
|| MADDF32 MR3, MR3, MR2 ; in parallel MR3 = (A + B + C) + D
MADDF32 MR3, MR3, MR2 ; MR3 = (A + B + C + D) + E
MMOV32 @_Result, MR3 ; Store the result MSTOP ; end of task

See also MMOV32 mem32, MSTF

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MMOV32 mem32, MSTF

Move 32-Bit MSTF Register to Memory

Operands MSTF Floating-point status register

mem32 32-bit destination memory

Opcode
LSW: mmmm mmmm mmmm mmmm
MSW: 0111 0111 0100 addr

Description Copy the CLA floating-point status register, MSTF, to memory.

[mem32] = MSTF;

Flags This instruction does not modify flags in the MSTF register:
Flag TF ZF NF LUF LVF
Modified No No No No No

Pipeline This is a single-cycle instruction.

One of the uses of this instruction is to save off the return PC (RPC) prior to calling a
function. The decision to jump to a function is made when the MCCNDD is in the decode2
(D2) phase of the pipeline; the RPC is also updated in this phase. The actual jump occurs
3 cycles later when MCCNDD enters the execution (E) phase. You must save the old RPC
before MCCNDD updates in the D2 phase; that is, save MSTF 3 instructions prior to the
function call.

Example The following example illustrates the pipeline flow for the context save (of the flags and
RPC) prior to a function call. The first column in the comments shows the pipeline stages
for the MMOV32 instruction while the second column pertains to the MCCNDD instruction.

MMOV32 @_temp, MSTF ; D2| |

MNOP ; R1|F1| MCCNDD is fetched
MNOP ; R2|F2|
MNOP ; E |D1|
MCCNDD _bar, UNC ; W |D2| old RPC written to memory,
; | | RPC updated with MPC+1
MNOP ; |R1|
MNOP ; |R2|
MNOP ; |E | execution branches to _bar

See also MMOV32 mem32, MRa

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MMOV32 MRa, mem32 {, CNDF}

Conditional 32-Bit Move

Operands MRa CLA floating-point destination register (MR0 to MR3)

mem32 32-bit memory location accessed using one of the available
addressing modes
CNDF Optional condition

Opcode
LSW: mmmm mmmm mmmm mmmm
MSW: 0111 00cn dfaa addr

Description If the condition is true, then move the 32-bit value referenced by mem32 to the floating-
point register indicated by MRa.

if (CNDF == TRUE) MRa = [mem32];

CNDF is one of the following conditions:

Encode(1) CNDF Description MSTF Flags Tested
0000 NEQ Not equal to zero ZF == 0
0001 EQ Equal to zero ZF == 1
0010 GT Greater than zero ZF == 0 AND NF == 0
0011 GEQ Greater than or equal NF == 0
to zero
0100 LT Less than zero NF == 1
0101 LEQ Less than or equal to ZF == 1 OR NF == 1
zero
1010 TF Test flag set TF == 1
1011 NTF Test flag not set TF == 0
1100 LU Latched underflow LUF == 1
1101 LV Latched overflow LVF == 1
1110 UNC Unconditional None
1111 UNCF(2) Unconditional with flag None
modification

(1) Values not shown are reserved.

(2) This is the default operation, if no CNDF field is specified. This condition
allows the ZF and NF flags to be modified when a conditional operation is
executed. All other conditions do not modify these flags.

Flags This instruction modifies the following flags in the MSTF register:
Flag TF ZF NF LUF LVF
Modified No Yes Yes No No

if(CNDF == UNCF)
{
NF = MRa(31);
ZF = 0;
if(MRa(30:23) == 0) { ZF = 1; NF = 0; }
}
else No flags modified;

Pipeline This is a single-cycle instruction.

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MMOV32 MRa, mem32 {, CNDF} (continued)

Conditional 32-Bit Move

Example
; Given A, B, X, M1 and M2 are 32-bit floating-point numbers
;
; if(A == B) calculate Y = X*M1
; if(A! = B) calculate Y = X*M2
;
_Cla1Task5:
MMOV32 MR0, @_A
MMOV32 MR1, @_B
MCMPF32 MR0, MR1
MMOV32 MR2, @_M1, EQ ; if A == B, MR2 = M1
; Y = M1*X
MMOV32 MR2, @_M2, NEQ ; if A! = B, MR2 = M2
; Y = M2*X
MMOV32 MR3, @_X
MMPYF32 MR3, MR2, MR3 ; Calculate Y
MMOV32 @_Y, MR3 ; Store Y
MSTOP ; end of task

See also MMOV32 MRa, MRb {, CNDF}

MMOVD32 MRa, mem32

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MMOV32 MRa, MRb {, CNDF}

Conditional 32-Bit Move

Operands MRa CLA floating-point destination register (MR0 to MR3)

MRb CLA floating-point source register (MR0 to MR3)
CNDF Optional condition

Opcode
LSW: 0000 0000 cndf bbaa
MSW: 0111 1010 1100 0000

Description If the condition is true, then move the 32-bit value in MRb to the floating-point register
indicated by MRa.

if (CNDF == TRUE) MRa = MRb;

CNDF is one of the following conditions:

Encode(1) CNDF Description MSTF Flags Tested
0000 NEQ Not equal to zero ZF == 0
0001 EQ Equal to zero ZF == 1
0010 GT Greater than zero ZF == 0 AND NF == 0
0011 GEQ Greater than or equal NF == 0
to zero
0100 LT Less than zero NF == 1
0101 LEQ Less than or equal to ZF == 1 OR NF == 1
zero
1010 TF Test flag set TF == 1
1011 NTF Test flag not set TF == 0
1100 LU Latched underflow LUF == 1
1101 LV Latched overflow LVF == 1
1110 UNC Unconditional None
1111 UNCF(2) Unconditional with flag None
modification

(1) Values not shown are reserved.

(2) This is the default operation, if no CNDF field is specified. This condition
allows the ZF, and NF flags to be modified when a conditional operation is
executed. All other conditions do not modify these flags.

Flags This instruction modifies the following flags in the MSTF register:
Flag TF ZF NF LUF LVF
Modified No Yes Yes No No

if(CNDF == UNCF)
{
NF = MRa(31); ZF = 0;
if(MRa(30:23) == 0) {ZF = 1; NF = 0;}
}
else No flags modified;

Pipeline This is a single-cycle instruction.

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MMOV32 MRa, MRb {, CNDF} (continued)

Conditional 32-Bit Move

Example
; Given: X = 8.0
; Y = 7.0
; A = 2.0
; B = 5.0
; _ClaTask1
MMOV32 MR3, @_X ; MR3 = X = 8.0
MMOV32 MR0, @_Y ; MR0 = Y = 7.0
MMAXF32 MR3, MR0 ; ZF = 0, NF = 0, MR3 = 8.0
MMOV32 MR1, @_A, GT ; true, MR1 = A = 2.0
MMOV32 MR1, @_B, LT ; false, does not load MR1
MMOV32 MR2, MR1, GT ; true, MR2 = MR1 = 2.0
MMOV32 MR2, MR0, LT ; false, does not load MR2
MSTOP

See also MMOV32 MRa, mem32 {,CNDF}

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MMOV32 MSTF, mem32

Move 32-Bit Value from Memory to the MSTF Register

Operands MSTF CLA status register

mem32 32-bit source memory location

Opcode
LSW: mmmm mmmm mmmm mmmm
MSW: 0111 0111 0000 addr

Description Move from memory to the CLA's status register MSTF. This instruction is most useful
when nesting function calls (using MCCNDD).

MSTF = [mem32];

Flags This instruction modifies the following flags in the MSTF register:
Flag TF ZF NF LUF LVF
Modified Yes Yes Yes Yes Yes

Loading the status register can overwrite all flags and the RPC field. The MEALLOW field
is not affected.
Pipeline This is a single-cycle instruction.

See also MMOV32 mem32, MSTF

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MMOVD32 MRa, mem32

Move 32-Bit Value from Memory with Data Copy

Operands MRa CLA floating-point register (MR0 to MR3)

mem32 32-bit memory location accessed using one of the available
addressing modes

Opcode
LSW: mmmm mmmm mmmm mmmm
MSW: 0111 0100 00aa addr

Description Move the 32-bit value referenced by mem32 to the floating-point register indicated by
MRa.

MRa = [mem32];
[mem32+2] = [mem32];

Flags This instruction modifies the following flags in the MSTF register:
Flag TF ZF NF LUF LVF
Modified No Yes Yes No No

NF = MRa(31);
ZF = 0;
if(MRa(30:23) == 0){ ZF = 1; NF = 0; }

Pipeline This is a single-cycle instruction.

Example
; sum = X0*B0 + X1*B1 + X2*B2 + Y1*A1 + Y2*B2
;
; X2 = X1
; X1 = X0
; Y2 = Y1
; Y1 = sum
;
_Cla1Task2:
MMOV32 MR0, @_B2 ; MR0 = B2
MMOV32 MR1, @_X2 ; MR1 = X2
MMPYF32 MR2, MR1, MR0 ; MR2 = X2*B2
|| MMOV32 MR0, @_B1 ; MR0 = B1
MMOVD32 MR1, @_X1 ; MR1 = X1, X2 = X1
MMPYF32 MR3, MR1, MR0 ; MR3 = X1*B1
|| MMOV32 MR0, @_B0 ; MR0 = B0
MMOVD32 MR1, @_X0 ; MR1 = X0, X1 = X0
; MR3 = X1*B1 + X2*B2, MR2 = X0*B0
; MR0 = A2
MMACF32 MR3, MR2, MR2, MR1, MR0
|| MMOV32 MR0, @_A2

MMOV32 MR1, @_Y2 ; MR1 = Y2

; MR3 = X0*B0 + X1*B1 + X2*B2, MR2 = Y2*A2
; MR0 = A1
MMACF32 MR3, MR2, MR2, MR1, MR0
|| MMOV32 MR0, @_A1
MMOVD32 MR1,@_Y1 ; MR1 = Y1, Y2 = Y1
MADDF32 MR3, MR3, MR2 ; MR3 = Y2*A2 + X0*B0 + X1*B1 + X2*B2
|| MMPYF32 MR2, MR1, MR0 ; MR2 = Y1*A1
MADDF32 MR3, MR3, MR2 ; MR3 = Y1*A1 + Y2*A2 + X0*B0 + X1*B1 + X2*B2
MMOV32 @_Y1, MR3 ; Y1 = MR3
MSTOP ; end of task

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MMOVD32 MRa, mem32 (continued)

Move 32-Bit Value from Memory with Data Copy

See also MMOV32 MRa, mem32 {,CNDF}

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MMOVF32 MRa, #32F

Load the 32-Bits of a 32-Bit Floating-Point Register

Operands This instruction is an alias for the MMOVIZ and MMOVXI instructions. The second
operand is translated by the assembler such that the instruction becomes:

MMOVIZ MRa, #16FHiHex MMOVXI MRa, #16FLoHex

MRa CLA floating-point destination register (MR0 to MR3)

#32F Immediate float value represented in floating-point representation

Opcode
LSW: IIII IIII IIII IIII (opcode of MMOVIZ MRa, #16FHiHex)
MSW: 0111 1000 0100 00aa
LSW: IIII IIII IIII IIII (opcode of MMOVXI MRa, #16FLoHex)
MSW: 0111 1000 1000 00aa

Description This instruction accepts the immediate operand only in floating-point representation. To
specify the immediate value as a hex value (IEEE 32-bit floating- point format), use the
MOVI32 MRa, #32FHex instruction.
Load the 32-bits of MRa with the immediate float value represented by #32F.
#32F is a float value represented in floating-point representation. The assembler only
accepts a float value represented in floating-point representation. That is, 3.0 can only be
represented as #3.0 (#0x40400000 results in an error).

MRa = #32F;

Flags This instruction modifies the following flags in the MSTF register:
Flag TF ZF NF LUF LVF
Modified No No No No No

Pipeline Depending on #32F, this instruction takes one or two cycles. If all of the lower 16-bits
of the IEEE 32-bit floating-point format of #32F are zeros, then the assembler converts
MMOVF32 into only an MMOVIZ instruction. If the lower 16-bits of the IEEE 32-bit
floating-point format of #32F are not zeros, then the assembler converts MMOVF32 into
MMOVIZ and MMOVXI instructions.

Example
MMOVF32 MR1, #3.0 ; MR1 = 3.0 (0x40400000)
; Assembler converts this instruction as
; MMOVIZ MR1, #0x4040
MMOVF32 MR2, #0.0 ; MR2 = 0.0 (0x00000000)
; Assembler converts this instruction as
; MMOVIZ MR2, #0x0
MMOVF32 MR3, #12.265 ; MR3 = 12.625 (0x41443D71)
; Assembler converts this instruction as
; MMOVIZ MR3, #0x4144
; MMOVXI MR3, #0x3D71

See also MMOVIZ MRa, #16FHi

MMOVXI MRa, #16FLoHex
MMOVI32 MRa, #32FHex

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MMOVI16 MARx, #16I

Load the Auxiliary Register with the 16-Bit Immediate Value

Operands MARx Auxiliary register MAR0 or MAR1

#16I 16-bit immediate value

Opcode
LSW: IIII IIII IIII IIII (opcode of MMOVI16 MAR0, #16I)
MSW: 0111 1111 1100 0000
LSW: IIII IIII IIII IIII (opcode of MMOVI16 MAR1, #16I)
MSW: 0111 1111 1110 0000

Description Load the auxiliary register, MAR0 or MAR1, with a 16-bit immediate value. Refer to the
Pipeline section for important information regarding this instruction.

MARx = #16I;

Flags This instruction does not modify flags in the MSTF register:
Flag TF ZF NF LUF LVF
Modified No No No No No

Pipeline This is a single-cycle instruction. The immediate load of MAR0 or MAR1 occurs in
the EXE phase of the pipeline. Any post increment of MAR0 or MAR1 using indirect
addressing occurs in the D2 phase of the pipeline. Therefore, the following applies when
loading the auxiliary registers:
• I1 and I2
The two instructions following MMOVI16 use MAR0 or MAR1 before the update
occurs. Thus, these two instructions use the old value of MAR0 or MAR1.
• I3
Loading of an auxiliary register occurs in the EXE phase while updates due to post-
increment addressing occur in the D2 phase. Thus, I3 cannot use the auxiliary register
or there is a conflict. In the case of a conflict, the update due to address-mode post
increment, the auxiliary register is not updated with #_X.
• I4
Starting with the 4th instruction, MAR0 or MAR1 is the new value loaded with
MMOVI16.

; Assume MAR0 is 50 and #_X is 20

MMOVI16 MAR0, #_X ; Load MAR0 with address of X (20)
<Instruction 1> ; I1 Uses the old value of MAR0 (50)
<Instruction 2> ; I2 Uses the old value of MAR0 (50)
<Instruction 3> ; I3 Cannot use MAR0
<Instruction 4> ; I4 Uses the new value of MAR0 (20)
<Instruction 5> ; I5
....

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MMOVI16 MARx, #16I (continued)

Load the Auxiliary Register with the 16-Bit Immediate Value

Table 8-18. Pipeline Activity for MMOVI16 MAR0/MAR1, #16I

Instruction F1 F2 D1 D2 R1 R2 E W
MMOVI16 MAR0, #_X MMOVI16
I1 I1 MMOVI16
I2 I2 I1 MMOVI16
I3 I3 I2 I1 MMOVI16
I4 I4 I3 I2 I1 MMOVI16
I5 I5 I4 I3 I2 I1 MMOVI16
I6 I6 I5 I4 I3 I2 I1 MMOVI16

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MMOVI32 MRa, #32FHex

Load the 32-Bits of a 32-Bit Floating-Point Register with the Immediate

Operands MRa Floating-point register (MR0 to MR3)

#32FHex A 32-bit immediate value that represents an IEEE 32-bit floating-
point value.

This instruction is an alias for the MMOVIZ and MMOVXI instructions. The second
operand is translated by the assembler such that the instruction becomes:

MMOVIZ MRa, #16FHiHex

MMOVXI MRa, #16FLoHex

Opcode
LSW: IIII IIII IIII IIII (opcode of MMOVIZ MRa, #16FHiHex)
MSW: 0111 1000 0100 00aa
LSW: IIII IIII IIII IIII (opcode of MMOVXI MRa, #16FLoHex)
MSW: 0111 1000 1000 00aa

Description This instruction only accepts a hex value as the immediate operand. To specify the
immediate value with a floating-point representation, use the MMOVF32 MRa, #32F
instruction.
Load the 32-bits of MRa with the immediate 32-bit hex value represented by #32FHex.
#32FHex is a 32-bit immediate hex value that represents the IEEE 32-bit floating-point
value of a floating-point number. The assembler only accepts a hex immediate value. That
is, 3.0 can only be represented as #0x40400000 (#3.0 results in an error).

MRa = #32FHex;

Flags This instruction modifies the following flags in the MSTF register:
Flag TF ZF NF LUF LVF
Modified No No No No No

Pipeline Depending on #32FHex, this instruction takes one or two cycles. If all of the lower 16-bits
of #32FHex are zeros, then the assembler converts MOVI32 to an MMOVIZ instruction.
If the lower 16-bits of #32FHex are not zeros, then the assembler converts MOVI32 to
MMOVIZ and MMOVXI instructions.

Example
MOVI32 MR1, #0x40400000 ; MR1 = 0x40400000
; Assembler converts this instruction as
; MMOVIZ MR1, #0x4040
MOVI32 MR2, #0x00000000 ; MR2 = 0x00000000
; Assembler converts this instruction as
; MMOVIZ MR2, #0x0
MOVI32 MR3, #0x40004001 ; MR3 = 0x40004001
; Assembler converts this instruction as
; MMOVIZ MR3, #0x4000
; MMOVXI MR3, #0x4001
MOVI32 MR0, #0x00004040 ; MR0 = 0x00004040
; Assembler converts this instruction as
; MMOVIZ MR0, #0x0000
; MMOVXI MR0, #0x4040

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MMOVI32 MRa, #32FHex (continued)

Load the 32-Bits of a 32-Bit Floating-Point Register with the Immediate

See also MMOVIZ MRa, #16FHi

MMOVXI MRa, #16FLoHex
MMOVF32 MRa, #32F

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MMOVIZ MRa, #16FHi

Load the Upper 16-Bits of a 32-Bit Floating-Point Register

Operands MRa Floating-point register (MR0 to MR3)

#16FHi A 16-bit immediate value that represents the upper 16-bits of an
IEEE 32-bit floating-point value. The low 16-bits of the mantissa
are assumed to be all 0.

Opcode
LSW: IIII IIII IIII IIII
MSW: 0111 1000 0100 00aa

Description Load the upper 16-bits of MRa with the immediate value #16FHi and clear the low 16-bits
of MRa.
#16FHi is a 16-bit immediate value that represents the upper 16-bits of an IEEE
32-bit floating-point value. The low 16-bits of the mantissa are assumed to be all 0.
The assembler only accepts a decimal or hex immediate value. That is, -1.5 can be
represented as #-1.5 or #0xBFC0.
By itself, MMOVIZ is useful for loading a floating-point register with a constant in which
the lowest 16-bits of the mantissa are 0. Some examples are 2.0 (0x40000000), 4.0
(0x40800000), 0.5 (0x3F000000), and -1.5 (0xBFC00000). If a constant requires all 32-
bits of a floating-point register to be initialized, then use MMOVIZ along with the MMOVXI
instruction.

MRa(31:16) = #16FHi;
MRa(15:0) = 0;

Flags This instruction modifies the following flags in the MSTF register:
Flag TF ZF NF LUF LVF
Modified No No No No No

Pipeline This is a single-cycle instruction.

Example
; Load MR0 and MR1 with -1.5 (0xBFC00000)
MMOVIZ MR0, #0xBFC0 ; MR0 = 0xBFC00000 (1.5)
MMOVIZ MR1, #-1.5 ; MR1 = -1.5 (0xBFC00000)
; Load MR2 with pi = 3.141593 (0x40490FDB)
MMOVIZ MR2, #0x4049 ; MR2 = 0x40490000
MMOVXI MR2, #0x0FDB ; MR2 = 0x40490FDB

See also MMOVF32 MRa, #32F

MMOVI32 MRa, #32FHex
MMOVXI MRa, #16FLoHex

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MMOVZ16 MRa, mem16

Load MRx with 16-Bit Value

Operands MRa CLA floating-point destination register (MR0 to MR3)

mem16 16-bit source memory location

Opcode
LSW: mmmm mmmm mmmm mmmm
MSW: 0111 0101 10aa addr

Description Move the 16-bit value referenced by mem16 to the floating-point register indicated by
MRa.

MRa(31:16) = 0;
MRa(15:0) = [mem16];

Flags This instruction modifies the following flags in the MSTF register:
Flag TF ZF NF LUF LVF
Modified No Yes Yes No No

The MSTF register flags are modified based on the integer results of the operation.

NF = 0;
if (MRa(31:0)== 0) { ZF = 1; }

Pipeline This is a single-cycle instruction.

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MMOVXI MRa, #16FLoHex

Move Immediate Value to the Lower 16-Bits of a Floating-Point Register

Operands MRa CLA floating-point register (MR0 to MR3)

#16FLoHex A 16-bit immediate hex value that represents the lower 16-bits
of an IEEE 32-bit floating-point value. The upper 16-bits are not
modified.

Opcode
LSW: IIII IIII IIII IIII
MSW: 0111 1000 1000 00aa

Description Load the lower 16-bits of MRa with the immediate value #16FLoHex. #16FLoHex
represents the lower 16-bits of an IEEE 32-bit floating-point value. The upper 16-bits of
MRa are not modified. MMOVXI can be combined with the MMOVIZ instruction to initialize
all 32-bits of a MRa register.

MRa(15:0) = #16FLoHex;
MRa(31:16) = Unchanged;

Flags Flag TF ZF NF LUF LVF

Modified No No No No No

Pipeline This is a single-cycle instruction.

Example
; Load MR0 with pi = 3.141593 (0x40490FDB)
MMOVIZ MR0,#0x4049 ; MR0 = 0x40490000
MMOVXI MR0,#0x0FDB ; MR0 = 0x40490FDB

See also MMOVIZ MRa, #16FHi

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MMPYF32 MRa, MRb, MRc

32-Bit Floating-Point Multiply

Operands MRa CLA floating-point destination register (MR0 to MR3)

MRb CLA floating-point source register (MR0 to MR3)
MRc CLA floating-point source register (MR0 to MR3)

Opcode
LSW: 0000 0000 00cc bbaa
MSW: 0111 1100 0000 0000

Description Multiply the contents of two floating-point registers.

MRa = MRb * MRc;

Flags This instruction modifies the following flags in the MSTF register:
Flag TF ZF NF LUF LVF
Modified No No No Yes Yes

The MSTF register flags are modified as follows:

• LUF = 1 if MMPYF32 generates an underflow condition.
• LVF = 1 if MMPYF32 generates an overflow condition.
Pipeline This is a single-cycle instruction.

Example
; Calculate Num/Den using a Newton-Raphson algorithum for 1/Den
; Ye = Estimate(1/X)
; Ye = Ye*(2.0 - Ye*X)
; Ye = Ye*(2.0 - Ye*X)
;
_Cla1Task1:
MMOV32 MR1, @_Den ; MR1 = Den
MEINVF32 MR2, MR1 ; MR2 = Ye = Estimate(1/Den)
MMPYF32 MR3, MR2, MR1 ; MR3 = Ye*Den
MSUBF32 MR3, #2.0, MR3 ; MR3 = 2.0 - Ye*Den
MMPYF32 MR2, MR2, MR3 ; MR2 = Ye = Ye*(2.0 - Ye*Den)
MMPYF32 MR3, MR2, MR1 ; MR3 = Ye*Den
|| MMOV32 MR0, @_Num ; MR0 = Num
MSUBF32 MR3, #2.0, MR3 ; MR3 = 2.0 - Ye*Den
MMPYF32 MR2, MR2, MR3 ; MR2 = Ye = Ye*(2.0 - Ye*Den)
|| MMOV32 MR1, @_Den ; Reload Den To Set Sign
MNEGF32 MR0, MR0, EQ ; if(Den == 0.0) Change Sign Of Num
MMPYF32 MR0, MR2, MR0 ; MR0 = Y = Ye*Num
MMOV32 @_Dest, MR0 ; Store result
MSTOP ; end of task

See also MMPYF32 MRa, #16FHi, MRb

MMPYF32 MRa, MRb, MRc || MADDF32 MRd, MRe, MRf
MMPYF32 MRd, MRe, MRf || MMOV32 MRa, mem32
MMPYF32 MRd, MRe, MRf || MMOV32 mem32, MRa
MMPYF32 MRa, MRb, MRc || MSUBF32 MRd, MRe, MRf
MMACF32 MR3, MR2, MRd, MRe, MRf || MMOV32 MRa, mem32

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MMPYF32 MRa, #16FHi, MRb

32-Bit Floating-Point Multiply

Operands MRa CLA floating-point destination register (MR0 to MR3)

#16FHi A 16-bit immediate value that represents the upper 16-bits of an
IEEE 32-bit floating-point value. The lower 16-bits of the mantissa
are assumed to be all 0.
MRb CLA floating-point source register (MR0 to MR3)

Opcode
LSW: IIII IIII IIII IIII
MSW: 0111 0111 1000 bbaa

Description Multiply MRb with the floating-point value represented by the immediate operand. Store
the result of the addition in MRa.
#16FHi is a 16-bit immediate value that represents the upper 16-bits of an IEEE 32-bit
floating-point value. The lower 16-bits of the mantissa are assumed to be all 0. #16FHi
is most useful for representing constants where the lowest 16-bits of the mantissa are
0. Some examples are 2.0 (0x40000000), 4.0 (0x40800000), 0.5 (0x3F000000), and -1.5
(0xBFC00000). The assembler accepts either a hex or float as the immediate value. That
is, the value -1.5 can be represented as #-1.5 or #0xBFC0.

MRa = MRb * #16FHi:0;

This instruction can also be written as MMPYF32 MRa, MRb, #16FHi.

Flags This instruction modifies the following flags in the MSTF register:.
Flag TF ZF NF LUF LVF
Modified No No No Yes Yes

The MSTF register flags are modified as follows:

• LUF = 1 if MMPYF32 generates an underflow condition.
• LVF = 1 if MMPYF32 generates an overflow condition.
Pipeline This is a single-cycle instruction.

Example 1
; Same as example 2 but #16FHi is represented in float
MMOVIZ MR3, #2.0 ; MR3 = 2.0 (0x40000000)
MMPYF32 MR0, #3.0, MR3 ; MR0 = 3.0 * MR3 = 6.0 (0x40C00000)
MMOV32 @_X, MR0 ; Save the result in variable X

Example 2
; Same as example 1 but #16FHi is represented in Hex
MMOVIZ MR3, #2.0 ; MR3 = 2.0 (0x40000000)
MMPYF32 MR0, #0x4040, MR3 ; MR0 = 0x4040 * MR3 = 6.0 (0x40C00000)
MMOV32 @_X, MR0 ; Save the result in variable X

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MMPYF32 MRa, #16FHi, MRb (continued)

32-Bit Floating-Point Multiply

Example 3
; Given X, M, and B are IQ24 numbers:
; X = IQ24(+2.5) = 0x02800000
; M = IQ24(+1.5) = 0x01800000
; B = IQ24(-0.5) = 0xFF800000
;
; Calculate Y = X * M + B
;
;
_Cla1Task2:
;
; Convert M, X, and B from IQ24 to float
MI32TOF32 MR0, @_M ; MR0 = 0x4BC00000
MI32TOF32 MR1, @_X ; MR1 = 0x4C200000
MI32TOF32 MR2, @_B ; MR2 = 0xCB000000
MMPYF32 MR0, MR0, #0x3380 ; M = 1/(1*2^24) * iqm = 1.5 (0x3FC00000)
MMPYF32 MR1, MR1, #0x3380 ; X = 1/(1*2^24) * iqx = 2.5 (0x40200000)
MMPYF32 MR2, MR2, #0x3380 ; B = 1/(1*2^24) * iqb = -.5 (0xBF000000)
MMPYF32 MR3, MR0, MR1 ; M*X
MADDF32 MR2, MR2, MR3 ; Y=MX+B = 3.25 (0x40500000)
; Convert Y from float32 to IQ24
MMPYF32 MR2, MR2, #0x4B80 ; Y * 1*2^24
MF32TOI32 MR2, MR2 ; IQ24(Y) = 0x03400000
MMOV32 @_Y, MR2 ; store result
MSTOP ; end of task

See also MMPYF32 MRa, MRb, #16FHi

MMPYF32 MRa, MRb, MRc
MMPYF32 MRa, MRb, MRc || MADDF32 MRd, MRe, MRf

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MMPYF32 MRa, MRb, #16FHi

32-Bit Floating-Point Multiply

Operands MRa CLA floating-point destination register (MR0 to MR3)

MRb CLA floating-point source register (MR0 to MR3)
#16FHi A 16-bit immediate value that represents the upper 16-bits of an
IEEE 32-bit floating-point value. The lower 16-bits of the mantissa
are assumed to be all 0.

Opcode
LSW: IIII IIII IIII IIII
MSW: 0111 0111 1000 bbaa

Description Multiply MRb with the floating-point value represented by the immediate operand. Store
the result of the addition in MRa.
#16FHi is a 16-bit immediate value that represents the upper 16-bits of an IEEE 32-bit
floating-point value. The low 16-bits of the mantissa are assumed to be all 0. #16FHi is
most useful for representing constants where the lowest 16-bits of the mantissa are 0.
Some examples are 2.0 (0x40000000), 4.0 (0x40800000), 0.5 (0x3F000000), and -1.5
(0xBFC00000). The assembler accepts either a hex or float as the immediate value. That
is, the value -1.5 can be represented as #-1.5 or #0xBFC0.

MRa = MRb * #16FHi:0;

This instruction can also be written as MMPYF32 MRa, #16FHi, MRb.

Flags This instruction modifies the following flags in the MSTF register:.
Flag TF ZF NF LUF LVF
Modified No No No Yes Yes

The MSTF register flags are modified as follows:

• LUF = 1 if MMPYF32 generates an underflow condition.
• LVF = 1 if MMPYF32 generates an overflow condition.

Pipeline This is a single-cycle instruction.

Example 1
;Same as example 2 but #16FHi is represented in float
MMOVIZ MR3, #2.0 ; MR3 = 2.0 (0x40000000)
MMPYF32 MR0, MR3, #3.0 ; MR0 = MR3 * 3.0 = 6.0 (0x40C00000)
MMOV32 @_X, MR0 ; Save the result in variable X

Example 2
;Same as example 1 but #16FHi is represented in Hex
MMOVIZ MR3, #2.0 ; MR3 = 2.0 (0x40000000)
MMPYF32 MR0, MR3, #0x4040 ; MR0 = MR3 * 0x4040 = 6.0 (0x40C00000)
MMOV32 @_X, MR0 ; Save the result in variable X

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MMPYF32 MRa, MRb, #16FHi (continued)

32-Bit Floating-Point Multiply

Example 3
; Given X, M, and B are IQ24 numbers:
; X = IQ24(+2.5) = 0x02800000
; M = IQ24(+1.5) = 0x01800000
; B = IQ24(-0.5) = 0xFF800000
;
; Calculate Y = X * M + B
;
_Cla1Task2:
;
; Convert M, X, and B from IQ24 to float
MI32TOF32 MR0, @_M ; MR0 = 0x4BC00000
MI32TOF32 MR1, @_X ; MR1 = 0x4C200000
MI32TOF32 MR2, @_B ; MR2 = 0xCB000000
MMPYF32 MR0, #0x3380, MR0 ; M = 1/(1*2^24) * iqm = 1.5 (0x3FC00000)
MMPYF32 MR1, #0x3380, MR1 ; X = 1/(1*2^24) * iqx = 2.5 (0x40200000)
MMPYF32 MR2, #0x3380, MR2 ; B = 1/(1*2^24) * iqb = -.5 (0xBF000000)
MMPYF32 MR3, MR0, MR1 ; M*X
MADDF32 MR2, MR2, MR3 ; Y=MX+B = 3.25 (0x40500000)
; Convert Y from float32 to IQ24
MMPYF32 MR2, #0x4B80, MR2 ; Y * 1*2^24
MF32TOI32 MR2, MR2 ; IQ24(Y) = 0x03400000
MMOV32 @_Y, MR2 ; store result
MSTOP ; end of task

See also MMPYF32 MRa, #16FHi, MRb

MMPYF32 MRa, MRb, MRc

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MMPYF32 MRa, MRb, MRc||MADDF32 MRd, MRe, MRf

32-Bit Floating-Point Multiply with Parallel Add

Operands MRa CLA floating-point destination register for MMPYF32 (MR0 to MR3)
MRa cannot be the same register as MRd
MRb CLA floating-point source register for MMPYF32 (MR0 to MR3)
MRc CLA floating-point source register for MMPYF32 (MR0 to MR3)
MRd CLA floating-point destination register for MADDF32 (MR0 to MR3)
MRd cannot be the same register as MRa
MRe CLA floating-point source register for MADDF32 (MR0 to MR3)
MRf CLA floating-point source register for MADDF32 (MR0 to MR3)

Opcode
LSW: 0000 ffee ddcc bbaa
MSW: 0111 1010 0000 0000

Description Multiply the contents of two floating-point registers with parallel addition of two registers.

MRa = MRb * MRc;

MRd = MRe + MRf;

Restrictions The destination register for the MMPYF32 and the MADDF32 must be unique. That is,
MRa cannot be the same register as MRd.

Flags This instruction modifies the following flags in the MSTF register:
Flag TF ZF NF LUF LVF
Modified No No No Yes Yes

The MSTF register flags are modified as follows:

• LUF = 1 if MMPYF32 or MADDF32 generates an underflow condition.
• LVF = 1 if MMPYF32 or MADDF32 generates an overflow condition.

Pipeline Both MMPYF32 and MADDF32 complete in a single cycle.

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MMPYF32 MRa, MRb, MRc||MADDF32 MRd, MRe, MRf (continued)

32-Bit Floating-Point Multiply with Parallel Add

Example
; Perform 5 multiply and accumulate operations:
;
; X and Y are 32-bit floating-point arrays
;
; 1st multiply: A = X0 * Y0
; 2nd multiply: B = X1 * Y1
; 3rd multiply: C = X2 * Y2
; 4th multiply: D = X3 * Y3
; 5th multiply: E = X3 * Y3
;
; Result = A + B + C + D + E
;
_Cla1Task1:
MMOVI16 MAR0, #_X ; MAR0 points to X array
MMOVI16 MAR1, #_Y ; MAR1 points to Y array
MNOP ; Delay for MAR0, MAR1 load
MNOP ; Delay for MAR0, MAR1 load
; <-- MAR0 valid
MMOV32 MR0, *MAR0[2]++ ; MR0 = X0, MAR0 += 2
; <-- MAR1 valid
MMOV32 MR1, *MAR1[2]++ ; MR1 = Y0, MAR1 += 2
MMPYF32 MR2, MR0, MR1 ; MR2 = A = X0 * Y0
|| MMOV32 MR0, *MAR0[2]++ ; In parallel MR0 = X1, MAR0 += 2
MMOV32 MR1, *MAR1[2]++ ; MR1 = Y1, MAR1 += 2
MMPYF32 MR3, MR0, MR1 ; MR3 = B = X1 * Y1
|| MMOV32 MR0, *MAR0[2]++ ; In parallel MR0 = X2, MAR0 += 2
MMOV32 MR1, *MAR1[2]++ ; MR1 = Y2, MAR2 += 2
MMACF32 MR3, MR2, MR2, MR0, MR1 ; MR3 = A + B, MR2 = C = X2 * Y2
|| MMOV32 MR0, *MAR0[2]++ ; In parallel MR0 = X3
MMOV32 MR1, *MAR1[2]++ ; MR1 = Y3
MMACF32 MR3, MR2, MR2, MR0, MR1 ; MR3 = (A + B) + C, MR2 = D = X3 * Y3
|| MMOV32 MR0, *MAR0 ; In parallel MR0 = X4
MMOV32 MR1, *MAR1 ; MR1 = Y4
MMPYF32 MR2, MR0, MR1 ; MR2 = E = X4 * Y4
|| MADDF32 MR3, MR3, MR2 ; in parallel MR3 = (A + B + C) + D

MADDF32 MR3, MR3, MR2 ; MR3 = (A + B + C + D) + E

MMOV32 @_Result, MR3 ; Store the result
MSTOP ; end of task

See also MMACF32 MR3, MR2, MRd, MRe, MRf || MMOV32 MRa, mem32

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MMPYF32 MRd, MRe, MRf ||MMOV32 MRa, mem32

32-Bit Floating-Point Multiply with Parallel Move

Operands MRd CLA floating-point destination register for MMPYF32 (MR0 to MR3)
MRd cannot be the same register as MRa
MRe CLA floating-point source register for MMPYF32 (MR0 to MR3)
MRf CLA floating-point source register for MMPYF32 (MR0 to MR3)
MRa CLA floating-point destination register for MMOV32 (MR0 to MR3)
MRa cannot be the same register as MRd
mem32 32-bit memory location accessed using one of the available
addressing modes. This is the source of MMOV32.

Opcode
LSW: mmmm mmmm mmmm mmmm
MSW: 0000 ffee ddaa addr

Description Multiply the contents of two floating-point registers and load another.

MRd = MRe * MRf;

MRa = [mem32];

Restrictions The destination register for the MMPYF32 and the MMOV32 must be unique. That is,
MRa cannot be the same register as MRd.

Flags This instruction modifies the following flags in the MSTF register:.
Flag TF ZF NF LUF LVF
Modified No Yes Yes Yes Yes

The MSTF register flags are modified as follows:

• LUF = 1 if MMPYF32 generates an underflow condition.
• LVF = 1 if MMPYF32 generates an overflow condition.
The MMOV32 instruction sets the NF and ZF flags as follows:

NF = MRa(31);
ZF = 0;
if(MRa(30:23) == 0) { ZF = 1; NF = 0; }

Pipeline Both MMPYF32 and MMOV32 complete in a single cycle.

Example 1
; Given M1, X1, and B1 are 32-bit floating point
; Calculate Y1 = M1*X1+B1
;
_Cla1Task1:
MMOV32 MR0, @M1 ; Load MR0 with M1
MMOV32 MR1, @X1 ; Load MR1 with X1
MMPYF32 MR1, MR1, MR0 ; Multiply M1*X1
|| MMOV32 MR0, @B1 ; and in parallel load MR0 with B1
MADDF32 MR1, MR1, MR0 ; Add M*X1 to B1 and store in MR1
MMOV32 @Y1, MR1 ; Store the result
MSTOP ; end of task

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MMPYF32 MRd, MRe, MRf ||MMOV32 MRa, mem32 (continued)

32-Bit Floating-Point Multiply with Parallel Move

Example 2
; Given A, B, and C are 32-bit floating-point numbers
; Calculate Y2 = (A * B)
; Y3 = (A * B) * C
;
_Cla1Task2:
MMOV32 MR0, @A ; Load MR0 with A
MMOV32 MR1, @B ; Load MR1 with B
MMPYF32 MR1, MR1, MR0 ; Multiply A*B
|| MMOV32 MR0, @C ; and in parallel load MR0 with C
MMPYF32 MR1, MR1, MR0 ; Multiply (A*B) by C
|| MMOV32 @Y2, MR1 ; and in parallel store A*B
MMOV32 @Y3, MR1 ; Store the result
MSTOP ; end of task

See also MMPYF32 MRd, MRe, MRf || MMOV32 mem32, MRa

MMACF32 MR3, MR2, MRd, MRe, MRf || MMOV32 MRa, mem32

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MMPYF32 MRd, MRe, MRf ||MMOV32 mem32, MRa

32-Bit Floating-Point Multiply with Parallel Move

Operands MRd CLA floating-point destination register for MMPYF32 (MR0 to MR3)
MRe CLA floating-point source register for MMPYF32 (MR0 to MR3)
MRf CLA floating-point source register for MMPYF32 (MR0 to MR3)
mem32 32-bit memory location accessed using one of the available
addressing modes. This is the destination of MMOV32.
MRa CLA floating-point source register for MMOV32 (MR0 to MR3)

Opcode
LSW: mmmm mmmm mmmm mmmm
MSW: 0100 ffee ddaa addr

Description Multiply the contents of two floating-point registers and move from memory to register.

MRd = MRe * MRf;

[mem32] = MRa;

Flags This instruction modifies the following flags in the MSTF register:
Flag TF ZF NF LUF LVF
Modified No No No Yes Yes

The MSTF register flags are modified as follows:

• LUF = 1 if MMPYF32 generates an underflow condition.
• LVF = 1 if MMPYF32 generates an overflow condition.

Pipeline MMPYF32 and MMOV32 both complete in a single cycle.

Example
; Given A, B, and C are 32-bit floating-point numbers
; Calculate Y2 = (A * B)
; Y3 = (A * B) * C
;
_Cla1Task2:
MMOV32 MR0, @A ; Load MR0 with A
MMOV32 MR1, @B ; Load MR1 with B
MMPYF32 MR1, MR1, MR0 ; Multiply A*B
|| MMOV32 MR0, @C ; and in parallel load MR0 with C
MMPYF32 MR1, MR1, MR0 ; Multiply (A*B) by C
|| MMOV32 @Y2, MR1 ; and in parallel store A*B
MMOV32 @Y3, MR1 ; Store the result
MSTOP ; end of task

See also MMPYF32 MRd, MRe, MRf || MMOV32 MRa, mem32

MMACF32 MR3, MR2, MRd, MRe, MRf || MMOV32 MRa, mem32

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MMPYF32 MRa, MRb, MRc ||MSUBF32 MRd, MRe, MRf

32-Bit Floating-Point Multiply with Parallel Subtract

Operands MRa CLA floating-point destination register for MMPYF32 (MR0 to MR3)
MRa cannot be the same register as MRd
MRb CLA floating-point source register for MMPYF32 (MR0 to MR3)
MRc CLA floating-point source register for MMPYF32 (MR0 to MR3)
MRd CLA floating-point destination register for MSUBF32 (MR0 to MR3)
MRd cannot be the same register as MRa
MRe CLA floating-point source register for MSUBF32 (MR0 to MR3)
MRf CLA floating-point source register for MSUBF32 (MR0 to MR3)

Opcode
LSW: 0000 ffee ddcc bbaa
MSW: 0111 1010 0100 0000

Description Multiply the contents of two floating-point registers with parallel subtraction of two
registers.

MRa = MRb * MRc;

MRd = MRe - MRf;

Restrictions The destination register for the MMPYF32 and the MSUBF32 must be unique. That is,
MRa cannot be the same register as MRd.

Flags This instruction modifies the following flags in the MSTF register:.
Flag TF ZF NF LUF LVF
Modified No No No Yes Yes

The MSTF register flags are modified as follows:

• LUF = 1 if MMPYF32 or MSUBF32 generates an underflow condition.
• LVF = 1 if MMPYF32 or MSUBF32 generates an overflow condition.

Pipeline MMPYF32 and MSUBF32 both complete in a single cycle.

Example
; Given A, B, and C are 32-bit floating-point numbers
; Calculate Y2 = (A * B)
; Y3 = (A - B)
;
_Cla1Task2:
MMOV32 MR0, @A ; Load MR0 with A
MMOV32 MR1, @B ; Load MR1 with B
MMPYF32 MR2, MR0, MR1 ; Multiply (A*B)
|| MSUBF32 MR3, MR0, MR1 ; and in parallel Sub (A-B)
MMOV32 @Y2, MR2 ; Store A*B
MMOV32 @Y3, MR3 ; Store A-B
MSTOP ; end of task

See also MSUBF32 MRa, MRb, MRc

MSUBF32 MRd, MRe, MRf || MMOV32 MRa, mem32
MSUBF32 MRd, MRe, MRf || MMOV32 mem32, MRa

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MNEGF32 MRa, MRb{, CNDF}

Conditional Negation

Operands MRa CLA floating-point destination register (MR0 to MR3)

MRb CLA floating-point source register (MR0 to MR3)
CNDF Condition tested

Opcode
LSW: 0000 0000 cndf bbaa
MSW: 0111 1010 1000 0000

Description
if (CNDF == true) {MRa = - MRb; }
else {MRa = MRb; }

CNDF is one of the following conditions:

Encode(1) CNDF Description MSTF Flags Tested
0000 NEQ Not equal to zero ZF == 0
0001 EQ Equal to zero ZF == 1
0010 GT Greater than zero ZF == 0 AND NF == 0
0011 GEQ Greater than or equal NF == 0
to zero
0100 LT Less than zero NF == 1
0101 LEQ Less than or equal to ZF == 1 OR NF == 1
zero
1010 TF Test flag set TF == 1
1011 NTF Test flag not set TF == 0
1100 LU Latched underflow LUF == 1
1101 LV Latched overflow LVF == 1
1110 UNC Unconditional None
1111 UNCF(2) Unconditional with flag None
modification

(1) Values not shown are reserved.

(2) This is the default operation, if no CNDF field is specified. This condition
allows the ZF, and NF flags to be modified when a conditional operation is
executed. All other conditions do not modify these flags.

Flags This instruction modifies the following flags in the MSTF register:
Flag TF ZF NF LUF LVF
Modified No Yes Yes No No

Pipeline This is a single-cycle instruction.

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MNEGF32 MRa, MRb{, CNDF} (continued)

Conditional Negation

Example 1
; Show the basic operation of MNEGF32
;
MMOVIZ MR0, #5.0 ; MR0 = 5.0 (0x40A00000)
MMOVIZ MR1, #4.0 ; MR1 = 4.0 (0x40800000)
MMOVIZ MR2, #-1.5 ; MR2 = -1.5 (0xBFC00000)
MMPYF32 MR3, MR1, MR2 ; MR3 = -6.0
MMPYF32 MR0, MR0, MR1 ; MR0 = 20.0
MMOVIZ MR1, #0.0
MCMPF32 MR3, MR1 ; NF = 1
MNEGF32 MR3, MR3, LT ; if NF = 1, MR3 = 6.0
MCMPF32 MR0, MR1 ; NF = 0
MNEGF32 MR0, MR0, GEQ ; if NF = 0, MR0 = -20.0

Example 2
; Calculate Num/Den using a Newton-Raphson algorithum for 1/Den
; Ye = Estimate(1/X)
; Ye = Ye*(2.0 - Ye*X)
; Ye = Ye*(2.0 - Ye*X)
;
_Cla1Task1:
MMOV32 MR1, @_Den ; MR1 = Den
MEINVF32 MR2, MR1 ; MR2 = Ye = Estimate(1/Den)
MMPYF32 MR3, MR2, MR1 ; MR3 = Ye*Den
MSUBF32 MR3, #2.0, MR3 ; MR3 = 2.0 - Ye*Den
MMPYF32 MR2, MR2, MR3 ; MR2 = Ye = Ye*(2.0 - Ye*Den)
MMPYF32 MR3, MR2, MR1 ; MR3 = Ye*Den
|| MMOV32 MR0, @_Num ; MR0 = Num
MSUBF32 MR3, #2.0, MR3 ; MR3 = 2.0 - Ye*Den
MMPYF32 MR2, MR2, MR3 ; MR2 = Ye = Ye*(2.0 - Ye*Den)
|| MMOV32 MR1, @_Den ; Reload Den To Set Sign
MNEGF32 MR0, MR0, EQ ; if(Den == 0.0) Change Sign Of Num
MMPYF32 MR0, MR2, MR0 ; MR0 = Y = Ye*Num
MMOV32 @_Dest, MR0 ; Store result
MSTOP ; end of task

See also MABSF32 MRa, MRb

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MNOP

No Operation

Operands none This instruction does not have any operands

Opcode
LSW: 0000 0000 0000 0000
MSW: 0111 1111 1010 0000

Description Do nothing. This instruction is used to fill required pipeline delay slots when other
instructions are not available to fill the slots.
Flags This instruction does not modify flags in the MSTF register.
Flag TF ZF NF LUF LVF
Modified No No No No No

Pipeline This is a single-cycle instruction.

Example
; X is an array of 32-bit floating-point values
; Find the maximum value in an array X
; and store the value in Result
;
_Cla1Task1:
MMOVI16 MAR1,#_X ; Start address
MUI16TOF32 MR0, @_len ; Length of the array
MNOP ; delay for MAR1 load
MNOP ; delay for MAR1 load
MMOV32 MR1, *MAR1[2]++ ; MR1 = X0
LOOP
MMOV32 MR2, *MAR1[2]++ ; MR2 = next element
MMAXF32 MR1, MR2 ; MR1 = MAX(MR1, MR2)
MADDF32 MR0, MR0, #-1.0 ; Decrememt the counter
MCMPF32 MR0 #0.0 ; Set/clear flags for MBCNDD
MNOP ; Too late to affect MBCNDD
MNOP ; Too late to affect MBCNDD
MNOP ; Too late to affect MBCNDD
MBCNDD LOOP, NEQ ; Branch if not equal to zero
MMOV32 @_Result, MR1 ; Always executed
MNOP ; Pad to seperate MBCNDD and MSTOP
MNOP ; Pad to seperate MBCNDD and MSTOP
MSTOP ; End of task

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MOR32 MRa, MRb, MRc

Bitwise OR

Operands MRa CLA floating-point destination register (MR0 to MR3)

MRb CLA floating-point source register (MR0 to MR3)
MRc CLA floating-point source register (MR0 to MR3)

Opcode
LSW: 0000 0000 00cc bbaa
MSW: 0111 1100 1000 0000

Description Bitwise OR of MRb with MRc.

MARa(31:0) = MARb(31:0) OR MRc(31:0);

Flags This instruction modifies the following flags in the MSTF register:
Flag TF ZF NF LUF LVF
Modified No Yes Yes No No

The MSTF register flags are modified based on the integer results of the operation.

NF = MRa(31);
ZF = 0;
if(MRa(31:0) == 0) { ZF = 1; }

Pipeline This is a single-cycle instruction.

Example
MMOVIZ MR0,
#0x5555 ; MR0 = 0x5555AAAA
MMOVXI MR0,
#0xAAAA
MMOVIZ MR1,
#0x5432 ; MR1 = 0x5432FEDC
MMOVXI MR1,
#0xFEDC
; 0101 OR 0101 = 0101 (5)
; 0101 OR 0100 = 0101 (5)
; 0101 OR 0011 = 0111 (7)
; 0101 OR 0010 = 0111 (7)
; 1010 OR 1111 = 1111 (F)
; 1010 OR 1110 = 1110 (E)
; 1010 OR 1101 = 1111 (F)
; 1010 OR 1100 = 1110 (E)
MOR32 MR2, MR1, MR0 ; MR3 = 0x5555FEFE

See also MAND32 MRa, MRb, MRc

MXOR32 MRa, MRb, MRc

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MRCNDD {CNDF}

Return Conditional Delayed

Operands CNDF Optional condition

Opcode
LSW: 0000 0000 0000 0000
MSW: 0111 1001 1010 cndf

Description If the specified condition is true, then the RPC field of MSTF is loaded into MPC and
fetching continues from that location. Otherwise, program fetches continue without the
return.
Refer to the Pipeline section for important information regarding this instruction.

if (CNDF == TRUE) MPC = RPC;

CNDF is one of the following conditions:

Encode(1) CNDF Description MSTF Flags Tested
0000 NEQ Not equal to zero ZF == 0
0001 EQ Equal to zero ZF == 1
0010 GT Greater than zero ZF == 0 AND NF == 0
0011 GEQ Greater than or equal NF == 0
to zero
0100 LT Less than zero NF == 1
0101 LEQ Less than or equal to ZF == 1 OR NF == 1
zero
1010 TF Test flag set TF == 1
1011 NTF Test flag not set TF == 0
1100 LU Latched underflow LUF == 1
1101 LV Latched overflow LVF == 1
1110 UNC Unconditional None
1111 UNCF(2) Unconditional with flag None
modification

(1) Values not shown are reserved.

(2) This is the default operation, if no CNDF field is specified. This condition
allows the ZF and NF flags to be modified when a conditional operation is
executed. All other conditions do not modify these flags.

Flags This instruction does not modify flags in the MSTF register.
Flag TF ZF NF LUF LVF
Modified No No No No No

Pipeline The MRCNDD instruction by itself is a single-cycle instruction. As shown in Table 8-19, 6
instruction slots are executed for each return; 3 slots before the return instruction (d5-d7)
and 3 slots after the return instruction (d8-d10). The total number of cycles for a return
taken or not taken depends on the usage of these slots. That is, the number of cycles
depends on how many slots are filled with a MNOP as well as which slots are filled.
The effective number of cycles for a return can, therefore, range from 1 to 7 cycles. The
number of cycles for a return taken cannot be the same as for a return not taken.

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MRCNDD {CNDF} (continued)

Return Conditional Delayed

Referring to the following code fragment and the pipeline diagrams in Table 8-19 and
Table 8-20, the instructions before and after MRCNDD have the following properties:

;
;
<Instruction 1> ; I1 Last instruction that can affect flags for
; the MCCNDD operation
<Instruction 2> ; I2 Cannot be stop, branch, call or return
<Instruction 3> ; I3 Cannot be stop, branch, call or return
<Instruction 4> ; I4 Cannot be stop, branch, call or return
MCCNDD _func, NEQ ; Call to func if not eqal to zero
; Three instructions after MCCNDD are always
; executed whether the call is taken or not
<Instruction 5> ; I5 Cannot be stop, branch, call or return
<Instruction 6> ; I6 Cannot be stop, branch, call or return
<Instruction 7> ; I7 Cannot be stop, branch, call or return
<Instruction 8> ; I8 The address of this instruction is saved
; in the RPC field of the MSTF register.
; Upon return this value is loaded into MPC
; and fetching continues from this point.
<Instruction 9> ; I9
<Instruction 10> ; I10
....
....
_func:
<Destination 1> ; d1 Can be any instruction
<Destination 2> ; d2
<Destination 3> ; d3
<Destination 4> ; d4 Last instruction that can affect flags for
; the MRCNDD operation
<Destination 5> ; d5 Cannot be stop, branch, call or return
<Destination 6> ; d6 Cannot be stop, branch, call or return
<Destination 7> ; d7 Cannot be stop, branch, call or return
MRCNDD NEQ ; Return to <Instruction 8> if not equal to zero
; Three instructions after MRCNDD are always
; executed whether the return is taken or not
<Destination 8> ; d8 Cannot be stop, branch, call or return
<Destination 9> ; d9 Cannot be stop, branch, call or return
<Destination 10> ; d10 Cannot be stop, branch, call or return
<Destination 11> ; d11
<Destination 12> ; d12
....
....
MSTOP
....

• d4
– d4 is the last instruction that can effect the CNDF flags for the MRCNDD instruction.
The CNDF flags are tested in the D2 phase of the pipeline. That is, a decision is
made whether to return or not when MRCNDD is in the D2 phase.
– There are no restrictions on the type of instruction for d4.
• d5, d6, and d7
– The three instructions proceeding MRCNDD can change MSTF flags but have no
effect on whether the MRCNDD instruction makes the return or not. This is because
the flag modification occurs after the D2 phase of the MRCNDD instruction.
– These instructions must not be the following: MSTOP, MDEBUGSTOP, MBCNDD,
MCCNDD, or MRCNDD.
• d8, d9, and d10
– The three instructions following MRCNDD are always executed irrespective of
whether the return is taken or not.
– These instructions must not be the following: MSTOP, MDEBUGSTOP, MBCNDD,
MCCNDD, or MRCNDD.

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MRCNDD {CNDF} (continued)

Return Conditional Delayed

Table 8-19. Pipeline Activity for MRCNDD, Return Not Taken

Instruction F1 F2 D1 D2 R1 R2 E W
d4 d4 d3 d2 d1 I7 I6 I5
d5 d5 d4 d3 d2 d1 I7 I6
d6 d6 d5 d4 d3 d2 d1 i7
d7 d7 d6 d5 d4 d3 d2 d1
MRCNDD MRCNDD d7 d6 d5 d4 d3 d2
d8 d8 MRCNDD d7 d6 d5 d4 d3
d9 d9 d8 MRCNDD d7 d6 d5 d4
d10 d10 d9 d8 MRCNDD d7 d6 d5
d11 d11 d10 d9 d8 - d7 d6
d12 d12 d11 d10 d9 d8 - d7
etc.... .... d12 d11 d10 d9 d8 -
.... .... .... d12 d11 d10 d9 d8
.... .... .... .... d12 d11 d10 d9
d12 d11 d10
d12 d11
d12

Table 8-20. Pipeline Activity for MRCNDD, Return Taken

Instruction F1 F2 D1 D2 R1 R2 E W
d4 d4 d3 d2 d1 I7 I6 I5
d5 d5 d4 d3 d2 d1 I7 I6
d6 d6 d5 d4 d3 d2 d1 i7
d7 d7 d6 d5 d4 d3 d2 d1
MRCNDD MRCNDD d7 d6 d5 d4 d3 d2
d8 d8 MRCNDD d7 d6 d5 d4 d3
d9 d9 d8 MRCNDD d7 d6 d5 d4
d10 d10 d9 d8 MRCNDD d7 d6 d5
I8 I8 d10 d9 d8 - d7 d6
I9 I9 I8 d10 d9 d8 - d7
I10 I10 I9 I8 d10 d9 d8 -
etc.... .... I10 I9 I8 d10 d9 d8
.... .... I10 I9 I8 d10 d9
.... .... I10 I9 I8 d10
I10 I9 I8
I10 I9
I10

See also MBCNDD #16BitDest, CNDF

MCCNDD 16BitDest, CNDF
MMOV32 mem32, MSTF
MMOV32 MSTF, mem32

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MSETC BGINTM

Set Background Task Interrupt Mask

Operands none This instruction does not have any operands

Opcode
LSW: 0000 0000 0000 0000
MSW: 0111 1111 0101 0000

Description This instruction sets the background task interrupt mask (BGINTM) bit in the
MSTSBGRND register, making any code thereafter uninterruptible. No other higher
priority task is able to interrupt the background task until the BGINTM is cleared. This
instruction sets the BGINTM bit at the end of the D2 phase.
This instruction does not require the MEALLOW bit to be asserted before, or de-asserted
after, setting BGINTM.

Flags This instruction does not modify the following flags in the MSTF register:
Flag TF ZF NF LUF LVF
Modified No No No No No

Pipeline This is a single-cycle instruction.

Example
MSETC BGINTM ; Set the MSTSBGRND.BGINTM bit
; to prevent any other tasks from
; interrupting the background task

See also MCLRC BGINTM

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MSETFLG FLAG, VALUE

Set or Clear Selected Floating-Point Status Flags

Operands FLAG 8-bit mask indicating which floating-point status flags to change.
VALUE 8-bit mask indicating the flag value: 0 or 1.

Opcode
LSW: FFFF FFFF VVVV VVVV
MSW: 0111 1001 1100 0000

Description The MSETFLG instruction is used to set or clear selected floating-point status flags in the
MSTF register. The FLAG field is an 11-bit value that indicates which flags are changed.
That is, if a FLAG bit is set to 1, that flag is changed; all other flags are not modified. The
bit mapping of the FLAG field is:
9 8 7 6 5 4 3 2 1 0
RNDF Reserved TF Reserved ZF NF LUF LVF
32

The VALUE field indicates the value the flag can be set to: 0 or 1.

Flags This instruction modifies the following flags in the MSTF register:
Flag TF ZF NF LUF LVF
Modified Yes Yes Yes Yes Yes

Any flag can be modified by this instruction. The MEALLOW and RPC fields cannot be
modified with this instruction.

Pipeline This is a single-cycle instruction.

Example To make it easier and legible, the assembler accepts a FLAG=VALUE syntax for the
MSTFLG operation as:

MSETFLG RNDF32=0, TF=0, NF=1; FLAG = 11000100; VALUE = 00XXX1XX;

See also MMOV32 mem32, MSTF

MMOV32 MSTF, mem32

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MSTOP

Stop Task

Operands none This instruction does not have any operands

Opcode
LSW: 0000 0000 0000 0000
MSW: 0111 1111 1000 0000

Description The MSTOP instruction must be placed to indicate the end of each task. In addition,
placing MSTOP in unused memory locations within the CLA program RAM can be useful
for debugging and preventing run away CLA code. When MSTOP enters the D2 phase of
the pipeline, the MIRUN flag for the task is cleared and the associated interrupt is flagged
in the PIE vector table.
There are three special cases that can occur when single-stepping a task such that the
MPC reaches the MSTOP instruction.
1. If you are single-stepping or halted in "task A" and "task B" comes in before the MPC
reaches the MSTOP, then "task B" starts if you continue to step through the MSTOP
instruction. Basically, if "task B" is pending before the MPC reaches MSTOP in "task
A" then there is no issue in "task B" starting and no special action is required.
2. In this case, you have single-stepped or halted in "task A" and the MPC has reached
the MSTOP with no tasks pending. If "task B" comes in at this point, "task B" is
flagged in the MIFR register but "task B" can or cannot start if you continue to
single-step through the MSTOP instruction of "task A". It depends on exactly when the
new task comes in. To reliably start "task B", perform a soft reset and reconfigure the
MIER bits. Once this is done, you can start single-stepping "task B".
3. Case 2 can be handled slightly differently if there is control over when "task B" comes
in (for example using the IACK instruction to start the task). In this case you have
single-stepped or halted in "task A" and the MPC has reached the MSTOP with no
tasks pending. Before forcing "task B", run free to force the CLA out of the debug
state. Once this is done you can force "task B" and continue debugging.

Restrictions The MSTOP instruction cannot be placed 3 instructions before or after a MBCNDD,
MCCNDD, or MRCNDD instruction.

Flags This instruction does not modify flags in the MSTF register.
Flag TF ZF NF LUF LVF
Modified No No No No No

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MSTOP (continued)

Stop Task

Pipeline This is a single-cycle instruction. Table 8-21 shows the pipeline behavior of the MSTOP
instruction. The MSTOP instruction cannot be placed with 3 instructions of a MBCNDD,
MCCNDD, or MRCNDD instruction.
Table 8-21. Pipeline Activity for MSTOP
Instruction F1 F2 D1 D2 R1 R2 E W
I1 I1
I2 I2 I1
I3 I3 I2 I1
MSTOP MSTOP I3 I2 I1
I4 I4 MSTOP I3 I2 I1
I5 I5 I4 MSTOP I3 I2 I1
I6 I6 I5 I4 MSTOP I3 I2 I1
New Task Arbitrated and
- - - - - I3 I2
Prioritized
New Task Arbitrated and
- - - - - - I3
Prioritized
I1 I1 - - - - - -
I2 I2 I1 - - - - -
I3 I3 I2 I1 - - - -
I4 I4 I3 I2 I1 - - -
I5 I5 I4 I3 I2 I1 - -
I6 I6 I5 I4 I3 I2 I1 -
I7 I7 I6 I5 I4 I3 I2 I1
....

Example
; Given A = (int32)1
; B = (int32)2
; C = (int32)-7
;
; Calculate Y2 = A - B - C
_Cla1Task3:
MMOV32 MR0, @_A ; MR0 = 1 (0x00000001)
MMOV32 MR1, @_B ; MR1 = 2 (0x00000002)
MMOV32 MR2, @_C ; MR2 = -7 (0xFFFFFFF9)
MSUB32 MR3, MR0, MR1 ; A + B
MSUB32 MR3, MR3, MR2 ; A + B + C = 6 (0x0000006)
MMOV32 @_y2, MR3 ; Store y2
MSTOP ; End of task

See also MDEBUGSTOP , MDEBUGSTOP1

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MSUB32 MRa, MRb, MRc

32-Bit Integer Subtraction

Operands MRa CLA floating-point destination register (MR0 to MR3)

MRb CLA floating-point destination register (MR0 to MR3)
MRc CLA floating-point destination register (MR0 to MR3)

Opcode
LSW: 0000 0000 00cc bbaa
MSW: 0111 1100 1110 0000

Description 32-bit integer addition of MRb and MRc.

MARa(31:0) = MARb(31:0) - MRc(31:0);

Flags This instruction modifies the following flags in the MSTF register:
Flag TF ZF NF LUF LVF
Modified No Yes Yes No No

The MSTF register flags are modified as follows:

NF = MRa(31);
ZF = 0;
if(MRa(31:0) == 0) { ZF = 1; }

Pipeline This is a single-cycle instruction.

Example
; Given A = (int32)1
; B = (int32)2
; C = (int32)-7
;
;
Calculate Y2 = A - B - C
;
_Cla1Task3:
MMOV32 MR0, @_A ; MR0 = 1 (0x00000001)
MMOV32 MR1, @_B ; MR1 = 2 (0x00000002)
MMOV32 MR2, @_C ; MR2 = -7 (0xFFFFFFF9)
MSUB32 MR3, MR0, MR1 ; A + B
MSUB32 MR3, MR3, MR2 ; A + B + C = 6 (0x0000006)
MMOV32 @_y2, MR3 ; Store y2
MSTOP ; End of task

See also MADD32 MRa, MRb, MRc

MAND32 MRa, MRb, MRc
MASR32 MRa, #SHIFT
MLSL32 MRa, #SHIFT
MLSR32 MRa, #SHIFT
MOR32 MRa, MRb, MRc
MXOR32 MRa, MRb, MRc

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MSUBF32 MRa, MRb, MRc

32-Bit Floating-Point Subtraction

Operands MRa CLA floating-point destination register (MR0 to R1)

MRb CLA floating-point source register (MR0 to R1)
MRc CLA floating-point source register (MR0 to R1)

Opcode
LSW: 0000 0000 00cc bbaa
MSW: 0111 1100 0100 0000

Description Subtract the contents of two floating-point registers

MRa = MRb - MRc;

Flags This instruction modifies the following flags in the MSTF register:
Flag TF ZF NF LUF LVF
Modified No No No Yes Yes

The MSTF register flags are modified as follows:

• LUF = 1 if MSUBF32 generates an underflow condition.
• LVF = 1 if MSUBF32 generates an overflow condition.
Pipeline This is a single-cycle instruction.

Example
; Given A, B, and C are 32-bit floating-point numbers
; Calculate Y2 = A + B - C
;
_Cla1Task5:
MMOV32 MR0, @_A ; Load MR0 with A
MMOV32 MR1, @_B ; Load MR1 with B
MADDF32 MR0, MR1, MR0 ; Add A + B
|| MMOV32 MR1, @_C ; and in parallel load C
MSUBF32 MR0, MR0, MR1 ; Subtract C from (A + B)
MMOV32 @Y, MR0 ; (A+B) - C
MSTOP ; end of task

See also MSUBF32 MRa, #16FHi, MRb

MSUBF32 MRd, MRe, MRf || MMOV32 MRa, mem32
MSUBF32 MRd, MRe, MRf || MMOV32 mem32, MRa
MMPYF32 MRa, MRb, MRc || MSUBF32 MRd, MRe, MRf

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MSUBF32 MRa, #16FHi, MRb

32-Bit Floating-Point Subtraction

Operands MRa CLA floating-point destination register (MR0 to R1)

#16FHi A 16-bit immediate value that represents the upper 16-bits of an
IEEE 32-bit floating-point value. The lower 16-bits of the mantissa
are assumed to be all 0.
MRb CLA floating-point source register (MR0 to R1)

Opcode
LSW: IIII IIII IIII IIII
MSW: 0111 1000 0000 baaa

Description Subtract MRb from the floating-point value represented by the immediate operand. Store
the result of the addition in MRa.
#16FHi is a 16-bit immediate value that represents the upper 16-bits of an IEEE 32-bit
floating-point value. The lower 16-bits of the mantissa are assumed to be all 0. #16FHi
is most useful for representing constants where the lowest 16-bits of the mantissa are
0. Some examples are 2.0 (0x40000000), 4.0 (0x40800000), 0.5 (0x3F000000), and -1.5
(0xBFC00000). The assembler accepts either a hex or float as the immediate value. That
is, the value -1.5 can be represented as #-1.5 or #0xBFC0.

MRa = #16FHi:0 - MRb;

Flags This instruction modifies the following flags in the MSTF register:
Flag TF ZF NF LUF LVF
Modified No No No Yes Yes

The MSTF register flags are modified as follows:

• LUF = 1 if MSUBF32 generates an underflow condition.
• LVF = 1 if MSUBF32 generates an overflow condition.
Pipeline This is a single-cycle instruction.

Example
; Y = sqrt(X)
; Ye = Estimate(1/sqrt(X));
; Ye = Ye*(1.5 - Ye*Ye*X*0.5)
; Ye = Ye*(1.5 - Ye*Ye*X*0.5)
; Y = X*Ye
;
_Cla1Task3:
MMOV32 MR0, @_x ; MR0 = X
MEISQRTF32 MR1, MR0 ; MR1 = Ye = Estimate(1/sqrt(X))
MMOV32 MR1, @_x, EQ ; if(X == 0.0) Ye = 0.0
MMPYF32 MR3, MR0, #0.5 ; MR3 = X*0.5
MMPYF32 MR2, MR1, MR3 ; MR2 = Ye*X*0.5
MMPYF32 MR2, MR1, MR2 ; MR2 = Ye*Ye*X*0.5
MSUBF32 MR2, #1.5, MR2 ; MR2 = 1.5 - Ye*Ye*X*0.5
MMPYF32 MR1, MR1, MR2 ; MR1 = Ye = Ye*(1.5 - Ye*Ye*X*0.5)
MMPYF32 MR2, MR1, MR3 ; MR2 = Ye*X*0.5
MMPYF32 MR2, MR1, MR2 ; MR2 = Ye*Ye*X*0.5
MSUBF32 MR2, #1.5, MR2 ; MR2 = 1.5 - Ye*Ye*X*0.5
MMPYF32 MR1, MR1, MR2 ; MR1 = Ye = Ye*(1.5 - Ye*Ye*X*0.5)
MMPYF32 MR0, MR1, MR0 ; MR0 = Y = Ye*X
MMOV32 @_y, MR0 ; Store Y = sqrt(X)
MSTOP ; end of task

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MSUBF32 MRa, #16FHi, MRb (continued)

32-Bit Floating-Point Subtraction

See also MSUBF32 MRa, MRb, MRc

MSUBF32 MRd, MRe, MRf || MMOV32 MRa, mem32
MSUBF32 MRd, MRe, MRf || MMOV32 mem32, MRa
MMPYF32 MRa, MRb, MRc || MSUBF32 MRd, MRe, MRf

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MSUBF32 MRd, MRe, MRf ||MMOV32 MRa, mem32

32-Bit Floating-Point Subtraction with Parallel Move

Operands MRd CLA floating-point destination register (MR0 to MR3) for the
MSUBF32 operation
MRd cannot be the same register as MRa
MRe CLA floating-point source register (MR0 to MR3) for the MSUBF32
operation
MRf CLA floating-point source register (MR0 to MR3) for the MSUBF32
operation
MRa CLA floating-point destination register (MR0 to MR3) for the
MMOV32 operation
MRa cannot be the same register as MRd
mem32 32-bit memory location accessed using one of the available
addressing modes. Source for the MMOV32 operation.

Opcode
LSW: mmmm mmmm mmmm mmmm
MSW: 0010 ffee ddaa addr

Description Subtract the contents of two floating-point registers and move from memory to a floating-
point register.

MRd = MRe - MRf;

MRa = [mem32];

Restrictions The destination register for the MSUBF32 and the MMOV32 must be unique. That is,
MRa cannot be the same register as MRd.

Flags This instruction modifies the following flags in the MSTF register:
Flag TF ZF NF LUF LVF
Modified No Yes Yes Yes Yes

The MSTF register flags are modified as follows:

• LUF = 1 if MSUBF32 generates an underflow condition.
• LVF = 1 if MSUBF32 generates an overflow condition.
The MMOV32 instruction sets the NF and ZF flags.
Pipeline Both MSUBF32 and MMOV32 complete in a single cycle.

Example
NF = MRa(31);
ZF = 0;
if(MRa(30:23) == 0) { ZF = 1; NF = 0; }

See also MSUBF32 MRa, MRb, MRc

MSUBF32 MRa, #16FHi, MRb
MMPYF32 MRa, MRb, MRc || MSUBF32 MRd, MRe, MRf

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MSUBF32 MRd, MRe, MRf ||MMOV32 mem32, MRa

32-Bit Floating-Point Subtraction with Parallel Move

Operands MRd CLA floating-point destination register (MR0 to MR3) for the
MSUBF32 operation
MRe CLA floating-point source register (MR0 to MR3) for the MSUBF32
operation
MRf CLA floating-point source register (MR0 to MR3) for the MSUBF32
operation
mem32 32-bit destination memory location for the MMOV32 operation
MRa CLA floating-point source register (MR0 to MR3) for the MMOV32
operation

Opcode
LSW: mmmm mmmm mmmm mmmm
MSW: 0110 ffee ddaa addr

Description Subtract the contents of two floating-point registers and move from a floating-point
register to memory.

MRd = MRe - MRf;

[mem32] = MRa;

Flags This instruction modifies the following flags in the MSTF register:
Flag TF ZF NF LUF LVF
Modified No No No Yes Yes

The MSTF register flags are modified as follows:

• LUF = 1 if MSUBF32 generates an underflow condition.
• LVF = 1 if MSUBF32 generates an overflow condition.
Pipeline Both MSUBF32 and MMOV32 complete in a single cycle.

See also MSUBF32 MRa, MRb, MRc

MSUBF32 MRa, #16FHi, MRb
MSUBF32 MRd, MRe, MRf || MMOV32 MRa, mem32
MMPYF32 MRa, MRb, MRc || MSUBF32 MRd, MRe, MRf

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MSWAPF MRa, MRb {, CNDF}

Conditional Swap

Operands MRa CLA floating-point register (MR0 to MR3)

MRb CLA floating-point register (MR0 to MR3)
CNDF Optional condition tested based on the MSTF flags

Opcode
LSW: 0000 0000 CNDF bbaa
MSW: 0111 1011 0000 0000

Description Conditional swap of MRa and MRb.

if (CNDF == true) swap MRa and MRb;

CNDF is one of the following conditions:

Encode(1) CNDF Description MSTF Flags Tested
0000 NEQ Not equal to zero ZF == 0
0001 EQ Equal to zero ZF == 1
0010 GT Greater than zero ZF == 0 AND NF == 0
0011 GEQ Greater than or equal NF == 0
to zero
0100 LT Less than zero NF == 1
0101 LEQ Less than or equal to ZF == 1 OR NF == 1
zero
1010 TF Test flag set TF == 1
1011 NTF Test flag not set TF == 0
1100 LU Latched underflow LUF == 1
1101 LV Latched overflow LVF == 1
1110 UNC Unconditional None
1111 UNCF(2) Unconditional with flag None
modification

(1) Values not shown are reserved.

(2) This is the default operation, if no CNDF field is specified. This condition
allows the ZF and NF flags to be modified when a conditional operation is
executed. All other conditions do not modify these flags.

Flags This instruction modifies the following flags in the MSTF register:
Flag TF ZF NF LUF LVF
Modified No No No No No

No flags affected

Pipeline This is a single-cycle instruction.

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MSWAPF MRa, MRb {, CNDF} (continued)

Conditional Swap

Example
; X is an array of 32-bit floating-point values
; and has length elements. Find the maximum value in
; the array and store the value in Result
;
; Note: MCMPF32 and MSWAPF can be replaced by MMAXF32
;
_Cla1Task1:
MMOVI16 MAR1,#_X ; Start address
MUI16TOF32 MR0, @_len ; Length of the array
MNOP ; delay for MAR1 load
MNOP ; delay for MAR1 load
MMOV32 MR1, *MAR1[2]++ ; MR1 = X0
LOOP
MMOV32 MR2, *MAR1[2]++ ; MR2 = next element
MCMPF32 MR2, MR1 ; Compare MR2 with MR1
MSWAPF MR1, MR2, GT ; MR1 = MAX(MR1, MR2)
MADDF32 MR0, MR0, #-1.0 ; Decrememt the counter
MCMPF32 MR0 #0.0 ; Set/clear flags for MBCNDD
MNOP
MNOP
MNOP
MBCNDD LOOP, NEQ ; Branch if not equal to zero
MMOV32 @_Result, MR1 ; Always executed
MNOP ; Always executed
MNOP ; Always executed
MSTOP ; End of task

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MTESTTF CNDF

Test MSTF Register Flag Condition

Operands CNDF Condition to test based on MSTF flags

Opcode
LSW: 0000 0000 0000 cndf
MSW: 0111 1111 0100 0000

Description Test the CLA floating-point condition and if true, set the MSTF[TF] flag. If the condition is
false, clear the MSTF[TF] flag. This is useful for temporarily storing a condition for later
use.

if (CNDF == true) TF = 1;
else TF = 0;

CNDF is one of the following conditions:

Encode(1) CNDF Description MSTF Flags Tested
0000 NEQ Not equal to zero ZF == 0
0001 EQ Equal to zero ZF == 1
0010 GT Greater than zero ZF == 0 AND NF == 0
0011 GEQ Greater than or equal NF == 0
to zero
0100 LT Less than zero NF == 1
0101 LEQ Less than or equal to ZF == 1 OR NF == 1
zero
1010 TF Test flag set TF == 1
1011 NTF Test flag not set TF == 0
1100 LU Latched underflow LUF == 1
1101 LV Latched overflow LVF == 1
1110 UNC Unconditional None
1111 UNCF(2) Unconditional with flag None
modification

(1) Values not shown are reserved.

(2) This is the default operation, if no CNDF field is specified. This condition
allows the ZF and NF flags to be modified when a conditional operation is
executed. All other conditions do not modify these flags.

Flags This instruction modifies the following flags in the MSTF register:
Flag TF ZF NF LUF LVF
Modified Yes No No No No

TF = 0;
if (CNDF == true) TF = 1;

Note: If (CNDF == UNC or UNCF), the TF flag is set to 1.

Pipeline This is a single-cycle instruction.

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MTESTTF CNDF (continued)

Test MSTF Register Flag Condition

Example
; if (State == 0.1)
; RampState = RampState || RAMPMASK
; else if (State == 0.01)
; CoastState = CoastState || COASTMASK
; else
; SteadyState = SteadyState || STEADYMASK
;
_Cla1Task2:
MMOV32 MR0, @_State
MCMPF32 MR0, #0.1 ; Affects flags for 1st MBCNDD (A)
MCMPF32 MR0, #0.01 ; Check used by 2nd MBCNDD (B)
MTESTTF EQ ; Store EQ flag in TF for 2nd MBCNDD (B)
MNOP
MBCNDD _Skip1, NEQ ; (A) If State != 0.1, go to Skip1
MMOV32 MR1, @_RampState ; Always executed
MMOVXI MR2, #RAMPMASK ; Always executed
MOR32 MR1, MR2 ; Always executed
MMOV32 @_RampState, MR1 ; Execute if (A) branch not taken
MSTOP ; end of task if (A) branch not taken
_Skip1:
MMOV32 MR3, @_SteadyState
MMOVXI MR2, #STEADYMASK
MOR32 MR3, MR2
MBCNDD _Skip2, NTF ; (B) if State != .01, go to Skip2
MMOV32 MR1, @_CoastState ; Always executed
MMOVXI MR2, #COASTMASK ; Always executed
MOR32 MR1, MR2 ; Always executed
MMOV32 @_CoastState, MR1 ; Execute if (B) branch not taken
MSTOP ; end of task if (B) branch not taken
_Skip2:
MMOV32 @_SteadyState, MR3 ; Executed if (B) branch taken
MSTOP

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MUI16TOF32 MRa, mem16

Convert Unsigned 16-Bit Integer to 32-Bit Floating-Point Value

Operands MRa CLA floating-point destination register (MR0 to MR3)

mem16 16-bit source memory location

Opcode
LSW: mmmm mmmm mmmm mmmm
MSW: 0111 0101 01aa addr

Description When converting F32 to I16/UI16 data format, the MF32TOI16/UI16 operation truncates to
zero while the MF32TOI16R/UI16R operation rounds to the nearest (even) value.

MRa = UI16TOF32[mem16];

Flags This instruction does not affect any flags:

Flag TF ZF NF LUF LVF
Modified No No No No No

Pipeline This is a single-cycle instruction.

See also MF32TOI16 MRa, MRb

MF32TOI16R MRa, MRb
MF32TOUI16 MRa, MRb
MF32TOUI16R MRa, MRb
MI16TOF32 MRa, MRb
MI16TOF32 MRa, mem16
MUI16TOF32 MRa, MRb

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MUI16TOF32 MRa, MRb

Convert Unsigned 16-Bit Integer to 32-Bit Floating-Point Value

Operands MRa CLA floating-point destination register (MR0 to MR3)

MRb CLA floating-point source register (MR0 to MR3)

Opcode
LSW: 0000 0000 0000 bbaa
MSW: 0111 1110 1110 0000

Description Convert an unsigned 16-bit integer to a 32-bit floating-point value. When converting
float32 to I16/UI16 data format, the MF32TOI16/UI16 operation truncates to zero while
the MF32TOI16R/UI16R operation rounds to the nearest (even) value.

MRa = UI16TOF32[MRb];

Flags This instruction does not affect any flags:

Flag TF ZF NF LUF LVF
Modified No No No No No

Pipeline This is a single-cycle instruction.

Example
MMOVXI MR1, #0x800F ; MR1(15:0) = 32783 (0x800F)
MUI16TOF32 MR0, MR1 ; MR0 = UI16TOF32 (MR1(15:0))
; = 32783.0 (0x47000F00)

See also MF32TOI16 MRa, MRb

MF32TOI16R MRa, MRb
MF32TOUI16 MRa, MRb
MF32TOUI16R MRa, MRb
MI16TOF32 MRa, MRb
MI16TOF32 MRa, mem16
MUI16TOF32 MRa, mem16

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MUI32TOF32 MRa, mem32

Convert Unsigned 32-Bit Integer to 32-Bit Floating-Point Value

Operands MRa CLA floating-point destination register (MR0 to MR3)

mem32 32-bit memory location accessed using one of the available
addressing modes

Opcode
LSW: mmmm mmmm mmmm mmmm
MSW: 0111 0100 10aa addr

Description
MRa = UI32TOF32[mem32];

Flags This instruction does not affect any flags:

Flag TF ZF NF LUF LVF
Modified No No No No No

Pipeline This is a single-cycle instruction.

Example
; Given x2, m2, and b2 are Uint32 numbers:
;
; x2 = Uint32(2) = 0x00000002
; m2 = Uint32(1) = 0x00000001
; b2 = Uint32(3) = 0x00000003
;
; Calculate y2 = x2 * m2 + b2
;
_Cla1Task1:
MUI32TOF32 MR0, @_m2 ; MR0 = 1.0 (0x3F800000)
MUI32TOF32 MR1, @_x2 ; MR1 = 2.0 (0x40000000)
MUI32TOF32 MR2, @_b2 ; MR2 = 3.0 (0x40400000)
MMPYF32 MR3, MR0, MR1 ; M*X
MADDF32 MR3, MR2, MR3 ; Y=MX+B = 5.0 (0x40A00000)
MF32TOUI32 MR3, MR3 ; Y = Uint32(5.0) = 0x00000005
MMOV32 @_y2, MR3 ; store result
MSTOP ; end of task

See also MF32TOI32 MRa, MRb

MF32TOUI32 MRa, MRb
MI32TOF32 MRa, mem32
MI32TOF32 MRa, MRb
MUI32TOF32 MRa, MRb

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MUI32TOF32 MRa, MRb

Convert Unsigned 32-Bit Integer to 32-Bit Floating-Point Value

Operands MRa CLA floating-point destination register (MR0 to MR3)

MRb CLA floating-point source register (MR0 to MR3)

Opcode
LSW: 0000 0000 0000 bbaa
MSW: 0111 1101 1100 0000

Description
MRa = UI32TOF32 [MRb];

Flags This instruction does not affect any flags:

Flag TF ZF NF LUF LVF
Modified No No No No No

Pipeline This is a single-cycle instruction.

Example
MMOVIZ MR3, #0x8000 ; MR3(31:16) = 0x8000
MMOVXI MR3, #0x1111 ; MR3(15:0) = 0x1111
; MR3 = 2147488017
MUI32TOF32 MR3, MR3 ; MR3 = MUI32TOF32 (MR3) = 2147488017.0 (0x4F000011)

See also MF32TOI32 MRa, MRb

MF32TOUI32 MRa, MRb
MI32TOF32 MRa, mem32
MI32TOF32 MRa, MRb
MUI32TOF32 MRa, mem32

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MXOR32 MRa, MRb, MRc

Bitwise Exclusive Or

Operands MRa CLA floating-point destination register (MR0 to MR3)

MRb CLA floating-point source register (MR0 to MR3)
MRc CLA floating-point source register (MR0 to MR3)

Opcode
LSW: 0000 0000 00cc bbaa
MSW: 0111 1100 1010 0000

Description Bitwise XOR of MRb with MRc.

MARa(31:0) = MARb(31:0) XOR MRc(31:0);

Flags This instruction modifies the following flags in the MSTF register:
Flag TF ZF NF LUF LVF
Modified No Yes Yes No No

The MSTF register flags are modified based on the integer results of the operation.

NF = MRa(31);
ZF = 0;
if(MRa(31:0) == 0) { ZF = 1; }

Pipeline This is a single-cycle instruction.

Example
MMOVIZ MR0, #0x5555 ; MR0 = 0x5555AAAA
MMOVXI MR0, #0xAAAA
MMOVIZ MR1, #0x5432 ; MR1 = 0x5432FEDC
MMOVXI MR1, #0xFEDC
; 0101 XOR 0101 = 0000 (0)
; 0101 XOR 0100 = 0001 (1)
; 0101 XOR 0011 = 0110 (6)
; 0101 XOR 0010 = 0111 (7)
; 1010 XOR 1111 = 0101 (5)
; 1010 XOR 1110 = 0100 (4)
; 1010 XOR 1101 = 0111 (7)
; 1010 XOR 1100 = 0110 (6)
MXOR32 MR2, MR1, MR0 ; MR3 = 0x01675476

See also MAND32 MRa, MRb, MRc

MOR32 MRa, MRb, MRc

8.8 CLA Registers

This section describes the Control Law Accelerator registers.
8.8.1 CLA Base Address Table (C28)
Table 8-22. CLA Base Address Table (C28)
Bit Field Name Pipeline
DriverLib Name Base Address CPU1 CPU2 DMA CLA
Instance Structure Protected

Cla1Regs CLA_REGS CLA1_BASE 0x0000_1400 YES YES - - -

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8.8.2 CLA_ONLY_REGS Registers

Table 8-23 lists the memory-mapped registers for the CLA_ONLY_REGS registers. All register offset addresses
not listed in Table 8-23 should be considered as reserved locations and the register contents should not be
modified.
Table 8-23. CLA_ONLY_REGS Registers
Offset Acronym Register Name Write Protection Section
80h _MVECTBGRNDACTIVE Active register for MVECTBGRND. EALLOW Go
C0h _MPSACTL CLA PSA Control Register EALLOW Go
C2h _MPSA1 CLA PSA1 Register EALLOW Go
C4h _MPSA2 CLA PSA2 Register EALLOW Go
E0h SOFTINTEN CLA Software Interrupt Enable Register Go
E2h SOFTINTFRC CLA Software Interrupt Force Register Go

Complex bit access types are encoded to fit into small table cells. Table 8-24 shows the codes that are used for
access types in this section.
Table 8-24. CLA_ONLY_REGS Access Type Codes
Access Type Code Description
Read Type
R R Read
R-0 R Read
-0 Returns 0s
Write Type
W W Write
W1S W Write
1S 1 to set
Reset or Default Value
-n Value after reset or the default
value
Register Array Variables
i,j,k,l,m,n When these variables are used in
a register name, an offset, or an
address, they refer to the value of
a register array where the register
is part of a group of repeating
registers. The register groups
form a hierarchical structure and
the array is represented with a
formula.
y When this variable is used in a
register name, an offset, or an
address it refers to the value of
a register array.

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8.8.2.1 _MVECTBGRNDACTIVE Register (Offset = 80h) [Reset = 0h]

_MVECTBGRNDACTIVE is shown in Figure 8-2 and described in Table 8-25.
Return to the Summary Table.
Gives the current interrupted MPC value of the background task, if the background task was running and
interrupted, or reflects the MVECTBGRND value, if MCTLBGRND.BGSTART bit is 0.
Figure 8-2. _MVECTBGRNDACTIVE Register
15 14 13 12 11 10 9 8
i16
R-0h

7 6 5 4 3 2 1 0
i16
R-0h

Table 8-25. _MVECTBGRNDACTIVE Register Field Descriptions

Bit Field Type Reset Description
15-0 i16 R 0h Gives the current interrupted MPC value of the background task,
if the background task was running and interrupted, or reflects the
MVECTBGRND value, if MCTLBGRND.BGSTART bit is 0.
Reset type: SYSRSn

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8.8.2.2 _MPSACTL Register (Offset = C0h) [Reset = 0h]

_MPSACTL is shown in Figure 8-3 and described in Table 8-26.
Return to the Summary Table.
PSA Control Register
Figure 8-3. _MPSACTL Register
15 14 13 12 11 10 9 8
RESERVED
R-0h

7 6 5 4 3 2 1 0
MPSA2CFG MPSA2CLEAR MPSA1CLEAR MDWDBCYC MDWDBSTART MPABCYC MPABSTART
R/W-0h R-0/W1S-0h R-0/W1S-0h R/W-0h R/W-0h R/W-0h R/W-0h

Table 8-26. _MPSACTL Register Field Descriptions

Bit Field Type Reset Description
15-8 RESERVED R 0h Reserved
7-6 MPSA2CFG R/W 0h CLA PSA2 Polynomial Configuration Bits: These bits configure the
type of polynomial used for PSA2. The polynomials chosen are
commonly used in the industry:
Mode Polynomial Type
0,0 PSA
0,1 CRC32
1,0 CRC16
1,1 CRC16-CCITT
Note: [1] Polynomial configuration should be performed when PSA2
is stopped.
Reset type: SYSRSn
5 MPSA2CLEAR R-0/W1S 0h CLA PSA2 Clear Bit:
Writing of "1" will clear contents of PSA2 register.
Writes of "0" are ignored.
Always reads back a "0"
Note: Clearing operation should be performed when PSA2 is
stopped.
Reset type: SYSRSn
4 MPSA1CLEAR R-0/W1S 0h CLA PSA1 Clear Bit:
Writing of "1" will clear contents of PSA1 register.
Writes of "0" are ignored.
Always reads back a "0"
Note: Clearing operation should be performed when PSA1 is
stopped.
Reset type: SYSRSn
3 MDWDBCYC R/W 0h CLA Data Write Data Bus PSA2 Cycle or Event Based Bit:
0 PSA2 calculated on every cycle
1 PSA2 calculated on every bus event
Reset type: SYSRSn
2 MDWDBSTART R/W 0h CLA Data Write Data Bus PSA2 Start/Stop Bit:
0 PSA2 stopped
1 PSA2 start
Reset type: SYSRSn
1 MPABCYC R/W 0h CLA Program Address Bus PSA1 Cycle/Event Based Bit:
0 PSA1 calculated on every cycle
1 PSA1 calculated on every bus event
Reset type: SYSRSn
0 MPABSTART R/W 0h CLA Program Address Bus PSA1 Start/Stop Bit:
0 PSA1 stopped
1 PSA1 start
Reset type: SYSRSn

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8.8.2.3 _MPSA1 Register (Offset = C2h) [Reset = 0h]

_MPSA1 is shown in Figure 8-4 and described in Table 8-27.
Return to the Summary Table.
PSA1 Register
Figure 8-4. _MPSA1 Register
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
i32
R/W-0h

Table 8-27. _MPSA1 Register Field Descriptions

Bit Field Type Reset Description
31-0 i32 R/W 0h PSA1 Value: Reading this register gives the current PSA1 value. The
value can be read at any time.
Writes to this register are allowed to initialize the PSA1 to a known
value. Writes to this register should only be made when PSA1 is
stopped.
Register value is cleared to zero by reset or by writing to the
MPSA1CLEAR bit in the MPSACTL register.
Reset type: SYSRSn

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8.8.2.4 _MPSA2 Register (Offset = C4h) [Reset = 0h]

_MPSA2 is shown in Figure 8-5 and described in Table 8-28.
Return to the Summary Table.
PSA2 Register
Figure 8-5. _MPSA2 Register
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
i32
R/W-0h

Table 8-28. _MPSA2 Register Field Descriptions

Bit Field Type Reset Description
31-0 i32 R/W 0h PSA2 Value: Reading this register gives the current PSA2 value. The
value can be read at any time.
Writes to this register are allowed to initialize the PSA2 to a known
value. Writes to this register should only be made when PSA2 is
stopped.
Register value is cleared to zero by reset or by writing to the
MPSA2CLEAR bit in the MPSACTL register.
Reset type: SYSRSn

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8.8.2.5 SOFTINTEN Register (Offset = E0h) [Reset = 0h]

SOFTINTEN is shown in Figure 8-6 and described in Table 8-29.
Return to the Summary Table.
Enables the ability to generate CLA task interrupt from within the task, by writing to SOFTINTFRC register.
SOFTINTFRC register can only be written from CLA.
Figure 8-6. SOFTINTEN Register
15 14 13 12 11 10 9 8
RESERVED
R/W-0h

7 6 5 4 3 2 1 0
TASK8 TASK7 TASK6 TASK5 TASK4 TASK3 TASK2 TASK1
R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h

Table 8-29. SOFTINTEN Register Field Descriptions

Bit Field Type Reset Description
15-8 RESERVED R/W 0h Reserved
7 TASK8 R/W 0h 0: End-Of-Task Interrupt is fired for the respective task
1: Enable Software Interrupt for the respective task. End-of-Task
interrupt is not sent to CPU in this case.
Note: SOFTINTEN register is read only in the CPU memory map.
Reset type: SYSRSn
6 TASK7 R/W 0h 0: End-Of-Task Interrupt is fired for the respective task
1: Enable Software Interrupt for the respective task. End-of-Task
interrupt is not sent to CPU in this case.
Note: SOFTINTEN register is read only in the CPU memory map.
Reset type: SYSRSn
5 TASK6 R/W 0h 0: End-Of-Task Interrupt is fired for the respective task
1: Enable Software Interrupt for the respective task. End-of-Task
interrupt is not sent to CPU in this case.
Note: SOFTINTEN register is read only in the CPU memory map.
Reset type: SYSRSn
4 TASK5 R/W 0h 0: End-Of-Task Interrupt is fired for the respective task
1: Enable Software Interrupt for the respective task. End-of-Task
interrupt is not sent to CPU in this case.
Note: SOFTINTEN register is read only in the CPU memory map.
Reset type: SYSRSn
3 TASK4 R/W 0h 0: End-Of-Task Interrupt is fired for the respective task
1: Enable Software Interrupt for the respective task. End-of-Task
interrupt is not sent to CPU in this case.
Note: SOFTINTEN register is read only in the CPU memory map.
Reset type: SYSRSn
2 TASK3 R/W 0h 0: End-Of-Task Interrupt is fired for the respective task
1: Enable Software Interrupt for the respective task. End-of-Task
interrupt is not sent to CPU in this case.
Note: SOFTINTEN register is read only in the CPU memory map.
Reset type: SYSRSn
1 TASK2 R/W 0h 0: End-Of-Task Interrupt is fired for the respective task
1: Enable Software Interrupt for the respective task. End-of-Task
interrupt is not sent to CPU in this case.
Note: SOFTINTEN register is read only in the CPU memory map.
Reset type: SYSRSn

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Table 8-29. SOFTINTEN Register Field Descriptions (continued)

Bit Field Type Reset Description
0 TASK1 R/W 0h 0: End-Of-Task Interrupt is fired for the respective task
1: Enable Software Interrupt for the respective task. End-of-Task
interrupt is not sent to CPU in this case.
Note: SOFTINTEN register is read only in the CPU memory map.
Reset type: SYSRSn

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8.8.2.6 SOFTINTFRC Register (Offset = E2h) [Reset = 0h]

SOFTINTFRC is shown in Figure 8-7 and described in Table 8-30.
Return to the Summary Table.
Writing a value of 1 in a bit will generate the corresponding task interrupt.
Figure 8-7. SOFTINTFRC Register
15 14 13 12 11 10 9 8
RESERVED
R/W-0h

7 6 5 4 3 2 1 0
TASK8 TASK7 TASK6 TASK5 TASK4 TASK3 TASK2 TASK1
R-0/W1S-0h R-0/W1S-0h R-0/W1S-0h R-0/W1S-0h R-0/W1S-0h R-0/W1S-0h R-0/W1S-0h R-0/W1S-0h

Table 8-30. SOFTINTFRC Register Field Descriptions

Bit Field Type Reset Description
15-8 RESERVED R/W 0h Reserved
7 TASK8 R-0/W1S 0h Write of '1' will generate a CLA software interrupt to the CPU for the
corresponding task.
Write of '0' has no effect.
Reset type: SYSRSn
6 TASK7 R-0/W1S 0h Write of '1' will generate a CLA software interrupt to the CPU for the
corresponding task.
Write of '0' has no effect.
Reset type: SYSRSn
5 TASK6 R-0/W1S 0h Write of '1' will generate a CLA software interrupt to the CPU for the
corresponding task.
Write of '0' has no effect.
Reset type: SYSRSn
4 TASK5 R-0/W1S 0h Write of '1' will generate a CLA software interrupt to the CPU for the
corresponding task.
Write of '0' has no effect.
Reset type: SYSRSn
3 TASK4 R-0/W1S 0h Write of '1' will generate a CLA software interrupt to the CPU for the
corresponding task.
Write of '0' has no effect.
Reset type: SYSRSn
2 TASK3 R-0/W1S 0h Write of '1' will generate a CLA software interrupt to the CPU for the
corresponding task.
Write of '0' has no effect.
Reset type: SYSRSn
1 TASK2 R-0/W1S 0h Write of '1' will generate a CLA software interrupt to the CPU for the
corresponding task.
Write of '0' has no effect.
Reset type: SYSRSn
0 TASK1 R-0/W1S 0h Write of '1' will generate a CLA software interrupt to the CPU for the
corresponding task.
Write of '0' has no effect.
Reset type: SYSRSn

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8.8.3 CLA_SOFTINT_REGS Registers

Table 8-31 lists the memory-mapped registers for the CLA_SOFTINT_REGS registers. All register offset
addresses not listed in Table 8-31 should be considered as reserved locations and the register contents should
not be modified.
Table 8-31. CLA_SOFTINT_REGS Registers
Offset Acronym Register Name Write Protection Section
0h SOFTINTEN CLA Software Interrupt Enable Register Go
2h SOFTINTFRC CLA Software Interrupt Force Register Go

Complex bit access types are encoded to fit into small table cells. Table 8-32 shows the codes that are used for
access types in this section.
Table 8-32. CLA_SOFTINT_REGS Access Type
Codes
Access Type Code Description
Read Type
R R Read
R-0 R Read
-0 Returns 0s
Write Type
W W Write
W1S W Write
1S 1 to set
Reset or Default Value
-n Value after reset or the default
value
Register Array Variables
i,j,k,l,m,n When these variables are used in
a register name, an offset, or an
address, they refer to the value of
a register array where the register
is part of a group of repeating
registers. The register groups
form a hierarchical structure and
the array is represented with a
formula.
y When this variable is used in a
register name, an offset, or an
address it refers to the value of
a register array.

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8.8.3.1 SOFTINTEN Register (Offset = 0h) [Reset = 0h]

SOFTINTEN is shown in Figure 8-8 and described in Table 8-33.
Return to the Summary Table.
Enables the ability to generate CLA task interrupt from within the task, by writing to SOFTINTFRC register.
SOFTINTFRC register can only be written from CLA.
Figure 8-8. SOFTINTEN Register
15 14 13 12 11 10 9 8
RESERVED
R/W-0h

7 6 5 4 3 2 1 0
TASK8 TASK7 TASK6 TASK5 TASK4 TASK3 TASK2 TASK1
R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h

Table 8-33. SOFTINTEN Register Field Descriptions

Bit Field Type Reset Description
15-8 RESERVED R/W 0h Reserved
7 TASK8 R/W 0h 0: End-Of-Task Interrupt is fired for the respective task
1: Enable Software Interrupt for the respective task. End-of-Task
interrupt is not sent to CPU in this case.
Note: SOFTINTEN register is read only in the CPU memory map.
Reset type: SYSRSn
6 TASK7 R/W 0h 0: End-Of-Task Interrupt is fired for the respective task
1: Enable Software Interrupt for the respective task. End-of-Task
interrupt is not sent to CPU in this case.
Note: SOFTINTEN register is read only in the CPU memory map.
Reset type: SYSRSn
5 TASK6 R/W 0h 0: End-Of-Task Interrupt is fired for the respective task
1: Enable Software Interrupt for the respective task. End-of-Task
interrupt is not sent to CPU in this case.
Note: SOFTINTEN register is read only in the CPU memory map.
Reset type: SYSRSn
4 TASK5 R/W 0h 0: End-Of-Task Interrupt is fired for the respective task
1: Enable Software Interrupt for the respective task. End-of-Task
interrupt is not sent to CPU in this case.
Note: SOFTINTEN register is read only in the CPU memory map.
Reset type: SYSRSn
3 TASK4 R/W 0h 0: End-Of-Task Interrupt is fired for the respective task
1: Enable Software Interrupt for the respective task. End-of-Task
interrupt is not sent to CPU in this case.
Note: SOFTINTEN register is read only in the CPU memory map.
Reset type: SYSRSn
2 TASK3 R/W 0h 0: End-Of-Task Interrupt is fired for the respective task
1: Enable Software Interrupt for the respective task. End-of-Task
interrupt is not sent to CPU in this case.
Note: SOFTINTEN register is read only in the CPU memory map.
Reset type: SYSRSn
1 TASK2 R/W 0h 0: End-Of-Task Interrupt is fired for the respective task
1: Enable Software Interrupt for the respective task. End-of-Task
interrupt is not sent to CPU in this case.
Note: SOFTINTEN register is read only in the CPU memory map.
Reset type: SYSRSn

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Table 8-33. SOFTINTEN Register Field Descriptions (continued)

Bit Field Type Reset Description
0 TASK1 R/W 0h 0: End-Of-Task Interrupt is fired for the respective task
1: Enable Software Interrupt for the respective task. End-of-Task
interrupt is not sent to CPU in this case.
Note: SOFTINTEN register is read only in the CPU memory map.
Reset type: SYSRSn

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8.8.3.2 SOFTINTFRC Register (Offset = 2h) [Reset = 0h]

SOFTINTFRC is shown in Figure 8-9 and described in Table 8-34.
Return to the Summary Table.
Writing a value of 1 in a bit will generate the corresponding task interrupt.This register is only accessible by the
CLA (not the CPU).
Figure 8-9. SOFTINTFRC Register
15 14 13 12 11 10 9 8
RESERVED
R/W-0h

7 6 5 4 3 2 1 0
TASK8 TASK7 TASK6 TASK5 TASK4 TASK3 TASK2 TASK1
R-0/W1S-0h R-0/W1S-0h R-0/W1S-0h R-0/W1S-0h R-0/W1S-0h R-0/W1S-0h R-0/W1S-0h R-0/W1S-0h

Table 8-34. SOFTINTFRC Register Field Descriptions

Bit Field Type Reset Description
15-8 RESERVED R/W 0h Reserved
7 TASK8 R-0/W1S 0h Write of '1' will generate a CLA software interrupt to the CPU for the
corresponding task.
Write of '0' has no effect.
Reset type: SYSRSn
6 TASK7 R-0/W1S 0h Write of '1' will generate a CLA software interrupt to the CPU for the
corresponding task.
Write of '0' has no effect.
Reset type: SYSRSn
5 TASK6 R-0/W1S 0h Write of '1' will generate a CLA software interrupt to the CPU for the
corresponding task.
Write of '0' has no effect.
Reset type: SYSRSn
4 TASK5 R-0/W1S 0h Write of '1' will generate a CLA software interrupt to the CPU for the
corresponding task.
Write of '0' has no effect.
Reset type: SYSRSn
3 TASK4 R-0/W1S 0h Write of '1' will generate a CLA software interrupt to the CPU for the
corresponding task.
Write of '0' has no effect.
Reset type: SYSRSn
2 TASK3 R-0/W1S 0h Write of '1' will generate a CLA software interrupt to the CPU for the
corresponding task.
Write of '0' has no effect.
Reset type: SYSRSn
1 TASK2 R-0/W1S 0h Write of '1' will generate a CLA software interrupt to the CPU for the
corresponding task.
Write of '0' has no effect.
Reset type: SYSRSn
0 TASK1 R-0/W1S 0h Write of '1' will generate a CLA software interrupt to the CPU for the
corresponding task.
Write of '0' has no effect.
Reset type: SYSRSn

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8.8.4 CLA_REGS Registers

Table 8-35 lists the memory-mapped registers for the CLA_REGS registers. All register offset addresses not
listed in Table 8-35 should be considered as reserved locations and the register contents should not be modified.
Table 8-35. CLA_REGS Registers
Offset Acronym Register Name Write Protection Section
0h MVECT1 Task Interrupt Vector EALLOW Go
1h MVECT2 Task Interrupt Vector EALLOW Go
2h MVECT3 Task Interrupt Vector EALLOW Go
3h MVECT4 Task Interrupt Vector EALLOW Go
4h MVECT5 Task Interrupt Vector EALLOW Go
5h MVECT6 Task Interrupt Vector EALLOW Go
6h MVECT7 Task Interrupt Vector EALLOW Go
7h MVECT8 Task Interrupt Vector EALLOW Go
10h MCTL Control Register EALLOW Go
1Bh _MVECTBGRNDACTIVE Active register for MVECTBGRND. EALLOW Go
1Ch SOFTINTEN CLA Software Interrupt Enable Register Go
1Dh _MSTSBGRND Status register for the back ground task. EALLOW Go
1Eh _MCTLBGRND Control register for the back ground task. EALLOW Go
1Fh _MVECTBGRND Vector for the back ground task. EALLOW Go
20h MIFR Interrupt Flag Register EALLOW Go
21h MIOVF Interrupt Overflow Flag Register EALLOW Go
22h MIFRC Interrupt Force Register EALLOW Go
23h MICLR Interrupt Flag Clear Register EALLOW Go
24h MICLROVF Interrupt Overflow Flag Clear Register EALLOW Go
25h MIER Interrupt Enable Register EALLOW Go
26h MIRUN Interrupt Run Status Register EALLOW Go
28h _MPC CLA Program Counter Go
2Ah _MAR0 CLA Auxiliary Register 0 Go
2Bh _MAR1 CLA Auxiliary Register 1 Go
2Eh _MSTF CLA Floating-Point Status Register Go
30h _MR0 CLA Floating-Point Result Register 0 Go
34h _MR1 CLA Floating-Point Result Register 1 Go
38h _MR2 CLA Floating-Point Result Register 2 Go
3Ch _MR3 CLA Floating-Point Result Register 3 Go
42h _MPSACTL CLA PSA Control Register EALLOW Go
44h _MPSA1 CLA PSA1 Register EALLOW Go
46h _MPSA2 CLA PSA2 Register EALLOW Go

Complex bit access types are encoded to fit into small table cells. Table 8-36 shows the codes that are used for
access types in this section.
Table 8-36. CLA_REGS Access Type Codes
Access Type Code Description
Read Type
R R Read
R-0 R Read
-0 Returns 0s
Write Type

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Table 8-36. CLA_REGS Access Type Codes

(continued)
Access Type Code Description
W W Write
W1C W Write
1C 1 to clear
W1S W Write
1S 1 to set
Reset or Default Value
-n Value after reset or the default
value
Register Array Variables
i,j,k,l,m,n When these variables are used in
a register name, an offset, or an
address, they refer to the value of
a register array where the register
is part of a group of repeating
registers. The register groups
form a hierarchical structure and
the array is represented with a
formula.
y When this variable is used in a
register name, an offset, or an
address it refers to the value of
a register array.

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8.8.4.1 MVECT1 Register (Offset = 0h) [Reset = 0h]

MVECT1 is shown in Figure 8-10 and described in Table 8-37.
Return to the Summary Table.
Each CLA interrupt has its own interrupt vector (MVECT1 to MVECT8). This interrupt vector points to the
first instruction of the associated task. When a task begins, the CLA will start fetching instructions at the
location indicated by the appropriate MVECT register .
Figure 8-10. MVECT1 Register
15 14 13 12 11 10 9 8
MVECT
R/W-0h

7 6 5 4 3 2 1 0
MVECT
R/W-0h

Table 8-37. MVECT1 Register Field Descriptions

Bit Field Type Reset Description
15-0 MVECT R/W 0h MPC Start Address: These bits specify the start address for the
given interrupt (task). The address range of the CLA with a 16-bit
MVECT is 64Kx16 words or 32K CLA instructions.
There is one MVECT register per interrupt (task). Interrupt 1 uses
MVECT1, interrupt 2 uses MVECT2 and so forth.
Note: While the CLA is running or executing a task, the CPU can
change the MVECT values..
Reset type: SYSRSn

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8.8.4.2 MVECT2 Register (Offset = 1h) [Reset = 0h]

MVECT2 is shown in Figure 8-11 and described in Table 8-38.
Return to the Summary Table.
Each CLA interrupt has its own interrupt vector (MVECT1 to MVECT8). This interrupt vector points to the
first instruction of the associated task. When a task begins, the CLA will start fetching instructions at the
location indicated by the appropriate MVECT register .
Figure 8-11. MVECT2 Register
15 14 13 12 11 10 9 8
MVECT
R/W-0h

7 6 5 4 3 2 1 0
MVECT
R/W-0h

Table 8-38. MVECT2 Register Field Descriptions

Bit Field Type Reset Description
15-0 MVECT R/W 0h MPC Start Address: These bits specify the start address for the
given interrupt (task). The address range of the CLA with a 16-bit
MVECT is 64Kx16 words or 32K CLA instructions.
There is one MVECT register per interrupt (task). Interrupt 1 uses
MVECT1, interrupt 2 uses MVECT2 and so forth.
Note: While the CLA is running or executing a task, the CPU can
change the MVECT values..
Reset type: SYSRSn

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8.8.4.3 MVECT3 Register (Offset = 2h) [Reset = 0h]

MVECT3 is shown in Figure 8-12 and described in Table 8-39.
Return to the Summary Table.
Each CLA interrupt has its own interrupt vector (MVECT1 to MVECT8). This interrupt vector points to the
first instruction of the associated task. When a task begins, the CLA will start fetching instructions at the
location indicated by the appropriate MVECT register .
Figure 8-12. MVECT3 Register
15 14 13 12 11 10 9 8
MVECT
R/W-0h

7 6 5 4 3 2 1 0
MVECT
R/W-0h

Table 8-39. MVECT3 Register Field Descriptions

Bit Field Type Reset Description
15-0 MVECT R/W 0h MPC Start Address: These bits specify the start address for the
given interrupt (task). The address range of the CLA with a 16-bit
MVECT is 64Kx16 words or 32K CLA instructions.
There is one MVECT register per interrupt (task). Interrupt 1 uses
MVECT1, interrupt 2 uses MVECT2 and so forth.
Note: While the CLA is running or executing a task, the CPU can
change the MVECT values..
Reset type: SYSRSn

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8.8.4.4 MVECT4 Register (Offset = 3h) [Reset = 0h]

MVECT4 is shown in Figure 8-13 and described in Table 8-40.
Return to the Summary Table.
Each CLA interrupt has its own interrupt vector (MVECT1 to MVECT8). This interrupt vector points to the
first instruction of the associated task. When a task begins, the CLA will start fetching instructions at the
location indicated by the appropriate MVECT register .
Figure 8-13. MVECT4 Register
15 14 13 12 11 10 9 8
MVECT
R/W-0h

7 6 5 4 3 2 1 0
MVECT
R/W-0h

Table 8-40. MVECT4 Register Field Descriptions

Bit Field Type Reset Description
15-0 MVECT R/W 0h MPC Start Address: These bits specify the start address for the
given interrupt (task). The address range of the CLA with a 16-bit
MVECT is 64Kx16 words or 32K CLA instructions.
There is one MVECT register per interrupt (task). Interrupt 1 uses
MVECT1, interrupt 2 uses MVECT2 and so forth.
Note: While the CLA is running or executing a task, the CPU can
change the MVECT values..
Reset type: SYSRSn

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8.8.4.5 MVECT5 Register (Offset = 4h) [Reset = 0h]

MVECT5 is shown in Figure 8-14 and described in Table 8-41.
Return to the Summary Table.
Each CLA interrupt has its own interrupt vector (MVECT1 to MVECT8). This interrupt vector points to the
first instruction of the associated task. When a task begins, the CLA will start fetching instructions at the
location indicated by the appropriate MVECT register .
Figure 8-14. MVECT5 Register
15 14 13 12 11 10 9 8
MVECT
R/W-0h

7 6 5 4 3 2 1 0
MVECT
R/W-0h

Table 8-41. MVECT5 Register Field Descriptions

Bit Field Type Reset Description
15-0 MVECT R/W 0h MPC Start Address: These bits specify the start address for the
given interrupt (task). The address range of the CLA with a 16-bit
MVECT is 64Kx16 words or 32K CLA instructions.
There is one MVECT register per interrupt (task). Interrupt 1 uses
MVECT1, interrupt 2 uses MVECT2 and so forth.
Note: While the CLA is running or executing a task, the CPU can
change the MVECT values..
Reset type: SYSRSn

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8.8.4.6 MVECT6 Register (Offset = 5h) [Reset = 0h]

MVECT6 is shown in Figure 8-15 and described in Table 8-42.
Return to the Summary Table.
Each CLA interrupt has its own interrupt vector (MVECT1 to MVECT8). This interrupt vector points to the
first instruction of the associated task. When a task begins, the CLA will start fetching instructions at the
location indicated by the appropriate MVECT register .
Figure 8-15. MVECT6 Register
15 14 13 12 11 10 9 8
MVECT
R/W-0h

7 6 5 4 3 2 1 0
MVECT
R/W-0h

Table 8-42. MVECT6 Register Field Descriptions

Bit Field Type Reset Description
15-0 MVECT R/W 0h MPC Start Address: These bits specify the start address for the
given interrupt (task). The address range of the CLA with a 16-bit
MVECT is 64Kx16 words or 32K CLA instructions.
There is one MVECT register per interrupt (task). Interrupt 1 uses
MVECT1, interrupt 2 uses MVECT2 and so forth.
Note: While the CLA is running or executing a task, the CPU can
change the MVECT values..
Reset type: SYSRSn

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8.8.4.7 MVECT7 Register (Offset = 6h) [Reset = 0h]

MVECT7 is shown in Figure 8-16 and described in Table 8-43.
Return to the Summary Table.
Each CLA interrupt has its own interrupt vector (MVECT1 to MVECT8). This interrupt vector points to the
first instruction of the associated task. When a task begins, the CLA will start fetching instructions at the
location indicated by the appropriate MVECT register .
Figure 8-16. MVECT7 Register
15 14 13 12 11 10 9 8
MVECT
R/W-0h

7 6 5 4 3 2 1 0
MVECT
R/W-0h

Table 8-43. MVECT7 Register Field Descriptions

Bit Field Type Reset Description
15-0 MVECT R/W 0h MPC Start Address: These bits specify the start address for the
given interrupt (task). The address range of the CLA with a 16-bit
MVECT is 64Kx16 words or 32K CLA instructions.
There is one MVECT register per interrupt (task). Interrupt 1 uses
MVECT1, interrupt 2 uses MVECT2 and so forth.
Note: While the CLA is running or executing a task, the CPU can
change the MVECT values..
Reset type: SYSRSn

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8.8.4.8 MVECT8 Register (Offset = 7h) [Reset = 0h]

MVECT8 is shown in Figure 8-17 and described in Table 8-44.
Return to the Summary Table.
Each CLA interrupt has its own interrupt vector (MVECT1 to MVECT8). This interrupt vector points to the
first instruction of the associated task. When a task begins, the CLA will start fetching instructions at the
location indicated by the appropriate MVECT register .
Figure 8-17. MVECT8 Register
15 14 13 12 11 10 9 8
MVECT
R/W-0h

7 6 5 4 3 2 1 0
MVECT
R/W-0h

Table 8-44. MVECT8 Register Field Descriptions

Bit Field Type Reset Description
15-0 MVECT R/W 0h MPC Start Address: These bits specify the start address for the
given interrupt (task). The address range of the CLA with a 16-bit
MVECT is 64Kx16 words or 32K CLA instructions.
There is one MVECT register per interrupt (task). Interrupt 1 uses
MVECT1, interrupt 2 uses MVECT2 and so forth.
Note: While the CLA is running or executing a task, the CPU can
change the MVECT values..
Reset type: SYSRSn

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8.8.4.9 MCTL Register (Offset = 10h) [Reset = 0h]

MCTL is shown in Figure 8-18 and described in Table 8-45.
Return to the Summary Table.
Control Register
Figure 8-18. MCTL Register
15 14 13 12 11 10 9 8
RESERVED
R-0h

7 6 5 4 3 2 1 0
RESERVED IACKE SOFTRESET HARDRESET
R-0h R/W-0h R-0/W1S-0h R-0/W1S-0h

Table 8-45. MCTL Register Field Descriptions

Bit Field Type Reset Description
15-3 RESERVED R 0h Reserved
2 IACKE R/W 0h IACK Operation Enable Bit: Writing a "1" to this bit will enable the
IACK operation for setting the MIFR bits in the same manner as the
MIFRC register (write of "1" will set respective MIFR bit). At reset,
this feature is disabled.
This feature enables the C28 CPU to efficiently trigger a task.
Note: IACK operation should ignore EALLOW status of C28 core
when accessing the MIFRC register.
Reset type: SYSRSn
0h (R/W) = The CLA ignores the IACK instruction. (default)
1h (R/W) = Enable the main CPU to use the IACK #16bit instruction
to set MIFR bits in the same manner as writing to the MIFRC
register. Each bit in the operand, #16bit, corresponds to a bit in the
MIFRC register. Using IACK has the advantage of not having to first
set the EALLOW bit. This allows the main CPU to efficiently trigger a
CLA task through software.
Examples IACK #0x0001 Write a 1 to MIFRC bit 0 to force task 1
IACK #0x0003 Write a 1 to MIFRC bit 0 and 1 to force task 1 and
task 2
1 SOFTRESET R-0/W1S 0h Soft Reset Bit: Writing a "1" to this bit will stop a current task, clear
the RUN flag and also clear all bits in the MIER register. Writes of "0"
are ignored and reads always return a "0".
Note: After issuing SOFTRESET command, user should wait at least
1 clock cycle before attempting to write to MIER register.
Reset type: SYSRSn
0h (R/W) = This bit always reads back 0 and writes of 0 are ignored.
1h (R/W) = Writing a 1 will cause a soft reset of the CLA. This
will stop the current task, clear the MIRUN flag and clear all bits
in the MIER register. After a soft reset you must wait at least 1
SYSCLKOUT cycle before reconfiguring the MIER bits. If these two
operations are done back-to-back then the MIER bits will not get set.
0 HARDRESET R-0/W1S 0h Hard Reset Bit: Writing a "1" to this bit will cause a HARD reset on
the CLA. The behavior of a HARD reset is the same as a system
reset SYSRSn on the CLA. Writes of "0" are ignored and reads
always return a "0".
Reset type: SYSRSn
0h (R/W) = This bit always reads back 0 and writes of 0 are ignored.
1h (R/W) = Writing a 1 will cause a hard reset of the CLA. This will
set all CLA registers to their default state.

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8.8.4.10 _MVECTBGRNDACTIVE Register (Offset = 1Bh) [Reset = 0h]

_MVECTBGRNDACTIVE is shown in Figure 8-19 and described in Table 8-46.
Return to the Summary Table.
Gives the current interrupted MPC value of the background task, if the background task was running and
interrupted, or reflects the MVECTBGRND value, if MCTLBGRND.BGSTART bit is 0.
Figure 8-19. _MVECTBGRNDACTIVE Register
15 14 13 12 11 10 9 8
i16
R-0h

7 6 5 4 3 2 1 0
i16
R-0h

Table 8-46. _MVECTBGRNDACTIVE Register Field Descriptions

Bit Field Type Reset Description
15-0 i16 R 0h Gives the current interrupted MPC value of the background task,
if the background task was running and interrupted, or reflects the
MVECTBGRND value, if MCTLBGRND.BGSTART bit is 0.
Reset type: SYSRSn

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8.8.4.11 SOFTINTEN Register (Offset = 1Ch) [Reset = 0h]

SOFTINTEN is shown in Figure 8-20 and described in Table 8-47.
Return to the Summary Table.
Enables the ability to generate CLA task interrupt from within the task, by writing to SOFTINTFRC register.
SOFTINTFRC register can only be written from CLA. Only reads are allowed from CPU. Writes are not allowed
from CPU.
Figure 8-20. SOFTINTEN Register
15 14 13 12 11 10 9 8
RESERVED
R/W-0h

7 6 5 4 3 2 1 0
TASK8 TASK7 TASK6 TASK5 TASK4 TASK3 TASK2 TASK1
R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h

Table 8-47. SOFTINTEN Register Field Descriptions

Bit Field Type Reset Description
15-8 RESERVED R/W 0h Reserved
7 TASK8 R/W 0h 0: End-Of-Task Interrupt is fired for the respective task
1: Enable Software Interrupt for the respective task. End-of-Task
interrupt is not sent to CPU in this case.
Note: SOFTINTEN register is read only in the CPU memory map.
Reset type: SYSRSn
6 TASK7 R/W 0h 0: End-Of-Task Interrupt is fired for the respective task
1: Enable Software Interrupt for the respective task. End-of-Task
interrupt is not sent to CPU in this case.
Note: SOFTINTEN register is read only in the CPU memory map.
Reset type: SYSRSn
5 TASK6 R/W 0h 0: End-Of-Task Interrupt is fired for the respective task
1: Enable Software Interrupt for the respective task. End-of-Task
interrupt is not sent to CPU in this case.
Note: SOFTINTEN register is read only in the CPU memory map.
Reset type: SYSRSn
4 TASK5 R/W 0h 0: End-Of-Task Interrupt is fired for the respective task
1: Enable Software Interrupt for the respective task. End-of-Task
interrupt is not sent to CPU in this case.
Note: SOFTINTEN register is read only in the CPU memory map.
Reset type: SYSRSn
3 TASK4 R/W 0h 0: End-Of-Task Interrupt is fired for the respective task
1: Enable Software Interrupt for the respective task. End-of-Task
interrupt is not sent to CPU in this case.
Note: SOFTINTEN register is read only in the CPU memory map.
Reset type: SYSRSn
2 TASK3 R/W 0h 0: End-Of-Task Interrupt is fired for the respective task
1: Enable Software Interrupt for the respective task. End-of-Task
interrupt is not sent to CPU in this case.
Note: SOFTINTEN register is read only in the CPU memory map.
Reset type: SYSRSn
1 TASK2 R/W 0h 0: End-Of-Task Interrupt is fired for the respective task
1: Enable Software Interrupt for the respective task. End-of-Task
interrupt is not sent to CPU in this case.
Note: SOFTINTEN register is read only in the CPU memory map.
Reset type: SYSRSn

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Table 8-47. SOFTINTEN Register Field Descriptions (continued)

Bit Field Type Reset Description
0 TASK1 R/W 0h 0: End-Of-Task Interrupt is fired for the respective task
1: Enable Software Interrupt for the respective task. End-of-Task
interrupt is not sent to CPU in this case.
Note: SOFTINTEN register is read only in the CPU memory map.
Reset type: SYSRSn

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8.8.4.12 _MSTSBGRND Register (Offset = 1Dh) [Reset = 0h]

_MSTSBGRND is shown in Figure 8-21 and described in Table 8-48.
Return to the Summary Table.
Status bits for the backgrondtask.
Figure 8-21. _MSTSBGRND Register
15 14 13 12 11 10 9 8
RESERVED
R/W-0h

7 6 5 4 3 2 1 0
RESERVED BGOVF _BGINTM RUN
R/W-0h R/W1C-0h R-0h R-0h

Table 8-48. _MSTSBGRND Register Field Descriptions

Bit Field Type Reset Description
15-3 RESERVED R/W 0h Reserved
2 BGOVF R/W1C 0h Value of 1 indicates a hardware trigger (which is enabled) occurred
while the MCTLBGRND.BGSTART bit is set.
Writing a value of 1 to this bit clears the BGOVF bit.
Write of 0 has no effect,
Value of 0 indicates the background task trigger did not result in a
overflow.
Reset type: SYSRSn
1 _BGINTM R 0h Value of 1 indicates that backgroiund task will not be interrupted.
This bit is set when MSETC _BGINTM bit is executed.
Value of 0 indicates that background task can be interrupted.
Reset type: SYSRSn
0 RUN R 0h Value of 1 indicates that background task is running.
Value of 0 indicates that background task is not running.
Reset type: SYSRSn

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8.8.4.13 _MCTLBGRND Register (Offset = 1Eh) [Reset = 0h]

_MCTLBGRND is shown in Figure 8-22 and described in Table 8-49.
Return to the Summary Table.
Holds the configuration bits to start the background task, enable hardware trigger.
Figure 8-22. _MCTLBGRND Register
15 14 13 12 11 10 9 8
BGEN RESERVED
R/W-0h R/W-0h

7 6 5 4 3 2 1 0
RESERVED TRIGEN BGSTART
R/W-0h R/W-0h R/W1S-0h

Table 8-49. _MCTLBGRND Register Field Descriptions

Bit Field Type Reset Description
15 BGEN R/W 0h 0 Background task is disabled, BGSTART will not be set either in a
hardware trigger or by writing 1 to BGSTART bit.
1 Background task is enabled and MIER[INT8] will be cleared,
preventing task 8 from triggering.
Reset type: SYSRSn
14-2 RESERVED R/W 0h Reserved
1 TRIGEN R/W 0h Hardware trigger enable for the background task.
1 Hardware trigger is enabled.
0 Hardware trigger is disabled.
Note: Trigger source for the background task will be the same as that
for task 8
Reset type: SYSRSn
0 BGSTART R/W1S 0h Value of 1 will start the background task, provided there are no other
pending tasks.
- Value of 0 has no effect if the background task has not started.
- This bit is also set by hardware, if MCTLBGRND.TRIGEN = 1 and a
hardware trigger occurs.
- This bit is cleared by hardware when a MSTOP instruction occurs in
the background task
- If the background task is running and this bit is cleared, it will not
have any effect on the task execution.
Reset type: SYSRSn

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8.8.4.14 _MVECTBGRND Register (Offset = 1Fh) [Reset = 0h]

_MVECTBGRND is shown in Figure 8-23 and described in Table 8-50.
Return to the Summary Table.
These bits specify the start address for the background task . The value in this register is forced into the MPC
register when the background task starts.
Figure 8-23. _MVECTBGRND Register
15 14 13 12 11 10 9 8
i16
R/W-0h

7 6 5 4 3 2 1 0
i16
R/W-0h

Table 8-50. _MVECTBGRND Register Field Descriptions

Bit Field Type Reset Description
15-0 i16 R/W 0h MPC Start Address: These bits specify the start address for the
background task . The value in this register is forced into the MPC
register, when the background task starts.
Reset type: SYSRSn

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8.8.4.15 MIFR Register (Offset = 20h) [Reset = 0h]

MIFR is shown in Figure 8-24 and described in Table 8-51.
Return to the Summary Table.
Each bit in the interrupt flag register corresponds to a CLA task. The corresponding bit is automatically set
when the task request is received from the peripheral interrupt. The bit can also be set by the main CPU
writing to the MIFRC register or using the IACK instruction to start the task. To use the IACK instruction to
begin a task first enable this feature in the MCTL register. If the bit is already set when a new peripheral
interrupt is received, then the corresponding overflow bit will be set in the MIOVF register.
The corresponding MIFR bit is automatically cleared when the task begins execution. This will occur if the
interrupt is enabled in the MIER register and no other higher priority task is pending. The bits can also be
cleared manually by writing to the MICLR register. Writes to the MIFR register are ignored.
Figure 8-24. MIFR Register
15 14 13 12 11 10 9 8
RESERVED
R-0h

7 6 5 4 3 2 1 0
INT8 INT7 INT6 INT5 INT4 INT3 INT2 INT1
R-0h R-0h R-0h R-0h R-0h R-0h R-0h R-0h

Table 8-51. MIFR Register Field Descriptions

Bit Field Type Reset Description
15-8 RESERVED R 0h Reserved
7 INT8 R 0h These bits, when set to "1", indicate a valid peripheral interrupt has
been latched by the CLA. Writes to this register are ignored.
The IFR flag bit is automatically cleared if the respective interrupt is
enabled in the MIER register and the respective task starts running.
If a new peripheral interrupt attempts to set the bit to "1" while on the
same cycle the task tries to clear it, then the peripheral interrupt will
have priority.
The IFR flag bits can also be set and cleared by the MIFRC and
MICLR registers.
If the MIFRC register is trying to set the respective bit while a new
task tries to clear it, then the MIFRC event has priority.
If the MICLR register is trying to clear the respective bit and a
peripheral interrupt occurs on the same cycle, then the peripheral
interrupt has priority. The respective overflow flag in the MIOVF
register will not be set under this condition.
Reset type: SYSRSn
0h (R/W) = TASK_FLAG_DISABLE
Task 8 interrupt is currently not flagged (default)
1h (R/W) = TASK_FLAG_ENABLE
Task 8 interrupt has been received and is pending execution

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Table 8-51. MIFR Register Field Descriptions (continued)

Bit Field Type Reset Description
6 INT7 R 0h These bits, when set to "1", indicate a valid peripheral interrupt has
been latched by the CLA. Writes to this register are ignored.
The IFR flag bit is automatically cleared if the respective interrupt is
enabled in the MIER register and the respective task starts running.
If a new peripheral interrupt attempts to set the bit to "1" while on the
same cycle the task tries to clear it, then the peripheral interrupt will
have priority.
The IFR flag bits can also be set and cleared by the MIFRC and
MICLR registers.
If the MIFRC register is trying to set the respective bit while a new
task tries to clear it, then the MIFRC event has priority.
If the MICLR register is trying to clear the respective bit and a
peripheral interrupt occurs on the same cycle, then the peripheral
interrupt has priority. The respective overflow flag in the MIOVF
register will not be set under this condition.
Reset type: SYSRSn
0h (R/W) = TASK_FLAG_DISABLE
Task 7 interrupt is currently not flagged (default)
1h (R/W) = TASK_FLAG_ENABLE
Task 7 interrupt has been received and is pending execution
5 INT6 R 0h These bits, when set to "1", indicate a valid peripheral interrupt has
been latched by the CLA. Writes to this register are ignored.
The IFR flag bit is automatically cleared if the respective interrupt is
enabled in the MIER register and the respective task starts running.
If a new peripheral interrupt attempts to set the bit to "1" while on the
same cycle the task tries to clear it, then the peripheral interrupt will
have priority.
The IFR flag bits can also be set and cleared by the MIFRC and
MICLR registers.
If the MIFRC register is trying to set the respective bit while a new
task tries to clear it, then the MIFRC event has priority.
If the MICLR register is trying to clear the respective bit and a
peripheral interrupt occurs on the same cycle, then the peripheral
interrupt has priority. The respective overflow flag in the MIOVF
register will not be set under this condition.
Reset type: SYSRSn
0h (R/W) = TASK_FLAG_DISABLE
Task 6 interrupt is currently not flagged (default)
1h (R/W) = TASK_FLAG_ENABLE
Task 6 interrupt has been received and is pending execution
4 INT5 R 0h These bits, when set to "1", indicate a valid peripheral interrupt has
been latched by the CLA. Writes to this register are ignored.
The IFR flag bit is automatically cleared if the respective interrupt is
enabled in the MIER register and the respective task starts running.
If a new peripheral interrupt attempts to set the bit to "1" while on the
same cycle the task tries to clear it, then the peripheral interrupt will
have priority.
The IFR flag bits can also be set and cleared by the MIFRC and
MICLR registers.
If the MIFRC register is trying to set the respective bit while a new
task tries to clear it, then the MIFRC event has priority.
If the MICLR register is trying to clear the respective bit and a
peripheral interrupt occurs on the same cycle, then the peripheral
interrupt has priority. The respective overflow flag in the MIOVF
register will not be set under this condition.
Reset type: SYSRSn
0h (R/W) = TASK_FLAG_DISABLE
Task 5 interrupt is currently not flagged (default)
1h (R/W) = TASK_FLAG_ENABLE
Task 5 interrupt has been received and is pending execution

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Table 8-51. MIFR Register Field Descriptions (continued)

Bit Field Type Reset Description
3 INT4 R 0h These bits, when set to "1", indicate a valid peripheral interrupt has
been latched by the CLA. Writes to this register are ignored.
The IFR flag bit is automatically cleared if the respective interrupt is
enabled in the MIER register and the respective task starts running.
If a new peripheral interrupt attempts to set the bit to "1" while on the
same cycle the task tries to clear it, then the peripheral interrupt will
have priority.
The IFR flag bits can also be set and cleared by the MIFRC and
MICLR registers.
If the MIFRC register is trying to set the respective bit while a new
task tries to clear it, then the MIFRC event has priority.
If the MICLR register is trying to clear the respective bit and a
peripheral interrupt occurs on the same cycle, then the peripheral
interrupt has priority. The respective overflow flag in the MIOVF
register will not be set under this condition.
Reset type: SYSRSn
0h (R/W) = TASK_FLAG_DISABLE
Task 4 interrupt is currently not flagged (default)
1h (R/W) = TASK_FLAG_ENABLE
Task 4 interrupt has been received and is pending execution
2 INT3 R 0h These bits, when set to "1", indicate a valid peripheral interrupt has
been latched by the CLA. Writes to this register are ignored.
The IFR flag bit is automatically cleared if the respective interrupt is
enabled in the MIER register and the respective task starts running.
If a new peripheral interrupt attempts to set the bit to "1" while on the
same cycle the task tries to clear it, then the peripheral interrupt will
have priority.
The IFR flag bits can also be set and cleared by the MIFRC and
MICLR registers.
If the MIFRC register is trying to set the respective bit while a new
task tries to clear it, then the MIFRC event has priority.
If the MICLR register is trying to clear the respective bit and a
peripheral interrupt occurs on the same cycle, then the peripheral
interrupt has priority. The respective overflow flag in the MIOVF
register will not be set under this condition.
Reset type: SYSRSn
0h (R/W) = TASK_FLAG_DISABLE
Task 3 interrupt is currently not flagged (default)
1h (R/W) = TASK_FLAG_ENABLE
Task 3 interrupt has been received and is pending execution
1 INT2 R 0h These bits, when set to "1", indicate a valid peripheral interrupt has
been latched by the CLA. Writes to this register are ignored.
The IFR flag bit is automatically cleared if the respective interrupt is
enabled in the MIER register and the respective task starts running.
If a new peripheral interrupt attempts to set the bit to "1" while on the
same cycle the task tries to clear it, then the peripheral interrupt will
have priority.
The IFR flag bits can also be set and cleared by the MIFRC and
MICLR registers.
If the MIFRC register is trying to set the respective bit while a new
task tries to clear it, then the MIFRC event has priority.
If the MICLR register is trying to clear the respective bit and a
peripheral interrupt occurs on the same cycle, then the peripheral
interrupt has priority. The respective overflow flag in the MIOVF
register will not be set under this condition.
Reset type: SYSRSn
0h (R/W) = TASK_FLAG_DISABLE
Task 2 interrupt is currently not flagged (default)
1h (R/W) = TASK_FLAG_ENABLE
Task 2 interrupt has been received and is pending execution

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Table 8-51. MIFR Register Field Descriptions (continued)

Bit Field Type Reset Description
0 INT1 R 0h These bits, when set to "1", indicate a valid peripheral interrupt has
been latched by the CLA. Writes to this register are ignored.
The IFR flag bit is automatically cleared if the respective interrupt is
enabled in the MIER register and the respective task starts running.
If a new peripheral interrupt attempts to set the bit to "1" while on the
same cycle the task tries to clear it, then the peripheral interrupt will
have priority.
The IFR flag bits can also be set and cleared by the MIFRC and
MICLR registers.
If the MIFRC register is trying to set the respective bit while a new
task tries to clear it, then the MIFRC event has priority.
If the MICLR register is trying to clear the respective bit and a
peripheral interrupt occurs on the same cycle, then the peripheral
interrupt has priority. The respective overflow flag in the MIOVF
register will not be set under this condition.
Reset type: SYSRSn
0h (R/W) = TASK_FLAG_DISABLE
Task 1 interrupt is currently not flagged (default)
1h (R/W) = TASK_FLAG_ENABLE
Task 1 interrupt has been received and is pending execution

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8.8.4.16 MIOVF Register (Offset = 21h) [Reset = 0h]

MIOVF is shown in Figure 8-25 and described in Table 8-52.
Return to the Summary Table.
Each bit in the overflow flag register corresponds to a CLA task. The bit is set when an interrupt overflow
event has occurred for the specific task. An overflow event occurs when the MIFR register bit is already
set when a new interrupt is received from a peripheral source. The MIOVF bits are only affected by
peripheral interrupt events. They do not respond to a task request by the main CPU IACK instruction or by
directly setting MIFR bits. The overflow flag will remain latched and can only be cleared by writing to the
overflow flag clear (MICLROVF) register. Writes to the MIOVF register are ignored.
Figure 8-25. MIOVF Register
15 14 13 12 11 10 9 8
RESERVED
R-0h

7 6 5 4 3 2 1 0
INT8 INT7 INT6 INT5 INT4 INT3 INT2 INT1
R-0h R-0h R-0h R-0h R-0h R-0h R-0h R-0h

Table 8-52. MIOVF Register Field Descriptions

Bit Field Type Reset Description
15-8 RESERVED R 0h Reserved
7 INT8 R 0h These bits, when set to "1", indicate an interrupt overflow event
occurred. Such an event occurs when the IFR bit is already set.
An overflow event remains latched and respective bits can only be
cleared by writing to the MICLROVF register.
If the MIFR bit is being cleared by a new task on the same cycle as a
new peripheral interrupt occurs, the overflow flag will not be affected
and the respective MIFR bit will be set.
If the MIOVF bit is being cleared by the MICLROVF register on the
same cycle as the overflow bit is being set by hardware, then the
hardware will have priority.
Notes: [1] The MIOVF bits are only affected by peripheral interrupt
events. Forcing an interrupt using the MIFRC or IACK operation will
not set the overflow flag even if the MIFR bit is set.
Reset type: SYSRSn
0h (R/W) = A task 8 interrupt overflow has not occurred (default)
1h (R/W) = A task 8 interrupt overflow has occurred
6 INT7 R 0h These bits, when set to "1", indicate an interrupt overflow event
occurred. Such an event occurs when the IFR bit is already set.
An overflow event remains latched and respective bits can only be
cleared by writing to the MICLROVF register.
If the MIFR bit is being cleared by a new task on the same cycle as a
new peripheral interrupt occurs, the overflow flag will not be affected
and the respective MIFR bit will be set.
If the MIOVF bit is being cleared by the MICLROVF register on the
same cycle as the overflow bit is being set by hardware, then the
hardware will have priority.
Notes: [1] The MIOVF bits are only affected by peripheral interrupt
events. Forcing an interrupt using the MIFRC or IACK operation will
not set the overflow flag even if the MIFR bit is set.
Reset type: SYSRSn
0h (R/W) = A task 7 interrupt overflow has not occurred (default)
1h (R/W) = A task 7 interrupt overflow has occurred

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Table 8-52. MIOVF Register Field Descriptions (continued)

Bit Field Type Reset Description
5 INT6 R 0h These bits, when set to "1", indicate an interrupt overflow event
occurred. Such an event occurs when the IFR bit is already set.
An overflow event remains latched and respective bits can only be
cleared by writing to the MICLROVF register.
If the MIFR bit is being cleared by a new task on the same cycle as a
new peripheral interrupt occurs, the overflow flag will not be affected
and the respective MIFR bit will be set.
If the MIOVF bit is being cleared by the MICLROVF register on the
same cycle as the overflow bit is being set by hardware, then the
hardware will have priority.
Notes: [1] The MIOVF bits are only affected by peripheral interrupt
events. Forcing an interrupt using the MIFRC or IACK operation will
not set the overflow flag even if the MIFR bit is set.
Reset type: SYSRSn
0h (R/W) = A task 6 interrupt overflow has not occurred (default)
1h (R/W) = A task 6 interrupt overflow has occurred
4 INT5 R 0h These bits, when set to "1", indicate an interrupt overflow event
occurred. Such an event occurs when the IFR bit is already set.
An overflow event remains latched and respective bits can only be
cleared by writing to the MICLROVF register.
If the MIFR bit is being cleared by a new task on the same cycle as a
new peripheral interrupt occurs, the overflow flag will not be affected
and the respective MIFR bit will be set.
If the MIOVF bit is being cleared by the MICLROVF register on the
same cycle as the overflow bit is being set by hardware, then the
hardware will have priority.
Notes: [1] The MIOVF bits are only affected by peripheral interrupt
events. Forcing an interrupt using the MIFRC or IACK operation will
not set the overflow flag even if the MIFR bit is set.
Reset type: SYSRSn
0h (R/W) = A task 5 interrupt overflow has not occurred (default)
1h (R/W) = A task 5 interrupt overflow has occurred
3 INT4 R 0h These bits, when set to "1", indicate an interrupt overflow event
occurred. Such an event occurs when the IFR bit is already set.
An overflow event remains latched and respective bits can only be
cleared by writing to the MICLROVF register.
If the MIFR bit is being cleared by a new task on the same cycle as a
new peripheral interrupt occurs, the overflow flag will not be affected
and the respective MIFR bit will be set.
If the MIOVF bit is being cleared by the MICLROVF register on the
same cycle as the overflow bit is being set by hardware, then the
hardware will have priority.
Notes: [1] The MIOVF bits are only affected by peripheral interrupt
events. Forcing an interrupt using the MIFRC or IACK operation will
not set the overflow flag even if the MIFR bit is set.
Reset type: SYSRSn
0h (R/W) = A task 4 interrupt overflow has not occurred (default)
1h (R/W) = A task 4 interrupt overflow has occurred
2 INT3 R 0h These bits, when set to "1", indicate an interrupt overflow event
occurred. Such an event occurs when the IFR bit is already set.
An overflow event remains latched and respective bits can only be
cleared by writing to the MICLROVF register.
If the MIFR bit is being cleared by a new task on the same cycle as a
new peripheral interrupt occurs, the overflow flag will not be affected
and the respective MIFR bit will be set.
If the MIOVF bit is being cleared by the MICLROVF register on the
same cycle as the overflow bit is being set by hardware, then the
hardware will have priority.
Notes: [1] The MIOVF bits are only affected by peripheral interrupt
events. Forcing an interrupt using the MIFRC or IACK operation will
not set the overflow flag even if the MIFR bit is set.
Reset type: SYSRSn
0h (R/W) = A task 3 interrupt overflow has not occurred (default)
1h (R/W) = A task 3 interrupt overflow has occurred

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Table 8-52. MIOVF Register Field Descriptions (continued)

Bit Field Type Reset Description
1 INT2 R 0h These bits, when set to "1", indicate an interrupt overflow event
occurred. Such an event occurs when the IFR bit is already set.
An overflow event remains latched and respective bits can only be
cleared by writing to the MICLROVF register.
If the MIFR bit is being cleared by a new task on the same cycle as a
new peripheral interrupt occurs, the overflow flag will not be affected
and the respective MIFR bit will be set.
If the MIOVF bit is being cleared by the MICLROVF register on the
same cycle as the overflow bit is being set by hardware, then the
hardware will have priority.
Notes: [1] The MIOVF bits are only affected by peripheral interrupt
events. Forcing an interrupt using the MIFRC or IACK operation will
not set the overflow flag even if the MIFR bit is set.
Reset type: SYSRSn
0h (R/W) = A task 2 interrupt overflow has not occurred (default)
1h (R/W) = A task 2 interrupt overflow has occurred
0 INT1 R 0h These bits, when set to "1", indicate an interrupt overflow event
occurred. Such an event occurs when the IFR bit is already set.
An overflow event remains latched and respective bits can only be
cleared by writing to the MICLROVF register.
If the MIFR bit is being cleared by a new task on the same cycle as a
new peripheral interrupt occurs, the overflow flag will not be affected
and the respective MIFR bit will be set.
If the MIOVF bit is being cleared by the MICLROVF register on the
same cycle as the overflow bit is being set by hardware, then the
hardware will have priority.
Notes: [1] The MIOVF bits are only affected by peripheral interrupt
events. Forcing an interrupt using the MIFRC or IACK operation will
not set the overflow flag even if the MIFR bit is set.
Reset type: SYSRSn
0h (R/W) = A task 1 interrupt overflow has not occurred (default)
1h (R/W) = A task 1 interrupt overflow has occurred

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8.8.4.17 MIFRC Register (Offset = 22h) [Reset = 0h]

MIFRC is shown in Figure 8-26 and described in Table 8-53.
Return to the Summary Table.
The interrupt force register can be used by the main CPU to start tasks through software. Writing a 1 to a
MIFRC bit will set the corresponding bit in the MIFR register. Writes of 0 are ignored and reads always
return 0. The IACK #16bit operation can also be used to start tasks and has the same effect as the
MIFRC register. To enable IACK to set MIFR bits you must first set the MCTL[IACKE] bit. Using IACK has
the advantage of not having to first set the EALLOW bit. This allows the main CPU to efficiently trigger
CLA tasks through software.
Figure 8-26. MIFRC Register
15 14 13 12 11 10 9 8
RESERVED
R-0h

7 6 5 4 3 2 1 0
INT8 INT7 INT6 INT5 INT4 INT3 INT2 INT1
R-0/W1S-0h R-0/W1S-0h R-0/W1S-0h R-0/W1S-0h R-0/W1S-0h R-0/W1S-0h R-0/W1S-0h R-0/W1S-0h

Table 8-53. MIFRC Register Field Descriptions

Bit Field Type Reset Description
15-8 RESERVED R 0h Reserved
7 INT8 R-0/W1S 0h Writing a "1" to any of the bits will set the corresponding MIFR bit.
Writes of "0" are ignored. Reads always return 0.
Notes: [1] Refer to MIFR register description for handling of
boundary conditions.
Reset type: SYSRSn
0h (R/W) = This bit always reads back 0 and writes of 0 have no
effect
1h (R/W) = Write a 1 to force the task 8 interrupt
6 INT7 R-0/W1S 0h Writing a "1" to any of the bits will set the corresponding MIFR bit.
Writes of "0" are ignored. Reads always return 0.
Notes: [1] Refer to MIFR register description for handling of
boundary conditions.
Reset type: SYSRSn
0h (R/W) = This bit always reads back 0 and writes of 0 have no
effect
1h (R/W) = Write a 1 to force the task 7 interrupt
5 INT6 R-0/W1S 0h Writing a "1" to any of the bits will set the corresponding MIFR bit.
Writes of "0" are ignored. Reads always return 0.
Notes: [1] Refer to MIFR register description for handling of
boundary conditions.
Reset type: SYSRSn
0h (R/W) = This bit always reads back 0 and writes of 0 have no
effect
1h (R/W) = Write a 1 to force the task 6 interrupt
4 INT5 R-0/W1S 0h Writing a "1" to any of the bits will set the corresponding MIFR bit.
Writes of "0" are ignored. Reads always return 0.
Notes: [1] Refer to MIFR register description for handling of
boundary conditions.
Reset type: SYSRSn
0h (R/W) = This bit always reads back 0 and writes of 0 have no
effect
1h (R/W) = Write a 1 to force the task 5 interrupt

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Table 8-53. MIFRC Register Field Descriptions (continued)

Bit Field Type Reset Description
3 INT4 R-0/W1S 0h Writing a "1" to any of the bits will set the corresponding MIFR bit.
Writes of "0" are ignored. Reads always return 0.
Notes: [1] Refer to MIFR register description for handling of
boundary conditions.
Reset type: SYSRSn
0h (R/W) = This bit always reads back 0 and writes of 0 have no
effect
1h (R/W) = Write a 1 to force the task 4 interrupt
2 INT3 R-0/W1S 0h Writing a "1" to any of the bits will set the corresponding MIFR bit.
Writes of "0" are ignored. Reads always return 0.
Notes: [1] Refer to MIFR register description for handling of
boundary conditions.
Reset type: SYSRSn
0h (R/W) = This bit always reads back 0 and writes of 0 have no
effect
1h (R/W) = Write a 1 to force the task 3 interrupt
1 INT2 R-0/W1S 0h Writing a "1" to any of the bits will set the corresponding MIFR bit.
Writes of "0" are ignored. Reads always return 0.
Notes: [1] Refer to MIFR register description for handling of
boundary conditions.
Reset type: SYSRSn
0h (R/W) = This bit always reads back 0 and writes of 0 have no
effect
1h (R/W) = Write a 1 to force the task 2 interrupt
0 INT1 R-0/W1S 0h Writing a "1" to any of the bits will set the corresponding MIFR bit.
Writes of "0" are ignored. Reads always return 0.
Notes: [1] Refer to MIFR register description for handling of
boundary conditions.
Reset type: SYSRSn
0h (R/W) = This bit always reads back 0 and writes of 0 have no
effect
1h (R/W) = Write a 1 to force the task 1 interrupt

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8.8.4.18 MICLR Register (Offset = 23h) [Reset = 0h]

MICLR is shown in Figure 8-27 and described in Table 8-54.
Return to the Summary Table.
Normally bits in the MIFR register are automatically cleared when a task begins. The interrupt flag clear
register can be used to instead manually clear bits in the interrupt flag (MIFR) register. Writing a 1 to a
MICLR bit will clear the corresponding bit in the MIFR register. Writes of 0 are ignored and reads always
return 0.
Figure 8-27. MICLR Register
15 14 13 12 11 10 9 8
RESERVED
R-0h

7 6 5 4 3 2 1 0
INT8 INT7 INT6 INT5 INT4 INT3 INT2 INT1
R-0/W1S-0h R-0/W1S-0h R-0/W1S-0h R-0/W1S-0h R-0/W1S-0h R-0/W1S-0h R-0/W1S-0h R-0/W1S-0h

Table 8-54. MICLR Register Field Descriptions

Bit Field Type Reset Description
15-8 RESERVED R 0h Reserved
7 INT8 R-0/W1S 0h Writing a "1" to any of the bits will clear the corresponding MIFR bit.
Writes of "0" are ignored. Reads always return 0.
Notes: [1] Refer to MIFR register description for handling of
boundary conditions.
Reset type: SYSRSn
0h (R/W) = This bit always reads back 0 and writes of 0 have no
effect
1h (R/W) = Write a 1 to clear the task 8 interrupt flag
6 INT7 R-0/W1S 0h Writing a "1" to any of the bits will clear the corresponding MIFR bit.
Writes of "0" are ignored. Reads always return 0.
Notes: [1] Refer to MIFR register description for handling of
boundary conditions.
Reset type: SYSRSn
0h (R/W) = This bit always reads back 0 and writes of 0 have no
effect
1h (R/W) = Write a 1 to clear the task 7 interrupt flag
5 INT6 R-0/W1S 0h Writing a "1" to any of the bits will clear the corresponding MIFR bit.
Writes of "0" are ignored. Reads always return 0.
Notes: [1] Refer to MIFR register description for handling of
boundary conditions.
Reset type: SYSRSn
0h (R/W) = This bit always reads back 0 and writes of 0 have no
effect
1h (R/W) = Write a 1 to clear the task 6 interrupt flag
4 INT5 R-0/W1S 0h Writing a "1" to any of the bits will clear the corresponding MIFR bit.
Writes of "0" are ignored. Reads always return 0.
Notes: [1] Refer to MIFR register description for handling of
boundary conditions.
Reset type: SYSRSn
0h (R/W) = This bit always reads back 0 and writes of 0 have no
effect
1h (R/W) = Write a 1 to clear the task 5 interrupt flag

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Table 8-54. MICLR Register Field Descriptions (continued)

Bit Field Type Reset Description
3 INT4 R-0/W1S 0h Writing a "1" to any of the bits will clear the corresponding MIFR bit.
Writes of "0" are ignored. Reads always return 0.
Notes: [1] Refer to MIFR register description for handling of
boundary conditions.
Reset type: SYSRSn
0h (R/W) = This bit always reads back 0 and writes of 0 have no
effect
1h (R/W) = Write a 1 to clear the task 4 interrupt flag
2 INT3 R-0/W1S 0h Writing a "1" to any of the bits will clear the corresponding MIFR bit.
Writes of "0" are ignored. Reads always return 0.
Notes: [1] Refer to MIFR register description for handling of
boundary conditions.
Reset type: SYSRSn
0h (R/W) = This bit always reads back 0 and writes of 0 have no
effect
1h (R/W) = Write a 1 to clear the task 3 interrupt flag
1 INT2 R-0/W1S 0h Writing a "1" to any of the bits will clear the corresponding MIFR bit.
Writes of "0" are ignored. Reads always return 0.
Notes: [1] Refer to MIFR register description for handling of
boundary conditions.
Reset type: SYSRSn
0h (R/W) = This bit always reads back 0 and writes of 0 have no
effect
1h (R/W) = Write a 1 to clear the task 2 interrupt flag
0 INT1 R-0/W1S 0h Writing a "1" to any of the bits will clear the corresponding MIFR bit.
Writes of "0" are ignored. Reads always return 0.
Notes: [1] Refer to MIFR register description for handling of
boundary conditions.
Reset type: SYSRSn
0h (R/W) = This bit always reads back 0 and writes of 0 have no
effect
1h (R/W) = Write a 1 to clear the task 1 interrupt flag

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8.8.4.19 MICLROVF Register (Offset = 24h) [Reset = 0h]

MICLROVF is shown in Figure 8-28 and described in Table 8-55.
Return to the Summary Table.
Overflow flag bits in the MIOVF register are latched until manually cleared using the MICLROVF register.
Writing a 1 to a MICLROVF bit will clear the corresponding bit in the MIOVF register. Writes of 0 are
ignored and reads always return 0.
Figure 8-28. MICLROVF Register
15 14 13 12 11 10 9 8
RESERVED
R-0h

7 6 5 4 3 2 1 0
INT8 INT7 INT6 INT5 INT4 INT3 INT2 INT1
R-0/W1S-0h R-0/W1S-0h R-0/W1S-0h R-0/W1S-0h R-0/W1S-0h R-0/W1S-0h R-0/W1S-0h R-0/W1S-0h

Table 8-55. MICLROVF Register Field Descriptions

Bit Field Type Reset Description
15-8 RESERVED R 0h Reserved
7 INT8 R-0/W1S 0h Writing a "1" to any of the bits will clear the corresponding MIOVF bit.
Writes of "0" are ignored. Reads always return 0.
Notes: [1] Refer to MIOVF register description for handling of
boundary conditions.
Reset type: SYSRSn
0h (R/W) = This bit always reads back 0 and writes of 0 have no
effect
1h (R/W) = Write a 1 to clear the task 8 interrupt overflow flag
6 INT7 R-0/W1S 0h Writing a "1" to any of the bits will clear the corresponding MIOVF bit.
Writes of "0" are ignored. Reads always return 0.
Notes: [1] Refer to MIOVF register description for handling of
boundary conditions.
Reset type: SYSRSn
0h (R/W) = This bit always reads back 0 and writes of 0 have no
effect
1h (R/W) = Write a 1 to clear the task 7 interrupt overflow flag
5 INT6 R-0/W1S 0h Writing a "1" to any of the bits will clear the corresponding MIOVF bit.
Writes of "0" are ignored. Reads always return 0.
Notes: [1] Refer to MIOVF register description for handling of
boundary conditions.
Reset type: SYSRSn
0h (R/W) = This bit always reads back 0 and writes of 0 have no
effect
1h (R/W) = Write a 1 to clear the task 6 interrupt overflow flag
4 INT5 R-0/W1S 0h Writing a "1" to any of the bits will clear the corresponding MIOVF bit.
Writes of "0" are ignored. Reads always return 0.
Notes: [1] Refer to MIOVF register description for handling of
boundary conditions.
Reset type: SYSRSn
0h (R/W) = This bit always reads back 0 and writes of 0 have no
effect
1h (R/W) = Write a 1 to clear the task 5 interrupt overflow flag
3 INT4 R-0/W1S 0h Writing a "1" to any of the bits will clear the corresponding MIOVF bit.
Writes of "0" are ignored. Reads always return 0.
Notes: [1] Refer to MIOVF register description for handling of
boundary conditions.
Reset type: SYSRSn
0h (R/W) = This bit always reads back 0 and writes of 0 have no
effect
1h (R/W) = Write a 1 to clear the task 4 interrupt overflow flag

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Table 8-55. MICLROVF Register Field Descriptions (continued)

Bit Field Type Reset Description
2 INT3 R-0/W1S 0h Writing a "1" to any of the bits will clear the corresponding MIOVF bit.
Writes of "0" are ignored. Reads always return 0.
Notes: [1] Refer to MIOVF register description for handling of
boundary conditions.
Reset type: SYSRSn
0h (R/W) = This bit always reads back 0 and writes of 0 have no
effect
1h (R/W) = Write a 1 to clear the task 3 interrupt overflow flag
1 INT2 R-0/W1S 0h Writing a "1" to any of the bits will clear the corresponding MIOVF bit.
Writes of "0" are ignored. Reads always return 0.
Notes: [1] Refer to MIOVF register description for handling of
boundary conditions.
Reset type: SYSRSn
0h (R/W) = This bit always reads back 0 and writes of 0 have no
effect
1h (R/W) = Write a 1 to clear the task 2 interrupt overflow flag
0 INT1 R-0/W1S 0h Writing a "1" to any of the bits will clear the corresponding MIOVF bit.
Writes of "0" are ignored. Reads always return 0.
Notes: [1] Refer to MIOVF register description for handling of
boundary conditions.
Reset type: SYSRSn
0h (R/W) = This bit always reads back 0 and writes of 0 have no
effect
1h (R/W) = Write a 1 to clear the task 1 interrupt overflow flag

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8.8.4.20 MIER Register (Offset = 25h) [Reset = 0h]

MIER is shown in Figure 8-29 and described in Table 8-56.
Return to the Summary Table.
Setting the bits in the interrupt enable register (MIER) allow an incoming interrupt or main CPU software to
start the corresponding CLA task. Writing a 0 will block the task, but the interrupt request will still be
latched in the flag register (MIFLG). Setting the MIER register bit to 0 while the corresponding task is
executing will have no effect on the task. The task will continue to run until it hits the MSTOP instruction.
When a soft reset is issued, the MIER bits are cleared. There should always be at least a 1 SYSCLKOUT
delay between issuing the soft reset and reconfiguring the MIER bits.
Figure 8-29. MIER Register
15 14 13 12 11 10 9 8
RESERVED
R-0h

7 6 5 4 3 2 1 0
INT8 INT7 INT6 INT5 INT4 INT3 INT2 INT1
R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h

Table 8-56. MIER Register Field Descriptions

Bit Field Type Reset Description
15-8 RESERVED R 0h Reserved
7 INT8 R/W 0h Setting any of the bits to "1" enables the corresponding interrupt
from triggering a corresponding CLA task. Writing a "0" blocks the
interrupt, but the interrupt can still be latched by the MIFR register.
When an interrupt is enabled and the corresponding MIFR bit is
set to "1", the CLA will start executing the corresponding task and
automatically clear the corresponding MIFR bit.
Interrupts are be serviced in normal priority order.
Notes: [1] If a task is currently executing and the corresponding
MIER bit is cleared to "0", it will have no effect on the task. The task
will run until it hits the STOP instruction.
Reset type: SYSRSn
0h (R/W) = TASK_INT_DISABLE
Task 8 interrupt is disabled (default)
1h (R/W) = TASK_INT_ENABLE
Task 8 interrupt is enabled
6 INT7 R/W 0h Setting any of the bits to "1" enables the corresponding interrupt
from triggering a corresponding CLA task. Writing a "0" blocks the
interrupt, but the interrupt can still be latched by the MIFR register.
When an interrupt is enabled and the corresponding MIFR bit is
set to "1", the CLA will start executing the corresponding task and
automatically clear the corresponding MIFR bit.
Interrupts are be serviced in normal priority order.
Notes: [1] If a task is currently executing and the corresponding
MIER bit is cleared to "0", it will have no effect on the task. The task
will run until it hits the STOP instruction.
Reset type: SYSRSn
0h (R/W) = TASK_INT_DISABLE
Task 7 interrupt is disabled (default)
1h (R/W) = TASK_INT_ENABLE
Task 7 interrupt is enabled

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Table 8-56. MIER Register Field Descriptions (continued)

Bit Field Type Reset Description
5 INT6 R/W 0h Setting any of the bits to "1" enables the corresponding interrupt