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Chapter III: Implementation Technology

• In this chapter, we will cover the following topics:

– MOS and CMOS implementations of logic gates.

– Programmable logic array (PLA).

– Programmable Array Logic (PAL).

– Complex programmable logic device (CPLD).

– Field programmable gate array (FPGA).

– Custom chip design.

– Application specific integrated circuits and gate arrays.

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MOSFET Technology:
• By now, you should be familiar with the metal-oxide-
silicon-field-effect-transistor (MOSFET).
• There are two
types of
MOSFET: NMOS
and PMOS.
• An NMOS
operates in
saturation
mode when
𝑽𝑫𝑺 ≥ 𝑽𝑮𝑺 − 𝑽𝒕
and in cut-off
mode when
𝑽𝑫𝑺 < 𝑽𝒕 .
• The PMOS is
inverted.

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The NOT Gate:

• In order to implement the
NOT gate, consider the
circuit shown here.
• When 𝑽𝒙 is high, the NMOS
shorts and 𝑽𝒇 = 𝟎 as it is
shorted to ground.
• The resistor is used to limit the
current flowing in the circuit.
• When 𝑽𝒙 is low, the NMOS
cuts off and 𝑽𝒇 = 𝟓𝑽 as no
current flows.
• The circuit is usually drawn in
a simplified manner.
• The dashed line is used to
indicate that the resistor is in
fact a transistor!
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The NAND & NOR Gates:

• We saw in EE211 that all logic
circuits can be represented
using only NAND or NOR gates.
• Consider connecting a
second NMOS in series.
• In this case, for the output 𝑽𝒇
to be low, both transistors must
be closed (saturation mode),
which means that 𝑽𝒙𝟏 = 𝑽𝒙𝟐
= 𝟓𝑽. Otherwise, the output
will be high.
• If the second NMOS is in
parallel, the output will only be
high if both transistors are
open (cut-off mode), which
means 𝑽𝒙𝟏 = 𝑽𝒙𝟐 = 𝟎𝑽.

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The AND & OR Gates:

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CMOS Implementation:
• Complementary MOS using NMOS in conjunction
with PMOS.
• In the circuit shown on the right, the two transistors
operate in opposite modes. They forma NOT gate.
• The NAND gate is shown on the left.
• To examine the result, you must check
each of the 4 transistors.

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CMOS Implementation:
• Below are the NAND and NOR gates implemented
in CMOS technology:

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CMOS Implementation:
• The AND gate
requires two more
transistors.
• This is the main
reason why NAND-
only and NOR-only
logic is preferred.
• Can you derive the
truth table for it?

𝒙𝟏 𝒙𝟐 𝑻𝟏 𝑻𝟐 𝑻𝟑 𝑻𝟒 𝑻𝟓 𝑻𝟔 𝒇

0 0 …… …… …… …… …… …… …
0 1 …… …… …… …… …… …… …
1 0 …… …… …… …… …… …… …
1 1 …… …… …… …… …… …… …

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Custom Logic Design:

• Any logic function can be
implemented by means of
CMOS transistors.
• Consider the function
𝒇 𝒙𝟏 , 𝒙𝟐 , 𝒙𝟑 = 𝒙′𝟏 + 𝒙′𝟐 𝒙′𝟑 .
• This function can be
implemented as shown
here.
• However, no systematic
way exists for
implementing such circuits.
• As the logic circuit gets
larger and more
complicated, the process
becomes near impossible.

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Programmable Logic Devices:

• PLDs are general –purpose chips for implementing
logic circuitry.
• A PLD can be thought of as a black box with inputs
and outputs that can be programmed to perform
any logic function.
• Small PLDs (SPLD) include the PLA and PAL.

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Programmable Logic Arrays (PLA):

• PLAs are the direct implementation of SoP circuits.
• They comprise of a set of input buffers/inverters
followed by an AND plane and then an OR plane.
• In the diagram, 𝑷𝒊
are the product
terms, and 𝒇𝒋 are the
output functions.
• Each output 𝒇𝒋 can
be configured to
realize any SoP.
• Each AND gate has
𝟐𝒏 possible input
connections.
• Each OR gate has 𝒌
possible input
connections.
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Programmable Logic Arrays (PLA):

• This is a more
detailed
Gate-level
diagram of a
PLA.
• In this
example:
𝑷𝟏 = 𝒙𝟏 𝒙𝟐
𝑷𝟐 = 𝒙𝟏 𝒙′𝟑
𝑷𝟑 = 𝒙′𝟏 𝒙′𝟐 𝒙𝟑
𝑷𝟒 = 𝒙𝟏 𝒙𝟑
• Can you
complete
outputs?
𝒇𝟏 =
𝒇𝟐 =

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Programmable Logic Arrays (PLA):

• A more convenient way of drawing PLA circuits is
depicted below.

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Programmable Array Logic (PAL):

• In the PLA, the input connections to both AND and
OR planes are programmable. Practically, this was
difficult to realize, was too expensive, and caused
too many delays.
• In the PAL,
only the
AND
plane
can be
program-
med.
• Can you
derive
the
outputs?

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Programmable Array Logic (PAL):

• The reduced flexibility is usually compensated for by:
– Providing different sizes of PALS.
– Using additional circuitry at the output.
• The OR gate and added circuitry form a macrocell.
• Below is an example of a typical macrocell.
• This cell allows for storage and thus sequential
circuit implementations.
• The tristate
buffer
allows bus
integration.
• The cell
also has a
feedback
option.

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Programming of Connections:
• The connections to the AND/OR planes are simply
switches that can be open or closed.
• The designer usually specifies the desired circuit
using a CAD tool, which automatically produces
the necessary information for programming each
switch in the PLD (programming file / fuse map).
• The PLD is usually placed within a programmer with
which the CAD interfaces through a cable.
• Usually, the PLD is packaged in a plastic-leaded
chip carrier (PLCC).
• Here is an example:

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Complex PLD (CPLD):

• PLAs and PALs are useful for small digital circuits.
• They are typically small with no more than 32 inputs
and outputs.
• For larger circuits, we use the CPLD.
• A CPLD contains multiple circuit blocks on a chip,
each similar to a PAL or PLA.
• This CPLD
contains 4
circuit blocks.
• Each I/O block
is connected
to a number of
the chip’s
input/output
pins.

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Complex PLD (CPLD):

• In addition to the inputs of the AND arrays being
programmable, so are the connections between
the blocks.
• The PAL-like
block here has 3
macrocells.
Realistic CPLDs
usually have
around 16.
• The XOR inverts
the OR output
when required.
• The tri-state
allows the pin to
be an input or
output.

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Complex PLD (CPLD):

• Commercial CPLDs contain anything from 2 to over
100 PAL-like blocks.
• CPLDs come in a PLCC package as well as a quad
flat pack (QFP) package. The latter has thinner pins
allowing for up to >200 pins (inputs/outputs to the
CPLD) compared to <100 for the PLCC.
• The large pin count of the QFP makes it difficult to
program directly due to:
– The fragile nature of the pins.
– The high cost of a QFP sockets.
• It is more
convenient to
use an on-chip
JTAG
connector.

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Field Prog. Gate Array (FPGA):

• We may use equivalent gates as a measure of
circuit complexity. This refers to the number of 2-
input NAND gates that can be used to implement
the circuit.
• A single CPLD macrocell contains about 20
equivalent gates.
• A 500-block CPLD can implement a 10000-
equivalent-gate circuit.
• Hence, by today’s standards, CPLDs are only
suitable for small to medium circuits.
• The FPGA supports the implementation of large
circuits (millions of equivalent gates).
• The FPGA uses a completely different structure (no
AND/OR planes).

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Field Prog. Gate Array (FPGA):

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Field Prog. Gate Array (FPGA):

• In the FPGA:
– I/O blocks: connect to the pins of the package.
Programmable connections exist between the I/O
blocks and the interconnection blocks.
– Interconnection blocks (wires & switches): provide
horizontal and vertical routing channels for the logic
blocks.
– Logic blocks: contain a 2-
dimensional logic array.
• This structure allows for more
flexibility in the circuit
implementation.
• The FPGA comes in different
packages including PLCC,
QFP, pin gate
array (PGA), and ball gate
array (BGA).
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Field Prog. Gate Array (FPGA):

• The most common logic block is the look-up table
(LUT), which is a set of storage cells each holding a
logic 0 or 1 as required by the programmed circuit.
• The inputs provide the select lines for multiplexers,
which determine the output:

• Commercial FPGA LUTs typically have 4/5 inputs.

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Field Prog. Gate Array (FPGA):

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Field Prog. Gate Array (FPGA):

• Typical logic blocks have a storage element for the
output:

• The CAD tool usually converts the designed circuit

into small functions that fit into these blocks.
• Unlike other PLDs, the LUTs in an FPGA are volatile
and those the FPGA loses its programming once
power is lost.
• The circuit board usually includes a programmable
ROM (PROM) to load the program onto the FPGA.

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Custom Chips:
• Although PLDs are cheap and provide reasonable
flexibility to the designer, the programmable
connections they feature suffer from two main
drawbacks:
– Low speed.
– Increased cost.
• When PLDs do not meet the requirements of the
desired circuit, the designer must resort to custom
designed chips, where the layout of each transistor
(and wire) must be specified.
• Custom chips have a huge overhead, and thus are
only feasible when a sufficient number of circuits is
to be sold.
• A middle solution can be:
– Application specific integrated circuits (ASIC).
– Gate Arrays.

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App. Specific Integ. Circuit (ASIC):

• An ASIC provides rows of cells, which may contain
any type of gate as required by the designer.
• The ASIC is created from scratch according to
specifications.
• The vertical and horizontal interconnections are on
different layers.
• In the circuit below: 𝒇𝟏 = 𝒙𝟏 𝒙𝟐 + 𝒙𝟏 𝒙′𝟑 + 𝒙′𝟏 𝒙′𝟐 𝒙𝟑 .

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Gate Array:
• In a gate array, parts of the chip are pre-fabricated
and parts are customized.
• The manufacturer create a gate array template.
• The template is basically a silicon wafer of partially
complete chips.
• NAND-only
templates are
common.
• The
connection
wires are
manufactured
after receiving
the circuit
requirements
from the user.

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An Example:
• Consider the function:
𝑭 𝒙𝟏 , 𝒙𝟐 , 𝒙𝟑 = ෍ 𝟎, 𝟐, 𝟒, 𝟓, 𝟔

• The function can be implemented directly in VHDL:

library IEEE;
use IEEE.std_logic_1164.all;
entity Func1 is
port(X1,X2,X3: in bit;
F: out bit);
end Func1;
architecture Arch1 of Func1 is
Begin
F <= (not X1 and not X2 and not X3) or
(not X1 and X2 and not X3) or
(X1 and not X2 and not X3) or
(X1 and not X2 and X3) or
(X1 and X2 and not X3);
end Arch1;

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An Example:
• The previous code is synthesized by the CAD tool
according to the devices to be programmed.
• The CAD optimizer produces: 𝑭 = 𝒙′𝟑 + 𝒙𝟏 𝒙′𝟐 .
• Below are two different implementations of the
function:
– Left: PAL-like implementation.
– Right: 4-input LUT implementation (d = don’t care).

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End of Chapter III

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