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Chapter V: Combinational Circuits

• In this chapter, we will cover the following topics:

– Multiplexers and their applications.

– Logic function synthesis using multiplexers (Shannon’s

theorem).

– Decoders, demultiplexers, and encoders.

– Code converters.

– VHDL implementation of combinational circuits.

Digital Design II (EE411) | Dr. Samir Bendoukha

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2:1 Multiplexer:
• A multiplexer circuit has
multiple inputs, one or
more select lines, and
one or more outputs.
• The values of the
outputs are selected
from the inputs based
on the select lines.
• The simplest multiplexer
is the 2:1.
• It can be implemented
as an SoP or using
transmission gates.
• The operation of a
transmission gate is
explained next.

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Transmission Gate:
• A transmission gate is a CMOS switch that passes
both 0 and 1 well. (What does this mean?)
• It is composed of an NMOS/PMOS pair with
opposite gate voltages.
• When the select line is equal to zero, the output is
undefined.
• When the select line is equal to one, the output is
the same as the input.

Digital Design II (EE411) | Dr. Samir Bendoukha

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VHDL Implementation:
• The 2:1 multiplexer can be implemented in VHDL
using conditional statements.
• For instance, using the select statement, we obtain
the following code:

library IEEE;
use IEEE.std_logic_1164.all;
entity Mux2to1 is
port(w0,w1,s: in STD_LOGIC;
f: out STD_LOGIC);
end Mux2to1;
architecture behavior of Mux2to1 is
begin
with s select
f <= w0 when ‘0’,
w1 when others;
end behavior;

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4:1 Multiplexer:
• A 4:1 multiplexer can be designed in a similar
manner.
• It is SoP expression is:
𝒇 = 𝒔′𝟏 𝒔′𝟎 𝒘𝟎 + 𝒔𝟏 𝒔′𝟎 𝒘𝟏 + 𝒔′𝟏 𝒔𝟎 𝒘𝟐 + 𝒔𝟏 𝒔𝟎 𝒘𝟑
• It can also be implemented using three 2:1
multiplexers as shown below.
• In fact, the 2:1 multiplexer can be used to
implement an arbitrary 𝒌: 𝒏 multiplexer.

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VHDL Implementation:
• The 4:1 multiplexer can be implemented in a similar
way to the 2:1 multiplexer:

library IEEE;
use IEEE.std_logic_1164.all;
entity Mux4to1 is
port(W: in STD_LOGIC_VECTOR(0 to 3);
S: in STD_LOGIC_VECTOR(1 downto 0);
f: out STD_LOGIC);
end Mux4to1;
architecture behavior of Mux4to1 is
begin
with S select
f <= W(0) when “00”,
W(1) when “01”,
W(2) when “10”,
W(3) when others;
end behavior;

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VHDL Implementation:
• Let us now implement a 16:1 multiplexer using the
4:1 multiplexer in the previous slide.

library IEEE;
use IEEE.std_logic_1164.all;
entity Mux16to1 is
port(W: in STD_LOGIC_VECTOR(0 to 15);
S: in STD_LOGIC_VECTOR(3 downto 0);
f: out STD_LOGIC);
end Mux16to1;
architecture behavior of Mux4to1 is
signal X: STD_LOGIC_VECTOR(0 to 3);
component Mux4to1 is
port(W: in STD_LOGIC_VECTOR(0 to 3);
S: in STD_LOGIC_VECTOR(1 downto 0);
f: out STD_LOGIC);
end component;
begin
…

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VHDL Implementation:
• Let us now implement a 16:1 multiplexer using the
4:1 multiplexer in the previous slide.

begin
MUX1: Mux4to1 port map (M(0 to 3),S(1 downto 0),
X(0));
MUX2: Mux4to1 port map (M(4 to 7),S(1 downto 0),
X(1));
MUX3: Mux4to1 port map (M(8 to 11),S(1 downto
0), X(2));
MUX4: Mux4to1 port map (M(12 to 15),S(1 downto
0), X(3));
MUX5: Mux4to1 port map (X(0 to 3),S(3 downto 2),
f);
end behavior;

Digital Design II (EE411) | Dr. Samir Bendoukha

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Tri-state Buffers:
• We have seen
The tri-state gate.
• It can be
Implemented
from the transmission gate.
• We saw that the
macrocells found in PALs
and CPLDs contain a tri-
state buffer.
• Another application is
building multiplexers.
• The choice between SoP,
crossbar, and tristate
implementations depends
on the PLD used.

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Crossbar Switches:
• A crossbar switch has as many outputs as inputs.
• Based on the select lines, it allows for different input
combinations at the output.
• The simplest type is the 2 × 2 crossbar switch.
• This can be implemented
by means of 2:1
multiplexers.
• When 𝒔 = 𝟎, 𝒚𝟏 = 𝒙𝟏 and
𝒚𝟐 = 𝒙𝟐 .
• When 𝒔 = 𝟏, 𝒚𝟏 = 𝒙𝟐 and
𝒚𝟐 = 𝒙𝟏 .
• These switches have
many applications
including telephony and
signal routing.

Digital Design II (EE411) | Dr. Samir Bendoukha

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Multiplexers & the FPGA:

• Earlier in the course, we saw the FPGA as a
programmable device.
• The programmable connections
can be formed as:
– Transistor/latch pairs.
– Multiplexers with latches.
• In both cases, the latches are
programmed by the CAD tool.

Digital Design II (EE411) | Dr. Samir Bendoukha

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Functions & Multiplexers:

• Multiplexers can also be used
to synthesize arbitrary logic
functions.
• Consider a 2-input XOR gate.
• The inputs of a 4:1 multiplexer
can be connected to latches
and the select lines to the
function inputs.
• This implementation can be
simplified by making the
observation shown here:
• This means that the function
can be implemented as a 2:1
multiplexer with 𝒘𝟏 as the
select line.
• Can we swap 𝒘𝟏 and 𝒘𝟐 ?
Digital Design II (EE411) | Dr. Samir Bendoukha
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Functions & Multiplexers:

• Consider a 3-input majority circuit.
• This circuit produces a one is the number of 𝟏s in the
inputs is ≥ 𝟐, otherwise it produces a zero.
• Direct implementation requires an 8:1 multiplexer.
• However, a simplification can be achieved by
relating the output to inputs 𝒘𝟏 and 𝒘𝟐 .

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Functions & Multiplexers:

• Now, consider a 3-input XOR gate.
• Here are two possible implementations.

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Shannon’s Expansion:
• In the previous examples, we simply connected the
multiplexer inputs to 𝟎, 𝟏, one of the inputs, or its
complement.
• More complex logic circuits can be connected to
the inputs.

• Shannon’s theorem states that:

Any function 𝒇 𝒘𝟏 , 𝒘𝟐 , … , 𝒘𝒏 can be written
in the form:
𝒇 = 𝒘′𝟏 𝒇 𝟎, 𝒘𝟐 , … , 𝒘𝒏 + 𝒘𝟏 𝒇 𝟏, 𝒘𝟐 , … , 𝒘𝒏

• This theorem is straightforward if you think about it.

• Can you prove it?
• NOTE: Shannon’s theorem can be used more than
once (see example 3).

Digital Design II (EE411) | Dr. Samir Bendoukha

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Example 1:
• We saw a 3-input majority circuit earlier.
• The sum of minterms expression is:
𝒇 = 𝚺 𝟑, 𝟓, 𝟔, 𝟕
• This can be simplified to:
𝒇 = 𝒘𝟏 𝒘𝟐 + 𝒘𝟏 𝒘𝟑 + 𝒘𝟐 𝒘𝟑
• Applying Shannon’s theorem yields:
𝒇 = 𝒘′𝟏 𝒇 𝟎, 𝒘𝟐 , 𝒘𝟑 + 𝒘𝟏 𝒇 𝟏, 𝒘𝟐 , 𝒘𝟑
= 𝒘′𝟏 𝟎 ∙ 𝒘𝟐 + 𝟎 ∙ 𝒘𝟑 + 𝒘𝟐 𝒘𝟑 + 𝒘𝟏 𝟏 ∙ 𝒘𝟐 + 𝟏 ∙ 𝒘𝟑 + 𝒘𝟐 𝒘𝟑
= 𝒘′𝟏 𝒘𝟐 𝒘𝟑 + 𝒘𝟏 𝒘𝟐 + 𝒘𝟑 + 𝒘𝟐 𝒘𝟑
= 𝒘′𝟏 𝒘𝟐 𝒘𝟑 + 𝒘𝟏 𝒘𝟐 + 𝒘𝟑
• Hence, we may implement the circuit by using a 2:1
multiplexer and some
Logic gates as shown
here:

Digital Design II (EE411) | Dr. Samir Bendoukha

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Example 2:
• The 3-input XOR gate we saw earlier is given by:
𝒇 = 𝒘𝟏 ⨁𝒘𝟐 ⨁𝒘𝟑
• This can be simplified by Shannon’s theorem as
follows:
𝒇 = 𝒘′𝟏 𝒇 𝟎, 𝒘𝟐 , 𝒘𝟑 + 𝒘𝟏 𝒇 𝟏, 𝒘𝟐 , 𝒘𝟑
= 𝒘′𝟏 𝟎⨁𝒘𝟐 ⨁𝒘𝟑 + 𝒘𝟏 𝟏⨁𝒘𝟐 ⨁𝒘𝟑
= 𝒘′𝟏 𝒘𝟐 ⨁𝒘𝟑 + 𝒘𝟏 𝒘𝟐 ⨁𝒘𝟑 ′
• This produces the same implementation we saw
earlier:

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Example 3:
• Consider the function:
𝒇 = 𝒘′𝟏 𝒘′𝟑 + 𝒘𝟏 𝒘𝟐 + 𝒘𝟏 𝒘𝟑
= 𝒘′𝟏 𝒘′𝟑 + 𝒘𝟏 𝒘𝟐 + 𝒘𝟑
• This yields the implementation below (left).
• The function above can be expanded by applying
Shannon’s theorem to both 𝒘𝟏 and 𝒘𝟐 yielding:
𝒇 = 𝒘′𝟏 𝒘′𝟑 + 𝒘𝟏 𝒘𝟐 + 𝒘𝟏 𝒘𝟑
= 𝒘′𝟏 𝒘′𝟐 𝒘′𝟑 + 𝒘′𝟏 𝒘𝟐 𝒘′𝟑 + 𝒘𝟏 𝒘′𝟐 𝒘𝟑 + 𝒘𝟏 𝒘𝟐 𝟏
• This leads to the second implementation below
(right).

Digital Design II (EE411) | Dr. Samir Bendoukha

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Binary Decoder:
• Decoder circuits are used to decode encoded
information.
• A binary decoder is shown below:

• In the decoder depicted above, only one output is

asserted at any time.
• 𝑬𝒏 = 𝟎 disables the output (no line is asserted).
• The value of 𝒘𝒏−𝟏 … 𝒘𝟏 𝒘𝟎 determines which
output is asserted.
• The output of a binary decoder is called one-hot
encoded.
Digital Design II (EE411) | Dr. Samir Bendoukha
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2:4 Binary Decoder:

• The simplest binary decoder is the 2:4 decoder.
• Each output’s function is represented as a single
minterm.
• Note that the assertion here refers to output=1,
which is active high.

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3:8 Binary Decoder:

• Larger decoders can be designed directly or
synthesized from the 2:4 decoder.
• Below is a synthesized 3:8 decoder.
• Depending on the value of 𝒘𝟐 , one of the two sets
of outputs is enabled and the other is disabled.

Digital Design II (EE411) | Dr. Samir Bendoukha

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VHDL Implementation:
• Here is the implementation of a 2:4 binary decoder:
library IEEE;
use IEEE.std_logic_1164.all;
entity Dec2to4 is
port(W: in STD_LOGIC_VECTOR(1 downto 0);
En: in STD_LOGIC;
Y: out STD_LOGIC_VECTOR(0 to 3));
end Dec2to4;
architecture behavior of Dec2to4 is
signal EnW: STD_LOGIC_VECTOR(2 downto 0);
begin
EnW <= En & W;
with EnW select
f <= “1000” when “100”,
“0100” when “101”,
“0010” when “110”,
“0001” when “111”,
“0000” when others;
end behavior;

Digital Design II (EE411) | Dr. Samir Bendoukha

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Decoder-Based Multiplexer:
• The binary decoder can be used along with tri-state
buffers to form a multiplexer.

• This is a 4:1 multiplexer where the two select lines

are decoded and used to control four tri-state
buffers.

Digital Design II (EE411) | Dr. Samir Bendoukha

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Demultiplexer:
• A demultiplexer performs the opposite function of
the multiplexer.
• A single input is routed onto multiple outputs.
• A demultiplexer can be built using decoders.
• Consider the 2:4 decoder.
• The 𝑬𝒏 serves as the input.
• The lines 𝒘𝟏 and 𝒘𝟐 are the controls
that determine which output is set to
the value of 𝑬𝒏.
• This gives us a 1:4 demultiplexer.
• In general, an 𝒏:𝟐𝒏 decoder can be used to
implement a 1:𝒏 demultiplexer.

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ROM Addressing:
• One of the applications of the decoder is
addressing in RAM/ROM memory blocks.

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Binary Encoder:
• Encoders reduce the number of bits needed to
represent information.
• A binary encoder is the opposite of a binary
decoder.

• Exactly one input is high. The outputs form the

binary number corresponding to the high input.

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Priority Encoder:
• The binary encoder assumes one-hot encoded
inputs.
• If multiple input lines are allowed to be high, we
need to prioritize. For instance:

• We have:
𝒊𝟎 = 𝒘′𝟑 𝒘′𝟐 𝒘′𝟏 𝒘𝟎
𝒚 𝟎 = 𝒊𝟏 + 𝒊𝟑
𝒊𝟏 = 𝒘′𝟑 𝒘′𝟐 𝒘𝟏
→ 𝒚 𝟏 = 𝒊𝟐 + 𝒊𝟑
𝒊𝟐 = 𝒘′𝟑 𝒘𝟐 𝒛 = 𝒊𝟎 + 𝒊𝟏 + 𝒊𝟐 + 𝒊𝟑
𝒊𝟑 = 𝒘 𝟑

Digital Design II (EE411) | Dr. Samir Bendoukha

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VHDL Implementation:
• Below is one possible implementation of the 4-bit
priority encoder:
library IEEE;
use IEEE.std_logic_1164.all;
entity priority is
port(W: in STD_LOGIC_VECTOR(3 downto 0);
Y: out STD_LOGIC_VECTOR(1 downto 0);
z: out STD_LOGIC);
end priority;
architecture behavior of priority is
begin
Y <= “11” when W(3)=‘1’ else
“10” when W(2)=‘1’ else
“01” when W(1)=‘1’ else
“00”;
z <= “0” when W=“0000” else ‘1’;
end behavior;

Digital Design II (EE411) | Dr. Samir Bendoukha

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Code Converter:
• The encoder and decoder we saw are both code
converters. The binary decoder converts binary to
one-hot, whereas the encoder does the opposite.
• There are other types of
converters.
• An example is the BCD-
to-7-segment decoder.
• The remaining 6 rows of
the truth table are
omitted as they are don’t
care conditions.
• They may also be used to
represent hexa-decimal
digits.
• Can you show how?

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End of Chapter V

Digital Design II (EE411) | Dr. Samir Bendoukha