ECE 586

Hardware Security and Advanced Computer

Architectures

LECTURE 3 :
RISC-V Instruction Set Architecture (Appendix A)
Pipelining (Appendix C)
01/17/2024
Erdal Oruklu, PhD

Illinois Institute of Technology

Department of Electrical and Computer Engineering

ECE586 Lecture 3
 Optimizing ISA:
▪ Use general-purpose registers with a load-store architecture.
▪ Support these addressing modes: displacement (with an address offset
size of 12–16 bits), immediate (size 8–16 bits), and register indirect
▪ Support these data sizes and types: 8-, 16-, 32-, and 64-bit integers
and 64-bit IEEE 754 floating-point numbers.
▪ Support these simple instructions, because they will dominate the
number of instructions executed: load, store, add, subtract, move
register-register, and shift.
▪ Compare equal, compare not equal, compare less, branch (with a PC-
relative address at least 8 bits long), jump, call, and return.
▪ Use fixed instruction encoding if interested in performance, and use
variable instruction encoding if interested in code size. In some low-end,
embedded applications, with small or only one-level caches, larger code
size may have significant performance implications. ISAs that provide a
compressed instruction set extension provide a way of addressing this
difference.
▪ Provide at least 16, and preferably 32, general-purpose registers, be
sure all addressing modes apply to all data transfer instructions, and
aim for a minimalist instruction set.

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 RISC-V
▪ Like its RISC predecessors, RISC-V emphasizes:
▪ A simple load-store instruction set.
▪ Design for pipelining efficiency, including a fixed
instruction set encoding.
▪ Efficiency as a compiler target

▪ The RISC-V instruction set is organized as three base

instruction sets that support 32-bit or 64-bit integers, and
a variety of optional extensions to one of the base
instruction sets.
▪ This allows RISC-V to be implemented for a wide range of potential
applications from a small embedded processor with a minimal
budget for logic and memory that likely costs $1 or less, to high-end
processor configurations with full support for floating point, vectors,
and multiprocessor configurations.

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 RISC-V instruction sets

Figure A.22 RISC-V has three base instructions sets (and a reserved spot for a future fourth); all the extensions extend one of the base
instruction sets. An instruction set is thus named by the base name followed by the extensions. For example, RISC-V64IMAFD refers to
the base 64-bit instruction set with extensions M, A, F, and D. For consistency of naming and software, this combination is given the
abbreviated name: RV64G, and we use RV64G through most of this text.

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 RISC-V ISA
▪ RV64G has 32 64-bit general purpose registers
▪ F and D extensions come with a set of 32 floating point
registers (64 bit).
▪ Data types are
▪ 8-bit byte, 16-bit half words, 32-bit words and 64-bit
doublewords for integer;
▪ 32-bit single precision and 64-bit double precision for
floating point.
▪ Addressing modes are immediate and displacement (12-
bit fields).
▪ Register indirect is done by placing 0 in 12-bit displacement
▪ Limited absolute addressing is done by using register 0 as
base register
▪ RV64G memory access is byte addressable with 64-bit
address and it uses little-endian byte ordering.

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 RISC-V Instruction set layout

▪ All instructions are 32-bit with a 7-bit primary

opcode

Figure A.23 The RISC-V instruction layout. There are two variations on these formats, called the SB and UJ formats; they deal with a
slightly different treatment for immediate fields.

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 RISC-V instruction fields

Figure A.24 The use of instruction fields for each instruction type. Primary use shows the major instructions that use the format. A
blank indicates that the corresponding field is not present in this instruction type. The I-format is used for both loads and ALU
immediates, with the 12-bit immediate holding either the value for an immediate or the displacement for a load. Similarly, the S-
format encodes both store instructions (where the first source register is the base register and the second contains the register
source for the value to store) and compare and branch instructions (where the register fields contain the sources to compare and
the immediate field specifies the offset of the branch target). There are actually two other formats: SB and UJ that follow the same
basic organization as S and J, but slightly modify the interpretation of the immediate fields.

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 RISC-V load and store instructions

Figure A.25 The load and store instructions in RISC-V. Loads shorter than 64 bits are available in both sign-extended and zero-extended
forms. All memory references use a single addressing mode. Of course, both loads and stores are available for all the data types
shown. Because RV64G supports double precision floating point, all single precision floating point loads must be aligned in the FP
register, which are 64-bits wide.

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 RISC-V ALU operations

Figure A.26 The basic ALU instructions in RISC-V are available both with register-register operands and with one immediate operand. LUI
uses the U-format that employs the rs1 field as part of the immediate, yielding a 20-bit immediate.

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 RISC-V Control Instructions

All branches are conditional. The branch condition is specified by the instruction, and any
arithmetic comparison (equal, greater than, less than, and their inverses) is permitted.
The branch-target address is specified with a 12-bit signed offset that is shifted left one
place (to get 16-bit alignment) and then added to the current program counter.

Figure A.27 Typical control flow instructions in RISC-V. All control instructions, except jumps to an address in a register, are PC-relative.

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 Floating Point Extension- RV64G

Figure A.28 A list of the vast majority of instructions in RV64G.

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 RISC-V Instruction mix in SPECint2006

Figure A.29 RISC-V dynamic instruction mix for the SPECint2006 programs. Omnetpp includes 7% of the instructions that are floating
point loads, stores, operations, or compares; no other program includes even 1% of other instruction types. A change in gcc in
SPECint2006, creates an anomaly in behavior. Typical integer programs have load frequencies that are 1/5 to 3x the store frequency. In
gcc, the store frequency is actually higher than the load frequency! This arises because a large fraction of the execution time is spent
in a loop that clears memory by storing x0 (not where a compiler like gcc would usually spend most of its execution time!). A store
instruction that stores a register pair, which some other RISC ISAs have included, would address this issue.

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 Fallacy: There is such a thing as a typical
program

Figure A.30 Data reference size of four programs from SPEC2000. Although you can calculate an average size, it would be hard to
claim the average is typical of programs.

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 Pitfall: Innovating at the instruction set architecture to
reduce code size without accounting for the compiler

Figure A.31 Code size relative to Apogee Software Version 4.1 C compiler for Telecom application of EEMBC benchmarks. The instruction
set architectures are virtually identical, yet the code sizes vary by factors of 2. These results were reported February–June 2000.

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 Fallacy: An architecture with flaws cannot be
successful

▪ The 80x86 provides a dramatic example.

▪ 80x86 supports segmentation, whereas all others picked paging; it
uses extended accumulators for integer data, but other processors
use general-purpose registers; and it uses a stack for floating-point
data, when everyone else abandoned execution stacks long before.
▪ Despite these major difficulties, the 80x86 architecture
has been enormously successful. The reasons are
threefold:
▪ Its selection as the microprocessor in the initial IBM PC makes
80x86 binary compatibility extremely valuable.
▪ Second, Moore’s Law provided sufficient resources for 80x86
microprocessors to translate to an internal RISC instruction set and
then execute RISC-like instructions. This mix enables binary
compatibility with the valuable PC software base and performance
on par with RISC processors.
▪ Third, the very high volumes of PC microprocessors mean Intel can
easily pay for the increased design cost of hardware translation.

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 Fallacy: You can design a flawless architecture

▪ All architecture design involves trade-offs made in the context

of a set of hardware and software technologies. Over time those
technologies are likely to change, and decisions that may have
been correct at the time they were made look like mistakes.
▪ For example, in 1975 the VAX designers overemphasized the importance of
code size efficiency, underestimating how important ease of decoding and
pipelining would be five years later.
▪ An example in the RISC camp is delayed branch. It was a simple matter to
control pipeline hazards with five-stage pipelines, but a challenge for
processors with longer pipelines that issue multiple instructions per clock
cycle.
▪ In addition, almost all architectures eventually succumb to the lack of
sufficient address space. This is one reason that RISC-V has planned for the
possibility of 128-bit addresses, although it may be decades before such
capability is needed.

▪ In general, avoiding such flaws in the long run would probably

mean compromising the efficiency of the architecture in the
short run, which is dangerous, since a new instruction set
architecture must struggle to survive its first few years.

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