ECE586 Lecture 3
ECE586 Lecture 3
LECTURE 3 :
RISC-V Instruction Set Architecture (Appendix A)
Pipelining (Appendix C)
01/17/2024
Erdal Oruklu, PhD
ECE586 Lecture 3
Optimizing ISA:
▪ Use general-purpose registers with a load-store architecture.
▪ Support these addressing modes: displacement (with an address offset
size of 12–16 bits), immediate (size 8–16 bits), and register indirect
▪ Support these data sizes and types: 8-, 16-, 32-, and 64-bit integers
and 64-bit IEEE 754 floating-point numbers.
▪ Support these simple instructions, because they will dominate the
number of instructions executed: load, store, add, subtract, move
register-register, and shift.
▪ Compare equal, compare not equal, compare less, branch (with a PC-
relative address at least 8 bits long), jump, call, and return.
▪ Use fixed instruction encoding if interested in performance, and use
variable instruction encoding if interested in code size. In some low-end,
embedded applications, with small or only one-level caches, larger code
size may have significant performance implications. ISAs that provide a
compressed instruction set extension provide a way of addressing this
difference.
▪ Provide at least 16, and preferably 32, general-purpose registers, be
sure all addressing modes apply to all data transfer instructions, and
aim for a minimalist instruction set.
ECE586 Lecture 3
RISC-V
▪ Like its RISC predecessors, RISC-V emphasizes:
▪ A simple load-store instruction set.
▪ Design for pipelining efficiency, including a fixed
instruction set encoding.
▪ Efficiency as a compiler target
ECE586 Lecture 3
RISC-V instruction sets
Figure A.22 RISC-V has three base instructions sets (and a reserved spot for a future fourth); all the extensions extend one of the base
instruction sets. An instruction set is thus named by the base name followed by the extensions. For example, RISC-V64IMAFD refers to
the base 64-bit instruction set with extensions M, A, F, and D. For consistency of naming and software, this combination is given the
abbreviated name: RV64G, and we use RV64G through most of this text.
ECE586 Lecture 3
RISC-V ISA
▪ RV64G has 32 64-bit general purpose registers
▪ F and D extensions come with a set of 32 floating point
registers (64 bit).
▪ Data types are
▪ 8-bit byte, 16-bit half words, 32-bit words and 64-bit
doublewords for integer;
▪ 32-bit single precision and 64-bit double precision for
floating point.
▪ Addressing modes are immediate and displacement (12-
bit fields).
▪ Register indirect is done by placing 0 in 12-bit displacement
▪ Limited absolute addressing is done by using register 0 as
base register
▪ RV64G memory access is byte addressable with 64-bit
address and it uses little-endian byte ordering.
ECE586 Lecture 3
RISC-V Instruction set layout
Figure A.23 The RISC-V instruction layout. There are two variations on these formats, called the SB and UJ formats; they deal with a
slightly different treatment for immediate fields.
ECE586 Lecture 3
RISC-V instruction fields
Figure A.24 The use of instruction fields for each instruction type. Primary use shows the major instructions that use the format. A
blank indicates that the corresponding field is not present in this instruction type. The I-format is used for both loads and ALU
immediates, with the 12-bit immediate holding either the value for an immediate or the displacement for a load. Similarly, the S-
format encodes both store instructions (where the first source register is the base register and the second contains the register
source for the value to store) and compare and branch instructions (where the register fields contain the sources to compare and
the immediate field specifies the offset of the branch target). There are actually two other formats: SB and UJ that follow the same
basic organization as S and J, but slightly modify the interpretation of the immediate fields.
ECE586 Lecture 3
RISC-V load and store instructions
Figure A.25 The load and store instructions in RISC-V. Loads shorter than 64 bits are available in both sign-extended and zero-extended
forms. All memory references use a single addressing mode. Of course, both loads and stores are available for all the data types
shown. Because RV64G supports double precision floating point, all single precision floating point loads must be aligned in the FP
register, which are 64-bits wide.
ECE586 Lecture 3
RISC-V ALU operations
Figure A.26 The basic ALU instructions in RISC-V are available both with register-register operands and with one immediate operand. LUI
uses the U-format that employs the rs1 field as part of the immediate, yielding a 20-bit immediate.
ECE586 Lecture 3
RISC-V Control Instructions
All branches are conditional. The branch condition is specified by the instruction, and any
arithmetic comparison (equal, greater than, less than, and their inverses) is permitted.
The branch-target address is specified with a 12-bit signed offset that is shifted left one
place (to get 16-bit alignment) and then added to the current program counter.
Figure A.27 Typical control flow instructions in RISC-V. All control instructions, except jumps to an address in a register, are PC-relative.
ECE586 Lecture 3
Floating Point Extension- RV64G
ECE586 Lecture 3
RISC-V Instruction mix in SPECint2006
Figure A.29 RISC-V dynamic instruction mix for the SPECint2006 programs. Omnetpp includes 7% of the instructions that are floating
point loads, stores, operations, or compares; no other program includes even 1% of other instruction types. A change in gcc in
SPECint2006, creates an anomaly in behavior. Typical integer programs have load frequencies that are 1/5 to 3x the store frequency. In
gcc, the store frequency is actually higher than the load frequency! This arises because a large fraction of the execution time is spent
in a loop that clears memory by storing x0 (not where a compiler like gcc would usually spend most of its execution time!). A store
instruction that stores a register pair, which some other RISC ISAs have included, would address this issue.
ECE586 Lecture 3
Fallacy: There is such a thing as a typical
program
Figure A.30 Data reference size of four programs from SPEC2000. Although you can calculate an average size, it would be hard to
claim the average is typical of programs.
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Pitfall: Innovating at the instruction set architecture to
reduce code size without accounting for the compiler
Figure A.31 Code size relative to Apogee Software Version 4.1 C compiler for Telecom application of EEMBC benchmarks. The instruction
set architectures are virtually identical, yet the code sizes vary by factors of 2. These results were reported February–June 2000.
ECE586 Lecture 3
Fallacy: An architecture with flaws cannot be
successful
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Fallacy: You can design a flawless architecture
ECE586 Lecture 3