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Electronics Practical (1) 3rd Sem

This 3-sentence summary provides the key details from the document: The document lists experiments performed on specific dates involving the construction and testing of logic gates like AND, OR, and NOT using NAND gates. It includes circuit diagrams showing how to realize different logic functions with NAND gates and notes the input/output truth tables for each logic gate implementation. Specific experiments involve realizing an OR gate, AND gate, NOT gate, and EX-OR gate using NAND gates.

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Suprabha479
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© © All Rights Reserved
Available Formats
Download as PDF, TXT or read online on Scribd
0% found this document useful (0 votes)
193 views

Electronics Practical (1) 3rd Sem

This 3-sentence summary provides the key details from the document: The document lists experiments performed on specific dates involving the construction and testing of logic gates like AND, OR, and NOT using NAND gates. It includes circuit diagrams showing how to realize different logic functions with NAND gates and notes the input/output truth tables for each logic gate implementation. Specific experiments involve realizing an OR gate, AND gate, NOT gate, and EX-OR gate using NAND gates.

Uploaded by

Suprabha479
Copyright
© © All Rights Reserved
Available Formats
Download as PDF, TXT or read online on Scribd
You are on page 1/ 17

Particulars of The Experiments Perforrned

Serial Experiment
Date No. No Subject/Experiment Page
No. Signatuts Remerks

1 sgn AND OR NOT 8nd


4tos nd ven 2

5|01]23 2. 2 Ntcaioy of De
inigt

8/D1123 3 2 Con_lustfo and


Neufica tion o4
hol ubtrac tor

ARcHon a
15/0/23 A 4 ton of H 13
Adder

Consycb'on ond
5 5 NeUticatren ef4:1| 16
Mwtple erL

Con stzuution
veruitatt onef
lal Adler Cltt
usinAwo mput

Cendlyuthon am dyek
Catsen o Ral Subtct
IC - 7400(NAND)

1
Nee
-o 14

-o 13
3O - 12

5
6

Gytound
Signature Teacher's
onics EXAtDeparn
t
enaliem. double b ilen be
FEA+B OXfORD
lput
NAND aom OR
chip gate NAND input two Quad 7400 -IC O
Speaificatton ompon
ent oTYpe
Canponata
eteCuteta OLEO' kuines lonnecfing D
DC. 5V Boand eu't O 0074IC- O
Keqused Appazatua
etc. diode resio, tatonastO,
felehents
he cheuit
cineuit electeonic boaic, Using done Casiy
becan qate NND reabzeion
od Hoxdusate
Gotie NAND
ven ond gatoEX-OR
s ond AND.OR.
NOT toble4huth Desgn hey
122 810 Date.
2No./ Page Expt.No.
Cineut Diagpam.
OR Aate om NÁND ate:

A NDI

B
B

AND gate drom NANDqale i

7400
400
A
AB
B ND2-
No.
Page No. 3
Date./ g|u| 22
F= AB =A4E = A 4B
Usna 190
no NAND gates an tno NOT gates ., se get Aondß
on Aand 8. Then aking NAND vsion o outpuls o
Hhe rgwned R aulput

Input Output
A AB At8
LL CV L CV CV CV LL CV
0
OR 1 N
5
ON

AND om NAND &


We ahe to 2 NAND and outpud of e
Stcond NAND gole
Dperoling a odQecomd gle NAND
be NANO otput ake
RD So. theorem, We wte
=A+ B
Teacher's Signature
NOT ate. toom NAND qate

1400
Y-A
A ND P
xpt.No. |Page No./ 4
Date./2[ftl22
The he hoaoulpais givet
F=X= AB AB

Input Ouput AB
A B A B A+B
olol J14 CV LL CV L CVLLICy
LLCV LL CV
ON
ONO
5N 1
ON

NOT ur NAND -
hurth toble NHN
iA-B=l; fz0, hus 1e eonne input ominal
H ond B hen NHM aate 91Duooperoteab
NOT
F nhen B=Oond F=0 nhen B- 1 - Thus
hah paic VAND
o2oted NDT ote o
ToPut
OXroRD CV
Loaie
Leve Noftage Leres LL CV LL
ON
Teacher's Signature
Expt.No. Page No./4
Date./8ttj22
Thua he a Dutput
utps givth
F=X= AB=AB
bush abe om AND aate :
Input Output
A B A B A+B AB
LLCV 11 CV LL LL CV LL CvLL Cy
olo SN ORO

1
GN

NOT ar NAD :
huth tobe IAND
nnd i A-8-1:F- 0, hus i e eonnect inpu ominak
then. NAM 9ate ntuld
an NOT re.toyer ne
F=l nhen B=0 and F=0 hen B=1. Thu
hiah paic me he doinpods, AND
oted O a NOT ac he ohen
beth TakleToPut
xroRD Logieeet Loglc
Level Noltage LeVei LL CV LL
ON
Teacher's Signature
-OR gte. om NAND gate i

A+AB
ND25

I400
400
A AB
B ND4
AB+ AB

ND3
B+AB
7400
pt.No.
Page No./5
Date. Os[u 22 |

We have dousn 2- input NAND gates manked os No1,


D-2. ND -3, ND-4. The output ND -1 NO-2 and NM)-3 coe
KYZpecvey
hen hen e an nute,
X= AB = tB
Y= AÀB = Ât AB
Z=B AB = B+ AB
The inal auout Fof ND 4is htainedas.
F= yz =Y+
e get
F= (A+B ) (h-+B) = AE +A8
ñ8
don EX-OR god
Input Output
A
oB o B AtABB tABYt2 AEn6
|CV
O ON N
O
N N
o IOr
XFORD

Teacher's Signature
ot.No.
Page No./6
6
Date./&//22

o The iaes must be oniecded canehull?.


Shot ongth mes must be wsed do avoid
in e Cuit

() Hter checking dhe coeuit


Sritch mut be ON.

roRD
Rkor22
Teacher'sSignature ....
daggam Cscuit
)tement of
thes eufieadion he oa
7404
7432 7404
=A.B
1404 A
7408
(istatement
) erifiation
thevitoalion
of the Hondon dkagam
A 7404
B
7408
8
AtB A
74D4 3432
Expt.No. Page No./7
Date.5 L|23
1.-Mogan' theorem ugna) qate
heozu)i

De-onga') thernem conast slate men


Complemento the SUm
mote wdiable is
Complementa d the yantales
lhe conplongn af he puoduet o anaoblea
is he sum of the

too miable AandB. he Beolean ex Þaes2ion


epeskon. o1 the
slotemen!s
(:) A+B ==
A: B

Appaatu, Ranuize
() TC 7A32. TC- 7408TC-7407
XFORD Boamd
o) 5V DC fana supply
() LEDS
Teacher's Signature
fin CntguPa.lion of -he ICs i

-o 14 (+8v)
2 o -o2

3 -o 1|
TC7432
4
5

TC 7432 (quad 2-input oR gate)

o 14 +5 v
-o 13
2
O 12

3o
IC 7408
4o

o8
7

Te T408 (Ruad 2-input AND gote)


Signature Teacher's
venf'ed 1
o oXFORD
ongan246ofDe - O
Yi=Ya of o o
evelaj voage v) led (V) levd Nettoge v evcl 4v)l(evel Jevet
VdlaggvolfagC Dic
Cinuit Creut
B A A+B Y A
emahs Output
TABLE
-I
A.B A+B pelaton, an
oouth
table
Resutai Expezmaral
chip inyate1 TeTlcex 7404 I
hANDgae
p input 2-Guad 408
7432 IC
dpeioainra ComponentA o
mpanerta Speeaabn
hzex Lomecing
()
5l|23 Date.
No., Page Expt.No.2
o13

2 G

3 o

5 o

6 o

TC 404 (Mex in vete


Expt.No. 2 Page No./
Date.J |L123
Vercieion o touth able do nelaston, A.B -
able - I
Input Output Retromks
A Y,=A.B A B Y,= A+ B
Ciauut
oo |ogic
levet elage fevelotageleve WTerelelevet Velfage evet
(v) vOttage
(V)

ON gr4 De- Morg an'A


NO
6NÔNO4! SN Noured

Ch The THBLE -I ond TABLE-I


ABLE-I veny.
veny ihe le-ogar'
heonem
6)he u8tze mu be eonested

Ne mwt be ed wed do ayeid


tonqlont in eietts
DXFORDiy Ater oheckng the ciost connectien sthe ponme7 &nitoh
amiteh
be
Teacher's Signature

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