COA Unit 5 Input/Output

1. Interrupt:
The interrupt is a signal emitted by hardware or software when a process or an event needs
immediate attention. It alerts the processor to a high-priority process requiring interruption
of the current working process. In I/O devices one of the bus control lines is dedicated for
this purpose and is called the Interrupt Service Routine (ISR).
When a device raises an interrupt at let’s say process i, the processor first completes the
execution of instruction i. Then it loads the Program Counter (PC) with the address of the
first instruction of the ISR. Before loading the Program Counter with the address, the
address of the interrupted instruction is moved to a temporary location. Therefore, after
handling the interrupt the processor can continue with process i+1.
Software Interrupts:
A sort of interrupt called a software interrupt is one that is produced by software or a
system as opposed to hardware. Traps and exceptions are other names for software
interruptions. They serve as a signal for the operating system or a system service to carry
out a certain function or respond to an error condition.
Hardware Interrupts:
In a hardware interrupt, all the devices are connected to the Interrupt Request Line. A
single request line is used for all the n devices. To request an interrupt, a device closes its
associated switch. When a device requests an interrupt, the value of INTR is the logical OR
of the requests from individual devices.

The sequence of events involved in handling an IRQ (Interrupt Processing):

1. Devices raise an IRQ.
2. The processor interrupts the program currently being executed.
3. The device is informed that its request has been recognized and the device
deactivates the request signal.
4. The requested action is performed.
5. An interrupt is enabled and the interrupted program is resumed.
Handling Multiple Devices:
When more than one device raises an interrupt request signal, then additional information is
needed to decide which device to be considered first. The following methods are used to
decide which device to select: Polling, Vectored Interrupts, and Interrupt Nesting. These
are explained as following below.
1. Polling: In polling, the first device encountered with the IRQ bit set is the
device that is to be serviced first. Appropriate ISR is called to service the same.
It is easy to implement but a lot of time is wasted by interrogating the IRQ bit of
all devices.
2. Vectored Interrupts: In vectored interrupts, a device requesting an interrupt
identifies itself directly by sending a special code to the processor over the bus.
This enables the processor to identify the device that generated the interrupt.
3. Interrupt Nesting: In this method, the I/O device is organized in a priority
structure. Therefore, an interrupt request from a higher priority device is
recognized whereas a request from a lower priority device is not. The processor
accepts interrupts only from devices/processes having priority.
Exception:
Exception is a software interrupt, which can be identified as a special handler routine.
Exception can be identified as an automatically occurring trap. Generally, there are no
specific instructions associated with exceptions (traps are generated using a specific
instruction). So, an exception occurs due to an “exceptional” condition that occurs during
program execution.
Example –
Division by zero, execution of an illegal opcode or memory related fault could cause
exceptions. Whenever an exception is raised, the CPU temporarily suspends the program it
was executing and starts the ISR. ISR will contain what to do with the exception. It may
correct the problem or if it is not possible it may abort the program gracefully by printing a
suitable error message.

Hardware Interrupt Vs Software Interrupt

BASIS OF
HARDWARE INTERRUPT SOFTWARE INTERRUPT
COMPARISON

Software interrupt is the interrupt

Hardware interrupt is an interrupt
that is generated by any internal
Description generated from an external device or
system of the computer (instruction
hardware.
in the program).

Type Of The Hardware interrupts are asynchronized Software interrupts are

process events. synchronized events.

Effect On
Hardware interrupts do not increment Software interrupts increase the
Program
the program counter. program counter.
Counter

Hardware interrupt is a kind of

Software interrupt is a type of
computer system interrupt that occur
interrupt that is caused either by a
as a result of outside interference,
Cause special instruction in the
whether that’s from the user, from
instruction set or by an exceptional
peripherals, from other hardware
condition in the processor itself.
devices or through a network.
 Maskable interrupt and Non Maskable
Categories Normal interrupt Exception
interrupts.

Software interrupt is triggered by

Hardware interrupt is triggered by software (program instructions)
external hardware and is considered and considered one of the ways to
Trigger
one of the ways to communicate with communicate with kernel or to
the outside peripherals, hardware. trigger system calls, especially
during error or exception handling.

Hardware interrupt has the lowest Software interrupt has the highest
Priority
priority than software interrupts. priority than hardware interrupt.

Maskable Interrupt:
A maskable interrupt is a hardware interrupt that may be ignored by setting a bit in an
interrupt mask register’s (IMR) bit-mask. Maskable interrupts are those which can be
disabled or ignored by the microprocessor. The interrupts are either edge-triggered or level-
triggered or level-triggered. Examples of maskable interrupts include RST6.5, RST7.5,
RST5.5 of 8085 microprocessor.
What You Need to Know About Maskable Interrupt:
• Maskable interrupts help to handle lower priority tasks.
• Can be masked or made pending
• It is possible to handle a maskable interrupt after executing the current instruction.
• May be vectored or non-vectored
• Response time is high
• Used to interface with peripheral device.

Non-Maskable Interrupt:
Non-maskable interrupt (NMI) is a hardware interrupt that lacks an associated bit-mask;
therefore, it can never be ignored. It typically occurs to signal attention for non-recoverable
hardware errors. A non-maskable interrupt is often used when response time is critical or
when an interrupt should never be disable during normal system operation. Such uses include
reporting non-recoverable hardware errors, system debugging and profiling and handling of
species cases like system resets. TRAP is an example of non-maskable interrupt; it consists of
both level as well as edge triggering and is used in critical power failure conditions.
What You Need to Know About Non-Maskable Interrupt:
• Non-maskable interrupt help to handle higher priority tasks such as watchdog
timer.
• Cannot be masked or made pending
 • When a non-maskable interrupt occurs, the current instructions and status are
stored in stack for the CPU to handle the interrupt.
• All are vectored interrupts
• Response time is low
• Used for emergency purpose e.g. power failure, smoke detector etc
• Examples of non-maskable interrupt include RST1, RST2, RST3, RST4, RST5,
RST6, RST7 and TRAP of 8085 microprocessor.
Difference Between Maskable and Non-Maskable Interrupt
BASIS OF NON-MASKABLE
MASKABLE INTERRUPT
COMPARISON INTERRUPT

A non-maskable interrupt is a
Maskable interrupt is a hardware
hardware interrupt that cannot
Description Interrupt that can be disabled or ignored
be disabled or ignored by the
by the instructions of CPU.
instructions of CPU.

Non-maskable interrupt help to

Maskable interrupts help to handle
Function handle higher priority tasks such
lower priority tasks.
as watchdog timer.

Cannot be masked or made

Operation Can be masked or made pending
pending

When a non-maskable interrupt

It is possible to handle a maskable
Current occurs, the current instructions
interrupt after executing the current
Instructions and status are stored in stack for
instruction.
the CPU to handle the interrupt.

Nature May be vectored or non-vectored All are vectored interrupts

Response Time Response time is high Response time is low

Used for emergency purpose e.g

Used to interface with peripheral
Use power failure, smoke detector
device.
etc

Examples of non-maskable
Examples of maskable interrupts interrupt include RST1, RST2,
Examples include RST6.5, RST7.5, RST5.5 of RST3, RST4, RST5, RST6,
8085 microprocessor RST7 and TRAP of 8085
microprocessor.

A vectored interrupt is where the CPU actually knows the address of the interrupt service
routine in advance. All it needs is that the interrupting device sends its unique vector through
a data bus and through its I/O interface to the CPU. The CPU takes this vector, checks an
interrupt table in memory and then carries out the correct ISR for that device.
A non–vectored interrupt is where the interrupting device never sends an interrupt vector.
An interrupt is received by the CPU and it jumps the program counter to a fixed address in
hardware. This is typically a hard coded ISR which is device agnostic.
Vectored Interrupts:
• Devices that use vectored interrupts are assigned an interrupt vector. This is a
number that identifies a particular interrupt handler. The ISR address of this
interrupts is fixed and is known to CPU.
• When the device interrupts the CPU branches to the particular ISR.
• The microprocessor jumps to the specific service routine.
• When the microprocessor executes the call instruction, it saves the address of the
next instruction on the stack.
• At the end of the service routine, the RET instruction returns the execution to
where the program was interrupted.
• All 8051 interrupts are vectored interrupts.
Non-vectored Interrupt:
• Non-vectored interrupt is an interrupt that has a common ISR, which is common to
all non-vectored interrupts in the system. Address of this common ISR is known to
the CPU.
• The interrupts which don’t have fixed memory location for transfer of control from
normal execution.
• The address of the memory is sent along with the interrupt.
• The CPU crucially does not know which device caused the interrupt without
polling each I/O interface in a loop.
• Once the interrupt occurs, the system must determine which device, of all the
devices associated actually interrupted.
Key Differences:
1. Handling mechanism: Vectored interrupts are handled by a dedicated interrupt
vector table, which contains the addresses of the interrupt handlers for each device.
Non-vectored interrupts, use a single interrupt handler that must identify the
source of the interrupt.
2. Identification of source: In a vectored interrupt system, the interrupt controller
automatically identifies the source of the interrupt and routes it to the appropriate
interrupt handler. In non-vectored systems, the interrupt handler must use a polling
mechanism to determine the source of the interrupt.
3. Response time: Vectored interrupts have a faster response time than non-vectored
interrupts, as the system can quickly identify and route the interrupt to the
appropriate handler without the need for polling.
4. Complexity: Vectored interrupts are more complex than non-vectored interrupts,
as they require a dedicated interrupt vector table and additional hardware for
 routing interrupts. Non-vectored interrupts are simpler, as they only require a
single interrupt handler.
5. Flexibility: Non-vectored interrupts are more flexible than vectored interrupts, as
they can be used with a wide range of devices and don’t require specific interrupt
handling mechanisms. Vectored interrupts, on the other hand, are optimized for
specific devices and require specific interrupt handling mechanisms.
6. Debugging: Debugging vectored interrupts can be more difficult than debugging
non-vectored interrupts, as there are multiple interrupt handlers to manage and
potential conflicts to resolve. Non-vectored interrupts are simpler to debug, as
there is only one interrupt handler to manage.

2. Asynchronous Data Transfer:

This Scheme is used when speed of I/O devices do not match with microprocessor, and
timing characteristics of I/O devices is not predictable. In this method, process initiates the
device and check its status. As a result, CPU has to wait till I/O device is ready to transfer
data. When device is ready CPU issues instruction for I/O transfer. In this method two types
of techniques are used based on signals before data transfer.

i. Strobe Control ii. Handshaking

Strobe Signal:
The strobe control method of Asynchronous data transfer employs a single control line to
time each transfer. The strobe may be activated by either the source or the destination unit.
Data Transfer Initiated by Source Unit:

In the block diagram fig. (a), the data bus carries the binary information from source to
destination unit. Typically, the bus has multiple lines to transfer an entire byte or word. The
strobe is a single line that informs the destination unit when a valid data word is available.
The timing diagram fig. (b) the source unit first places the data on the data bus. The
information on the data bus and strobe signal remains in the active state to allow the
destination unit to receive the data.
Data Transfer Initiated by Destination Unit:
In this method, the destination unit activates the strobe pulse, to informing the source to
provide the data. The source will respond by placing the requested binary information on the
data bus.
The data must be valid and remain in the bus long enough for the destination unit to accept
it. When accepted the destination unit then disables the strobe and the source unit removes
the data from the bus.

Disadvantage of Strobe Signal:

The disadvantage of the strobe method is that, the source unit initiates the transfer has no
way of knowing whether the destination unit has actually received the data item that was
places in the bus. Similarly, a destination unit that initiates the transfer has no way of
knowing whether the source unit has actually placed the data on bus. The Handshaking
method solves this problem.

Handshaking:
The handshaking method solves the problem of strobe method by introducing a second
control signal that provides a reply to the unit that initiates the transfer.

Principle of Handshaking:
The basic principle of the two-wire handshaking method of data transfer is as follow:
One control line is in the same direction as the data flows in the bus from the source to
destination. It is used by source unit to inform the destination unit whether there a valid data
in the bus. The other control line is in the other direction from the destination to the source.
It is used by the destination unit to inform the source whether it can accept the data. The
sequence of control during the transfer depends on the unit that initiates the transfer.

Source Initiated Transfer using Handshaking:

The sequence of events shows four possible states that the system can be at any given time.
The source unit initiates the transfer by placing the data on the bus and enabling its data
valid signal. The data accepted signal is activated by the destination unit after it accepts the
data from the bus. The source unit then disables its data accepted signal and the system goes
into its initial state.
Destination Initiated Transfer Using Handshaking:
The name of the signal generated by the destination unit has been changed to ready for data
to reflects its new meaning. The source unit in this case does not place data on the bus until
after it receives the ready for data signal from the destination unit. From there on, the
handshaking procedure follows the same pattern as in the source-initiated case.
The only difference between the Source Initiated and the Destination Initiated transfer is
in their choice of Initial sate.

Advantage of the Handshaking method:

➢ The Handshaking scheme provides degree of flexibility and reliability because the
successful completion of data transfer relies on active participation by both units.
➢ If any of one unit is faulty, the data transfer will not be completed. Such an error can
be detected by means of a Timeout mechanism which provides an alarm if the data is
not completed within time.

3. Modes of Data Transfer:

Transfer of data is required between CPU and peripherals or memory or sometimes between
any two devices or units of your computer system. To transfer a data from one unit to another
one should be sure that both units have proper connection and at the time of data transfer the
receiving unit is not busy. This data transfer with the computer is Internal Operation.
All the internal operations in a digital system are synchronized by means of clock pulses
supplied by a common clock pulse Generator.
The data transfer can be
i. Synchronous ii. Asynchronous

When both the transmitting and receiving units use same clock pulse then such a data
transfer is called Synchronous process. On the other hand, if there is no concept of clock
pulses and the sender operates at different moment than the receiver then such a data transfer
is called Asynchronous data transfer.
The data transfer can be handled by various modes. some of the modes use CPU as an
intermediate path, others transfer the data directly to and from the memory unit and this can
be handled by 3 following ways:

(a) Programmed I/O

(b) Interrupt-Initiated I/O
(c) Direct Memory Access (DMA)

(a) Programmed I/O Mode:

In this mode of data transfer, the operations are the results in I/O instructions which is a
part of computer program. Each data transfer is initiated by an instruction in the program.
Normally the transfer is from a CPU register to peripheral device or vice-versa.
Once the data is initiated the CPU starts monitoring the interface to see when next transfer
can made. The instructions of the program keep close tabs on everything that takes place in
the interface unit and the I/O devices.

The transfer of data requires three instructions:

In this technique CPU is responsible for executing data from the memory for output
and storing data in memory for executing of Programmed I/O as shown in Flowchart-:
Drawback of the Programmed I/O:
The main drawback of the Program Initiated I/O was that the CPU has to monitor the units
all the times when the program is executing. Thus, the CPU stays in a program loop until the
I/O unit indicates that it is ready for data transfer. This is a time-consuming process and the
CPU time is wasted a lot in keeping an eye to the executing of program.
To remove this problem an Interrupt facility and special commands are used.

(b) Interrupt-Initiated I/O:

In this method an interrupt facility an interrupt command is used to inform the device about
the start and end of transfer. In the meantime, the CPU executes other programs. When the
interface determines that the device is ready for data transfer it generates an Interrupt
Request and sends it to the computer.
When the CPU receives such a signal, it temporarily stops the execution of the program and
branches to a service program to process the I/O transfer and after completing it returns back
to task, what it was originally performing.
• In this type of IO, computer does not check the flag. It continues to perform its task.
• Whenever any device wants the attention, it sends the interrupt signal to the CPU.
• CPU then deviates from what it was doing, store the return address from PC and
branch to the address of the subroutine.
• There are two ways of choosing the branch address:
• Vectored Interrupt
• Non-vectored Interrupt
• In vectored interrupt the source that interrupt the CPU provides the branch
information. This information is called interrupt vectored.
• In non-vectored interrupt, the branch address is assigned to the fixed address in the
memory.
The Execution process of Interrupt–Initiated I/O is represented in the flowchart:

(c) Direct Memory Access (DMA):

In the Direct Memory Access (DMA) the interface transfers the data into and out of the memory unit
through the memory bus. The transfer of data between a fast storage device such as magnetic disk and
memory is often limited by the speed of the CPU. Removing the CPU from the path and letting the
peripheral device manage the memory buses directly would improve the speed of transfer. This transfer
technique is called Direct Memory Access (DMA).
During the DMA transfer, the CPU is idle and has no control of the memory buses. A
DMA Controller takes over the buses to manage the transfer directly between the I/O
device and memory.
The CPU may be placed in an idle state in a variety of ways. One common method
extensively used in microprocessor is to disable the buses through special control
signals such as:
◼ Bus Request (BR)
◼ Bus Grant (BG)
These two control signals in the CPU that facilitates the DMA transfer. The Bus Request
(BR) input is used by the DMA controller to request the CPU. When this input is active, the
CPU terminates the execution of the current instruction and places the address bus, data bus
and read write lines into a high Impedance state. High Impedance state means that the
output is disconnected.
 The CPU activates the Bus Grant (BG) output to inform the external DMA that the
Bus Request (BR) can now take control of the buses to conduct memory transfer
without processor.
When the DMA terminates the transfer, it disables the Bus Request (BR) line. The
CPU disables the Bus Grant (BG), takes control of the buses and return to its normal
operation.
The transfer can be made in several ways that are:
i. DMA Burst
ii. Cycle Stealing
i) DMA Burst: - In DMA Burst transfer, a block sequence consisting of a
number of memory words is transferred in continuous burst while the DMA
controller is master of the memory buses.
ii) Cycle Stealing: - Cycle stealing allows the DMA controller to transfer one
data word at a time, after which it must returns control of the buses to the
CPU.
DMA Controller:
The DMA controller needs the usual circuits of an interface to communicate with the CPU and I/O
device. The DMA controller has three registers:
i. Address Register ii. Word Count Register iii. Control Register

i. Address Register: - Address Register contains an address to specify the desired location in
memory.
ii. Word Count Register: - WC holds the number of words to be transferred. The register is incr/decr
by one after each word transfer and internally tested for zero.
iii. Control Register: - Control Register specifies the mode of transfer

The unit communicates with the CPU via the data bus and control lines. The registers in the DMA are
selected by the CPU through the address bus by enabling the DS (DMA select) and RS (Register
select) inputs. The RD (read) and WR (write) inputs are bidirectional.
When the BG (Bus Grant) input is 0, the CPU can communicate with the DMA registers through the
data bus to read from or write to the DMA registers. When BG =1, the DMA can communicate
directly with the memory by specifying an address in the address bus and activating the RD or WR
control.
DMA Transfer:

The CPU communicates with the DMA through the address and data buses as with
any interface unit. The DMA has its own address, which activates the DS and RS
lines. The CPU initializes the DMA through the data bus. Once the DMA receives
the start control command, it can transfer between the peripheral and the memory.
When BG = 0 the RD and WR are input, lines allowing the CPU to communicate
with the internal DMA registers. When BG=1, the RD and WR are output lines
from the DMA controller to the random-access memory to specify the read or write
operation of data.
Note:
Why does DMA have priority over the CPU when both request a memory transfer?
DMA (Direct Memory Access) has priority over the CPU when both request a memory
transfer because DMA allows devices to transfer data to and from memory without
involving the CPU. This reduces the burden on the CPU and allows it to focus on other
tasks, improving overall system performance. DMA controllers are designed to handle
data transfers independently, and they can take control of the system bus to perform
these transfers without CPU intervention. This prioritization of DMA over the CPU for
memory transfers helps optimize the efficiency of data movement within a computer
system.

Peripheral Devices:
The Input / output organization of computer depends upon the size of computer and the
peripherals connected to it. The I/O Subsystem of the computer, provides an efficient mode
of communication between the central system and the outside environment
The most common input output devices are:
i) Monitor ii) Keyboard iii) Mouse iv) Printer v) Magnetic tapes

The devices that are under the direct control of the computer are said to be connected online.
Input - Output Interface:
Input Output Interface provides a method for transferring information between internal
storage and external I/O devices.
Peripherals connected to a computer need special communication links for interfacing them
with the central processing unit.
The purpose of communication link is to resolve the differences that exist between the central
computer and each peripheral.
The Major Differences are: -
1. Peripherals are electromechanical and electromagnetic devices and CPU and
memory are electronic devices. Therefore, a conversion of signal values may be
needed.
2. The data transfer rate of peripherals is usually slower than the transfer rate of CPU
and consequently, a synchronization mechanism may be needed.
3. Data codes and formats in the peripherals differ from the word format in the CPU
and memory.
 4. The operating modes of peripherals are different from each other and must be
controlled so as not to disturb the operation of other peripherals connected to the
CPU.
To Resolve these differences, computer systems include special hardware components
between the CPU and Peripherals to supervises and synchronizes all input and out transfers
These components are called Interface Units because they interface between the
processor bus and the peripheral devices.

I/O BUS and Interface Module:

It defines the typical link between the processor and several peripherals.
The I/O Bus consists of data lines, address lines and control lines.
The I/O bus from the processor is attached to all peripherals interface.
To communicate with a particular device, the processor places a device address on address
lines.
Each Interface decodes the address and control received from the I/O bus, interprets them
for peripherals and provides signals for the peripheral controller.
It is also synchronizing the data flow and supervises the transfer between peripheral and
processor.
Each peripheral has its own controller.
For example, the printer controller controls the paper motion, the print timing
The control lines are referred as I/O command. The commands are as following:
Control command- A control command is issued to activate the peripheral and to inform it
what to do.
Status command- A status command is used to test various status conditions in the interface
and the peripheral.
Data Output command- A data output command causes the interface to respond by
transferring data from the bus into one of its registers.
Data Input command- The data input command is the opposite of the data output.
In this case the interface receives on item of data from the peripheral and places it in its
buffer register. I/O Versus Memory Bus
 To communicate with I/O, the processor must communicate with the memory unit. Like the
I/O bus, the memory bus contains data, address and read/write control lines. There are 3
ways that computer buses can be used to communicate with memory and I/O:
i. Use two Separate buses, one for memory and other for I/O.
ii. Use one common bus for both memory and I/O but separate control lines for each.
iii. Use one common bus for memory and I/O with common control lines.

I/O Processor:
In the first method, the computer has independent sets of data, address and control buses one
for accessing memory and other for I/O. This is done in computers that provides a separate
I/O processor (IOP). The purpose of IOP is to provide an independent pathway for the
transfer of information between external device and internal memory.

 It is a processor with direct memory access capability that communicates with

IO devices.
 IOP is similar to CPU except that it is designed to handle the details of IO
operation.
 Unlike DMA which is initialized by CPU, IOP can fetch and execute its own
instructions.
 IOP instruction are specially designed to handle IO operation.

 Memory occupies the central position and can communicate with each
processor by DMA.
 CPU is responsible for processing data.
 IOP provides the path for transfer of data between various peripheral devices
and memory.
 Data formats of peripherals differ from CPU and memory. IOP maintain such
problems.
 Data are transfer from IOP to memory by stealing one memory cycle.
 Instructions that are read from memory by IOP are called commands to
distinguish them from instructions that are read by the CPU.
Instruction that are read from memory by an IOP:
» Distinguish from instructions that are read by the CPU
» Commands are prepared by experienced programmers and are stored in memory
» Command word = IOP program

Serial Communication in Computer organization:

Serial communication is the process of sequentially transferring the information/bits on the

same channel. Due to this, the cost of wire will be reduced, but it slows the transmission speed.
Generally, communication can be described as the process of interchanging information
between individuals in the form of audio, video, verbal words, and written documents. The
serial protocol is run on every device that can be our mobile, personal computers, and many
more with the help of following some protocols. The protocol is a type of reliable and secure
form of communication that contains a set of rules addressed with the help of a source host and
a destination host. In serial communication, binary pulses are used to show the data. Binary
contains the two numbers 0 and 1. 0 is used to show the LOW or 0 Volts, and 1 is used to show
the HIGH or 5 Volts. The serial communication can either be asynchronous or synchronous.
Synchronous Communication:
In synchronous communication, the frames or data will be constructed with the help of
combining the groups of bits. That frames will be continuously sent in time with a master clock.
It uses a synchronized clock frequency to operate the data of sender or receiver. In synchronous
communication, there is no need to use the gaps, start bits and stop bits. The time taken by the
sender and receiver is synced that's why the frequency of timing error will be less, and the data
will move faster. On the basis of the timing being synced correctly between the sender and
receiver devices, the data accuracy is totally dependent. The synchronous serial transmission
is more expensive as compared to asynchronous serial transmission.

Asynchronous Communication:
In asynchronous communication, the groups of bits will be treated as an independent unit,
and these data bits will be sent at any point in time. In order to make synchronization between
sender and receiver, the stop bits and start bits are used between the data bytes. These bits are
useful to ensure that the data is correctly sent. The time taken by data bits of sender and receiver
is not constant, and the time between transmissions will be provided by the gaps. In
asynchronous communication, we don't require synchronization between the sender and
receiver devices, which is the main advantage of asynchronous communication. This method
is also cost-effective. In this method, there can be a case when data transmission is slow, but it
is not compulsory, and it is the main disadvantage of the asynchronous method.

On the basis of the data transfer rate and the type of transmission mode, serial communication
will take many forms. The transmission mode can be classified into simplex, half-duplex, and
full-duplex. Each transmission mode contains the source, also known as sender or transmitter,
and destination, also known as the receiver.

Parallel processing:
• Parallel processing is a term used for a large class of techniques that
are used to provide simultaneous data-processing tasks for the purpose of increasing the
computational speed of a computer system.
 It refers to techniques that are used to provide simultaneous data processing.
  The system may have two or more ALUs to be able to execute two or more
instruction at the same time.
 The system may have two or more processors operating concurrently.
 It can be achieved by having multiple functional units that perform same or different
operation simultaneously.
• Example of parallel Processing:
– Multiple Functional Unit:
Separate the execution unit into eight functional units operating in parallel.
 There are variety of ways in which the parallel processing can be classified
 Internal Organization of Processor
 Interconnection structure between processors
 Flow of information through system

Architectural Classification:
Flynn's classification
» Based on the multiplicity of Instruction Streams and Data Streams
» Instruction Stream
Sequence of Instructions read from memory
» Data Stream
Operations performed on the data in the processor
  SISD represents the organization containing single control unit, a processor unit
and a memory unit. Instruction are executed sequentially and system may or may
not have internal parallel processing capabilities.
 SIMD represents an organization that includes many processing units under the
supervision of a common control unit.
 MISD structure is of only theoretical interest since no practical system has been
constructed using this organization.
 MIMD organization refers to a computer system capable of processing several
programs at the same time.
Note: The main difference between multicomputer system and multiprocessor
system is that the multiprocessor system is controlled by one operating system that
provides interaction between processors and all the component of the system
cooperate in the solution of a problem.