Time Stealing and Time Borrowing

Time borrowing:
https://www.physicaldesign4u.com/2020/05/time-borrowing-concept-in-sta.html
Here some more about Time borrowing .....

The High-speed CMOS clocking design style are --- time borrowing in Latches and time-
stealing in Edge triggered flip flop.

Since in an edge-triggered system, the operation time of each pipeline partition will
never equal to others and the longest logic delay between two registers will determine
the maximum clock frequency of the system.

In any circuit, the concept of how to fit more combinational logic within each logic
partition (between flip flops). So every pipeline partition will want more time than
allocated. Time borrowing and time-stealing which allows one stage to pass slack time
from fast logics to neighboring slower logic then we will remedy those problems.

Time borrowing by definition is permitting logic to automatically use slack time (borrow
the time) from a previous cycle. It always indicates the situation that logic partition in a
pipeline structure (flip flops and combinational delays are present between flip flops)
use leftover time from the previous stage and this passing of slack time from one cycle to
the next cycle is automatic without any additional circuitry or clock adjustments.

This transparent nature allows latches to be used for high-performance designs since
they offer more flexibility than edge-triggered circuits in terms of the minimum clock
period achievable – a result of time borrowing.

Method of borrowing time from the previous stage allowing combinational paths to have
a delay of more than the clock period is referred to variously as time borrowing or cycle
borrowing.
Time borrowing happens due to only the latches because latches are level sensitive.
Since the use of an edge-triggered structure must require a clock arrival time adjustment
at the circuit and this will violate the definition of time borrowing. So time borrowing is
ideally suitable for static logic in a two-phase clocking system latches (non-edge
triggered).

The advantage of slack (time) borrowing is that it allows logic between cycle boundaries
to use more than one clock cycle while satisfying the cycle time constraint. Mostly time
borrowing is only allowed in exceptional cases, which are carefully verified individually.

Time borrowing has been traditionally used to reduce the effect of clock skew and jitter
on the maximum clock frequency and it also has been widely used in critical delay paths
of high-speed circuits especially in high-speed adder designs.

Since time borrowing can automatically average out delay variations along a path caused
by process variation and inaccuracies, time borrowing is used to alleviate the mean
maximum clock frequency degradation caused by within-die parameter variations.
Time Stealing:
Time stealing gains time by taking it from the next cycle. Time stealing happens when
some logical partition needs additional time for evaluation but cannot use leftover time
from previous cycles or phases like in time borrowing.

Therefore the most important difference between time stealing and time borrowing is
that time-stealing will not automatically use the leftover time but time borrowing
automatically use the leftover time.

It has to be forced to steal evaluation time from the subsequence cycle and leave less
time to that cycle or phase which is achieved by adjusting clock arrival time. Since this
additional time is obtained by adjusting clock arrival time, it is usually used in edge-
triggered logic.

Time Stealing can be used when a particular logic partition needs additional time. The
additional time required should be deterministic at the time of the design and can adjust
the clock phase of capture Flip Flop (FF2), so that data arrival time at the capture edge
of FF2, will not violate setup.

So if a dynamic logic needs more time to evaluate, it has to increase its phase time by
widening the active clock time and this can only be done by shifting the rising edge
earlier or falling edge later.

This means instead of using the symmetric 2 phase system with a 50%duty cycle as
shown in time borrowing, time-stealing has to use asymmetric duty cycle to gain
additional time. Time stealing is used to reduce leakage power.

Time Stealing can be used when a particular logic paths need additional time. This
additional time should be deterministic at the time of the design so we can adjust the
phase of capture Flip Flop2 clock, so that data arrival time at the capture edge of Flip
Flop2, should not violate setup time.

In the fig, there are 4 flip flops and 4 combination logic circuits having
path1,path2,path3 and path4 delays are 12ns, 1ns, 8ns, and 1ns respectively.

The combinational delay in the first stage between FF1 and FF2 is path1 having a delay
of 12ns and it is higher than the clock time period (10ns). On the other hand, we have a
positive slack available in the second stage between FF2 and FF3 because of the smaller
combinational delay of path2 with a delay of 1ns. Here we were able to support the
higher combinational path delay (path1) without increasing the time period by
controlling the clock arrival time to FF2.

As shown in fig the path1 stole a time of 4ns (Ck2 offset, not the time borrowed by path1)
from path2 available time of 10ns, leaving path2 with 6ns. Since path2 needs only 1ns,
there is enough time for Flip Flop3 to capture data at 20ns.

The negative edge-triggered flip-flop is not used instead

If we replace Latch1 with negative edge-triggered flip-flop as shown in Fig, the path1 will
still have that extra 2.5 ns (half of the clock cycle) to borrow from the next clock cycle,
just like in latch. So why we are not using Flip flops in place of Latch.
On the input side, a negative edge triggered flip flop will behave just the same way as a
latch. The transparent nature of the latch will help to the succeeding stage to use positive
slack (leftover, if any) in the current stage OR pass on the negative slack in the current
stage to succeeding stage.

By comparing waveforms of both, we can understand the benefits of the LATCH over
negative edge triggered FLOP.

In the case of positive level-sensitive latch, data appears at the input of path2 (output of
latch1) at time = 2ns, because of the transparent nature of the latch (in case of negative
edge flop data appeared at the input of path2 at t = 2.5ns) so in this case, we have
a positive slack of 2 ns (5 – 3) ns.

Now let’s assume path2 requires 2.7 ns, data arrival time at second positive clock
edge is 2ns + 2.7ns = 4.7ns. The second positive clock edge occurs at t = 5 ns and in this
case we have a positive slack of 0.3 ns (5 – 4.7) ns.

In fig, in case of negative edge flop, the data appears at the input of path2 (output of
negative edge triggered FF) at time = 2.5 ns. With path2 consuming 1 ns, data arrives at
the output of path2 at 3.5 ns (2.5ns + 1ns) and we have a positive slack of 1.5 ns (5 ns
-3.5 ns).
Now, assume a situation where path2 requires 2.7ns, instead of 1ns so available time
is 2.5 ns and Required time by path2 is 2.7ns then in this situation, there is a timing
violation at the edge of the clock at t = 5 ns, with negative slack of 0.2 ns as shown in
fig below.

So as compared to positive level-sensitive latch in negative edge triggered flop the