CD74HC139,

Data sheet acquired from Harris Semiconductor

SCHS148A
CD74HCT139
High-Speed CMOS Logic
September 1997 - Revised May 1999 Dual 2-to-4 Line Decoder/Demultiplexer

Features Description
• Multifunction Capability The CD74HC139 and CD74HCT139 devices contain two
- Binary to 1 of 4 Decoders or 1 to 4 Line independent binary to one of four decoders each with a
[ /Title Demultiplexer single active low enable input (1E or 2E). Data on the select
(CD74 inputs (1A0 and 1A1 or 2A0 and 2A1) cause one of the four
• Active Low Mutually Exclusive Outputs normally high outputs to go low.
HC139
• Fanout (Over Temperature Range) If the enable input is high all four outputs remain high. For
,
- Standard Outputs . . . . . . . . . . . . . . . 10 LSTTL Loads demultiplexer operation the enable input is the data input.
CD74 - Bus Driver Outputs . . . . . . . . . . . . . 15 LSTTL Loads The enable input also functions as a chip select when these
HCT13 devices are cascaded. This device is functionally the same
• Wide Operating Temperature Range . . . -55oC to 125oC
9) as the CD4556B and is pin compatible with it.
/Sub- • Balanced Propagation Delay and Transition Times The outputs of these devices can drive 10 low power
ject • Significant Power Reduction Compared to LSTTL Schottky TTL equivalent loads. The 74HCT logic family is
(High Logic ICs functionally as well as pin equivalent to the 74LS logic family.

Speed • HC Types Ordering Information

CMOS - 2V to 6V Operation
Logic - High Noise Immunity: NIL = 30%, NIH = 30%of VCC at PKG.
VCC = 5V PART NUMBER TEMP. RANGE (oC) PACKAGE NO.
Dual
2-to-4 • HCT Types CD74HC139E -55 to 125 16 Ld PDIP E16.3
Line - 4.5V to 5.5V Operation CD74HCT139E -55 to 125 16 Ld PDIP E16.3
Decod - Direct LSTTL Input Logic Compatibility,
VIL= 0.8V (Max), VIH = 2V (Min) CD74HC139M -55 to 125 16 Ld SOIC M16.15
- CMOS Input Compatibility, Il ≤ 1µA at VOL, VOH CD74HCT139M -55 to 125 16 Ld SOIC M16.15
• Memory Decoding, Data Routing, Code Conversion NOTES:
1. When ordering, use the entire part number. Add the suffix 96 to
obtain the variant in the tape and reel.
2. Die is available which meets all electrical specifications. Please
contact your local sales office or customer service for ordering
information.

Pinout
CD74HC139, CD74HCT139
(PDIP, SOIC)
TOP VIEW

1E 1 16 VCC

1A0 2 15 2E

1A1 3 14 2A0

1Y0 4 13 2A1

1Y1 5 12 2Y0
1Y2 6 11 2Y1

1Y3 7 10 2Y2

GND 8 9 2Y3

CAUTION: These devices are sensitive to electrostatic discharge. Users should follow proper IC Handling Procedures.
Copyright © Texas Instruments Incorporated 1999
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 CD74HC139, CD74HCT139

Functional Diagram

4 (12)
Y0
2 (14)
5 (11)
A0
Y1
3 (13) 6 (10)
Y2
A1
7 (9)
Y3

1 (15)
E

TRUTH TABLE

INPUTS ENABLE SELECT OUTPUTS

E A1 A0 Y3 Y2 Y1 Y0

0 0 0 1 1 1 0

0 0 1 1 1 0 1

0 1 0 1 0 1 1

0 1 1 0 1 1 1

1 X X 1 1 1 1

NOTE: X = Don’t Care, Logic 1 = High, Logic 0 = Low

Logic Diagram

4 (12)
2 (14) Y0
A0
5 (11)
Y1
3 (13)
A1 6 (10)
Y2

7 (9)
1 (15) Y3
E

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 CD74HC139, CD74HCT139

Absolute Maximum Ratings Thermal Information

DC Supply Voltage, VCC . . . . . . . . . . . . . . . . . . . . . . . . -0.5V to 7V Thermal Resistance (Typical, Note 3) θJA (oC/W)
DC Input Diode Current, IIK PDIP Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90
For VI < -0.5V or VI > VCC + 0.5V . . . . . . . . . . . . . . . . . . . . . .±20mA SOIC Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 115
DC Output Diode Current, IOK Maximum Junction Temperature . . . . . . . . . . . . . . . . . . . . . . . 150oC
For VO < -0.5V or VO > VCC + 0.5V . . . . . . . . . . . . . . . . . . . .±20mA Maximum Storage Temperature Range . . . . . . . . . .-65oC to 150oC
DC Output Source or Sink Current per Output Pin, IO Maximum Lead Temperature (Soldering 10s) . . . . . . . . . . . . . 300oC
For VO > -0.5V or VO < VCC + 0.5V . . . . . . . . . . . . . . . . . . . .±25mA (SOIC - Lead Tips Only)
DC VCC or Ground Current, ICC or IGND . . . . . . . . . . . . . . . . . .±50mA

Operating Conditions
Temperature Range (TA) . . . . . . . . . . . . . . . . . . . . . -55oC to 125oC
Supply Voltage Range, VCC
HC Types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2V to 6V
HCT Types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4.5V to 5.5V
DC Input or Output Voltage, VI, VO . . . . . . . . . . . . . . . . . 0V to VCC
Input Rise and Fall Time
2V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1000ns (Max)
4.5V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 500ns (Max)
6V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 400ns (Max)
CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation
of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied.

NOTE:
3. θJA is measured with the component mounted on an evaluation PC board in free air.

DC Electrical Specifications
TEST
CONDITIONS 25oC -40oC TO 85oC -55oC TO 125oC
VCC
PARAMETER SYMBOL VI (V) IO (mA) (V) MIN TYP MAX MIN MAX MIN MAX UNITS
HC TYPES
High Level Input VIH - - 2 1.5 - - 1.5 - 1.5 - V
Voltage
4.5 3.15 - - 3.15 - 3.15 - V
6 4.2 - - 4.2 - 4.2 - V
Low Level Input VIL - - 2 - - 0.5 - 0.5 - 0.5 V
Voltage
4.5 - - 1.35 - 1.35 - 1.35 V
6 - - 1.8 - 1.8 - 1.8 V
High Level Output VOH VIH or VIL -0.02 2 1.9 - - 1.9 - 1.9 - V
Voltage
-0.02 4.5 4.4 - - 4.4 - 4.4 - V
CMOS Loads
-0.02 6 5.9 - - 5.9 - 5.9 - V
High Level Output - - - - - - - - - V
Voltage
-4 4.5 3.98 - - 3.84 - 3.7 - V
TTL Loads
-5.2 6 5.48 - - 5.34 - 5.2 - V
Low Level Output VOL VIH or VIL 0.02 2 - - 0.1 - 0.1 - 0.1 V
Voltage
0.02 4.5 - - 0.1 - 0.1 - 0.1 V
CMOS Loads
0.02 6 - - 0.1 - 0.1 - 0.1 V
Low Level Output - - - - - - - - - V
Voltage
4 4.5 - - 0.26 - 0.33 - 0.4 V
TTL Loads
5.2 6 - - 0.26 - 0.33 - 0.4 V
Input Leakage II VCC or - 6 - - ±0.1 - ±1 - ±1 µA
Current GND
Quiescent Device ICC VCC or 0 6 - - 8 - 80 - 160 µA
Current GND

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 CD74HC139, CD74HCT139

DC Electrical Specifications (Continued)

TEST
CONDITIONS 25oC -40oC TO 85oC -55oC TO 125oC
VCC
PARAMETER SYMBOL VI (V) IO (mA) (V) MIN TYP MAX MIN MAX MIN MAX UNITS
HCT TYPES
High Level Input VIH - - 4.5 to 2 - - 2 - 2 - V
Voltage 5.5
Low Level Input VIL - - 4.5 to - - 0.8 - 0.8 - 0.8 V
Voltage 5.5
High Level Output VOH VIH or VIL -0.02 4.5 4.4 - - 4.4 - 4.4 - V
Voltage
CMOS Loads
High Level Output -4 4.5 3.98 - - 3.84 - 3.7 - V
Voltage
TTL Loads
Low Level Output VOL VIH or VIL 0.02 4.5 - - 0.1 - 0.1 - 0.1 V
Voltage
CMOS Loads
Low Level Output 4 4.5 - - 0.26 - 0.33 - 0.4 V
Voltage
TTL Loads
Input Leakage II VCC and 0 5.5 - ±0.1 - ±1 - ±1 µA
Current GND
Quiescent Device ICC VCC or 0 5.5 - - 8 - 80 - 160 µA
Current GND
Additional Quiescent ∆ICC VCC - 4.5 to - 100 360 - 450 - 490 µA
Device Current Per -2.1 5.5
Input Pin: 1 Unit Load
(Note 4)
NOTE:
4. For dual-supply systems theoretical worst case (VI = 2.4V, VCC = 5.5V) specification is 1.8mA.

HCT Input Loading Table

INPUT UNIT LOADS

All 0.7

NOTE: Unit Load is ∆ICC limit specified in DC Electrical Table, e.g.,

360µA max at 25oC.

Switching Specifications Input tr, tf = 6ns

-40oC TO -55oC TO
25oC 85oC 125oC
TEST VCC
PARAMETER SYMBOL CONDITIONS (V) MIN TYP MAX MIN MAX MIN MAX UNITS

HC TYPES
Propagation Delay tPLH, tPHL CL = 50pF 2 - - 145 - 180 - 220 ns

A0, A1 to Outputs 4.5 - - 29 - 36 - 44 ns

6 - - 25 - 31 - 38 ns

E to Outputs tPLH, tPHL CL = 50pF 2 - - 135 - 170 - 205 ns

4.5 - - 27 - 34 - 41 ns

6 - - 23 - 29 - 35 ns

Select to Output tPLH, tPHL CL = 15pF 5 - 12 - - - - - ns

Enable to Output tPLH, tPHL CL = 15pF 5 - 11 - - - - - ns

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 CD74HC139, CD74HCT139

Switching Specifications Input tr, tf = 6ns (Continued)

-40oC TO -55oC TO
25oC 85oC 125oC
TEST VCC
PARAMETER SYMBOL CONDITIONS (V) MIN TYP MAX MIN MAX MIN MAX UNITS

Output Transition Time (Figure 1) tTLH, tTHL CL = 50pF 2 - - 75 - 95 - 110 ns

4.5 - - 15 - 19 - 22 ns

6 - - 13 - 16 - 19 ns

Power Dissipation CPD - 5 - 55 - - - - - pF

Capacitance, (Notes 5, 6)

Input Capacitance CIN - - - - 10 - 10 - 10 pF

HCT TYPES
Propagation Delay

A0, A1 to Outputs tPLH, CL = 50pF 4.5 - - 34 - 43 - 51 ns

tPHL

E to Outputs tPLH, CL = 50pF 4.5 - - 34 - 43 - 51 ns

tPHL

Select to Output tPLH, tPHL CL = 15pF 5 - 14 - - - - - ns

Enable to Output tPLH, tPHL CL = 15pF 5 - 14 - - - - - ns

Output Transition Time tTLH, tTHL CL = 50pF 4.5 - - 15 - 19 - 22 ns

(Figure 2)

Power Dissipation CPD - 5 - 59 - - - - - pF

Capacitance, (Notes 5, 6)

Input Capacitance CIN - - - - 10 - 10 - 10 pF

NOTES:
5. CPD is used to determine the dynamic power consumption, per decoder/demux.
6. PD = VCC2 fi (CPD + CL) where: fi = Input Frequency, CL = Output Load Capacitance, VCC = Supply Voltage.

Test Circuits and Waveforms

tr = 6ns tf = 6ns tr = 6ns tf = 6ns
VCC 3V
90% 2.7V
INPUT 50% INPUT 1.3V
10% GND 0.3V GND

tTHL tTLH tTHL tTLH

90% 90%
50%
INVERTING 10% INVERTING 1.3V
OUTPUT 10%
OUTPUT
tPHL tPLH tPHL tPLH

FIGURE 1. HC AND HCU TRANSITION TIMES AND PROPAGA- FIGURE 2. HCT TRANSITION TIMES AND PROPAGATION
TION DELAY TIMES, COMBINATION LOGIC DELAY TIMES, COMBINATION LOGIC

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Copyright  1999, Texas Instruments Incorporated