The VLSI Voyager

SATHYABAMA INSTITUTE OF SCIENCE AND TECHNOLOGY

DEPARTMENT OF ECE
COURSE MATERIAL
COURSE NAME: CMOS VLSI DESIGN COURSE CODE:SEC1316

UNIT-I (MOS TRANSISTOR THEORY)

The MOS transistor- Current Voltage Relations- Threshold Voltage- Second order effects-
Capacitances in MOSFET - Scaling of MOS circuits - Review of CMOS - DC characteristics -
Dynamic behaviour- Power consumption.

______________________________________________________________________

Introduction :

The MOSFET – Metal Oxide FET

As well as the Junction Field Effect Transistor (JFET), there is another type of Field Effect
Transistor available whose Gate input is electrically insulated from the main current carrying
channel and is therefore called an Insulated Gate Field Effect Transistor or IGFET. The most
common type of insulated gate FET which is used in many different types of electronic circuits is
called the Metal Oxide Semiconductor Field Effect Transistor or MOSFET for short.

The IGFET or MOSFET is a voltage controlled field effect transistor that differs from a JFET
in that it has a “Metal Oxide” Gate electrode which is electrically insulated from the main
semiconductor n-channel or p-channel by a very thin layer of insulating material usually silicon
dioxide, commonly known as glass. This ultra thin insulated metal gate electrode can be thought
of as one plate of a capacitor. The isolation of the controlling Gate makes the input resistance of
the MOSFET extremely high way up in the Mega-ohms (MΩ) region thereby making it almost
infinite.

As the Gate terminal is isolated from the main current carrying channel “NO current flows into
the gate” and just like the JFET, the MOSFET also acts like a voltage controlled resistor were the
current flowing through the main channel between the Drain and Source is proportional to the
input voltage. Also like the JFET, the MOSFETs very high input resistance can easily
accumulate large amounts of static charge resulting in the MOSFET becoming easily damaged
unless carefully handled or protected.

Characteristics of MOSFET :

1. Bilaterally Symmetric device

2. Unipolar device
3. High Input Impedance
4. Voltage Controlled
5. Self Isolated

MOS transistor performs very well as a switch; it introduces very few parasitic effects, simple
integration density, simple manufacturing process which make it possible to produce large and
complex circuits in an economical way.
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DEPARTMENT OF ECE
COURSE MATERIAL
COURSE NAME: CMOS VLSI DESIGN COURSE CODE:SEC1316

MOS Transistor Types and Construction :

MOSFETs are three terminal devices with a Gate, Drain and Source and both P-channel (PMOS)
and N-channel (NMOS) MOSFETs are available. Figure 1 represents the conduction
characteristics of MOS transistors.

n-Channel MOS : Majority carriers are electrons.

p-Channel MOS : Majority carriers are holes.

Positive/negative voltage applied to the gate (with respect to substrate)

enhances the number of electrons/holes in the channel and increases
conductivity between source and drain.

Vt defines the voltage at which a MOS transistor begins to conduct. For

voltages less than V t (threshold voltage), the channel is cut off.

Figure 1. Conduction characteristics of MOS transistors.

The main difference this time is that MOSFETs are available in two basic forms:

1. Depletion Type – the transistor requires the Gate-Source voltage, ( VGS ) to switch the
device “OFF”. The depletion mode MOSFET is equivalent to a “Normally Closed”
switch.
2. Enhancement Type – the transistor requires a Gate-Source voltage, ( VGS ) to switch
the device “ON”. The enhancement mode MOSFET is equivalent to a “Normally Open”
switch.

The symbols and basic construction for both configurations of MOSFETs are shown below.
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DEPARTMENT OF ECE
COURSE MATERIAL
COURSE NAME: CMOS VLSI DESIGN COURSE CODE:SEC1316

Figure 2. Construction and symbols of MOS transistors

The four MOSFET symbols above show an additional terminal called the Substrate and it is not
normally used as either an input or an output connection but instead it is used for grounding the
substrate. It connects to the main semiconductive channel through a diode junction to the body or
metal tab of the MOSFET. Usually in discrete type MOSFETs, this substrate lead is connected
internally to the source terminal. As in enhancement types, it can be omitted from the symbol for
clarification.

The line between the drain and source connections represents the semiconductive channel. If this
is a solid unbroken line then this represents a “Depletion” (normally-ON) type MOSFET as drain
current can flow with zero gate potential. If the channel line is shown dotted or broken it is an
“Enhancement” (normally-OFF) type MOSFET as zero drain current flows with zero gate
potential. The direction of the arrow indicates whether the conductive channel is a p-type or an
n-type semiconductor device.
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DEPARTMENT OF ECE
COURSE MATERIAL
COURSE NAME: CMOS VLSI DESIGN COURSE CODE:SEC1316

Basic MOSFET Structure and Symbol :

Figure 3. MOSFET Structure

The construction of the Metal Oxide Semiconductor FET is very different to that of the Junction
FET. Both the Depletion and Enhancement type MOSFETs use an electrical field produced by a
gate voltage to alter the flow of charge carriers, electrons for n-channel or holes for P-channel,
through the semiconductive drain-source channel. The gate electrode is placed on top of a very
thin insulating layer and there are a pair of small n-type regions just under the drain and source
electrodes. Figure 3 represents the MOSFET structure.The gate of a junction field effect
transistor, JFET must be biased in such a way as to reverse-bias the pn-junction. With a insulated
gate MOSFET device no such limitations apply so it is possible to bias the gate of a MOSFET in
either polarity, positive (+ve) or negative (-ve).This makes the MOSFET device especially
valuable as electronic switches or to make logic gates because with no bias they are normally
non-conducting and this high gate input resistance means that very little or no control current is
needed as MOSFETs are voltage controlled devices. Both the p-channel and the n-channel
MOSFETs are available in two basic forms, the Enhancement type and the Depletion type.

Enhancement-mode MOSFET:

The more common Enhancement-mode MOSFET or eMOSFET, is the reverse of the

depletion-mode type. Here the conducting channel is lightly doped or even undoped making it
non-conductive. This results in the device being normally “OFF” (non-conducting) when the
gate bias voltage, VGS is equal to zero. The circuit symbol shown above for an enhancement
MOS transistor uses a broken channel line to signify a normally open non-conducting channel.
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DEPARTMENT OF ECE
COURSE MATERIAL
COURSE NAME: CMOS VLSI DESIGN COURSE CODE:SEC1316

For the n-channel enhancement MOS transistor a drain current will only flow when a gate
voltage (VGS) is applied to the gate terminal greater than the threshold voltage (VTH) level in
which conductance takes place making it a transconductance device. The application of a
positive (+ve) gate voltage to n-type eMOSFET attracts more electrons towards the oxide layer
around the gate thereby increasing or enhancing (hence its name) the thickness of the channel
allowing more current to flow. This is why this kind of transistor is called an enhancement mode
device as the application of a gate voltage enhances the channel.

Increasing this positive gate voltage will cause the channel resistance to decrease further causing
an increase in the drain current, ID through the channel. In other words, for an n-channel
enhancement mode MOSFET: +VGS turns the transistor “ON”, while a zero or -VGS turns the
transistor “OFF”. Then, the enhancement-mode MOSFET is equivalent to a “normally-open”
switch.The reverse is true for the p-channel enhancement MOS transistor. When VGS = 0 the
device is “OFF” and the channel is open. The application of a negative (-ve) gate voltage to the
p-type eMOSFET enhances the channels conductivity turning it “ON”. Then for an p-channel
enhancement mode MOSFET: +VGS turns the transistor “OFF”, while -VGS turns the transistor
“ON”.

Enhancement-mode N-Channel MOSFET and circuit Symbols

Figure 4. Drain characteristics of eMOSFET

Enhancement-mode MOSFETs make excellent electronics switches due to their low “ON”
resistance and extremely high “OFF” resistance as well as their infinitely high input resistance
due to their isolated gate. Enhancement-mode MOSFETs are used in integrated circuits to
produce CMOS type Logic Gates and power switching circuits in the form of as PMOS (P-
channel) and NMOS (N-channel) gates. CMOS actually stands for Complementary MOS
meaning that the logic device has both PMOS and NMOS within its design. Figure 4 represents
the drain characteristics of Enhancement mode transistor.
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DEPARTMENT OF ECE
COURSE MATERIAL
COURSE NAME: CMOS VLSI DESIGN COURSE CODE:SEC1316

Figure 5. Symbols of eMOSFET transistors

Depletion-mode MOSFET :

The Depletion-mode MOSFET, which is less common than the enhancement mode types is
normally switched “ON” (conducting) without the application of a gate bias voltage. That is the
channel conducts when VGS = 0 making it a “normally-closed” device. The circuit symbol
shown above for a depletion MOS transistor uses a solid channel line to signify a normally
closed conductive channel.For the n-channel depletion MOS transistor, a negative gate-source
voltage, -VGS will deplete (hence its name) the conductive channel of its free electrons
switching the transistor “OFF”. Likewise for p-channel depletion MOS transistor a positive gate-
source voltage, +VGS will deplete the channel of its free holes turning it “OFF”.

In other words, for an n-channel depletion mode MOSFET: +VGS means more electrons and
more current. While a -VGS means less electrons and less current. The opposite is also true for
the p-channel types. Then the depletion mode MOSFET is equivalent to a “normally-closed”
switch.

Depletion-mode N-Channel MOSFET and circuit Symbols

The depletion-mode MOSFET is constructed in a similar way to their JFET transistor

counterparts were the drain-source channel is inherently conductive with the electrons and holes
already present within the n-type or p-type channel. This doping of the channel produces a
conducting path of low resistance between the Drain and Source with zero Gate bias. The drain
characteristics and the circuit symbols of depletion mode transistor are shown in Figure.6.
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DEPARTMENT OF ECE
COURSE MATERIAL
COURSE NAME: CMOS VLSI DESIGN COURSE CODE:SEC1316

Figure 6. Drain characteristics and symbols of Depletion MOS

Operating modes of nMOS transistor:

Three sets, of D.C conditions are needed to apply for understanding the operating modes of
nMOS transistor. There are three modes based on the magnitude of V gs is shown in Figure.7
and named as,

1. accumulation, 2. depletion 3. inversion.

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DEPARTMENT OF ECE
COURSE MATERIAL
COURSE NAME: CMOS VLSI DESIGN COURSE CODE:SEC1316

Depletion Mode

Inversion Mode

Figure 7. Operating modes of MOS transistor

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DEPARTMENT OF ECE
COURSE MATERIAL
COURSE NAME: CMOS VLSI DESIGN COURSE CODE:SEC1316

Enhancement mode Transistor action:-

The device requires a voltage to be applied before the channel is formed is called as
“Enhancement mode transistor”. Three basic sets of dc conditions required for understanding
the operating regions of MOS transistor. To establish the channel between the source and the
drain a minimum voltage ( Vt ) must be applied between gate and source. This minimum
voltage is called as Vth. There is no conducting channel present initially hence nMOS
enhancement is normally called as “OFF device. It is known as “threshold voltage” that is
required to form the channel to bring out transistor into conduction.

a) Vgs
>Vt
Vds =
0

Since Vgs > Vt and Vds = 0 the channel is formed but no current flows between
drain and source. This region is called Cut-off region.

b) Vgs > Vt
Vds < Vgs - Vt

This region is called the Non-Saturation Region or linear region where the drain current
increases linearly with Vds. When Vds is increased the drain side becomes more reverse biased
(hence more depletion region towards the drain end) and the channel starts to pinch. This is
called as the pinch off point.

c) Vgs > Vt
Vds > Vgs - Vt

This region is called Saturation Region where the drain current remains almost constant. As the
drain voltage is increased further beyond (Vgs-Vt) the pinch off point starts to move from the
drain end to the source end. Even if the Vds is increased more and more, the increased voltage
gets dropped in the depletion region leading to a constant current. The typical threshold voltage
for an enhancement mode transistor is given by Vt = 0.2 * Vdd.
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DEPARTMENT OF ECE
COURSE MATERIAL
COURSE NAME: CMOS VLSI DESIGN COURSE CODE:SEC1316

Figure.8 (a)(b)(c) Enhancement mode transistor with different Vds values

Current and Voltage Relationships of MOS transistor:

A mathematical description of enhancement MOSFET behavior is relatively straightforward

with just 3 equations. Specifically, the drain current iD can be expressed in terms of vGS and
vDS for each of the three MOSFET modes (i.e., Cutoff, Triode, Saturation).The drain to source
current is defined as the ratio between the charges induced in the channel and electron transit
time. This section first derives the current-voltage relationships for various bias conditions in a
MOS transistor. Although the subsequent discussion is centred on an nMOS transistor, the basic
expressions can be
derived for a pMOS transistor by simply replacing the electron mobility by the hole mobility
and reversing the polarities of voltages and currents.

As mentioned in the earlier section, the fundamental operation of a MOS transistor arises out of
the gate voltage VGS (between the gate and the source) creating a channel between the source
and the drain, attracting the majority carriers from the source and causing them to move towards
the drain under the influence of an electric field due to the voltage VDS (between the drain and
the source). The corresponding current IDS depends on both VGS and VDS .
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COURSE NAME: CMOS VLSI DESIGN COURSE CODE:SEC1316

Steps involved:
Let us consider the simplified structure of an nMOS transistor shown in Figure.9, in which
the majority carriers such as electrons flow from the source to the drain.
The conventional current flowing from the drain to the source is given by

Now, transit time = ( length of the channel) / (electron velocity) = L / v where

velocity is given by the electron mobility and electric field; or, Now, EDS

= VDS/ L, so that velocity Thus, the transit time is

At room temperature (300 K), typical values of the electron and hole mobility are given by

, and

The current-voltage relationship can be derived separately for the linear (or non-saturated)

region and the saturated region of operation.

Figure 9. Geometrical structure of nMOS transistor

Linear region:

Note that this region of operation implies the existence of the uninterrupted channel between the
source and the drain, which is ensured by the voltage relation VGS - Vth > VDS . In the channel,
the voltage between the gate and the source varies linearly with the distance x from the source
due to the IR drop in the channel.
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DEPARTMENT OF ECE
COURSE MATERIAL
COURSE NAME: CMOS VLSI DESIGN COURSE CODE:SEC1316

Assume that the device is not saturated and the average channel voltage is VDS /2. The

effective gate voltage or VG,eff = Vgs - Vth

Charge per unit area =

where Eg average electric field from gate to channel, : relative permittivity of oxide
between gate and channel (~4.0 for SiO2 ), and : free space permittivity (8.85 x 10 -14 F/cm).
So, induced charge is expressed as equation,

where W is the width of the gate and L is the length of channel.

Substitute the formula for Eg = {(Vgs -Vt ) – Vds /2 } / D D

is the oxide thickness

Thus, the current from the drain to the source may be expressed as

Thus, in the non-saturated region, where

...........................(1)

where the parameter

Writing , where W/L is contributed by the geometry of the device,

.......................................(2)
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DEPARTMENT OF ECE
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COURSE NAME: CMOS VLSI DESIGN COURSE CODE:SEC1316

Since, the gate-to-channel capacitance is (parallel plate capacitance), then

, so that equation may be written as

........................ .(3)

Denoting CG = C0 / WL where C0 is the gate capacitance per unit area,

...................... (4)

Saturated region: Under the voltage condition VGS - Vth = VDS , a MOS device is said to be in
saturation region of operation. In fact, saturation begins when VDS = VGS - Vth , since at this
point, the resistive voltage drop (IR drop) in the channel equals the effective gate-to-channel
voltage at the drain. One may assume that the current remains constant as VDS increases further.
Putting VDS = VGS - Vth , the equations (1-4) under saturation condition need to be modified as

................................... (5)

.................................................. (6)

..................................... (7)

....................................... (8)

Note: The expressions derived for IDS are valid for both the enhancement and the depletion
mode devices. However, the threshold voltage for the nMOS depletion mode devices (generally
denoted as Vtd ) is negative . From Figure of the typical current-voltage characteristics for nMOS
enhancement as well as depletion mode transistors, the corresponding curves for a pMOS device
may be obtained with appropriate reversal of polarity.
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COURSE NAME: CMOS VLSI DESIGN COURSE CODE:SEC1316

For an n -channel device with = 600 cm2/ V.s, C0 = 7 X 10-8 F/cm2 , W = 20 m, L =

2 m and Vth = VT0 = 1.0 V, let us examine the relationship between the drain current and the
terminal voltages.

Now, the current-voltage equation can be written as follows.

Threshold Voltage:

The threshold voltage Vth for a nMOS transistor is the minimum amount of the gate-to-source
voltage VGS necessary to cause surface inversion so as to create the conducting channel between
the source and the drain. For VGS< Vth , no current can flow between the source and the drain.
For VGS> Vth , a larger number of minority carriers (electrons in case of an nMOS transistor)
are drawn to the surface, increasing the channel current. However, the surface potential and the
depletion region width remain almost unchanged as VGS is increased beyond the threshold
voltage.

The physical components determining the threshold voltage are the following.

work function difference between the gate and the substrate.

gate voltage portion spent to change the surface potential.
gate voltage part accounting for the depletion region charge.
gate voltage component to offset the fixed charges in the gate oxide and the silicon-oxide
boundary.

Although the following analysis pertains to an nMOS device, it can be simply modified to
reason for a p-channel device. The work function difference between the doped polysilicon
gate and the p-type substrate, which depends on the substrate doping, makes up the first
component of the threshold voltage. The externally applied gate voltage must also account for
the strong inversion at the surface, expressed in the form
of surface potential 2 , where denotes the distance between the intrinsic energy level EI and
the Fermi level EF of the p-type semiconductor substrate.
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COURSE NAME: CMOS VLSI DESIGN COURSE CODE:SEC1316

The factor 2 comes due to the fact that in the bulk, the semiconductor is p-type, where EI is
above EF by , while at the inverted n-type region at the surface EI is below EF by , and
thus the amount of the band bending is 2 . This is the second component of the threshold
voltage. The potential difference between EI and EF is given as

second component of the threshold voltage. The potential difference between EI and EF is
given as

where k is the Boltzmann constant, T is the temperature, q : electron charge NA : acceptor

concentration in the p-substrate and ni is the intrinsic carrier concentration. The expression kT/q
is 0.02586 volt at 300 K. The applied gate voltage must also be large enough to create the
depletion charge. Note that the charge per unit area in the depletion region at strong inversion is
given by

where is the substrate permittivity. If the source is biased at a potential VSB with
respect to the substrate, then the depletion charge density is given by

The component of the threshold voltage that offsets the depletion charge is then given
by -Qd /Cox , where Cox is the gate oxide capacitance per unit area, or Cox = (ratio of the
oxide permittivity and the oxide thickness). A set of positive charges arises from the interface
states at the Si-SiO2 interface. These charges, denoted as Qi , occur from the abrupt termination
of the semiconductor crystal lattice at the oxide interface. The component of the gate voltage
needed to offset this positive charge (which induces an equivalent negative charge in the
semiconductor) is -Qi /Cox. On combining all the four voltage components, the threshold voltage
VTO, for zero substrate bias, is expressed as

For non-zero substrate bias, however, the depletion charge density needs to be modified to
include the effect of VSB on that charge, resulting in the following generalized expression for
the threshold voltage, namely
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The generalized form of the threshold voltage can also be written as

Note that the threshold voltage differs from VTO by an additive term due to substrate bias.
This term, which depends on the material parameters and the source-to-substrate voltage VSB, is given
by

Thus, in its most general form, the threshold voltage is determined as

........................... (1)
in which the parameter , known as the substrate-bias (or body-effect ) coefficient is given by

.................................... (2)

The threshold voltage expression given by (1) can be applied to n-channel as well as p-channel
transistors. However, some of the parameters have opposite polarities for the pMOS and the
nMOS transistors. For example, the substrate bias voltage VSB is positive in nMOS and negative
in pMOS devices. Also, the substrate potential difference
is negative in nMOS, and positive in pMOS. Whereas, the body-effect coefficient is positive
in nMOS and negative in pMOS. Typically, the threshold voltage of an enhancement mode n-
channel transistor is positive, while that of a p-channel transistor is negative.

Second order effects:

The current-voltage equations in the previous section however are ideal in nature. These have
been derived keeping various secondary effects out of consideration. The effects are, 1.
Threshold voltage variations 2.Subthreshold region 3. Channel length modulation 4.Mobility
variation 5. Fowler-Nordheim Tunneling 6. Drain Punch through 7.Impact Ionization

Threshold voltage and body effect: The threshold voltage Vth does vary with the voltage
difference Vsb between the source and the body (substrate). Thus including this difference, the
generalized expression for the threshold voltage is reiterated as

..................................... (3)
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in which the parameter , known as the substrate-bias (or body-effect ) coefficient is given by

Typical values of range from 0.4 to 1.2. It may also be written as

Drain punch-through:

In a MOSFET device with improperly scaled small channel length and too low channel doping,
undesired electrostatic interaction can take place between the source and the drain known as
drain-induced barrier lowering (DIBL) takes place. This leads to punch-through leakage or
breakdown between the source and the drain, and loss of gate control. One should consider the
surface potential along the channel to understand the punch-through phenomenon. As the drain
bias increases, the conduction band edge (which represents the electron energies) in the drain is
pulled down, leading to an increase in the drain-channel depletion width.

In a long-channel device, the drain bias does not influence the source-to-channel potential
barrier, and it depends on the increase of gate bias to cause the drain current to flow. However, in
a short-channel device, as a result of increase in drain bias and pull-down of the conduction band
edge, the source-channel potential barrier is lowered due to DIBL. This in turn causes drain
current to flow regardless of the gate voltage (that is, even if it is below the threshold voltage
Vth). More simply, the advent of DIBL may be explained by the expansion of drain depletion
region and its eventual merging with source depletion region, causing punch-through breakdown
between the source and the drain. The punch-through condition puts a natural constraint on the
voltages across the internal circuit nodes.

Sub-threshold region conduction:

The cutoff region of operation is also referred to as the sub-threshold region, which is
mathematically expressed as IDS =0 ; VGS < Vth However, a phenomenon called sub-threshold
conduction is observed in small-geometry transistors. The current flow in the channel depends on
creating and maintaining an inversion layer on the surface. If the gate voltage is inadequate to
invert the surface (that is, VGS< VT0 ), the electrons in the channel encounter a potential barrier
that blocks the flow. However, in small-geometry MOSFETs, this potential barrier is controlled
by both VGS and VDS .
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If the drain voltage is increased, the potential barrier in the channel decreases, leading to drain-
induced barrier lowering (DIBL). The lowered potential barrier finally leads to flow of electrons
between the source and the drain, even if VGS < VT0 (that is, even when the surface is not in
strong inversion). The channel current flowing in this condition is called the sub-threshold
current. This current, due mainly to diffusion between the source and the drain, is causing
concern in deep sub-micron designs. The model implemented in SPICE brings in an exponential,
semi-empirical dependence of the drain current on VGS in the weak inversion region. Defining a
voltage V on as the boundary between the regions of weak and strong inversion,

where Ion is the current in strong inversion for VGS =Von .

Channel length modulation :

so far one has not considered the variations in channel length due to the changes in drain-to-
source voltage VDS . For long-channel transistors, the effect of channel length variation is not
prominent. With the decrease in channel length, however, the variation matters. Figure shows
that the inversion layer reduces to a point at the drain end when

VDS = VDSAT = VGS -Vth .

That is, the channel is pinched off at the drain end. The onset of saturation mode operation is
indicated by the pinch-off event. If the drain-to-source voltage is increased beyond the saturation
edge (VDS > VDSAT ), a still larger portion of the channel becomes pinched off.
Let the effective channel (that is, the length of the inversion layer) be .
where L : original channel length (the device being in non-saturated mode), and : length of the
channel segment where the inversion layer charge is zero. Thus, the pinch-off point moves from the
drain end toward VDS the source with increasing drain-to-source voltage . The remaining portion of
the channel between the pinch-off point and the drain end will be in depletion mode. For the
shortened channel, with an effective channel voltage of VDSAT , the channel current is given by

...................... (1)
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The current expression pertains to a MOSFET with effective channel length Leff, operating in
saturation. The above equation depicts the condition known as channel length modulation, where
the channel is reduced in length. As the effective length decreases with increasing VDS, the
saturation current IDS(SAT) will consequently increase with increasing VDS . The current given
by (1) can be re-written as

..................(2)

The second term on the right hand side accounts for the channel modulation effect. It
can be shown that the factor channel length is expressible as

One can even use the empirical relation between and VDS given as follows.

The parameter is called the channel length modulation coefficient, having a value in
the range 0.02V -1 to 0.005V -1. Assuming that , the modified saturation
current expression can be written as

This simplified equation points to a linear dependence of the saturation current on the drain-to-
source voltage. The slope of the current-voltage characteristic in the saturation
region is determined by the channel length modulation factor .

Impact ionization:

An electron traveling from the source to the drain along the channel gains kinetic energy at the
cost of electrostatic potential energy in the pinch-off region, and becomes a “hot” electron. As
the hot electrons travel towards the drain, they can create secondary electron-hole pairs by
impact ionization. The secondary electrons are collected at the drain, and cause the drain current
in saturation to increase with drain bias at high voltages, thus leading to a fall in the output
impedance. The secondary holes are collected as substrate current. This effect is called impact
ionization.
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The hot electrons can even penetrate the gate oxide, causing a gate current. This finally leads to
degradation in MOSFET parameters like increase of threshold voltage and decrease of
transconductance. Impact ionization can create circuit problems such as noise in mixed-signal
systems, poor refresh times in dynamic memories, or latch-up in CMOS circuits. The remedy to
this problem is to use a device with lightly doped drain. By reducing the doping density in the
source/drain, the depletion width at the reverse-biased drain-channel junction is increase and
consequently, the electric filed is reduced. Hot carrier effects do not normally present an acute
problem for p -channel MOSFETs. This is because the channel mobility of holes is almost half
that of the electrons. Thus, for the same filed, there are fewer hot holes than hot electrons.
However, lower hole mobility results in lower drive currents in p -channel devices than in n -
channel devices.

Capacitances in MOSFET:

The parasitic transistor can be clearly seen in Figure as the N+ / P / N+ region between drain and
source. If the distance the current travels from the enhanced region across the source N+ region
is small, Rbe is negligible and the base collector junction of the parasitic transistor appears as a
diode.

Figure 10. MOSFET Capacitances

The equivalent circuit of an enhancement MOSFET is shown in Figure 10.

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Two parasitic capacitances between gate to source and gate to drain will cause switching delays
if the gate driver cannot support large initial currents. A further parasitic capacitance and
transistor exist between drain and source but due to the internal structure the transistor appears as
a diode and capacitor connected between drain and source as shown in Figure 6b. Unfortunately
the parasitic diode does NOT have the structure of a fast diode and must be neglected and a
separate fast diode used in a high speed switching circuit.

Gate Capacitances
The build-up and removal of the channel and its associated charge is similar to charging
and discharging a capacitor. In the case of the channel, this capacitor has an upper plate
or electrode, that is the MOS gate, and a lower electrode mad of three plates, the source,
the bulk (substrate) and the drain. Hence, charges can enter or leave the upper plate only
through the gate terminal. For the lower plate, the charges can enter/leave through any of
the three terminals (S, B and D).

Hence the channel charge is lumped (modeled) into three capacitances, as shown in the
figure below, Gate-to-Bulk capacitance (CGB), Gate-to-Source capacitance (CGS), and
Gate-to-Drain capacitance (CGD). These capacitances are not constant; their values
depend on the region of operation. CGS and CGD have two components, called overlap
capacitance, that are constant. They basically represent the capacitance between the gate
and S/D regions in the overlap area, as shown in the figure below. In the cut-off region,
where the channel region is in accumulation (of majority carriers), the gate capacitance is
the same as Cox (times L*W), and it is all to the bulk (i.e. CGS and CGD = 0).

When the device is on (i.e. channel is created and surface is in strong-inversion), the
channel charge shields the bulk from the gate, i.e. CGB becomes zero and the gate
capacitance is distributed between CGS and CGD. In linear region, the gate capacitance
is distributed equally between CGS and CGD while in saturation, almost all of the
channel charge is controlled by the source, i.e. CGD =0, while CGS =2/3 Cox* L*W.

The table below summarizes the values of the gate capacitances for the three different
regions of operation as a function of the oxide capacitance Cox, the device length L and
width W, and the overlap length LD between the gate and S/D regions. Also shown
below the table, a graph of the gate capacitances versus VGS for the different regions of
operation. For this graph, VDS is kept constant. The value of VGS that gives a minimum
total gate capacitance is actually the threshold voltage.
 SATHYABAMA INSTITUTE OF SCIENCE AND TECHNOLOGY
DEPARTMENT OF ECE
COURSE MATERIAL
COURSE NAME: CMOS VLSI DESIGN COURSE CODE:SEC1316

S/D Junction Capacitances

The source and drain forms diodes with the bulk. As seen before these diodes will have
junction capacitances that are dependent on the voltage difference between their
terminals. Hence, as the source or drain voltages change, these capacitances will be
charged or discharged. These capacitances, named CSB and CDB are also shown in the
Figure 11.below.

Gate

Source Drain
LD
CGB
CGS CGD

Bulk
CSB (Substrate) CDB
L

The MOS Capacitances

Cut-Off Saturation Linear

Region

Capacitance

CGB Cox*W*L 0 0

CGS LDWCox 2/3(CoxWL)+LDWCox ½(CoxWL)+LDWCox

CGD LDWCox LDWCox ½(CoxWL)+LDWCox

Values of Gate Capacitances at different regions

Scaling of MOS Circuits :

Scaling
Figure 12. MOSFET Scaling
 SATHYABAMA INSTITUTE OF SCIENCE AND TECHNOLOGY
DEPARTMENT OF ECE
COURSE MATERIAL
COURSE NAME: CMOS VLSI DESIGN COURSE CODE:SEC1316

To increase the number of devices per IC, the device dimensions had to be shrunk from
one generation to another (i.e. scaled down)There are two methods of scaling:
1. Full-Scaling (also called Constant-Field scaling): In this method the device
dimensions (both horizontal and vertical) are scaled down by 1/S, where S is the
scaling factor. In order to keep the electric field constant within the device, the
voltages have to be scaled also by 1/S such that the ratio between voltage and
distance (which represents the electric field) remain constant. The threshold voltage
is also scaled down by the same factor as the voltage to preserve the functionality of
the circuits and the noise margins relative to one another. As a result of this type of
scaling the currents will be reduced and hence the total power per transistor (P=IxV)
will also be reduced, however the power density will remain constant since the
number of transistors per unit area will increase. This means that the total chip power
will remain constant if the chip size remains the same (this usually the case).

Gate W
tox
X
j
L

Figure 13. MOSFET Scaling

The table 1 below summarizes how each device parameter scales with S (S>1)

Parameter Before scaling After scaling

Channel length L L/S

Channel width W W/S

Oxide thickness tox tox/S

S/D junction
depth Xj Xj/S

Power Supply VDD VDD/S

Threshold
voltage VTO VTO /S

Doping Density NA&ND NA *S and ND *S

Oxide
Capacitance Cox S*Cox
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DEPARTMENT OF ECE
COURSE MATERIAL
COURSE NAME: CMOS VLSI DESIGN COURSE CODE:SEC1316

Drain Current IDS IDS /S

Power/Transisto
r P P/S2

Power
Density/cm 2 p p
 SATHYABAMA INSTITUTE OF SCIENCE AND TECHNOLOGY
DEPARTMENT OF ECE
COURSE MATERIAL
COURSE NAME: CMOS VLSI DESIGN COURSE CODE:SEC1316

2. Constant-Voltage scaling (CVS): In this method the device dimensions (both

horizontal and vertical are scaled by S, however, the operating voltages remain
constant. This means that the electric fields within the device will increase (filed
=Voltage/distance). The threshold voltages remain constant while the power per
transistor will increase by S. The power density per unit area will increase by S 3! This
means that for the same chip area, the power chip power will increase by S 3. This
makes constant-voltage-scaling (CVS) very impractical. Table 2 represents the device
parameter scales under constant voltage.

3. Also, the device doping has to be increased more aggressively (by S 2) than the
constant-field scaling to prevent channel punch-through. Channel punch-through
occurs when the Source and Drain Depletion regions touches one another. By
increasing the doping by S2, the depletion region thickness is reduced by S (the same
ratio as the channel length). However, there is a limit for how much the doping can
be increased (the solid solubility limit of the dopant in Silicon). Again, this makes the
CVS impractical in most cases. The following table summarizes the changes in key
device parameters under constant-voltage scaling: In almost all cases, the scaling is a
combination of constant-field scaling and constant-voltage scaling, such that the
number of devices is increased and the total power/chip does not increase much.
Before
Parameter scaling After scaling

Channel length L L/S

Channel width W W/S

Oxide thickness tox tox/S

S/D junction
depth Xj Xj/S

Power Supply VDD VDD

Threshold
voltage VTO VTO

NA * S2 and ND
Doping Density NA&ND * S2

Oxide
Capacitance Cox S*Cox
 SATHYABAMA INSTITUTE OF SCIENCE AND TECHNOLOGY
DEPARTMENT OF ECE
COURSE MATERIAL
COURSE NAME: CMOS VLSI DESIGN COURSE CODE:SEC1316

Drain Current IDS IDS*S

Power/Transisto
r P P*S

Power
Density/cm 2 p p * S3