Analog & Digital VLSI

Design
EEE/ INSTR F313
BITS Pilani ANU GUPTA
Pilani Campus EEE
 BITS Pilani
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Digital VLSI Design

Concepts
• Boolean Algebra, and minimization

• Gates, Combinational networks

• Logic design with PLD

• FLIP FLOPS, counters

• Synchronous sequential networks-mealy / moore machine, state

table and its reduction

• ASM- design using ASM chart, state assignment, ASM tables, ASM
realizations

• Asynchronous sequential network-analysis, primitive flow table and

its reduction, races, hazards

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Digital VLSI Design

Digital VLSI Design

• Full Automation
• Maximum benefit of scaling
• High speed
• low power
• Robustness

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Design metrics
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Design of CMOS inverter

for long channel MOSFET s
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INVERTER

STATIC CHARACTERISTICS
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VTC-- DESIGN ISSUES

Static Power Consumption

Full Logic Levels

Sharp Transition

Switching Threshold→ Noise Margins

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PRACTICAL VTC

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FIVE CRITICAL VOLTAGES

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 SWITCHING THRESHOLD
• Vth= VM= Vinv

• Output changes its state

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Noise Margins

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BITS Pilani, Deemed to be University under Section 3 of UGC Act, 1956
Noise margin vs. noise
immunity.
Question---Does having a Noise margin always guarantee Noise immunity
????

Answer---- not always. How much noise margin is required depends on

the value of total noise generated in a system.

If value of total noise generated in a system is high, large noise margins

will be required that necessitates a high Vdd.

Working at low values of Vdd will not give noise immunity to a system. Else
noise reduction techniques to be used aggressively in design.

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Noise immunity –
required Signal magnitude/ swing to tolerate noise

Binary signaling----

Required swing

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Example---Noise immunity vs. noise
margin

Binary signaling----

Required swing

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Noise sources in a digital system -example

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Cross Talk ( swing dependent noise
source) - Coupling between Lines

Cross talk from a driven line, A, to a static line, B:

Any incremental voltage waveform on A will appear on B

attenuated by the capacitive voltage divider

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Cross talk reduction using keeper
MOSFET to maintain logic ‘1’ at B

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Implementation
Resistive load inverter
Reference: Kang. S.M and Leblebici Y., “CMOS Digital
Integrated Circuits: Analysis and Design,

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VOH

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Operating region of NMOS

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VOL

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VIH
VIL

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Design for Vol
SAT. ENHANCEMENT LOAD INV.
LIN. ENHANCEMENT LOAD INV.
CMOS INVERTER

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Static characteristics

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Operating regions
VOH
VOL
VIL
VIH
V inv=V th --- switching/ logic threshold
Long channel MOSFET-- VM
Long channel VM

Here kp defined is negative as ID= - IS.

Hence I (pmos) is positive
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Symmetric CMOS inverter

 Critical voltage
• Nothing
• We can design for wide noise margins
• Set Vth= ½Vdd
 Critical voltage
• Nothing
• We can design for wide noise margins
• Set Vth= ½Vdd
Choose appropriate VM
Impact of reducing Vdd on
VTC
Vdd ≥ Vtn + │Vtp│

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Reducing supply voltage
 Hysteresis behavior
• If the power supply voltage is reduced below the
sum of the two threshold –

• The VTC will contain a region in which none of

the transistors is conducting

• The output voltage level is determine by

previous state of the output

• The VTC exhibits a hysteresis behavior

Hysteresis behavior
 Vdd < Vtn + │Vtp│

Both
transistors
off
 CMOS Schmitt trigger ckt
used to improve signal slope and noise margins
CMOS BUFFER

SCHMITT TRIGGER
Steady state power
consumption ‘Pstatic’
Pstatic =0 in CMOS inverter

As no path between Vdd and Gnd for current to flow

As for logic ‘1’, PMOS OFF

For logic’0’, NMOS off

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Design of CMOS inverter in sub-

threshold region
Subthreshold region operated
MOS

Io represents the drain current when Vgs = Vt,

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 Subthreshold region threshold voltage
Vtsub

• Sub threshold region threshold voltage ‘Vtsub’ can be

defined as the voltage Vgs at which the drain current is

equal to 0.01Io,

• n= η= subthreshold slope factor

• parameter n is process dependent.

• Typical range of values for n is 1 to 1.5.

Id -- Vgs Characteristics
Id -- Vds Characteristics
Sub-threshold current
Subthreshold region VM ,
Vi= Vo

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Available operating range from Vt, sub to Vt
 Piecewise linear VTC
Noise margins in subthreshold region
Gain of subthreshold CMOS
inverter

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 Sub-threshold swing ‘S’

Required----

A device characterized by steep subthreshold slope (1/S) exhibits a faster

transition between off (low current) and on (high current) states.
 Subthreshold slope ‘1/S’
The transition from the ON state to the OFF state is gradual.
This is more clearly when ID is plotted on a logarithmic scale

log
scale
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Design of CMOS inverter

for short channel MOSFET s
THE SHORT CHANNEL
MOSFET

Operating condition --L> xd1+xd2

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Short channel MOSFET- DIBL

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 Punch through
• This continue until the VDS reaches value that deplete the
whole remaining neutral substrate region where the two space
charge region almost touch each other.
• As the voltage is increased further the drain space charge
region expands while the space charge region of the source
junction contracts
• This means that its internal electric field decreases which
means that the source junction becomes appreciable forward
biased
• So, the net barrier height at the source is appreciably
decrease which enables electrons to flow with large number
from source to drain.
• This is the punch through current signifying the onset of punch
through breakdown.
• Long-channel MOSFET is defined as devices with width and
length long enough so that edge effects from the four sides
can be neglected
• Short channel MOSFET is defined as devices with width and
length short enough such that the edge effects can not be
neglected.
• Channel length L is comparable to the depletion widths
associated with the drain and source, or , channel depletion
width in channel region before inversion layer appears..
• Channel length L must be much greater than the sum of the
drain and source depletion widths

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Velocity saturated device
 Short channel MOS

CONSTANT 105 m/s for silicon

Short channel MOS current
equation

This model is first order and empirical

Long Channel Vs. Short Channel
SAME
Long Channel Vs. Short Channel
Id vs Vgs
Extended sat. region operation

NMOS

PMOS

vsat= 105 m/sec, VDSATn= 0.63V, VDSATp= -1 V

 Switching threshold, Vm—
short channel CMOS Inv.

 w    p V DSATp 
 p c ox   V DSATp W p c ox 
 
 l  p  l  p W c ox v
r   
p SAT

 w    n V DSATn  W c ox v
 n c ox   V DSATn W n c ox   n SAT

 l n  l n
VM--For velocity saturated device-
inverter
Long channel VM
Finding VIL, VIH
Using Piece wise linear approx.
Gain of CMOS inverter
Inverter gain
 Gain of CMOS inverter
Alternative way

Drift velocity, Vde= µVdsat/ L = 105 m/sec

gds (in saturation) is dominated by channel length

modulation. Va is early voltage

1 I D sat
 g ds  Early Voltage, Va = 7 V / um
ro LVa
Noise margins
Short channel MOSFET--Estimation of NM
USING Piecewise lin. approx.
Determine g at Vin~Vm
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Slow/ fast MOSFET---PVT variations

Variation in VM by (W/L)
Impact Of Device Variations on Vm
Effect on kR= unCox[W/L]n / upCox[W/L]p
Why design for Vth≠ ½Vdd?
Choose appropriate VM
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END