Silicon (2022) 14:1053–1067

https://doi.org/10.1007/s12633-020-00904-5

REVIEW PAPER

Study and Analysis of Advanced 3D Multi-Gate

Junctionless Transistors
Raj Kumar 1 & Shashi Bala 2 & Arvind Kumar 1

Received: 16 October 2020 / Accepted: 14 December 2020 / Published online: 6 January 2021
# Springer Nature B.V. 2020

Abstract
As the IC technology is evolving very rapidly, the feature size of the device has been migrating to sub-nanometre regime for
achieving the high packing density. To continue with further scaling of ICs, some novel devices such as multiple-gate silicon-on-
insulator (SOI) devices, Gate-All-Around (GAA) nanowire and Nanotube MOSFETs have been proposed by researchers in
recent years. The short channel transistor below 10 nm needs to have ultra-sharp junctions at source and drain ends with the
channel region. The creation of such a sharp junction is quite challenging process from fabrication point of view. Therefore,
junctionless transistors (JLT) were proposed to eradicate junction’s related issues, exhibit full CMOS functionality. The multigate
junctionless transistors have been proposed, designed and fabricated. This paper illustrated basic working mechanism and
behaviour of the various single and multi-gate junctionless MOSFETs. Junctionless nanowires transistor with single circular
gate and gate material engineered techniques has also been explained. From simulation results, it has been observed that
junctionless Nanotube GAA MOSFET has shown superior electrical behaviour over the Nanowire GAA MOSFET.
Junctionless GaAs-Nanotube MOSFET has shown tremendous response over Junctionless Si-Nanotube MOSFET in terms of
leakage and ON current. Junctionless GaAs-Nanotube MOSFET may be observed as alternate candidate for future CMOS
applications.

Keywords Junctionless . Subthreshold . High-k . Nanowire . Nanotube . SCE

1 Introduction To follow the technology roadmap of ITRS, various ad-

vanced 3D MOSFETs architectures such as silicon on insula-
Over the past several decades, the planar MOS transis- tor (SOI), FinFET and GAA were proposed, analysed and
tors have been shrinking continuously to fuel the sus- fabricated at nanoscales regime. SOI architecture was de-
tainable growth of integrated-circuit (IC) technology. signed to have less leakage current but self-heating issues limit
MOS device’s scaling has been responsible for the en- consistency in device operation. However, GAA Nanowire
hancement in integrated circuits (ICs) such as enhanced MOSFET with sufficient electrical hold over the entire chan-
functionality, high speed and ultra-large-scale integration nel region provides improved immunity towards SCEs.
(ULSI). However, the severe short-channel effects However, low drive current and technological concerns of
(SCEs) such as drain induced barrier lowering (DIBL), the device may limit its utility [1–6]. Recently, a unique struc-
subthreshold swing (SS), velocity saturation, large leak- tured device double gate-all-around (DGAA) MOSFET or
age current have got appeared at the cost of perfor- silicon-nanotube (Si-NT) FET was proposed, can be a poten-
mance enhancement by the downsizing of transistors. tial candidate for future ULSI. Apart from this, carbon nano-
tubes and III-V compound semiconductor materials have also
been introduced for channel as silicon reached its limits for
* Shashi Bala further enhancement of mobility and driving current [7, 8].
[email protected] The traditional transistors even with multi-gates below
10 nm required to have an ultra-sharp doping profile within
1
University Institute of Engineering and Technology, Panjab
a couple of nanometres. Fabrication of extremely sharp junc-
University, Chandigarh, India tions at Source/Drain ends with channel region has put a great
2
Chandigarh Engineering College, Landran, Punjab, India
challenge in front of the semiconductor industry to boost the
1054 Silicon (2022) 14:1053–1067

performance of the device for low and standby power con- the carrier’s concentration becomes equal to doping concen-
sumption applications [9, 10]. To eliminate abovementioned tration ND [17, 18]. ON and OFF state can be described by the
junction-related design issues, Junctionless Transistors (JLT) energy band diagram of n-type JLT, depicted in Fig. 2. As the
was proposed as a novel structure. The heavily doped source, applied positive gate voltage becomes equal to the work func-
channel, and drain region are used to alleviate the formation of tion difference between the channel and the gate material, then
junctions and allow easy fabrication [11–13]. The working band becomes flat leading to turn on the device shown in Fig.
mechanism of JLT is quite different from conventional tran- 2a. The channel is fully depleted as there is no applied bias and
sistors. The channel turns off by depleting the charge carriers in off state as shown in Fig. 2b. In ON state, it acts as a resistor
from the channel by maintaining appropriate work-function and current flowing through a channel does not get affected by
difference between the gate and channel of the device. electric field perpendicular to the channel due to the bulk
Thereby, the bulk conduction occurs in the channel of the conduction in JLT unlike in inversion mode transistor [17,
JLT instead of surface conduction. Therefore, it offers minia- 18]. The band curvature is totally based on cross-sections of
turization of feature size of MOSFET with tremendous immu- nanowire.
nity towards short channel effects and power dissipation. In JLT, the distance between the non-depleted source and
“Punch through” problem is completely removed due to ab- drain larger than the actual gate length. That really impacts the
sence of junctions. The functionality and electrical perfor- short-channel characteristics of the device. On the other hand,
mance of nanowire JL MOSFET declare it as suitable candi- in a “regular”, tri-gate device, Junctions present at the source/
date for future CMOS applications [14–16]. In this paper, the channel and channel/ drain responsible for the reduction in
working of junctionless transistor will be discussed in section effective gate length of the device, lead to SCEs as shown in
II. Then, section III describes Junctionsless double-gate Fig. 3. Voltage-doping transformation model (VDT) to mea-
MOSFET, tri-gate MOSFET, Nanowire GAA transistor and sure the electrical parameters attributes to the effects of scaling
Nanotube Transistors along with different techniques used to down the design parameters i.e. gate length or drain voltage of
enhance their performance and future applications. device. For SCEs, the VDT model gives the following equa-
tions are [19].
" #
ɛsi X 2j t ox t dep ɛsi
SCE ¼ 0:64 1þ 2 V bi ¼ 0:64 EI V bi ð1Þ
2 Junctionless Transistor ɛox Lel Lel Lel ɛox

The JL MOSFET is basically silicon nanowire without PN,

NN+, PP+ junctions with a high uniform doping concentra-
tion in the source, channel and drain to have large ON current, " #
depicted in Fig. 1. Junctionless FET is basically an on-state ɛsi X 2j t ox t dep ɛsi
DIBL ¼ 0:84 1þ 2 V ds ¼ 0:64 EI V ds ð2Þ
device, forced to turn it off by depleting the channel fully ɛox Lel Lel Lel ɛox
attributed to appropriate work function between the gate ma-
terial and channel nanowire. The carriers in the channel are Here, Lel represents the effective channel length, tox is the
controlled by gate electrode is known as a gate resistor. The thickness of gate oxide, Xj gives the depth of source and drain
thickness of the nanowire should be small enough to deplete it junction, Vbi is built-in potential and ddep is the gate field
fully to turn off the transistor [17]. SCEs are far less than penetration depth in the channel region. EI is called the
inversion mode transistor owing to high doping concentration “Electrostatic Integrity” factor. EI depends upon the architec-
in channel. ture of the device and describes how does electric field exiting
Below threshold voltage, JLT is fully depleted and in an off from drain affects the channel region and causes SCEs [20].
state. The carrier’s density starts getting increase as the gate The threshold voltage of MOSFET can be calculated by Eqs.
voltage is increased and reached to the threshold voltage and (1) and (2). The large effective gate length of JLT is

Fig. 2 Band illustration for n-type JLT in (A) ON state (Flat band point)
Fig. 1 Schematic of Junctionless transistor and (B) OFF state (fully depleted channel). [18]
Silicon (2022) 14:1053–1067 1055

Fig. 3 Description of effective

channel length in (a) inversion-
mode and (b) junctionless
MOSFET [14]

responsible for the reduction in SCEs [21] and direct tunneling quite difficult [24–26]. An analytical model was derived to
from source-to-drain for short-channel devices. determine the potential across the channel region by using
the Schwarz Christoffel transformation. The calculated poten-
tial is further used to calculate threshold voltage and DIBL for
3 Multigate Junctionless Transistor both n- and p-type of double-gate MOSFETs [27].
Figure 4(a) depicts the 2D cross-sectional view of a
Multiple-gate SOI MOSFETs are being inquired and investi- junctionless double-gate MOSFET incorporating concentra-
gated for nanometre CMOS applications across the globe by tion profile. ϕs and ϕ0 are presenting the surface potential
semiconductor companies and researchers, as these devices and central potential of channel respectively. Figure 5(b) de-
show their credibility to push scaling beyond the limits of picts the energy band diagram from source to drain at thresh-
traditional technologies. The silicon nanowire is fully old voltage, in which ϕT and ϕB signifies the potential differ-
surrounded by a gate electrode that provides tremendous elec- ence between the Fermi level EF in the source region and
trostatic control over the channel region [22, 23]. In JLT, wire intrinsic level Ei in the channel, respectively. ϕmin is the min-
cross-section should be enough small for good coupling be- imum potential at the barrier due to being partially depleted
tween channel and gate to be fully depleted the channel region device, as shown in Fig. 4(c). In double-gate JLT, the thresh-
to turn the device off despite having a heavily doped channel. old voltage is immensely reduced with a reduction in device’s
The different multi-gate JLTs are discussed in this section. channel length. The effect on threshold appears even more
when drain voltage (Vd) increases, predominately at sub-
3.1 Planner Channel JLT 22 nm channel length due to the DIBL. In addition to that,
high doping causes reduction in threshold voltage. It was de-
The junctionless double-gate MOSFET was investigated, as termined that DIBL is not as influenced by doping concentra-
the depletion of the channel region fully with a single gate is tion as by decreasing channel length [28]. The gate material

Fig. 4 (a) Structure of DG Junction less FET (b) Band Diagram from Source to drain (c) Band Diagram from upper Gate to bottom gate [27]
1056 Silicon (2022) 14:1053–1067

Fig. 5 Electric field and density

of holes across the channel of the
device for (a) OFF and (b) ON
states [31]

should be of high work function to have reasonable threshold [31]. When highly doped p-type JLT is taken, then the band
voltages for highly doped devices. bending in the vertical direction is smaller than the inversion-
mode PMOS. Thereby, the gate-induced leakage effect is very
3.2 Rectangular GAA low in JL devices.
The holes carriers are predominantly right at the center of
GAA silicon nanowires are considered as the most suitable the channel regardless of the device’s operation [31], as
candidates for future generation’s high-performance ICs, as it pushed away by the electric field at the channel and oxide
exhibits the tremendous electrostatic gate controllability and interface, as shown in Fig. 5. GAA structure helps to deplete
carrier transport properties [29]. The architecture of GAA is channel region completely to turn OFF the transistor and pro-
highly suitable for JL transistors, as the surrounding gate de- vide a uniform electric field. However, holes concentration
pletes the channel region from all sides to make the device off increases, as electric field is not affecting the bulk conduction.
effectively [30]. P-type GAA JL nanowire transistors exhibit The excellent switching current ratio attributed to electric field
excellent Ion/off current ratio and electrical characteristics for distribution during ON and OFF state. The random dopant
short-channel owing to its fabrication of mid-gap gate material fluctuation (RDF) severely affects threshold voltage and

Fig. 6 (a) 3D view and (b) 2D

cross-sectional view of JL SRG
MOSFET
Silicon (2022) 14:1053–1067 1057

structure of a cylindrical surrounding gate or GAA

MOSFET provides better electrostatic hold over the channel
region.
Subthreshold characteristics of cylindrical GAA JLT de-
grade owing to DIBL [35]. That can be efficiently improved
by reducing the radius of the nanowire and thickness of gate
oxide for certain channel length. The threshold voltage VTH
for short channel, Cylindrical GAA FET drops as channel
length decreases. The threshold voltage can be calculated by
measuring the gate voltage as drain current reaches some val-
ue [36]. The subthreshold models with insight of Single cy-
lindrical surrounding gate (SCSG) JLT were also proposed
[37, 38]. They stated that fringe electric field causes the de-
pletion of the S/D region of SCSG JLT in OFF-state as the
transistor scale down to sub-32 nm. Circuit design perfor-
mance really gets affected by this issue. Then, subthreshold
model of the SCSG JLTs with inclusion of S/D depletion
effect was presented to improve the efficiency in the circuit
design [38].
Figure 7(a) shows that the central potential with source and
drain regions of SCSG JLT with and without incorporating the
S/D depletion effect. It can be seen that the central potential
with S/D depletion is smaller than without the S/D depletion
region. The transistor without S/D depletion region gave huge
drain current than that with the S/D depletion region and fur-
ther increases as scaling down the feature size of device as
shown in Fig. 7(b). The S/D depletion region provides great
short channel effects immunity to JLT [39]. Threshold voltage
predominantly measured by the minimum central potential of
channel for JLT. The minimum central potential increases
with effects of drain bias for short channel length leading to
Fig. 7 (a) Central potential distribution (b) drain current distribution [39] reduction in threshold voltage. SS of transistor represents how
efficiently gate can control channel and suppression the SCEs.
subthreshold swing. ON-state current is decreased due to The leakage current would be small for smaller SS with the
screening effect of carriers at high gate voltage bias. The nar- same ON-state current. SS increases with reduction in the
row channel with high doping device can be a challenge to channel length and radius of nanowires.
deplete it fully. Thereby, unwanted partially depleted channel
gets created [31]. At first, JLT was presented on an SOI sub-
strate owing to its scaling down capability. But, it’s non-
compatibility with standard CMOS technology and high fab-
rication cost causes to implement JLT on a bulk substrate [32].

3.3 Cylindrical GAA JL Nanowire Transistor

In the rectangular nanowire GAA JLTs, the width of nanowire

severely affects the performance parameters of the device. The
threshold voltage varies greatly with respect to nanowire
width and SCEs got even worse despite the GAA structure
due to corner effects. Additional S/D doping also affects the
gate control by shortening of effective gate length [33].
Therefore, a cylindrical GAA JL FET has been introduced to
Fig. 8 Illustration of energy Band diagram from source to drain for JLT
overcome these problems [33, 34]. Figure 6 shows the [42]
1058 Silicon (2022) 14:1053–1067

Fig. 9 Schematic view of dual

material gate junctionless
surrounding gate nanowire
MOSFET [60]

3.4 Gate-Material-Engineered Junctionless Nanowire resolved. BTBT was also found to be dependent on channel
Transistor (JLNWT) thickness and doping concentration of a JLT [42, 43].

Band to Band Tunneling (BTBT) In MOS transistor, a very high

electric field across drains causes impact ionization effect and Apart from BTBT and hot carrier’s effects, the device’s
BTBT, which generates hot carriers. These hot carriers further reliability depends upon the Localized charges, generat-
get trapped in oxide under the gate and alter the electrical ed throughout the manufacturing process is responsible
characteristics of the device such as drive current, subthresh- for degradation of device performance. These localized
old slope, transconductance, threshold voltage, and carrier charges are mainly generated due to process-induced
mobility [40, 41]. For n-channel JLT, depletion process of damage [44], stress-induced damage [45] and
heavily doped channel region of nanowire causes the valence radiation-induced damage [46]. The effects of hot car-
and conduction bands under the gate material are quit higher riers and localized charges have been explored widely
than source and drain end as shown in Fig. 8. for inversion mode tri-gate and GAA transistors
Fig. 8 shows that as negative bias increases at the gate to [47–49]. The effect can be seen on threshold voltage
deplete the channel, the valence and conduction bands in the for JL double-gate MOSFETs with localized charges
channel at the drain side get overlapped separately, which generated in dielectric of device [50].
motives the electrons tunneling between the two bands. This
BTBT gives rise to large leakage current while transistor in
OFF state. In nanoscale MOSFET, hot carrier induced degra- Gate-Material-Engineered Dual-material gate (DMG) FET, a
dation and BTBT are foremost reliability concerns, need to be technique called “Gate-Material Engineering (GME)” was

Fig. 10 2D Cross-sectional view of GME Vacuum JL Nanowire Fig. 11 Energy band diagram along the channel length for SGM JNT and
Transistor [65] SGMVJNT [65]
Silicon (2022) 14:1053–1067 1059

Table 1 Design Parameters of different Junctionless devices

Device Parameter JL DG FET SMG JL GAA GME JL GAA SGM SGM GME GME JLSiNW- JLSiNT-
FET MOSFET JLT VJLT JLT VJLT FET FET

Channel length (nm) 22 to 100 20 20 40 40 40 40 45 45

Gate oxide material Sio2 Sio2 Sio2 Al2o3 Vaccum Al2o3 Vaccum Sio2 Sio2
(20nm) (20nm)
/Al2o3 /Al2o3
Channel Material Silicon Silicon Silicon GaAs GaAs GaAs GaAs Si Si
Gate oxide Thickness (nm) 2 2 2 2 2 2 2 1 1
Gate Metal Work Fucntion 4.7 5.2 M1 5.2/ M2 4.2 4.8 4.8 5/4.6 5/4.6 4.94 4.68
Channel Thickness (nm) 10 10 10 10 10 10 10 10 10
Length of S/D 10 10 10 10 10 10 10 10 10
Source/Drain/Channel 1×1018 to 1×1019 1×1019 1×1019 7.3×1018 2.1×1019 2×1019 5×1018 1×1019
DopingND(cm−3) 5×1019

proposed to suppress the SCEs and improve carrier transport offered by gate material engineering [53]. GME JLGAA
efficiency as well [51, 52]. In this technique, gate material on nanowire transistors also offer a better immunity to SCEs as
source end must have high work function, behaves as the compared to non-gate engineered JLGAA MOSFET [58, 59].
“control gate” and gate material to be used at drain side need Triple metal (TM)-JLGAA devices are highly immunized to
to have lower work function, works as the “screening gate” SCEs. TM structures with gate length L1 > L2 > L3 offers bet-
that avoid channel region below the gate at source side to get ter VTh roll-off and steeper subthreshold swing due to its larger
affected due to the changes happens in drain bias. Two gate “control gate”. However, gate length L1 < L2 < L3 provides
metals M1 and M2 of different work functions are bound higher carrier-transport efficiency and better DIBL perfor-
together laterally shown in Fig. 9. Gate metal M1 has high mance due to its larger “screen gate” [58]. The presence of
work function greater than M2 i.e. ΦM1>ΦM2 . [53–57]. This two gates with different work functions (ΦM1 > ΦM2) in
configuration is used to enhance the electric field distribution GME architecture creates a step potential profile in the chan-
at the source side leads to an increase the carrier’s velocity and nel. Thus, electric field decreases at the drain and device deg-
screened the effect on potential due to drain bias. Work func- radation decreases due to the hot carrier’s effects lead to im-
tion of M2 needs to be greater than M1 for a p-type and vice- provement in its electrical characteristics. It is also observed
versa for an n-type MOSFET. The viability of fabrication can that for better threshold-voltage roll-off and DIBL perfor-
be the major issue of concern despite the several benefits mance of DMJLGAA devices, oxide thickness, and channel
radius are reduced [60].

Fig. 12 Band energy across the channel length for different junctionless Fig. 13 Band energy across the channel length for different work-
transistors [65] function differences [65]
1060 Silicon (2022) 14:1053–1067

Fig. 14 (a) 3D-structure of a

SiNT FET (b) Cross-section view
of SiNT FET depicting inner core
gate (c) Circular crossectional
view of SiNT FET [73]

GME JLT shows tremendous immunity against the local- dielectric increases. The gain of any device is decided by
ized charges induced degradation as compared to the single transconductance and must be high comparably to achieve
GM JLT and the effect of localized charges decreases as tem- high cut-off frequency [65]. The presence of a vacuum dielec-
perature elevates. Gaussian localized charge distribution pro- tric also decreases the gate to source capacitance (Cgs) in JNT
file shows less oxide destruction than a uniform localized that affects the speed of device. It is preferred to have low Cgs
charge distribution profile [61]. Then, to deal with reliability for effective speed and high cut-off frequency of device. Cgs
issues, researchers came up with different channel and gate was found lower in SGM-VJNT as compared to SGM JNT.
oxide materials. Transistors with the vacuum gate oxide at the Thereby, switching speed can be increased by having vacuum
drain side were proposed, as the hot carrier’s effects occur at dielectric with Al2O3 dielectric. The expression for cut-off
the drain side due high electric field [62–64]. GME technique frequency of device given below
with irregular gate oxide of JLT was also introduced. The
f T¼ 2πCgm ; where;C gg ¼C gs þC gd
source end occupied by Al2O3 dielectric and drain end filled gg

by vacuum dielectric to enhance hot carrier reliability. BTBT

of charge carriers also get affected by applying this technique, Cgg is the total gate capacitance. From the equation, it is
shown in Fig. 10 [65]. evident that the cut-off frequency can be increased by incor-
In JLT, BTBT is considered as a severe reliability issue porating a vacuum gate dielectric which decreases gate to
attributed to heavy doping throughout the channel region. source capacitance (Cgs). The design parameters of different
Depletion of charge carriers from the channel region in JLT junctionless devices are described in Table 1. Moreover, that
causes to drive valence and conduction bands of channel re- tunneling effects reduce with GME architecture, as the dis-
gion at higher positions than both the of source and drain tance between bands increases as shown in Fig. 12. In addition
regions [22]. The valence band and conduction band of the to that, Fig. 13 shows that the tunneling effects decrease with
channel and drain respectively get overlapped attributed to an increase in the work function difference of gate metals.
high drain bias. Therefore, tunneling of charge carriers from
valence to conductance band of the drain takes place signifi-
cantly in of-state lead to huge drain leakage current. The static
power dissipation due to BTBT creates huge challenge for low Table 2 Design Parameter
standby power applications [22, 23]. Therefore, to investigate
Design Parameter Values
tunneling effects, the BTBT standard model along with
Selberg impact ionization model is available. Figure 11 shows Gate length (Lg) 30 nm
the energy band diagram for single GMJLT and single GM Channel thickness (tGaAs) 10 nm
Vacuum JLT (SGM-VJLT). When vacuum dielectric at drain Oxide thickness (tox) 2 nm
side is placed, tunneling distances increases and tunneling will Inner gate radius (tc) 5 nm
be reduced due to electric field reduces as compared to Al2O3 Oxide material Hfo2
gate dielectric at drain end [65]. Metal workfuction (ɸ) 4.7
However, reduction in the drain-on current and Source/ Drain/channel doping ND 1×1019cm−3
transconductance can be seen as the length of vacuum
Silicon (2022) 14:1053–1067 1061

Fig. 15 3D structure of
junctionless GaAs-Nanotube
MOSFET

Asymmetric vacuum dielectric with gate material engineer- drive current, leading to having excellent OFF- and ON- state
ing of JNT at drain end can be used to improve ON-current electrical characteristics. Moreover, Si-NT transistors having
and transconductance. Cut-off frequency can also be en- subthreshold swing and DIBL lower than the conventional
hanced by using GME with a vacuum dielectric which makes and GAA MOSFETs because of presence of inner gate in
it suitable for analog applications. the transistor. Si-NT transistors provide superb resistance to
SCEs as compared to Si nanowire transistors because of pres-
3.5 Junctionless Nanotube Transistors ence of inner core gate [71–74].
Recently, the subthreshold and threshold voltage model of
Silicon-nanotube (SiNT) MOSFETs were investigated to Silicon-Nanotube-MOSFETs by Incorporating Quantum
know their suitability for future ultra large scale integration Confinement Effects for ultra-scaled devices was proposed.
(ULSI) applications. SiNT MOSFETs are considered as the The carrier’s distribution and transport properties in ultra-
most promising candidate for future ULSI due to its scalability scaled devices are quite different from the conventional de-
strength below 22 nm gate length effectively [66–70]. Silicon vice. The shift in threshold voltage and tunneling current can
nanotube FETs (SiNT-FET) has unique structure among be seen in ultra-scaled devices [75, 76]. The thickness of the
multigate structure device. The two gates, inner and outer nanotube is considered as an important parameter to observe
gate, wrap around the nanotube channel depicted in Fig. 14, its carrier transport properties [74]. The threshold voltage in-
provide tremendous performance over nanowires. Nanotube creases as channel length decrease for a fixed channel length
transistor provides better immunity against SCEs as well high attributed to increase in quantization energy in channel. The
threshold voltage decreases as oxide thickness increases ow-
ing to less gate control over the channel. DIBL effects also
found to be more severe with thicker channel due to control of
over the channel shifted drain [75]. Subthreshold current in
Nanotube MOSFETs increases with gate oxide thickness in-
crease owing to weak control over the channel. However, it
decreases as channel thickness decreases [76].
The SiNT-FET has two gates as outer and inner gates,
can be driven simultaneously (same bias applied to both
outer and inner gates) or independently (−different biased
applied at outer and inner gates) like double-gate FinFETs
[77–84]. It was observed that VTHand IOFF varied more as
control given at the outer gate compared to inner gate.
When both the gates use the same gate oxide thickness,
the independent gate operation was symmetrical for
double-gate FinFET in contrast to SiNT independent
mode operation [84]. SiNT FET with an inner gate as core
enhances electrostatic controllability of nanotube transis-
tors leads to increase the total gate capacitance. On other
Fig. 16 2D view of junctionless GaAs-Nanotube MOSFET
1062 Silicon (2022) 14:1053–1067

Fig. 17 Log (Ids) vs Vgs 1.00E-03

characteristics of JL GaAs and Si 1.00E-04
nanotube MOSFET with
Tox=2 nm, TGaAs=10 nm and 1.00E-05
Vds=0.05 1.00E-06
1.00E-07
1.00E-08

IDS(A)
JL Si-NT MOSFET
1.00E-09
JL GaAs-NT MOSFET
1.00E-10
1.00E-11
1.00E-12
1.00E-13
1.00E-14
0 0.2 0.4 0.6 0.8 1
VGS(V)

hand, underlap devices were designed to conquer the is- The effect of eccentricity has also been investigated for
sue of gate capacitance and showed tremendous improve- conventional and JL Si-NWT and JL Si-NT transistors [96].
ment in cut-off frequency (fT) and maximum oscillation Nanowires’ structure may be having square or circular cross-
frequency (fMAX) [85, 86]. section. But, the circular nanowires having lower effective
Junctionless NT MOSFET was proposed and investigated gate oxide thickness leading to excellent gate control over
by sahay et al. [87] and reported to have superior ION/IOFF the nanowire channel, even alleviate gate oxide tunneling
ratio as compared to JL NW MOSFETs. JL NT MOSFETs [97, 98]. Nanotubes show better immunity against the eccen-
provides tremendous Subthreshold Characteristics and SCEs tricity than Nanowires in terms of leakage current.
immunity [88–90]. Further, gate and oxide engineering Performance variation of JL NT MOSFETs due to tempera-
techniqus were also employed to improve the RF and digital ture has also been investigated and studied by Tayal et al. [99].
performance of junctionles NT MOSFETs [91–93]. Now, JL NT can be investigated, as it is considered as superior
Junctionless Silicon-Nanotube-FET (JLSiNT-FET) has candidate over other nanowires transistors for future use in
shown an impact on device performance on varying the tube digital applications.
thickness, by keeping one diameter constant, either inner or Silicon material as channel for CMOS is not preferred due
outer diameter of the tube [20]. Junctionless devices in nano- to its electrical limitations. Therefore, III-V semiconductor
regime are also suffering from some reliability issues for RFIC materials were proposed to replace silicon transistors to en-
Design [20, 94]. Hanna et al. [95], had also introduced the hance the device performance in terms of mobility and drive
fabrication feasibility of silicon nanotube. current [100–104]. Therefore, in this work, JL GaAs-

Fig. 18 Comparison of Log (Ids) 1.00E+00

vs Vgs characteristics of JL GaAs-
nanotube MOSFET between SiO2 1.00E-02
and HfO2 with Tox=2 nm,
TGaAs=10 nm and Vds=0.05 1.00E-04

1.00E-06
IDS(A)

1.00E-08
HfO2
1.00E-10
SiO2
1.00E-12

1.00E-14
0 0.2 0.4 0.6 0.8 1
VGS(V)
Silicon (2022) 14:1053–1067 1063

Fig. 19 Log (Ids) vs Vgs 1.00E-03

characteristics of JL GaAs-
nanotube MOSFET and GaAs- 1.00E-04
nanotube MOSFET between with
Tox=2 nm, TGaAs=10 nm and 1.00E-05
Vds=0.05
1.00E-06

IDS(A)
1.00E-07
GaAs-NT MOSFET
1.00E-08
JL GaAs-NT MOSFET
1.00E-09

1.00E-10

1.00E-11
0 0.2 0.4 0.6 0.8 1
VGS(V)

Nanotube n-MOSFET is designed and investigated with Comparison of Log (Ids) vs Vgs characteristics of JL GaAs-
VisualTCAD device simulator [105]. Nanotube MOSFET is nanotube MOSFET between SiO2 andHfO2 shown in Fig. 18.
also called Double gate all around (DGAA) MOSFETs owing It has been concluded that drive current increases and OFF
to presence of two gates. The 3D structure of junctionless current decreases significantly while replacing silicon oxide
GaAs-Nanotube MOSFET and 2D view of JL NT MOSFET (SiO2) with HfO2 as oxide.
are shown in Figs. 15 and 16 respectively. The design param- Form Fig. 19, transfer characteristics of JL GaAs-nanotube
eters considered for simulation are demonstrated in Table 2. MOSFET and GaAs-nanotube MOSFET are depicted. The
Numerical simulations of junctionless GaAs-Nanotube leakage current in JLNT MOSFET is less than junction based
MOSFET have been carried out by incorporating Drift diffu- nanotube MOSFET, whereas JL device suffering from Low
sion, SRH and unified mobility models by using genius 3D ON current. Comparison of Log (Ids) vs Vgs characteristics of
device simulator. Figure 17 shows the transfer characteristics JL-GAA MOSFET and JL-DGAA MOSFETs have also
of JL GaAs and Si nanotube MOSFET. It has been concluded done. From Fig. 20, it has been observed that a JL DGAA
that the GaAs based JLNT MOSFET has shown very less transistor gives better ON and OFF current against the JL-
leakage current (OFF-current) and high drive current (ON- GAA FET, as it provides tremendous electrostatics control
current) as compared to JL SiNT MOSFET. over the channel region due to presence of two gates.

Fig. 20 Comparison of Log (Ids) 1.00E-03

vs Vgs characteristics JL-NW
MOSFET and JL- NT MOSFET 1.00E-04
with Tox=2 nm, TGaAs=10 nm and
1.00E-05
Vds=0.05
1.00E-06
1.00E-07
IDS(A)

JL GaAs-NW MOSFET
1.00E-08
1.00E-09 JL GaAs-NT MOSFET

1.00E-10
1.00E-11
1.00E-12
0 0.2 0.4 0.6 0.8 1
VGS(V)
1064 Silicon (2022) 14:1053–1067

Therefore, JL-DGAA MOSFETs may be promising candidate current against the JL-GAA FET, as provides tremendous
for future CMOS technology. electrostatics control over the channel region due to presence
of two gates. JL-GaAs-NT MOSFET offers better results as
compared to JL-SiNT MOSFET in terms of leakage and ON
4 Digital Applications current. Now, JL NT transistors can be investigated, as it is
considered as superior candidate over other nanowires transis-
JLTs have been investigated over the years to show its func- tors for future use in digital applications.
tionality and DC performance. Thereby, they have shown tre-
mendous potential to use for future CMOS technology Acknowledgments Raj Kumar acknowledges the RGNF (UGC) for the
financial assistance and UIET (ECE), Panjab University for providing
[106–109]. It is very essential to see any of the device’s
Lab facility.
circuit-level performance to declare it as a prominent candi-
date for next-generation technology. Noise margins are one of Author Contributions All the authors have contributed in framing, writ-
the device metrics measure the performance of digital circuit. ing and proofreading the manuscript.
JL NW MOSFETs are considered inferior to inversion and
accumulation transistors due to their low ON-current [110, Data Availability The research data of this manuscript will not be
111]. However, JLT has provided very low intrinsic device available.
delay and also suppress overshoot effect in the circuits [112].
The ON current can be improved by replacing high-k dielec- Compliance with Ethical Standards This article does not
contain any studies involving animals or human participants performed
tric with silicon dioxide dielectric, leading to enhance the cir- by any of the authors.
cuit performance of JLT [113]. Gate oxide stacking and hetero
dielectric engineering also propped to improve the digital per- Conflict of Interest The authors declare that they have no conflicts of
formance of junctionless MOSFETs [114]. SRAM cell was interest.
also designed and investigated using high-k Junctionless NT
MOSFET for the enhancement of its digital performance Consent to Participate Not Applicable.
[115]. HfO2 as gate oxide considered as most preferable to
Consent for Publication Not Applicable.
improve JLTs circuit performance [115–117]. Therefore,
Junctionless NT MOSFETs can be further investigated with
different design material and parameters for their betterment
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