The complexity of a chip

Scale of integration:
Chapter 5 • SSI 1 - 10 gates
• MSI 10 - 100 gates
Logic Design with MSI Components • LSI 100 - 1000 gates
and Programmable Logic Devices • VLSI > 1000 gates

J. C. Huang, 2004 Digital Logic Design 1

Half Adder
Specialized MSI components
• adders x y sum carry
• comparators x Sum
0 0 0 0
• encoders/decoders 0 1 1 0
y Carry 1 0 1 0
• multiplexers/demultiplexers 1 1 0 1

sum = x’y + xy’

carry = xy

J. C. Huang, 2004 Digital Logic Design 2 J. C. Huang, 2004 Digital Logic Design 3

The Karnaugh maps for a full adder

Full Adder
xi yi ci ci+1 si
0 0 0 0 0
0 0 1 0 1
xi
si
0 1 0 0 1
yi 0 1 1 1 0
ci+1 1 0 0 0 1
ci
1 0 1 1 0
1 1 0 1 0
1 1 1 1 1

J. C. Huang, 2004 Digital Logic Design 4 J. C. Huang, 2004 Digital Logic Design 5

1
 A realization of the binary full adder

SUM and CARRY functions

SUM = x'y'c + x'yc' + xy'c' + xyc
CARRY = xy + yc + cx

J. C. Huang, 2004 Digital Logic Design 6 J. C. Huang, 2004 Digital Logic Design 7

Parallel binary subtracter constructed by using a parallel binary adder

Parallel (ripple) binary adder

Designed to add two binary numbers bit by bit

J. C. Huang, 2004 Digital Logic Design 8 J. C. Huang, 2004 Digital Logic Design 9

Parallel binary adder/subtracter

Carry-look-ahead adder
• Problem: the time required to do addition is
proportional to the number of bits involved.
• Solution: compute the carry for each stage
independently by using a carry-look-ahead
network.

J. C. Huang, 2004 Digital Logic Design 10 J. C. Huang, 2004 Digital Logic Design 11

2
 A carry lookahead adder. (a) General organization. (b) Sigma block
Carry-Look-ahead Adder

Recall that
ci+1 = xiyi + xici + yici =xiyi + (xi + yi)ci
Let gi = xiyi be the carry-generate function, and
pi = xi + yi be the carry-propagate function.
Σ Σ Σ
Then we can write ci+1 = gi + pici and
c1 = g0 + p0c0
c2 = g1 + p1g0 + p1p0c0
c3 = g2 + p2g1 + p2p1g0 + p2p1p0c0
…
We see that all carry signal ci can be computed by a two level logic
circuit.
J. C. Huang, 2004 Digital Logic Design 12 J. C. Huang, 2004 Digital Logic Design 13

A 4-bit carry lookahead adder

Cascade connection of 4-bit carry lookahead adders

J. C. Huang, 2004 Digital Logic Design 14 J. C. Huang, 2004 Digital Logic Design 15

A 4-bit carry look-ahead generator

A 16-bit high-speed adder

J. C. Huang, 2004 Digital Logic Design 16 J. C. Huang, 2004 Digital Logic Design 17

3
 Organization of a single-decade decimal adder Organization of a single-decade BCD adder

J. C. Huang, 2004 Digital Logic Design 18 J. C. Huang, 2004 Digital Logic Design 19

A single-decade BCD adder

Organization of a 1-bit comparator

J. C. Huang, 2004 Digital Logic Design 20 J. C. Huang, 2004 Digital Logic Design 21

Comparing two binary numbers A and B. (a) 1-bit comparator

network. (b) Cascade connection of 1-bit comparators.
From the truth table (Table 5.4) on page 247 we obtained

Gi+1 = AiB'i + AiGi + B'iGi

Ei+1 = A'iB'iEi + AiBiEi

Li+1 = A'iBi + BiLi + A'iLi

J. C. Huang, 2004 Digital Logic Design 22 J. C. Huang, 2004 Digital Logic Design 23

4
 A 2n-to-n-line encoder symbol
D0 D0
D1 D1
D2 D2
D3 8x3 3x8 D3
D4 encoder decoder
D4
D5 D5
D6 D6
D7 (sender) (receiver) D7

Main function of encoder and decoder

The purpose is to reduce the number of wires required for interconnection.

J. C. Huang, 2004 Digital Logic Design 24 J. C. Huang, 2004 Digital Logic Design 25

An 8-to-3-line encoder Symbol for an n-to-2n-line decoder

J. C. Huang, 2004 Digital Logic Design 26 J. C. Huang, 2004 Digital Logic Design 27

Decoder realization of f1(x2,x1,x0) =

A 3-to-8-line decoder Σm(1,2,4,5) and f2(x2,x1,x0) = Σm(1,5,7)
(a) Logic diagram.
(b) Truth table.
(c) Symbol

J. C. Huang, 2004 Digital Logic Design 28 J. C. Huang, 2004 Digital Logic Design 29

5
 Decoder realization of Boolean functions A decoder realization of f1(x2,x1,x0) = ΠM(0,1,3,5) and f2(x2,x1,x0) =
f1 = ΠM(2, 7) and f2 = ΠM(0, 5, 7) ΠM(1,3,6,7) (a) Using output or-gates. (b) Using output nor-gates.

J. C. Huang, 2004 Digital Logic Design 30 J. C. Huang, 2004 Digital Logic Design 31

A 3-to-8-line decoder using nand-gates Realization of the pair of maxterm canonical expressions
f1(x2,x1,x0) = ΠM(0,3,5) and f2(x2,x1,x0) = ΠM(2,3,4) with a
3-to-8-line decoder and two and-gates.

J. C. Huang, 2004 Digital Logic Design 32 J. C. Huang, 2004 Digital Logic Design 33

Realization of the Boolean expressions f1(x2,x1,x0) =

ΠM(0,1,3,4,7) with a 3-to-8-line decoder and two nand-gates. A decoder realization of f1(x2,x1,x0) = Σm(0,2,6,7) and f2(x2,x1,x0) =
Σm(3,5,6,7) (a) Using output and-gates. (b) Using output nand-gates.

J. C. Huang, 2004 Digital Logic Design 34 J. C. Huang, 2004 Digital Logic Design 35

6
 And-gate 2-to-4-line decoder with an enable input. (a) Logic Nand-gate 2-to-4-line decoder with an enable input
diagram. (b) Compressed truth table. (c) Symbol.

J. C. Huang, 2004 Digital Logic Design 36 J. C. Huang, 2004 Digital Logic Design 37

A 4-to-16-line D0 D0
D1
decoder constructed D1
D2
from 2-to-4-line D2
D3 8x1 1x8 D3
decoder demultiplexer
D4 multiplexer D4
D5 D5
D6 D6
D7 (sender) (receiver) D7

S2 S1 S0 S2 S1 S0
control signal control signal

Main function of multiplexer and demultiplexer

The purpose is to reduce the number of wires required for interconnection

by making the signals to time-share the link.

J. C. Huang, 2004 Digital Logic Design 38 J. C. Huang, 2004 Digital Logic Design 39

A multiplexer/demultiplexer arrangement A 4-to-1-line multiplexer

for information transmission.

J. C. Huang, 2004 Digital Logic Design 40 J. C. Huang, 2004 Digital Logic Design 41

7
 Demultiplexer A 2n-to-1-line multiplexer symbol

J. C. Huang, 2004 Digital Logic Design 42 J. C. Huang, 2004 Digital Logic Design 43

Example: f(x, y, z) = Σm(2, 5, 6, 7)

MUX implementation of a Boolean function

• Any Boolean function of n variables can be

implemented by a multiplexer with n x y z | f(x, y, z) | =
control inputs in a straightforward manner. 0 0 0 | f(0, 0, 0) | 0
0 0 1 | f(0, 0, 1) | 0
0 1 0 | f(0, 1, 0) | 1
0 1 1 | f(0, 1, 1) | 0
1 0 0 | f(1, 0, 0) | 0
1 0 1 | f(1, 0, 1) | 1
1 1 0 | f(1, 1, 0) | 1
1 1 1 | f(1, 1, 1) | 1

J. C. Huang, 2004 Digital Logic Design 44 J. C. Huang, 2004 Digital Logic Design 45

Implementing a function of 3 variables with a 4x1 MUX: Method 1

MUX implementation of a Boolean function

• Even better, any Boolean function of n I0

variables can be implemented by a
I1
multiplexer with n-1 control inputs as f(x, y, z)
illustrated in the following. I2

I3
s1 s0

x y

J. C. Huang, 2004 Digital Logic Design 46 J. C. Huang, 2004 Digital Logic Design 47

8
 The value for input I0 is to be determined as follows.
Using a multiplexer to implement a Boolean function: Method 1
if f(0, 0, 0) = and f(0, 0, 1) = then f(0, 0, 0)x'y'z' + and thus we should
f(0, 0, 1)x'y'z = let I0 =
Note that the output of a 4x1 multiplexer is 0 0 0=x'y'0 0
F(x, y, z) = x'y'I0 + x'yI1 + xy'I2 + xyI3 0 1 x'y'z z
1 0 x'y'z' z'

Now, given a Boolean function 1 1 x'y'=x'y'1 1

f(x, y, z) = f(0, 0, 0)x'y'z' + f(0, 1, 0)x'yz' + f(1, 0, 0)xy'z' + f(1, 1, 0)xyz'

+f(0, 0, 1)x'y'z + f(0, 1, 1)x'yz + f(1, 0, 1)xy'z + f(1, 1, 1)xyz The value for I1 , I2 , and I3 are to be determined in a similar manner.

J. C. Huang, 2004 Digital Logic Design 48 J. C. Huang, 2004 Digital Logic Design 49

Implementing a function of 3 variables with a 4x1 MUX: Method 2

Using a multiplexer to implement a Boolean function: Method 2

I0
Note that the output of a 4x1 multiplexer is
I1
f(x, y, z) F(x, y, z)= I0y'z' + I1y'z + I2yz' + I3yz
I2

I3 Now, given a Boolean function

s1 s0 f(x, y, z) = f(0, 0, 0)x'y'z' + f(0, 0, 1)x'y'z + f(0, 1, 0)x'yz' + f(0, 1, 1)x'yz
+ f(1, 0, 0)xy'z' + f(1, 0, 1)xy'z + f(1, 1, 0)xyz' + f(1, 1, 1)xyz
y z

J. C. Huang, 2004 Digital Logic Design 50 J. C. Huang, 2004 Digital Logic Design 51

A multiplexer tree to form a

16-to-1-line multiplexer
The value for input I0 is to be determined as follows.
if f(0, 0, 0) = and f(0, 0, 1) = then f(0, 0, 0)x'y'z' + and thus we should
f(1, 0, 0)xy'z' = let I0 =
0 0 0=0y'z' 0
0 1 xy'z' x
1 0 x'y'z' x'
1 1 y'z'=1y'z' 1

The value for I1 , I2 , and I3 are to be determined in a similar manner.

J. C. Huang, 2004 Digital Logic Design 52 J. C. Huang, 2004 Digital Logic Design 53

9
Realization of a three-variable function Example: realization of f(x,y,z) = Σm(0,2,3,5)
using a 8-to-1-line multiplexer.
(a) Three-variable truth table.
(b) General realization.

J. C. Huang, 2004 Digital Logic Design 54 J. C. Huang, 2004 Digital Logic Design 55

Realization of f(x,y,z) = Σm(0,2,3,5) using a 4-to-1-line multiplexer

Realizing a 3-variable Boolean function with a 4-to-1 multiplexer

J. C. Huang, 2004 Digital Logic Design 56 J. C. Huang, 2004 Digital Logic Design 57

Obtaining multiplexer realizations using Karnaugh maps.

Realization of f(x,y,z) = Σm(0,2,3,5).
(a) Cell groupings corresponding to the data line functions.
(a) Karnaugh map.
(b) Karnaugh maps for the Ii subfunctions. (b) I0, I1, I2, and I3 submaps.

J. C. Huang, 2004 Digital Logic Design 58 J. C. Huang, 2004 Digital Logic Design 59

10
Using Karnaugh maps to obtain multiplexer realizations under various
Alternative realizations of f(x,y,z) = Σm(0,2,3,5).
assignments to the select inputs.
(a) Applying input variables y and z to the S1 and S0 select lines.
(b) Applying input variables x and y to the S0 and S1 select lines.

J. C. Huang, 2004 Digital Logic Design 60 J. C. Huang, 2004 Digital Logic Design 61

A select line assignment and corresponding data line functions

Realizations of f(w,x,y,z) = Σm(0,1,5,6,7,9,12,15).
for a multiplexer realization of a four-variable function.

J. C. Huang, 2004 Digital Logic Design 62 J. C. Huang, 2004 Digital Logic Design 63

Using a four-variable Karnaugh map to obtain a Boolean Realizations of the Boolean function
function realization with a 4-to-1-line multiplexer. f(w,x,y,z) = Σm(0,1,5,6,7,9,13,14).

J. C. Huang, 2004 Digital Logic Design 64 J. C. Huang, 2004 Digital Logic Design 65

11
 General structure of Programmable Logic Buffer/inverter. (a) Symbol. (b) Logic equivalent
Devices (PLDs)

J. C. Huang, 2004 Digital Logic Design 66 J. C. Huang, 2004 Digital Logic Design 67

Programming by blowing fuses.

Types of PLDs (a) Before programming.
(b) After programming.

Device AND-array OR-array

PROM Fixed Programmable
PLA Programmable Programmable
PAL Programmable Fixed

J. C. Huang, 2004 Digital Logic Design 68 J. C. Huang, 2004 Digital Logic Design 69

Structure of a PROM
PLD notation

J. C. Huang, 2004 Digital Logic Design 70 J. C. Huang, 2004 Digital Logic Design 71

12
A 2n × m PROM.
(a) Logic diagram. Using a PROM for logic design. (a) Truth table. (b) PROM realization.
(b) Representation in PLD notation.

J. C. Huang, 2004 Digital Logic Design 72 J. C. Huang, 2004 Digital Logic Design 73

Example of combinational logic design using a PLA. (a) Maps showing the
multiple-output prime implicants. (b) Partial covering of the f1 and f2 maps. (c)
Maps for the multiple-output minimal sum. (d) Realization using a 3 × 4 × 2
Logic diagram of PLA.
an n × p × m PLA

J. C. Huang, 2004 Digital Logic Design 74 J. C. Huang, 2004 Digital Logic Design 75

Example of combinational logic design using a PLA. (a) Maps

showing the multiple-output prime implicants. (b) A multiple- Exclusive-or-gate with a programmable fuse.
output minimal sum covering. (c) Alternative multiple-output (a) Circuit diagram. (b) Symbolic representation.
minimal sum covering. (d) Realization using a 3 × 4 × 2 PLA.

J. C. Huang, 2004 Digital Logic Design 76 J. C. Huang, 2004 Digital Logic Design 77

13
 General structure of a PLA having true Karnaugh maps for the functions f1(x,y,z) = Σm(1,2,3,7)
and complemented output capability and f2(x,y,z) = Σm(0,1,2,6)

J. C. Huang, 2004 Digital Logic Design 78 J. C. Huang, 2004 Digital Logic Design 79

A simple four-input, three-output PAL device.

Two realizations of f1(x,y,z) = Σm(1,2,3,7) and f2(x,y,z) = Σm(0,1,2,6).

J. C. Huang, 2004 Digital Logic Design 80 J. C. Huang, 2004 Digital Logic Design 81

An example of using a PAL device to realize two Boolean

functions. (a) Karnaugh maps. (b) Realization.

A PLD programming unit

J. C. Huang, 2004 Digital Logic Design 82 J. C. Huang, 2004 Digital Logic Design 83

14
 Limitations of PLAs and PALs
These chips are limited to fairly modest
size, typically supporting a combined
number of inputs plus outputs of not more
than 32.

d
o ar
tb
cui
d ci r
nte
Pri

A PLCC package with socket

J. C. Huang, 2004 Digital Logic Design 84 J. C. Huang, 2004 Digital Logic

Slide Design
3.31.1 85

Complex Programmable Logic Devices

I/O block

I/O block
(CPLDs) PAL-like
block
PAL-like
block

A CPLD comprises multiple PAL-like

blocks on a single chip with internal wiring
resources to connect the circuit blocks. Interconnection wires

It is made to implement complex circuits

I/O block

I/O block
PAL-like PAL-like
that cannot be done on a PAL or PLA. block block

Structure of a CPLD

J. C. Huang, 2004 Digital Logic Design 86 J. C. Huang, 2004 Digital Logic Design 87

CPLD packaging and programming

A section of a CPLD PAL-like block (details not shown)

(a) CPLD in a Quad Flat Pack (QFP) package

PAL-like block
To computer

D Q

D Q

Printed
circuit board
D Q

(b) JTAG programming

J. C. Huang, 2004 Digital Logic Design 88 J. C. Huang, 2004 Digital Logic Design 89

15
 A Measure of Circuit Size Field-Programmable Gate Arrays (FPGAs)

A commonly used measure is the total An FPGA is a PLD that supports

number of two-input NAND gates that implementation of large logic circuits.
would be needed to build the circuit.
It is different from others in that it does not
It is called the number of equivalent gates. contain AND or OR planes. Instead, it
contains logic blocks as depicted in the next
slide.

J. C. Huang, 2004 Digital Logic Design 90 J. C. Huang, 2004 Digital Logic Design 91

Logic block Interconnection switches

I/O block
Typical FPGAs
FPGAs can be used to implement logic
Structure of an FPGA
circuits of more than a few hundred
I/O block
I/O block

thousand equivalent gates in size.

The most commonly used logic block is a

lookup table (LUT) as depicted in Fig. 3.36.
I/O block
Slide 3.35.1

J. C. Huang, 2004 Digital Logic Design 92 J. C. Huang, 2004 Digital Logic Design 93

x1
x2
x
0/1

0/1 0/1
A three-input LUT
0/1
0/1
f
0/1
f
0/1 0/1
0/1
A two-input lookup table
0/1
0/1
0/1
y
x3

J. C. Huang, 2004 Digital Logic Design 94 J. C. Huang, 2004 Digital Logic Design 95

16
 x3 f

A section
of a
programmed
FPGA
x1

x1 0 x2 0
0 f1 1 f2
0 0
x2 x2 x3
1 0

f1 0
1 f
1
f2
1

J. C. Huang, 2004 Digital Logic Design 96

17