COMPUTER AND MICROPROCESSOR

1. Refers to physical interface on a computer through which data are passed to and from peripherals.
a. data bus
b. port
c. internal bus
d. peripheral component interconnect (PCI)

2. Instructions and data are stored in memory in specific locations determined by:
a. address
b. control bus
c. CPU
d. program

3. This is also called as the operating system (OS) of a computer and allows the user to interface with the computer and run
several programs at the same time.
a. firmware
b. device driver software
c. system software
d. application software

4. Arrange the following in terms of computer's boot sequence:

I. Operating System
II. Power-On Self Test (POST)
III. Bootstrap Loader
IV. Basic I/O System (BIOS)

a. II, IV, III, I

b. IV, II, III, I
c. II, III, IV, I
d. I, II, IV, III

5. Any value other than 1234H in a memory address 0000:0472H indicates:

a. cold boot
b. warm boot
c. restart
d. reboot

6. Storage area in which all programs are executed?

a. Primary memory
b. Processor memory
c. Read/Write Semiconductor Memory
d. Hard disk

7. The ideal memory:

a. has high storage capacity
b. is non-volatile
c. has in-system read and write capacity
d. has all of the above characteristics

8. Which is not used for memory system performance measures?

a. Memory Bandwidth
b. Memory Access time
c. Memory Size
d. Memory Mapping
9. The next byte of memory can be accessed while the current byte is being refreshed refers to:
a. Memory cycle
b. Latency
c. Burst Mode
d. Interleaving

10. A 12-bit address line using 2-nibble data width will give a memory size of:
a. 4096 b
b. 4 kb
c. 32,768 B
d. 32,768 b

11. This type of memory stores, so called, "close at hand" information that will be used again instead of having to retrieve it
from farther away in the main memory.
a. RAM
b. Flash memory
c. Cache
d. Register

MODULE 2
12. Generally means sending data to or taking data from the device or performing some updating process.
a. polling
b. interrupt
c. handshaking
d. service

13. A set of conductive paths that serves to interconnect two or more functional components of a system or several diverse
systems.
a. port
b. bus
c. interface
d. glue logic

14. Is the only internal bus that connects directly to the microprocessor.
a. PCI bus
b. local bus
c. SCSI
d. universal serial bus

15. The original PC bus system is known as the which provide an 8-bit expansion slot allowing the transfer of one byte at a time,
and allowing 1 MB of memory to be accessed via 20 address lines.
a. ISA
b. MCA
c. EISA
d. PCI

16. Part of core logic chipset that is directly connected to the CPU, thus, controlling the high-speed channels:
a. Southbridge
b. Northbridge
c. Peripheral Control Interconnect (PCI)
d. AGP bus

17. The bandwidth or maximum theoretical throughput of the front side bus is determined by the:
a. width of data path
b. clock frequency
c. number of data cycle it performs per clock cycle
d. all of them
18. Which of the following uses control pin on microprocessor chip which is the IO/M.
a. Programmed I/O
b. Standard I/O
c. Memory-mapped I/O
d. Memory address I/O

19. When the DMA chip takes-over the system bus, what memory storage is used by the microprocessor?
a. processor's memory
b. RAM
c. ROM
d. cache

20. To prevent the devices from interfering with each other, is used to disconnect all devices except the ones that are
communicating at any given time.
a. external interrupt
b. tristate buffer
c. block transfer
d. exception

21. A type of external interrupt that can be enable/disable by an instruction?

a. maskable interrupt
b. non-maskable interrupt
c. auxiliary interrupt
d. more than one of the above

22. An output register and can be used to configure the bits in the port as input or output.
a. command register
b. status register
c. register file
d. port data register

23. is suitable only for devices that can be serviced at regular and predictable intervals and only in situations in which
there are no priority considerations.
a. polling
b. interrupt
c. exception
d. contention

24. Under Interrupt I/O, an external device can force the microcomputer system t' stop executing the current program
temporarily so that it can execute another program known as the:
a. internal interrupt
b. interrupt service routine
c. sub-routine instruction
d. call delay instruction

25. The first 4-bit microprocessor unit (MPU) invented by three Intel Engineers?
a. Intel 432
b. Intel 4004
c. Intel 8008
d. Intel 8086

26. The of microprocessor determines the instruction set and the process for executing those instructions.
a. architecture
b. specific units
c. design
d. organization

27. The common architecture behind all Intel microprocessors is known as the:
a. 8080
b. 8085
c. 8088
d. 8086

MODULE 3
28. What section of the 8086 microprocessor unit (MPU) is responsible for generating bus control signals such as those for
memory read or write and I/O read or write?
a. Bus Interface Unit (BIU)
b. Pipelining
c. Queue
d. Execution Unit (EU)

29. To use pipelining, a CPU or (MPU) must detect dependencies (dependent on the result of an instruction further down the
pipeline) and hold up an instruction's execution until the result(s) it needs are available. This holding up of instruction is called
a:
a. reset
b. interlock
c. queuing
d. wait mode

30. Which of the following is also called handshaking programmed data transfer?
a. Synchronous transfer
b. Asynchronous transfer
c. Interrupt driver transfer
d. Both (a) and (c)

31. What is used by the microprocessor to coordinate its operations and communicate with external devices?
a. address bus
b. data bus
c. control bus
d. all of them

32. A microprocessor is generally:

a. single chip SSI
b. single chip MSI
c. single chip LSI
d. any of the above

33. The computer Harvard architecture also refers to:

a. CISC Architecture
b. Von-Neumann Architecture
c. RISC Architecture
d. all of them

34. Which of the following refers to the element(s) of a microprocessor?

a. Arithmetic and Logic Unit
b. Register File
c. Control Unit
d. all of them

35. A type of register used for storing the result after most ALU operations and always the destination register of most
arithmetic and logical operations.
a. Program counter
b. Index register
c. Data register
d. Accumulator
36.A special area in read/write memory, served to hold information about the status of a micro-computer the instant an
interrupt occurs so that the microcomputer can routine processing after the interrupt has been handled.
a. stack register
b. status register
c. index register
d. control register

37. The purposes of is to increase the number of effectively individual programs that a CPU can execute simultaneously.
a. Instruction level parallelism
b. Instruction pipelining
c. Thread level parallelism
d. Multi-tasking

38. deals with multiple pieces of data in the context of one instruction.
a. Scalar processor
b. Single Instruction-Single Data
c. Vector processor
d. both a and c

39. The type of the operation that a processor performs on the contents of the address field refers to:
a. Flynn's taxonomy
b. Data parallelism
c. Branch prediction
d. Addressing mode

40. Translates source file of High-Level Language code into object file of machine language code?
a. Translator
b. Interpreter
c. Compiler
d. Assembler

41. makes the OS to think that there are two CPU's installed on the system.
a. Hyper-Transport
b. System Request Queue
c. Hyper-Threading Technology
d. Legacy System

42. A two-line, synchronous, serial bus that is widely used to connect chips together on a circuit board developed by Philips
and is used extensively in a variety of applications as a control, diagnostic and power management bus.
a. I 2C bus
b. I C 2 bus
c. Dual in-line bus (DIB)
d. PCI

43. is basically extremely small microcomputers that is entirely self-contained on a single chip which needs program
memory to store program/instructions to perform defined tasks.
a. Embedded System
b. Microprocessor
c. Microcomputer
d. Microcontroller

44. Which of the following "computer performance factor" connects path between the processor and other key components
such as memory controller hub?
a. Architecture
b. Clock speed
c. Cache
d. Frontside Bus
45. A type of "cache coherency protocol" that contains a "un-modified copy" of the location?
a. Modified
b. Exclusive
c. Shared
d. Invalid

46. Relocatable program means that program will run at any location in memory. The requirements for writing relocatable
programs is/are:
a. no references be made to physical addresses
b. no changes to the segment registers are allowed
c. no suspension of instructions fetch
d. more than one of the above

47. It prevents two sources from trying to use the bus at the same time?
a. Bus contention
b. Bus mutliplexing
c. Bus arbitration
d. Bus selection

48. Which of the following flag is not used to alter the processor operations in certain situations?
a. Interrupt flag
b. Trap flag
c. Direction flag
d. Auxiliary flag