中興電機系電子學歷試繪整 1(簡解)

Copyright by @劉明彰電子戰神
111 中興電機系
電子學
1. (10%) (a) In the Fig., use the small-signal model of the diode to find
the value of R ，so that Vo  2.8V when I L  0 ，and Vo changes by
10mV per 1mA of load current. (b) Find the value of I S of D .
【111 中興電機】

【解】：

Ans. (a) R  1.22K ，(b) I S  6.914 1012 mA

2. For the circuit as shown in the Fig., in which mode does this
npn BJT operate? If   100 , find I E ， I B ， I C ，and VC .(10%)
【111 中興電機】

【解】：
Ans. I E  0.18mA ， I C  0.178mA ， I B  0.00178mA
， VC  1.61V

3. For the circuit given in the Fig., the MOSFET is specified to

have Vt  0.7V and nCox (W / L)  20mA / V 2 . Neglect the
channel length modulation effect. (a) If I D  0.1mA ，
VS  1V ，VD  2V ，and VDD  3V ，find the values of RS and
RD .(6%) (b) If a current of 1A is used in the voltage divider,
find the values of RG1 and RG 2 . (6%) (c) Find the
transconductance g m of the MOSFET at the bias point. (3%)
【111 中興電機】
【解】：
Ans. (a) RD  10K ， RS  10K
(b) RG1  1200K ， RG 2  1800K ，(c) g m  2mA/ V

4. For the current mirror-loaded MOS differential amplifier

of the Fig. ,all the transistors work in saturation. vG1 and
vG 2 are the differential inputs. Vo is the output. The
overdrive voltages of Q1 and Q2 are the same as VOV .
(a) If Q1 and Q2 exhibit a (W / L) N mismatch of

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 中興電機系電子學歷試繪整 1(簡解)
Copyright by @劉明彰電子戰神
(W / L) N , and Q3 and Q4 also exhibit a (W / L) P mismatch of (W / L) P ，
derive the expression of the worst-case total offset voltage ( VOS ) in terms of
(W / L) N ， (W / L) N ， (W / L) P ， (W / L) P ，and VOV . (16%) (b) If the DC
components of vG1 and vG 2 are 0.6V and those of the source of Q1 and Q2 are
0V . The threshold voltages ( Vth ) of all transistors are the same as 0.4V . The Early
voltages of all transistors are the same as 10V . Find the value of the differential
voltage gain. (Note: The transistors are matched. (8%) (c) If the W / L ratios of
NMOS transistors are accurate to within  1% of normal，what is the accuracy
limitation of the W / L ratios of PMOS transistors to achieve VOS  5mV ? (6%)
【111 中興電機】
【解】：

VOV K p K N
Ans. (a) VOS  (  ) ，(b) AV  50 (V / V )
2 Kp KN
K p
(c)   1.5%
Kp

5. The simplified small-signal model of transistor is shown in the Fig.(a), and you
can use the model to solve the following problems. In Figs.(b) and (c)，we
assume all transistors are with g m  12.5mA / V and ro  16K and VB1 … VB 6
are the bias voltages.
(a) The amplifier shown in Fig.(b)employs a cascode stage and a CS stage，and a
compensation capacitor CC  10 pF is introduced in the circuit. The output has
the load capacitance, that is CL  1 pF . The transfer function of the amplifier is
s
(1  )
Vo ( s) Z
given as follows ： H ( s)   AM Determine the
Vi ( s) s s
(1  )(1  )
A B
low-frequency gain AM ，the dominant pole(  A )，the non-dominant pole(  B ),
and the zero  Z . (Note: The poles and zero are in rad/s.) (20%)
(b) Fig. (c) shows the amplifier with two feedback resistors R1  2K and
V
R2  2K . Determine the voltage gain o and the output resistance Rof . (15%)
Vi
【111 中興電機】

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 中興電機系電子學歷試繪整 1(簡解)
Copyright by @劉明彰電子戰神

【解】：
Ans. (a) AM  2 106 (V / V ) ， A  625 rad / s ， B  1.25 1010 rad / s
Vo
(b)  1.99 (V / V ) ， Rof  0.0116K
Vi

110 中興電機系
電子學

1. (10%) Consider a half-wave peak rectifier fed by a 60-Hz sinusoid having a peak
value V p  110V as shown in the Fig. Assume the
diode turn-on voltage is 0.5V and the load resistance
R  5K . Please find the value of the capacitance C
that will result in a peak-to-peak ripple of 4.5V . Also
calculate the fraction of the cycle during which the diode is turn-on, and the average
value of the diode current.【110 中興電機】
【解】：
Ans. C  8.11 105 ( F ) ，導通時間所佔比例為 4.57%
， 二極體平均電流太難，放棄。

2. (15%) Please determine the current ( I Q ) and voltages

( VGS 1，VGS 2，VGS 3，VGS 4，VDS 1，VDS 2 ) in a constant current
source with the supply voltages V   5V ， V   5V ，
and RD  20K as depicted in the Fig. The transistor
1 W
parameters are： nCox ( )1  0.2mA / V 2
2 L
1 W 1 W 1 W
， nCox ( ) 2  nCox ( )3  nCox ( ) 4  0.1mA / V 2 ，
2 L 2 L 2 L
threshold voltages are Vt  1V .【110 中興電機】
3
 中興電機系電子學歷試繪整 1(簡解)
Copyright by @劉明彰電子戰神
【解】：

Ans. VGS 4  VGS 3  2.5V ， I ref  0.225mA 且 VGS 2  2.5V

， VGS1  2.06V ， VDS1  2.56V ， VDS 2  2.94V

3. (10%) Consider an n-type silicon for which the dopant concentration

N D  1018 / cm3 . (a) Find the electron concentration at T  350K . (b) Find the hole
concentration at T  350K . [Note：the intrinsic carrier concentration ni for
silicon at T  350K is 4.15 1011 / cm3 .]【110 中興電機】
【解】：
Ans. (a) n  1018 / cm3 ，(b) p  1.72 105 / cm3

W
4. (15%) Consider an NMOS transistor having nCox ( )  20 mA / V 2 . Let the
L
transistor to be biased at VOV  0.1V . (a) For operation in saturation，what dc bias
current I D results? (b) If a 0.01V signal is superimposed on VGS ，find the
corresponding increment in drain current. (c) Calculate g m of the NMOS at this bias
point..【110 中興電機】
【解】：
Ans. (a) I D  0.1mA ，(b) I D  I D 'I D  0.021mA
，(c) g m  2.1mA/ V

5. (25%) The inverting amplifier shown in the following Fig has RS  2K ，
RL  5K ， and RF  8K . The op-amp parameters are Ri  2M and
Ro  75 ，and the open-loop voltage gain is  g  210 . Determine the input
5

Vo
resistance Rin ，the output resistance Rout ，and the voltage gain AV  .【110
VS
中興電機】

【解】：

Ans. Rin  4.1105 K ， Rout  1.88 106 K

Vo V
  4.0
VS V

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 中興電機系電子學歷試繪整 1(簡解)
Copyright by @劉明彰電子戰神

6. (25%) The Fig. shows a folded cascade amplifier.

VG1 and VG 2 are the DC bias voltages to make the
two transistors working in saturation. Vi and Vo
are the small signal input and output voltages,
respectively. For both transistors ( Q1 and Q2 )，
the Early-voltage is VA  8V ， the over-drive
voltage is VOV  0.2V ，and the threshold voltage is
Vt  0.5V . The output resistance of the 1.2mA current source is Ro3   ，and
that of the 0.4mA current source is Ro 4  Ro 2 . (a) What is the value of VG1 ? What
is the lower bound value of VG 2 to make Q2 in saturation. (b) Find g m
(transconductance) and ro (output resistance) of Q1 and Q2 . (c) What is the
output resistance ( Ro 2 ) looking into the drain of Q2 . (d) Find the voltage gain
V
AV  o . (e)If Cgs1  Cgs2  0.5 pF ， Cgd1  Cgd 2  0.1 pF ，and the DC bias and the
Vi
input signal voltage source have 0 source resistance，estimate the value of 3-dB
frequency using the method of open-circuit time constant.【110 中興電機】
【解】：
Ans. (a) VG1  0.7V ，VG 2 下限由 Q2 在歐飽交接處決定，本題缺少，故依潛規則，
令 Vo ( dc)  0V ； VG 2(min)  0  Vt 2   0.5V
(b) g m1  8mS 、 ro1  10K ， g m 2  4mS 、 ro 2  20K
V
(c) Ro 2  800K ，(d) AV   3200 ( )
V
(e) D1 節點極點  p1  33.1 10 (rad / s) ， D2 節點極點 p 2  2.5  10 (rad / s)
7 7

  H   p1 //  p 2  2.324  107 (rad / s)

H
 fH   3.70 106 ( Hz)
2

109 中興電機系
電子學

1. (16%) For a Zerner diode regulator circuit as shown in the Fig.(a). Assume the
Zerner diode can be modeled by two segments as shown in Fig.(b). If the input
voltage Vi varies from 8 ~ 12V and the RL  2.5K , please plot the graphs of
VL as a function of Vi (ie., VL vs Vi relationship curve) as the Ri  0.1K

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 中興電機系電子學歷試繪整 1(簡解)
Copyright by @劉明彰電子戰神
and Ri  0.5K ，respectively.【109 中興電機】

【解】：

Ans. (a) Ri  0.1K ：VTC 如右圖：

(a) Ri  0.1K ：VTC 如右圖：

2. (9%) Consider the electric circuit as shown in the Fig. At VCE  1V ， VBE is
adjusted to yield a collector current I C of 4.5mA . Then，while VBE is kept
constant， VCE is raised to 10V . Find the new value of I C . And what is the main
reason to cause this effect? Assume the Early voltage V A of this transistor is 50V .
【109 中興電機】

【解】：
Ans. I C  5.294mA ；此為 Early-effect ，即增加 VCE ，導致空乏區擴大，使有效
基級寬度縮減，導致 I C 增加，又稱為 Base-width modulation effect.

4. (25%) Neglecting channel-length modulation effect，high frequency equivalent

circuit of CD-CG amplifier is shown in the Fig. The parameters for each transistor are
g m ， C gs ，and C gd . Consider the circuit for the case： I  100A and VOV  0.25V
(overdrive voltage) for operating transistors ， Rsig  200K ， RD  100K ，
Vo
Cgs  2 pF ，Cgd  1 pF and CL  3 pF . Find the midband gain ( AM  )，the two
VS
high-frequency poles ( f p1 and f p 2 ) in Hz，and an estimate of the 3-dB pole

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 中興電機系電子學歷試繪整 1(簡解)
Copyright by @劉明彰電子戰神
2I D
frequency f H in Hz. (Note： g m  for an NMOS transistor).【109 中興電機】
VOV

【解】：
V
Ans. AM  20 ( ) ； f p1  3.98 105 ( Hz) ， f p 2  3.98 105 ( Hz)
V
2 2
f H  ( f p1  f p 2 ) 1/ 2  2.814 105 ( Hz)

3. (25%) This Fig. shows a differential cascade amplifier with an active load formed
by a modified Wilson MOS current mirror. The parameters of all MOS transistors are
given in the table below. VB1 and VB 3 are the
DC bias voltages to make all transistors working in
saturation. vid is a small signal. The relation
between the Early voltage and channel length is
VA  VA 'L . Vt is the threshold voltage. Vo and
vo are the DC voltage and small-signal output
signal，respectively.
(a) Find the values of the small-signal parameters
g m (transconductance) and ro (output resistance) of every transistor. (b) What
are the over-drive voltages ( VOV ) of Q6 and Q8 ? What is the maximum possible
value of ( Vo  vo )? (Hint：All transistors are always in saturation.) (c) Find the value of
v
differential voltage gain Ad  o .【109 中興電機】
vid

【解】：
Ans. (a) g m1, 2  1mA/ V ， ro1, 2  40K ； g m3, 4  0.5 mA/ V ， ro3, 4  160K ；
g m5,5  1mA/ V ， ro5,6  20K ； g m7,8  0.5mA/ V ， ro 7,8  80K
(b) VOV 6   0.4V ， VOV 8   0.8V ， (VO  vo )max  2.3V
(c) Ro  1070 ， GmS  1 ； Ad  1070 (V / V )

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 中興電機系電子學歷試繪整 1(簡解)
Copyright by @劉明彰電子戰神
5. (25%) Please calculate each diodes ( D1 ， D2 ， D3 ) currents I D1 ， I D 2 ，and I D 3
the node voltages V A and VB in the Fig. Assume each diode has on-voltage of
0.7V .【109 中興電機】

【解】：

Ans. I D1  1.43mA ， VA   2.15V ，

VB   0.7V ， I D 3  0.86mA ， I D 2  0mA

108 中興電機所

1. (25%) Please find the drain current ( I D ) and source drain voltage ( VSD ) in the
following circuits of Fig. (a),(b),(c). Assume PMOS device parameters ：
k ' p   pCox  100A / V 2 ，   0 ， Vtp  0.4V ，and W / L  20A /1A .
【108 中興電機】

【解】：
Ans. (a) I D  1.74mA ， VD  0.87V ；VSD  0.93V
(b) I D  0.615mA ， VD  0.615V ， VSD  1.18V
(c) I D  0.615mA ， VSD  1.18V

2. (25%) (a)The NMOS transistor in the source-follower circuit of Fig. (a) has
g m  5mA / V . Neglect ro . Find the output resistance and the open circuit
voltage gain. (b) The NMOS transistor in the common-gate circuit of Fig. (b) has
g m  5mA / V . Neglect ro . Find the input resistance and the voltage gain. (c)If
the output of the source-follower in (a) is connected to the input of the

8
 中興電機系電子學歷試繪整 1(簡解)
Copyright by @劉明彰電子戰神
common-gate amplifier in (b), use the result of (a) and (b) to obtain the overall
voltage gain vo / vi . 【108 中興電機】

【解】：
Vo1
Ans. (a)  0.962(V / V ) ； RO1  0.192K
Vi
V
(b) Ri 2  0.192K ； o  5(V / V )
Vi 2
V
(c) o  2.4(V / V )
Vi

3. (25%) The Fig. shows a differential amplifier with matched Q3 and Q4 operated
in the triode region and acted as the source resistance rDS 3 and rDS 4 . Assume that
Q1 and Q2 are matched and operate in saturation at an overdrive voltage
I
VOV  0.2V that corresponds to a drain bias current of  0.2mA and the
2
resistance of each current source RSS is 400K . The threshold of all transistors
are. The W/L ratios of Q1 and Q2 are (W / L) N , and those of Q3 and Q4 are
(W / L) N
(W / L) S , where  3.
(W / L) S
(a) When vG1  vG 2  0 ，what DC voltage appear at the source of Q1 and Q2 ?
What current flow through Q3 and Q4 ? At what overdrive voltages are Q3 and
Q4 operating? Find the transconductance g m of Q1 and the resistance rDS 3 .
(b) When vG1  vG 2  vid , when vid is a small signal and RD1  RD 2  50K , find
the differential voltage Ad  vo / vid . (Assume ro   ).
(c) Let RD1  RD  (RD / 2) , RD 2  RD  (RD / 2)，with RD  50K，RD / RD  2%
and vG1  vG 2  vicm ， what is the
common-mode gain Acm  vo / vicm ? What
is the CMRR?
(d) For the same parameters in (c)，what is
the input offset voltage ( VOS )? vG1 is
higher or lower than vG 2 to compensate
RD1 and RD 2 mismatch?【108 中興電機】

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 中興電機系電子學歷試繪整 1(簡解)
Copyright by @劉明彰電子戰神
【解】：
Ans. (a) VS1  VS 2   0.8V ， VOV 3, 4  0.2V
， g m1, 2  2mA/ V ， rDS 3, 4  1.5K
(b) Ad  25(V / V ) (c) Ad  2.5 10 3 ，(d) VOS  8mV
因 RD1 較大，故須減少左側的電流以達平衡，故 VG1 要小於 VG 2 以消除偏差

4. (25%)Recharged batteries must be charged by a constant current to avoid

damage. The battery charger must therefore generate a constant current from a
golden reference， Vref . As shown in the Fig., we can insert a small resistance r in
the output path, apply the voltage across r to an amplifier A1 ，and subtract the
output of A1 from Vref to another
amplifier A2 .
The parameters for the transistor M 1
are the transconductance
gm  1 /( 25m) and the output
resistance ro  1K ， the op amplifier
A1 and A2 have the same gain of
100V / V ，the reference voltage is Vref  1V ，and the resistance of the small resistor
is r  5 . Assume the battery loading Z L  ro ，calculate the output current ( I out )
and impedance ( Rout ) of the circuit.【108 中興電機】
【解】：本題怪怪的，求 I out 時應該是直流分析，但缺少 M 1 的 K 值，而且又何須
給多餘的 Z L  ro ，勉力一試！
1
g m  1 /( 25m)  6
 4 10 4 mS
25 10 K
<1> I out 分析： VGS  (1  I out  r  A1 )  A2  (1  I out  0.5) 100
且 I out  K (VGS  Vt ) ；由上兩式可求出但缺少 Vt
2

<2> Rout 分析：

Vt  [ I t  g m  I t  r 10 4 ] 1  I t  r
 Rout  Vt / It  2 106 K

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 中興電機系電子學歷試繪整 1(簡解)
Copyright by @劉明彰電子戰神
107 中興電機系
電子學
1. (15%)The following non-inverting amplifier incorporating an operational amplifier
with feedback is designed for a nominal gain of 10.
(1) What feedback topology is employed ? (A)series-series，(B)series-shunt，(C)
shunt-series，(D) shunt-shunt，(e) none
(2) Assuming the operational amplifier is ideal, determine the value of R1 . (A)0.1,
(B) 1.1, (C) 9, (D) 10, (E) none K
(3) Determine the minimum value of A1 for a gain error of 1%
(A) 10, (B) 100, (C) 1000, (D) 1000, (E) none
(4) The operational amplifier has the frequency response：
10 4
A1 ( s)  ，and its output resistance is very small.
s
1
2 1000
Calculate the output resistance of the feedback circuit， Ro . (A) 10, (B) 100, (C) 1000,
(D) 10000, (E) none 
(5) According to (4), calculate the 3-dB frequency of the feedback amplifier circuit.
(A) 1, (B) 10, (C) 100, (D) 1000, (E) none KHz 【107 中興電機】
【解】：
1
(1) (B) ，(2) (C) ，(3)    0.1  A1  990
1 9
0
(4) Rof   0 ，選(E) ，(5) f3dB  103  (1  104  0.1)  106 Hz ，選(D)
1  A1  

2. (15%) A single pole amplifier has the gain of 3103 at 100KHz and 9103 at
1KHz， respectively. Please find the corner frequency (3dB frequency， f 3dB ) and
the unit gain frequency， f t . 【107 中興電機】
【解】：
Ans. f3dB  35.34KHz ， ft  318KHz

＊＊3. (20%) The biased cascode current for the differential amplifier is designed
with I SS  200A and the power supply is VDD  3V . For all transistors, the
channel-length modulation effect and body effect are ignored and their overdrive
voltage ( VOV  VGS  VTH ) is set by 0.2V， where
VTH  0.6V .
(1) (5%) For the current mirror， calculate the
value of RB .
(2) (5%) Calculate the value of VB ，then the

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 中興電機系電子學歷試繪整 1(簡解)
Copyright by @劉明彰電子戰神
cascode current source consumes minimum headroom.
(3) (10%) Assuming R1  R2  400 ，calculate the small-signal differential voltage
( AV  (Vo1  Vo 2 ) /(Vi1  Vi 2 ) )in the differential pair. 【107 中興電機】
【解】：
Vo
Ans. (1) RB  22K ，(2) VB  1V ，(3)  0.6V / V
Vi

4. (20%)Please find the small-signal gain Vo / Vi in the following Fig. The MOS
transistors M1 and M2 have transconductance g m1 and g m 2 , respectively. The
output resistance ro is neglected in Fig.(a) and Fig.(b), and the output resistance
ro1 and ro 2 must be considered in Fig.(c) (Note: You need carefully to watch the
arrow direction of the transistor to present NMOS or PMOS) 【107 中興電機】

【解】：
g m1 g g R
Ans. (a) AV   ，(b) AV   m1 m 2 D
gm2 g m1  g m 2
1
(c) AV   g m 2  (ro1 // ro 2 // )
g m1

5. (15%) Under the low and medium frequencies, what is the working purpose of the
circuit as shown in the Fig. If the input waveform is
Vi  2 sin  t V , please plot the V-t waveforms of
Vi , VD1 and Vo in the same figure. Assume D1
and D2 are ideal diodes. 【107 中興電機】
【解】：
Ans. VD1  2 sin( t )  2 ， Vo  4V

6. (15%) Under (1) RS  0 ，and (2) RS  5K ，please

calculate the drain-to-source current ( I DSQ ) and drain-to-source
voltage ( VDSQ ) of a common-source electric circuit with a
n-channel enhancement-mode MOSFET as shown in the Fig. The
device's parameters are Vt  1.0V ， kn 'W / L  1.0mA / V 2 ， and

12
 中興電機系電子學歷試繪整 1(簡解)
Copyright by @劉明彰電子戰神
  0. 【107 中興電機】
【解】：
Ans. (1) RS  0 ： VDS  0.515V ， I DS  0.9mA
(2) RS  0 ： VGS  1.72V ， I D  0.26mA ， VDS  2.4V

106 中興電機系
電子學

1. The Figure depicts an abrupt pn junction under open-circuit conditions. The

N A and N D are the doping concentrations of the p side and n side of the
junction, respectively. The charge is
denoted by q ，the dielectric constant is
 in the semiconductor, the junction
S

area is A and the thermal voltage is VT .

The hole and free electrons have diffusion
constant D p and Dn ， mobility
 n and  p ，and diffusion length L p ，
Ln ，respectively. (a) (6%) If a reverse voltage VR is applied in the pn junction,
please find the incremental depletion capacitor C j . (b) (5%) If a forward bias
current I F is applied in the pn junction，please find the incremental diffusion
capacitor Cd . 【106 中興電機所】
【解】：半導體
q S N AND
Ans. (a) C j  A
N N
2(VT ln A 2 D  VR )( N A  N D )
ni

d I  D L N   p D p Ln N A
(b) Cd  (Qn  Qp )  F  ( n n p D )
dVD VT D p Ln N A  Dn L p N D

2. An emitter follower of BJT transistor implements the buffer amplifier as shown

in the Figure. The transistor   99 is used in this design. The thermal voltage is
VT  25mV at a pn junction.
(a) (3%) To guarantee the operation in active mode, find the minimum value of the
13
 中興電機系電子學歷試繪整 1(簡解)
Copyright by @劉明彰電子戰神
transistor，  min value.
(b) (3%) Find the maximum allowed VS value if the small-signal base-emitter
voltage V is to be limited to 1.25mV in order to obtain reasonably linear
operation.
(c) (6%) Assume the input voltage VS  100mV ， determine VO value when the
load resistance is changed to RL  2.5K and RL  0.5K 【106 中興電機所】

【解】：

Ans. (a) min  80 (b) VS  500mV

(c ) RL  2.5K ： VO  83.33mV ， RL  0.5K ： VO  50mV

3. (12%) The Fig. shows the circuit in this program. Both

NMOS and PMOS are matched ，
kn ' (W / L)n  k p ' (W / L) p  2mA / V 2
and Vt  1V .
Assume   0 for both devices ，please find the drain
currents iDN and iDP ，as well as Vo ，for Vi  0V ，
 2.5V ，and  2.5V . 【106 中興電機所】
【解】：
Ans.<1> Vi  0V ： Vo  0V ， iDN  iDp  2.25mA
<2> Vi  2.5V ： Vo   2.47V ， iDN  0.247mA
<3> Vi  2.5V ： iDN  0 ， Vo  2.47V ， iDP  0.247mA

4. The differential amplifier as shown in the Fig. has a bias current I  0.2mA .
Q1, 2 are identical with (W / L) N  16 and VA  40V . Q3, 4 are identical with
(W / L) P  12.5 and VA  20V . VCM is the dc voltage at the two differential
inputs. ( nCox  2 pCox  20A / V 2 ， Vt  0.5V ， VDD  5V
(a) (8%) Determine the dc voltages of VG and
VS . (b)(6%) Find the small-signal parameters
of transconductance ( g m ) and output
resistance ( ro ) of Q1 and Q3 . (c) (4%)

14
 中興電機系電子學歷試繪整 1(簡解)
Copyright by @劉明彰電子戰神
Determine the differential voltage gain Vo / Vid . (d) (6%) If the current source
requires a minimum voltage of 0.5V，find the input common-mode range. (e) (6%)
If (W / L) N of Q1 and Q2 are mismatched by 4%, what is the input offset
voltage ? 【106 中興電機系】
【解】：

Ans. (a) VG  3.235V ， VS  0.71V

(b) g m1, 2  0.253mA/ V ， g m3, 4  0.158mA/ V
ro1, 2  400K ， ro3, 4  200K
(c) Ad  gm1  (ro 2 // ro 4 )  33.73V / V
(d) 1.79V  VCM  3.735V ，(e) VOS  15.8 10 3V

5. An op amp connected in the non-inverting configuration is shown in the

following. The op amp has an open-circuit voltage gain AV ，a differential input
resistance Rid ，and an output resistance ro .
(a) (5%) Neglecting the effect of Rid and ro ，the circuit of Figure (a) employing
the op amp is designed for a nominal gain of 10. Determine the value of R1 / R2 .
(b) (10%) According to (a), determine the minimum value of AV for a gain error of
0.1 %.
(c) (20%) In Figure (b)， the circuit is given with AV  103 ， Rid  12K ，
ro  200K ， R3  8K and R4  1M . Calculate the closed-loop gain Vo / VS ，
the input resistance Rin ，and the output resistance Rout . 【106 中興電機所】

【解】：
R 1
Ans. (a) R2  9 ，(b) AV  9990
1

Vo
(c) Rin  99.4K ， Rout  33.5K ，  100.7(V / V )
VS

15
 中興電機系電子學歷試繪整 1(簡解)
Copyright by @劉明彰電子戰神
105 中興電機系
1. Consider the electric circuit as shown in the Fig.
Determine the small-signal voltage gain,
Av  | VO / VS | under (a)   0 ，(b)   0.05 V 1 ，
respectively. The other transistor’s parameters are
VTN  1V and k n  2 mA/V 2 . (15%)【105 中興電機
所】
【解】：

Vo V
Ans. ro     12
Vs V
Vo V
ro  35.6K   9.8
Vs V

2. Please plot the transfer curve, i.e. Vi （x-axis）

vs Vo（y-axis）of the electric circuit as shown in the
Fig. Assume D1 and D2 are ideal diode, and
VR1  1V ， VR 2  3V . If the input waveform is
Vi  5 sin(t )V ，please plot the output waveform,
Vo . (10%) 【105 中興電機所】
【解】
：
Ans.  Vo  Vi  轉換圖與 Vo 波形圖如下：

3. The Fig. shows a differential pair with the potentiometer setting, represented by
the fraction x of a 4K resistor connected in series
with RD1 , that is required for nulling the output
voltage. VDD  1.2V ，and VA (Early voltage)  10V .
(a)Assume that Q1 and Q2 are identical,
k  k W / L  6.4 mA/V （where k    Cox ，  is the
2

mobility and Cox is the gate capacitance per unit

area.）, and x  0.5，what is the DC voltage at the drain
of Q1 or Q2 ? What are the transconductance g m and output resistance ro of
16
 中興電機系電子學歷試繪整 1(簡解)
Copyright by @劉明彰電子戰神
Q1 or Q2 ? (8%)
(b) Use the results in (a) to find the differential voltage gain Vod / Vid ? (4%)
(c) If k of Q1 is 5% higher than that of Q2 ，find the fraction x for nulling the
output voltage. (5%)
(d) If Vt of Q1 is 0.01V higher than Vt of Q2 ，find the fraction x for nulling the
output voltage. (8%) (Hint：The value of Vt is not required. Use the ratio of Vt
and overdrive voltage.) 【105 中興電機所】
【解】：
Ans. (a) VD1  VD 2  0.6 V ， g m  0.8mA/ V ， ro  200K
Vo V
(b)  9.6 ，(c) x  0.425 ，(d) x  0.76
Vi V

4. A feedback amplifier including a three-stage amplifier H (s) and a feedback

network is shown in the Fig.

A1 has an 82K differential input resistance, a 20-V/V open-circuit differential

voltage gain, and a 3.2K output resistance. A2 has a 5K input
resistance，a 20-mA/V short-circuit transconductance，and a 20K output
resistance. For high-frequency response, a 20 pF compensation capacitance CC
is connected between nodes X and Y (in the negative path of A2 ). A3 has a
20K input resistance, unity open-circuit voltage gain, and a 1K output
resistance. The feedback amplifier feeds a 1K load resistance RL and is fed by
a signal source with a 9 K resistance RS . The feedback network has
R1  10K and R2  90K .
(a) Show that the feedback is negative. (2%)
(b) Sketch the small-signal equivalent circuit of the closed-loop circuit, including
A1 ， A2 and A3 . (4%)
(c) Find the midband closed-loop gain Af  Vo / VS . (4%)
(d) Find the feedback amplifier’s input resistance Ri . (3%)
(e) Find the feedback amplifier’s output resistance Ro . (3%)
(f) If for some reason A1 drops to half its nominal value of gain，what is the
percentage change to A f ? (3%)

17
 中興電機系電子學歷試繪整 1(簡解)
Copyright by @劉明彰電子戰神
(g) For high-frequency response, find the dominant pole of H (s) and determine
the upper-3-dB frequency of the closed-loop circuit (in Hz). (6%)【105 中興電機所】
【解】：

(a)考慮封閉迴路

設 Vo 電壓因雜訊而增加，將透過 R1  R2 分壓使 K 電壓增加，接著透過 A1 使

X 電壓增加，再透過 A2 使 Y 電壓下降，再透過 A3 使 Vo 電壓下降，故此封閉迴
路為負回授電路。
V
Af  9.9 ， Rin  10 4 K ， Rout  4.95
V
 Af Af  Af
∴    1%
Af Af
(g) f p  2.03 10 4 Hz ， f p  2.05 106 Hz

5. The Fig. shows a two-stage CMOS op-amp. Assume VDD  1.4V ，

 VSS  1.2V ，all transistors are operated at overdrive voltage of 0.2V magnitude,
Vtn  | Vtp |  0.3V ，all g m  1mA / V ，all ro  10K ， I Q11  2mA ， CL  4 pF .

(a) Find its input common-mode range. (6%)

(b) Find the range allowed for output， Vo . (6%)
(c) Find slew rate. (6%)
(d) Find the output resistance of the CG transistor Q4 ， Ro 4 . (7%)
Hint: You must consider the resistance in the source lead of Q4 .【105 中興電機所】
【解】：

18
 中興電機系電子學歷試繪整 1(簡解)
Copyright by @劉明彰電子戰神
Ans. (a) 輸入共模範圍： ViCM (max)  1.5V ，ViCM (min)  0.5V
(b)輸出擺幅分析：  0.5V  V  1V
I I I
(c) <1> I B  I SS ： SR  SS ， <2> SS  I B  I SS ： SR  B 但本題 I B 資料
CL 2 CL
I
不清，僅能採取情形<1>： SR  B = 5 108V/ sec
CL
(d) Ro 4   50 K

104 中興電機系 電子學

1. Consider the MOSFET amplifier circuit as shown in the Figure. The parameters of
the transistor are VTN  1V , and k 'n W / L  1mA/V 2 . Bias conditions are
VGS  3V ， VDD  5V ，and RD  1.2KΩ .
(a) Find the dc quantities I D and VD . (4%)
(b) Calculate the value of g m at the bias point. (2%)
(c) Calculate the value of voltage gain， AV . (4%)
(d) If the MOSFET has   0.1V 1 ，find ro at the bias point
and calculate the voltage gain， AV . (5%) 【104 中興電機所】
【解】：
Ans. (a) I D  2mA ， VD  2.6V ，(b) g m  2mS
V V
(c) AV   2.4 ，(d) ro  5K ， AV   1.935
V V

2. The Figure shows a folded-cascode CMOS amplifier utilizing a simple current

source Q2 ， supplying a current 2 I ， and a
cascade current-source ( Q4，and Q5 ) supplying a
current I . Assume that all transistors are biased
at saturation and have equal k  k 'W / L and
VA (Early voltage).
(a) Find the transconductance and the output
resistance for Q1 ， Q2 ，and Q5 in terms of k
and VA and I . (5%)
(b) If the transconductance and the output
resistance of Q1 are expressed as ro and g m , what are those of Q2 ， Q3 ， Q4 ，
Q5 in terms of ro and g m ? (4%)
(c) If ro  1 / g m ，give approximate expressions for the resistances Ro1 ， Ro 2 ，
Ro 3 ， Ro 4 ， Ro 5 and Rin 3 in the Figure. (8%)
(d) Find the amplifier output resistance Ro . (3%)
(e) Find the overall voltage gain vo / vi . (5%)【104 中興電機所】

19
 中興電機系電子學歷試繪整 1(簡解)
Copyright by @劉明彰電子戰神
【解】：
VA V
Ans. (a) g m1,3, 4,5  2 Ik ， g m 2  2 Ik ， ro1,3, 4,5  ， ro 2  A
I 2I
r
(b) g m1,3, 4,5  g m , ro1,3, 4,5  ro ， g m 2  2 g m , ro 2  o
2
r
(c) Ro1  ro1  ro , Ro 2  ro 2  o
2
Ro5  ro5  ro ， Ro 4  Ro5  4  g m ro ， Rin3  ro
2

1 1
(d) Ro  Ro3 // Ro 4  g m ro2 ，(e) AV   g m2 ro2
4 4

3. Determine the resistance of R in the electric circuit shown in

the Fig. to provide an output voltage， Vo of 2.4V . Assume that all
of the diodes are the same and have 0.7V drop at 1mA . (The
temperature is 20 C ， so the thermal voltage VT  25mV 、and
  1.2 ) (10%)【104 中興電機所】
【解】：
Ans. R  0.2K

4. In the feedback path of the common-emitter stage we place a compensating

capacitor C f between nodes B and C. The Figure shows the simplified equivalent
circuit.
(a) In the absence of the compensating capacitor C f ，find the two poles-one at the
input ( p1 ) and one at the output ( p 2 ) . (6%)
(b) With C f present, calculate the transfer function Vo / I i . (7%)
(c) Using (b), find the poles，  p1 and  p 2 ，where  p1 and  p 2 are the new
frequencies of the two poles. Normally one of the poles will be dominant;
p1  p 2 . (6%)
(d) According to (c), explain “Miller compensation” and “pole splitting” for the
frequency compensation. (6%)【104 中興電機所】

【解】：
20
 中興電機系電子學歷試繪整 1(簡解)
Copyright by @劉明彰電子戰神
1 1
Ans. (a)  p1  ,  p2 
R1C1 R2C2
Vo ( sC f  g m ) R1R2
(b) 
Ii 1  sC f g m R1R2  s 2 [C1C2  C f (C1  C2 )]R1R2
1 g mC f
(c) p1  ，  p 2 
g m R1R2C f C1C2  C f (C1  C2 )
(d)由上式可知 p1   p1 ， p 2   p 2 ，稱 pole-splitting。

5. The Figure shows a two-stage

CMOS op-amp. Assume
VDD  1.2V ，  VSS  1.0V ， all
overdrive voltages of 0.2V
magnitude, Vtn  | Vtp |  0.3V ，
I1  0.8mA ， I 2  1.6mA ，
CC  4 pF .
(a)Find its input common-mode
range. (6%)
(b)Find the range allowed for
output， vO . (6%)
(c) Find slew rate. (6%)
(d)Describe when slewing phenomenon happens. (7%) 【104 中興電機所】
【解】：
Ans. (a) ViCM (max)  0.5V ， ViCM (min)  0.8V
(b) Vo (max)  1V ， Vo(min)  0.8V
V dVo
(c) SR  2108 ，(d)若  SR 值，將導致 Vo 波形失真。
s dt

103 中興電機系

1. A simple current mirror circuit with BJT devices is shown in the Figure. Please
explain the requirements and operating principles of this
current mirror circuit. If VCC1  10V , VCC 2  15V ，
R  20K ，load  1K ，the parameters of BJT device are
VBE ( act.)  0.7V ， VBE ( sat.)  0.8V ， VCE( sat.)  0.2V ，and

21
 中興電機系電子學歷試繪整 1(簡解)
Copyright by @劉明彰電子戰神
 F  200 , VT  25mV ，please calculate the collector currents, I C1 and I C 2 ，
individually, under (a) VA   and (b) VA  125V . ( VA is an Early voltage of the BJT
device.) (25%)【103 中興電機所】
【解】：
Ans. (a)本結構包含偏壓明確的 Q1 產生參考電流，再經由 Q2 (與 Q1 偏壓相同)的
集極產生一相依電流供給輸出。
(b) I C  0.460 mA ， I C1  0.460 mA ， I C 2  0.54 mA

2. Three MOS-transistor amplifiers are shown in the following. For simplicity, we

assume the transconductance of each transistor is g m and neglect the
channel-length modulation (ro  ) .
(a)In Fig.(a), find the voltage gain Vo / Vs . (5%)
(b)In Fig.(b), find the voltage gain Vo / Vs . (5%)
(c)Fig.(c) shows a feedback amplifier. Show that the feedback is negative. (5%)
(d)In Fig.(c)，find the input resistance Rin ，the output resistance Rout ，and the
voltage gain Vo / Vs . (10%) 【103 中興電機所】

【解】：
Vo V  g m RD
Ans. (a)   g m RD ，(b) o  ，(c)略。
Vs VS 1  g m RS
RD 2 //( RS1  RS 2 ) Vo A
(d) Rin   ， Rout  ， 
1 A  Vs 1  A  

3. For the CMOS class AB output stage of the Figure，

consider the case of matched Q1 and Q2 ， and
matched QN and QP . If I Q  1mA and
I BIAS  0.1mA ，find (W / L) for each of Q1 ， Q2 ，
QN ，and QP so that in the quiescent state each
transistor operates at an overdrive voltage of 0.2 V. Let
VDD  VSS  2.5V ，k n  250 μA/V 2，k p  100 μA/V 2，
and Vtn  Vtp  0.6V . Also find VGG . (25%) 【103 中興電機所】
【解】：
22
 中興電機系電子學歷試繪整 1(簡解)
Copyright by @劉明彰電子戰神

Ans. (a) 
W W  W  W 
  20 ，    50 ，    200 ，    500
 L 1  L 2  L N  L P
(b) VGG  1.6V

4. If Q3 is operated in the triode region as shown in the Figure，it is equivalent to

the resistance Rs connected between the sources of Q1 and Q2 . The value of
Rs is determined by the voltage VC at the gate of Q3 . All the three transistors
have the same W / L and Vt . (a)With vG1  vG 2  0V ，and assuming that Q1 and
Q2 are operating in saturation, what DC
voltages appear at the sources of Q1 and
Q2 ? Express these in terms of the overdrive
voltage VOV ant Vt . (Note: Q1 and Q2 are
identical ， so VOV  VVO1  VOV 2 and
Vt  Vt1  Vt 2 .) (3%)
(b)For the situation in (a), what current flows in Q3 ? What overdrive voltage VOV 3
is Q3 operating at， in terms of VC , VOV , and Vt ? (6%)
(c) Consider the case vG1  vid / 2 and vG 2  vid / 2 ，where vid is a small
signal. Q3 operates in triode region with a small vDS . What resistance rDS does
it have, expressed in terms of VOV 3 , VOV and g m ? ( g m  g m1  g m 2 .) (5%)
1
(d)Find VOV 3 and hence VC that results in Rs  . (6%) (e)For the situation
2 gm
in (d), what is the differential gain vod / vid , expressed in terms of RD and g m ?
(5%)【103 中興電機所】
【解】：
Ans. (a) VS   (VOV  Vt )
VOV
(b) I 3  0 ， VOV 3  VC  VOV ，(c) rds  ，(d) VC  VOV
g mVOV 3
Vo 4
(e)  g m RD
Vi 5

102 中興電機系

23
 中興電機系電子學歷試繪整 1(簡解)
Copyright by @劉明彰電子戰神

1. Consider the electric circuit shown in the Fig.

Determine the DC operating points， I CQ ， VCEQ and
small-signal voltage gain， Av . Assume (a) RE  0 ，
(b) RE  2K ， respectively. The npn transistor’s
parameters are VBE ( on)  0.7V ，  F   o  200 ，
VT  25mV (thermal voltage), base resistance
rb  100 ，and VA   . (18%)【102 中興電機所】
【解】：
Ans. (a) I CQ  8 mA , VCEQ  2 V ， Av    150.7(V / V )
V
(b) RE  2K ： I CQ  2.93 mA , VCEQ  1.2 V ， Av    0.49
V

2. Analyze the circuit shown in the Fig. to determine the

voltages at all nodes， VD ，VS ，VG and the currents through
all branches ， I D ， I S ， I G . Let VTN  1V and
 N  10 mA/V 2 . Neglect the channel-length modulation effect
(i.e., assume   0 ). (7%)【102 中興電機所】
【解】：
Ans. VG  5 V ， I G  0 ， I DS  0.724 mA
VS  3.62 V ， VD  6.38 V

3. A class B output stage usually has a higher power-conversion efficiency than a

class A output stage does. (you can use current sources, voltage sources, BJT or
MOS transisters and other passive components in questions (a) and (b).)
(a) Please draw a class A output stage circuit schematic. (10%)
(b) Please draw a class B output stage circuit schematic. (10%)
(c) Please explain why usually a class B output stage has a higher power-conversion
efficiency than a class A output stage does. (5%) 【102 中興電機所】
【解】：
(a)A 類 C.C.圖騰式如下圖： (b) B 類 C.C.推拉式電路如下：

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 中興電機系電子學歷試繪整 1(簡解)
Copyright by @劉明彰電子戰神

(c) B 類靜態功率為零。而 A 類靜態時，偏壓源 I ref 消耗太多功率。

4. Neglecting channel-length modulation and body effect, compute the transfer

function of the common-gate amplifier shown in the Fig. Assume that the
transistor operates with the transconductance of g m , and
VDD ， VB ，and I B are supply voltage, bias voltage and
bias current respectively, the overall transfer function can
V AV
be given by： o ( s)  (15%)
Vi s s
(1  )(1  )
 p1  p2
(a) Find Av . (b) The equivalent capacitances at nodes
X and Y are C S and C D respectively, yielding two pole frequencies. Please
find  p1 and  p 2 . 【102 中興電機所】
【解】：
1  g m Rs 1 g m RD
Ans.  p1  ，  p2  ， Av 
Rs CS RD C D 1  g m Rs

5. The transistor operates with the transconductance of

g m . Neglecting channel-length modulation, find the
voltage gain Vo /VS of the feedback circuit in the Fig.
(10%) 【102 年中興電機所】
【解】：
Vo  ( g m RF  1)  ( RF // RD )
Ans. 
Vi R
RF  Rs  ( g m Rs  s )  ( RF // RD )
RF

6. A design error has resulted in a gross mismatch in the circuit of the Fig.
Specifically, Q2 has 3/2 times the W / L ratio of Q1 . If Vid is a small

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 中興電機系電子學歷試繪整 1(簡解)
Copyright by @劉明彰電子戰神
sine-wave signal, and Vod is the small-signal output voltage, find: (Note
k n  Cox  n and W / L of Q1 is expressed as W / L . Assume the current
source I is ideal.)
(a)The DC bias currents of Q1 and Q2 ( I D1 and I D 2 ). (5%)
(b) VOV for each of Q1 and Q2 in terms of I , W / L , k n ? ( VOV means the
overdrive voltage of transistor.) (4%)
(c)The transconductance for each Q1 and Q2 in
terms of I and VOV . (6%)

(d)The small-signal differential gain

Ad ( vod / vid ) in terms of RD ， I and VOV .
(The channel length modulation is neglected
(  0) . (5%) (e) The DC voltage difference between the drains Q1 and Q2 in
terms of I and RD . (5%)【102 中興電機所】
【解】：

2 3 4 I
Ans. (a) I D1  I  ， I D 2  I ，(b) VOV  
5 5 5 W 
kn   
L
4I 6 I
(c) g m1  ， gm2  
5VOV 5 VOV

Vo 24 I  RD 1
(d) Ad    ，(e) Vo (dc)    I  RD
Vi 25 VOV 5

101 中興電機系

1. Consider the electric circuit shown in the Fig. Determine

the quiescent values I CQ and VECQ and the small-signal
voltage gain, Av  ? The transistor’s parameters are
VEB ( on)  0.7V ，  F  200 ， VT  25mV (thermal voltage)
and VA   . (15%)【101 中興電機所】
【解】：

Ans. <1> I C  0.61mA ， VECQ  1.334V

Vo V
<2> Av     1.95
VS V

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 中興電機系電子學歷試繪整 1(簡解)
Copyright by @劉明彰電子戰神
2. The electric circuit is shown in the Fig. Assume that the device’s parameters are
VTN , E  1V , VTP, E  1V ,  N , E  10mA/V 2 ，  P, E  1mA/V 2 ，and   0 . VDD is
5V. Please draw the transfer curve (i.e., Vo vs Vi ) and find the output voltage,
Vo ， as the input voltages， Vi , are 0V and 5V.【102 中興電機所】
【解】：

Ans. 輸出入轉換曲線如下：
當 Vi  0 對應的 Vo  5V ，當 Vi  5V 對應的 Vo  0

3. The Fig. shows a circuit for a differential amplifier with an active load with all
transistors biased at saturation. The DC bias circuit that establishes an appropriate
DC voltage at the drains of Q1 and Q2 is not shown. The technology is specified
as follows: Vtn | Vtp |  0.6V ,
VAn  30V ， | VAp |  20V ，
 n   p  1.25mA/V 2
for all
transistors except  p  2.5mA/V for 2

Q3 , and R  10K . Neglect body

effects for all transistors. For DC bias
calculations you may also neglect
channel length modulation. (Note
 n  Cox  nW / L and
 p  Cox  pW / L ) (a)Find VGS 7 , I ref and I . (7%) (b)What is the input
common-mode range ( VCM max and VCM min are the upper and lower limits of the
gate voltages of Q1 and Q2 )? (6%) (c)Find transcondctance g m and output
resistance ro for Q1 and Q4 . (6%) (d)Find the differential gain Vo / Vid . (6%)
【101 中興電機所】
【解】：

Ans. (a) VGS 7  1V ， I ref  0.1mA ， I  0.2mA

(b) ViCM (max)  1.6V ， ViCM (min)   0.2V
(c) g m1, 2, 4,5  0.5mS ， ro,1, 2  200K ， ro 4,5  300K
Vo V
(d)  60
Vd V

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 中興電機系電子學歷試繪整 1(簡解)
Copyright by @劉明彰電子戰神
4. In the Fig. ，consider the class AB output stage under the conditions that
VCC  20V ， RL  75 ，and the output is sinusoidal with a maximum amplitude of
15V. Let QN and QP be matched with I S  10 13 A and   100 . Assume that
the biasing diodes have one-third the junction area
of the output devices. Vt  25mV .
(a)Find the I L max ， the largest current of RL .
(b)Find the I B QN ，the base current of QN when
RL has the largest current.
(c)Find the minimum value of I bias that
guarantees a minimum of 1mA through the diodes
at all times.
(d)Determine the quiescent current and the quiescent power dissipation in the
output transistors (i.e., at Vo  0 )【101 中興電機所】
【解】：
Ans. (a) I L(max)  0.2 A ，(b) I B, N  1.98mA ，(c) I Bias  2.98mA
(d) I CQ  8.68mA ， PQ  347.2mW

5. A CMOS operation amplifier with the bias circuit is illustrated in the Fig.
Neglecting channel-length modulation effect and body effect, all transistors operate
in saturation mode with the parameters: Vtn  | Vtp |  0.6V ， nCox  2 pCox  K ，
and the sizes are shown in the schematic. (Note that： Cc is the compensated
capacitor and Vo   A2 V1 .) (25%) 【101 年中興電機所】
(a)Calculate the biased current I B . (Please represent with K , W / L , RB ，etc.)
(b)In the circuit, we can observe that i1  Gm  vi where Gm  X / RB . Please
calculate X .
(c)Find the unit-gain frequency for the operation amplifier.
(d)The slew rate (SR) is the maximum rate at which the output changes when input
dv
signals are large. Find SR for the operation amplifier. ( SR  o )
dt max
(e)Assume the p-type transistor QSS operates at VSG, p  1V . The operation
amplifier is placed in unity-gain feedback. What is the allowable input voltage
range? 【101 中興電機所】

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 中興電機系電子學歷試繪整 1(簡解)
Copyright by @劉明彰電子戰神
【解】：
8 1 4 4  rad 
Ans. (a) I B   ，(b X  ，(c) t   
9 W 2
K RB 3 3 R B C C  s 
L
IB 8
(d) S.R.   ，(e) Vi (max)  1.72V ， Vi (min)  0.28V
CC 9 K W  R 2  C
B C
L

100 中興電機系

1. Answer the following questions. (12%)

(a)A p-channel enhancement-mode MOSFET has a threshold voltage of
VTP, E  1.2V and an applied gate-to-source voltage of VGS  2.4V . Determine
the operating region (i.e. triode region or saturation region) when (i) VDS  0.4V ;
(ii) VDS  2.5V and (iii) VDS  5V .
(b)Repeat (a) for a p-channel depletion-mode MOSFET with a threshold voltage of
VTP, D  1.2V . 【100 中興電機所】
【解】：
Ans. (a) VDS  0.4V  VSD  | Vov | (triode region)
VDS  2.5V  VSD  | Vov | (saturation region)
VDS  5V  VSD  | Vov | (saturation region)
(b) Vov  2.4  1.2  3.6V
VDS  0.4V  VSD  | Vov | (triode)
VDS  2.5V  VSD  | Vov | (triode)
VDS  5V  VSD  | Vov | (saturation)

2. For the circuit shown in the Fig.，please calculate the node voltages VE and
VC , and the branch currents I E , I C , and I B . Assume the current gain  F to be
100 and the thermal voltage, VT  25mV . (13%) 【100 中興電機所】

【解】：

29
 中興電機系電子學歷試繪整 1(簡解)
Copyright by @劉明彰電子戰神
Ans. VE   4.3V  I E  1.433mA
VC   4.5V  I C  0.73mA ， I B  0.703mA

3. For the feedback circuit in the Fig. ，assume the transconductances of

transistors M 1 and M 2 are g m1 and g m 2 ，
respectively，and   0 (i.e.，ro   ). (Note that:
VDD is power supply and VB is dc bias.)
(a) Show that the feedback is negative. (3%)
(b)Find an expression for Af  Vout / I in . (6%)
(c) Find Rin and Rout . (6%)【100 中興電機所】
【解】：
Ans. (a)設 M 1 源極訊號往上升，導致 M 1 汲極訊號往上升，使 M 2 汲極訊號往下
降，再透過 RF 使 M 1 源極訊號往下降，故為負回授
1
// RF
g m1 RD 2 // RF
(b)(c) Rin  ， Rout 
g  g  RD1  ( RD 2 // RF ) g  g  RD1  ( RD 2 // RF )
1  m1 m 2 1  m1 m 2
1  g m1  RF 1  g m1  RF
Vo g m1 g m 2  RF  RD1  ( RD 2 // RF )

I in 1  g m1  RF  g m1  g m 2  RD1  ( RD 2 // RF )

4. For the active filter in the Fig.，assume all operation amplifiers are ideal.
(a)Find the transfer function of the circuit, T (s)  Vo / Vi . (7%)
(b)What kind of filter does this circuit realize? (3%)【100 中興電機所】

【解】：

Vo s 2 R 2C 2  sRC  1
Ans. (a)  2 2 2 ， (b)二階全通濾波器
Vi s R C  sRC  1

5. The Fig. shows a two-stage CMOS op-amp.

Please find its input common-mode range，
the range allowed for output， Vo ，the first
stage gain， A1，the op-amp input resistance，
30
 中興電機系電子學歷試繪整 1(簡解)
Copyright by @劉明彰電子戰神
and the op-amp output resistance. Assume VDD  1.5V ，  VSS  1.5V ，all
overdrive voltages of 0.3-V magnitude, Vtn  | Vtp |  0.4V ，all devices are 2m
 |  25V/m , I1  I 2  0.5mA ，and the operating frequency is very
  | VAp
long, VAn
close to zero. (25%)【100 中興電機所】
【解】：

Ans. ViCM (max)  0.5V ， ViCM (min)   1.2V

V
(b) A1   167 ，(c) Ro  50K
V

6. A DRAM cell is shown in Fig. (a). For a particular DRAM design, the cell
capacitance CS  60 fF ，VDD  5V ，and Vt (including the body effect)  1V . Each
cell represents a capacitive load on the bit line of 2 fF . The sense amplifier given in
Fig. (b) and other circuitry attached to the bit line have a 30 fF capacitance.
Assume the bit lines are precharged to VDD / 2 before sensing and the word line
becomes VDD when the cell is selected. (a)Explain the operation that the sense
amplifier in Fig.(b) can read the data stored in a DRAM cell. (8%) (b)What is the
maximum number of cells that can be attached to a bit line while ensuring a
minimum bit-line signal of 0.1V? (8%) (c)How many bits of row addressing can be
used? (4%) (d)If the sense-amplifier gain is increased by a factor of 4, how many
word-line address bits can be accommodated? (5%)【100 中興電機所】

【解】：
Ans. 略

-------------------------------同學加油，堅持---

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