INTRODUCTION

INTRODUCTION TO VERILOG:
Verilog is a hardware description language (HDL) that describes
the functionality of hardware design and the synthesis tool converts
hardware descriptions into an actual design that has combinational
and sequential elements. Verilog language is simpler than VHDL
Verilog is based on ‘C’ language, whereas VHDL is based on Ada and
Pascal languages.
Latest Verilog standards : IEEE standard 1364-2005.
Verilog is basically a structural language and defines four
abstraction levels to implement modules . With respect to the external
environment , the module is viewed as identical irrespective of
abstraction levels. But internal module implementation differ on
abstraction.
TECH EVOLUTION:
 SSI (Small scale integration).
 MSI (Medium scale integration).
 LSI (Large scale integration).
 VLSI (Very large scale integration).
HARDWARE DISCRIPTION LANGUAGE:
Hardware description language (HDL) used to model electronic
systems. It is most commonly used in the design and verification
of digital circuits at the register-transfer level of abstraction. It is also
used in the verification of analog circuits and mixed-signal circuits.
WHY VERILOG HDL’S:
 Verilog HDL’S used to model electronic systems (or) to design
hardware circuits.
 Verilog HDL allows different levels of abstraction to be mixed in the
same model.
 Verilog HDL’s is similar to computer programming to understand.
 Most synthesis tool support.
 Easy to learn and easy to use.
VERILOG (VS ) VHDL:

MODULE AND PORTS IN VERILOG:

 Module is a basic building design block that implements certain

functionality.It is enclosed within module and end module
keywords.
 It has a module name and port interface. All variable declarations,
data flow statements, functions or task, behaviour statements ,
lower module instances are must be defined within the module
and end module.
SYNTAX:
module <name> ( [port_list] );
//contents of the module
endmodule
RULES FOR MODULE:
 Verilog is case sensitive
 It can be composed of letters, digits , dollar sign and underscore
only.
 It must start with letter or underscore.
 No spaces are allowed inside an identifier.
 It has reserved keywords cannot be used as identifier.
STRUCTURE OF THE MODULE:
It starts with module and ends with endmodule.
Module name (outputs, inputs, inouts);
//declaration of outputs
// declaration of inputs
//statements for describing hardware
endmodule .

PORTS:
 An interface to communicate with other modules or a test bench
environment is called a port. In simple words, the input/ output
pins of digital design are known as ports.This interface is termed a
port interface or port list.

1. Input port - input.

To receive signal values from another module.
2. Output port - output
To send signal values to another module.
3. Bidirectional - inout
To send (or) receive signal values to another module.
COMPONENTS OF STIMULATION:
 DUT and TB are the components of stimulation:
DUT: (Design under test)
 DUT is a verilog module (or) design that we want to test for
different inputs.
TB: (TEST BENCH)
Test bench is used to generate inputs for the DUT and comparing it
with different outputs.

LEXICAL CONVENTIONS:
1) Comments
2) White spaces
3) Number specification
4) Strings
5) Identifiers
6) Keywords
7) Operators

COMMENTS:
 Comments are used for better understanding and to describe any
functionality in simple language.
 Comments are two types:
 Single line comment ( starts with //)
//This is the single line comment
 Multiple lines comment (multiple lines can be enclosed as
comments within /* and */ ).
 /* This is the first line
This is the second line
This is the third line
….
*/
WHITE SPACES:
 Is a term used to represent the characters for spaces, tabs, and
newlines.
 It helps in making of code easier to read.
“\t” -tabs
“\n” - newlines
“\b” -blankspaces.
NUMBER SPECIFICATION:
The numbers can be specified in two ways
 Sized
 Un sized
SIZED:
 Sized is specified
 Underscore is used separate the bits for redability.
Syntax: <size>`<radix> <number>
Ex:4`b1111 - 4 bit binary number
12`habc-12`b1010_1011_1100 - 12 bit hexadecimal number
UNSIZED:
 Size is not specified and tool it has the default number of bits
(usually 32-bits).
Syntax: `<radix> <number>

Ex:`o21 - 32 bit octal

`d225-32 bit decimal
`h13x- 32 bit hexa decimal
`b1111- 32 bit binary.
STRINGS :
Group of characters with in double quotes.They can not be divided
into multiple lines.Each character in string take 1byte to store. They
are Stored as reg type variables.
Ex: “Hello world”

IDENTIFIERS:
The identifiers are the names given to the objects (or) written beside of
the keywords.

Ex: assign andgate // and gate is a name of the module

RULES FOR IDENTIFIERS:
 They are case-sensitive and made up of alphanumeric
characters(A to Z, a to z, 0 to 9) , the underscore( _ ) and the dollar
sign( $ ).
 They cannot start with dollar sign ( $ ) and numbers.
KEYWORDS:
The keywords are special identifiers that are reserved to define the
verilog language construct . They are in lowercase
Ex: module , endmodule, assign , initial , begin , end , always etc.
OPERATORS :
Operators are symbols that performs various operations on data.
Verilog has different types of operators.
1) Bitwise
2) Logical
3) Reduction
4) Arithmetic
5) Relational
6) Equality
7) Shift
8) Concatenate
9) Conditional
10) Replication
BITWISE:
 Bitwise operators operate on individual bits of operands.

Program:
module bitwise_operators;
reg[3:0]a,b,c,d;
reg[2:0]x,y,z;
initial begin
$monitor(“x=%0b, y=%0b, z=%0b”,x,y,z);
a=2;b=5;c=3’b101;
 x = a&b;
y =c|d;
z =a^b;
end
endmodule

LOGICAL:
 Logical operators operates on individual bits of operands
 Logical operators provides result either as true (or) false (or) either .

Program:
module logical_operator;
reg[3:0] a,b,c,d;
reg[3:0] x,y,z;
initial begin
$monitor(“x=%0b, y=%0b, z=%0b”,x,y,z);
a=6;b=2;c=4’b1001;d=4’b0000;
x=a&&b;
y=c||d;
z=!d;
end
endmodule

ARITHMETIC:
 It performs arithmetic operation between two operands.
 There are two types of operators unary and binary.
 If the result of any expression is ‘x’ , the result of the expression
is ‘x’.

 5 arithmetic operators (+,-,*, /,%).

Program:
module arithemtic_operator;
reg[2:0] a,b,c;
reg[2:0] x,y,z;
initial begin
a=4;b=3’b101;c=1’b1;
x=a+b;
y=a-b;
z=a*b;
$display(“x=%b,y=%b,z=%b”,x,y,z);
end
endmodule

REDUCTION:
 Reduction operator is used to convert vector to scalar .
 Reduction operator , operates on all bits in a vector to convert the
answer in a single bit.
 In reduction operator we are having only one operand.
Program:
module reduction_operator;
reg[2:0] a,b,c;
reg[2:0] x,y,z;
initial begin
a='b1001;b='b100;c='b0000;
x=(&a);
y=(~|b);
z=(|a);
$monitor("x=%b,y=%b,z=%b",x,y,z);
end
endmodule

RELATIONAL:
 The relational operator compare operands (or) two values and
returns either 1(or) 0 as a result.

Program:

module relational_operators;
reg[3:0] a,b,c,d;
reg[3:0] w,x,y,z;
initial begin
a=5;b=3'b101;c=4'b1000;d=4'b1111;
x=a>b;
y=b<a;
z=c>=d;
w=d<=c;
$display("x=%b,y=%b,z=%b,w=%b",w,x,y,z);
end
Endmodule
EQUALITY OPERATOR:
 The equality and in equality operator compares the values (or) two
operands and results 1 (or) 0.
 If the values (or) either one operand is ‘x’ then it will return
 the value as ‘x’.
 case equality never produces an ‘x’ result it produces only ‘1’
 (or) ‘0’.
 Equality will produce an ‘x’ result if any of the operands has ‘x’
bits.
Program:

module equality_operators;
reg[3:0] a,b,c,d;
reg[3:0] w,x,y,z;
initial begin
a=6;b=2;c=4'b1001;d=4'0000;
x=a>b;
y=c<d;
z=a>=c;
w=d<=b;
$display("x=%b,y=%b,z=%b,w=%b",w,x,y,z);
end
endmodule

SHIFT OPERATOR:
 Shift operator are used to shift the operators either right (or) left.
 The shifted bits are lost and zero is filled.
 (<<) - left shift
 (>>) - right shift
Program:
module shift_operator;
reg[3:0] a;
reg[3:0] x;
initial begin
a=1001;
x=a<<2;
$monitor("x=%b,a=%b",x,a);
end
endmodule
CONCATENATION OPERATOR [{}]:
 It combines bits of 2(or) more data
 Ex: a=3’b101
b=2’b10
c=4’b1001
then y={a,b} = 5’b10110
Y={c,b,a}=9’b100110101

Program:
module concatenation_operators;
reg[2:0] a,b,c,d;
reg[4:0] w,x,y,z;
initial begin
a=1'b1;b=3'b101;c=2'b11;d=2'b10;
w={b,c};
x={a,b,c,2'b01};
y={a,b[2],c[0]};
z={b[1],d[1]};
$display("a=%b,b=%b,c=%b,d=%b,w=%b,x=%b,y=%b,z=%b",a,b,c,d,w,x,y,z);
end
endmodule

REPLICATION OPERATOR:

 It is used to replicate (or) repeat a group of bits ‘n’ times in verilog.

[n[m]] - replication operator

 Ex: y={3{2’b10}} = 101010
 Y={2{3’b101}} = 101101

Program:
module replication_operators;
reg[2:0] a,b,c,d;
reg[15:0] x,y,z;
initial begin
a=1'b1;b=2'b00;c=2'b10;
x={4{a[0]}};
y={ {4{a[0]}},{2{b[1]}} };
z={ {4{a[0]}},{2{b}},c[1]};
$display("x=%b,y=%b,z=%b",x,y,z);
end
endmodule
CONDITIONAL OPERATOR:
 It is used to evaluate the conditions (or) logical expression

Syntax:
<result>=<conditional_expression>?<true_expression>:
<false_expression>

 Ex: 3’b101,b=3’b100
Y=(a>b) ? (a+b) : (a-b)
Y=(a= =b) ? (~a) : (a&b)

Program:
module conditional_operators;
reg a,b,x;
reg y;
initial begin
a=0;b=1;x=1;
assign y=x?a:b;
$display("the result y=%b",y);
end
endmodule
LEVELS OF ABSTARCTION:
Verilog has a capability of designing a module in several coding
styles depending on the needs of a design , each module can be
defined at four levels of abstraction.
They are :
1. Behaviour level
2. Data flow level
3. Gate level/structural level
4. Switch level

1.BEHAVIOUR LEVEL:
In behaviour model the module is implemented based on the
behaviour of the circuit without of the hardware implementation.

2.DATAFLOW LEVEL:
In data flow level the module is implemented by specifying the data
flow.
It is similar to the logical expression.
In data flow level by seeing the data we can realize how the data is
flowing from input to the output .

3.GATE LEVEL:
In these method the module is implemented in terms of the logic
gates and interconnections between the gates.

4.SWITCH LEVEL:
In these method the module is implemented in terms of the
transistors, switches and interconnections between them.
DATA TYPES:
The data storage and transmission elements found in digital
hardware are represented by data types.
Verilog data types are 4- state, they can take on 4 values they are
0,X,1,Z.
0 - Represents number ‘0’ (or) logic ‘0’ (or) false ‘0’.
1- Represents number ‘1’ (or) logic ‘1’ (or) false ‘1’.
X- Represents unknown logic value.
Z- Represents hign impedance.
The verilog data types are divided into 2 types .
They are:
 NET
 REG
NET:
The net data type represents the physical connection between
gates (or) modules (or) structural entities.The net data type does not
store any value.The value changes when the driver changes the value.
Net data types can only be assigned values by continuous assignment
or driven it from an output port.These net data types we have to use
with output ports. Default value of wire ‘z’.
SYNTAX: net_type[range] list_of_variables.
NET TYPES:
Wire , tri.
Supply 1, supply 0.
Wor , trior.
Wand , triand.
Tri 1, tri 0 are non- synthesizable.
REG:
Reg data type represents the storage.The register variables are used in
procedural block which values from one assignment to the next.
Reg data type is used to hold the value.Default value of reg is ‘x’.
REG TYPES:
integer
real
reg
time
real time
time and realtime for storing simulation times in test benches.
Syntax:
integer list _ of _register _ variables;
real list_ of_ variables;
reg [range] list _ of_ register_variables;
time list _ of_ register_variables;

COMPILER DIRECTIVES :
The compiler directives are used to specify certain information
and ask the complier to process it.Verilog has different types of
compiler directives to set the timescale of stimulation, control the
compiler flow.
Complier directives start with the ( ` ) back quote symbol.The most
commonly used compiler directives are `include,`define and `timescale.

`include:
 Include directive is used when a module defined in a file needs to
be included in another file
Syntax:
`include “file_name”
`define:
 This directive is used to declare a macro (or) to define a data type.
 Macros are code that can be used to perform some tasks.
Syntax:
`define name code
`timescale:
 This directive is used to define the timescale of the timescale.
 Timescale is divided into two types:
 Time unit
 Time precision.
SYSTEM TASK:
 The system tasks are used to perform some operations like
displaying the messages, terminating simulation, generating
random number etc.
Syntax: $<keyword>
$MONITOR:
 The $monitor automatically print out variable (or) expression
values whenever the variable (or) expression in its argument list
changes.
Example:
module tb;
reg a,b;
monitor dut(a,b);
initial begin
$monitor("a=%b,b=%b,s=%b,c=%b",a,b,s,c);
a=0;b=0;
#5;
a=0;b=1;
#5;
a=1;b=0;
#5;
a=1;b=1;
#5;
end
endmodule
$DISPLAY:
 Is the normal display, which executes its parameters wherever it is
present in the code.
$WRITE:
 Is similar to $display except that $display displays the contents in
the next line (cursor moves to the next line before displaying),
unlike $write in which the contents are displayed in the same line.
$STROBE:
 Executes only once in a time instant, when all processes in that
time instant have executed.
Example:
module tb;
reg a=0;b=0;
initial begin
a=0;
b=1;
$display(a,b);
$strobe(a,b);
b=0;
a=1;
$display(a,b);
$write(a,b);
#1 b=1;
$display(a,b);
end
endmodule
DATA FLOW MODELLING:

Data flow modeling describes hardware in terms of the flow of

data from input to output.The data flow modeling style is mainly used
to describe combinational circuits.
The primary mechanism used is a continuous assignment.It is
similar to the logical expression.
It is designed by specifying the data flow.By specifying the design, we
can realize how data flows between the hardware and register and
data is processed in the design.
CONTINUOUS ASSIGNMENT:

These continuous assignment statement is typically used to

continuously drive a signal to wire datatype and gets synthesized as
combinational logic.A continuous assignment statement is
represented by using “assign” statement.
Continuous assignments are always active because when ever
any operand on the RHS change in value , then LHS will be updated
with the new value.The LHS of an assignment should be either scalar
(or) vector (or) concatenation of both.Registers are not applicable on
the LHS.RHS may be register, net (or) function calls of scalar (or)
vector type.
Syntax: assign <expression> = <delay> <constant value or
expression>

Ex: wire one=1’b1; // implicit

assign ab=a&b; // explicit
assign= {count, sum}= a+b+cin // concatenation.

IMPLICIT CONTINUOUS ASSIGNMENT:

The implicit continuous assignment is a single statement that
contents net declaration and the continuous assignment .
// wire result =i1^i2;
SYNTAX:
module module_name(port_list);
input input_ports;
output output_ports;
wire LHS_variable = RHS_variable;
// RHS_constants;
// RHS_expression;
Ex: wire result = i1^i2;
wire x=a&b;
PROGRAM:

// IMPLICIT TYPE:
module and2(a,b,x);
input a,b;
output x;
wire x=a&b; //continuous implicit statement
endmodule

// IMPLICIT DATA FLOW STYLE WITH DELAY

module and2(a,b,x);
input a,b;
output x;
wire #2 x=a&b; // continuous implicit delay statement
endmodule

EXPLICIT ASSIGNMENT STATEMENT:

Regular continuous assignment /explicit assignment means the
declaration of net and its continuous assignment are done in two
different statements.One is to define the value.Another is to assign the
value.
Syntax:
module module_name(port_list);
input in_ports;
output out_ports;
//inout inout_ports; // inout is used in bidirectional
wire out_ports;
assign LHS_variables = RHS_variable (or) constant (or) expression;
endmodule
Ex: wire result;
Assign result = i1^i2;

PROGRAM:

// EXPLICIT TYPE:
module and2(a,b,x);
input a,b;
output x;
//output wire x;
wire x;
assign x=a&b;
endmodule

CODES IN DATA FLOW MODELLING:

Logic gates:
module all_gates(a,b,p,q,r,s,t,u,v); // dut for all logic gates
input a,b;
output p,q,r,s,t,u,v;
assign p= (a&b);
assign q= (a|b);
assign r= ~(a&b);
assign s= ~(a|b);
assign t= (a^b);
assign u= ~(a^b);
assign v= !(a);
endmodule

// test bench for all logic gates

module allgates_tb;
reg a,b;
wire p,q,r,s,t,u,v;
all_gates dut(a,b,p,q,r,s,t,u,v);
$monitor(“a=%0b,b=%0b,p=%0b,q=%0b,r=%0b,s=%0b,t=%0b,u=%0b,v=%0b”,a,b,p,q,
r,s,t,u,v);
a=0;b=0;
#5;
a=0;b=1;
#5;
a=1;b=0;
#5;
a=1;b=1;
#5;
end
endmodule
 STIMULATION RESULT:

HALF ADDER:
 The half adder is a basic building block of adding two numbers and
produces two outputs.
 The carry and sum are the two outputs .
BLOCK DIAGRAM:

TRUTH TABLE:

‘A’ and ‘B’ are the inputs and ‘sum’ and ‘carry’ are the outputs.

Sum = x'y+xy'
Carry = xy
PROGRAM:

// dut for half adder

module half_adder(a,b,s,c);
input a,b;
output s,c;
assign s=a^b;
assign c=a&b;
endmodule

// test bench for half adder

module half_adder_tb;
reg a,b;
wire s,c;
//instantiation
half_adder dut(a,b,s,c);
initial begin
$monitor("a=%b,b=%b,s=%b,c=%b",a,b,s,c);
a=0;b=0;
#5;
a=0;b=1;
#5;
//$display("a=%b,b=%b,s=%b,c=%b",a,b,s,c);
a=1;b=0;
#5;
//$display("a=%b,b=%b,s=%b,c=%b",a,b,s,c);
a=1;b=1;
#5;
//$display("a=%b,b=%b,s=%b,c=%b",a,b,s,c);
end
endmodule

STIMULATION RESULT:
FULL ADDER:
 Full adder is used to add three inputs and produces two outputs.
 The three inputs are A,B and Cin (input carry).
 The two outputs are sum and carry(Cout).
BLOCK DIAGRAM:

TRUTH TABLE:

Sum = x' y' z+x' yz+xy' z'+xyz

Carry = xy+xz+yz
PROGRAM:

// dut for full adder

module full_adder(a,b,cin,s,cout);
input a,b,cin;
output s,cout;
assign s=a^b^cin;
assign cout=(a&b)|(b&cin)|(a&cin);
endmodule

// testbench for full adder

module full_adder_tb;
reg a,b,cin;
wire s,cout;
//instantiation
full_adder dut(a,b,cin,s,cout);
initial begin
$monitor("a=%b,b=%b,cin=%b,s=%b,cout=%b",a,b,cin,s,cout);
a=0;b=0;cin=0;
#5;
a=0;b=0;cin=1;
#5;
a=0;b=1;cin=0;
#5;
a=0;b=1;cin=1;
#5;
a=1;b=0;cin=0;
#5;
a=1;b=0;cin=1;
#5;
a=1;b=1;cin=0;
#5;
a=1;b=1;cin=1;
#5;
end
endmodule

STIMULATION RESULT:

HALF SUBSTRACTOR:
 The half substractor is a basic building block of subtracting two
binary numbers .
 It has two inputs and produces the two outputs.
 The difference and the borrow are the outputs of the half
substractor.
BLOCK DIAGRAM:

TRUTH TABLE:

EXPRESSION:

Diff= A'B+AB'
Borrow = A'B
‘A’ and ‘ B’ are the inputs .
‘ Diff ’ and ‘ Borrow ’ are the outputs.

Program:
//dut for half substractor
module half_substractor(a,b,D,B);
input a,b;
output D,B;
assign D=a^b;
assign B=~a&b;
Endmodule

// testbench for half substractor

module half_subtractor_tb;
reg a,b;
wire D,B;
//instantiation
half_subtractor dut(a,b,D,B);
initial begin
$monitor("a=%b,b=%b,D=%b,B=%b",a,b,D,B);
a=0;b=0;
#5;
a=0;b=1;
#5;
//$display("a=%b,b=%b,D=%b,B=%b",a,b,D,B);
a=1;b=0;
#5;
//$display("a=%b,b=%b,D=%b,B=%b",a,b,D,B);
a=1;b=1;
#5;
//$display("a=%b,b=%b,D=%b,B=%b",a,b,D,B);
end
endmodule

STIMULATION RESULT:

FULL SUBSTRACTOR:

 Full substractor is used to to substarct the three 1- bit numbers.

 It has three inputs and produces two outputs.
 The three inputs are A,B and C they are minuend , substrahed
and borrow.
 The two outputs are difference and borrow.
BLOCK DIAGRAM:

TRUTH TABLE:

 ‘ A ’ and ‘ B ’ are the two inputs .

 ‘ Borrow in ’ is the third input which represents the borrow.

 ‘ Diff ’ and ‘ Borrow ’ are the output variables that defines the
output values.

PROGRAM:

// dut for full substractor

module full_subtractor(a,b,Bin,D,Bout);
input a,b,Bin;
output D,Bout;
assign D=a^b^Bin;
assign Bout=(a&b)|((a^b)&Bin);
endmodule
// testbench for full substractor
module full_subtractor_tb;
reg a,b,Bin;
wire D,Bout;
//instantiation
full_subtractor dut(a,b,Bin,D,Bout);
initial begin
$monitor("a=%b,b=%b,Bin=%b,D=%b,Bout=%b",a,b,Bin,D,Bout);
a=0;b=0;Bin=0;
#5;
a=0;b=0;Bin=1;
#5;
a=0;b=1;Bin=0;
#5;
a=0;b=1;Bin=1;
#5;
a=1;b=0;Bin=0;
#5;
a=1;b=0;Bin=1;
#5;
a=1;b=1;Bin=0;
#5;
a=1;b=1;Bin=1;
#5;
end
endmodule

STIMULATION RESULT:
MULTIPLEXER:
 Multiplexer(MUX) is a combinational logic circuit that has 2n input
lines and a single output line and selection line.
 The binary information received from the input line and directed to
the output line.
 On the basis of selection line, one of these data inputs will be
connected to the output.
2x1 MUX:
 It has 2 inputs A1,A0 and 1 selection line (s) and 1 output ( Y ).
 On the bases of the selection line (s) one of these inputs are
connected to the output.
Block diagram:

TRUTH TABLE:

EXPRESSION:
Y=S0'.A0+S0.A1
Program:

//dut for 2x1 mux

module mux_2x1(y,s,i0,i1);
input s,i0,i1;
output y;
assign y=(~s&i0)|(s&i1);
endmodule

//test bench for 2x1 mux

module mux_2x1_tb;
reg s,i0,i1;
wire y;
//instantiation
mux_2x1 dut(y,s,i0,i1);
initial begin
$monitor("i0=%0b,i1=%0b,s=%0b,y=%0b",i0,i1,s,y);
s=0;i1=0;i0=0;
#5;
i0=1;
#5;
s=1;i1=1;i0=0;
#5;
i0=1;
#5;
end
endmodule

STIMULATION RESULT:
4x1 MUX:
 In 4x1 mux there are 4 inputs A0,A1,A2,A3 and two selection
lines S0,S1 and single output Y.
BLOCK DIAGRAM:

TRUTH TABLE:

EXPRESSION:
Y=S1' S0' A0+S1' S0 A1+S1 S0' A2+S1 S0 A3

PROGRAM:
//dut for 4x1 mux
module mux_4x1(y,s1,s0,i3,i2,i1,i0);
output y;
input s1,s0,i3,i2,i1,i0;
assign y=(~s1&~s0&i0)|
(~s1&s0&i1)|
(s1&~s0&i2)|
(s1&s0&i3);
endmodule
// testbench for 4x1 mux
module tb_mux_4x1;
wire y;
reg s1,s0,i3,i2,i1,i0;
mux_4x1 dut (y,s1,s0,i3,i2,i1,i0);
initial begin
$monitor("time=%d,s1=%b,s0=%b,i3=%b,i2=%b,i1=%b,i0=%b,y=%b",$time,s1,s0,i3,i2
,i1,i0,y);
{s1,s0,i3,i2,i1,i0}=6'b000000;
#5;
{s1,s0,i3,i2,i1,i0}=6'b000001;
#5;
{s1,s0,i3,i2,i1,i0}=6'b010001;
#5;
{s1,s0,i3,i2,i1,i0}=6'b010011;
#5;
{s1,s0,i3,i2,i1,i0}=6'b100011;
#5;
{s1,s0,i3,i2,i1,i0}=6'b100111;
#5;
{s1,s0,i3,i2,i1,i0}=6'b110111;
#5;
{s1,s0,i3,i2,i1,i0}=6'b111111;
#5;
end
endmodule

STIMULATION RESULT:
DEMULTIPLEXER:
 A demultiplexer is a combinational circuit that has only single
input and 2N output line and one selection line and one output.
 The information received from the single input line and directed to
the output lines.
 On the basis of the values of the selection lines , the input line is
connected to the one of these output lines.
1x2 demultiplexer:
 The 1x2 demultiplexer has one single input ( A ) and two outputs
Y0, Y1 and one selection line.
BLOCK DIAGRAM:

TRUTH TABLE:

EXPRESSION:
Y0=S0'.A
Y1=S0.A
PROGRAM:
//dut for demux 1x2
module demux_1x2(y0,y1,a,s);
input a,s;
output y1,y0;
assign y0=~s&a;
assign y1=s&a;
endmodule

//testbench for demux 1x2

module demux_1x2_tb;
reg a,s;
wire y0,y1;
demux_1x2 dut(y0,y1,a,s);
initial begin
$monitor("a=%b,s=%b,y0=%b,y1=%b",a,s,y0,y1);
s=0; a=1;
#5;
s=1; a=1;
#5;
end
endmodule
STIMULATIONRESULT:

ENCODER:
 The combinational circuit that change the binary information into
N output line.
 The binary information is passed in the form of 2N input lines.
 The output line defines the N- bit code for binary information.
4 to 2 encoder:
 The 4 to 2 line encoder has 4 inputs Y0, Y1, Y2, Y3 and two
outputs A0,A1.
 At any time from these four inputs only one input can be ‘1’ to get
the respective binary code at the output .
BLOCK DIAGRAM:

TRUTH TABLE:
EXPRESSION:
A1=Y3+Y2
A0=Y3+Y1

PROGRAM:

// dut for 4 to 2 encoder

module encoder_4x2(a,b,c,d,x,y);
input a,b,c,d;
output x,y;
assign x=b|d;
assign y=c|d;
endmodule

// test bench for 4 to 2 encoder

module encoder_4x2_tb;
reg a,b,c,d;
wire x,y;
//instantiation
encoder_4x2 dut(a,b,c,d,x,y);
initial begin
$monitor("a=%b,b=%b,c=%b,d=%b,x=%b,y=%b",a,b,c,d,x,y);
a=0;b=0;c=0;d=1;
#5;
a=0;b=0;c=1;d=0;
#5;
a=0;b=1;c=0;d=0;
#5;
a=1;b=0;c=0;d=0;
#5;
end
endmodule

STIMULATION RESULT:
8 to 3 encoder:
 It is also called as octal to binary encoder.
 It has 8 inputs Y0,Y1,Y2,Y3,Y4,Y5,Y6,Y7.
 It has 3 outputs A0,A1,A2.
BLOCK DIAGRAM:

TRUTH TABLE:

EXPRESSION:
A2=Y4+Y5+Y6+Y7
A1=Y2+Y3+Y6+Y7
A0=Y7+Y5+Y3+Y1

PROGRAM:

//dut for 8 to 3 encoder

module encoder_8x3(y7,y6,y5,y4,y3,y2,y1,y0,a,b,c);
output a,b,c;
input y7,y6,y5,y4,y3,y2,y1,y0;
assign a=y7|y5|y3|y1;
assign b=y2|y3|y6|y7;
assign c=y4|y6|y7;
endmodule
//test bench for 8 to 3 encoder
module encoder_8x3_tb;
reg y7,y6,y5,y4,y3,y2,y1,y0;
wire a,b,c;
encoder_8x3 uut(y7,y6,y5,y4,y3,y2,y1,y0,a,b,c);
initial begin
$monitor("a=%b,b=%b,c=%b,y7=%b,y6=%b,y5=%b,y4=%b,y3=%b,y2=%b,y1=%b,y0=
%b",a,b,c,y7,y6,y5,y4,y3,y2,y1,y0);
y7=0;y6=0;y5=0;y4=0;y3=0;y2=0;y1=0;y0=1;
#5;
y7=0;y6=0;y5=0;y4=0;y3=0;y2=0;y1=1;y0=0;
#5;
y7=0;y6=0;y5=0;y4=0;y3=0;y2=1;y1=0;y0=0;
#5;
y7=0;y6=0;y5=0;y4=0;y3=1;y2=0;y1=0;y0=0;
#5;
y7=0;y6=0;y5=0;y4=1;y3=0;y2=0;y1=0;y0=0;
#5;
y7=0;y6=0;y5=1;y4=0;y3=0;y2=0;y1=0;y0=0;
#5;
y7=0;y6=1;y5=0;y4=0;y3=0;y2=0;y1=0;y0=0;
#5;
y7=1;y6=0;y5=0;y4=0;y3=0;y2=0;y1=0;y0=0;
#5;
end
endmodule

STIMULATION RESULT:
DECODER:
 The combinational circuit that changes the binary information into
2N output lines.
 The binary information is passed in the form of N input lines.
 Decoder perform the reverse operation of encoder.

2 to 4 line decoder:
 The 2 to 4 line decoder has 3 inputs A1,A0 and one enable E.
 It has 4 outputs Y0,Y1,Y2,Y3.
 For each combination of inputs, when the enable ‘E’ is set to 1,one
of these four outputs will be ‘1’.

BLOCK DIAGRAM:

TRUTH TABLE:
EXPRESSION:

Y3=E.A1.A0
Y2=E.A1.A0'
Y1=E.A1'.A0
Y0=E.A1'.A0'

PROGRAM:

//dut for 2 to 4 decoder

module decoder_2x4(w,x,y,z,a,b,en);
output w,x,y,z;
input a,b,en;
assign w=en&a&b;
assign x=en&a&~b;
assign y=en&~a&b;
assign z=en&~a&~b;
endmodule

//testbench for 2 to 4 decoder

module decoder_2x4_tb;
reg a,b,en;
wire w,x,y,z;
//instantiation
decoder_2x4 dut(w,x,y,z,a,b,en);
initial begin
$monitor("a=%b,b=%b,en=%b,w=%b,x=%b,y=%b,z=%b",a,b,en,w,x,y,z);
en=1;
a=0;b=0;
#5;
a=0;b=1;
#5;
a=1;b=0;
#5;
a=1;b=1;
#5;
end
endmodule
STIMULATION RESULT:

3 to 8 decoder:
 3 to 8 decoder is also known as binary to octal decoder.
 It has 3 inputs A1,A0 and A2.
 It has 8 outputs Y0,Y1,Y2,Y3,Y4,Y5,Y6,Y7.
BLOCK DIAGRAM:

TRUTH TABLE:
PROGRAM:
//dut for 3 to 8 decoder
module decoder_3x8(y7,y6,y5,y4,y3,y2,y1,y0,a,b,c);
output y7,y6,y5,y4,y3,y2,y1,y0;
input a,b,c;
assign y0=(~a)&(~b)&(~c);
assign y1=a&(~b)&(~c);
assign y2=(~a)&b&(~c);
assign y3=a&b&(~c);
assign y4=(~a)&(~b)&c;
assign y5=a&(~b)&c;
assign y6=(~a)&b&c;
assign y7=a&b&c;
endmodule

//testbench for 3 to 8 decoder

module decoder_3x8_tb;
reg a,b,c;
wire y7,y6,y5,y4,y3,y2,y1,y0;
decoder_3x8 dut(y7,y6,y5,y4,y3,y2,y1,y0,a,b,c);
initial begin
$monitor("a=%b,b=%b,c=%b,y7=%b,y6=%b,y5=%b,y4=%b,y3=%b,y2=%b,y1=%b,y0=
%b",a,b,c,y7,y6,y5,y4,y3,y2,y1,y0);
a=0;b=0;c=0;
#5;
a=0;b=0;c=1;
#5;
a=0;b=1;c=0;
#5;
a=0;b=1;c=1;
#5;
a=1;b=0;c=0;
#5;
a=1;b=0;c=1;
#5;
a=1;b=1;c=0;
#5;
a=1;b=1;c=1;
#5;
end
endmodule
STIMULATION RESULT:

MAGNITUDE COMPARATOR:

 A magnitude comparator is a combinational circuit that compares

the two binary numbers.
 Checks whether the one binary number is equal , less than or
greater than other binary number.
 It has 2 inputs ‘A’ and ‘B’ and 3 outputs A=B, A<B and A>B.

1- bit Comparator:
 A 1-bit comparator is used to compare two bits.
 It has 2 inputs A and B and 3 outputs .
 The three outputs are A>B, A=B,A<B.
TRUTH TABLE:

EXPRESSION:

A>B: AB'
A<B: A'B
A=B: A'B' + AB
2 - bit comparator:
 2 bit comparator is used to compare two binary numbers each of
two bits.
 It has four inputs A1,A0,B1,B0 and three outputs A>B,A<B and
A=B.

EXPRESSION:
A>B:A1B1’ + A0B1’B0’ + A1A0B0’

A=B: A1’A0’B1’B0’ + A1’A0B1’B0 + A1A0B1B0 + A1A0’B1B0’

: A1’B1’ (A0’B0’ + A0B0) + A1B1 (A0B0 + A0’B0’)

: (A0B0 + A0’B0’) (A1B1 + A1’B1’)

: (A0 Ex-Nor B0) (A1 Ex-Nor B1)

A<B:A1’B1 + A0’B1B0 + A1’A0’B0

TRUTH TABLE:
PROGRAM:
// dut 2-bit comparator
module comp_2_bit(x,y,z,a1,a0,b1,b0);
input a1,a0,b1,b0;
output x,y,z;
//x=a<b y=a=b z=a>b
assign
x=~a1&~a0&~b1&b0|~a1&~a0&b1&~b0|~a1&~a0&b1&b0|~a1&a0&b1&b0|a1&~a
0&~b1&~b0|a1&~a0&b1&b0;
assign
y=~a1&~a0&~b1&~b0|~a1&a0&~b1&b0|~a1&a0&b1&~b0|a1&~a0&~b1&b0|a1&~
a0&b1&~b0|a1&a0&b1&b0;
assign z=~a1&a0&~b1&~b0|a1&a0&~b1&~b0|a1&a0&~b1&b0|a1&a0&b1&~b0;
endmodule

// testbench for 2-bit comparator

module tb_comp_2_bit;
reg a1,a0,b1,b0;
wire x,y,z;
comp_2_bit dut(x,y,z,a1,a0,b1,b0);
initial begin
$monitor("a1=%b,a0=%b,b1=%b,b0=%b,x=%b,y=%b,z=%b",a1,a0,b1,b0,x,y,z);
a1=0;a0=0;b1=0;b0=0;
#5;
a1=0;a0=0;b1=0;b0=1;
#5;
a1=0;a0=0;b1=1;b0=0;
#5;
a1=0;a0=0;b1=1;b0=1;
#5;
a1=0;a0=1;b1=0;b0=0;
#5;
a1=0;a0=1;b1=0;b0=1;
#5;
a1=0;a0=1;b1=1;b0=0;
#5;
a1=0;a0=1;b1=1;b0=1;
#5;
a1=1;a0=0;b1=0;b0=0;
#5;
a1=1;a0=0;b1=0;b0=1;
#5;
a1=1;a0=0;b1=1;b0=0;
#5;
a1=1;a0=0;b1=1;b0=1;
#5;
a1=1;a0=1;b1=0;b0=0;
#5;
a1=1;a0=1;b1=0;b0=1;
#5;
a1=1;a0=1;b1=1;b0=0;
#5;
a1=1;a0=1;b1=1;b0=1;
#5;
end
endmodule

STIMULATION RESULT:
CODE CONVERTERS
Code converters are used convert one type of binary code to one
another.
There are different types of binary codes like BCD code,gray code,
Excess-3 code.
BCD TO 7- SEGMENT:

BCD encoding method uses binary patterns to encode each

decimal value ( from 0 to 9).A seven-segment display is an electrical
device that displays decimal digits using seven Light Emitting Diodes
(LEDs) arranged in a specific pattern (common cathode or common
anode type).
The seven-segment decoder, which has four input lines and
seven output lines (a, b, c, d, e, f, and g), receives this BCD (A, B, C,
and D) as input.The output is provided to a seven-segment LED
display that shows the decimal number depending on the inputs.

BLOCK DIAGRAM:
TRUTH TABLE:

PROGRAM:

// dut for bcd to 7 segment display

module bcd_7(b3,b2,b1,b0,a,b,c,d,e,f,g);
input b3,b2,b1,b0;
output a,b,c,d,e,f,g;
assign a=(b3|b1|(~b2&~b0)|b2&b0);
assign b=(~b1&b0|b1&b0|~b2|~b3);
assign c=(b3|b2|~b1|b0);
assign d=(b3|(b1&~b0)|(~b2|~b0)|(~b2&b1)|(b2&~b1&b0));
assign e=(b1&~b0)|(~b2&~b0);
assign f=(b3|b2&~b1|b2&~b0|~b1&~b0);
assign g=(b3|b2&~b1|~b2&b1|b1&~b0);
endmodule

//testbench for bcd to 7 segment

module bcd_7_tb;
reg b3,b2,b1,b0;
wire a,b,c,d,e,f,g;
bcd_7 dut(b3,b2,b1,b0,a,b,c,d,e,f,g);
initial begin
$monitor("b3=%0b,b2=%0b,b1=%0b,b0=%0b,a=%0b,b=%0b,c=%0b,d=%0b,e=%0b,f=
%0b,g=%0b",b3,b2,b1,b0,a,b,c,d,e,f,g);
b3=0;b2=0;b1=0;b0=0;
#10;
b3=0;b2=0;b1=0;b0=1;
#10;
b3=0;b2=0;b1=1;b0=0;
#10;
b3=0;b2=0;b1=1;b0=1;
#10;
b3=0;b2=1;b1=0;b0=0;
#10;
b3=0;b2=1;b1=0;b0=1;
#10;
b3=0;b2=1;b1=1;b0=0;
#10;
b3=0;b2=1;b1=1;b0=1;
#10;
b3=1;b2=0;b1=0;b0=0;
#10;
end
endmodule

STIMULATION RESULT:
BINARY to GRAY:

 The Most Significant Bit (MSB) of the gray code is always equal to
the MSB of the given binary code.
 Other bits of the output gray code can be obtained by XORing
binary code bit at that index and previous index.

TRUTH TABLE:
 It has four binary inputs a,b,c,d.
 It has four gray outputs g3,g2,g1,g0.

EXPRESSION:
g0=(~c&d|c&~d);
g1=(b&~c|~b&c);
g2=(a^b);
g3=a;

PROGRAM:

//dut for binary to gray code

module binary_gray(a,b,c,d,g3,g2,g1,g0);
input a,b,c,d;
output g3,g2,g1,g0;
assign g0=(~c&d|c&~d);
assign g1=(b&~c|~b&c);
assign g2=(a^b);
assign g3=a;
endmodule

// testbench for binary to gary code

module binary_gray_tb;
reg a,b,c,d;
wire g3,g2,g1,g0;
binary_gray dut(a,b,c,d,g3,g2,g1,g0);
initial begin
$monitor("a=%0b,b=%0b,c=%0b,d=%0b,g3=%0b,g2=%0b,g1=%0b,g0=%0b",a,b,c,d,g
3,g2,g1,g0);
a=0;b=0;c=0;d=0;
#10;
a=0;b=0;c=0;d=1;
#10;
a=0;b=0;c=1;d=0;
#10;
a=0;b=0;c=1;d=1;
#10;
a=0;b=1;c=0;d=0;
#10;
a=0;b=1;c=0;d=1;
#10;
a=0;b=1;c=1;d=0;
#10;
a=0;b=1;c=1;d=1;
#10;
a=1;b=0;c=0;d=0;
#10;
a=1;b=0;c=0;d=1;
#10;
a=1;b=0;c=1;d=0;
#10;
a=1;b=0;c=1;d=1;
#10;
a=1;b=1;c=0;d=0;
#10;
a=1;b=1;c=0;d=1;
#10;
a=1;b=1;c=1;d=0;
#10;
a=1;b=1;c=1;d=1;
#10;
end
endmodule

STIMULATION RESULT:
BCD TO DECIMAL:
 The BCD to Decimal Converter is used to convert a BCD (Binary-
coded decimal) to a decimal (Base-10) integer.
Ex: (0010)2 = (2)10.
(0111)2 = (7)10
 BCD to decimal converter has 3 bcd inputs and a nine decimal
outputs.
 In BCD each bit is represented by a 4 bit binary number.
 BCD also called as 8421 code.
 In BCD to decimal converter 10 to 15 are don’t care conditions .

TRUTH TABLE:

EXPRESSION:

y0=~a&~b&~c&~d;
y1=~a&~b&~c&d;
y2=~a&~b&c&~d;
y3=~a&~b&c&d;
y4=~a&b&~c&~d;
y5=~a&b&~c&d;
y6=~a&b&c&~d;
y7=~a&b&c&d;
y8=a&~b&~c&~d;
y9=a&~b&~c&d;

PROGRAM:

//dut for bcd to decimal

module bcd_decimal(y9,y8,y7,y6,y5,y4,y3,y2,y1,y0,a,b,c,d);
input a,b,c,d;
output y9,y8,y7,y6,y5,y4,y3,y2,y1,y0;
assign y0=~a&~b&~c&~d;
assign y1=~a&~b&~c&d;
assign y2=~a&~b&c&~d;
assign y3=~a&~b&c&d;
assign y4=~a&b&~c&~d;
assign y5=~a&b&~c&d;
assign y6=~a&b&c&~d;
assign y7=~a&b&c&d;
assign y8=a&~b&~c&~d;
assign y9=a&~b&~c&d;
endmodule

//testbench for bcd to decimal

module bcd_decimal_tb;
reg a,b,c,d;
wire y9,y8,y7,y6,y5,y4,y3,y2,y1,y0;
bcd_decimal dut(y9,y8,y7,y6,y5,y4,y3,y2,y1,y0,a,b,c,d);
initial begin
$monitor("a=%b,b=%b,c=%b,d=%b,y9=%b,y8=%b,y7=%b,y6=%b,y5=%b,y4=%b,y3=%
b,y2=%b,y1=%b,y0=%b",a,b,c,d,y9,y8,y7,y6,y5,y4,y3,y2,y1,y0);
{a,b,c,d}=4'b0000;
#5;
{a,b,c,d}=4'b0001;
#5;
{a,b,c,d}=4'b0010;
#5;
{a,b,c,d}=4'b0011;
#5;
{a,b,c,d}=4'b0100;
#5;
{a,b,c,d}=4'b0101;
#5;
{a,b,c,d}=4'b0110;
#5;
{a,b,c,d}=4'b0111;
#5;
{a,b,c,d}=4'b1000;
#5;
{a,b,c,d}=4'b1001;
#5;
end
endmodule

STIMULATION RESULT:

GATE LEVEL MODELLING :

Gate level modelling is virtually the lowest level of abstraction
because the switch-level abstraction is rarely used.Gate level
modelling is used to implement the lowest-level modules in a design,
such as multiplexers, full-adders,etc.
Verilog has a predefined set of logic gates known as
primitives.
Types of primitives : 1. Multiple inputs ==> Single output
ex: and, or, nor, nand, xor, xnor
Syntax: primitive instance_name(output,input1,input2);
2.Single input ==> multiple outputs
ex: buff, not, buff-if1, buf-if0, not-if1, not-if0
Syntax: primitive instance_name(output1,output2,input);
User Defined Premitives :
Gate
Syntax Description
Types
and u0(out, i1,
and Performs AND operation on two or more inputs
i2, …)
or u0(out, i1,
or Performs OR operation on two or more inputs
i2, …)
xor u0(out, i1,
xor Performs XOR operation on two or more inputs
i2, …)
nand u0(out,
nand Performs NAND operation on two or more inputs
i1, i2, …)
nor u0(out, i1,
nor Performs NOR operation on two or more inputs
i2, …)
xnor u0(out,
xnor Performs XNOR operation on two or more inputs
i1, i2, …)
The buffer (buf) passes input to the output as it is. It has
buf buf u0(out, in)
only one scalar input and one or more scalar outputs.
The not passes input to the output as an inverted version. It
not not u0(out, in)
has only one scalar input and one or more scalar outputs.
bufif1 u0(out, It is the same as buf with additional control over the buf
bufif1
in, control) gate and drives input signal only when a control signal is 1.
notif1 u0(out, It is the same as not having additional control over the not
notif1
in, control) gate and drives input signal only when a control signal is 1.
It is the same as buf with additional inverted control over
bufif0 u0(out,
bufif0 the buf gate and drives input signal only when a control
in, control)
signal is 0
It is the same as not with additional inverted control over
notif0 u0(out,
notif0 the not gate and drives input signal only when a control
in, control)
signal is 0.

STRUCTURAL LEVEL MODELLING :

Structural modeling in Verilog is a way of describing a hardware

system using basic components such as digital gates and adders. It is
also called gate level modeling because we only describe a hardware in
logic gates and their inteconnections.
In structural modeling, the programmer or the designer thinks
about the circuit as a box or a module. It is encapsulated from the
outer environment. In other words, it communicates with the outer
environment through inputs and outputs.
INSTANTIATION :
Port mapping in module instantiation can be done in two different
ways:
1. Port mapping by order
2. Port mapping by name

Port mapping by order :

The ports/signals to be coonnected must appear in the module
instantiation in the same order as the ports in the port list of the
module definition.

Port mapping by name :

Verilog provides the capability to connect external signals to
ports by the port names, rather than by position.
For large list of ports in sub module can easily represent by using this
rule.
The dot . indicates that the port name following the dot belongs to the
design.
Signal name to which the design port has to be connected is given
within parentheses ( ).
STRATIFIED EVENT QUEUE (VERILOG REGIONS):

ACTIVE EVENTS:
Events which occur at current stimulation time and can be executed
in any order.
These include:
 Blocking assignments.
 Continuous assignments.
 $display commands.
 The evaluations of non- blocking RHS expressions.
INACTIVE EVENTS:
 Events which are processed after the processing of active events.
 In this queue , #0 delay assignments are scheduled.
NON-BLOCKING ASSIGN UPDATE EVENTS:
 Events that were evaluated during previous stimulation time, but
are assigned at this stimulation time after the processing of active
and inactive events.
 It is these queue the LHS of non- blocking assignment is updated.
MONITOR EVENTS:
 Events that are processed after all the active, in active and non
blocking assign update events have been processed.
 This queue contains $monitor and $strobe assignments.
BEHAVIOUR LEVEL MODELLING :
Behavioural modelling is a higher abstraction in verilog
programming.It is a modelling style that allows the designer to
describe the behaviour and nature of the digital system without
knowing the gate-level design of the circuit.
In verilog, behaviour modelling contains procedural statements
that control the simulation and manipulate the data types of the
variables involved.
PROCEDURAL BLOCKS :
 These are used to group a set of statements together and execute
them sequentially.
 Verilog provides two structured procedural blocks.
1. Initial block
2. Always block
INITIAL BLOCK :
Starts its execution at the beginning of a simulation.The initial
block executes only once.It is a non-synthesizable block.Multiple
initial blocks are valid in a module and each block executes at zero
simulation time. An individual block may finiah their execution
independently.
Nested initial blocks are not valid.It can execute in zero time or
take some time depending on the delay involved.Multiple statements
are enclosed within ‘beign’ and ‘end’ keywords and statements are
executed sequentially.
ALWAYS BLOCK :
Always block is executed sequentially (similar to the initial
block ).Based on changes in the sensitivity list , always block is
executed repeated.
If no sensitivity list is specified, always block executes
repeatedly throughout the simulation.Multiple always blocks are valid
in a module and each block executes independently.
 Nested always blocks are not valid.

=> Use of Procedural blocks :

INITIAL BLOCK ALWAYS BLOCK

1.Initialize variables. 1.To implement

combinational
and sequential elements
in digital circuits.
2.Implementing a testbench code. 2.To model repetitve
activity in a digital design.
ex : Clock generation.
3.Monitoring waveforms and other 3.Used to model
Sequential
processes that are executed only circuits.
once during the entire simulation.
4.Drives ports with soecific values.
5.Used in test benches or to perform
Housekeeping activities that do not
directly affect the design.
SENSITIVITY LIST :
Any signal that is inside always block, which effects the result
will be included in sensitivity list.The sensitivity list can be a single or
multiple signals placed within
Parentheses ( ) after @ operator.
Based on the change in any signal value, it allows executing the
always block.
` * ` is used to represent all inputs instead of writing all inputs.
Need of Sensitivity List :
The always block repeats continuously throughout a simulation.
The sensitivity list brings a certain sense of timing , i.e., whenever any
signal in the sensitivity list changes,the always block is triggered.
If there are no timing control statements within an always block,
the simulation will hang because of a zero-delay infinite loop.
Ex: module adder (cout ,sum,a,b,cin);
input a,b,cin;
output cout,sum;
reg cout,sum;
always @(a or b or cin) // always @( * )
begin
Sum = a^ b^ cin;
Cout = a & b | a & !b & cin | !a & b & cin;
end
endmodule

PROCEDURAL TIMING CONTROL :

 Delay control ( # ).
 Which is introduced by the number symbol.
 Event control ( @ ).
 Which is introduced by AT symbol.
 Wait statement. (combination of while loop and event control).
PROCEDURAL ASSIGNMENTS :
Procedural assignments are employed for updating the memory
variables.These assignments control the flow and keep updating the
new data to the variables (like reg, real, integer or time variable) in the
left-hand side of expression on the sensitivity list.
There are two types of procedural assignments :
1. Blocking and
2. Non-blocking.
We can use both blocking snd non-blocking assignments for reg.
BLOCKING ASSIGNMENT:
Blocking assignments executes in series because a blocking
assignment blocks the execution of next statement until it completes.
 It is denoted with `=`. (a = b)
 Ex-1: a = 1’b1; b = 1’b0;
always @ (posedge clk) begin //sequential circuit
a = b; // o\p : a = 0
b = a; // o\p : b = 0
end
 Ex-2: a = 1’b1; b = 1’b0;
always @ (posedge clk)
a = b;
always @ (posedge clk)
b = a;
//Simulator can choose which always block to executes first
//o\p : either a = b = 0 (or) a = b = 1.

NON- BLOCKING ASSIGNMENT :

Non-blocking assignments executes in parallel because it
describes assignments that all occur at the same time.
It is denoted with `<=`. (a <= b)
Real hardware circuit always acts in parallel.
In non-blocking assignments all the RHS statements are evaluated
first and updated to the left sides.
 Ex-1: a = 1’b1; b = 1’b0;
always @ (posedge clk) begin
a <= b; // o\p : a = 0 ;
b <= a; // o\p : b = 1;
end

 Ex-2: a = 1’b1; b = 1’b0;


always @ (posedge clk)
a <= b; // o\p : a = 0; b = 1;
always @ (posedge clk)
b <= a; // o\p : a = 1; b = 0;
//Simulator can choose which always block to executes first.

=> Difference between Blocking & Non-blocking

Blocking Assignment Non-blocking Assignments

1.Blocking assignments (=) means 1.Non-blocking assignments

evaluate and update immediately. (<=) Means evaluates
immediately but postpones
the update until the other
evaluations in the
same time step has been
completed.
2.These assignments are used for 2.These assignments are
Combinational circuits. used for sequential circuits.
3.Combinational logic will not depend 3.Sequential logic will
upon the clock,so it is written as depend upon the clock,so
always @ (*). it is written as
always @ (posedge clk).

TIMING CONTROL DELAYS:

 There are 3 types of timing control.
1.Delay based
2.Event based
Delay based Timing control :
 Delay is the time taken to evaluates some events.
 If we don’t provide any delay the events would occur at 0 time step
(0 simulation time ).
 # is used to assign delay.
 Delays are not synthesizable.
 There are 3 types of Delay based timing control.
 a.Inter delay
b.Intra delay
c.Zero control delay
d.Gate delay(propagation delay)
e.Rise delay
f.Fall delay
g.Turn-off delay

Inter Delay :

 It is the delay to left of assignment operator.

 Ex: always @ (a or b)
#3 c1 = (a & b); //after 3ns (a & b) evaluated and assigned to
‘c’.
//it doesnot executes at 0ns.

Intra Delay (Wire Delay) :

 It is the delay to right of assignment operator.

 Ex: always @ (a or b)
c1 = #3 ( a & b); //here (a & b) are evaluated immediately (at
0ns) but assigned to ‘c’ after 3ns.
//after 3ns it checks for change,if (a & b)
changes in 3ns, the new value doesnot effect the output
and old value remains.

Zero Control Delay :

 If we write #0 delay in a procedural block then this #0 forces the

procedural block to be executed after all the other blocks are
executed.
 It is a method to ensure that statement is executed last, after all
other statements in that stimulation times are executed.
 If we write #0 in procedural block is called Zero-Control delay.
 Ex-1: Suppose we have two procedural blocks.
initial begin
x = 0; z = 0; //normal assignment
end //after executing first block only then these #0
block will be executed
initial begin
#0 x = 1; //these #0 forces procedural block to be executed
at last
#0 y = 1;
end

 When we don’t know which blocks are executed to know that we

are using zero control delay and to avoid race-arround condition.
 Ex-2: Suppose we have three procedural blocks.
initial begin
x = 0; z = 0; //normal assignment
end //this initial block is executed first.
initial begin
#0 x = 1; //we cannot predit that which blocks executes first
it is #0 y = 1; different from stimulator to stimulator.
end
initial begin
#0 p = 1;
#0 q = 1;
end

Gate Delay (Propagation delay):

Propagation delay is the time taken by output to change its

state after the input changes.The propagation delay depends on
whether the output changes to 1 or 0.

Input changes at time ‘x’ and dependent output changes at

same time later.When the input changes we get updated output at y
but output is not updated at the same time it takes some time update
the output.

Rise Delay(t_rise) :

 Time taken by output to transition from 0,X,Z to logic ‘1’.

Fall Delay (t_fall):

 Time taken by output to transition from 1,X,Z to logic ‘0’.

Turn-Off Delay(t_turn-off) :

 Time taken by gate output to transition from 1,0,X to Z.

3. EVENT BASED CONTROL:

Event is change in the value on a register or net.
 Events can be utilized to trigger execution of a statement (or) a
block of statements.
 TYPES :
i) Regular Event Control
ii) Named Event Control
Regular Event Control (@ ( )):
Statement begin with @ halts the flow into the body of
statement until an event occurs on any of the signal listed inside @ ( )
(so this affects the timing).
 Ex: @ (clock)q = d; //q = d executed when clock changes.
 Ex: @ (posedge clk) q = d; //q = d executed only when clock does
positive transition.
 Ex: @ (posedge clk) d; //d is evaluated immediatedly and
assigned to q at the positive edge of clock.
CONDITIONAL STATEMENTS:
 If-else is called conditional statement because statements are evaluated based on
condition
 If-else generally infers a multiplexer in digital logic.
 The if and if-else statements.
 The case statements.
IF AND IF-ELSE STATEMENTS:

The if and if-else statements are the most common branching

statements.For a multiple statements in if-else, begin and are
necessary so as to avoid incorrect results.
If else generally enforce a multiplexer in digital logic simulator
considers as a multiplexer it is converted into a piece if real hardware.
SYNTAX:
If: if(expression)
Statement;
If-else: if(expression)
statement;
else
statement;
else-if: if(expression)
statement;
else if(expression)
statement;
else
statement;
nested if: if(expression)
statement;
else if(expression)
statement;
else
statement;
else
statement;
PROGRAM:

//DUT
module _4x1_mux(y,s1,s0,i3,i2,i1,i0);
input s1,s0,i3,i2,i1,i0;
output y;
reg y;

always @(*)
begin
if(s1)
if(s0)
y=i3;
else
y=i2;
else
if(s0)
y=i1;
else
y=i0;
end
endmodule

//TESTBENCH
Module tb_4x1_mux;
wire y;
reg s1,s0,i3,i2,i1,i0;
_4x1_mux dut (y,s1,s0,i3,i2,i1,i0);
initial begin
$monitor("time=%d,s1=%b,s0=%b,i3=%b,i2=%b,i1=%b,i0=%b,y=%b",$time,s1
,s0,i3,i2,i1,i0,y);
{s1,s0,i3,i2,i1,i0}=6'b000001;
#5;
{s1,s0,i3,i2,i1,i0}=6'b010010;
#5;
{s1,s0,i3,i2,i1,i0}=6'b100100;
#5;
{s1,s0,i3,i2,i1,i0}=6'b111000;
#5;
end
endmodule
CASE STATEMENT:
Case statement is like an if-else statement that uses identity
operators.The case statement automatically breaks after the first
match.The case statement checks if the given expression matches the
other expressions in the list. It is mostly used to implement
multiplexer type logic.
If no cases match default statement is executed. But default is
optional. So if no default execution will exit the case block without
doing anything.If many conditions are there then if-else may not be a
suitable choice so we use case statement.
SYNTAX:
case(expression)
case value
------------
------------
default statement
endcase

PROGRAM:

//DUT
module case_mux_4x1(y,s,i3,i2,i1,i0);
input i3,i2,i1,i0;
input [1:0]s;
output y;
reg y;
always @ (*)
begin
case(s)
2'b00:y=i0;
2'b01:y=i1;
2'b10:y=i2;
default : y=i3;
Endcase
end
endmodule

//TESTBENCH
module case_mux_4x1_tb;
reg i3,i2,i1,i0;
reg [1:0]s;
wire y;
//instantiation
case_mux_4x1 dut (y,s,i3,i2,i1,i0);
initial begin
$monitor("s=%b,i3=%b,i2=%b,i1=%b,i0=%b, y=%b",s,i3,i2,i1,i0,y);
s=2'b00; {i3,i2,i1,i0}=4'b0001;
#5;
s=2'b01; {i3,i2,i1,i0}=4'b0010;
#5;
s=2'b10; {i3,i2,i1,i0}=4'b0100;
#5;
s=2'b11; {i3,i2,i1,i0}=4'b1000;
#5;
end
endmodule

IF ELSE VS CASE STATEMENT:

 There is no difference - performance wise. They are equally

efficient.
 Case is useful when output depends on large number of
conditions.
 But if the no.of conditions are very small (2 or 3) then use if----
else if-----if.
 Both infers multiplexer in digital logic.
CASEX STATEMENTS:

 In casex statements , the simulator does not compare a bit

position having a Z or X values.
 Casex ignores any bit position containing an X or Z ; casez only
ignores bit positions with a Z.
PROGRAM:

// DUT
module priorityencoder83(d,y);
input [7:0]d;
output [2:0]y;
reg [2:0]y;
always@(*)
begin
casex(d)
8'b1xxx_xxxx: y=3'b111;
8'b01xx_xxxx: y=3'b110;
8'b001x_xxxx: y=3'b101;
8'b0001_xxxx: y=3'b100;
8'b0000_1xxx: y=3'b011;
8'b0000_01xx: y=3'b010;
8'b0000_001x: y=3'b001;
default: y=3'b000;
endcase
end
endmodule

//TESTBENCH
module priorityencoder83_tb;
reg [7:0]d;
wire [2:0]y;
priorityencoder83 dut(d,y);
initial begin
$monitor("d=%0b -> y=%0b",d,y);
repeat(5)
begin
d=$random; #1;
end
end
endmodule

STIMULATION RESULT:
CASEZ STATEMENTS:
 The casez statements, the simulator does not compare a bit
position having a Z value.
PROGRAM:

//DUT
module casex_ex(a,b,c,d);
input [3:0] a,b,c,d;
output [3:0] y;
always@ (a or b or c or d)
casez(d)
4’b0000: y=a;
4’b0??1: y=b;
4’b111?: y=c;
4’b???1: y=c;
default: 4’b0000;
endcase
endmodule

//TESTBENCH
module casex_ex_tb;
reg [3:0] a,b,c,d;
wire y;
//instantiation
casex_ex dut (a,b,c,d,y);
initial begin
$monitor("a=%b, b=%b, c=%b,d=%b, y=%b",a,b,c,d,y);
{i3,i2,i1,i0}=4'b0001;
#5;
{i3,i2,i1,i0}=4'b0010;
#5;
{i3,i2,i1,i0}=4'b0100;
#5;
{i3,i2,i1,i0}=4'b1000;
#5;
end
endmodule
PARAMETRES:
Parameters are verilog constructs that allow a module to be
reused with a different specification. They are like arguments to a
function that are passed in during a function call. Parameters are
constants and do not belong to any other data type
we cannot modify parameter values at runtime , we can modify
only at the compilation time. Verilog allows changing parameter
values during compilation time using the ‘defparam’ keyword. The
‘defparam’ is used as overriding the parameter value using a
hierarchical name of the module instance.
For example, a 4- bit adder can be parameterized to accept a
value for the number of bits and new parameter values can be passed
in during module instantiation. So an N-bit adder can be become a 4-
bit , 8-bit (or) 16-bit adder.
SYNTAX:
Module <module_name> #(<parameter list>) <port_list>;
The parameter value can be updated in two ways:
 By using module instance statement.
 By using defparam statement.
Defparam:
 Defparam is a verilog construct used to set the new parameter
values.
 It is used in test bench simulations to quickly update the design
parameters without having to re instantiate the module.
Example: Parameter using ripple carry adder
 To design N bit parameter using ripple carry adder we need 4 bit
full adder.
PROGRAM: parameter RCA
//dut for full adder
module fa(a,b,cin,s,cout);
input a,b,cin;
output s,cout;
assign s=a^b^cin;
assign cout=((a&b)|(b&cin)|(a&cin));
endmodule

// dut for parameterRCA

module rca4bitparam(a,b,cin,s,cout);
parameter N=4;
input [N-1:0]a,b;
input cin;
output[N-1:0]s;
output cout;
wire[N:0]carry;
wire c0,c1,c2;
assign carry[0]=cin;
generate
genvar i;
for(i=0;i<N;i=i+1)
begin
fa fa1(a[i],b[i],carry[i],s[i],carry[i+1]);
end
endgenerate
assign cout=carry[N];
endmodule

//testbench for parameterRCA

module rca4bitparam_tb;
parameter N=4;
reg[N-1:0]a,b;
reg cin;
wire cout;
wire [N-1:0]s;
rca4bitparam dut(a,b,cin,s,cout);
initial begin
repeat(50)
begin
{a,b,cin}=$random;
#1;
$display("$time=%0t,a=%0b,b=%0b,cin=%0b,s=%0b,cout=%0b",$time,a,b,cin,s,cout);
end
end
endmodule
STIMULATION RESULT:

VERILOG GENERATE BLOCK:

A generate block is a verilog construct that allows to multiply
module instances (or) perform conditional instantiation of any module.
It provides the ability for the design to be built based on verilog
parameters. A generate block cannot contain port (or) specify blocks,
other module items and other blocks are allowed.
All generate instantiation are coded within a module and
between the keywords generate and end generate. Generate
instantiations can have either modules , continuous assignments ,
always (or) initial blocks and user defined primitives.
Methods to write generate statements:
1. Generate loop
2. Generate conditional (includes generate if-else and generate
case).

GENERATE LOOP:
 The generate loop is similar to the for loop statement, but it uses
genvar keyword as a loop variable
 The genvar keyword is only used during the evaluation of generate
block and does not exist during the simulation of the design. It
needs to be used by a generate loop.
 Generate loop provides flexibility to reduce code lines by replacing
repetitive statements to a single statement like for loop.
 Similar to a for loop, generate loops also can be nested with
different genvar as an index variable.

ALWAYS BLOCK INSIDE GENERATE BLOCK:

genvar k;
generate
for (k = 0; k < 4; k++) begin
always@(posedge clk) begin
val[k] = a[k] & b[k];
end
end
endgenerate
FUNCTION AND TASK:
A function or task is a group of statements that performs some
specific action. Both of them can be called at various points to
perform a certain operation. They are also used to break large code
into smaller pieces to make it easier to read and debug. The main
function of task and function is reuse ability.
VERILOG FUNCTION:
In verilog, a function is a subprogram which takes one or more
input values, performs some calculation and returns an output value.
A function that does not consume simulation time, returns a single
value or an expression, and may or may not take arguments.
A function is defined within a module definition and within
function and endfunction keywords, but without a port list. Function
by default returns a scalar reg, but you can size or type the function
definition.The main purpose of the function is to return a value that is
to be used in an expression.
A functions definition always start with the keyword function
and ends with the keyword endfunction. A function can contain only
one statement. Group multiple statements with the begin - end
keywords.
Syntax:
function <return _type> <name>;
(input <arguments>);
begin
//function code
end
endfunction

FUNCTION RULES:
 A function cannot contain any time - controlled statements like
#,@, wait, posedge, negedge.
 A function cannot start a task because it may consume simulation
time, but can call another functions and returns only one value.
 A function should have at least one input.
 A function cannot have any triggers.
Example program for function:

module comb15( A,B,CIN,S,COUT);

input[3:0]A,B;
input CIN;
output[3:0]S;
output COUT;
wire[1:0] S0,S1,S2,S3;
assign S0=ADD ( A[0],B[0],CIN),
S1=ADD ( A[1],B[1],S0[1]),
S2=ADD ( A[2],B[2],S1[1]),
S3=ADD ( A[3],B[3],S2[1]),
S={S3[0],S2[0],S1[0],S0[0]}, COUT=S3[1];
function [1:0] ADD;
input A,B,CIN;
reg S,COUT;
begin
S=A^B^CIN;
COUT =(A&B) | (A&CIN) | (B&CIN);
ADD = {COUT,S};
end
endfunction
endmodule

VERILOG TASK:

We use verilog tasks to write small sections of code we can

reuse throughout the design.A task is used to calculate multiple
results values and return them using output and inout type statement.
Task can contain simulation time consuming elements such as
@,#,wait, posedge ect.We can use both blocking and non - blocking
assignments. We can call another task from within a task, we can also
make calls to functions from within a task.
 A task is defined within a module definition.
 It is defined Within task and and endtask keywords , but without
port list
 A task can have input, output, and inout ports.
 A task can contain only one statement.
 Group multiple statements with the begin - end or fork - join
keywords.
Syntax:
task [name];
input [port_list];
inout [port_list];
output [port_list];
begin
//statements
end
endtask

Example program for task:

module example(A,B,CIN,S,COUT);
input [3:0] A,B;
input CIN;
output reg[3:0]S;
output reg COUT;
reg c1,c2,c3;

always @(A or B or CIN)

begin
ADD(A[0],B[0],CIN,S[0],c1);
ADD(A[1],B[1],C1,S[1],c2);
ADD(A[2],B[2],C2,S[2],c3);
ADD(A[3],B[3],C3,S[3],COUT);
end

task ADD;
input A,B,CIN;
output s,cout;
begin
S = A^B^CIN;
COUT= (A&B)|(A&CIN)|(B&CIN)
end
endtask
endmodule
CODES FOR SEQUENTIAL CIRCUIT:
FLIPFLOPS:
 A flip-flop is a sequential digital electronic circuit having two
stable states that can be used to store one bit of binary data.
 Flip-flops are the fundamental building blocks of all memory
devices.
TYPES OF FLIPFLOPS:
1) SR flip flop.
2) JK flip flop.
3) D flip flop
4) T flip flop
JK FLIPFLOP:
 The JK flip flop is used to remove the drawback of the S-R flip flop,
i.e., undefined states.
 The JK flip flop is formed by doing modification in the SR flip flop.
 When S and R input is set to true, the SR flip flop gives an
inaccurate result. But in the case of JK flip flop, it gives the correct
output.
 When the input J and K are different then the output Q takes the
value of J at the next clock edge.
 When J and K both are low then NO change occurs at the output.
 If both J and K are high, then at the clock edge, the output will
toggle from one state to the other.
LOGIC DIAGRAM:

TRUTH TABLE:

Program:
//dut for jk flipflop
module jk_ff(j,k,clk,q);
input j,k,clk;
output q;
reg q;
always@(posedge clk)begin
case({j,k})
2'b00 : q<=q;
2'b01 : q<=1'b0;
2'b10 : q<=1'b1;
default q<=~q;
endcase
end
endmodule
// test bench for jk flipflop
module jk_ff_tb;
reg j,k,clk;
wire q;
jk_ff dut(j,k,clk,q);
always #5 clk<=~clk;
initial begin
$monitor("$time=%0t,j=%0b,k=%0b,q=%0b",$time,j,k,q);
clk=0;
j<=0;k<=0;
#5;
j<=0;k<=1;
#5;
j<=1;k<=0;
#5;
j<=1;k<=1;
#5;
end
endmodule

STIMULATION RESULT:
D FLIPFLOP:
 D flip flop is an electronic devices that is known as “delay flip flop”
or “data flip flop” which is used to store single bit of data.
 The D flip flop has two inputs, data and clock input which
controls the flip flop.
 when clock input is high, the data is transferred to the output of
the flip flop.
 when the clock input is low, the output of the flip flop is held in
its previous state.
LOGIC DIAGRAM:

TRUTH TABLE:
REGISTERS:
Flip flops can be used to store a single bit of binary data (1 or
0). However, in order to store multiple bits of data, we need multiple
flip-flops. N flip flops are to be connected in order to store n bits of
data.
A Register is a device that is used to store such information.
It is a group of flip-flops connected in series used to store multiple
bits of data. The information stored within these registers can be
transferred with the help of shift registers.
SHIFT REGISTERS:
 Shift Register is a group of flip flops used to store multiple bits of
data.
 An n-bit shift register can be formed by connecting n flip-flops
where each flip-flop stores a single bit of data.
 The registers which will shift the bits to the left are called “Shift
left registers”.
 The registers which will shift the bits to the right are called “Shift
right registers”.

TYPES OF SHIFT REGISTERS:

 Serial In Serial Out shift register
 Serial In parallel Out shift register
 Parallel In Serial Out shift register
 Parallel In parallel Out shift register
 Bidirectional Shift Register
 Universal Shift Register

SERIAL IN SERIAL OUT (SISO)

 The shift registers which allows serial input and produces serial
output.
 There is only one output so data leaves the shift register one bit
at a time in a serial pattern.
 The circuit consists of four D flip-flops which are connected in a
serial manner. All these flip-flops are synchronous with each
other since the same clock signal is applied to each flip-flop.

BLOCK DIAGRAM:

TRUTH TABLE:

SERIAL IN PARALLEL OUT (SIPO)

 The shift register which allows serial input and produces parallel
output.

 The circuit consists of four D flip-flops which are connected .

 The output of the first flip-flop is connected to the input of the

next flip flop and so on.
BLOCK DIAGRAM:

PROGRAM:

//dut for SIPO register

module sipo(clk,rst,si,po);
input clk,rst,si;
output reg [3:0]po=0;
always@(posedge clk)
begin
po[3]<=si;
po[2]<=po[3];
po[1]<=po[2];
po[0]<=po[1];
end
endmodule

//testbench for SIPO register

module sipo_tb;
reg clk,rst,si;
wire [3:0]po;
sipo dut(clk,rst,si,po);
always #5clk=~clk;
initial begin
$monitor("si=%0b,po=%0b",si,po);
clk=0;
si=1;
#10;
si=1;
#10;
si=1;
#10;
si=1;
#10;
end
initial begin
rst=1'b1;
#3;
rst=1'b0;
end
endmodule

STIMULATION RESULT:

PARALLEL IN SERIAL OUT:

 A shift register which allows only parallel inputs and produces
serial outputs.
 Shift/Load by using these signals we are performing load and shift
operation.
 These entire circuit is operated in 2 modes they are load and shift.
 LOAD: The data inputs are loaded into shift registers.
SHIFT: In shift mode the data base loaded into the shift
register using load mode that are to be shifted
towards right one bit at a time.

BLOCK DIAGRAM:

PARALLEL IN PARALLEL OUT (PIPO):

 The shift register which allows parallel input and parallel out.
 The inputs A0, A1, A2, and A3, are directly passed to the data
inputs D0, D1, D2, and D3 of the respective flip flop.

BLOCK DIAGRAM:
PROGRAM:

// dut for PISO register

module pipo(clk,rst,pi,po);
input clk,rst;
input [3:0]pi;
output reg[3:0]po=0;
always@(posedge clk)
begin
po<=pi;
end
endmodule

// testbench for PIPO register

module pipo_tb;
reg clk,rst;
reg [3:0]pi;
wire [3:0]po;
pipo dut(clk,rst,pi,po);
initial begin
$monitor("pi=%0b,po=%0b",pi,po);
clk=0;
pi=0;
#50;
pi=4'b1000;
end
initial begin
rst=1'b1;
#3;
rst=1'b0;
end
initial begin
forever #5 clk=~clk;
end
initial begin
#200 $finish;
end
endmodule
STIMULATION RESULT:

UNIVERSAL SHIFT REGISTER:

 When we have bi directional and parallel loading then that register

is known as Universal shift register.
 We are using 4x1 mux and 2 select line’s are connected to all 4
registers.
 The universal shift register can store the data in parallel and can
transmit the data in parallel.
 In the same manner the data can stored and transmitted by serial
path through shift left and shift right operations.
LOGIC DIAGRAM:

TABLE:

OPERATION:

 When S0 = 0 and S1 = 0, then the universal shift register will be in

locked state, that means no operation will be performed.
 When S0 = 1 and S1 = 0, then it will shift the data to right, that is
shift right operation is performed.
 When S0 = 0 and S1 = 1, then it will shift the data to right, that is
shift left operation is performed.
 When S0 = 0 and S1 = 0, then the register results in PARALLEL
LOAD operation.
PROGRAM:

//dut for Universal register

module universal(q,clk,rst,s,din);
input clk,rst;
input [1:0]s;
input [3:0]din;
output reg[3:0]q;
always@(posedge clk)
begin
if(rst)
q<=0;
else
if (s[1]==0 && s[0]==0)
begin
q<=q;
end
if (s[1]==0 && s[0]==1)
begin
q<=q>>1;
end
if (s[1]==0 && s[0]==0)
begin
q<=q<<1;
end
if (s[1]==0 && s[0]==0)
begin
q<=din;
end
end
endmodule

//testbench for universal register

module universal_tb;
reg clk,rst;
reg [1:0]s;
reg [3:0]din;
wire [3:0]q;
universal dut(q,clk,rst,s,din);
always#5clk=~clk;
initial begin
$monitor("q=%0b,s=%0b,din=%0b",q,s,din);
clk=1;rst=0;
#5;
rst=1;
din=4'b0000;
/*#10; din = 4'b1111;
 #10; s = 2'b11;
#10; s = 2'b01;
#10; s = 2'b10;
#10; s = 2'b00;
#10;
din = 4'b1010;
#10;*/
repeat(5)
begin
#5;
din=$random;
#5;
s=$random;
end
end
endmodule

STIMULATION RESULT:
COUNTERS:
Counter is used to count pulses and it can be used as frequency
divider.Counters are wide applications of flipflops.A counter circuit is
usually constructed of several flipflops connected in a cascade.
Counters are used in digital electronics for counting purpose,
they can count specific event happening in the circuit.The main
properties of a counter are timing , sequencing , and counting.
Counters operates in three modes:
 Up counter
 Down counter
 Up / down counter
CLASSIFICATION OF COUNTER:
 Asynchronous counter.
 Synchronous counter.
ASYNCHRONOUS COUNTER:
The Asynchronous counter is also known as the ripple
counter. In asynchronous counter we don’t use universal clock, only
first flip flop is driven by main clock and the clock input of rest of the
following flip flop is driven by output of previous flip flops.The
transition of the first stage ripples till the last flip-flop stage.
Hence, it is also known as the “Ripple Counter”.It is also called
as serial counter.In the asynchronous counter, individual flip-flop
stages are triggered with the different clocks. Due to this, it is slower
when compared with a synchronous counter.
SYNCHRONOUS COUNTER:

synchronous counter has one clock which drives each flip flop
so output changes in parallel. It is also called as parallel counter.
The clock signals produced by all the flip flops are the same as each
other.
Synchronous counter operates fastly.Johnson and ring counters
are examples of synchronous counters.In synchronous counter
counting is not fixed.Speed is high compared to asynchronous counter.
MOD - N COUNTER:
Modulus Counters, or MOD counters, are defined based on the
number of states that the counter will sequence before returning to its
original value.Therefore, a "Mod-N" counter will require the "N"
number of flip-flops connected to count a single data bit while
providing 2n different output states (n is the number of bits).
Note that N is always a whole integer value.
If there are only two bits ( n = 2 ) then the maximum number of
possible output states (maximum modulus) for the counter is 2n =
22 or 4.However, counters can be designed to count to any 2n states
in their sequence by cascading together multiple counting stages to
produce a single modulus or MOD-N counter.
TYPES OF MOD COUNTERS:
 2-bit counter is called as mod -4.
 3-bit counter is called as mod-8.
 MOD - N counter is called as modulus of the counter.

Example: mod-10 counter

Program:
//dut for mod10counter
module mod10coun(clk,rst,count); //bcd counter , decade counter
input clk,rst;
output reg [3:0]count;
always@(posedge clk)
begin
if(rst==1 || count==9)
count<=0;
else
count= count+1;
end
endmodule
//testbench for mod10counter
module mod10coun_tb;
reg clk,rst;
wire [3:0]count;
mod10coun dut(clk,rst,count);
always#5clk=~clk;
initial begin
$monitor("$time=%0t,count=%0b",$time,count);
clk=0;
#5;
rst=1;
#5;
rst=0;
end
endmodule

STIMULATION RESULT:

RING COUNTER:
 Ring counter is a typical application of shift register.
 The only change is output of last flipflop is connected to input to
first flipflop.
 we use 4 D flip flops. The same clock pulse is passed to the clock
input of all the flip flops as a synchronous counter.
number states in a ring counter = number of flipflops .

LOGIC DIAGRAM:

 The Overriding input(ORI) is used to design this circuit.

 The Overriding input is used as clear and pre-set.
 Output is ‘1’ when preset is set ‘0’ and the output is ‘0’ when the
clear set to ‘0’.

PR=0, Q=1

CLR=0 , Q=1

WORKING:
 The ORI input is passed to the PR input of the first flip flop, i.e.,
FF-0, and it is also passed to the clear input of the remaining
three flip flops, i.e., FF-1, FF-2, and FF-3.
 The pre-set input set to 0 for the first flip flop. So, the output of
the first flip flop is one, and the outputs of the remaining flip flops
are 0.
 The output of the first flip flop is used to form the ring in the ring
counter and referred to as Pre-set 1.
TRUTH TABLE:

 A ring forms when the pre-set 1 is shifted to the next flip-flop at

each clock pulse.

 For 4- bit counter to return value it takes 4 states.

1000
0100
0010
0001

PROGRAM:
// dut for ring counter
module ringcounter(clk, rst,count);
parameter N=4; //using parameter
input clk,rst;
output reg[N-1:0]count;
always@(posedge clk)
begin
if(rst)
count<=4'b0001;
else
count<={count[0],count[N-1:1]};
end
endmodule

// test bench for ring counter

module ringcounter_tb;
parameter N=4;
reg clk,rst;
wire [N-1:0]count;
ringcounter dut(clk,rst,count);
always#5clk=~clk;
initial begin
$monitor("$time=%0t,clk=%0b,rst=%0b,count=%0b",$time,clk,rst,count);
clk=0;
#5;
rst=1;
#5;
rst=0;
#5;
end
endmodule

STIMULATION RESULT:

JOHNSON COUNTER :
 The Johnson counter is similar to the Ring counter.
 The only difference between the Johnson counter and the ring
counter is that the outcome of the last flip flop is passed to the
first flip flop as an input.
 In Johnson counter, the inverted outcome Q' of the last flip flop is
passed as an input.
 Johnson counter is called creeping counter.

NO.Of states in johnson counter = no.of flipflops

Number of used states = 2n
Number of unused states=2n-2*n.

 Four D flip flops are used in the 4-bit Johnson counter, and the
same clock pulse is passed to all the input of the flip flops.
LOGIC DIAGRAM:

TRUTH TABLE:

PROGRAM:

//dut for johnson counter

module johnson(clk,rst,q);
input clk,rst;
output reg[3:0]q;
always@(posedge clk)
begin
if(rst)
q=4'b0;
else
begin
q[3]<=q[2];
q[2]<=q[1];
 q[1]<=q[0];
q[0]<=~q[3];
end
end
endmodule

//test bench for johnson counter

module johnson_tb;
reg clk,rst;
wire [3:0]q;
johnson dut(clk,rst,q);
always#5clk=~clk;
initial begin
$monitor("$time=%0t,clk=%0b,rst=%0b,q=%0b",$time,clk,rst,q);
clk=0;
#5;
rst=1;
#5;
rst=0;
end
Endmodule

STIMULATION RESULT:
DECADE COUNTER(MOD 10):
 A binary coded decimal (BCD) is a serial digital counter that
counts ten digits and it resets for every new clock input.
 As it can go through 10 unique combinations of output, it is also
called as “Decade counter”.
 A BCD counter can count 0000, 0001, 0010, 1000, 1001, 1010,
1011, 1110, 1111, 0000, and 0001 and so on.

BLOCK DIAGRAM:

TRUTH TABLE:
MEMORIES:
Memory is the faculty of the brain by which data (or)
information is encoded , stored and retrieved when needed.Memories
are digital storage elements, that helps to store data and information
in digital circuits.Memory is the most essential element of a
computing system.
Basically each memory cells have either ‘1’ or ‘0’.The memory is
divided into large number of small parts called cells.Each location (or)
cell has a unique address.Memory is an internal storage area in a
computer, which is used to store data and programs either
permanently (or) temporarily.

READ ONLY MEMORY:

 ROM is a non volatile memory.

 The name itself indicates that we can read data from a ROM, but it
cannot be modified or written after it has been programmed.
 The structure of ROM is basically made up of decoder and or gates.
 Information stored in ROM is permanent.

ROM SIZE:

2X X Y

x = number of inputs
Y = number of outputs
Internal Structure of ROM
The internal structure of ROM have two basic components.
 Decoder
 OR gates

 A circuit known as a decoder converts an encoded form, such

as binary coded decimal, or BCD, into a decimal form.
 As a result, the output is the binary equivalent of the input. The
outputs of the decoder will be the output of every OR gate in the
ROM.
 Let’s use a 64 x 4 ROM as an example. This read-only memory
has 64 words with a 4 bit length.
 As a result, there would be four output lines. Since there are only
six input lines and there are 64 words in this ROM, we can
specify 64 addresses or minimum terms by choosing one of the
64 words that are available on the output lines from the six input
lines. Each address entered has a unique selected word.
PROGRAM:

//dut for ROM

module rom_tb;
reg clk,rst;
reg [2:0]addr;
wire [7:0]dout;
rom dut(dout,clk,rst,addr);
always#5clk=~clk;
initial begin
$monitor("dout=%0b,addr=%0b",dout,addr);
clk=1;rst=0;
addr=0;
#10;
addr=1;
#5;
addr=2;
#5;
addr=3;
#5;
addr=4;
#5;
addr=5;
#5;
addr=6;
#5;
addr=7;
end
endmodule

//testbench for ROM

module rom_tb;
reg clk,rst;
reg [2:0]addr;
wire [7:0]dout;
rom dut(dout,clk,rst,addr);
always#5clk=~clk;
initial begin
$monitor("dout=%0b,addr=%0b",dout,addr);
clk=1;rst=0;
addr=0;
#10;
addr=1;
#5;
addr=2;
#5;
addr=3;
#5;
addr=4;
#5;
addr=5;
#5;
addr=6;
#5;
addr=7;
end
Endmodule

STIMULATION RESULT:

RAM:
 RAM, which stands for Random Access Memory.
 RAM is a volatile memory, which means it does not store data or
instructions permanently.
 RAM is the main memory in a computer , it is must faster to read
and write .
BLOCK DIAGRAM:

 A RAM has a data bus form which we can access content from the
RAM or we can put a content on this, and if we give write
command to the RAM it will write RAM with the content on the
data bus.
 RAM has lots of addresses and these addresses can be accesssed
by the address bus.
 Other than data and address bus, RAM has one more input
read/write.
 If the r/w is high , the content at data bus is written to the
address provided to the RAM from address bus else the content of
the address provided by address bus is reflected to the data bus.

PROGRAM:

//dut for RAM

module ram1(dout,addr,din,clk,rst,wr);
input [3:0]addr;
input [7:0]din;
input clk,rst,wr;
output reg[7:0]dout;
reg[7:0]mem[15:0];
always@(posedge clk)
begin
if(rst)
dout<=0;
 else
begin
if(wr)
mem[addr]<=din;
else
dout<=mem[addr];
end
end
endmodule

//test bench for RAM

module ram1_tb;
reg [3:0]addr;
reg [7:0]din;
reg clk,rst,wr;
wire[7:0]dout;
ram1 dut(dout,addr,din,clk,rst,wr);
always#2clk=~clk;
initial begin
rst=1;clk=0;
wr=0;
#10;
rst=0;
wr=1;
//@(posedge clk) wr=1;
addr=4'b0000; din=8'b01010010;
#5;
addr=4'b0001; din=8'b01110010;
#5;
addr=4'b0010; din=8'b11010010;
#5;
addr=4'b0011; din=8'b01011110;
#5;
addr=4'b0100; din=8'b11010011;
#5;
addr=4'b0101; din=8'b01010011;
#5;
addr=4'b0110; din=8'b01011010;
#5;
addr=4'b0111; din=8'b01110010;
#5;
wr=0;
addr=4'b0000;
#5;
addr=4'b0100;
#5;
addr=4'b0010;
#5;
addr=4'b0001;
#5;
addr=4'b0111;
#5;
#1000;
$finish;
end
endmodule

STIMULATION RESULT:

Fig RAM
FINITE STATE MACHINE (FSM):

Finite state machine is used to recognize patterns.Synchronous

sequential circuits change effect there states for every positive or
negative transition of the clock signal based on the input.

So, this behavior of synchronous sequential circuits can be

represented in the graphical form and it is known as state diagram.A
synchronous sequential circuit is also called as Finite State
Machine(FSM) it has finite number of states.

There are two types of FSM’s.

 MEALY STATE MACHINE.

 MOORE STATE MACHINE.

SEQUENCE DETECTOR:

Both Mealy and Moore machines can be used to design sequence

detector logic. Further, these machines are classified as

1. Overlapping sequence detector – Final bits of the sequence can

be the start of another sequence. Thus, it allows overlap.
2. Non-overlapping sequence detector – Once sequence detection is
completed, another sequence detection can be started without any
overlap.

MEALY STATE MACHINE:

A Finite State Machine is said to be Mealy state machine, if

outputs depend on both present inputs & present states.There are two
parts present in Mealy state machine they are combinational logic
and memory. Memory is useful to provide some or part of previous
outputs present states as inputs of combinational logic.
 So, based on the present inputs and present states, the Mealy
state machine produces outputs. The outputs will be valid only at
positive or negative transition of the clock signal.

STATE DIAGRAM:

In the above figure, there are three states, namely A, B & C.

These states are labelled inside the circles & each circle corresponds
to one state. Transitions between these states are represented with
directed lines. Here, 0 / 0, 1 / 0 & 1 / 1 denotes input / output.In
the above figure, there are two transitions from each state based on
the value of input, x.

In general, the number of states required in Mealy state

machine is less than or equal to the number of states required in
Moore state machine. There is an equivalent Moore state machine for
each Mealy state machine.Both Mealy and Moore machines can be
used to design sequence detector logic.
MOORE STATE MACHINE:

A Finite State Machine is said to be Moore state machine, if

outputs depend only on present states. There are two parts present in
Moore state machine they are combinational logic and memory.

In this case, the present inputs and present states determine

the next states. So, based on next states, Moore state machine
produces the outputs. Therefore, the outputs will be valid only after
transition of the state.

In the above figure, there are four states, namely A, B, C & D.

These states and the respective outputs are labelled inside the circles.
Here, only the input value is labeled on each transition. In the above
figure, there are two transitions from each state based on the value of
input, x.In general, the number of states required in Moore state
machine is more than or equal to the number of states required in
Mealy state machine. There is an equivalent Mealy state machine for
each Moore state machine. So, based on the requirement we can use
one of them.