filename: uat1.

vhd, last modified: 2023-1216

-- --------------------------------------------------------------------
-- some GHDL-cmds: ghdl -s xxx.vhd : Syntax check
-- ghdl -a xxx.vhd : Assembles file xxx.vhd
-- ghdl -e xyz : Elaborates xyz, no packages
-- prepare waveform: ghdl -r xxx_TB1 --wave=xxx_TB1_wave.ghw
-- --------------------------------------------------------------------
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE WORK.top_pack.ALL;
-- --------------------------------------------------------------------
ENTITY uat1 IS
PORT (rb_i : IN STD_LOGIC; -- reset, active low
cp_i : IN STD_LOGIC; -- Syscp, 12MHz
br_i : IN STD_LOGIC; -- Baudrate, 9k6
d_i : IN STD_LOGIC_VECTOR(23 DOWNTO 0);
dv_i : IN STD_LOGIC; -- Data Byte is valid
txd_o : OUT STD_LOGIC; -- Serial out, to RS232
tld_o : OUT STD_LOGIC); -- used as trigger
END uat1;
-- --------------------------------------------------------------------
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE WORK.top_pack.ALL;
-- --------------------------------------------------------------------
-- --------------------------------------------------------------------
ARCHITECTURE a1 OF uat1 IS
-- --------------------------------------------------------------------
--FOR ALL : a1x_c05xc USE ENTITY WORK.c05xc (a1);
--FOR ALL : a2x_c05xc USE ENTITY WORK.c05xc (a2);
-- --------------------------------------------------------------------
SIGNAL clr_s : STD_LOGIC; -- clear, via fsm
SIGNAL nxt_s : STD_LOGIC; -- inc via fsm
SIGNAL nxbyte_s : STD_LOGIC; -- next byte
SIGNAL dne_s : STD_LOGIC; -- last byte done
SIGNAL db_s : STD_LOGIC_VECTOR(7 DOWNTO 0); -- byte
SIGNAL adr_byts_s : STD_LOGIC_VECTOR(3 DOWNTO 0); -- select byte adr
SIGNAL adr_bits_s : STD_LOGIC_VECTOR(3 DOWNTO 0); -- select bit adr
SIGNAL txd_s : STD_LOGIC; -- serial data out
SIGNAL xxx_s : STD_LOGIC; -- all done
-- --------------------------------------------------------------------
BEGIN
-- --------------------------------------------------------------------
-- Select one of the nibbles, convert to ASCII, provide CR and LF
-- --------------------------------------------------------------------
WITH adr_byts_s SELECT
db_s <= '0'&'0'&'1'&'1'&d_i(23)&d_i(22)&d_i(21)&d_i(20) WHEN "0000",
'0'&'0'&'1'&'1'&d_i(19)&d_i(18)&d_i(17)&d_i(16) WHEN "0001",
'0'&'0'&'1'&'1'&d_i(15)&d_i(14)&d_i(13)&d_i(12) WHEN "0010",
'0'&'0'&'1'&'1'&d_i(11)&d_i(10)&d_i( 9)&d_i( 8) WHEN "0011",
'0'&'0'&'1'&'1'&d_i( 7)&d_i( 6)&d_i( 5)&d_i( 4) WHEN "0100",
'0'&'0'&'1'&'1'&d_i( 3)&d_i( 2)&d_i( 1)&d_i( 0) WHEN "0101",
B"0000_1101" WHEN "0110",
B"0000_1010" WHEN "0111",
B"0011_1111" WHEN OTHERS;
-- --------------------------------------------------------------------
-- Make frame (idle,start-bit,8-data-bits,two stop-bits,idle..
-- --------------------------------------------------------------------
WITH adr_bits_s SELECT
txd_s <= '1' WHEN "0000", -- when idle
'0' WHEN "0001", -- start-bit
db_s(0) WHEN "0010", -- ASCII-d0, LSB
db_s(1) WHEN "0011", -- ASCII-d1
db_s(2) WHEN "0100", -- ASCII-d2
db_s(3) WHEN "0101", -- ASCII-d3
db_s(4) WHEN "0110", -- ASCII-d4
db_s(5) WHEN "0111", -- ASCII-d5
db_s(6) WHEN "1000", -- ASCII-d6
db_s(7) WHEN "1001", -- ASCII-d7, MSB
'1' WHEN OTHERS; -- Stop-Bits
-- --------------------------------------------------------------------
ubits_adr: c16eqc PORT MAP (rb_i,cp_i, -- counts bits 8N2
nxt_s,clr_s, -- ena and clear
adr_bits_s,nxbyte_s); -- sel 8N2-bits
ubyte_adr: c16eqc PORT MAP (rb_i,cp_i, -- counts bytes
nxbyte_s,clr_s, -- ena and clear
adr_byts_s,xxx_s); -- selects bytes
dne_s <= adr_byts_s(3);
-- --------------------------------------------------------------------
uufsm : fsm1 PORT MAP
 (rb_i, -- Primary Input, Reset, active low
cp_i, -- Primary Input, Syscp, @ 12MHz
dv_i, -- to fsm, new reg8-data
br_i, -- to fsm, Baudrate to ena Counter
dne_s, -- to fsm, last Bit transmitted
clr_s, -- from fsm, clear Bit-Counter
nxt_s); -- from fsm, next Bit, inc count

txd_o <= txd_s; -- serial data out, TTL, 8N2,9k2

tld_o <= txd_s; -- same as txd_o
-- --------------------------------------------------------------------
END a1;