EXPT.

NO: 01 VERIFICATION OF BOOLEAN THEOREMS USING

DATE: DIGITAL LOGIC GATES

AIM:
To verify the Boolean Theorems using logic gates.

APPARATUS REQUIRED:

SL. NO. COMPONENT SPECIFICATION QTY.

1. AND GATE IC 7408 1
2. OR GATE IC 7432 1
3. NOT GATE IC 7404 1
4. IC TRAINER KIT - 1
As per
5. CONNECTING WIRES - required

THEORY:

BASIC BOOLEAN LAWS

1. Commutative Law
The binary operator OR, AND is said to be commutative if,
1. A+B = B+A
2. A.B=B.A

2. Associative Law
The binary operator OR, AND is said to be associative if,
1. A+(B+C) = (A+B)+C
2. A.(B.C) = (A.B).C

3. Distributive Law
The binary operator OR, AND is said to be distributive if,
1. A+(B.C) = (A+B).(A+C)
2. A.(B+C) = (A.B)+(A.C)

4. Absorption Law
1. A+AB = A
2. A+AB = A+B

5. Involution (or) Double complement Law

(A’)’ = A

6. Idempotent Law
1. A+A = A
2. A.A = A
7. Complementary Law
1. A+A' = 1
2. A.A' = 0

8. De Morgan’s Theorem
1. The complement of the sum is equal to the sum of the product of the individual
complements.
A+B = A.B
2. The complement of the product is equal to the sum of the individual complements.
A.B = A+B
Demorgan’s Theorem
a) Proof of equation (1):
Construct the two circuits corresponding to the functions A’. B’and (A+B)’
respectively. Show that for all combinations of A and B, the two circuits give identical
results. Connect these circuits and verify their operations.
b) Proof of equation (2)
Construct two circuits corresponding to the functions A’+B’and (A.B)’
A.B, respectively. Show that, for all combinations of A and B, the two circuits
give identicalresults. Connect these circuits and verify their operations.
 We will also use the following set of postulates:
P1: Boolean algebra is closed under the AND, OR, and NOT operations.
P2: The identity element with respect to • is one and + is zero. There is no
identityelement with respect to logical NOT.
P3: The • and + operators are commutative.
P4: • and + are distributive with respect to one another. That is,
A • (B + C) = (A • B) + (A • C) and A + (B • C) = (A + B) • (A + C).
P5: For every value A there exists a value A’ such that A•A’ = 0 and A+A’ = 1.
This value is the logical complement (or NOT) of A.
P6: • and + are both associative. That is, (A•B)•C = A•(B•C) and (A+B)+C = A+(B+C).
You can prove all other theorems in boolean algebra using these postulates.

PROCEDURE:

1. Obtain the required IC along with the Digital trainer kit.

2. Connect zero volts to GND pin and +5 volts to Vcc .
3. Apply the inputs to the respective input pins.
4. Verify the output with the truth table.

RESULT:
Thus the above stated Boolean laws are verified.
EXPT NO: 02 DESIGN AND IMPLEMENTATION OF
DATE: ADDER AND SUBTRACTOR

AIM:
To design and construct half adder, full adder, half subtractor and full subtractor circuits and
verify the truth table using logic gates.

APPARATUS REQUIRED:

SL.NO. COMPONENT SPECIFICATION QTY.

1. AND GATE IC 7408 1
2. X-OR GATE IC 7486 1
3. NOT GATE IC 7404 1
4. OR GATE IC 7432 1
5. IC TRAINER KIT - 1
6. PATCH CORDS - 23

THEORY:
HALF ADDER:
A half adder has two inputs for the two bits to be added and two outputs
one from the sum ‘ S’ and other from the carry ‘ c’ into the higher adder
position. Above circuit is called as a carry signal from the addition of the less
significant bits sum from the X-OR Gate the carry out from the AND gate.
FULL ADDER:
A full adder is a combinational circuit that forms the arithmetic sum of
input; it consists of three inputs and two outputs. A full adder is useful to add
three bits at a time buta half adder cannot do so. In full adder sum output will be
taken from X-OR Gate, carry output will be taken from OR Gate.

HALF SUBTRACTOR:
The half subtractor is constructed using X-OR and AND Gate. The half
subtractor has two input and two outputs. The outputs are difference and borrow.
The difference can be applied using X-OR Gate, borrow output can be
implemented using an AND Gate and an inverter.
FULL SUBTRACTOR:
The full subtractor is a combination of X-OR, AND, OR, NOT Gates. In
a full subtractor the logic circuit should have three inputs and two outputs. The
 two half subtractor put together gives a full subtractor .The first half subtractor
will be C and A B. The output will be difference output of full subtractor. The
expression AB assembles the borrow output of the half subtractor and the
second term is the inverted difference outputof first X-OR.

HALF ADDER: TRUTH TABLE:

A B CARRY SUM

0 0 0 0
0 1 0 1
1 0 0 1
1 1 1 0

K-Map for SUM: K-Map for CARRY:

1
1

SUM = A’B + AB’ CARRY = AB

LOGIC DIAGRAM:
 FULL ADDER

TRUTH TABLE:

A B C CARRY SUM

0 0 0 0 0
0 0 1 0 1
0 1 0 0 1
0 1 1 1 0
1 0 0 0 1
1 0 1 1 0
1 1 0 1 0
1 1 1 1 1

K-Map for SUM

1 1

1 1

SUM = A’B’C + A’BC’ + ABC’ + ABC

K-Map for CARRY
 CARRY = AB + BC + AC

LOGIC DIAGRAM:

FULL ADDER USING TWO HALF ADDER

HALF SUBTRACTOR

TRUTH TABLE:
A B BORROW DIFFERENCE

0 0 0 0
0 1 1 1
1 0 0 1
1 1 0 0

K-Map for DIFFERENCE

1
 DIFFERENCE = A’B + AB’

K-Map for BORROW

BORROW = A’B

LOGIC DIAGRAM

FULL SUBTRACTOR

TRUTH TABLE:

A B C BORROW DIFFERENCE

0 0 0 0 0
0 0 1 1 1
0 1 0 1 1
0 1 1 1 0
1 0 0 0 1
1 0 1 0 0
1 1 0 0 0
1 1 1 1 1

K-Map for Difference

1 1
 1 1

Difference = A’B’C + A’BC’ + AB’C’ + ABC

K-Map for Borrow

Borrow = A’B + BC + A’C

LOGIC DIAGRAM:

FULL SUBTRACTOR USING TWO HALF SUBTRACTOR

PROCEEDURE:

(i) Connections are given as per circuit diagram.

(ii) Logical inputs are given as per circuit diagram.
(iii) Observe the output and verify the truth table.

RESULT:

Thus, the half adder, full adder, half subtractor and full
subtractor circuits are designed, constructed and verified the truth
table using logic gates.
EXPT NO: 03 DESIGN AND IMPLEMENTATION OF
DATE: 4-BIT ADDER AND SUBTRACTOR

AIM:
To design and implement 4-bit adder and subtractor using basic gates
and MSI device IC 7483.

APPARATUS REQUIRED:

SL.NO. COMPONENT SPECIFICATION QTY.

1. IC IC 7483 1
2. EX-OR GATE IC 7486 1
3. NOT GATE IC 7404 1
3. IC TRAINER KIT - 1
4. PATCH CORDS - 40

THEORY:

4 BIT BINARY ADDER:

A binary adder is a digital circuit that produces the arithmetic sum of two
binary numbers. It can be constructed with full adders connected in cascade,
with the output carry from each full adder connected to the input carry of next
full adder in chain. The augends bits of ‘A’ and the addend bits of ‘B’ are
designated by subscript numbers from right to left, with subscript 0 denoting
the least significant bits. The carries are connected in chain
through the full adder. The input carry to the adder is C0 and it ripples through
the full adder to the output carry C4.

4 BIT BINARY SUBTRACTOR:

The circuit for subtracting A-B consists of an adder with inverters, placed
between each data input ‘B’ and the corresponding input of full adder. The
input carry C0 must be equal to 1 when performing subtraction.
4 BIT BINARY ADDER/SUBTRACTOR:
The addition and subtraction operation can be combined into one circuit
with one common binary adder. The mode input M controls the operation. When
M=0, the circuit is adder circuit. When M=1, it becomes subtractor.

4 BIT BCD ADDER:

Consider the arithmetic addition of two decimal digits in BCD, together
with an input carry from a previous stage. Since each input digit does not exceed
9, the output sum cannot be greater than 19, the 1 in the sum being an input
carry. The output of two decimal digits must be represented in BCD and should
appear in the form listed in the columns.

BCD adder adds 2 BCD digits and produce a sum digit in BCD. The 2
decimal digits, together with the input carry, are first added in the top 4 bit
adder to produce the binary sum.
PIN DIAGRAM FOR IC 7483:
 4-BIT BINARY ADDER
LOGIC DIAGRAM:

4-BIT BINARY SUBTRACTOR

LOGIC DIAGRAM:

4-BIT BINARY ADDER/SUBTRACTOR

LOGIC DIAGRAM:
 TRUTH TABLE:

Input Data A Input Data B Addition Subtraction

A4 A3 A2 A1 B4 B3 B2 B1 C S4 S3 S2 S1 B D4 D3 D2 D1
1 0 0 0 0 0 1 0 0 1 0 1 0 1 0 1 1 0
1 0 0 0 1 0 0 0 1 0 0 0 0 1 0 0 0 0
0 0 1 0 1 0 0 0 0 1 0 1 0 0 1 0 1 0
0 0 0 1 0 1 1 1 0 1 0 0 0 0 1 0 1 0
1 0 1 0 1 0 1 1 1 0 0 1 0 0 1 1 1 1
1 1 1 0 1 1 1 1 1 1 0 1 0 0 1 1 1 1
1 0 1 0 1 1 0 1 1 0 1 1 1 0 1 1 0 1

PROCEDURE:

(i) Connections were given as per circuit diagram.

(ii) Logical inputs were given as per truth table
(iii) Observe the logical output and verify with the truth tables.
RESULT:

Thus the 4-bit adder and subtractor using basic gates and MSI device IC
7483 isdesigned and implemented.
EXPT NO: 04 DESIGN AND IMPLEMENTATION OF
DATE: CODE CONVERTERS

AIM:
To design and implement 4-bit
(i) Binary to gray code converter
(ii) Gray to binary code converter
(iii) BCD to excess-3 code converter
(iv) Excess-3 code to BCD code converter

APPARATUS REQUIRED:
SL.NO. COMPONENT SPECIFICATION QTY.
1. X-OR GATE IC 7486 1
2. AND GATE IC 7408 1
3. OR GATE IC 7432 1
4. NOT GATE IC 7404 1
5. IC TRAINER KIT - 1
6. PATCH CORDS - 35

THEORY:

The availability of large variety of codes for the same discrete elements of
information results in the use of different codes by different systems. A conversion
circuit must be inserted between the two systems if each uses different codes for
same information. Thus, code converter is a circuit that makes the two systems
compatible even though each uses different binary code.

The bit combination assigned to binary code to gray code. Since each code
uses four bits to represent a decimal digit. There are four inputs and four outputs.
Gray code is a non-weighted code.

The input variable are designated as B3, B2, B1, B0 and the output variables
are designated as C3, C2, C1, Co. from the truth table, combinational circuit is
designed. The Boolean functions are obtained from K-Map for each output variable.
 A code converter is a circuit that makes the two systems compatible even
though each uses a different binary code. To convert from binary code to Excess-3
code, the input lines must supply the bit combination of elements as specified by code
and the output lines generate the corresponding bit combination of code. Each one of
the four maps represents one of the four outputs of the circuit as a function of the four
input variables.

A two-level logic diagram may be obtained directly from the Boolean

expressions derived by the maps. These are various other possibilities for a logic
diagram that implements this circuit. Now the OR gate whose output is C+D has been
used to implement partially each of three outputs.

BINARY TO GRAY CODE CONVERTER

TRUTH TABLE:

Binary Input Gray Code Output

B3 B2 B1 B0 G3 G2 G1 G0
0 0 0 0 0 0 0 0
0 0 0 1 0 0 0 1
0 0 1 0 0 0 1 1
0 0 1 1 0 0 1 0
0 1 0 0 0 1 1 0
0 1 0 1 0 1 1 1
0 1 1 0 0 1 0 1
0 1 1 1 0 1 0 0
1 0 0 0 1 1 0 0
1 0 0 1 1 1 0 1
1 0 1 0 1 1 1 1
1 0 1 1 1 1 1 0
1 1 0 0 1 0 1 0
1 1 0 1 1 0 1 1
1 1 1 0 1 0 0 1
1 1 1 1 1 0 0 0
K-Map for G3

G3 = B3

K-Map for G2

K-Map for G1
K-Map for G0

LOGIC DIAGRAM:

GRAY CODE TO BINARY CONVERTER

TRUTH TABLE:

GRAY CODE BINARY CODE

G3 G2 G1 G0 B3 B2 B1 B0
0 0 0 0 0 0 0 0
0 0 0 1 0 0 0 1
0 0 1 1 0 0 1 0
0 0 1 0 0 0 1 1
0 1 1 0 0 1 0 0
 0 1 1 1 0 1 0 1
0 1 0 1 0 1 1 0
0 1 0 0 0 1 1 1
1 1 0 0 1 0 0 0
1 1 0 1 1 0 0 1
1 1 1 1 1 0 1 0
1 1 1 0 1 0 1 1
1 0 1 0 1 1 0 0
1 0 1 1 1 1 0 1
1 0 0 1 1 1 1 0
1 0 0 0 1 1 1 1

K-Map for B3:

B3 = G3

K-Map for B2:

K-Map for B1:

K-Map for B0:

LOGIC DIAGRAM:

TRUTH TABLE:
BCD TO EXCESS-3 CONVERTER

| BCD input | Excess – 3 output |

B3 B2 B1 B0 G3 G2 G1 G0

0 0 0 0 0 0 1 1

0 0 0 1 0 1 0 0

0 0 1 0 0 1 0 1

0 0 1 1 0 1 1 0

0 1 0 0 0 1 1 1

0 1 0 1 1 0 0 0
 0 1 1 0 1 0 0 1

0 1 1 1 1 0 1 0

1 0 0 0 1 0 1 1

1 0 0 1 1 1 0 0

1 0 1 0 x x x x

1 0 1 1 x x x x

1 1 0 0 x x x x

1 1 0 1 x x x x

1 1 1 0 x x x x

1 1 1 1 x x x X

K-Map for E3:

E3 = B3 + B2 (B0 + B1)

K-Map for E2:

K-Map for E1:

K-Map for E0:

 EXCESS-3 TO BCD CONVERTER

TRUTH TABLE:

| Excess – 3 Input | BCD Output |

B3 B2 B1 B0 G3 G2 G1 G0

0 0 1 1 0 0 0 0

0 1 0 0 0 0 0 1

0 1 0 1 0 0 1 0

0 1 1 0 0 0 1 1

0 1 1 1 0 1 0 0

1 0 0 0 0 1 0 1

1 0 0 1 0 1 1 0

1 0 1 0 0 1 1 1

1 0 1 1 1 0 0 0

1 1 0 0 1 0 0 1

LOGIC DIAGRAM:
 EXCESS-3 TO BCD CONVERTER

K-Map for A:

A = X1 X2 + X3 X4
X1

K-Map for B:

K-Map for C:
 23

K-Map for D:

EXCESS-3 TO BCD CONVERTER

 PROCEDURE:

(i) Connections were given as per circuit diagram.

(ii) Logical inputs were given as per truth table
(iii) Observe the logical output and verify with the truth tables.

RESULT:

Thus the following 4-bit converters are designed and

constructed.

(i) Binary to gray code converter

(ii) Grayto binary code converter
(iii) BCD to excess-3 code converter
(iv) Excess-3 to BCD code converter
 EXPT NO: 05.a DESIGN AND IMPLEMENTATION OF
DATE: BCD ADDER USING IC7483

AIM:
To design and implement a BCD adder using IC 7483

APPARATUS REQUIRED:

S.NO COMPONENTS/EQUIPMENTS SPECIFICATION QUANTITY

1. AND GATE IC 7408 2
2. OR GATE IC7432 2
3. XOR GATE IC 7486 4
4. 4-Bit Binary Full Adder IC 7483 2
5. IC TRAINER KIT - 1
6. PATCH CORDS - 35

THEORY:

Consider the arithmetic addition of two decimal digits in BCD, together with an input

carry from a previous stage. Since each input digit does not exceed 9, the output sum cannot

be greater than9, the 1 in the sum being an input carry. The output of two decimal digits must

be represented in BCD and should appear in the form listed in the columns. The 2 decimal

digits, together with the input carry, are first added in the top 4 bit adder to produce the binary

sum.

PIN DIAGRAM FOR IC 7483:

TRUTH TABLE:

BCD SUM CARRY

S4 S3 S2 S1 C
0 0 0 0 0
0 0 0 1 0
0 0 1 0 0
0 0 1 1 0
0 1 0 0 0
0 1 0 1 0
0 1 1 0 0
0 1 1 1 0
1 0 0 0 0
1 0 0 1 0
1 0 1 0 1
1 0 1 1 1
1 1 0 0 1
1 1 0 1 1
1 1 1 0 1
1 1 1 1 1

K MAP

Y = S4 (S3 + S2)
 LOGICAL REPRESENTATION

PROCEDURE:

(i) Give connections as per circuit diagram.

(ii) Apply logical inputs as given in the truthtable

(iii) Observe the logical output and verify with the truthtable.

RESULT:
Thus a BCD adder using IC 7483 was designed and implemented successfully.
 EXPT NO: 05.b DESIGN AND IMPLEMENTATION OF
DATE: AN ENCODER USING LOGIC GATES

AIM:
To design and implement an Encoder using logic gates.

APPARATUS REQUIRED:

S.NO COMPONENTS/EQUIPMENTS SPECIFICATION QUANTITY

1. OR GATE IC 7432 9
2. IC TRAINER KIT - 1
3. PATCH CORDS - 32

THEORY:

An encoder is a digital circuit that performs the inverse operation of a decoder. An

encoder has 2n input lines and n output lines. In encoder the output lines generates the binary
code corresponding to the input value. In octal to binary encoder it has eight inputs, one for
each octal digitand three output that generate the corresponding binary code.

TRUTH TABLE:

INPUT OUTPUT
Y1 Y2 Y3 Y4 Y5 Y6 Y7 A B C
1 0 0 0 0 0 0 0 0 1
0 1 0 0 0 0 0 0 1 0
0 0 1 0 0 0 0 0 1 1
0 0 0 1 0 0 0 1 0 0
0 0 0 0 1 0 0 1 0 1
0 0 0 0 0 1 0 1 1 0
0 0 0 0 0 0 1 1 1 1
 LOGICAL REPRESENTATION

PROCEDURE:

(i) Give connections as per circuit diagram.

(ii) Apply logical inputs as given in the truth table

(iii) Observe the logical output and verify with the truth table.

RESULT:

Thus an Encoder was designed and implemented successfully using logic gates.
 EXPT NO:05.c DESIGN AND IMPLEMENTATION OF
DATE: DECODER USING LOGIC GATES

AIM:
To design and implement a Decoder using logic gates.

APPARATUS REQUIRED:

S.NO COMPONENTS/EQUIPMENTS SPECIFICATION QUANTITY

1. 3 I/P NAND GATE IC 7410 4
2. NOT GATE IC 7404 3
3. IC TRAINER KIT - 1
4. PATCH CORDS - 32

THEORY:

A decoder is a multiple input multiple output logic circuit which converts coded input
into coded output where input and output codes are different. The input code generally has
fewer bits thanthe output code. Each input code word produces a different output code word i.e
there is a one to one mapping in the truth table. In the block diagram of decoder circuit the
encoded information is present as n input producing 2n outputs bits.

TRUTH TABLE:

INPUT OUTPUT
E A B D0 D1 D2 D3
1 0 0 1 1 1 1
0 0 0 0 1 1 1
0 0 1 1 0 1 1
0 1 0 1 1 0 1
0 1 1 1 1 1 0
LOGICAL REPRESENTATION

PROCEDURE:

(i) Give connections as per circuit diagram.

(ii) Apply logical inputs as given in the truth table

(iii) Observe the logical output and verify with the truth table.

RESULT:
Thus a Decoder was designed and implemented using logic gates successfully.
EXPT NO: 06 DESIGN AND IMPLEMENTATION OF
DATE: MULTIPLEXER AND DEMULTIPLEXER

AIM:

To design and implement the multiplexer and demultiplexer using logic

gatesand study of IC 74150 and IC 74154

APPARATUS REQUIRED:

SL.NO. COMPONENT SPECIFICATION QTY.

1. 3 I/P AND GATE IC 7411 2
2. OR GATE IC 7432 1
3. NOT GATE IC 7404 1
2. IC TRAINER KIT - 1
3. PATCH CORDS - 32

THEORY:

MULTIPLEXER:
Multiplexer means transmitting a large number of information units over a
smaller number of channels or lines. A digital multiplexer is a combinational circuit
that selects binary information from one of many input lines and directs it to a single
output line. The selection of a particular input line is controlled by a set of selection
lines. Normally there are 2n input line and n selection lines whose bit
combination determine which input is selected.

DEMULTIPLEXER:
The function of Demultiplexer is in contrast to multiplexer function. It takes
information from one line and distributes it to a given number of output lines. For this
reason, the demultiplexer is also known as a data distributor. Decoder can also be used
as demultiplexer. In the 1: 4 demultiplexer circuit, the data input line goes to all of the
AND gates. The data select lines enable only one gate at a time and the data on the
data input line will pass through the selected gate to the associated data output line.
4:1 MULTIPLEXER

BLOCK DIAGRAM FOR 4:1 MULTIPLEXER:

FUNCTION TABLE:

S1 S0 INPUTS Y
0 0 D0 → D0 S1’ S0’
0 1 D1 → D1 S1’ S0
1 0 D2 → D2 S1 S0’
1 1 D3 → D3 S1 S0

Y = D0 S1’ S0’ + D1 S1’ S0 + D2 S1 S0’ + D3 S1 S0

TRUTH TABLE:

S1 S0 Y = OUTPUT

0 0 D0

0 1 D1

1 0 D2

1 1 D3
CIRCUIT DIAGRAM FOR MULTIPLEXER:

1:4 DEMULTIPLEXER

BLOCK DIAGRAM FOR 1:4 DEMULTIPLEXER:

FUNCTION TABLE:

S1 S0 INPUT
0 0 X → D0 = X S1’ S0’
0 1 X → D1 = X S1’ S0
1 0 X → D2 = X S1 S0’
1 1 X → D3 = X S1 S0

Y = X S1’ S0’ + X S1’ S0 + X S1 S0’ + X S1 S0

TRUTH TABLE:

INPUT OUTPUT
S1 S0 I/P D0 D1 D2 D3
0 0 0 0 0 0 0
0 0 1 1 0 0 0
0 1 0 0 0 0 0
0 1 1 0 1 0 0
1 0 0 0 0 0 0
1 0 1 0 0 1 0
1 1 0 0 0 0 0
1 1 1 0 0 0 1

LOGIC DIAGRAM FOR DEMULTIPLEXER:

PIN DIAGRAM FOR IC 74150:

PIN DIAGRAM FOR IC 74154:

PROCEDURE:

(i) Connections are given as per circuit diagram.

(ii) Logical inputs are given as per circuit diagram.
(iii) Observe the output and verify the truth table.

RESULT:
Thus the multiplexer and demultiplexer using logic gates are designed and
implemented.
 EXPT NO:7 DESIGN AND IMPLEMENTATION OF
DATE: SYNCHRONOUS SEQUENTIAL CIRCUITS

AIM:
To design and implement a 3-Bit Synchronous Up Counter/Down Counter.
APPARATUS REQUIRED:

S.NO COMPONENTS/EQUIPMENTS SPECIFICATION QUANTITY

1. JK FLIP FLOP IC 7476 2
2. 3 I/P AND GATE IC 7411 2
3. OR GATE IC 7432 1
4. XOR GATE IC 7486 1
5. NOT GATE IC 7404 2
6. IC TRAINER KIT - 1
7. PATCH CORDS - 35

THEORY:

A counter is a register capable of counting number of clock pulse arriving at its clock
input. Counter represents the number of clock pulses arrived. An up/down counter is one that is
capable of progressing in increasing order or decreasing order through a certain sequence. An
up/down counter is also called bidirectional counter. Usually up/down operation of the counter
is controlled by up/down signal. When this signal is high counter goes through up sequence
and when up/down signalis low counter follows reverses equence.

STATE DIAGRAM:
CHARACTERISTIC TABLE FOR J-K FLIP FLOP:

Q Qt+1 J K
0 0 0 X
0 1 1 X
1 0 X 1
1 1 X 0

TRUTH TABLE:

Input PresentState NextState A B C

Up/Down QA QB QC QA+1 Q B+1 QC+1 JA KA JB KB JC KC
0 0 0 0 1 1 1 1 X 1 X 1 X
0 1 1 1 1 1 0 X 0 X 0 X 1
0 1 1 0 1 0 1 X 0 X 1 1 X
0 1 0 1 1 0 0 X 0 0 X X 1
0 1 0 0 0 1 1 X 1 1 X 1 X
0 0 1 1 0 1 0 0 X X 0 X 1
0 0 1 0 0 0 1 0 X X 1 1 X
0 0 0 1 0 0 0 0 X 0 X X 1
1 0 0 0 0 0 1 0 X 0 X 1 X
1 0 0 1 0 1 0 0 X 1 X X 1
1 0 1 0 0 1 1 0 X X 0 1 X
1 0 1 1 1 0 0 1 X X 1 X 1
1 1 0 0 1 0 1 X 0 0 X 1 X
1 1 0 1 1 1 0 X 0 1 X X 1
1 1 1 0 1 1 1 X 0 X 0 1 X
1 1 1 1 0 0 0 X 1 X 1 X 1
K MAP

LOGICAL REPRESENTATION:
PROCEDURE:

(i) Give connections as per circuit diagram.

(ii) Apply logical inputs as given in the truthtable

(iii) Observe the logical output and verify with the truthtable.

RESULT:
Thus a 3-Bit Synchronous Up/Down Counter was designed and implemented successfully.
 EXPT NO: 8 DESIGN AND IMPLEMENTATION OF
DATE: UNIVERSAL SHIFT REGISTER

AIM:
To design and implement the universal shift registers which can performs the following
operations
(i) Serial in serial out
(ii) Serial in parallel out
(iii) Parallel in serial out
(iv) Parallel in parallel out

APPARATUS REQUIRED:

SL.NO. COMPONENT SPECIFICATION QTY.

1. D FLIP FLOP IC 7474 2

2. OR GATE IC 7432 1

3. IC TRAINER KIT - 1

4. PATCH CORDS - 35

THEORY:

A register capable of shifting its binary information in one or both directions

is known as shift register. The logical configuration of shift register consist of a D-
Flip flop cascaded with output of one flip flop connected to input of next flip flop.
All flip flops receive common clock pulses which causes the shift in the output of
the flip flop. The simplest possible shift register is one that uses only flip flop. The
output of a given flip flop is connected to the input of next flip flop of the register.
Each clock pulse shifts the contentof register one bit position to right.
PIN DIAGRAM OF IC 7474:

SERIAL IN SERIAL OUT

LOGIC DIAGRAM:

TRUTH TABLE:

CLK Serial In Serial Out

1 1 0
2 0 0
3 0 0
4 1 1
5 X 0
6 X 0
7 X 1
 SERIAL IN PARALLEL OUT

LOGIC DIAGRAM:

TRUTH TABLE:

OUTPUT
CLK DATA QA QB QC QD
1 1 1 0 0 0
2 0 0 1 0 0
3 0 0 0 1 1
4 1 1 0 0 1

PARALLEL IN SERIAL OUT

LOGIC DIAGRAM:
 TRUTH TABLE:

CLK Q3 Q2 Q1 Q0 O/P

0 1 0 0 1 1

1 0 0 0 0 0

2 0 0 0 0 0

3 0 0 0 0 1

PARALLEL IN PARALLEL OUT

LOGIC DIAGRAM:

TRUTH TABLE:

DATA INPUT OUTPUT

CLK
DA DB DC DD QA QB QC QD

1 1 0 0 1 1 0 0 1

2 1 0 1 0 1 0 1 0
 Universal Shift Register

PROCEDURE:
(i) Connections are given as per circuit diagram.
(ii) Logical inputs are given as per circuit diagram.
(iii) Observe the output and verify the truth table.

RESULT:

The Serial in serial out, Serial in parallel out, Parallel in serial out and Parallel in
parallel out shift registers and universal shift registers are designed and implemented.