UNIT-5

Fsm
Moore Machine

Moore machine is a finite state machine in which the next state is decided
by the current state and current input symbol.

The output symbol at a given time depends only on the present state of
the machine.

Moore machine has six tuples (Q, q0, Σ, O, δ, λ)

Where,

 Q: set of Finite states

 q0: Initial state of machine.
 Σ: Finite set of input symbols.
 O: Output symbol
 δ: Transition function where Q × Σ → Q.
 λ': Output function where Q → O.
Mealy Machine

In a Mealy machine the output symbol depends upon the present state of
the machine as well as on the present input symbol.

In the Mealy machine, the output is represented with each input symbol
and state separated by /.

The length of output for a mealy machine is equal to the length of input

The Mealy machine can be described by six tuples (Q, q0, Σ, O, δ, λ')

Where,

 Q: Finite set of states.

 q0: Initial state of machine.
 Σ: Finite set of input symbol.
 O: Output symbol
 δ: Transition function where Q × Σ → Q.
 λ': Output function where Q × Σ → O.
Output The output of a Moore machine is also The output of a Mealy Machine is placed on the
placed on the transition. transition.

State and Both the state and output of a Moore The asynchronous output of a Mealy machine
Output Machine change synchronously with the becomes synchronous with the current clock when
clock edge. the state changes.

Counter A counter can be classified as a Moore A counter cannot be classified as a Mealy

Machine. Machine.

Design Designing a Moore Machine is relatively The design process of a Mealy Machine can be
Complexity easy. complex.
 BASI
C DESIGN STEPS
Suppose that we wish to design a circuit that meets the following specification:
1. The circuit has one input, w, and one output, z.
2. All changes in the circuit occur on the positive edge of a clock signal.
3. The output z is equal to 1, if two immediately preceding clock cycles the input w was
equal to 1. Otherwise, the value of z is equal to 0.
STEP -1: State Diagram: The first step in designing a finite state machine is to determine
how many states are needed and which transitions are possible from one state to another.
This can be done by State Diagram.
A state diagram, which is a graph that depicts states of the circuit as nodes (circles) and
transitions between states as directed arcs.
EXAMPLE: For our example let starting state is called state A. As long as the input w is 0, the
circuit remains in state A. When w = 1, the circuit move to the state B on the next active
clock edge after w =1. In state B, z = 0, because w is not equal to 1 for two consecutive clock
cycles. If in state B, w = 0 at the next active clock edge, the circuit move back to state A.
However in state B, if w = 1 then the circuit transition to a third state, called C, and then it
generate an output z = 1. The circuit should remain in state C as long as w = 1 and continue
to maintain z = 1. When w becomes 0, the machine move back to state A.
2 State Table:
a state-transition table shows in which state a FSM will move to, based on the
current state and other inputs.

STEP-3: State Assignment

State assignment is a process of mapping from the set of states of an FSM to the
set of binary codes in order to minimise the area of the combinational circuit
required to realise the FSM. i.e. it reduces the no. of flip-flops by assigning binary
codes to the state
EXAMPLE:
From the specification, the output z is a function of only y1 and y2(i.e. present state of
circuit because our design is of Moore type. )
The signals y1 and y2 are also fed back to the combinational circuit that determines the next
state of the FSM. This circuit also uses the primary input signal w. Its outputs are two
signals, Y1 and Y2, which are used as input to set the state of the flip-flops. At Each active
edge of the clock, Therefore, Y1 and Y2 are called the next-state variables, and y1 and y2 are
called the present-state variables.
To produce the desired truth table, the states A, B, and C are represented by y2y1 = 00, 01,
and 10, respectively. This type of table is usually called a state-assigned table
From the state-assigned table, we can derive the expressions for the next-state and output
functions.
Here we have used the D-type flip-flops, because, if the inputs to the flip-flops are called D1
and D2, then these signals are the same as Y1 and Y2.
The required logic expressions can be derived using Karnaugh map:
A key point to observe is that even though w changes slightly after the active clock edge, and thus the value
of w is equal to 1 (or 0) for almost the entire clock cycle, no change in the circuit will occur until the
beginning of the next clock cycle when the positive edge causes the flip-flops to change their state. Thus
the value of w must be equal to 1 for two clock cycles if the circuit is to reach state C and generate the
output z = 1

8.1.5 FINAL IMPLEMENTATION OF THE CIRCUIT

8.2 STATE ASSIGNMENT PROBLEM
Some state assignments may be better than others. We already know that the state assignment, which
leads to a simple-looking circuit in final implementation.

But the FSM can be implemented with an even simpler circuit by using a different state assignment called as
improved assignment. To illustrate this we can reconsider the example

Suppose that we wish to design a circuit that meets the following specification:
1. The circuit has one input, w, and one output, z.
2. All changes in the circuit occur on the positive edge of a clock signal.
3. The output z is equal to 1, if during two immediately preceding clock cycles the input w
was equal to 1. Otherwise, the value of z is equal to 0.
STEP -1: State Diagram

2 State Table:

STEP-3: State Assignment

8.1.5 FINAL IMPLEMENTATION OF THE CIRCUIT
For above discussed example the improved state assignment can be defined as

In this case we represent the states A, B, and C with the valuations y2y1 = 00, 01, and 11, respectively. The remaining
valuation, y2y1 = 10, is not needed, and we will treat it as a don’t-care condition.

If we again choose to implement the circuit using D-type flip-flops, the next-state and output expressions derived

ONE-HOT ENCODING METHOD

In one hot encoding method, for each state not all but one of the state variable
is equal to 1. The variable whose value is 1 is called as “hot.” The approach is
known as the one-hot encoding method.
One-hot encoding assigns one flip-flop for each state.
A FSM with N states requires N flip-flops. The states are
assigned N-bit binary numbers; where only one of the
corresponding bit position is equal to 1, the remaining bits are
equal to0.
One-hot encoding is an alternative state assignment method which
attempts to minimize the combinational logic by increasing the
number of flip-flops.
The goal of the method is to try to reduce the number of
connections between the logic gates in the combinational circuit of
FSM. As presence of more gate inter-connections results into longer
propagation delays and a slower FSM. Since the propagation delay
through the flip-flops is faster, FSMs require fewer logic gates but
not necessarily fewer flip-flops.

Suppose that we wish to design a circuit that meets the following specification:

1. The circuit has one input, w, and one output, z.

2. All changes in the circuit occur on the positive edge of a clock signal.
3. The output z is equal to 1, if during two immediately preceding clock cycles the input w
was equal to 1. Otherwise, the value of z is equal to 0.
State Table:

since there are three states. The chosen assignment will represent the states A, B, and C
using the valuations y3y2y1 = 001, 010, and 100, respectively. The remaining five valuations
of the state variables can be treated as don’t cares.
the resulting expressions are.
Y1 = w
Y2 = wy1
Y3 = w y 1
z = y3

advantages of onehot encoding in FSMs are as follows:

1. Low switching activity. Since only single bit is switched at a time, the
power consumption is less and it is less prone to glitches.
2. Simplified encoding. One can determine the state just by looking at the bit
position of '1' in the current state variable.
The disadvantage of this technique is that it requires more number of flops.
VERILOG CODE FOR MOORE
TYPE FSM VERILOG CODE FOR MEALY TYPE
FSM

SERIAL ADDER
Serial adder consists of the shift registers and the adder FSM. In serial
adder three shift registers are used for the inputs A and B and the output
sum. The shift registers are loaded with parallel data when the circuit is
reset. It also includes a down counter to determine when the adder
should halted because all 'n' bits of the required sum are present in the
output shift register. When the circuit is reset, the counter is loaded with
the ‘n’ bit numbers. The counter counts down to '0', then stop and
disables the further changes in the output shift register.
Verilog CODE:

module serial_adder(a,b,cin, clk,reset,s,cout)

input clk,reset;
input a,b,cin;
output reg s,cout;

reg c,flag;

always@(posedge clk or posedge reset)

begin
if(reset == 1) begin
s = 0;
cout = c;
flag = 0;
end else begin
if(flag == 0)
begin
c = cin;
flag = 1;
end
cout = 0;
s = a ^ b ^ c; //SUM
c = (a & b) | (c & b) | (a & c);
end
end

endmodule
A vending machine is an automated machine that dispenses items such as
snacks, beverages, cigarettes, and lottery tickets to consumers after cash, a
credit card, or other forms of payment are inserted into the machine.

The specification for the controller is:

• It accepts nickels and dimes.
• A total of 15 cents is needed to release the candy from the machine.
• No change is given if 20 cents is deposited.
Coins are deposited one at a time. The coin-sensing mechanism generates signals N = 1 and
D = 1 when it sees a nickel or a dime, respectively. It is impossible to have N = D = 1 at the
same time. Following the insertion of a coin for which the sum equals or exceeds 15 cents,
the machine releases the candy and resets to the initial state.
Design Code

module vending_machine(out, in, clk, rst);

input clk;
input rst;
input [1:0]in;
output reg out;
reg out;

parameter s0=2'b00;
parameter s5=2'b01;
parameter s10=2'b10;
parameter s15=2'b11;
reg [1:0]c_state, n_state;

always @(posedge clk)

begin
if (rst==1)
begin
c_state = 0;
n_statement = 0
end
else
beging
always @(state,coin)
begin
case (state)
s0:
begin
if (coin==2'b00)
next_state=s0;
else
if (coin==2'b01)
next_state=s5;
else
if (coin==2'b10)
next_state=s10;
end
s5:
begin
if (coin==2'b00)
next_state=s5;
else
 if (coin==2'b01)
next_state=s10;
else
if (coin==2'b10)
next_state=s15;
end
s10:
begin
if (coin==2'b00)
next_state=s10;
else
if (coin==2'b01)
next_state=s15;
else
if (coin==2'b10)
next_state=s15;
end
s15:
begin
next_state=s0;
end
default : next_state=s0;

endcase // case (state)

end // always @ (state,next_state)

always @(state)
begin
case (state)
s0 : nw_pa<=1'b0;
s5 : nw_pa<=1'b0;
s10: nw_pa<=1'b0;
s15: nw_pa<=1'b1;
default: nw_pa<=1'b0;
endcase // case (state)
end

endmodule
BUS ARCHITECTUR
The bus architecture is an efficient compromise between point-to-point architectures, which are too
decentralized, which are too centralized. The bus architecture provides the benefits of logically centralized
configuration and management but its parts are physically decentralized.
One of the main benefits of bus architectures is that they enable efficient sharing of resources and data
between components. This allows for more efficient use of available system resources, which in turn can
lead to increased performance and reliability.

What is an arbiter?

An Arbiter is used to provide access of data bus whenever there are more than one requesters for the bus, we can say
arbiter is like a traffic police constable who grant the access of road to the vehicle drivers according to the traffic rules.

Consider the case of a System-on-Chip (SoC). When we say SoC it symbolizes a complete system compromising of
different units on single chip. In SoC the data transfer between different units takes place via single bus.

So to remove ambiguity we need to provide bus to a single unit at a particular time. Here we have different units as
requesters and bus as our resource.