5LPE Layout learning's – Samsung Foundry:

- Created By: mahesh N

Information:

1. Gate length – 6nm – Core devices – Voltage (0.875V), Poly pitch – 57um, Fin-pitch 27nm
Gate length – 8nm for Analog devices

2. Advised width & Spacing for Metal :

Metals Width Spacing

M1: 0.024 0.018
M2: 0.030 0.024
M3: 0.032 0.024
M4: 0.030 0.024
M5: 0.040 0.044
M6: 0.060 0.068
M7-M11: 0.08/0.12/0.16 0.10

3. Layer Hierarchy.

OD POLY

CR
CA CB

VA VB

M1 M1

V1

M2

V2

Do’s:

1. OD must be continuous as possible (add dummy gate if required), minimum 4 dummy gates required
at OD ending followed by a FinCut (FC) layer

2. M1,M2 is more resistive, so try routing in M3 and above metals

3. Try to make strong power connections, advised to follow a pitch (alternate metal track for power
routing in each metal) and stack metals for better power supply.

4. Make sure the Outline and FIN layer exits along with PR boundary
5. From M7-M12, resistance is almost same. Try to route important signals in M8 and above.

6. Long routed (Digital) signals can be routed in M6 and above.

7. Long routed signals > 30um are responsible for antenna effect, so try adding metal jumpers for
signals traveling more than 30um.

8. Advised to add Large VIA wherever possible instead of Large/square VIA

9. Gate contact need to on top/near to OD as possible.

10. Layers like NWell, NPlus, Pplus, LVTN, LVTP (VT layers) should end their x-direction edges at
center of poly (DRC).

11. Different Poly width transition should coincide with CT center.

12. Max width of M1-M3 – 0.2um, M4 – 0.24um

13. Advised to add more Tap connections. Each OD row with a tap connection if possible

14. For a device with more fingers/multipliers, its advised to add 2 parallel tracks for the drain and
source connections on top of device (OD).

15. Dummy devices added should have AUX_PC (indicating dummy device) on poly. The dummy
poly gate must be connected to power (results in Leakage – PERC error)

Don’ts:
1. Total width of parallel long routing signals (Bus) should not exceed more than 3um, to avoid VIA
density in that area, Maintain 1.5X spacing between the long routed signals

2. OD - OD spacing can't exceed 0.54um.

3. Advised to reduce the polylength, cut the poly with cut poly layer.

4. No matching techniques are followed, only the devices which required matching are kept at close
proximity. (Interdigitation and Common centroid will result in lot of parasitics on signal nets)

5. Shielding of high speed clock signals are not advised to use side wall shielding, it might add more
capacitance on the clock net. Try to provide more space between the clock and other signal net.

6. CB (Gate contact) drawn for >1.5u will result in DRC. So Gate connection should be <1.5um. Can
add gate contact on top or bottom to meet DRC requirement.

7. M1 pattern error – maintain spacing between M1 horizontal and M1 vertical <0.006um

8. Only M1 can bend. Rest all layers should be rectangular. Advised not to bend any metals.
5nm Layout learning's – TSMC Foundry:

- Created By: Mahesh N

Information:

1. Gate length – 6nm – Core devices – Voltage (0.96V), Poly pitch – 51, 57, 85 um, Fin-pitch 28nm.
Different Fin Bound layers like FB1, FB9 for different Poly pitch. Metal Stack - 16 Metals

2. Advised width & Spacing for Metal :

Metals Width Spacing

M0: 0.018 0.024
M1: 0.024 0.018
M2: 0.030 0.024
M3: 0.032 0.024
M4: 0.030 0.024
M5: 0.040 0.044
M6: 0.060 0.068

3. Layer Hierarchy.

OD PC

MD MP

VD VG

M0 CM0A, CM0B M0

V0 V0

M1 M1
V1

M2

V2

Do’s:

1. OD must be continuous as possible (add dummy gate if required), minimum 8 dummy gates required
at OD ending followed by a FinCut (FC) layer - To satisfy LOD

2. Maintain even number of poly’s

3. M1,M2 is more resistive, so try routing in M3 and above metals

4. Poly ending must be on 51nm poly pitch irrespective of polypitch.

5. Try to make strong power connections, advised to follow a pitch (alternate metal track for power
routing in each metal) and stack metals for better power supply.

6. Spacing between the FinBound layers FB1,FB9..etc must be followed

7. From M8-M10, resistance is almost same. Try to route important signals in M8 and above.
8. Long routed (Digital) signals can be routed in M8 and above.

7. Long routed signals > 30um are responsible for antenna effect, so try adding metal jumpers for
signals traveling more than 30um.

8. Advised to add Large VIA wherever possible instead of Large/square VIA

9. Gate contact need to on top/near to OD as possible - Lgc check

10. Layers like NWell, NP, PP, LVT_N, LVT_P (VT layers) should end their x-direction edges at
center of poly (DRC).

11. Different Poly width transition should coincide with CT center.

12. Max width of M1-M3 – 0.2um, M4 – 0.24um

13. Advised to add more Tap connections. Each OD row with a tap connection if possible

14. For a device with more fingers/multipliers, its advised to add 2 parallel tracks for the drain and
source connections on top of device (OD).

14. Utilize more tracks in M0. M1 alternatively to power.

15. Dummy devices added should have PODE (indicating dummy device) on poly. The dummy poly
gate must be connected to power (results in Leakage – PERC error)

16. Maintain height of analog cells in terms of 420, 240. As the guard rings cells will be provided by
foundry, else new cells need to be created and DRC need to be taken care
Don’ts:

1. Total width of parallel long routing signals (Bus) should not exceed more than 3um, to avoid VIA
density in that area, Maintain 1.5X spacing between the long routed signals

2. OD - OD spacing can't exceed 0.54um.

3. Advised to reduce the poly length, cut the poly with cut poly layer.

4. No matching techniques are followed, only the devices which required matching are kept at close
proximity. (Interdigitation and Common centroid will result in lot of parasitics on signal nets)

5. Shielding of high speed clock signals are not advised to use side wall shielding, it might add more
capacitance on the clock net. Try to provide more space between the clock and other signal net.

6. VG (Gate contact) drawn for >1.5u will result in DRC. So Gate connection should be <1.5um. Can
add gate contact on top or bottom to meet DRC requirement.

7. OD max length should not exceed 80um.

8. Long poly and MD connections need to be avoided, as it adds more resistance.

9. All metal layers should be rectangular. Advised not to bend any metals.