Microprogrammed Control

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Reference: http://ecl.incheon.ac.kr/
We will study …

 Chapter 7: Microprogrammed Control:

 Control Memory
 Sequencing Microinstructions
 Microprogram Example
 Design of Control Unit
 Microinstruction Format

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Control Unit

 The function of the Control Unit in a digital computer

is to initiate sequences of microoperations.

 Number of different types of microoperations that are

available in a system are finite.

 The complexity of the digital system is derived from

the number of sequences of microoperations that are
performed.

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Comparison of Control Unit
Implementation
 Control Unit Implementation
 Hardwired Control Unit (Combinational Logic Circuits)

 Microprogrammed Control Unit (Control Memory + Microprogram)

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Terminology – (1)
 Microprogram
 Program stored in control memory that generates all the
control signals required to execute the instruction set
correctly
 Consists of microinstructions

 Microinstruction
 Contains a control word and a sequencing word
 Control Word - All the control information required for one
clock cycle
 Sequencing Word - Information needed to decide the next
microinstruction address
 Vocabulary to write a microprogram

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Terminology – (2)
 Control Memory (CM)
 Storage in the microprogrammed control unit to store the
microprogram
 ROM

 Writeable Control Memory

 CM whose contents can be modified
 → Allows the microprogram to be changed

 → Instruction set can be changed or modified

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Terminology – (3)
 Dynamic Microprogramming
 Computer system whose control unit is implemented with a
microprogram in Writable CM
 Microprogram can be changed by a systems programmer,
but not an occasional user.

 Sequencer (Microprogram Sequencer)

 It is a next address generator that determines the
Microinstruction Address to be executed in the next clock
cycle.

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Terminology – (4)
 The general configuration of a microprogrammed
control unit is demonstrated in the following block
diagram

 Control Address Register:

 Specifies the address of the microinstruction to be executed
in the next clock cycle.
 Control Data Register (pipeline register):
 Holds the microinstruction read from the control memory.
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Terminology – (5)
 The microinstruction contains a control word that
specifies one or more microoperations for the data
processor.
 Once these operations are executed, the control
must determine the next address. Thus, some bits of
the present microinstruction are used to control the
generation of the address of the next
microinstruction.

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Microinstruction Sequencing (1)

 Microinstructions are stored in control

memory in groups, with each group
specifying a routine.

 Each computer instruction has its own

microprogram routine in control memory to
generate the microoperations that execute
the instruction.

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Microinstruction Sequencing (2)

 Address Sequencing Capabilities Required in

a Control Memory:
 Incrementing of the control address register (CAR)
 Unconditional branch or conditional branch,
depending on status bit condition
 A mapping process from the bits of the instruction
to an address for control memory
 A facility for subroutine call and return

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Microinstruction Sequencing (3)
 Circuit to determine the Microinstruction Address:

Clock

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Conditional Branching
 Conditional Branch
 If Condition is true, then
Branch (address from
the next address field of
the current
microinstruction)
else Fall Through
(address register is
incremented)
 Conditions to test:
O(overflow),
N(negative), Z(zero),
C(carry), etc.

 Unconditional Branch
 Fixing the value of one
status bit at the input of
the MUX to 1 13
Mapping of Instructions to
Microroutines (1)
 Assume that the op-code has 4 bits (gives 16 distinct
instructions)
 Assume that the control memory has 128 words
(needs 7 bits address)
 For each operation code there exists a microprogram
routine in control memory that executes the
instruction.
 Thus, we need one simple mapping process that
converts the 4-bit operation code to a 7-bit address
for control memory

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Mapping of Instructions to
Microroutines (2)
 Mapping from the opcode of an instruction to the
address of the microinstruction, which is the starting
microinstruction of its execution microprogram
(provides each computer instruction a microprogram
routine with a capacity of four microinstructions)

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Mapping of Instructions to
Microroutines (3)
 Generalization: Mapping function implemented by
ROM
 Input: opcode
 Output: CM address

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 Microprogram Example
 Computer HW Configuration (similar but not identical to Chap 5)
 Two memory units:
 Main memory (2048x16)
 Instructions and Data
 Control memory (128x20)
 Microprogram
 4 registers for processing
 PC, AR, DR, AC
 2 registers for CU
 CAR, SBR
 Info transfer through MUXs
 AR recv from PC and DR
 PC recv from AR
 DR recv from Mem, PC, AC
 Arith, logic, and shift unit
 Process data in DR and AC
 Put result in AC
 Data read from mem can go
only to DR
 Data written to mem comes
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only from DR
Machine Instruction Format

 Machine Instruction Format

 Sample Machine Instruction

 Microinstruction Format

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Microinstruction field – F1, F2, F3, CD,
BR

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Symbolic Microinstructions
 Symbols are used in microinstructions as in assembly language
 A symbolic microprogram can be translated into its binary equivalent by a
microprogram assembler.

 Format
 five fields : label; micro-ops; CD; BR; AD

 Label : empty or specify a symbolic address; terminated with a colon ( : )

 microoperations : consists of one, two, or three symbols separated by
commas
 CD : one of {U,I,S,Z} where
 U : unconditional branch -- always 1

 I : indirect address bit -- DR(15)

 S : sign of AC -- AC(15)

 Z : zero value in AC -- AC=0

 BR : one of {JMP,CALL,RET,MAP}
 AD : one of {symbolic address, NEXT, empty}

 ORG pseudo instr : the origin (first address) of a microprogram routine in CM

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Symbolic Microprogram – Fetch
Routine

 Sequence of microoperations in the fetch cycle

 Symbolic microprogram for the fetch cycle

 Binary equivalents translated by an assembler

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Symbolic Microprogram
 Control Memory : 128 20-bit words
 The first 64 words: Routines for the 16 machine
instructions
 The last 64 words: Used for other purpose (e.g.,
fetch routine and other subroutines)

 Mapping: opcode XXXX into 0XXXX00 the first

address for the 16 routines are :
0(0 0000 00), 4(0 0001 00), 8, 12, 16, 20, ..., 60

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Symbolic Microprogram

 Partial Symbolic Microprogram:

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Binary Microprogram

 This microprogram can be implemented using ROM 24

Design of Control Unit

 Decoding ALU Control Information

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Microprogram Sequencer – (1)

 Next microinstruction address logic :

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Microprogram Sequencer – (2)
 MUX1 selects an address from one of four sources and routes it
into a CAR
 In-line sequencing → CAR + 1
 Branch, or Subroutine call → CM(AD)
 Return from Subroutine → Output of SBR
 New machine instruction → MAP

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Microprogram Sequencer – (3)

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 Microprogram Sequencer – (4)
 Condition BR Input Mean Src of Addr MUX1 Ld SBR
Field I1 I0 T S1 S0 L
and Branch
0 0 0 0 0 In-line CAR + 1 0 0 0
Control:
0 0 0 0 1 JMP CM(AD) 0 1 0
S1 = I 1 0 1 0 1 0 In-line CAR + 1 0 0 0
S0 = I1I0 + I1’T 0 1 0 1 1 CALL CM(AD) and 0 1 1
L = I1’I0T SBR ← CAR+1
1 0 1 0 x RET SBR 1 0 0
1 1 1 1 x MAP DR(11-14) 1 1 0

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