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Ac7050 - SDM - Xc7s50-1fgga484i

This document is a schematic diagram showing the connections between an FPGA chip and other components on a circuit board. It includes labels for the FPGA pins connected to interfaces like JTAG and SPI as well as labels for connections to power supplies, clocks and LED indicators. The schematic is split across two pages with the FPGA and nearby components shown on page 1 and additional components shown on page 2.

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mahimithran16
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0% found this document useful (0 votes)
90 views10 pages

Ac7050 - SDM - Xc7s50-1fgga484i

This document is a schematic diagram showing the connections between an FPGA chip and other components on a circuit board. It includes labels for the FPGA pins connected to interfaces like JTAG and SPI as well as labels for connections to power supplies, clocks and LED indicators. The schematic is split across two pages with the FPGA and nearby components shown on page 1 and additional components shown on page 2.

Uploaded by

mahimithran16
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
Available Formats
Download as PDF, TXT or read online on Scribd
You are on page 1/ 10

5 4 3 2 1

D D

C C

B B

A A

www.alinx.com
Title
PAGE01 BLOCK DIAGRAM

ALINX Confidential Size

Date:
Document Number
AC7050核心板 Schematics
Friday, February 23, 2018 Sheet 1 of 10
Rev
1.0

5 4 3 2 1
5 4 3 2 1

J1

FPGA_TMS 1
FPGA_TDI 2
FPGA_TDO 3
FPGA_TCK 4
5
+3.3V 6
D D

CON6
U1-1
BANK0 N12
DXP_0 N11
DXN_0 L12
VP_0 M11
VN_0
G9 FPGA_TCK 10
TCK_0 Y10 FPGA_TMS FPGA_TCK
TMS_0 FPGA_TMS 10
W10 FPGA_TDO 10 +3.3V +3.3V +1.8V AVCC +1.8V
TDO_0 W9 FPGA_TDI FPGA_TDO
TDI_0 FPGA_TDI 10
T9 R1 4.7K
INIT_B_0 U11 R2 4.7K
PROGRAM_B_0 V11
CFGBVS_0 U9 FPGA_DONE
DONE_0
M12
VREFP_0 L11
VREFN_0
E9 600Ohm@100MHz L1
VCCBATT_0 K11
VCCADC_0
T11 FPGA_M0 R3 1K
M0_0 T10 FPGA_M1
M1_0 U10 FPGA_M2
M2_0
C D9 QSPI_CLK 8 C1 C2 C
CCLK_0 QSPI_CLK 0.1uF 470nf
K12
GNDADC_0

xc7s50fgga484
MASTER SPI x4
AGND AGND M[2:0] = 001

L2 600Ohm@100MHz

AGND

B B

+3.3V FPGA DONE LED +3.3V


POWER LEDD1
D2
R4 220
R5 220 FPGA_DONE R6 330
LED
LED

A A

www.alinx.com
Title
PAGE02 FPGA BANK0

ALINX Confidential Size

Date:
Document Number
AC7050核心板 Schematics
Friday, February 23, 2018 Sheet 2 of 10
Rev
1.0

5 4 3 2 1
5 4 3 2 1

D D

+3.3V

X2
4 3 R60 33 CLK_50MHZ
VCC OUT
R61 1K 1 2
C149 OE GND
50MHz
0.1uF

PUDC_B=1: Deactive internal Pull up Resister U1-2


BANK14
10 B14_IO0 N15 P15 CLK_50MHZ
+3.3V B14_IO0 QSPI_DQ0 M21 IO_0_14 IO_L13P_T2_MRCC_14 P16
8 QSPI_DQ0 IO_L1P_T0_D00_MOSI_14 IO_L13N_T2_MRCC_14
8 QSPI_DQ1 M22 P17 B14_L14_P 10
QSPI_DQ1 IO_L1N_T0_D01_DIN_14 IO_L14P_T2_SRCC_14 B14_L14_P
8 QSPI_DQ2 N21 R18 B14_L14_N 10
QSPI_DQ2 IO_L2P_T0_D02_14 IO_L14N_T2_SRCC_14 B14_L14_N
8 QSPI_DQ3 N22 T17 B14_L15_P 10
QSPI_DQ3 IO_L2N_T0_D03_14 IO_L15P_T2_DQS_RDWR_B_14 B14_L15_P
B14_L3_P M19 U17 B14_L15_N 10
IO_L3P_T0_DQS_PUDC_B_14 IO_L15N_T2_DQS_DOUT_CSO_B_14 B14_L15_N
C R7 1K B14_L3_P N19 R16 B14_L16_P 10 C
IO_L3N_T0_DQS_EMCCLK_14 IO_L16P_T2_CSI_B_14 B14_L16_P
10 B14_L4_P P21 R17 B14_L16_N 10
B14_L4_P IO_L4P_T0_D04_14 IO_L16N_T2_D31_14 B14_L16_N
10 B14_L4_N P22 R19 B14_L17_P 10
B14_L4_N IO_L4N_T0_D05_14 IO_L17P_T2_D30_14 B14_L17_P
10 B14_L5_P N20 R20 B14_L17_N 10
B14_L5_P IO_L5P_T0_D06_14 IO_L17N_T2_D29_14 B14_L17_N
10 B14_L5_N P20 T19 B14_L18_P 10
B14_L5_N IO_L5N_T0_D07_14 IO_L18P_T2_D28_14 B14_L18_P
8 QSPI_CS N17 T20 B14_L18_N 10
QSPI_CS IO_L6P_T0_FCS_B_14 IO_L18N_T2_D27_14 B14_L18_N
N18 Y20 B14_L19_P 10
IO_L6N_T0_D08_VREF_14 IO_L19P_T3_D26_14 B14_L19_P
10 B14_L7_P T21 AA20 B14_L19_N 10
B14_L7_P IO_L7P_T1_D09_14 IO_L19N_T3_D25_VREF_14 B14_L19_N
10 B14_L7_N T22 Y22 B14_L20_P 10
B14_L7_N IO_L7N_T1_D10_14 IO_L20P_T3_D24_14 B14_L20_P
10 B14_L8_P V21 AA22 B14_L20_N 10
B14_L8_P IO_L8P_T1_D11_14 IO_L20N_T3_D23_14 B14_L20_N
10 B14_L8_N W22 W18 B14_L21_P 10
B14_L8_N IO_L8N_T1_D12_14 IO_L21P_T3_DQS_14 B14_L21_P
10 B14_L9_P U22 Y19 B14_L21_N 10
B14_L9_P IO_L9P_T1_DQS_14 IO_L21N_T3_DQS_D22_14 B14_L21_N
10 B14_L9_N V22 AA21 B14_L22_P 10
B14_L9_N IO_L9N_T1_DQS_D13_14 IO_L22P_T3_D21_14 B14_L22_P
10 B14_L10_P W21 AB21 B14_L22_N 10
B14_L10_P IO_L10P_T1_D14_14 IO_L22N_T3_D20_14 B14_L22_N
10 B14_L10_N Y21 AB19 B14_L23_P 10
B14_L10_N IO_L10N_T1_D15_14 IO_L23P_T3_D19_14 B14_L23_P
10 B14_L11_P U20 AB20 B14_L23_N 10
B14_L11_P IO_L11P_T1_SRCC_14 IO_L23N_T3_D18_14 B14_L23_N
10 B14_L11_N V20 V18 B14_L24_P 10
B14_L11_N IO_L11N_T1_SRCC_14 IO_L24P_T3_D17_14 B14_L24_P
10 B14_L12_P U18 V19 B14_L24_N 10
B14_L12_P IO_L12P_T1_MRCC_14 IO_L24N_T3_D16_14 B14_L24_N
10 B14_L12_N U19 T16
B14_L12_N IO_L12N_T1_MRCC_14 IO_25_14

xc7s50fgga484

B B

A A

www.alinx.com
Title
PAGE03 FPGA BANK14

ALINX Confidential Size

Date:
Document Number
AC7050核心板 Schematics
Friday, February 23, 2018 Sheet 3 of 10
Rev
1.0

5 4 3 2 1
5 4 3 2 1

D D

U1-3
BANK15
A21 M15 B15_L13_P 10
IO_0_15 IO_L13P_T2_MRCC_15 B15_L13_P
F17 L15 B15_L13_N 10
IO_L1P_T0_AD0P_15 IO_L13N_T2_MRCC_15 B15_L13_N
F18 M17 B15_L14_P 10
IO_L1N_T0_AD0N_15 IO_L14P_T2_SRCC_15 B15_L14_P
H17 M18 B15_L14_N 10
IO_L2P_T0_AD8P_15 IO_L14N_T2_SRCC_15 B15_L14_N
G17 L16
J17 IO_L2N_T0_AD8N_15 IO_L15P_T2_DQS_15 K17
H18 IO_L3P_T0_DQS_AD1P_15 IO_L15N_T2_DQS_15 K18 B15_L16_P
IO_L3N_T0_DQS_AD1N_15 IO_L16P_T2_15 B15_L16_P 10
10 B15_L4_P H16 K19 B15_L16_N 10
B15_L4_P IO_L4P_T0_15 IO_L16N_T2_15 B15_L16_N
10 B15_L4_N G16 J19
B15_L4_N B15_L5_P K16 IO_L4N_T0_15 IO_L17P_T2_15 J20
10 B15_L5_P IO_L5P_T0_AD9P_15 IO_L17N_T2_15
10 B15_L5_N J16 L18
B15_L5_N B15_L6_P K15 IO_L5N_T0_AD9N_15 IO_L18P_T2_15 L19
10 B15_L6_P IO_L6P_T0_15 IO_L18N_T2_15
10 B15_L6_N J15 H19
B15_L6_N B15_L7_P B21 IO_L6N_T0_VREF_15 IO_L19P_T3_15 G20
10 B15_L7_P IO_L7P_T1_AD2P_15 IO_L19N_T3_VREF_15
10 B15_L7_N B22 G21 B15_L20_P 10
B15_L7_N IO_L7N_T1_AD2N_15 IO_L20P_T3_15 B15_L20_P
10 B15_L8_P D20 G22 B15_L20_N 10
B15_L8_P IO_L8P_T1_AD10P_15 IO_L20N_T3_15 B15_L20_N
10 B15_L8_N C20 H20
B15_L8_N B15_L9_P D21 IO_L8N_T1_AD10N_15 IO_L21P_T3_DQS_15 H21
10 B15_L9_P IO_L9P_T1_DQS_AD3P_15 IO_L21N_T3_DQS_15
10 B15_L9_N C22 L22
B15_L9_N B15_L10_P E22 IO_L9N_T1_DQS_AD3N_15 IO_L22P_T3_15 K22
10 B15_L10_P IO_L10P_T1_AD11P_15 IO_L22N_T3_15
10 B15_L10_N D22 J21
B15_L10_N B15_L11_P F21 IO_L10N_T1_AD11N_15 IO_L23P_T3_15 J22
10 B15_L11_P IO_L11P_T1_SRCC_15 IO_L23N_T3_15
10 B15_L11_N F22 L20
B15_L11_N IO_L11N_T1_SRCC_15 IO_L24P_T3_RS1_15
C 10 B15_L12_P F19 L21 C
B15_L12_P IO_L12P_T1_MRCC_15 IO_L24N_T3_RS0_15
10 B15_L12_N F20 M16
B15_L12_N IO_L12N_T1_MRCC_15 IO_25_15

xc7s50fgga484

U1-4
BANK16
10 B16_IO0 G13 C15 B16_L13_P 10
B16_IO0 IO_0_16 IO_L13P_T2_MRCC_16 B16_L13_P
10 B16_L1_P G11 C16 B16_L13_N 10
B16_L1_P IO_L1P_T0_16 IO_L13N_T2_MRCC_16 B16_L13_N
10 B16_L1_N F11 B15 B16_L14_P 10
B16_L1_N IO_L1N_T0_16 IO_L14P_T2_SRCC_16 B16_L14_P
B16_L2_P G10 B16 B16_L14_N
10
10
B16_L2_P
B16_L2_N
B16_L2_N F10
E11
IO_L2P_T0_16
IO_L2N_T0_16
IO_L14N_T2_SRCC_16
IO_L15P_T2_DQS_16
D16
C17
B16_L15_P
B16_L14_N
B16_L15_P
10
10
USER LED
10 B16_L3_P B16_L15_N 10
B16_L3_P IO_L3P_T0_DQS_16 IO_L15N_T2_DQS_16 B16_L15_N
10 B16_L3_N D11 E15 B16_L16_P 10
B16_L3_N IO_L3N_T0_DQS_16 IO_L16P_T2_16 B16_L16_P
10 B16_L4_P F13 E16 B16_L16_N 10
B B16_L4_P IO_L4P_T0_16 IO_L16N_T2_16 B16_L16_N B
10 B16_L4_N F14 B14 B16_L17_P 10
B16_L4_N IO_L4N_T0_16 IO_L17P_T2_16 B16_L17_P VCCIO
10 B16_L5_P F12 A14 B16_L17_N 10
B16_L5_P IO_L5P_T0_16 IO_L17N_T2_16 B16_L17_N
10 B16_L5_N E12 A16 B16_L18_P 10
B16_L5_N IO_L5N_T0_16 IO_L18P_T2_16 B16_L18_P
10 B16_L6_P G14 A17 B16_L18_N 10
B16_L6_P IO_L6P_T0_16 IO_L18N_T2_16 B16_L18_N
10 B16_L6_N F15 D18 B16_L19_P 10 D3
B16_L6_N IO_L6N_T0_VREF_16 IO_L19P_T3_16 B16_L19_P
10 B16_L7_P D13 C18 B16_L19_N 10 LED
B16_L7_P IO_L7P_T1_16 IO_L19N_T3_VREF_16 B16_L19_N
10 B16_L7_N C13 C19 B16_L20_P 10
B16_L7_N IO_L7N_T1_16 IO_L20P_T3_16 B16_L20_P
10 B16_L8_P A11 B19 B16_L20_N 10
B16_L8_P IO_L8P_T1_16 IO_L20N_T3_16 B16_L20_N
10 B16_L8_N A12 A18 B16_L21_P 10
B16_L8_N IO_L8N_T1_16 IO_L21P_T3_DQS_16 B16_L21_P
10 B16_L9_P B13 A19 B16_L21_N 10
B16_L9_P IO_L9P_T1_DQS_16 IO_L21N_T3_DQS_16 B16_L21_N
10 B16_L9_N A13 E17 B16_L22_P 10 R13
B16_L9_N IO_L9N_T1_DQS_16 IO_L22P_T3_16 B16_L22_P
10 B16_L10_P C10 E18 B16_L22_N 10 220
B16_L10_P IO_L10P_T1_16 IO_L22N_T3_16 B16_L22_N
10 B16_L10_N C11 B20 B16_L23_P 10
B16_L10_N IO_L10N_T1_16 IO_L23P_T3_16 B16_L23_P
10 B16_L11_P D14 A20 B16_L23_N 10
B16_L11_P IO_L11P_T1_SRCC_16 IO_L23N_T3_16 B16_L23_N
10 B16_L11_N D15 E19 B16_L24_P 10
B16_L11_N IO_L11N_T1_SRCC_16 IO_L24P_T3_16 B16_L24_P
10 B16_L12_P D12 D19 B16_L24_N 10
B16_L12_P IO_L12P_T1_MRCC_16 IO_L24N_T3_16 B16_L24_N
10 B16_L12_N C12 G15 LED1
B16_L12_N IO_L12N_T1_MRCC_16 IO_25_16

xc7s50fgga484

A A

www.alinx.com
Title
PAGE04 FPGA BANK15/16

ALINX Confidential Size

Date:
Document Number
AC7050核心板 Schematics
Friday, February 23, 2018 Sheet 4 of 10
Rev
1.0

5 4 3 2 1
5 4 3 2 1

+1.5V +1.5V

R8 R9
U1-5 10K 10K
R10
D BANK34 100 1% D
R2 AA6 SYS_CLK_P 8
IO_0_34 IO_L13P_T2_MRCC_34 SYS_CLK_P
7 DDR3_A4 DDR3_A4 W5 AB6 SYS_CLK_N 8
IO_L1P_T0_34 IO_L13N_T2_MRCC_34 SYS_CLK_N
7 DDR3_A8 W4 Y6 DDR3_A9 7
DDR3_A8 IO_L1N_T0_34 IO_L14P_T2_SRCC_34 DDR3_A9
7 DDR3_A3 T7 Y5 DDR3_A10 7
DDR3_A3 IO_L2P_T0_34 IO_L14N_T2_SRCC_34 DDR3_A10
7 DDR3_A5 T6 Y4 DDR3_A14 7
DDR3_A5 IO_L2N_T0_34 IO_L15P_T2_DQS_34 DDR3_A14
V5 AA3 R11 R12
DDR3_CKE0 V4 IO_L3P_T0_DQS_34 IO_L15N_T2_DQS_34 AB3 10K 10K
7 DDR3_CKE0 IO_L3N_T0_DQS_34 IO_L16P_T2_34
7 DDR3_A2 T5 AB2 RESET_N
DDR3_A2 DDR3_A7 U5 IO_L4P_T0_34 IO_L16N_T2_34 AA2
7 DDR3_A7 IO_L4N_T0_34 IO_L17P_T2_34
7 DDR3_RAS V7 AA1 DDR3_RESET 7
DDR3_RAS DDR3_ODT V6 IO_L5P_T0_34 IO_L17N_T2_34 AB5 DDR3_RESET
7 DDR3_ODT IO_L5N_T0_34 IO_L18P_T2_34
7 DDR3_CAS T8 AB4
DDR3_CAS DDR3_WE U8 IO_L6P_T0_34 IO_L18N_T2_34 V8
7 DDR3_WE IO_L6N_T0_VREF_34 IO_L19P_T3_34
7 DDR3_S0 V1 W8
DDR3_S0 DDR3_A6 W1 IO_L7P_T1_34 IO_L19N_T3_VREF_34 Y8
7 DDR3_A6 IO_L7N_T1_34 IO_L20P_T3_34
7 DDR3_A11 W2 AA8
DDR3_A11 IO_L8P_T1_34 IO_L20N_T3_34
7 DDR3_BA0 Y1 W7
DDR3_BA0 IO_L8N_T1_34 IO_L21P_T3_DQS_34
7 DDR3_BA1 U2 Y7
DDR3_BA1 DDR3_A12 U1 IO_L9P_T1_DQS_34 IO_L21N_T3_DQS_34 AA10
7 DDR3_A12 IO_L9N_T1_DQS_34 IO_L22P_T3_34
7 DDR3_BA2 W3 AB10
DDR3_BA2 IO_L10P_T1_34 IO_L22N_T3_34
7 DDR3_A0 Y3 AA7
DDR3_A0 IO_L10N_T1_34 IO_L23P_T3_34
7 DDR3_A13 U4 AB7
DDR3_A13 IO_L11P_T1_SRCC_34 IO_L23N_T3_34
7 DDR3_A1 U3 AA9
DDR3_A1 IO_L11N_T1_SRCC_34 IO_L24P_T3_34
7 DDR3_CLK0_P T3 AB9
DDR3_CLK0_P DDR3_CLK0_N T2 IO_L12P_T1_MRCC_34 IO_L24N_T3_34 T1
7 DDR3_CLK0_N IO_L12N_T1_MRCC_34 IO_25_34

C xc7s50fgga484 C

U1-6

VTTREF
BANK35 VTTREF
H7
DDR3_D7 J3 IO_0_35 M4 DDR3_DM2
7 DDR3_D7 IO_L1P_T0_AD4P_35 IO_L13P_T2_MRCC_35 DDR3_DM2 7
7 DDR3_D0 H2 M3 DDR3_D22 7
DDR3_D0 DDR3_D6 H4 IO_L1N_T0_AD4N_35 IO_L13N_T2_MRCC_35 L1 DDR3_D16 DDR3_D22
7 DDR3_D6 IO_L2P_T0_AD12P_35 IO_L14P_T2_SRCC_35 DDR3_D16 7
7 DDR3_D2 H3 K1 DDR3_D18 7
DDR3_D2 DDR3_DQS0_P J2 IO_L2N_T0_AD12N_35 IO_L14N_T2_SRCC_35 M2 DDR3_DQS2_P DDR3_D18
7 DDR3_DQS0_P IO_L3P_T0_DQS_AD5P_35 IO_L15P_T2_DQS_35 DDR3_DQS2_P 7
7 DDR3_DQS0_N J1 M1 DDR3_DQS2_N 7
C3 DDR3_DQS0_N DDR3_DM0 K3 IO_L3N_T0_DQS_AD5N_35 IO_L15N_T2_DQS_35 N4 DDR3_D19 DDR3_DQS2_N
7 DDR3_DM0 IO_L4P_T0_35 IO_L16P_T2_35 DDR3_D19 7
0.1uF 7 DDR3_D1 K2 N3 DDR3_D23 7
DDR3_D1 DDR3_D3 H6 IO_L4N_T0_35 IO_L16N_T2_35 P1 DDR3_D21 DDR3_D23 C4
7 DDR3_D3 IO_L5P_T0_AD13P_35 IO_L17P_T2_35 DDR3_D21 7
7 DDR3_D4 H5 N1 DDR3_D20 7 0.1uF
DDR3_D4 DDR3_D5 K6 IO_L5N_T0_AD13N_35 IO_L17N_T2_35 P3 DDR3_D17 DDR3_D20
7 DDR3_D5 IO_L6P_T0_35 IO_L18P_T2_35 DDR3_D17 7
J6 P2
B
DDR3_D11 J8 IO_L6N_T0_VREF_35 IO_L18N_T2_35 P8 DDR3_D30 B
7 DDR3_D11 IO_L7P_T1_AD6P_35 IO_L19P_T3_35 DDR3_D30 7
7 DDR3_D15 J7 N8
DDR3_D15 IO_L7N_T1_AD6N_35 IO_L19N_T3_VREF_35
7 DDR3_DM1 L7 N5 DDR3_D27 7
DDR3_DM1 IO_L8P_T1_AD14P_35 IO_L20P_T3_35 DDR3_D27
7 DDR3_D10 L6 M5 DDR3_DM3 7
DDR3_D10 IO_L8N_T1_AD14N_35 IO_L20N_T3_35 DDR3_DM3
7 DDR3_DQS1_P L5 P6 DDR3_DQS3_P 7
DDR3_DQS1_P IO_L9P_T1_DQS_AD7P_35 IO_L21P_T3_DQS_35 DDR3_DQS3_P
7 DDR3_DQS1_N K5 N6 DDR3_DQS3_N 7
DDR3_DQS1_N IO_L9N_T1_DQS_AD7N_35 IO_L21N_T3_DQS_35 DDR3_DQS3_N
7 DDR3_D14 L4 P7 DDR3_D26 7
DDR3_D14 IO_L10P_T1_AD15P_35 IO_L22P_T3_35 DDR3_D26
7 DDR3_D12 K4 N7 DDR3_D29 7
DDR3_D12 IO_L10N_T1_AD15N_35 IO_L22N_T3_35 DDR3_D29
DDR3_D9 L8 R7 DDR3_D28
7
7
DDR3_D9
DDR3_D13
DDR3_D13 K8 IO_L11P_T1_SRCC_35
IO_L11N_T1_SRCC_35
IO_L23P_T3_35
IO_L23N_T3_35
R6 DDR3_D25
DDR3_D28
DDR3_D25
7
7
RESET KEY
7 DDR3_D8 M8 R5 DDR3_D31 7
DDR3_D8 IO_L12P_T1_MRCC_35 IO_L24P_T3_35 DDR3_D31
M7 R4 DDR3_D24 7
IO_L12N_T1_MRCC_35 IO_L24N_T3_35 R3 DDR3_D24 +1.5V
IO_25_35

xc7s50fgga484 R15
1K
KEY1

RESET_N 1 2
P1 P2

Button

A A

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Title
PAGE05 FPGA BANK34/35

ALINX Confidential Size

Date:
Document Number
AC7050核心板 Schematics
Friday, February 23, 2018 Sheet 5 of 10
Rev
1.0

5 4 3 2 1
5 4 3 2 1

U1-8 U1-9
A1 M6 B5 B10
A8 GND GND M10 E7 NC1 NC47 A10
A15 GND GND M14 F3 NC2 NC48 C9
A22 GND GND M20 U13 NC3 NC49 C8
B4 GND GND N2 Y15 NC4 NC50 A7
B11 GND GND N9 T15 NC5 NC51 A6
B18 GND GND N13 T14 NC6 NC52 B8
+1.0V U1-7 +3.3V C7 GND GND N16 U15 NC7 NC53 B7
C14 GND GND P5 T12 NC8 NC54 D8
H11 C21 GND GND P10 T13 NC9 NC55 D7
H13 VCCINT E10 D3 GND GND P12 V14 NC10 NC56 C6
J10 VCCINT VCCO_0 V9 D10 GND GND P14 V15 NC11 NC57 C5
J12 VCCINT VCCO_0 VCCIO D17 GND GND P19 U12 NC12 NC58 D6
D
K13 VCCINT R21 E6 GND GND R1 V13 NC13 NC59 D5 D
L10 VCCINT VCCO_14 P18 E13 GND GND R8 W15 NC14 NC60 G8
M13 VCCINT VCCO_14 W19 E20 GND GND R9 W16 NC15 NC61 F8
N10 VCCINT VCCO_14 F2 GND GND R11 U16 NC16 NC62 F5
P11 VCCINT E21 F9 GND GND R13 V16 NC17 NC63 E5
P13 VCCINT VCCO_15 G18 F16 GND GND R15 Y18 NC18 NC64 G7
R10 VCCINT VCCO_15 K20 G5 GND GND R22 AA18 NC19 NC65 G6
+1.8V R12 VCCINT VCCO_15 G12 GND GND T4 AA17 NC20 NC66 F7
VCCINT B12 G19 GND GND T18 AB18 NC21 NC67 F6
J14 VCCO_16 B17 H1 GND GND U7 AA15 NC22 NC68 B6
L14 VCCAUX VCCO_16 E14 +1.5V H8 GND GND U14 AA16 NC23 NC69 A5
+1.0V N14 VCCAUX VCCO_16 H10 GND GND U21 AB16 NC24 NC70 A4
R14 VCCAUX U6 H12 GND GND V3 AB17 NC25 NC71 A3
VCCAUX VCCO_34 V2 H14 GND GND V10 W17 NC26 NC72 B3
H9 VCCO_34 AA4 H15 GND GND V17 Y17 NC27 NC73 A2
K9 VCCBRAM VCCO_34 J5 H22 GND GND W6 AA14 NC28 NC74 C4
M9 VCCBRAM VCCO_35 L2 J4 GND GND W13 AB14 NC29 NC75 C3
P9 VCCBRAM VCCO_35 P4 J9 GND GND W20 V12 NC30 NC76 B2
VCCBRAM VCCO_35 J11 GND GND Y2 W12 NC31 NC77 B1
J13 GND GND Y9 W14 NC32 NC78 C2
J18 GND GND Y16 Y14 NC33 NC79 C1
xc7s50fgga484 K7 GND GND AA5 AA13 NC34 NC80 G4
K10 GND GND AA12 AB13 NC35 NC81 G3
K14 GND GND AA19 W11 NC36 NC82 E4
K21 GND GND AB1 Y11 NC37 NC83 D4
L3 GND GND AB8 AB11 NC38 NC84 F1
L9 GND GND AB15 AB12 NC39 NC85 E1
L13 GND GND AB22 Y12 NC40 NC86 G2
L17 GND GND Y13 NC41 NC87 G1
GND AA11 NC42 NC88 E3
C C
E8 NC43 NC89 D2
B9 NC44 NC90 E2
xc7s50fgga484 A9 NC45 NC91 D1
NC46 NC92 F4
NC93

xc7s50fgga484

+1.5V +1.0V
For VCCINT
+3.3V For VCCO_34
For VCCO_14
C5 C6 C7 C8 C9 C10 C11 C12 C13 C14
C15 C16 C17 C18 C19 C20 C26 4.7uF 4.7uF 470nF 470nF 470nF 470nF 100uF 100uF 100uF 100uF
47uF 4.7uF 4.7uF 470nF 470nF 470nF 470nF

+1.0V
VCCIO +1.5V
For VCCO_15 For VCCO_35
B B
C21 C22 C23 C24 C25 C33
C34 C35 C44 C45 C46 C47 C48 C27 C28 C29 C30 C31 C32 4.7uF 4.7uF 4.7uF 4.7uF 4.7uF 4.7uF
47uF 4.7uF 4.7uF 470nF 470nF 470nF 470nF 4.7uF 4.7uF 470nF 470nF 470nF 470nF

+1.0V

VCCIO +1.8V For VCCAUX C36 C37 C38 C39 C40 C41 C42 C43
For VCCO_16 470nF 470nF 470nF 470nF 470nF 470nF 470nF 470nF

C51 C52 C53 C54 C55 C56 C57 C49 C50 C61 C62 C63 C64 C65 C66 C67
47uF 4.7uF 4.7uF 470nF 470nF 470nF 470nF 47uF 4.7uF 4.7uF 4.7uF 470nF 470nF 470nF 470nF 470nF

+1.0V
For VCCBRAM

C58 C59 C60


100uF 470nF 470nF

A A

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Title
PAGE06 FPGA Power

ALINX Confidential Size

Date:
Document Number
AC7050核心板 Schematics
Friday, February 23, 2018 Sheet 6 of 10
Rev
1.0

5 4 3 2 1
5 4 3 2 1

VTTREF
VTTREF

DDRVTT

C70 C71 C72 C73 C74 C75 C76 C77 C78 C79 C80
4.7uF 4.7uF 4.7uF 4.7uF 0.1uF 0.1uF 0.1uF 0.01uF 0.01uF 4.7uF 47nF C68 C69
4.7uF 47nF

+1.5V VTTREF +1.5V +1.5V VTTREF +1.5V


D D

C81 C82
0.01uF 0.01uF

DDRVTT
C83 C84
R16 49.9 0.01uF 0.01uF

M8

M8
G7

G7
H1

C1
C9
D2

H2
H9

D9

N1
N9
R1
R9

H1

C1
C9
D2

H2
H9

D9

N1
N9
R1
R9
DDR3_A0

A1
A8

E9

B2

K2
K8

A1
A8

E9

B2

K2
K8
F1

F1
R17 49.9 U3 U2
DDR3_A1

VREFDQ

VREFDQ
VREFCA

VREFCA
VDDQ1
VDDQ2
VDDQ3
VDDQ4
VDDQ5
VDDQ6
VDDQ7
VDDQ8
VDDQ9

VDD1
VDD2
VDD3
VDD4
VDD5
VDD6
VDD7
VDD8
VDD9

VDDQ1
VDDQ2
VDDQ3
VDDQ4
VDDQ5
VDDQ6
VDDQ7
VDDQ8
VDDQ9

VDD1
VDD2
VDD3
VDD4
VDD5
VDD6
VDD7
VDD8
VDD9
R21 49.9
DDR3_A2 DDR3_A0 5 N3 E3 DDR3_D0 5 DDR3_A0 N3 E3 DDR3_D16 5
DDR3_A0 A0 DQ0 DDR3_D0 A0 DQ0 DDR3_D16
R18 49.9 DDR3_A1 5 P7 F7 DDR3_D1 5 DDR3_A1 P7 F7 DDR3_D17 5
DDR3_A1 A1 DQ1 DDR3_D1 A1 DQ1 DDR3_D17
DDR3_A3 DDR3_A2 5 P3 F2 DDR3_D2 5 DDR3_A2 P3 F2 DDR3_D18 5
DDR3_A2 A2 DQ2 DDR3_D2 A2 DQ2 DDR3_D18
R20 49.9 DDR3_A3 5 N2 F8 DDR3_D3 5 DDR3_A3 N2 F8 DDR3_D19 5
DDR3_A3 A3 DQ3 DDR3_D3 A3 DQ3 DDR3_D19
DDR3_A4 DDR3_A4 5 P8 H3 DDR3_D4 5 DDR3_A4 P8 H3 DDR3_D20 5
DDR3_A4 A4 DQ4 DDR3_D4 A4 DQ4 DDR3_D20
R19 49.9 DDR3_A5 5 P2 H8 DDR3_D5 5 DDR3_A5 P2 H8 DDR3_D21 5
DDR3_A5 A5 DQ5 DDR3_D5 A5 DQ5 DDR3_D21
DDR3_A5 DDR3_A6 5 R8 G2 DDR3_D6 5 DDR3_A6 R8 G2 DDR3_D22 5
DDR3_A6 A6 DQ6 DDR3_D6 A6 DQ6 DDR3_D22
R22 49.9 DDR3_A7 5 R2 H7 DDR3_D7 5 DDR3_A7 R2 H7 DDR3_D23 5
DDR3_A7 A7 DQ7 DDR3_D7 A7 DQ7 DDR3_D23
DDR3_A6 DDR3_A8 5 T8 D7 DDR3_D8 5 DDR3_A8 T8 D7 DDR3_D24 5
DDR3_A8 A8 DQ8 DDR3_D8 A8 DQ8 DDR3_D24
R23 49.9 DDR3_A9 5 R3 C3 DDR3_D9 5 DDR3_A9 R3 C3 DDR3_D25 5
DDR3_A9 A9 DQ9 DDR3_D9 A9 DQ9 DDR3_D25
DDR3_A7 DDR3_A10 5 L7 C8 DDR3_D10 5 DDR3_A10 L7 C8 DDR3_D26 5
DDR3_A10 A10/AP DQ10 DDR3_D10 A10/AP DQ10 DDR3_D26
R24 49.9 DDR3_A11 5 R7 C2 DDR3_D11 5 DDR3_A11 R7 C2 DDR3_D27 5
DDR3_A11 A11 DQ11 DDR3_D11 A11 DQ11 DDR3_D27
DDR3_A8 DDR3_A12 5 N7 A7 DDR3_D12 5 DDR3_A12 N7 A7 DDR3_D28 5
DDR3_A12 A12/BC# DQ12 DDR3_D12 A12/BC# DQ12 DDR3_D28
R25 49.9 DDR3_A13 5 T3 A2 DDR3_D13 5 DDR3_A13 T3 A2 DDR3_D29 5
DDR3_A13 A13 DQ13 DDR3_D13 A13 DQ13 DDR3_D29
DDR3_A9 DDR3_A14 5 T7 B8 DDR3_D14 5 DDR3_A14 T7 B8 DDR3_D30 5
DDR3_A14 A14 DQ14 DDR3_D14 A14 DQ14 DDR3_D30
R26 49.9 A3 DDR3_D15 5 A3 DDR3_D31 5
DQ15 DDR3_D15 DQ15 DDR3_D31
DDR3_A10 DDR3_BA0 5 M2 DDR3_BA0 M2
DDR3_BA0 BA0 BA0
R27 49.9 DDR3_BA1 5 N8 F3 DDR3_DQS0_P 5 DDR3_BA1 N8 F3 DDR3_DQS2_P 5
DDR3_BA1 BA1 LDQS DDR3_DQS0_P BA1 LDQS DDR3_DQS2_P
C DDR3_A11 DDR3_BA2 5 M3 G3 DDR3_DQS0_N 5 DDR3_BA2 M3 G3 DDR3_DQS2_N 5 C
DDR3_BA2 BA2 LDQS DDR3_DQS0_N BA2 LDQS DDR3_DQS2_N
R28 49.9
DDR3_A12 C7 DDR3_DQS1_P 5 C7 DDR3_DQS3_P 5
UDQS DDR3_DQS1_P UDQS DDR3_DQS3_P
R29 49.9 DDR3_CLK0_P J7 B7 DDR3_DQS1_N 5 DDR3_CLK0_P J7 B7 DDR3_DQS3_N 5
CLK_P UDQS DDR3_DQS1_N CLK_P UDQS DDR3_DQS3_N
DDR3_A13 DDR3_CLK0_N K7 DDR3_CLK0_N K7
R30 49.9 DDR3_CKE0 5 K9 CLK_N E7 DDR3_DM0 DDR3_CKE0 K9 CLK_N E7 DDR3_DM2
DDR3_CKE0 CKE LDM DDR3_DM0 5 CKE LDM DDR3_DM2 5
DDR3_A14 D3 DDR3_DM1 5 D3 DDR3_DM3 5
UDM DDR3_DM1 UDM DDR3_DM3
R31 49.9 DDR3_S0 5 L2 DDR3_S0 L2
DDR3_S0 CS CS
DDR3_BA0 DDR3_RAS 5 J3 L8 DDR3_RAS J3 L8
DDR3_RAS RAS ZQ RAS ZQ
R32 49.9 DDR3_CAS 5 K3 DDR3_CAS K3
DDR3_CAS CAS CAS
DDR3_BA1 DDR3_WE 5 L3 J1 DDR3_WE L3 J1
DDR3_WE WE NC1 WE NC1
R33 49.9 J9 J9
DDR3_BA2 DDR3_ODT K1 NC2 L1 DDR3_ODT K1 NC2 L1
DDR3_ODT 5 ODT NC3 ODT NC3
R34 49.9 L9 L9
DDR3_S0 T2 NC4 M7 DDR3_RESET T2 NC4 M7
DDR3_RESET 5 RESET# NC5 RESET# NC5
R36 49.9 R38 R35
VSSQ1
VSSQ2
VSSQ3
VSSQ4
VSSQ5
VSSQ6
VSSQ7
VSSQ8
VSSQ9

VSSQ1
VSSQ2
VSSQ3
VSSQ4
VSSQ5
VSSQ6
VSSQ7
VSSQ8
VSSQ9
VSS10
VSS11
VSS12

VSS10
VSS11
VSS12
VSS1
VSS2
VSS3
VSS4
VSS5
VSS6
VSS7
VSS8
VSS9

VSS1
VSS2
VSS3
VSS4
VSS5
VSS6
VSS7
VSS8
VSS9
DDR3_RAS R37 240 1% 240 1%
R39 49.9 4.7K R0402
DDR3_CAS
R40 49.9
B1
B9
D1
D8
E2
E8
F9
G1
G9

A9
B3
E1
G8
J2
J8
M1
M9
P1
P9
T1
T9

B1
B9
D1
D8
E2
E8
F9
G1
G9

A9
B3
E1
G8
J2
J8
M1
M9
P1
P9
T1
T9
DDR3_WE MT41J256M16HA-125 MT41J256M16HA-125
R41 49.9
DDR3_ODT
R42 49.9
DDR3_CKE0

R58 49.9 +1.5V


DDR3_CLK0_P 5
DDR3_CLK0_P
B C150 B
DDR POWER For VTT/VREF
R59 49.9 +3.3V VTTREF
DDR3_CLK0_N 5 0.01uF DDRVTT +1.5V
DDR3_CLK0_N
R44 10K 1% C86
C85 U4 4.7uF
0.01uF
R45 10K 1% 1 10
2 REFIN VIN 9 R46 100K
3 VLDOIN PGOOD 8
4 VO GND 7
PWRGND

C89 C90 5 PGND EN 6


C87 C88 10uF 10uF VOSNS REFOUT C92 C93
10uF 100uF C91 0.1uF 4.7uF
4.7uF
11

TPS51200DRCR

+1.5V +1.5V

A C94 C95 C96 C97 C98 C99 C100 C101 C102 C103 C104 C105 C106 C107 C108 C109 C110 C111 C112 C113 C114 C115 C116 C117 C118 C119 C120 C121 C122 C123 C124 C125 A
47nF 47nF 47nF 47nF 47nF 47nF 47nF 47nF 47nF 47nF 47nF 47nF 47nF 47nF 47nF 47nF 47nF 47nF 47nF 47nF 47nF 47nF 47nF 47nF 47nF 47nF 47nF 47nF 47nF 47nF 47nF 47nF

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Title
PAGE07 DDR3

ALINX Confidential Size

Date:
Document Number
AC7050核心板 Schematics
Friday, February 23, 2018 Sheet 7 of 10
Rev
1.0

5 4 3 2 1
5 4 3 2 1

D FPGA CONFIG SPI +3.3V


D

C126
R47 R48
4.7K 4.7K 0.1uF R49
4.7K
U5

3 QSPI_CS 1 8
QSPI_CS QSPI_DQ1 2 /CS VCC 7 QSPI_DQ3
3 QSPI_DQ1 DO(IO1) /HOLD(IO3) QSPI_DQ3 3
3 QSPI_DQ2 3 6 QSPI_CLK 2
QSPI_DQ2 /WP(IO2) CLK QSPI_CLK

EPAD
4 5 QSPI_DQ0 3
GND DI(IO0) QSPI_DQ0

N25Q128

9
C C

SYSTEM CLOCK

200MHz
+3.3V

L3
600Ohm@100MHz

R50 C127 C128 C129


4.7K 0.1uF 0.1uF 4.7uF
G1
1 6
OE VDD

2 PLL 5
CLKn
NC C130 5
SYS_CLK_N
0.1uF
C131 5
SYS_CLK_P
3 GND CLKp
4 0.1uF
B B

NC

预留不安装

A A

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Title
PAGE08 CLOCK&FLASH

ALINX Confidential Size

Date:
Document Number
AC7050核心板 Schematics
Friday, February 23, 2018 Sheet 8 of 10
Rev
1.0

5 4 3 2 1
5 4 3 2 1

VCC5V
J2

1
VCC 2
D- 3
D+ 4
ID 5

SH1
SH2
SH3
SH4
GND
POWER ON: VCCINT(1.0V)->VCCBRAM(1.0V)->VCCAUX-(1.8V)>VCCO(1.5V and 3.3V)
MINI_USB

6
7
8
9
D D

+1.0V VCC5V 1.8V POWER +1.8V


1.0V POWER U11
VCC5V
R65 +1.0V L6 2.2uH 5000mA
U6 10 1
10K AVIN1 SW1
11 2
4 14 1V0_PG 12 PVIN2 SW2 3
5 PVIN1 PWRGD PVIN3 SW3
R241 6 PVIN2 13 C265 0.1uF 14
VIN BOOT L4 2.2uH 5000mA 1V0_PG 13 VOS
C133 C266 20K 1% 12 EN 4 1V8_PG R62 10K R64
10 PH1 11 9 PG C153 C154
EN PH2 SS/TR 300K 1%
10uF 4.7uF C152 7 22uF 0.1uF
R242 9 R52 C151 3.3nF FSW

PGND1
PGND2
AGND3
SS/TR

TPAD
1 7 4.99K 1% 10uF 8 5

PWPD
RT/CLK V_SNS DEF FB

GND1
GND2
15K 1% 8
COMP VREF=0.8V C136 C132
TLV62130RGT R63

20
16
15
6
TPS54620 47uF 0.1uF 240K 1%

15

2
3
R204
C280 R203 R54
4.02K C281 20K 1%
0.01uF 80.6K
C C282 NC C

0.01uF

VCC5V 1.5V POWER VCC5V +1.5V VCC5V +3.3V

U8
L5 2.2uH 5000mA
10 1
11 AVIN1 SW1 2 U9
12 PVIN2 SW2 3 1 5
PVIN3 SW3 VIN VOUT
14 C144 4
1V8_PG 13 VOS ADJ
EN 4 1V5_PG R55 10K R56 0.1uF 1V5_PG 3 C141 C145
9 PG C139 C140 EN 10uF 0.1uF
SS/TR 130K 1%
C143 7 22uF 0.1uF 2
C142 3.3nF FSW GND
PGND1
PGND2
AGND3
TPAD

10uF 8 5 SPX3819M5-3-3
DEF FB
B B

TLV62130RGT R57
20
16
15
6

150K 1%

VCC5V +3.3V VCCIO

U10
1 5
VIN VOUT
4
C148 ADJ
0.1uF 3 C146 C147
EN 10uF 0.1uF
2
GND
SPX3819M5-3-3

A A

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Title
PAGE09 POWER

ALINX Confidential Size

Date:
Document Number
AC7050核心板 Schematics
Friday, February 23, 2018 Sheet 9 of 10
Rev
1.0

5 4 3 2 1
5 4 3 2 1

D D

VCC5V VCC5V

83

84

83

84
CON1 CON2

83

84

83

84
4 B15_L10_P 1 2 B15_L11_P 4 1 2
B15_L10_P 1 2 B15_L11_P 1 2
4 B15_L10_N 3 4 B15_L11_N 4 3 4
B15_L10_N 3 4 B15_L11_N 3 4
4 B15_L7_P 5 6 B15_L20_P 4 5 6
B15_L7_P 5 6 B15_L20_P 5 6
4 B15_L7_N 7 8 B15_L20_N 4 7 8
B15_L7_N 7 8 B15_L20_N 7 8
9 10 9 10
B15_L9_P 11 9 10 12 B15_L12_P B14_L4_N 11 9 10 12 B14_L5_P
4 B15_L9_P 11 12 B15_L12_P 4 3 B14_L4_N 11 12 B14_L5_P 3
4 B15_L9_N 13 14 B15_L12_N 4 3 B14_L4_P 13 14 B14_L5_N 3
B15_L9_N 13 14 B15_L12_N B14_L4_P 13 14 B14_L5_N
4 B15_L8_P 15 16 B16_L24_P 4 3 B14_L7_N 15 16 B14_L20_N 3
B15_L8_P 15 16 B16_L24_P B14_L7_N 15 16 B14_L20_N
4 B15_L8_N 17 18 B16_L24_N 4 3 B14_L7_P 17 18 B14_L20_P 3
B15_L8_N 17 18 B16_L24_N B14_L7_P 17 18 B14_L20_P
19 20 19 20
B16_L20_P 21 19 20 22 B16_L22_P B14_L9_P 21 19 20 22 B14_L22_N
4 B16_L20_P 21 22 B16_L22_P 4 3 B14_L9_P 21 22 B14_L22_N 3
4 B16_L20_N 23 24 B16_L22_N 4 3 B14_L9_N 23 24 B14_L22_P 3
B16_L20_N 23 24 B16_L22_N B14_L9_N 23 24 B14_L22_P
4 B16_L19_P 25 26 B16_L16_P 4 3 B14_L8_N 25 26 B14_L23_P 3
B16_L19_P 25 26 B16_L16_P B14_L8_N 25 26 B14_L23_P
4 B16_L19_N 27 28 B16_L16_N 4 3 B14_L8_P 27 28 B14_L23_N 3
B16_L19_N 27 28 B16_L16_N B14_L8_P 27 28 B14_L23_N
29 30 29 30
B16_L15_P 31 29 30 32 B16_L6_P B14_L24_N 31 29 30 32 B14_L19_P
4 B16_L15_P 31 32 B16_L6_P 4 3 B14_L24_N 31 32 B14_L19_P 3
4 B16_L15_N 33 34 B16_L6_N 4 3 B14_L24_P 33 34 B14_L19_N 3
B16_L15_N 33 34 B16_L6_N B14_L24_P 33 34 B14_L19_N
4 B16_L13_P 35 36 B16_L4_P 4 3 B14_L12_N 35 36 B14_L21_P 3
B16_L13_P 35 36 B16_L4_P B14_L12_N 35 36 B14_L21_P
4 B16_L13_N 37 38 B16_L4_N 4 3 B14_L12_P 37 38 B14_L21_N 3
B16_L13_N 37 38 B16_L4_N B14_L12_P 37 38 B14_L21_N
C 39 40 39 40 C
B16_L23_N 41 39 40 42 B16_IO0 B14_L15_N 41 39 40 42 B15_L14_N
4 B16_L23_N 41 42 B16_IO0 4 3 B14_L15_N 41 42 B15_L14_N 4
4 B16_L23_P 43 44 B16_L17_N 4 3 B14_L15_P 43 44 B15_L14_P 4
B16_L23_P 43 44 B16_L17_N B14_L15_P 43 44 B15_L14_P
45 46 B16_L17_P 4 3 B14_L16_N 45 46
45 46 B16_L17_P B14_L16_N 45 46
4 B16_L21_N 47 48 B16_L7_N 4 3 B14_L16_P 47 48 B15_L16_N 4
B16_L21_N 47 48 B16_L7_N B14_L16_P 47 48 B15_L16_N
4 B16_L21_P 49 50 B16_L7_P 4 3 B14_IO0 49 50 B15_L16_P 4
B16_L21_P 49 50 B16_L7_P B14_IO0 49 50 B15_L16_P
51 52 51 52
B16_L18_N 53 51 52 54 B16_L11_P B14_L14_N 53 51 52 54 B15_L5_N
4 B16_L18_N 53 54 B16_L11_P 4 3 B14_L14_N 53 54 B15_L5_N 4
4 B16_L18_P 55 56 B16_L11_N 4 3 B14_L14_P 55 56 B15_L5_P 4
B16_L18_P 55 56 B16_L11_N B14_L14_P 55 56 B15_L5_P
57 58 B16_L12_P 4 3 B14_L10_N 57 58
57 58 B16_L12_P B14_L10_N 57 58
4 B16_L14_N 59 60 B16_L12_N 4 3 B14_L10_P 59 60 B15_L13_N 4
B16_L14_N 59 60 B16_L12_N B14_L10_P 59 60 B15_L13_N
4 B16_L14_P 61 62 B16_L5_N 4 3 B14_L11_N 61 62 B15_L13_P 4
B16_L14_P 61 62 B16_L5_N B14_L11_N 61 62 B15_L13_P
63 64 63 64
B16_L9_N 65 63 64 66 B16_L5_P B14_L11_P 65 63 64 66 B15_L6_N
4 B16_L9_N 65 66 B16_L5_P 4 3 B14_L11_P 65 66 B15_L6_N 4
4 B16_L9_P 67 68 B16_L3_N 4 3 B14_L18_N 67 68 B15_L6_P 4
B16_L9_P 67 68 B16_L3_N B14_L18_N 67 68 B15_L6_P
69 70 B16_L3_P 4 3 B14_L18_P 69 70
69 70 B16_L3_P B14_L18_P 69 70
4 B16_L8_N 71 72 B16_L1_N 4 3 B14_L17_N 71 72 B15_L4_N 4
B16_L8_N 71 72 B16_L1_N B14_L17_N 71 72 B15_L4_N
4 B16_L8_P 73 74 B16_L1_P 4 3 B14_L17_P 73 74 B15_L4_P 4
B16_L8_P 73 74 B16_L1_P B14_L17_P 73 74 B15_L4_P
75 76 75 76
B16_L10_N 77 75 76 78 B16_L2_N FPGA_TDI 77 75 76 78 FPGA_TCK
4 B16_L10_N 77 78 B16_L2_N 4 2 FPGA_TDI 77 78 FPGA_TCK 2
4 B16_L10_P 79 80 B16_L2_P 4 2 FPGA_TMS FPGA_TMS 79 80 FPGA_TDO FPGA_TDO 2
B16_L10_P 79 80 B16_L2_P 79 80
81

82

81

82
81

82

81

82
CON40X2_0_8MM CON40X2_0_8MM

B B

A A

www.alinx.com
Title
PAGE10 Connector

ALINX Confidential Size

Date:
Document Number
AC7050核心板 Schematics
Friday, February 23, 2018 Sheet 10 of 10
Rev
1.0

5 4 3 2 1

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