Chapter 9: Sequential Logic Modules

Chapter 9: Sequential Logic Modules

Prof. Soo-Ik Chae

Digital System Designs and Practices Using Verilog HDL and FPGAs @ 2008, John Wiley 9-1
 Chapter 9: Sequential Logic Modules

Objectives

After completing this chapter, you will be able to:

 Describe how to model asynchronous and synchronous D-
type flip-flops
 Describe how to model registers (data register, register file,
and synchronous RAM)
 Describe how to model shift registers
 Describe how to model counters (ripple/synchronous
counters and modulo r counters)
 Describe how to model sequence generators
 Describe how to model timing generators

Digital System Designs and Practices Using Verilog HDL and FPGAs @ 2008, John Wiley 9-2
 Chapter 9: Sequential Logic Modules

Basic Sequential Logic Modules

 Commonly used sequential logic modules:

 Synchronizer
 Finite state machine
 Sequence detector
 Data register
 Shift register
 CRC generator
 Register file
 Counters (binary, BCD, Johnson)
 Timing generator
 Clock generator
 Pulse generator
Digital System Designs and Practices Using Verilog HDL and FPGAs @ 2008, John Wiley 9-3
 Chapter 9: Sequential Logic Modules

Options for Modeling Sequential Logic

 Options for modeling sequential logic:

 Behavioral statement
 Task with delay or event control
 Sequential UDP
 Instantiated library register cell
 Instantiated modules

Digital System Designs and Practices Using Verilog HDL and FPGAs @ 2008, John Wiley 9-4
 Chapter 9: Sequential Logic Modules

Libraries

 Library files contain all of the encapsulated and reusable

modules for a design.
 These modules include
 All flip-flops,
 Memories,
 Input, output, tri-state drivers
 Clock generators
 Parity trees
 Muxes
 Error-correcting encode/decode logic
 Queues
Digital System Designs and Practices Using Verilog HDL and FPGAs @ 2008, John Wiley 9-5
 Chapter 9: Sequential Logic Modules

Parity tree

Digital System Designs and Practices Using Verilog HDL and FPGAs @ 2008, John Wiley 9-6
 Chapter 9: Sequential Logic Modules

Asynchronous Reset D-Type Flip-Flops

 Asynchronous reset D-type flip-flop

 The reset signal is embodied into the event-sensitivity list
of always statement.
// asynchronous reset D-type flip-flop
module DFF_async_reset (clk, reset_n, d, q);
input clk, reset_n, d;
output reg q;
// the body of flip flop
always @(posedge clk or negedge reset_n)
if (!reset_n) q <= 0; // reset_n signal is active-low.
else q <= d;
endmodule

 How would you model a D-type latch?

Digital System Designs and Practices Using Verilog HDL and FPGAs @ 2008, John Wiley 9-7
 Chapter 9: Sequential Logic Modules

Inferred Latch

module latch(dout, din, le);

input din;
output dout;
input le; // latch enable
reg dout;
always @(din or le)
if (le == 1'b1)
dout = din;
endmodule

 Three cases for inferred

1. if statement with no else
2. case conditions are not complete
3. when sensitive list is not complete (only in simulation)

Simulation and synthesis results can be inconsistent?!

Digital System Designs and Practices Using Verilog HDL and FPGAs @ 2008, John Wiley 9-8
 Chapter 9: Sequential Logic Modules

Synchronous Reset D-Type Flip-Flops

 Synchronous reset D-type flip-flop

 The reset signal is not embodied into the event-sensitivity
list of always statement.
// synchronous reset D-type flip-flop
module DFF_sync_reset (clk, reset, d, q);
input clk, reset, d;
output reg q;
// the body of flip flop
always @(posedge clk)
if (reset) q <= 0; // reset signal is active-high.
else q <= d;
endmodule

Digital System Designs and Practices Using Verilog HDL and FPGAs @ 2008, John Wiley 9-9
 Chapter 9: Sequential Logic Modules

Registers

 Registers (or data registers) provide a means for storing

information in any digital system.
 Types of registers used in digital systems:
 Data register using flip-flops or latches.
 Register file being used in data paths.
 Synchronous RAM (random access memory) being used
for storing moderate amount of information.
 A flip-flop may take up 10 to 20 times the area of a 6-
transistor static RAM cell.
 In Xilinx FPGA, both register file and synchronous RAM
are synthesized into static RAM structures consisting of
LUTs or block RAMs.

Digital System Designs and Practices Using Verilog HDL and FPGAs @ 2008, John Wiley 9-10
 Chapter 9: Sequential Logic Modules

Data Registers
din[3] din[2] din[1] din[0]

D Q D Q D Q D Q
CK CK CK CK
Q' Q' Q' Q'

clk
qout[3] qout[2] qout[1] qout[0]

// an n-bit data register

module register(clk, din, qout);
parameter N = 4; // number of bits
input clk;
input [N-1:0] din;
output reg [N-1:0] qout;
// the body of an n-bit data register
always @(posedge clk) qout <= din;
endmodule
Digital System Designs and Practices Using Verilog HDL and FPGAs @ 2008, John Wiley 9-11
 Chapter 9: Sequential Logic Modules

Data Registers
// an n-bit data register with asynchronous reset
module register_reset (clk, reset_n, din, qout);
parameter N = 4; // number of bits
input clk, reset_n;
input [N-1:0] din;
output reg [N-1:0] qout;

// The body of an n-bit data register

always @(posedge clk or negedge reset_n)
if (!reset_n) qout <= {N{1'b0}};
else qout <= din;
endmodule

Coding style:
• For active-low signal, end the signal name with an underscore followed by
a lowercase letter b or n, such as reset_n.

Digital System Designs and Practices Using Verilog HDL and FPGAs @ 2008, John Wiley 9-12
 Chapter 9: Sequential Logic Modules

Data Registers
// an N-bit data register with synchronous load and
// asynchronous reset
module register_load_reset (clk, load, reset_n, din, qout);
parameter N = 4; // number of bits
input clk, load, reset_n;
input [N-1:0] din;
output reg [N-1:0] qout;

// the body of an N-bit data register

always @(posedge clk or negedge reset_n)
if (!reset_n) qout <= {N{1'b0}};
else if (load) qout <= din;
else qout <= qout; // a redundant expression
endmodule

Notice that: the else part is a redundant expression for sequential circuit.
Why? Try to explain it.
Digital System Designs and Practices Using Verilog HDL and FPGAs @ 2008, John Wiley 9-13
 Chapter 9: Sequential Logic Modules

A Register File
// an N-word register file with one-write and two-read ports
module register_file(clk, rd_addra, rd_addrb, wr_addr, wr_enable, din, douta, doutb);
parameter M = 4; // number of address bits
parameter N = 16; // number of words, N = 2**M
parameter W = 8; // number of bits in a word
input clk, wr_enable;
input [W-1:0] din;
output [W-1:0] douta, doutb;
input [M-1:0] rd_addra, rd_addrb, wr_addr;
reg [W-1:0] reg_file [N-1:0];

// the body of the N-word register file

assign douta = reg_file[rd_addra],
doutb = reg_file[rd_addrb];
always @(posedge clk)
if (wr_enable) reg_file[wr_addr] <= din;
endmodule

Digital System Designs and Practices Using Verilog HDL and FPGAs @ 2008, John Wiley 9-14
 Chapter 9: Sequential Logic Modules

An Synchronous RAM

// a synchronous RAM module example

module syn_ram (addr, cs, din, clk, wr, dout);
parameter N = 16; // number of words
parameter A = 4; // number of address bits
parameter W = 4; // number of wordsize in bits
input [A-1:0] addr;
input [W-1:0] din;
input cs, wr, clk; // chip select, read-write control, and clock signals
output reg [W-1:0] dout;
reg [W-1:0] ram [N-1:0]; // declare an N * W memory array

// the body of synchronous RAM

always @(posedge clk)
if (cs) if (wr) ram[addr] <= din;
else dout <= ram[addr];
endmodule

Digital System Designs and Practices Using Verilog HDL and FPGAs @ 2008, John Wiley 9-15
 Chapter 9: Sequential Logic Modules

Shift Registers

 Shift registers perform left or right shift operation.

 Parallel/serial format conversion:
 SISO (serial in serial out)
 SIPO (serial in parallel out)
 PISO (parallel in serial out)
 PIPO (parallel in parallel out)

Digital System Designs and Practices Using Verilog HDL and FPGAs @ 2008, John Wiley 9-16
 Chapter 9: Sequential Logic Modules

Shift Registers

QA QB QC QD

Serial input D Q D Q D Q D Q Serial output

(SI) CK CK CK CK (SO)
Q' Q' Q' Q'

CP

CP

SI

QA 1 1 0 1

QB 0 1 1 0 1

QC 0 0 1 1 0 1

QD 0 0 0 1 1 0 1

Digital System Designs and Practices Using Verilog HDL and FPGAs @ 2008, John Wiley 9-17
 Chapter 9: Sequential Logic Modules

Shift Registers

// a shift register module example

module shift_register(clk, reset_n, din, qout);
parameter N = 4; // number of bits
input clk, reset_n;
input din;
output reg [N-1:0] qout;

// the body of an N-bit shift register

always @(posedge clk or negedge reset_n)
if (!reset_n) qout <= {N{1'b0}};
else qout <= {din, qout[N-1:1]};
endmodule

Digital System Designs and Practices Using Verilog HDL and FPGAs @ 2008, John Wiley 9-18
 Chapter 9: Sequential Logic Modules

A Shift Register with Parallel Load

// a shift register with parallel load module example

module shift_register_parallel_load(clk, load, reset_n, din, sin, qout);
parameter N = 8; // number of bits
input sin, clk, load, reset_n;
input [N-1:0] din;
output reg [N-1:0] qout;

// the body of an N-bit shift register

always @(posedge clk or negedge reset_n)
if (!reset_n) qout <= {N{1'b0}};
else if (load) qout <= din;
else qout <= {sin, qout[N-1:1]};
endmodule

Digital System Designs and Practices Using Verilog HDL and FPGAs @ 2008, John Wiley 9-19
 Chapter 9: Sequential Logic Modules

Universal Shift Registers

 A universal shift register can carry out

 SISO (serial in serial out)
 SIPO (serial in parallel out)
 PISO (parallel in serial out)
 PIPO (parallel in parallel out)
 The register must have the following capabilities:
 Parallel load
 Serial in and serial out
 Shift left and shift right

Digital System Designs and Practices Using Verilog HDL and FPGAs @ 2008, John Wiley 9-20
 Chapter 9: Sequential Logic Modules

Universal Shift Registers

Right din[3] din[2] din[1] din[0] Left shift
shift serial serial
input input
(rsi) (lsi)
s1 32 1 0 32 1 0 32 1 0 3 2 1 0 4-to-1
s0 Y Y Y Y MUX

D Q D Q D Q D Q
CK CK CK CK
Q' Q' Q' Q'
clear clear clear clear
clk
reset
qout[3] qout[2] qout[1] qout[0]

Paralle data input

Right shift Left shift s1 s0 Function
serial input serial input
D C B A
0 0 No change
reset CLR S1
4-bit universal Mode
shift register
0 1 Right shift
clk control
CK QD QC QB QA S0
1 0 Left shift
1 1 Load data
Paralle data output

Digital System Designs and Practices Using Verilog HDL and FPGAs @ 2008, John Wiley 9-21
 Chapter 9: Sequential Logic Modules

Universal Shift Registers

// a universal shift register module

module universal_shift_register (clk, reset_n, s1, s0, lsi, rsi, din, qout);
parameter N = 4; // define the size of the universal shift register
input s1, s0, lsi, rsi, clk, reset_n;
input [N-1:0] din;
output reg [N-1:0] qout;
// the shift register body
always @(posedge clk or negedge reset_n)
if (!reset_n) qout <= {N{1'b0}};
else case ({s1,s0})
2'b00: ; // qout <= qout; // No change
2'b01: qout <= {lsi, qout[N-1:1]}; // Shift right
2'b10: qout <= {qout[N-2:0], rsi}; // Shift left
2'b11: qout <= din; // Parallel load
endcase
endmodule

Digital System Designs and Practices Using Verilog HDL and FPGAs @ 2008, John Wiley 9-22
 Chapter 9: Sequential Logic Modules

Counters

 Counter is a device that counts the input events such as input

pulses or clock pulses.
 Types of counters:
 Asynchronous
 Synchronous
 Asynchronous (ripple) counters:
 Binary counter (up/down counters)
 Synchronous counters:
 Binary counter (up/down counters)
 BCD counter (up/down counters)
 Gray counters (up/down counters)
Digital System Designs and Practices Using Verilog HDL and FPGAs @ 2008, John Wiley 9-23
 Chapter 9: Sequential Logic Modules

Binary Ripple Counters

1 qout[0] 1 qout[1] 1 qout[2]

J Q J Q J Q
clk CK CK CK
K Q' K Q' K Q'
1 2 3

clk

qout[0]

qout[1]

qout[2]

Digital System Designs and Practices Using Verilog HDL and FPGAs @ 2008, John Wiley 9-24
 Chapter 9: Sequential Logic Modules

Binary Ripple Counters

// a 3-bit ripple counter module example

module ripple_counter(clk, qout);
input clk;
output reg [2:0] qout;
wire c0, c1;
// the body of the 3-bit ripple counter
assign c0 = qout[0], c1 = qout[1];
always @(negedge clk)
qout[0] <= ~qout[0];
• The output cannot be observed from
always @(negedge c0)
simulators due to lacking initial
qout[1] <= ~qout[1];
always @(negedge c1) values of qout. => reset is required!
qout[2] <= ~qout[2];
endmodule

Digital System Designs and Practices Using Verilog HDL and FPGAs @ 2008, John Wiley 9-25
 Chapter 9: Sequential Logic Modules

Binary Ripple Counters

// a 3-bit ripple counter with enable control
module ripple_counter_enable(clk, enable, reset_n, qout);
input clk, enable, reset_n;
output reg [2:0] qout;
wire c0, c1;
// the body of the 3-bit ripple counter
assign c0 = qout[0], c1 = qout[1];
always @(posedge clk or negedge reset_n)
if (!reset_n) qout[0] <= 1'b0;
else if (enable) qout[0] <= ~qout[0];
always @(posedge c0 or negedge reset_n)
if (!reset_n) qout[1] <= 1'b0;
else if (enable) qout[1] <= ~qout[1];
always @(posedge c1 or negedge reset_n)
if (!reset_n) qout[2] <= 1'b0;
else if (enable) qout[2] <= ~qout[2];
endmodule

Digital System Designs and Practices Using Verilog HDL and FPGAs @ 2008, John Wiley 9-26
 Chapter 9: Sequential Logic Modules

A Binary Ripple Counter --- Using the generate Statement

// an N-bit ripple counter using generate blocks

module ripple_counter_generate(clk, reset_n, qout);
parameter N = 4; // define the size of counter
input clk, reset_n;
output reg [N-1:0] qout;
// the body of the N-bit ripple counter
genvar i;
generate for (i = 0; i < N; i = i + 1) begin: ripple_counter
if (i == 0) // specify LSB
always @(negedge clk or negedge reset_n)
if (!reset_n) qout[0] <= 1'b0; else qout[0] <= ~qout[0];
else // specify the rest bits
always @(negedge qout[i-1] or negedge reset_n)
if (!reset_n) qout[i] <= 1'b0; else qout[i] <= ~qout[i];
end
endgenerate
endmodule
Digital System Designs and Practices Using Verilog HDL and FPGAs @ 2008, John Wiley 9-27
 Chapter 9: Sequential Logic Modules

A Binary Counter Example

// an n-bit binary counter with synchronous reset and enable control.

module binary_counter(clk, enable, reset, qout, rco);
parameter N = 4;
input clk, enable, reset;
output reg [N-1:0] qout;
output rco;
// the body of the N-bit binary counter
always @(posedge clk)
if (reset) qout <= {N{1’b0}};
else if (enable) qout <= qout + 1;
// generate carry output
assign #1 rco= &qout; // why #1 is required?
endmodule

What if #1 is not used?

Digital System Designs and Practices Using Verilog HDL and FPGAs @ 2008, John Wiley 9-28
 Chapter 9: Sequential Logic Modules

A Binary Counter Example

// an n-bit binary counter with synchronous reset and enable control.

module binary_counter(clk, enable, reset, qout, rco);
parameter N = 4;
input clk, enable, reset;
output reg [N-1:0] qout;
output rco;
// the body of the N-bit binary counter
always @(posedge clk)
if (reset) qout <= {N{1’b0}};
else if (enable) qout <= qout + 1;
// generate carry output
assign rco= &qout;
endmodule

When rco is used as enable in a cascaded counter, possible hold time

violation.
Digital System Designs and Practices Using Verilog HDL and FPGAs @ 2008, John Wiley 9-29
 Chapter 9: Sequential Logic Modules

A Binary Counter Example- revised

// an n-bit binary counter with synchronous reset and enable control.

module binary_counter(clk, enable, reset, qout, rco);
parameter N = 4;
input clk, enable, reset;
output reg [N-1:0] qout;
output reg rco;
// the body of the N-bit binary counter
always @(posedge clk)
if (reset) qout <= {N{1’b0}};
else if (enable) qout <= qout + 1;
// generate carry output
always @(negedge clk)
rco <= &qout;
endmodule

Digital System Designs and Practices Using Verilog HDL and FPGAs @ 2008, John Wiley 9-30
 Chapter 9: Sequential Logic Modules

Binary Up/Down Counters --- version 1

// an N-bit binary up/down counter with synchronous reset and enable control.
module binary_up_down_counter_reset(clk, enable, reset, upcnt, qout, cout, bout);
parameter N = 4;
input clk, enable, reset, upcnt;
output reg [N-1:0] qout;
output cout, bout; // carry and borrow outputs
// the body of N-bit up/down binary counter
always @(posedge clk)
if (reset) qout <= {N{1'b0}};
else if (enable) begin
if (upcnt) qout <= qout + 1;
else qout <= qout - 1; end
// else qout <= qout; // a redundant expression
// Generate carry and borrow outputs
assign #1 cout = &qout; // Why #1 is required ?
assign #1 bout = |qout;
endmodule

Digital System Designs and Practices Using Verilog HDL and FPGAs @ 2008, John Wiley 9-31
 Chapter 9: Sequential Logic Modules

Binary Up/Down Counters --- version 2

// an N-bit up/down binary counter with synchronous reset and enable control.
module up_dn_bin_counter(clk, reset, eup, edn, qout, cout, bout);
Parameter N = 4;
// Enable up count (eup) and enable down count (edn)
// cannot be set to one simultaneously.
input clk, reset, eup, edn;
output reg [N-1:0] qout;
output cout, bout;
// the body of the N-bit binary counter
always @(posedge clk)
if (reset) qout <= {N{1'b0}}; // synchronous reset
else if (eup) qout <= qout + 1;
else if (edn) qout <= qout - 1;
assign #1 cout = (&qout)& eup; // generate carry out
assign #1 bout = (~|qout)& edn; // generate borrow out
endmodule

Digital System Designs and Practices Using Verilog HDL and FPGAs @ 2008, John Wiley 9-32
 Chapter 9: Sequential Logic Modules

Binary Up/Down Counters --- revised

// an N-bit up/down binary counter with synchronous reset and enable control.
module up_dn_bin_counter(clk, reset, eup, edn, qout, rco, rbo);
Parameter N = 4;
// Enable up count (eup) and enable down count (edn)
// cannot be set to one simultaneously.
input clk, reset, eup, edn;
output reg [N-1:0] qout;
output reg rco, rbo;
// the body of the N-bit binary counter
always @(posedge clk)
if (reset) qout <= {N{1'b0}}; // synchronous reset
else if (eup) qout <= qout + 1;
else if (edn) qout <= qout - 1;
always @(negedge clk) begin
rco <= (&qout)& eup; // generate carry out
rbo <= (~|qout)& edn; // generate borrow out
end
endmodule
Digital System Designs and Practices Using Verilog HDL and FPGAs @ 2008, John Wiley 9-33
 Chapter 9: Sequential Logic Modules

Binary Up/Down Counters --- version 2

// an example to illustrating the cascade of two up/down counters.

module up_dn_bin_counter_cascaded(clk, reset,eup, edn, qout, cout, bout);
parameter N = 4;
input clk, reset, eup, edn;
output [2*N-1:0] qout;
output cout, bout;

// declare internal nets for cascading both counters

wire cout1, bout1;

// The body of the cascaded up/down counter

up_dn_bin_counter #(4) up_dn_cnt1 (clk, reset,eup, edn, qout[3:0], cout1, bout1);
up_dn_bin_counter #(4) up_dn_cnt2 (clk, reset,cout1, bout1, qout[7:4], cout, bout);
endmodule

Digital System Designs and Practices Using Verilog HDL and FPGAs @ 2008, John Wiley 9-34
 Chapter 9: Sequential Logic Modules

A Modulo r Binary Counter

// the body of modulo r binary counter with synchronous reset and enable control.
module modulo_r_counter(clk, enable, reset, qout, rco);
parameter N = 4;
parameter R= 10; // BCD counter
input clk, enable, reset;
output reg [N-1:0] qout;
output rco; // carry output
// the body of modulo r binary counter.
assign rco = (qout == R - 1);
always @(posedge clk)
if (reset) qout <= {N{1'b0}};
else begin
if (enable) if (rco) qout <= 0;
else qout <= qout + 1;
end
endmodule

Digital System Designs and Practices Using Verilog HDL and FPGAs @ 2008, John Wiley 9-35
 Chapter 9: Sequential Logic Modules

A Modulo r Binary Counter with % (modulo)

// the body of modulo r binary counter with synchronous reset and enable control.
module modulo_r_counter(clk, enable, reset, qout, rco);
parameter N = 4;
parameter R= 10; // BCD counter
input clk, enable, reset;
output reg [N-1:0] qout;
output rco; // carry output
// the body of modulo r binary counter.
assign rco = (qout == R - 1);
always @(posedge clk)
if (reset) qout <= {N{1'b0}};
else begin
if (enable) qout <= (qout + 1)% R; • Not synthesizable if R is
end not a power of 2.
endmodule

Digital System Designs and Practices Using Verilog HDL and FPGAs @ 2008, John Wiley 9-36
 Chapter 9: Sequential Logic Modules
A Modulo r Binary Counter: revised
// the body of modulo r binary counter with synchronous reset and enable control.
module modulo_r_counter(clk, enable, reset, qout, rco);
parameter N = 4;
parameter R= 10; // BCD counter
input clk, enable, reset;
output reg [N-1:0] qout;
output reg rco; // carry output
wire cout;
// the body of modulo r binary counter.
assign cout = (qout==R-1);
always @(negedge clk)
rco <= cout; // rco will be used as enable if cascaded
always @(posedge clk)
if (reset) qout <= {N{1'b0}};
else begin
if (enable) if (rco) qout <= 0;
else qout <= qout + 1;
end
endmodule
Digital System Designs and Practices Using Verilog HDL and FPGAs @ 2008, John Wiley 9-37
 Chapter 9: Sequential Logic Modules

Sequence Generators

 In this lecture, we focus on the following three circuits:

 PR (pseudo random)-sequence generator
 Ring counter
 Johnson counter
f Combinational Circuit

Qn-1 Qn-2 Q1 Q0
Dn-1
D Q D Q ••• D Q D Q z
CK CK CK CK
Q' Q' Q' Q'
n-1 n-2 1 0
clk

The general paradigm of sequence generator

Digital System Designs and Practices Using Verilog HDL and FPGAs @ 2008, John Wiley 9-38
 Chapter 9: Sequential Logic Modules

Primitive Polynomials

n f(x) n f(x) n f(x)

1, 2, 3, 4, 6, 24 1+x+x2+x7+xn 43 1+x+x5+x6+xn
1+x+xn
7, 15, 22, 60 26 1+x+x2+x6+xn 44, 50 1+x+x26+x27+xn
5, 11, 21, 29 1+x2+xn 30 1+x+x2+x23+xn 45 1+x+x3+x4+xn
10, 17, 20, 25, 32 1+x+x2+x22+xn 46 1+x+x20+x21+xn
1+x3+xn
28, 31, 41, 52 33 1+x13+xn 48 1+x+x27+x28+xn
9 1+x4+xn 34 1+x+x14+x15+xn 49 1+x9+xn
23, 47 1+x5+xn 35 1+x2+xn 51, 53 1+x+x15+x16+xn
18 1+x7+xn 36 1+x11+xn 54 1+x+x36+x37+xn
8 1+x2+x3+x4+xn 37 1+x2+x10+x12+xn 55 1+x24+xn
12 1+x+x4+x6+xn 38 1+x+x5+x6+xn 56,59 1+x+x21+x22+xn
13 1+x+x3+x4+xn 39 1+x4+xn 57 1+x7+xn
14, 16 1+x3+x4+x5+xn 40 1+x2+x19+x21+xn 58 1+x19+xn
19, 27 1+x+x2+x5+xn 42 1+x+x22+x23+xn
n
f ( x) = ∑ ai x i = a0 + a1 x + a2 x 2 +  + an x n
i =0

Digital System Designs and Practices Using Verilog HDL and FPGAs @ 2008, John Wiley 9-39
 Chapter 9: Sequential Logic Modules

Maximal Length Sequence Generators

D Q D Q D Q D Q
CK CK CK CK
an n-1 Q' an-1 n-2 Q' an-2 1 Q' a1 0 Q' a0

clk

(a) Standard format

D Q D Q D Q D Q
CK CK CK CK
a0 n-1 Q' a1 n-2 Q' a2 1 Q' an-1 0 Q' an

clk

(b) Modular format

Digital System Designs and Practices Using Verilog HDL and FPGAs @ 2008, John Wiley 9-40
 Chapter 9: Sequential Logic Modules

A PR-Sequence Generator Example

 An example of 4-bit pr-sequence generator:

 primitive polynomial: 1 + x + x4
qout[3] qout[2] qout[1] qout[0]

d[3] d[2] d[1] d[0]

D Q D Q D Q D Q
CK CK CK CK
Q' Q' Q' Q'
preset clear clear clear
clk
start

• Using start to set the initial to 1000, the circuit will start from state
4’b1000 after reset signal is applied.

Digital System Designs and Practices Using Verilog HDL and FPGAs @ 2008, John Wiley 9-41
 Chapter 9: Sequential Logic Modules

A PR-Sequence Generator Example

// an N-bit pr_sequence generator module --- in standard form

module pr_sequence_generate (clk, qout);
parameter N = 4; // define the default size
parameter [N:0] tap = 5'b10011;
input clk; = 4’b0100 for simulation only. Without
output reg [N-1:0] qout = 4’b0100; the initial value, simulators cannot
wire d; calculate qout and hence we could not
observe the qout values.
// pseudo-random sequence generator body
assign d = ^(tap[N-1:0] & qout[N-1:0]);
always @(posedge clk)
qout <= {d, qout[N-1:1]};
endmodule

Q: Write an N-bit pr_sequence generator in modular form.

Digital System Designs and Practices Using Verilog HDL and FPGAs @ 2008, John Wiley 9-42
 Chapter 9: Sequential Logic Modules

A PR-Sequence Generator Example

// an N-bit pr_sequence generator module --- in standard form
module pr_sequence_generate (clk, start, qout);
parameter N = 4; // define the default size
parameter [N:0] tap = 5'b10011;
input clk, start;
output reg [N-1:0] qout;
wire d;
// pseudo-random sequence generator body
assign d = ^(tap[N-1:0] & qout[N-1:0]);
always @(posedge clk or posedge start)
if (start) qout <= {1'b1, {N-1{1'b0}}};
else qout <= {d, qout[N-1:1]};
endmodule

• Using start to set the initial value to 4’b1000, hence simulators can calculate
qout and hence we could observe the qout values.
• Of course, the circuit will start from state 4’b1000 after reset signal is applied.
Digital System Designs and Practices Using Verilog HDL and FPGAs @ 2008, John Wiley 9-43
 Chapter 9: Sequential Logic Modules

Ring Counters
qout[0] qout[1] qout[2] qout[3]

d[0] d[1] d[2] d[3]

D Q D Q D Q D Q
CK CK CK CK
Q' Q' Q' Q'
preset clear clear clear
clk
start

// a ring counter with initial value

module ring_counter(clk, start, qout);
parameter N = 4;
input clk, start;
output reg [0:N-1] qout;
// the body of ring counter
always @(posedge clk or posedge start)
if (start) qout <= {1'b1,{N-1{1'b0}}};
else qout <= {qout[N-1], qout[0:N-2]};
endmodule
Digital System Designs and Practices Using Verilog HDL and FPGAs @ 2008, John Wiley 9-44
 Chapter 9: Sequential Logic Modules

Johnson Counters
qout[0] qout[1] qout[2] qout[3]

d[0] d[1] d[2] d[3]

D Q D Q D Q D Q
CK CK CK CK
Q' Q' Q' Q'
clear clear clear clear
clk
start

// Johnson counter with initial value

module ring_counter(clk, start, qout);
parameter N = 4; // define the default size
input clk, start;
output reg [0:N-1] qout;
// the body of Johnson counter
always @(posedge clk or posedge start)
if (start) qout <= {N{1'b0}};
else qout <= {~qout[N-1], qout[0:N-2]};
endmodule
Digital System Designs and Practices Using Verilog HDL and FPGAs @ 2008, John Wiley 9-45
 Chapter 9: Sequential Logic Modules

Self-starting counters

 An n-bit Johnson counter has 2n valid states and 2n-2n

invalid states.
 It may be locked in one of the invalid-state loops and cannot
return to its normal counting loop.

Digital System Designs and Practices Using Verilog HDL and FPGAs @ 2008, John Wiley 9-46
 Chapter 9: Sequential Logic Modules

Timing Generators

 A timing generator is a device that generates timings

required for specific application.
 Multiphase clock signals:
 Ring counter
 Binary counter with decoder
 Digital monostable circuits:
 Retriggerable
 Nonretriggerable

Digital System Designs and Practices Using Verilog HDL and FPGAs @ 2008, John Wiley 9-47
 Chapter 9: Sequential Logic Modules

A Multiphase Clock Signal

clk

T0

T1

T2

T3

T4

T5

T6

T7

Digital System Designs and Practices Using Verilog HDL and FPGAs @ 2008, John Wiley 9-48
 Chapter 9: Sequential Logic Modules

Multiphase Clock Generators

T0 T1 T2 T3 T4 T5 T6 T7
(a) Ring counter approach
D 0 1 2 3 4 5 6 7
clk CK

// a ring counter with initial value serve as a timing generator

module ring_counter_timing_generator(clk, reset, qout);
parameter n = 4; // define the counter size
input clk, reset;
output reg [0:n-1] qout;
// the body of ring counter
always @(posedge clk or posedge reset)
if (reset) qout <= {1'b1,{n-1{1'b0}}};
else qout <= {qout[n-1], qout[0:n-2]};
endmodule

Digital System Designs and Practices Using Verilog HDL and FPGAs @ 2008, John Wiley 9-49
 Chapter 9: Sequential Logic Modules

Multiphase Clock Generators

 Binary counter with decoder approach

T7 T6 T5 T4 T3 T2 T1 T0

7 6 5 4 3 2 1 0
3-to-8 decoder
A2 A1 A0

Synthesized output from

SynplifyPro with n = 4 and m =2. Q2 Q1 Q0
(Program is listed on the next page.) CP CK
Binary counter

clk

[1:0]
decode
+ [1:0] [1:0]
D[1:0] Q[1:0] [1:0] [1:0]
D[1:0] EQ[3:0] [3:0] [3:0]
qout[3:0]
enable R
bcnt_out_5[1:0] qout[3:0]
reset bcnt_out[1:0]
Digital System Designs and Practices Using Verilog HDL and FPGAs @ 2008, John Wiley 9-50
 Chapter 9: Sequential Logic Modules

Multiphase Clock Generators

// a binary counter with decoder serve as a timing generator

module binary_counter_timing_generator(clk, reset, enable, qout);
parameter N = 8; // define the number of phases
parameter M = 3; // define the bit number of binary counter
input clk, reset, enable;
output reg [N-1:0] qout;
reg [M-1:0] bcnt_out;
// the body of binary counter
always @(posedge clk or posedge reset)
if (reset) bcnt_out <= {M{1'b0}};
else if (enable) bcnt_out <= bcnt_out + 1;
// decode the output of the binary counter
always @(bcnt_out)
qout = {N-1{1'b0},1'b1} << bcnt_out;
endmodule

Digital System Designs and Practices Using Verilog HDL and FPGAs @ 2008, John Wiley 9-51