204 Modern Digital Electronics

7.3 CLOCKED S-R FLIP-FLOP

Tt is often required to set or reset the memory cell (Fig. 7.4) in synchro
nism with a train of pulses (Fig. 7.2) known as clock (abbreviated as CK).
Such a cireuit is shown in Fig. 7.5, and is referred to as a clocked set-reset
(S-R) FLIP-FLOP A

So D D
CKO-

RO G2
o,
Fig. 7.5 A clocked S. R FLIP-FLOP

In thiscircuit, if a clock pulse is present (CK 1), its operation is

=

exactly the same as that of Fig. 7.4. Oa the other hand, when the clock
pulse is not present (CK = 0), the gates G and Gi are inhibited, i.e. their
outputs are 1 irrespective of the values of S' or R. In other words, the circuit
responds to the inputs S and R only when the clock is present.
Assuming that the inputs do not change during the presence of the
clock pulse, we can express the operation of a FLIP-FLOP in the form of the
truth table in Table 7.1 for the S-R FLIP-FLOP. Here S, and R, denote the
inputs and On the output during the bit timen (Fig. 7.2). Qni1 denotes the
output Q after the pulse passes, i.e. in the bit time n +1.

Table 7.1 Truth Table of S-R FLIP-FLOP

Inputs Output
S R On+1
0
geu
1 0
0
1

If S,= R, 0, and the clock pulse is applied, the output at t

=

ofthe clock pulse is same as the output before the clock pulse, i.e. Qn,1
Q This is indicated in the first row of the truth table.
IfSn= 1 and R, = 0, the output at the end of the clock pulse will be
1, whereas if S,= 0 and R,= 1, then Qn,1 0. These are indicated
the second and third rows of the truth table in
respectively.
In the circuit of Fig. 7.4, it was mentioned that S= R = 1 is not
 FLIP-FLOPs 205
what happens in the S-R
see
when the clock 1s present the outputsFLIP-FLOP of Fig. 7.5 if
allowed.

Ry= 1. WVh
of gates G and S, =

of
making one of the inputs Gi and Ga NAND
of Gg are both
gates 0.
logidwhich is inconsistent with Consequently, Q
both will attain log
nd
outputs. Now when the clock pulse our
complementary outputs
has
assumption of
(CK=0), theoutp and G will rise from 0 passed away
to 1.
the propagation delays
the P
of the gates, either the stableDepending
state
upon
0)
-
or On,1= (On41 1) will result. That means the Qn1= 1
circuit is determinate
defined, inde or
ambiguous
state
and therefore is
of the
by question mark (fourth row of the truth table). indicated
The condition S,=R 1 is forbidden and
it must not be
occur.
allowed to
The logic symbol of clocked S-R FLIP-FLOP is
given in Fig. 7.6

SO-
S-R
CKO
FLIP FLOP
RO-

Fig. 7.6 Logic symbol of clocked

S-R FLIP-FLOP

Preset and Clear

In the FLIP-FLOP of Fig. 7.5, when the power is switched on, the state of
the circuit is uncertain. It may come to set ( =1) or reset ( 0) =
state
In many applications it is desired to initially set or reset the FLIP-FLOP, i.e.
the initial state of the FLIP-FLOP is to be assigned. This is accomplished by
bng the direct, or asynchronous inputs, referred to as preset (Pr) and clear
Cr)inputs., These inputs may be applied at any time between clock pulses
An S-R FLIP-FLOP with preset
ae not in synchronism with the clock.
and clear is shown in Fig. 7.7. If Pr= Cr = 1 the circuit operates in

given in Table 7.1.

ance with the truth table of S-R FLIP-FLOPwill certainly be 1. Conse
I 0 and Cr =1, the output of G(0) = 0. Hence
the three inputs to Ga will be 1 which will make
makKing Pr = 0 sets the FLIP-FLOP. lo p r s
reset. Once the state
milar
oftary if Pr =1 and Cr= 0, the FLIP-FLOP is
asynchronous inputs
-FLOP is established asynchronously, the
Pr and
Pr clock is applied.
and Crust
must be connected logic 1 before the next
The conditio conn
to
since this leads to
an
must not be used,
Pr= Cr 0 =

uncertain state.
In the logic are used for Pr and Cr inputs,
8IC Symbol of Fig. 7.76, bubbles
 206 Modern Digital Electronics

Preset ( Pr)

SO-
G3 G
CKO-
bete

RO- G2 -o
Clear (Cr)

(a)

Pr

SO-
S-R
CKO-
FLIP FLOP
RO -o

(b)

Fig, 7.7 (a) An S-R FLIP-FLOP with preset and clear

(6) its logic symbol

which means these are active-low, i.c. the intended function is performed
when the signal applied to Pr or Cr is LOW. The operation of Fig. 7.7 is
summarized in Table 7.2. 0 Te 2igtuo se
Table 7.2 Summary of Operation of S-R FLIP-FLOP

Inputs Output Operation performed

CK Cr Pr

Qnn (Table 7.1) Normal FLIP-FLOP

Clear
0 Preset
 aFLIP-FLOPS 207
ireuit can be designed such that
the
i.e. the ircuit can be set or
asynchronous inputs override
the clock, reset even in the
clock pulse (Prob. 7.3). presence of the

7.4 J - K FLIP-FLOP

ncertainty in the state of an S-R FLIP-FLOP

af truth table) can be eliminated by converting when S, R, =1 (fourth =

it into a J-K FLIP-FLOP.

data inputs are J and K which are ANDed
The
The
and R inputs, i.e.
with and Q respectively
to obtain S'

S-J-Q2 (7.1a)
R K (7.1b)
A J-K FLIP-FLOP thus obtained is shown in
Fig. 7.8. Its truth table is
oiven in Table 7.3a which is reduced to Table 7.3b for
73a has been prepared for all the possible
convenience.
Table
combinations of J and Kinputs
and for each combination both the states of the
dered. The reader can verify this (Prob. 7.4). output have been consi-

Pr

S=J. -o a
JO-
S-R
CKO-
KO- FF

D R KQ -oã

oue CrA
Fig. 7.8 An S-R FLIP-FLOP Converted into J-K FLIP-FLOP

Table 7.3a Truth Table for Fig. 7.8

Inputs to Outpur
Data Inputs Outputs S-RFF On+1
K, S R
0
0 0 1-
****e**ee*******a**

0 -
0 0=0
e
0 * * * * * *

0
1 1
O-
208 Modern Digital Electronics
Table 7.3b Truth Table
of J-K FLIP-FLOP

Output
Inputs
K Ont

0
0

It is not necessary to use the AND gates of Fig. 7.8, Since the same fune.
tion can be performed by adding an extra input terminal to each NANn
gate G and G of Fig. 7.7 (Prob. 7.5). With this modiication incorporat.
ed in Fig. 7.7, we obtain the J-K FLIP-FLOP uSing NAND gates as shoWn in

Fig. 7.9. The logic symbol of J-K FLIP-FLOP is given in Fig. 7.10,

otsridinoo daao not s

G -O

CKO

-oQ
KO-

Cr
Fig. 7.9 A JK FLIP-FLOP USing NAND gates

Pr n6 3

JO- -O Q
J-K
CKO-
FF
KO- -oG

Fig. 7.10 Loglo symbol of J-K FLIP FLOP

 alooE tait PLIP-FLOP 209
The Race-around Condition

dificulty of both inputs 1 (S

R= 1) being not
FLIP-FLO is inated in a J-K FLIP-FL allowed
in an S-R
by using the feedback connection
FLIP- ts to the inputs of the gates Ga and G (Fig.
7.9). Table 7.3
assumes that
that the inputs do not change during the
clock pulse (CK= 1).
which is not true because of the feedback connections. Consider, for
that the inputs are J= K=l and Q 0 and a pulse as shown
. 7.11 is applied at the cloCk input, After a time interval At equal
the propagation delay through two NAND gates in series, the output will
to the p
I(see fourth row of Table 7.3b). Now we
chau and after another time interval of Ar the have J=k =1
and
output will change
ck to Q=0. Hence, we conclude that for the duration 1, of the 'clock
otlse. the output will oscillate
back and forth between
0 and 1.
d of the clock pulse, the value of Q is uncertain. This situation is At the
end
referr
ed to as the race-around condition.
The race-around condition can be avoided if < At< T.
a he difficult to satisfy this inequality because t,of small
However,
very propaga-
tion delays in ICs. A more practical method of overcoming this difficulty
is the use of the master-slave (M-S) configuration discussed below.

s02t-tE 3Y Trailing (negative)

Leadingpositive) edgere goits
edge

-tp gid

Fig. 7.11 A clock pulse

TheMaster-Slave J-K FLIP-FLOP
A master-slave J-K FLIP-FLOP is a cascade of two S-R FLIP-FLOPs with feed-
ack from the outputs of the second to the inputs of the first as illustraied
in Fig. 7.12. Positive clock pulses are applied to-the first FLIp-FLOP and
ae clock pulses are inverted befofe these are applied to the second FLIP-
FLOP
When CK=1, the irst FLIP-FLOP is enabled and the outputs OM and
M respond to the inputs Jand K according to Table 7.3. At this time,
wthe seco FLIP-PLOP is inhibited because its clock is LOW (CK= 0).
Whe
C n CK goes LOW (CK= 1), the first FLIP-FLOP is inhibited and the

second FLIP-FLOP is because now its clock is HIGH (CK 1).

=

Therefore
enabled,
(secimd e outputs Q and follow the outputs QM and QM respectively
econd and third rows of Table 7.36). the second FLIP-FLOP simply
Since
follows the first one, it is referred to as the slave and the first one as the
master. Hence, this configura
,
is referred to as master-slave (M-S) FLIP-
FLOP.
 210 Modern Digital Electronics

Master Slave
0MSs
Jo

CKO

KO
DD
CK bo
Fig.7.12 A master-slave J-K FLIP-FLOP

In this circuit, the inputs to the gates Gaw and Gan do not change du-
ring the clock pulse, therefore the race-around condition does not exist.
The state of the master-slave FLIP-FLOP changes at the negative transition
(trailing end) of the clock pulse. The logic symbol of a M-S FLP-FLOP is
given in Fig. 7.13. At the clock input terminal, the symbol > is used to
illustrate that the output changes when the clock makes a transition
the accompanying bubble signifies negative transition (change in CK from
1 to 0).

Pr

M-S
CKO J-K
FF
KO -oa

Cr

Fig. 7.13 A master-slave J-K FLIP-FLOP

logic symbol
 FLIP-FLOPS 211

7.5 D-TYPE FLIP-FLOP

If we use only
the middle two rows
of the truth table of the S-R
7.1) or J-K (Table 7.36) FLIP-FLOP, We obtain a (Table
in Fig. 7.14. It has only one input referred to as
D-type FLIP-FLOP as shown

Its truth table is given in Table 7.4

D-input or data input.
from which it is clear that the
Ona1 at the end of the clock pulse equals the input D. before the output
clock
pulse.

Pr

Jor S O
DO Hoo Do-
J-K
or
CKO-d D
S-R CKO-d FF
FF
KorR -o -o

C Cr
(a) (b)
Fig. 7.14 (a) A J-K or S-R FLIP-FLOP COuverted intoa
D-type FLIP-FLOP (b) its logic symbol

oTh gTable 7.4 Truth Table of a D-type FLIP-FLOP

Input Output
D

This is equivalent to saying that the input data appears at the output at
the end of the clock pulse. Thus, the transfer of data from the input to the
Output is delayed and hence the name delay (D) FLIP-FLOP. The D-type
FLIP-FLOP is either used as a delay device or as a latch to store 1-bit of
binary information.

7.6 T-TYPE FLIP-FLOP

In a J-KFLIP-FLOP, if J = K, the resulting FLIP-FLOP iS referred to as a T-type
input, referred to as
LIP-FLOP and is shown in Fig. 7.15. It has only which
one
it is clear that if
nput. Its truth table is given in Table 7.5 from
clock pulse, the output Q
1it acts as a toggle switch. For every
changes.
 i0 de
iberny Nobodv al ant vufrom makinn
o isat

9o-d p-o
 FLIP-FLOPs 213
ln the
design of sequential
circuits, we usually come across
Which
we
the present
state and the next state
of the circuit are specified,
situations1n
have to find the and
transition
input conditions that must prevail to cause the desired
of the state.
By the
the circuit prior to andpresent
the state of state and the next state
aftor the clock pulse
we mean
example, the output of an S-R FLIP-PLOP before the clock respectively. For
On-0 and it is desired pulse 1s
pulse is applied. What that the output does not change when the clock
achieve this? input conditions (Sn and R, values) must exist to
From the truth
table (or the characteristic table) of an S-R FLIP-FLOP
(Table 7.1) we obtain the
1. S
following conditions:
2. R,=0 (first row)
We
S0, R, 1 (third row)
conclude from the above conditions
the that the S input must be 0 whereas
R, input may be either 0 or 1
(don't care).
can be found
for all possible situations. A Similarly, input conditions
1s known as the tabulation of these conditions
excitation table. It is a very
aid for important and useful design
sequential circuits. Table 7.6 gives the
J-K, T, and D FLIP-FLOPS. This is derived from exeitation tables of S-R,
the characteristic table of
the FLIP-FLOP.

Table 7.6 Excitation Table of FLIP-FLOPS bvodaadf

Present Next S-R FF J-K FF T-FF D-FF
State State S,R 00J, K, T, D,
0 0 X 0 0
0 0
10 1
0
X 0 0

7.8 CLOCKED FLIP-FLOP DESIGN

In earlier sections we defined or specified the operation of different FLIP-

FLOPS assuming a circuit without regard to where the circuit came from or
how it was designed. In this section, the design of a FLIP-FLOP is
given.
The design philosophy illustrated is, in fact, a general approach for the
design of sequential circuits and systems,
Consider the general model of the FLIP-FLOP shown in Fig. 7.17. Basic-
ally, a clocked FLIP-FLOP is a sequential circuit which stores the bits 0 and
1. This operation is accomplished by using a binary cell coupled with some
combinational set/reset decoding logic to allow some input control over the
set and reset operations of the cell. The steps for the design of FLIP-FLOP
are given below.
Step I: Examine each row of the given characteristic table, specifying che
 o oocooo
N

o oo

oo--o o

-o -o-o -o - o

xX oo- o-
o-o

XXXo X X-X -X -X -

- -X
-X - - x
 PLIP-FLOPS 215

Solution:
Step I: Determine the values of Yi and Y, for each row. For example, for
thefirst row On-0 and Ona0. To obtain Qn0, Y mustbe equal
to 1, since O n 1 . Y, can be 0 or 1 since O,=0. In a similar manner,
complete the truth table (Table 7.7).
Srep 11: The K-maps for Y and Y, are given in Fig. 7.18 which give

YCK4 3-CK S
bototh
Y R CK CKRo ult a noon
CKS CKS
ROn00 01 11 10 Ra 00 01 1110orno
00 1
oox1
ar alde 01 x
X- bna01
11

1o
Y2
Fig. 7.18 K-maps for Ex. 7.1

Thus, we see that the circuit resulting fron this desiga is the same as
that shown in Fig. 7.5.

Conversion From One Type of FLIP-FLOP to Another Type

In carlier sections, we have discussed conversion from S-R to J-K, S-R (or
J-K) to D-type, and J-K to T-type FLIP-FLOPs. Now, we shall effect the
conversion from one type of FLIP-FLOP to another type by using a formal
technique which is similar to the one used above and will be useful in the
design of clocked sequential circuits.
Consider the general model for conversion from one type of FLIP-FLOP

FLIP-FLOP FLIP-FLOP
Given
data Conversion FLIP-FLOP
inputs O Logic
-o

Fig. 7.19 The general model used to convert one type of FLIP-FLOP to another type
 Electronics
Digital
Modern type (Fig. 7.19). In this, we are required to design tho
to
216 another t
innuembj.
for converting new
decoder (conversion logic) FLIP-FLOP to
defini.
national logic
codes which will c a u s e the given
as
perforn
tions into input
desired. combine the excitation

To design the conversion logic we

need to
table with data input(s) andoe
tabl
and make a truth as
for both FLIP FLOPS FLIP-FLOP as the output(s).
the output(s)
the given The
the inputs and the input(s) of then follows
he a
of combinational logic design usual.
conventional method 7.2.
The conversion is illustrated in Example

Example 7.2
o Convert an S-R FLIP-FLOP to a J-K FLIP-FLOP.

Solution:
The excitation tables of S-R and J-K FLIP-FLOPS are given in Table 7.6
from which we make the truth table given in Table 7.8.

Table 7.8 Truth Table of Conversion Logic

Row FF Data Inputs Output S-RFF Inputs

J K S R

0 0 0

0 0
6 1 1 1D 0d
** * *°°°** *

0
0
0 x 0

The K-maps are given in Fig. 7.20 which give

t lt
S J.2
R K Q
Thus we see that the circuit
that shown in Fig. 7.8. resulting from this design is the same as

JK
O0 01 1 1 10
JK
O0 01 11 10
0 x

R
Fig. 7.20 K-maps for Ex. 7.2
 na FLIP-FLOPS 217

7.9 EDGE-TRIGGERED FLIP-FLOPS

in carlier
discussed
FLIP-FLOPS other than the master-slave type
All
to the inputs (acord
sections are level triggered, i.e. the outputs respond avail
clock is present. The only ICs
the
ing to the truth table) as long
as
are trans-
for example, 7475 and 74100
able in this category are latches,
parent latches.
the pulse-triggered
The master-slave FLIP-FLOPS are also referred to as
when a pulse 1s appiea
FLIP-FLOPs, i.e, the outputs respond to the inputs
responds when the clock
1s
pre
at the clock input. The master FLIP-FLOP
the falling
available at
sent (CK= 1) and the output of the
slave will be

Active transition
point
Juo

setup
thold
Inputs can change
Inputs c a n change
aee upto this point
from this point
o griivasht
(a)

FLIP-FLOP propa- Propagation delay

of next state
gation delay decoder

pd (FF)4 ns
thold
tsetup
tcH
cL
Clock period (Tc
h I n p u t s must
Inputs must U e r r e m a i n stable
remain s t a b l e r
(b) bo
specifications of FLIP-FLOPSs
to illustrate timing
Fig. 7.21 Typical clock waveforms
 Electronics
218 Modern Digital
discussed in Section 7.4, this als
As
clock pulse (CK= 0).condition. In this the
data is locked
edge of the race-around
at the
nates the problem of i.e. the changes occurring in.
the clock pulse, of the FLIP-FLOP
at the falling edge of affect the operation
not
CK goes to 0 will the presence of+
the
puts once
may change during
Theinputs to the FLIP-FLOP
the system.
This causes uncen
operations in
clock pulse due to certain which is
eliminated by using edae
of the FLIP-FLOP
tainty in the outputs
triggered FLIP-FLOPs.
FLIP-FLOP, the
transfer of information
In the case of an edge-triggered OCCurs at the positive
the FLIP-FLOP
from data input(s) to the output of The only time the outputs can
(or negative) edge of the clock pulse. the clock signal i
interval of time when
change state is during the brief
or in some circuits, from the
making a transition from the 0 to 1 (),
only to rising (or falling)
) states. A FLIP-FLOP which responds
I to 0is (referred
edge to as positive-edge-triggered (or negative-edge-triggered).
The data lock-out occurs at the end of the edge.
The logic symbol used for an edge-triggered FLIP-FLOP 1s the same as

that of a master-slave FLIP-FLOP.

The timing specifications of an edge-triggered FLIP-FLOP are illustrated
in Fig. 7.21 and are explained below
Set-up Time: It is the time required for the input data to settle in before
the triggering edge of the clock.

Hold Time: It is the time for which the data must remain stable after the
triggering edge of the clock.

Maximum Frequency: This is the highest

frequency of clock pulses for pro-
per and stable operation. It is given by
90J2-913
Jmax Tetsetup + tpd (7.2)
(FF)Tns
Clock HIGH Pulse Width (tCH): This is the
clock must remain HIGH.
minimum time for which the
ufas blon
Clock LOW Pulse Width (tcL): This is the
clock must remain LOW. minimum time for which the
Exampte 7.3
The clock (Fig. 7.22a) and input (Fig. 7.22b) waveforms
or J input of e. h of the
following types of FLIP-FLOPS. applied
are to D
put waveform in each case.
Sketch the ou
(a)
(6) Positive-edge-triggered D-type FLIP-FLOP 7474.Pum aluge
(c) Positive-level-triggered D-type FLIP-FLOp 7475 (transparent latch).
Negative-cdge-triggered
(d) Master-slave J-K
J-K FLIP-FLOP (K =
1) 74I12.
FLIP-FLOP (K =
1) 7476. la JeoireS
 FLIP-FLOPs 219

Clock
(a)
10 11
Input
Dor J) (b)

Q7474
(c)

7475 (d)

a 74112
(e)

(G
7476
g

Fig. 7.22 Waveforms of Ex. 7.3

Solution:
(a) In the case of positive-edge-triggered D-type FLIP-FLOP, the output Q
is same as the input D at the positive edge of the clock pulse. The
output does not change till the next positive edge arrives. The output
(2) waveform is shown in Fig. 7.22c.
(6) 7475 is a transparent latch, i.e. the output (2) follows the input (D) as
1. The output does not change when CK 0. The out-
=

long as CK =

7.22d.
put (Q) waveform is shown in Fig.
the output (Q)
(c) In the case of negative-edge-triggered J-K FLIP-FLOP,
responds to the J and K inputs present at the negative edge of the
clock pulse (according to J-K truth table). The output does not change
the next
till the arrival of The output (2) waveform is
negative edge.
shown in Fig. 7.22e.
the output of the
(d) In the case of the master-slave J-K FLIP-FLOP,
when CK 1 (accord-
=

master responds to the J and Kinputs present

of master (QM) is shown in Fig.
ing to J-K truth table). The output
7.22f. the negative edge of the
The output of the slave (2) follows OM at
shown in Fig. 7.22g.
clock pulse. The output (2) waveform is
 220 Modern
Digital Electronics
7.10 APPLICATIONS OF FLIPp-FLOPS

Some of the common uses of FLIP-FLOPs are as:

1. Bounce elimination switch,
2. latch,
3. registers,
4. counters,
5. memory, ete.
Some examples on the of FLIP-FLOPs
uses are given below.

Bounce-elimination switch
Mechanical switches are employed in
which digital information digital systems input devices as
(0 or 1) is entered into the system. There is by
very serious problem associated a
with these switches, viz.
(or chattering).
When the arm of the switch is thrown switch-bouncing
to
another, it chatters or bounces several times before from one position
rest in the
position of contact. The bounce is the result finally coming to
loaded impact of the switch of the
throw contact and the pole spring.
In a
sequential circuit, if 1 is to
be entered through a
a contacts
corresponding position. As soon asswitch,
Switch is thrown to the then the
this position, the it is thrown to
some time due to
output is I but the output oscillates between
make and break 0 and 1 for
contact before (bouncing) of the switch at the
coming to rest. This changes the output of the point of
circuit and creates
is
dificulties in the operation of the sequential
eliminated by using
bounce-elimination switches. system. This problem
Example 7.4
Show that the circuit of
Fig. 7.23a acts as
less)switch.ool sd ho a
bounce-elimination (chatter-
gbe vilieog sd Jds0g
Solution: vitssho 9iieg enpft t sgto 33 a 8ns
The waveforms at 7on 29ob Juguo
S, R, Q and Q are
(SW) thrown from position A to illustrated in Fig. 7.23b. The switch
is
voltage at S will be Vcc (logic and B at t 0. Therefore at t 0* the
1) will
=

thrown to position A continue to remain so as long as

the switch is not
At R (B), the again.
voltage at
is 0
(logic 0) ( being the time delay of the Vcc (logic 1) and goes to 0V
at h
contact at B
at t= t1, and then switch). The switch arm
changes from 0 to 1 and vice-versa.bounces off. Therefore, the level makes
at R
Between = 0 and This
is illustrated in
, both the Fig. 7.23b.
therefore Q does not inputs S and R are at
logic 1 and
Now, even when R change. The output Q
changes at
shows that it is a
is
changing at ta, ts, etc. Q doestynotand becomes 0.
The latch
chatterless switch. change. This
used in Fig. 7.23a can
a
quad S-R latch. be replaced by the IC 74279 which 1s
 FLIP-FLOPS 221

sw B
D
-o0
eio L- -J oe
of Latch
(a)

(b)
Fig. 7.23 (a) A bounce-elimination switch (b) Waveforms

of3, R, Q and
Registers
A register is composed of a group of FLIP-FLOPS to store a group of bits

3-bit Input

D2(MSB) Do (LSB) adr

boronoo ai 9
Preset Ob- be1sel
30 Jsnimol
bolaaaeu a-o0,4b Pri Pr o G0
CK FF2 CK FF1 CK FFO
3tlug
Gr Cr
R/WotClear O 9
Read

ClockO
Fig. 7.24 A 3-bit register using FLIP-FLOPS
 222 Modern Digital Electronics

number of FLIP-FLOPs
(word). For storing an N-bit word, the require-edge-is
7474 positive-
N (one FLIP-FLOP for each bit). A 3-bit register using 74
triggered FLIP-FLOPs is shown in Fig. 7.24. The bits to be stored
applied at the D-inputs which are clocked in at the are
clock pulse. In this register, the data to be entered must be availahi.e
leading-edge of
parallel form. Other types of registers will be discussed in Chapter 8. e in

Counters
Digital counters are often needed to count events. For example, count :
the number of tablets filled in a vial. Electrical pulses ing
the event are produced using a transducer and these
corresponding
t
pulses are counted
using a counter.
The counters are composed of FLIP-FLOPS. A 3-bit counter
three FLIP-FLOPS is shown in Fig. 7.25. A circuit with consisting of
n-FLIP-FLOPs has 2
possible states. Therefore the 3-bit counter can count from
decimal0 to 7.

Outputs
To TT21
To o Go
Pulses O- FFO
to be CK FF1
|CK FF2
counted

o Cr
cr Cr
Clear O

Fig. 7.25 A 3-bit counter

using FLIP-FLOPS suiga
The FLIP-FLOPS used are
74107 J-K master-slave
T-type. The pulses to be counted are connected FLIP-FLOPS, used as
The Qo output of FFO is at the clock input of FFO.
connected to the
1 is connected to the clock input FF2. clock input of FFl and similarly
The FLIp-FLOPS are cleared of
by applying logic 0 at the
terminal momentarily. For clear input
normal
tained at logic 1. 1The pulses and the counting operation, is to be main
it
Fig. 7.26. output waveforms
The output Qo of the
iliustrated are i

least-significant stage changes at the

ofeach pulse (since T,1). The output
Q changes at the
negative cdg
of each o pulse (since Qo acts as CK for FF1 and negative cog
Q changes at the negative edge of each T=1) and the outpu
FF2 and T= 1). Qi pulse (since Qi acts
as 0A
9N
At any time, the decimal equivalent of the
binary number Qa Qi o
asot- gpia 191eigs tid-CA T-s
 FLIP-FLOPS 223

Pulses
be
counted

1
0

Fig. 7.26 Waveforms of counter of Fig. 1.25

oa ti 0
the number of pulses counted till that time. For example, at x the count
is 100 (decimal 4). The circuit resets after
counting eight pulses.
There are various types of counters, some of which will be discussed in
the next chapter.

Random-Access Memory
In computers, digital control systems, information processing systems, etc.
it is necessary to store digital data and retrieve the data as desired. For
this purpose, earlier only magnetic memory devices were possible, whereas
these days it has become possible to make memory devices using semi-
conductor devices. Semiconductor memories have become very
popular
because of their small size (availa le in ICs) and convenience to use.
Chapter 11 deals with various semiconductor memories.
FLIP-FLOPS can be used for making memories in which data can be
stored for any desired length of time and then read out whenever
In such a memory, data can be put into
required.
(writing into the memory) or
retrieved from (reading from the memory) the memory in a random fashion
and is known as random-access memory.

D-
(Data input)
G3 Do
Level D (Data output)
FF

a9inols

CAddress
select) a i bovaxos
R/wo
(Read/ write control) s r lo otatoqo bolicio 3
Fig. 7.27 A 1-bit read/write memory cell
 Electronics
224 Modern Digital
shown in Fig. 7.27 which io
1-bit read/write
memory is
s
the basic
A memory ICs
are built around a system of
basic 1-bit
memory element and
cell. level D is used which has
FLIP-FLOP
In this memory cell,
a o
long as G terminal is at logic 1. The Put
follows the D input
as
that does not change and iment
to logic 0, the Q output
the G input changes
ition from 1 to 0
existed just before the transition
tains
the D input level that at
is used to select the memory cell. In the 1-bit
input G. This input cell
shown there are three inputs-D (data input), A (address sele
R/W (read/write control) and one output Do (data output). A,=1 enables
the cell for reading or writing operation, RJW at logic 1 is for readiling
from the cell and 'ogic 0 for writing into the cell. As long as all
input and output activities are blocked, and the cell is in the hold mod.
ode
where its stored output is protected.
The complete function of this cell can be understood from the function
table of Table 7.9. The read operation is nondestructive, that is, the stored
bit can be read out any number of times without disturbing it. The stored
bit will be protected as long as power is on. Therefore this type of memory
is known as volatile memory.

Table 7.9 Function Table of 1-bit Memory Cell oun

Inputs Mode
RIW D
Hold, D = 0
1 0 d 03 Write 0 into memory,
1 oldei D, =0
0 2032h 198 G Write 1 into memory,
X
20 b Do,= 0
to l Read, D, = Storedo
D; bit.

As far as writing into the cell is concerned, it is not

entering the new bit. Whenever a new bitrequired
to be
cleared before
is entered the
earlier one gets destroyed automatically.

7.11 SUMMARY

The basic element of

sequential circuits, FLIP-FLOP has been
here. This is a basic
memory element which is used to stôre 1-bitintroduced
of digital
information. The four types of
commonly
T-Aype, and D-type have been covered in used FLIP-FLOPS S-R, J-A
gates, detail, including
their design USIng
The various
triggering systems have been discussed which will be
helpful in understanding the detailed vesy
circuits containing these operation of the FLIP-FLOP and o er
FLIP-FLOPS. eA g
 FLIP-FLOPS 225

of the uses of FLIP-FLOPS in registers, counte

Simple examples will be covercu
elements, etc. have been included. These
topics
memory
in greater detail in later chapters.

PROBLEMS
1.3.
0 is the same as that of Fig.
7.1 Show that the circuit of Fig. 7.4 with S= R =

7.2 In a circuit of Fig. 7.4 if the inputs change from

(a) S-1, R=0 to S -R=0, and
(6) S=0, R= 1 to S =R=0,
show that the outputs do not change.
7.3 In the FLIP-FLOP circuit of Fig. 7,28 show that if
(a) Pr=0 and Cr =
1, then Q =
1 (independent of S, R, and CK).
(6) Pr=1 and Cr= 0, then Q =0 (independent of S, R, and CK).
(c) Pr= Cr=1, then it functions as a clocked S-R FLIP-FLOP

SO

CKO-

ROD D D l
Fig. 7.28 FLIP-FLOP circuit for Prob. 7.3

7.4 Verify Table 7.3a.

7.5 Determine the output Y1 of Fig. 7.29a and Y, of Fig. 7.296 and show that Y,= Y,

JO JO-

D
CKO

(a) (b) o
Fig. 7.29 Figures for Prob. 7.5

7.6 Verify that the circuit of Fig 7.16 acts as a toggle switch.
7.7 Prepare the truth table for the cireuit of Fig. 7.30 and show that it acts as a 7-type
FLIP-FLOP.
 Electronics
226 Modern Digital

TO-
S-R
CKO-o
FF
-oã

7.7
Fig. 7.30 Circuit for Prob.
7.8 If Qoutput of a D-type FLIP-FLOP is connected to D input, it acts as a toal
switch. Verify.
7.9 Using the method outlined in Sec. 7.8, design the following FLIP-FLOPS:
(a) J-K
(6) D-type
() T-type
7.10 Using the conversion method outlined in Sec. 7.8, carry out the followin
conversions:
(a) S-R to D
(b) J-K to D
(c) D to J-K
(d) S-R to T
(e) J-K to T
) Tto J-K
&) Tto D
(h) D to S-R
) D to T
) Tto S-R
k) J-K to S-R
7.11 Figure 7.31 shows a
positive-edge-triggered D FLIP-FLOP. Verify its operation.

Clock O-
(CK)
D
O
Data O-

Fi . 7.31
Positive-edge-triggered D FLIP-FLOP
 FLIP-FLOPS 227

7.12 IC 74111 is a master-slave J-K FLIP-FLOP with data lock out at the positive edge
of the clock (the state changes at the negative edge of the clock).
If the waveform shown in Fig. 7.22a is applied at the clock input and the
waveform of 7.22b is applied at the J input, sketch the output (O) waveform when
(a) Kis connected to logic 0
(b) Kis connected to logic 1.
7.13 Verify the operation of the debounce switches shown in Fig. 7.32.

da Pr
7404

7.474
90 7404
Cr -oa

(a) (b)
Fig. 7.32 Debounce switches for Prob. 7.13

7.14 Consider the circuit of Fig. 7.33 consisting of positive-edge-triggered FLIP-FLOPS.

Ar and Ar, are the time delays introduced in the clock (CLOCK SKEW) by
buffer devices and the propagation delay of wires. At the rising edge of the clock,
new data enters the source FF and the content of source FF enters the destination
FF. Show the effect of clock skew (At > A) on the operation of the circuit.
Discuss the problems created by clock skew for data transmission.

Ds
CKs Source CKp Destination
L FF FF

Clock O- at

Fig. 7.33 Circuit for Prob. 7.14

228 Modern Digital Electronics

pulse) is shown in Fig. 7.34,

7.15 A mod-3 counter (resets after every three The Dr s.

FLOPS Used are master-slave J-K. Sketch the waveforms of Q, and Q when clock
pulses are applied and verify its operation. Assume Qo 1 - 0 initially.

O CK FFO oCK FF1

C
Logic1 o
Clock O
pulses
Fig. 7.34 A mod-3 counter