Evolving passive optical networks (PONs) demand FPGA

design flexibility
edn.com/evolving-passive-optical-networks-pons-demand-fpga-design-flexibility

EDN March 12, 2008

Overview
FPGA technology, low cost optics, and a passive architecture have made significant
contributions to passive optical networks (PONs) and to the evolution of these networks.
System OEMs continue to discover that FPGAs deliver both technical design and economic
benefits, especially at the central office (CO) infrastructure end of the network side.

Prior to 2002, lower-performance FPGA generations served primarily as prototyping tools.

Today's FPGAs are high performance, feature rich, and well suited to meet growing PON
design requirements. Plus, FPGAs that offer lower design costs, flexibility, and scalability are
the linchpin for turbo-charging the PON market.

A PON is a point-to-multi-point (P2MP) fiber to the premises (FTTP) network topology, which
may also be defined as fiber to the curb (FTTC) and fiber to the home (FTTH). Either FTTP
or CPE (customer premises equipment) is used in the PON definition. Un-powered or
passive optical splitters are used so that a single optical fiber serves multiple premises;
usually 32, but as many as 64. A PON comprises an optical line termination (OLT) at the
service provider's CO and a number of optical network terminals (ONTs), also known as
optical network units (ONUs) going to the premises.

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1. DSL and PON topologies side-by-side.
Downstream OLT signals are broadcast to each ONT sharing a fiber. Current PON standards
have defined downstream data rates up to 2.5 gigabits per second (Gbps). Upstream signals
are combined using time-division multiplexed (TDM) access. Compared to digital subscriber
line (DSL) or cable, PONs offer an unparalleled bandwidth advantage for high-speed triple
play services (voice, video, and data).

According to Infonetics, PON subscribers are expected to grow dramatically at a compound

annual growth of 150 percent through 2010 in North America and Asia Pacific. Gigabit PON
(GPON) is making strong headway in North America, while Ethernet PON (EPON) is mostly
used in Japan. Japanese government subsidies are helping to grow the PON market
substantially year to year, while EPON and GPON is being carefully weighed in China.

Broadband PON (BPON) or International Telecommunications Union (ITU-T) G.983x is the

prevailing U. S. PON standard. It features a maximum downstream data rate of 622
megabits per second (Mbps) and 155 Mbps upstream. Passive optical splitters installed in
the fiber allow up to 64 subscribers to use the line. This year, GPON or ITU-T G.984, an
evolution of BPON, is expected to enter greater numbers of U. S. premises. It supports TDM
and packet data with data rates of up to 2.5 Gbps downstream and 1.24 Gbps upstream. Key
GPON advantages are support of switched digital video and native TDM voice without
having to add IP.

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Cost sensitive
Regardless of standard, PON systems deployed for broadband access are highly cost-
sensitive. DSL is currently the most widely used technology for broadband access. DSL has
set the bar for cost per port at an extremely aggressive level based on today's volumes.
Consequently, DSL poses a strong challenge to PON. But PON systems have steadily
continued to evolve in the last two years with low volumes and increasingly ambitious feature
sets.

As the PON market develops, system OEMs and carriers are looking closely at reducing
costs, particularly for OLT. On the ONT side, volume is expected to increase into millions of
units due to the millions of premises PONs will serve. A number of ASIC and ASSP suppliers
are focused on ONT with a variety of chip offerings. Since ONT is a high volume market
segment, ASIC and ASSP suppliers can help drive costs down and enable system OEMs
and carriers to offer lower prices.

On the other hand, OLT system volume is in the tens of thousands, not millions and is
characterized by higher costs. For example, PON home modems costs range from $100 to
$300, while PON infrastructure OLT systems cost about $10,000. In particular, OLT costs
have been extremely critical for carriers and are largely centered on multi-port line cards that
handle an increasing number of premises.

Volume expectations for OLT line cards remain moderate to low in the foreseeable future
based on two key reasons. First, only one OLT port is required for up to 64 ONTs; secondly,
each OLT line card can support four to eight OLT ports. Thus, the number of OLT line cards
and components is dramatically lower than that used for high volume ONT equipments.

Design complexity compounds the cost issue. The PON OLT and ONT topology is a shared
media architecture that creates challenges for system OEM designers. Interaction between
OLT and individual ONTs becomes highly complex due to TDM in PON standards. TDM is
used to share capacity between different premises. Early PON standards initially used static
TDM so that each premise received the same capacity.

However, newer PON standards call for capacity to be dynamically assigned to different
premises, according to a premise's changing requirements. This dynamic bandwidth
allocation (DBA) requires signaling between ONTs and the OLT to inform the OLT of the
capacity needs for each ONT. The OLT also needs to inform each ONT about the allocation
of capacity. This scheme's protocol is based on request messages from the ONTs to the OLT.
The OLT determines the best capacity allocation and responds with grant messages.

Also, unlike simpler Ethernet ports which are point-to-point, PON ports are more complex
P2MP due to the dynamic TDM requirements. As a result, OLT ports must continuously
switch between multiple ONT premises. ONTs are allocated one of 32 or one of 64 available
time slots to interact with the OLT. The OLT has to rapidly and continuously lock to one ONT

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data stream after another, also known as burst mode. A highly specialized media access
controller (MAC), serial/deserializer (SerDes), and clock and data recovery (CDR) functions
are necessary to support this blazingly fast locking scheme. A PON MAC is especially critical
for coordinating access to each ONT.FPGA-based design
Against this backdrop, system OEMs have few low-cost and effective OLT design choices.
One option is to develop the design using ASIC technology. But this involves an extremely
high investment. ASSPs also do not bode well for several reasons. ASSPs have limited
flexibility to support evolving PON requirements. ASSPs lack design scalability and have
increasing power consumption with increased clock rates. ASSPs offer limited competitive
differentiation options, plus a big risk of device obsolescence. As well as having an increased
cost of ownership and delayed time to market.

However, FPGAs offer lower cost, more effective platform for developing an OLT design.
Costs are further reduced when the design is seamlessly migrated to a structured ASIC for
volume production. By taking this migration route, system OEMs take a major cost savings
and faster time-to-market detour since it eliminates the large, time-consuming ASIC
investment.

FPGAs, like Stratix devices, provide the high-performance logic necessary to implement and
integrate major OLT line card functions (see Fig 2 ). But also, FPGAs are the technology of
choice for implementing EPON and GPON MACs, both at CO OLT and ONT customer
premises. Plus, PHY and MAC can be integrated in an FPGA to form a virtual line card on a
chip. An advanced, highly-efficient core fabric of an FPGA is based on innovative logic units
called adaptive logic modules (ALMs).

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2. Distributed versus centralized architectures for OLT line cards.
Each ALM has eight inputs with a fracturable look-up table (LUT), two dedicated embedded
adders, two dedicated registers, and additional logic enhancements (see Fig 3 ). These
features allow the ALM to implement a full 6-input LUT or select a 7-input LUT. They can also
be used to create two independent outputs of multiple combinations of smaller LUT sizes for
efficient logic packing. Thirdly, complex logic-arithmetic functions can be implemented
without additional resources.

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3. FPGA ALM block diagram.
ALMs are routed with a multi-track interconnect architecture enabling the FPGA to implement
high-speed logic, arithmetic, and register functions. Multi-track provides high levels of
connectivity and accessibility to surrounding logic array blocks (LABs) with fewer
connections. Plus, it avoids area congestion for better logic packing.

High-performance logic, well-distributed and configurable memory blocks, and efficient

placement and routing tools are required for implementing MAC and packet processing.

Also, forward error correction (FEC) plays a significant role in supporting PON P2MP
topology. Programmable logic is ideal for implementing FEC for two reasons. First, it is
inherently flexible, easing coding modification and improving algorithms. Plus, the high-
performance and density optimally align with PON system requirements in an FPGA. Unlike
ASSPs that are designed specifically for FEC, FPGAs offer system designers the speed of
hardware and the flexibility of software while implementing FEC functions.

Scaling profitable designs

From an overall design perspective, an FPGA enables designers to quickly implement and
verify functionality of an OLT application. Moreover, an FPGA-based design can be easily re-
programmed to make changes or additions without incurring major design overhead. Another
system OEM benefit is having the capability of building an OLT line card portfolio featuring
different functionalities, all using the same board-level design and assembly. For example, a

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high-end OLT card can use a high-performance FPGA integrating the MAC and traffic
management. On the other hand, a lower end card can use a reduced performance FPGA
with the same footprint to implement only the MAC. Here, costs are scaled without having to
maintain different boards and associated bills of materials (BOMs).

Further, device flexibility and scalability enable designers to begin modestly with a low level
portion of an OLT design and incrementally scale it as more features and functions are
required. A major US carrier provides a recent example of an expanding and changing PON
requiring scalability like this. The carrier deployed IPTV services as part of its PON by
providing an RF overlay. It added a second wavelength inside the optical fiber for IPTV to
complement an existing one used for Internet access.

The ever-changing nature of PONs reflect the need for fast and cost-effective upgrades.
FPGA scalability helps designers avoid the high cost and design time involved in redesigning
OLT line cards each time new functionality is added. Designers can exploit inherent FPGA
scalability to continue adding features and functions as PON standards evolve. In effect, an
FPGA-based design gives system OEMs a sustained roadmap for economically adding
those enhancements at the most opportune market windows.

Low-cost design scalability thus becomes a major contributor to continued PON market
growth. As part of this expansion, both system OEMs and carriers can anticipate PON OLT
line cards that can be remotely configured in the field, thanks to reprogrammable and
scalable FPGA-based designs. Hence, system OEMs are relieved of major R&D outlays for
new designs. Likewise, carriers are alleviated of high operating expenses (OPEX). Currently,
some are having problems keeping up with constant network upgrades without maintaining
the same revenue stream. But with the aid of reconfigurable PON systems, carriers can
boost their profits by offering services they can economically scale as premise demand
changes.

FPGA-based designs also permit system OEMs to create staggered pricing/expanding PON
feature plans so that they are well positioned to conduct efficient business planning with
carrier customers. New upgrades and their associated costs can be negotiated well ahead of
the time carriers need them, and accordingly, they can be better organized for profitable
operations.

After carriers complete initial network trials and are ready to place large quantity equipment
orders, system OEMs can seamlessly and cost-effectively migrate an FPGA-based design to
a functionally equivalent structured ASIC like HardCopy II. This design methodology provides
system OEMs with a host of benefits.

It allows reaching the market six to nine months earlier than standard-cell technology. New
functions, features, or even complete products can be created at a fraction of traditional
development cost. They can demonstrate fully-functional designs to carrier customers before

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committing to structured ASIC silicon. Plus, they can show multiple variations, customized to
perform certain PON features. Best of all, the design can quickly move from prototype to low-
cost production while minimizing engineering cost and effort.

The high cost of the most advanced FPGAs can be reduced by up to 90 percent using
structured ASICs (Fig 4 ). Such design migration guarantees worst-case system timing, while
removing programmable elements and interconnect to shrink die size and resulting cost.

4. Cost-effective, FPGA-based design platform.

Outlook
The PON challenge for system OEMs and carriers is focused on continual cost reduction that
will put them ahead of DSL. DSL still maintains leadership as far as low-cost access
networking to the premises. At this time, various carriers are deploying different and
changing ways of providing customer services. For the system OEM, this means supporting
the next levels of those evolving requirements.

The flexibility and scalability of FPGAs pave the way toward efficiently meeting those
evolving requirements and reducing costs. For example, FPGA-based design investments
for first and second generation OLT line cards can be carried into a third generation with an
incremental investment to meet those carrier needs.

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These attributes also play a pivotal role in dealing with uncertainties inherent to the evolving
standards of PONS going forward. Those uncertainties relate to data rates and a variety of
application-level standards.

There is an uncertainty about how the two PON standard bodies, ITU-T and IEEE, will move
to the next data rates within their respective standards. Also, those standards bodies are
presenting a variety of application-level standards. This alone spawns a wide assortment of
uncertainties. Questions arise as to which application will gain greater acceptance at which
level of volume. Also, which carriers will want which applications and in what priority?

These issues will continue wavering for the foreseeable future, but for certain will be market
driven. Consequently, the burden falls on system OEMs to expeditiously respond to these
different market demands. These uncertainties are best resolved with FPGAs, rather than
with fixed architecture solutions.

Nilam Ruparelia is Senior Marketing Manager, Communications Business Unit, Altera

Corporation. Nilam has more than sixteen years of experience in the semiconductor industry
focusing on ASICs, ASSPs, and FPGAs targeted at the communication infrastructure market
with companies such as Altera, Cypress Semiconductor and Arcus Technologies.

Nilam's current responsibilities with Altera include driving marketing efforts for the broadband
access market segment, as well as focusing on marketing initiatives to key customers.
Previously, he has led the development and launch of numerous framer / mapper, PHY, and
specialty memory products. Nilam holds a B.S. degree in electrical engineering from Gujarat
University, Ahmedabad, India.

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