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Session 3

This document contains exercises related to analog electronics circuits. Exercise 1 involves analyzing a differential amplifier circuit, including deriving equations for voltage gain and output voltages. Exercise 2 analyzes an operational transconductance amplifier (OTA) circuit, involving deriving equations for voltage gain and determining design parameters to meet specifications for gain, bandwidth, and input/output voltage ranges. The exercises involve using provided figures and equations to calculate values for various circuit parameters.

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hung kung
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© © All Rights Reserved
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Download as PDF, TXT or read online on Scribd
30 views

Session 3

This document contains exercises related to analog electronics circuits. Exercise 1 involves analyzing a differential amplifier circuit, including deriving equations for voltage gain and output voltages. Exercise 2 analyzes an operational transconductance amplifier (OTA) circuit, involving deriving equations for voltage gain and determining design parameters to meet specifications for gain, bandwidth, and input/output voltage ranges. The exercises involve using provided figures and equations to calculate values for various circuit parameters.

Uploaded by

hung kung
Copyright
© © All Rights Reserved
Available Formats
Download as PDF, TXT or read online on Scribd
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Brussels, November 25, 2021

Analog Electronics Exercises


session 3
Contact: Thomas Gorzka, M.Sc.
[email protected]

Exercise 1
In Fig. 1 a differential pair with resistive load is given. Assume for simplicity
that in this circuit the bulks of M1 and M2 are connected to their source con-
nections thanks to triple-well-technology. Moreover, assume for VD = 0V that
M1 and M2 are in strong inversion and assume VDsat = VOV .

Figure 1: Differential amplifier with ideal current source

vout,− vout,+
a) Give the equation of the small signal voltage gain vD , vD and the
differential voltage gain, when VD = 0?

Analog Electronics -1- session 3


Brussels, November 25, 2021

Figure 2: Vout as a function of vD

b) Draw on Fig. 2 the voltages Vout,+ , Vout,− and V0 and on Fig. 3 (Vout,+ −
Vout,− ) qualitatively. Moreover, indicate on both figures:
√
(i) VOV and 2VOV ,
(ii) AV ,
(iii) range, where M1 and M2 are in strong inversion,
(iv) range, where M1 is in weak inversion, but M2 in strong inversion,
(v) range, where M1 is in strong inversion, but M2 in weak inversion.

c) Give the amount of current, which is flowing through M1 and M2 , when


(i) VD = 0,
√
(ii) VD < − 2 · VOV ,
√
(iii) VD > 2 · VOV .

Analog Electronics -2- session 3


Brussels, November 25, 2021

Figure 3: Vout as a function of vD

d) Based on Fig. 3, derive an equation describing the relationship between


Vswing , VOV and AV .
Remark: Vswing = max(Vout,+ − Vout,− ) − min(Vout,+ − Vout,− )

Analog Electronics -3- session 3


Brussels, November 25, 2021

Now the considered circuit is extended with a current mirror (Fig. 3) and
your employer mandates the following specifications:
• Pdiss = 1.2mW ;
• Vswing = 0.8Vpp ;
• AV = 0dB;
• VDD = 1.1V ;
• Vth,n = 0.4V ;
• Ibias = 100µA.
Moreover, assume for simplicity that that VDsat = VOV in this exercise.

Figure 4: Differential amplifier with current mirror

e) Give Vswing as a function of Ibias .


gm
f) Calculate, what ID is required to have exactly AV and Vswing .
g) Calculate R and gm such that this circuit passes exactly the Vswing -, Pdiss
and AV -specification.
h) Calculate the required width W1 and W2 as well as L1 and L2 with aid of
Fig. 5 and Fig. 6.
i) Decide what length L1 , L2 and VOV you would choose for M3 and M4 .
Explain why? Then, calculate the width W3 and W4 with aid of Fig. 6.
j) Calculate the minimum allowed input common mode voltage Vcm,min,in .
What happens, if one sets Vcm,in < Vcm,min,in ?

Analog Electronics -4- session 3


Brussels, November 25, 2021

Figure 5: gm /IDS as a function of VOV

Analog Electronics -5- session 3


Brussels, November 25, 2021

(a) W as a function of VOV for fixed gm

(b) W as a function of VOV for fixed iDS

Figure 6: plots for calculating required width

Analog Electronics -6- session 3


Brussels, November 25, 2021

Exercise 2
Now an OTA is considered (Fig. 7) and it is assumed again for simplicity that
in this circuit the bulks of M1 and M2 are connected to their source connections
thanks to triple-well-technology. Moreover, assume following specifications:
• VDD = 1.1V
• Vth,n = 0.4V , Vth,p = −0.22V
• fGBW = 716M Hz
• CL = 500f F

Figure 7: OTA

a) Give the small signal voltage gain equation of this circuit including the
capacitances and indicate
(i) dominant pole,
(ii) non-dominant pole,
(iii) zero.
b) Assume the pole-zero-doublet to be far away from the dominant pole.
Draw the bode- and phase plot and indicate location of the dominant pole
and GBW.
c) What happens to the pole-zero-doublet, if one increases/decreases the VOV
of M5 and M6 assuming that the current flowing through M4 is fixed as
well as the lengths are fixed?

Analog Electronics -7- session 3


Brussels, November 25, 2021

d) Assume VOV,3,4 = 0.2V , VDsat,5,6 = −0.25V and VOV < −0.1V for the
remaining devices. With aid of Fig. 9, calculate the maximum/minimum
possible output common mode voltage Vcm,max,out and Vcm,min,out , where
all transistors are still in saturation.
e) The designer decides to set the output common mode voltage for vD = 0
to the midpoint between Vcm,max,out and Vcm,min,out . Explain how and
calculate for that the required VOV .
Hint: Examine the PMOS pair for vD = 0.
f) Find and explain a suitable simplification of the equation from ”a)” such
that Fig. 8 becomes useful for designing the OTA. Then, calculate the
required VOV and Vin,cm,min for M1 and M2 to achieve AV > 8.
g) Calculate Vin,cm,max .

h) Assume a current of I0 is flowing through M4. Given that all transistors


are in saturation, determine what current ICL flows through CL , if
(i) VD = 0,
(ii) VD < −X: M1 is in weak inversion and M2 in strong inversion,
(iii) VD > X: M1 is in strong inversion and M2 in weak inversion.
Moreover, determine X.
i) Calculate the SR, the required I0 and gm,1,2 necessary to pass exactly the
fGBW -requirement with aid of Fig. 5. After that, calculate gm,5,6 .

Analog Electronics -8- session 3


Brussels, November 25, 2021

gm
Figure 8: gds as a function of VDS

Analog Electronics -9- session 3


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Figure 9: VDsat as a function of VOV . Assume VDsat (VOV = −0.1V ) ≈ 50mV


for L = 1um and L = 65nm

Analog Electronics - 10 - session 3

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