Ch3

DC-DC Converters

Ch3-1

Introduction

 Convert a dc voltage to a different dc voltage

level, often providing a regulated output
 Classified as switched-mode dc-dc converters,
also called switching power supplies or
switchers

Ch3-2

1
 DC-DC Converter Scheme

AC line Regulated
voltage DC

Ch3-3

Linear Voltage Regulator

Vo  I L RL ( Vs ), Ps  Vs I L , Po  Vo I L , PBJT  VCE I L
 Load current is controlled by BJT. By adjusting the IB to
compensate for variations in the source or load, thus
P V V
regulating the output voltage   
o o o

Po  PBJT Vo  VCE Vs
 Power dissipates in BJT is large, leading to low efficiency
 Suitable only for low-power applications Ch3-4

2
 Basic Switching Converter
 An efficient alternative to the linear regulator is the
switching converter (SC)
 In SC circuit, the transistor operates as an electronic
switch by being completely on or completely off
 Saturation or cutoff for a BJT or the triode and cutoff
regions of a MOSFET
 This circuit is also known as a dc chopper

Switch operated in fully saturation or cut-off region Ch3-5

Basic Switching Converter

 vo = Vs as switch is closed, and vo = 0 as switch is open

 Periodic opening and closing of the switch results in
the pulse output of vo Ch3-6

3
 Basic Switching Converter
 The vo average or dc component Vavg  vo (t )
1
vo (t )dt    Vsdt   0dt 
T DT T
Vo 
T 
0  0 DT 
1
  DT Vs  = DVs  vo
T 
t on t  f : switching frequency
D  on  t on f 
t on  t off T T : switching period
 The dc component of the vo is controlled by adjusting
the duty ratio (cycle) D
 D is defined by the fraction of the switching period
that the switch is closed (ton)
 For this circuit, Vo  Vs Ch3-7

Basic Switching Converter

 The power absorbed by the ideal switch is zero
 When the switch is open, there is no current in it; when
the switch is closed, there is no voltage across it
 All power is absorbed by the load, and the energy
efficiency is 100%
 However, losses will occur in a real switch because the
voltage across it will not be zero as it is on (conduction
loss)
 And the switch must pass through the linear region
when making a transition from one state to the other
(switching loss)
Ch3-8

4
Power Loss in an Ideal Switch

In practice, real switches mainly include switching losses

and conduction loss
Ch3-9

Pulse-Width Modulation (PWM)

Duty Ratio (Cycle ) D

t on vcontrol
D 
Ts Vˆ st

Ch3-10

5
Pulse-Width Modulation (PWM)

1 T 1 DT
Vo 
T 
0
vo (t )dt 
Ts 
0
Vs dt DVs

t on t on
Duty ratio: D    t on fs
t on  toff T
Ts : switching period
fs : switching frequency
Ch3-11

Buck (Step-Down)
Converter

Ch3-12

6
Introduction to Buck Converter
Vavg  v o (t )  Vo  DV s

 Fig. (c) may be sufficient for some applications, such as

dc motor speed control
 But often the objective is to produce an output that is
purely dc
 One way of obtaining a dc output from the circuit of Fig.
(a) is to insert a low-pass filter (LPF) after the switch
Ch3-13

Buck Converter
single pole single throw (SPST)

LC LPF

 The diode D provides a path for the iL as switch is

opened and is reverse-biased as switch is closed
 This circuit is called a buck or a step-down converter
because the output voltage is less than the input (Vo < Vs)
Ch3-14

7
Voltage - Current Relationships
vx  Vs , Qon, D off

vx  0, Qoff , D on
If Q is on periodically
at a duty ratio D
LC LPF  avg[vx ]  Vx  DVs

 If the LPF is ideal, the output voltage (Vo) is the average

of the input voltage (vx) to the LC filter
 iL remains positive throughout the switching period is
known as continuous current mode (CCM)
 Conversely, discontinuous current mode (DCM) is
characterized by iL returning to zero during each T
Ch3-15

Properties in Steady State Operation

1. Inductor current is periodic
i(t  T )  i(t ), v(t  T )  v(t )
2. Average inductor voltage is zero
1 t T
avg[vL (t )]  vL (t )  VL   vL ( )d  0
T t
3. Average capacitor current is zero
1 t T
avg[iC (t )]  iC (t )  IC   iC ( )d  0
T t
4. Power supplied  power delived to load  losses
Ps  Po (ideal)
Ps  Po  Ploss (nonideal)
Ch3-16

8
 Analysis Assumptions

LC LPF
1. Circuit is operating in steady state (SS)
2. iL is continuous (always “positive +”)  CCM
3. C very large  Vo holds at constant value
4. Q closed time (ton) = DT, opened time (toff) = (1-D)T
5. Components are ideal
Ch3-17

Analysis Conceptions

LC LPF
 The key to the analysis of determining the Vo is to
inspect the iL and vL first for the Q closed and then for
the Q open
 The net change in iL over one period must be zero in
steady-state operation
 The average inductor voltage is zero, apply volt-
second balance to derive voltage conversion ratio Ch3-18

9
Analysis Steps
for SC in SS
(CCM Example)

DTs D’Ts

KVL & KCL

Ch3-19

Small Ripple Approximation

v(t) consists of desired dc component V, plus small undesired ac component

vripple(t) arising from incomplete filtering of switching harmonics by LP filter
Ch3-20

10
Small Ripple Approximation

Why want to ignore the

ripple as doing circuit
analysis at steady state?

e.g.: In computer power supply, Vo = 3.3 V, the vripple(t) <

a few tens of mV (< 1% of Vo)
Ch3-21

Derivation of Inductor volt-second Balance

iL (Ts )

(v-s or flux-linkage)  iL (0)  iL (Ts )

Ch3-22

11
Derivation of Inductor volt-second Balance

Fluxlinkage 
d d di
v N  L  d  vdt  Nd  Ldi
dt dt dt

Inductor v-s balance allow

us to derive the average of
output voltage

Ch3-23

Derivation of Capacitor amp-second (Charge) Balance

iC (t )  dt  C  dvC (t )  Q
Amp-second balance

 vC (0)  vC (Ts )

Ch3-24

12
Buck Analysis for Switch Closed
Q on (ton  DT ), D off
voltage across inductor
diL
vL  Vs  Vo  L
dt
diL V V
(slope)  s o  0 (Vs  Vo )
dt L
iL derivative (slope) is positive
 iL linearly increase
diL iL i V V
  L s o
dt t ( ton ) DT L
 V V 
(iL )closed   s o  DT

   L  length of subinterval
change in iL during Q on  
slope Ch3-25

Buck Analysis for Switch Opened

Q off (toff  (1  D)T ), D on
voltage across inductor
di
vL  Vo  L L
dt
diL V
(slope)  o  0 (Vo  0)
dt L
iL derivative (slope) is negative
 iL linearly decrease
diL iL iL V
   o
dt t( toff ) (1  D)T L
 V 
(iL )open   o    1  D T
  L   
change in iL during Q off  length of subinterval
slope Ch3-26

13
 Relationship between Vo & Vs
iL at end of T is same as that at beginning in SS
 iLnet change over one T is zero
(iL )closed  (iL )open  0
 Vs  Vo   Vo 
 L  DT    L  (1  D)T  0
   
Vo  Vs  D, Vo  f  Vs , D
 Alternative derviative:
volt-second balance  avg[vL ]  0
VL  (Vs  Vo )DT  (Vo )(1  D)T  0
 Vo  Vs  D
Vo
Mbuck,CCM (D)  D
Vs
 0  D  1  Vo  Vs Ch3-27

Inductor Current in CCM

The avg[iL] must be equal to the
avg[iR], since the avg[iC] must be
zero in SS operation (A-s balance)
iL
 avg[iL ]  avg[iR ] (  avg[iC ]  0) Imax
V IL=IR iL
I L  IR  o Imin
R
t
 max. & min. iL 0 DT T

iL Vo 1  Vo   1 (1  D) 
Imax  IL     (1  D)T   Vo   
2 R 2 L   R 2Lf 
iL Vo 1  Vo   1 (1  D) 
Imin  IL     (1  D)T   Vo   
2 R 2 L   R 2Lf 
Ch3-28

14
 Lmin Required for CCM
 For the preceding analysis to be iL
valid, the CCM in iL must be Imax
CCM
verified IL=IR iL
Imin
 An easy CCM check is to inspect t
0
whether the min. iL is positive or DT T
iL
not (IL > iL  CCM) BCM
Imax
 1 (1  D)  IL=IR iL
Imin  Vo    Imin t
 R 2Lf 
DT T
 Boundary between CCM & DCM: Imin  0
 1 (1  D)  (1  D)R
Imin  0  Vo     (Lf )min 
 R 2Lf  2
(1  D)R
If f is selected, the min. L required for CCM is Lmin 
2f Ch3-29

L Design for CCM Buck

iL
 The peak-to-peak variation Imax
(or called current ripple iL) IL=IR iL
in the iL is often used as a Imin Vs  Vo Vo
L L
design criterion 0 t
DT T
 Typical iL values lie in a range of 10% to 20% full load value
of IL (iL = (10%~20%) IL,FL)
 The L value required for a specified iL under CCM operation
can be obtained by
iL   iL slope  (subinterval time)
 V V   V V  V (1  D)
  s o  DT   s o  D  o
 L   Lf  Lf
 V V  V (1  D)
 L  s o D o
 iL f  iL f
Ch3-30

15
Energy Conservation is Q
D

Components are ideal iL

Power supplied = Power absorbed t

iQ (is)
Ps  Po  Vs Is  Vo Io
voltage conversion ratio M iD
t

Vo Is
Mbuck (D)   D t
Vs Io i
iL Qon (DT )
is (iQ )   1  D  D'
0 Qoff (D' T)
Equivalent to a dc transformer 1
 avg[is ]  Is  IL (DT )  0(D'T )  DIL
T
0 Qon (DT)
iD  
iL Qoff (D'T )
1
 avg[iD ]  ID  0(DT)  IL (D' T )  D' IL
T
Ch3-31

Output Voltage Ripple

 In practice, the Vo cannot keep perfectly constant with
a finite C
 The variation (or ripple) in Vo, can be computed from
the v-i relationship of the capacitor

In practice, C is finite  Vo has variation

iC  iL  iR
iC  0  C charging
Q
Q  CVo  Q  CVo
D
Q
Vo 
C
Ch3-32

16
 Output Voltage Ripple
charge change Q  triangle area
1  T   i  TiL
Q    L    C  Vo  Q  It  CVo
2  2  2  8
T
 Vo   i
8C L
T Vo V (1  D)
 (1  D)T  o
8C L 8LCf 2
Vo (1  D)
Voltage ripple % 
Vo 8LCf 2
(1  D) 1 t
C 0 C
C  vC  i (  )d 
8L Vo /Vo  f 2
 Vo is peak-to-peak ripple voltage
Ch3-33

Waveform of Filter Capacitor

iL
Completely filter iL ripple

L
t
IL=IR i (t )  I  iˆ (t ), i (t )  I  i
C C C L L ripple (t )(  2iL )
t

iL=IL+iripple iC iR IL iR (t )  I R  iˆR (t )  I R , v(t )  V

v( t ) V
C R iC (t )  IC  iˆC (t )  iL (t )   I L  iripple (t ) 
iripple R R
V V
iC
IC  I L   0 ( I L  )  iˆC (t )  iripple (t )
R R
t

Ch3-34

17
Capacitor Resistance  Effect on Voltage Ripple
 In practice, a real capacitor can be modeled as a C with an
equivalent series resistance (ESR) and an equivalent series
inductance (ESL)
 The ripple due to ESR can be much larger than that due to the
pure C
 The ESL is significant when frequency above 300 kHz
 Output filter C choose: not only C value but also ESR
 ESR is inversely proportional to the C value a larger C results
in a lower ESR  Voltage variation across ERS
Vo,C rC,ESR Vo , ESR  iC rC  iL rC
iC C Vo,ESR ESL  Total output voltage ripple
Vo (1  D )
Vo  Vo,C  Vo, ESR , Vo ,C 
8 LCf 2
Ch3-35

電解(Electrolytic)電容規格
Vo,C rC,ESR

iC C Vo,ESR ESL

Ch3-36

18
Output Voltage Ripple Reduction
L
iL iC iR
CT
R
resr

 C provides significant filtering of iL ripple, and chosen

CT is large enough, then its impedance at fs is much
smaller than load R
 XC = 1/2fsCT, if CT is large enough  XC << R  most of
iripple will flow through CT to ground
 In practice, capacitor equivalent series resistance (resr)
further increases vo
Ch3-37

Output Voltage Ripple Reduction

iC iC iC iR CT  C  C  C
C C C
R resr
resr resr resr resr ,T 
3
Solution
 Select high quality capacitor with lower esr
 Employ larger C values than the design value to
compensate the vo induced by the esr
 Using several capacitors with lower C values in
parallel to reduce ers
 All events may at the price of cost increase
Ch3-38

19
 CCM Buck理論波形
vPWM
f = 40kHz，D=0.5
12V
0 t
-12V
vL
Vs-Vo
iL
0 Q
-Vo
D
vDS
20V iDS
0
iD
0
vD
-20V
Vo
10V
iC
0
Ch3-39

Ex. 3-1: Buck Converter

Specifications: Vs = 50V, D = 0.4, L = 400H, C = 100F, f = 20kHz,
R = 20. Assuming ideal components, calculate (a) the output
voltage Vo, (b) the maximum and minimum inductor current, and
(c) the output voltage ripple, (d) if rC,ESR = 0.1, find Vo,ESR.
Assume that buck operates in CCM
[Sol]
(a) Vo  DVs  (0.4)(50)  20V
 1 (1  D)  1 (1  0.4) 
(b) Imax  Vo     20     1.75A
 R 2 Lf   20 2(400μ)(20k) 
 1 (1  D)  1 (1  0.4) 
Imin  Vo     20     0.25A  0  Verify CCM
 R 2Lf   20 2(400μ)(20k) 
Vo (1  D) (1  0.4)
(c)    0.469%
Vo 8LCf 2 8(400μ)(100μ)(20k)2
(Vs  Vo ) (50  20) 1
(d) iL  DT  (0.4)( )  1.5A
L 400μ 20k
V 0.15
 Vo, ESR  (1.5)(0.1)  0.15V  o,ESR   0.75%
Vo 20 Ch3-40

20
Synchronous Buck Converter (SBC)
 Buck converter uses a second MOSFET (S2) in place of the
diode S2 called synchronous rectifier (SR)
 The S2 has a much lower VFD than that of a diode, leading
to higher efficiency in low-voltage, high-current
applications
 A flywheel diode parallels with S2 to carry iL during the
dead time when both MOSFETs are off
 The SBC should be operated in CCM because the S2 allows
bidirectional current

SBC Ch3-41

Synchronous Buck Converter (SBC)

Conduction loss
• use diode: V FD  I avg
2
• use SR: I rm s R D S (on )

A Shottky diode would have a VFD of 0.3 to 0.4 V, whereas a MOSFET

may have an extremely low VFD due to a single-digits m-grade RDS(on)
Ch3-42

21
Voltage Regulator Module (VRM)

VRM (parts external to the processor's fully integrated voltage regulator) on a

computer motherboard, covered with heat sinks. (Wikipedia)
Low V high I
application

Ch3-43

Design Considerations
 CCM, BCM, or DCM
 Switching-frequency selection (20kHz ~ 100kHz ~
MHz) related to
 Storage component (L, Transformer, C) size
 Switching losses heat  cooling device  cost
+ size
 Output voltage ripple limit (C). Low V high I SR
 Magnetic components (L, Tr) design
 Components spec./voltage stress/peak current
 Temperature rise subdue
Ch3-44

22
 Ex. 3-2: Buck Converter Design
Specifications: Vo = 18V, R = 10, voltage ripple < 0.5%, Vs = 48V,
CCM. Specify the duty ratio, sizes of L and C, peak voltage rating
of each device, rms current in L and C. Assume ideal components.
[Sol] Assume in CCM operation
Vo
D  18 / 48  0.375
Vs
(1  D)R (1  0.375)10
Let f  40 kHz,  Lmin    78H
2f 2  40  103
Select L  1.25Lmin  1.25  (78H)  97.5H
Vo 18
IL    1.8A
R 10
 V V   48  18  1
iL   s o  DT   6 
(0.375)   2.88A
 L   97.5  10  40k
i i
Imax  IL  L  3.24A, Imin  IL  L  0.36A > 0  Verify CCM
2 2
Ch3-45

Ex. 3-2: Buck Converter Design (續)

rms value of iL (triangle wave)
[Sol]
2 2
 i /2   1.44 
IL,rms  I   L   (1.8)2  
2
L   1.98A
 3   3 
Capacitor selection
1 D 1  0.375
C   100F
 Vo  2 8(97.5  106 )(0.005)(40k)2
8L  f
 Vo 
iC , peak  iL /2  1.44A
iC ,rms  1.44/ 3  0.83A (triangle waveform)
Devices rating:
Vsw,max  48V  VD,max , Isw,max  3.24A  ID,max
Vs  Vo  48  18  30V , Q on
vL  
 Vo  18V , Q off
vC  18V Ch3-46

23
 Buck in DCM Operation

Imin = 0

 DCM: iL will fall to zero (stay at 0 in a duration)

over the switching period
 Imin =0

Ch3-47

Analysis of DCM Buck

 v-s balance avg[vL ]  0
(Vs  Vo )DT  ( Vo )D1T  0
Vo D

Vs D  D1
Vo
IL  IR 
R
 average value of iL (triangle wave)
11 1 
IL   Imax DT  Imax D1T 
T2 2 
1 V
 Imax ( D  D1 )  o (avg[iC ]  0)
2 R

Ch3-48

24
 Analysis of DCM Buck
 sw closed
iL  Imax , vL  Vs  Vo , Vs  Vo   D  D1  / D
di Vs  Vo iL Imax
  
dt L t DT
 V V  V DT
Imax  iL   s o  DT  o 1
L 
  L
  slope
 slope

1 1 Vo D1T V
 IL  Imax ( D  D1 )  ( D  D1 )  o
iL  IL 2 
  2 L R
( Area of iL )/ T

8L
 D  D2 
2L RT
iL  iL  iR D12  DD1   0  D1 
RT 2
V
iL  IL  iC  iR  0 o
R Ch3-49

Analysis of DCM Buck

8L
 D  D2 
 Substituting D1  RT
2
 D  2D
Vo  Vs   Vs
 D  D1  D  D 2  8L
RT
Vo 2D
 Mbuck , DCM ( D, R)  
Vs 8L
D  D2 
RT
2

1 8L
1 1 2
D RT
 Boundary between CCM & DCM
1. Imin  0
2. D1  1  D
Ch3-50

25
 Vo vs. D of Buck
CCM
D1 < 1 - D D1 > 1 - D

D1 = 1 - D

Voltage Conversion Ratio of Buck

D CCM (linear)
V   2
Mbuck  o  DCM (nonlinear)
Vs  1 8L
1 1 2
 D RT
Ch3-51

Ex. 3-3: DCM Buck Converter

Specifications: Vs=24V, L=200H, R=20, C=1000F, f=10kHz,
D=0.4. (a) Show iL is discontinuous. (b) Determine Vo.
[Sol]
19.2V

13.9V

(a) For DCM D1  1  D

D = 0.4, D1 = 0.29
8L
D  D  2
D = 0.8, D1 = 0.2
D1  RT  0.29
2
D1  0.29  (1  D)  1  0.4  0.6  DCM
 D 
(b) Vo  Vs    13.9V
 1  D1  Ch3-52

26
 Boost (Step-Up)
Converter

Ch3-53

Boost Converter in CCM

 Vo  Vs
 Steady-state operation exist
 Analysis assumptions are the same as Buck
Ch3-54

27
Analysis for Switch Closed
0  t  DT , Q on, D off
voltage across inductor
diL di V
vL  Vs  L  L  s 0
dt dt L
current slope is positive
 iL linearly increase
diL iL iL Vs
  
dt t DT L
V 
(iL )closed   s   DT
 L
Ch3-55

Analysis for Switch Open

DT  t  T , Q off, D on
voltage across inductor
di
vL  Vs  Vo  L L
dt
diL Vs  Vo
  0 (Vs  Vo )
dt L
current slope is negative
 iL linearly decrease
diL iL iL V  Vo
   s
dt t (1  D)T L
 V  Vo 
(iL )open   s   (1  D)T
 L  Ch3-56

28
 Steady-State Operation
iLnet change over one T is zero
(iL )closed  (iL )open  0
 Vs   Vs  Vo 
 L  DT   L  (1  D)T  0
   
V
 Vo  s
1 D
 v-s balance  avg[vL ]  0
1
avg[vL ]  0 
V DT  (Vs  Vo )(1  D)T 
T s
V V 1
CCM  Vo  s , Mboost ,CCM  o 
1 D Vs 1  D
0  D  1  Vo  Vs for boost
Ch3-57

Steady-State Operation
CCM

Vs V 1
Vo  , Mboost ,CCM (D)  o 
1 D Vs 1  D

 At D = 0, Vo = Vs
 Vo nonlinearly increases as D increases
 In the ideal case Vo tends to  as D  1
Ch3-58

29
 Steady-State Operation
 average inductor current IL is
2
V
Ps  Vs Is  Vs IL  Po  Vo Io  o
(ideal)
R
2
 Vs 
Vo  1  D 
2
Vs2 Vs Vo
Vs IL     IL  
R R (1  D) R
2
(1  D) R (1  D)R
2

 max. & min. iL i L

i Vs 1 Vs
Imax  IL  L   DT Imax
2 (1  D)2 R 2 L IL
Imin Vs V  V
iL
s o

i
L
Vs 1 Vs L
t
Imin  IL  L   DT 0 DT T
2 (1  D) R 2 L
2
Ch3-59

Steady-State Operation is

 CCM & DCM boundary

Vs V DT
Imin  0   s
(1  D) R
2
2L
Vs V DT Vs D
  s 
(1  D) R
2
2L 2Lf
 min. L for CCM  L design for CCM
iL ( DTs )  iL (0)  iL ( DTs )  iL (Ts )  iL
D(1  D)2 R
( Lf )min  V  Vs D
2 (iL )closed   s   
DT  L 
L  on time (iL )closed f
D(1  D)2 R
 Lmin   slope
2f Set iL  (10% ~ 20%) of I full load
Choose L such that desired ripple
magnitude is obtained
Ch3-60

30
Output Voltage Ripple is

In practice, C is finite  Vo has variation

Change in C charge Q  rectangle area
V 
Q  It   o  DT  CVo
 R
V DT Vo D V D
Vo  o   o (%)
RC RCf Vo RCf
D
C
 V 
R o  f
 Vo 
Vo, ESR  iC rC , ESR  I L,max rC ,ESR

Ch3-61

CCM Boost理論波形

Ch3-62

31
 Ex. 3-4: CCM Boost Converter Design
Design a boost converter that will have an output of 30 V from a 12-V source.
Design for continuous inductor current and an output ripple voltage of less than
one percent. The load resistance is 50 . Assume ideal components for this
design. Specification:
Assume in CCM operation
Vo
Vs Vo  30V , Vs  12V , R  50,  1%, CCM
[Sol] D  1  1  (12 / 30)  0.6 Vo
Vo
D(1  D)2 R 0.6  (1  0.6)2  50
Let f  25 kHz,  Lmin    96H
2f 2  25  103
Select L  1.25Lmin  1.25  (96H)  120H
Vs 12
IL    1.5A
(1  D)2 R (1  0.6)2 50
V   30  1
iL   s  DT   6 
(0.6)   2.4A
 L  120  10  25 k
i i
Imax  I L  L  2.7A, Imin  I L  L  0.3A > 0  Verify CCM
2 2
D 0.6
C   48μF
R  Vo / Vo  f 50  (1%)  25k Ch3-63

Copper Loss from Inductor Resistance

 The ESR of the inductor (rL) has little
effect on buck
 However, rL affects the performance of
boost especially at high duty ratios
vL
 Only consider rL, neglecting other
iL L rL
losses
Vs V
Vo  , Is  IL , ID  IR  o
1 D R
Ps  Po  PrL  Vs IL  Vo ID  IL2rL (1)
0, Qon, D off V
iD    ID   D  0  D' IL   D' IL  o (2)
iL , Qoff , D on R
From (1) Vs IL  Vo (D' IL )  IL2rL  Vs  Vo D' ILrL (3)
Ch3-64

32
 Copper Loss from Inductor Resistance
Vo
From (2) IL  Substituting into (3)
D' R
Vo M(D)
 Vs  Vo (1  D)  rL
(1  D) R
ideal
V 1 1
 o
Vs D '  rL 
 1  R( D ')2 
 
A correction factor to account for the rL

 RL = 0, M(D) =1/D’, ideal boost M

 As rL increased in relation to R, the
second term is increased, and M is
reduced as well
 rL limits max. voltage that the
converter can produce Ch3-65

Copper Loss from Inductor Resistance

 In practice, component non-idealities lead to large power

losses, efficiency decreases rapidly at high duty cycle
 At D = 1, switch is always on, no energy is transferred to
output, i.e. Vo  0
 iL tends to a large valued, limited only by rL
Ch3-66

33
 Copper Loss from Inductor Resistance

 A large amount of power is lost in

rL (Vs2 / rL ) , while no power is
delivered to load, Po = 0, efficiency
Efficiency
=0
P V2 / R
 Need more boosting ratio  need   o
 o

Po  Pr  Vo2 / R  I L2 rL
operation in larger D  leading to L

larger inductor current  more V

代入IL  o   
1
power losses  lower efficiency D' R
1
rL
R(1  D)2
Ch3-67

Boost in DCM Operation

iD  iC  iR
 avg[iD ]  avg[iC ]  avg[iR ]
Vo
I D  0  IR 
R

I/P & O/P voltage relationship is determined from

1. Avg [vL] = 0  v-s balance
2. Avg [iD] = IR  avg [iC] = 0 (A-s balance)
Ch3-68

34
Analysis of DCM Boost

 avg[vL ]  0 (v-s balance)

1
V DT  (Vs  Vo )D1T   0
T s
 D  D1 
Vo  Vs   ()
 D1 
11  1
 avg[iD ]  ID  IR   Imax D1T   Imax D1
T2 2
  
triangle area

V DT 1  V DT  V
Imax  iL  s  ID   s  D1  I R  o
L 2 L  R
 V   2L 
 D1   o   
 Vs   RDT 
Ch3-69

Analysis of DCM Boost

 D  D1   V   2L 
Vo  Vs   (), D1   o   
 D1   Vs   RDT 
Substituting D1 to ()
Vo 1  
2
 Vo   Vo   D2 RT  2D2 RT

        0    1  1  
 Vs   Vs   2L  Vs 2  L 

D2 RT V 1 RT
If  1  o   KD ( linear), K 
L Vs 2 2L
Vo 1  2D2 RT  1
Mboost , DCM  1 1    KD
Vs 2  L  2

 Boundary between CCM & DCM
 D1  1- D
 Imin  0
Ch3-70

35
 Vo vs. D of Boost
D1 > 1 - D

CCM
D1 = 1 - D
D1 < 1 - D

Voltage Conversion Ratio of Boost

 1
 CCM (nonlinear)
Vo  1  D
Mboost  
Vs  1  2D2 RT  1
1 1    KD DCM (  linear)
2  L  2
 
K  RT / 2L Ch3-71

Ex. 3-5: DCM Boost Converter

Specifications: Vs = 20V, D = 0.6, L = 100H, C = 100F, f = 15kHz, R = 50.
Assuming ideal components, (a) Verify that the inductor current is discontinuous,
(b) determine the output voltage, and (c) determine the maximum inductor
current.
Assume in CCM operation
[Sol] (a) Compute Imin
Vs 1 Vs 20 1 20 1
Imin   DT    0.6   1.5A
(1  D)2 R 2 L (1  0.6)2 (50) 2 100 15k
Imin  0, verifing in DCM
 1 
2(0.6)2  50 
1 2D2 RT  1 15k

(b) Vo,DCM   1  1  V  1 1  (20)  60V
2  L  s 2  100 
 
 
V 20
Vo,CCM  s   50V
1  D 1  0.6
V D 20 0.6
(c) Imax  s   8A
L f 100 15k
Ch3-72

36
 Buck-Boost Converter

Ch3-73

Buck-Boost Converter in CCM

 Vo > or < Vs
 Output voltage polarity reverse with input
source
 Steady-state operation exist
 Analysis assumptions are the same as Buck
Ch3-74

37
Analysis for Switch Closed
0  t  DT , Q on, D off
voltage across inductor
diL di V
vL  Vs  L  L  s 0
dt dt L
current slope is positive
 iL linearly increase
diL iL iL Vs
  
dt t DT L
V 
( iL )closed   s   DT
 L
Ch3-75

Analysis for Switch Open

DT  t  T , Q off, D on
voltage across inductor
di
vL  Vo  L L
dt
diL Vo
  0 ( polarity reverse)
dt L
current slope is negative
 iL linearly decrease
diL iL iL V
   o
dt t (1  D)T L
V 
(iL )open   o   (1  D)T
 L Ch3-76

38
 Steady-State Operation
iLnet change over one T is zero
(iL )closed  (iL )open  0
 Vs   Vo 
 L  DT   L  (1  D)T  0
   
 D 
 Vo  Vs  
 1 D 
 v-s balance  avg[vL ]  0
1
VL  V DT  Vo (1  D)T   0
T s
 D  V D
 Vo  Vs   , Mbb,CCM  o  
 1 D  Vs 1 D
Vo
CCM D
Vo  Vs
Ch3-77

Steady-State Operation

CCM

Vo D
D > 0.5  Vo > Vs Mbb,CCM  
Vs 1 D
D < 0.5  Vo < Vs
Sw closed : energy stored in L Indirect
Sw open : energy transferred to load Convert

Output voltage polarity reverse with input source

Ch3-78

39
 SS Operation
 Po  Ps (ideal case)
Vo2
Po   Ps  Vs I s , and I s  DI L
R
Vo2 Vo2
 Vs DI L  I L 
R Vs RD
D  Boundary of CCM & DCM :
代入Vo  Vs
1 D Imin  0
2
 D  Vs D V DT
 Vs    s 0
1 D  Vs D R(1  D) 2
2L
 IL   
Vs RD R(1  D)2 (1  D)2 R
 ( Lf )min 
 max & min inductor current 2
i Vs D V DT  minimum L for CCM:
Imax  I L  L   s
2 R(1  D)2 2L (1  D)2 R
Lmin 
iL Vs D V DT 2f
Imin  I L    s
2 R(1  D) 2
2L Ch3-79

Output Voltage Ripple

In practice, C is finite  Vo has variation

Change in C charge Q  rectangle area
V 
Q  It   o  DT  CVo
 R
V DT D V D
Vo  o  Vo  o  (%)
RC RCf Vo RCf
D
C
 V   Vo
R o  f
iR   R sw on
 Vo  iC  
Vo,ESR  iC rC ,ESR  IL,max rC ,ESR i  Vo sw off
 L R
Ch3-80

40
 CCM Buck-Boost理論波形

Ch3-81

Ex. 3-6: CCM Buck-Boost Converter

Specifications: Vs = 24V, D = 0.4, L = 20H, C = 80F, f = 100kHz, R = 5.
Assuming ideal components, determine the output voltage, inductor current
average, maximum and minimum values, and the output voltage ripple.
[Sol]
Assume in CCM operation
DVs 0.4  24
Vo     16V
1 D 1  0.4
DVs 0.4  24
IL    5.33A
R(1  D)2 5(1  0.4)2
V   24  1
iL   s  DT   6 
(0.4)   4.8A
 L  20  10  100k
i i
IL,max  IL  L  7.33A, Imin  IL  L  2.93A > 0  Verify CCM
2 2
Vo D 0.4
   0.01  1%
Vo RCf 5  (80)  100k
Ch3-82

41
 C’uk Converter

Ch3-83

C’uk Converter in CCM

 Vo > or < Vs (Vo polarity reverse with Vs)

 L1, L2-C2 input and output filter
 Energy transfer depend on C1
 Steady-state operation exist
 Analysis assumptions are the same as Buck
Ch3-84

42
 Operation Mechanism

 Q off, D on: iL1, iL2 flow through D, energy in Vs & L1

transfer to C1, VC1 > Vs , then iL1 decreases, energy in L2
transfer to load, then iL2 decreases
 Q on, D off: iL1, iL2 flow through Q, VC1 > Vo, energy in
C1 transfer to load & L2, iL2 increases, Vs energizes L1
causing iL1 increases
 In SS, avg[vL1] = 0 = avg[vL2] , then VC1 = Vs - Vo
Ch3-85

Analysis for Switch Closed

L1 L2
diL1 diL2
vL1  Vs  L1 vL2  VC1  Vo  Vs  L2
dt dt
diL1 Vs diL2 Vs
  0, iL1 increase   0, iL2 increase
dt L1 dt L2
iL1 iL1 Vs iL2 iL2 Vs
   
t DT L1 t DT L2
Vs Vs
(iL1 )closed  DT (iL2 )closed  DT
L1 L2

Ch3-86

43
Analysis for Switch Open
L1 L2
diL1 diL2
vL1  Vs  VC1  L1 vL2  Vo  L2
dt dt
diL1 Vs  VC1 diL2 Vo
  0, iL1 decrease   0, iL2 decrease
dt L1 dt L2
iL1 iL1 V V iL2 iL2 V
  s C1   o
t (1  D)T L1 t (1  D)T L2
Vs  VC1 Vo
(iL1 )open  (1  D)T (iL2 )open  (1  D)T
L1 L2
Vo Vo
 (1  D)T  (1  D)T
L1 L2
In SS, VC1 = Vs - Vo Ch3-87

Steady-State Operation
L1 L2
(iL1 )closed  (iL1 )open  0 (iL2 )closed  (iL2 )open
 Vs   Vo   Vs   Vo 
  DT    (1  D)T  0   DT    (1  D)T  0
 L1   L1   L2   L2 
D D
Vo   Vs Vo   Vs
1 D 1 D
 v-s balance avg[vL ]  0
Vs D  (Vo )(1  D)  0 (Vs )D  Vo (1  D)  0
D D
 Vo   V  Vo   V
1 D s 1 D s
Vo
D
Vo  Vs
• In SS, VC1 = Vs - Vo
• “” indicates a polarity reversal between output and input
Ch3-88

44
 Steady-State Operation
VC1  Vs  Vo ( avg[vL1,2 ]  0)
(iC1 )closed   IL2
(iC1 )open  IL1
Ps  Po  Vs IL1  Vo IL2
Vo IL1
 
Vs I L2
A-s balance avg[iC ]  0
[(iC1 )closed ]DT  [(iC1 )open ](1  D)T  0
 IL2 D  IL1 (1  D)  0
IL1 D V
   o
IL2 1  D Vs
Ch3-89

Ripple in C1
VC1  Vs  Vo ( avg[vL1,2 ]  0)
Vo IL1 D D V
  , IL1   IL2 , IL2  o ( avg[iC 2 ]  0)
Vs IL2 1 D 1 D R
Q Open: iC1  iL1  IL1 (assume constant)
1 T I D 1
vC1 
C1 DT
IL1dt  L1 (1  D)T  
C1
IL2 (1  D)T
1  D C1
DT DT  Vo  D  Vo  Vs  D2 
 IL2        
C1 C1  R  RC1 f RC1 f  1 D 
D
 vC1 
RC1 f
 Vo 
Ch3-90

45
Max. & Min. Inductor Current
 min. inductor current
V D D Vo
IL2  o , IL1   I L2  
R 1 D 1 D R
i V DT
IL1,min  IL1  L1  IL1  s
2 2L1
iL2 V DT
IL2,min  IL2   I L2  s
2 2L2
 Boundary of CCM & DCM : Imin  0
 min. L for CCM
(1  D)2 R (1  D)R
L1,min  , L2,min 
2Df 2f
Ch3-91

Output Voltage Ripple

Q
Q  C2Vo  Vo 
C2
1  T   i  T iL2
Q    L2  
2  2  2  8 The same as the LPF of Buck
T
Vo   iL2
8C2
T Vo V (1  D)
 (1  D)T  o
8C2 L2 8L2C2 f 2
Vo (1  D)

Vo 8L2C2 f 2
Q: triangle area
Ch3-92

46
C’uk Key Waveforms

Ch3-93

Ex. 3-7: CCM C’uk Design

Specifications: Vs = 12V, Vs = -18V, Po = 40W. Assuming ideal components, select
the duty ratio, the switching frequency, the inductor sizes such that the change
in inductor currents is no more than 10 % of the average inductor current, the
output ripple voltage is no more than 1 %, and the ripple voltage across C1 is no
more than 5 %.
[Sol]
Assume in ideal and CCM operation. Let f  50 kHz
Vo 18 D
   D  0.6
Vs 12 1  D
Vo P 40 D 0.6
I L2  I R   o   2.22A, IL1  I   2.22  3.33A
R Vo 18 1  D L2 1  0.6
V  VD
iL1,2   s  DT  L1,2  s
L  iL1,2 f
 1,2 
12  0.6 VD 12  0.6
 L1   432H, L2  s   649H
(10% 3.33)  50k iL2 f (10%  2.22)  50k
Ch3-94

47
 Ex. 3-7: CCM C’uk Design (續)
Specifications: Vs = 12V, Vs = -18V, Po = 40W. Assuming ideal components, select
the duty ratio, the switching frequency, the inductor sizes such that the change
in inductor currents is no more than 10 % of the average inductor current, the
output ripple voltage is no more than 1 %, and the ripple voltage across C1 is no
more than 5 %.
[Sol] Assume in ideal and CCM operation. Let f  50 kHz
D  0.6, IL2  2.22A, IL1  3.33A, L1  432H, L2  649H
iL1 0.222 i 0.333
IL1,min  IL1   2.22   2.1A, IL2,min  IL2  L2  3.33   3.1A
2 2 2 2
Both  0  verify CCM
1 D 1  0.6
C2    3.08μF
8L2  Vo / Vo  f 2 8  649 (1%)  (50k)2
VC1  Vs  Vo  12  (18)  30V  vC1  30V  0.05  1.5V
V 18
R   8.1
I L2 2.22
Vo D 18  0.6
 C1    17.8μF
Rf  vC1  (8.1)  50k  1.5
Ch3-95

Summary of CCM Operation

型式 Buck Boost Buck-Boost C’uk

Vo 1 D D
D 1 D 1 D 1 D
Vs
Vo 1 D D D 1 D
Vs 8 LCf 2 RCf RCf 8 L2C2 f 2
(1  D)2 R
(1  D) R D(1  D)2 R (1  D)2 R L:1
2 Df
L min

2f 2f 2f (1  D) R
L2 2 f
:

Vs D2 1 V 
 1 1  D 
L : R(1  D)
1 2
  s  DT
2  L1 
I Vs V DT Vs D V DT
max Vo     s  s 1 V 
R 2 Lf  (1  D)2 R 2L R(1  D)2 2L L :
Vs D
  s  DT
2
R(1  D) 2  L2 

Vs D2 1 V 
 1 (1  D)  Vs V DT Vs D V DT L : R(1  D) 2
  s  DT
2  L1 
Vo    s
1
 s
I R 2 Lf  (1  D)2 R 2L R(1  D)2 2L 1 V 
min
Vs D
L 2
:   s  DT
R(1  D) 2  L2 

Ch3-96

48
 Single-End Primary
Inductance Converter
(SEPIC)

An SEPIC circuit using mutually

coupled inductors Ch3-97

SEPIC Converter in CCM

 Properties like the C’uk converter, Vo > or < Vs ,

but with no polarity reversal
 Energy transfer depend on C1
 Steady-state operation exist, v-s and charge
balances are used to derive M  Vo/Vs
 Analysis assumptions are the same as Buck Ch3-98

49
SEPIC Operation Mechanism
From KVL :
Vs  vL1  vC1  vL2  0
Average voltage:
Vs  0  VC1  0  0  VC1  Vs

 Q on, D off: iL1, iL2 flow through Q, Vs energizes L1, C1

discharges to energize L2, iL1, iL2 increase, load is
supplied by C2, vC1, vC2 decrease
 Q off, D on: iL1, iL2 flow through D, energy in Vs, L1 & L2
charges C1 and transfers to load and charges C2, then iL1,
iL2 decrease, vC1, vC2 increase
 In SS, avg[vL1] = 0 = avg[vL2], then VC1 = Vs
Ch3-99

Analysis for Switch

Closed

L1 L2
diL1 diL2
vL1  Vs  L1 vL2  VC1  Vs  L2
dt dt
diL1 Vs diL2 Vs
  0, iL1 increase   0, iL2 increase
dt L1 dt L2
iL1 iL1 Vs iL2 iL2 Vs
   
t DT L1 t DT L2
Vs Vs
(iL1 )closed  DT (iL2 )closed  DT
L1 L2
In SS, VC1 = Vs Ch3-100

50
Analysis for Switch
Open

L1 L2
diL1 diL2
vL1  Vs  VC1  Vo  Vo  L1 vL2  Vo  L2
dt dt
diL1 Vo diL2 Vo
  0, iL1 decrease   0, iL2 decrease
dt L1 dt L2
iL1 iL1 V iL2 iL2 V
  o   o
t (1  D)T L1 t (1  D)T L2
Vo Vo
(iL1 )open  (1  D)T (iL2 )open  (1  D)T
L1 L2
In SS, VC1 = Vs Ch3-101

Steady-State Operation
L1 L2
(iL1 )closed  (iL1 )open  0 (iL2 )closed  (iL2 )open
 Vs   Vo   Vs   Vo 
  DT    (1  D)T  0   DT    (1  D)T  0
 L1   L1   L2   L2 
D D
Vo  Vs Vo  Vs
1 D 1 D
 v-s balance avg[vL ]  0
Vs D  (Vo )(1  D)  0 (Vs )D  (Vo )(1  D)  0
D D
 Vo  V  Vo  V
1 D s 1 D s
Vo
D
Vs  Vo
Ch3-102

51
 A B
Steady-State Operation
VC1  Vs ( avg[vL1,2 ]  0)
(iC1 )Q on  iL2 , (iC1 )Q off  iL1
(iC 2 )Q on   Io , (iC 2 )Q off  iL1  iL2  Io
Node A iL2  iD  iC1  IL2  ID V
From KCL   IL2  Io  o , Is  IL1
 Node B i D  iC2  Io  I D  Io R
2
V V D Vo
Ps  Po (no loss)  Vs IL1  Vo Io  IL1  o Io  o 
Vs Vs R 1  D R
IL1 Vo D
    M( D)
IL2 Vs 1  D
current and voltaage stress of Q and D
iL1  iL2 Q on 0 Q on
iQ   iD  
0 Q off iL1  iL2 Q off
0 Q on   Vs  Vo  D off

vQ   vD  
Vs  Vo Q off 0 D on Ch3-103

Max. & Min. Inductor Current

Vo D
I L 2  Io , IL1  I
R 1  D L2
 min. and max. inductor current
 iL1  Vs D iL2 Vs D
 IL1,max  IL1  2  IL1  2L f
 IL2,max  IL2  2  IL2  2L f
  1 2
 
I iL1 I VD iL2 VD
L1,min  I L1   IL1  s
L2,min  I L2   I L2  s
 2  2L1 f 2 2L2 f
 Boundary of CCM & DCM : Imin  0
 min. L for CCM
(1  D)2 R (1  D)R
L1,min  , L2,min 
2Df 2f
Ch3-104

52
Output Voltage Ripple
Vo
Q  It   DT  CVo
R
Vo D V D is
Vo  VC 2   o (%)
RC2 f Vo RC2 f
D
C2 
R  Vo / Vo  f The same as the LPF of Boost
voltage variation in C1
Vo
iC1  iL2 , I L2  Io 
R
QC1 Io (t ) Vo DT
VC1   
C1 C1 R C1
VC1 D
  (%)
Vo RC1 f
D
C1 
R  VC1 / Vo  f
Ch3-105

SEPIC Key Waveforms

D
M( D) 
1 D

Step-down
Step-up

Ch3-106

53
 Ex. 3-8: CCM SEPIC
Specifications: Vs = 9V, D = 0.4, L1 = L2 = 90H, C1 = C2 = 90 = 80F, f = 100kHz,
Io = 2A. Assuming ideal components, determine the output voltage; the average,
maximum, and minimum inductor currents; and the variation in voltage across
each capacitor.
Assume in ideal and CCM operation
[Sol] D 0.4
Vo  Vs  (9)  6V
1 D 1  0.4
D 0.4 D 0.6
IL2  Io  2A, IL1  I  (2)  1.33A, IL1  I   2.22  3.33A
1  D L2 1  0.4 1  D L2 1  0.6
V  9  0.4
iL1,2   s  DT   0.4A  L1  L2 
L  90 100k
 1,2 
 i 0.4  i 0.4
I  I  L1  1.33   1.53A  IL2,max  IL2  L2  2   2.2A
 L1,max L1 2 2  2 2
 
I iL1 0.4 i 0.4
L1,min  I L1   1.33   1.13A  IL2,min  IL2  L2  2   1.8A
 2 2  2 2
R  Vo / Io  6 / 2  3
Vo D 6  (0.4) VD 6  (0.4)
Vo  VC 2    0.1V, VC1  o   0.1V
RC2 f 3  80  100k RC1 f 3  80 100k
Ch3-107

Interleaved Converter
(交錯式轉換器)

Ch3-108

54
 Interleave Buck Converter

 Interleaving, also called multiphasing, aims to reduce the

size of filter components
 A parallel combination of two sets of switches, diodes, and
inductors connected to a common filter capacitor and load
 Two switches are operated 180 out of phase, such that
inductor currents (iL1, iL2) are also 180 out of phase
Ch3-109

Interleave Buck Converter

 iL1 and iL2 180 out of phase  ripples cancel each other
 io = iL1+ iL2 = iC + Io, io has a smaller ripple with twice the
frequency of the respective iL
 This results in a smaller ripple in iC and requires less
filtering C for the same output ripple voltage
 The variation in source current is also reduced
Ch3-110

55
 Interleave Buck Converter
For CCM, from v-s balance
L1
Vs  Vo DT
vL1  
Vo (1  D)T
(Vs  Vo )D  (Vo )(1  D)  0
 Vo  DVs
L2
Vs  Vo DT
vL2  
Vo (1  D)T
(Vs  Vo )D  (Vo )(1  D)  0
 Vo  DVs
Ch3-111

Interleave Buck Converter

 Each L1,2 supplies one-half of the Io and Po, so

the average avg[iL1,2] is one-half of a single buck
 More than 2 converters can be interleaved. The
phase shift between switch closing is 360/n (n:
the number of converters in parallel)
Ch3-112

56
Non-ideal Effects on Converter Performance
Switch voltage drops
 Significant effect when Vs and Vo is low
 Non-ideal components must be accounted for

Consider Buck switches on voltage drops

sw on : vL  (Vs  Vo )  VQ , VQ  voltage across conducting switch

sw off: vL  (Vo )  VD , VD  voltage across conducting diode
avg[vL ]  VL  0  (Vs  Vo  VQ )D  (Vo  VD )(1  D)  0
 Vo  Vs D  VQD  VD (1  D)  DVs (ideal case)
Ch3-113

Non-ideal Effects on Converter Performance

Capacitor Resistance: effect on ripple
 ESR often produces a ripple greater than that of C
 ESL is significant when frequency above 300 kHz
 Output C choose: not only capacitance but also
ESR
 Voltage variation across C
C C ESL ESR Vo,ESR  iC rC
ideal real  Total output voltage ripple
Vo  Vo,C  Vo,ESR
Vo (1  D)
Vo,C  for Buck
8LCf 2
Ch3-114

57
Non-ideal Effects on Converter Performance
Inductor Resistance: Boost used as an example
(neglect other losses)
Is  IL , ID  IR , Ps  Po  PrL
L
Vs IL  Vo ID  IL2 rL
ideal avg[iD ]  ID  IL (1  D) (1)
ESC L ESR Vs IL  Vo IL (1  D)  IL2 rL  Vs  Vo (1  D)  ILrL (2)
real rL ID V /R
from (1)  IL   o (3)
1 D 1 D
VorL
substituting IL in (2)  Vs   Vo (1  D)
R(1  D)
 
 Vs   1  Correction factor
Vo     
 1 D  1 rL 
 R(1  D)2 
  Ch3-115

Non-ideal Effects on Converter Performance

Inductor Resistance: Boost used as an example

Po V2 / R
power efficiency: η   2 o
Po  Ploss Vo / R  IL2 rL
Vo2 /R 1
using (3) for IL η 
 V /R 
2
rL
Vo2 /R   o  rL 1
 1 D  R(1  D)2
 D increases   decreases Ch3-116

58
Non-ideal Effects on Converter Performance
Switching Losses
 Switch on-off transition losses
 Energy loss = area under the power curve
 Higher switching frequency results in higher switching
loss
 Reduce loss: zero v/i switching

v/i simultaneous transition Worst case transitions Ch3-117

59