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Verilog 18012022

This document contains module definitions for logic gates in Verilog including AND, OR, NOT, NAND, NOR, XOR, and XNOR gates. It also contains test benches and stimulus modules to simulate and test a 2-input AND gate, half adder, and logic gate modules.

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salusivasankaran
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© © All Rights Reserved
Available Formats
Download as PDF, TXT or read online on Scribd
30 views

Verilog 18012022

This document contains module definitions for logic gates in Verilog including AND, OR, NOT, NAND, NOR, XOR, and XNOR gates. It also contains test benches and stimulus modules to simulate and test a 2-input AND gate, half adder, and logic gate modules.

Uploaded by

salusivasankaran
Copyright
© © All Rights Reserved
Available Formats
Download as PDF, TXT or read online on Scribd
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module and1(z,z)

A N D

input ,Y
e Can write tnpuks and okput
Oukpat z)
nside brackots. instead of ne<t
nnes

end module In Jate levele model ung instead of


.

3C19)
and 31 2,a9)P

O R

module Or1(1,2,9)
input ,9
Output z
or (7,z1);
endmodude

NOT

module ota(3,a);
2nput
Outp utY
not(,))
endl module

k, C,9);
madu le nand
N A N D

Tnpub , y
Output Z
hand (z, T9)
Pnd module
N
N O
O R6
Module ho ri( 2,T)

nput T9
Output zZ
no(x,,9);
endmodule
XOR

module zo ,I,1)
input ,Y
Output z
Tor (z, y ) ;
end nodule

XNOR
module Tno7i( ZTI);
nput y
Oukput Zi
noY x(T)
end module

Test heneh for and 9ate.

modul and 9 a,b)j est bond


Output reg abi inodt
AND-
DUT
Out put eg out desian rle
nhial
begin
a0 b 0 our 0
$ dunpfile (and- vd ))
$dwmpvars
a- Ob=o Out =O
#5 after 5 ns.
a-O b=I) out=0
#5

d=lb=0 out 0

Calus v l o 9
a b =) Ot =1.) t k wave

+5
Phnish
end
end module

module and-gt-Stimulus C)3

wiTe ab
(2,y) T k wave
a1
and 9
à tb X9) ;
and g t b

endmodule
HalP adder

S AOB

CzA-B

Verilog Code

module halfadder (S,C, T,9)


nput 9
Output S,C
and (C, c9)
CO (S, 2,9))

end module

Test beneh for half adde

medule halfadder -tb (a,b);


Output Teg ab
Output Teg
innial
begin
a -0b 0)

dumpfile half addey. Vcd")


dumpvars
a -0 b=o ) Z=0
#5
a 0 b =I z =12
5

#5

a b=lz =
5

$finish
end
enlmodule
module halfadder-Stimulus C);
Or GTKk wave
Wire a,b
halP adder ha (S,x4)
half adder tb has (z,y)

endmadule

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