CHAPTER 1

DIGITAL ELECTRONICS

Syllabus: Digital electronics: logic functions, minimization, design and synthesis of combinational and sequential
­circuits, number representation and computer arithmetic (fixed and floating point).

1.1 INTRODUCTION Number system

Digital electronics represents discrete signals instead of Radix/Base representation Codes representation
signals in a continuous range. It uses two binary levels
0’s (corresponding to false) and 1’s (corresponding to
true). The main reason for advancement in digital elec-
Numeric codes Alphanumeric codes
tronics is integrated circuits (ICs).
EBCDIC
Weighted Non-weighted ASCII
1.2 NUMBER SYSTEM
Binary Gray code

Number system is an age old method to represent BCD XS3 code

numerals (Fig. 1.1). Decimal number system is the most 2421 code
common number system and binary number system is
used by computers. Figure 1.1 |   Number system.

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 4     Chapter 1: Digital Electronics 

Table 1.1 |   Types of number systems

Base/Radix Unique ­Numbers Terminology Example
10 0 to 9 Decimal number system 10.47
8 0 to 7 Octal number system 65.32
2 0 to 1 Binary number system 110.11
16 0 to 15 Hexadecimal number system BAD.1A
0 to 9 are numerals and 10
to 15 are represented with
alphabets 10 = A, 11 = B,
12 = C, … 15 = F (111001.0100)2 = 1 × 25 + 1 × 24 + 1 × 23 + 0 × 22
+ 0 × 21 + 1 × 20 + 0 × 2-1
Radix or base is the number of unique digits, so the + 1 × 2-2 + 0 × 2-3 + 0 × 2-4
­different base or radix can be expressed as represented
in Table 1.1. For example, (57)10 − here 10 is the base
= 32 + 16 + 8 + 0 + 0 + 1 + 0
(or radix) and 57 is the number. + 0.25 + 0 + 0 = (57.25)10

Another example is of (101.11)2 = (5.75)10 = (5.6)8 =

Example 1.1 (5.C)16.
Let us understand the logic of representation by consid-
ering (57.1)10. We know 57 means 50 + 7 + (1/10). Now, 1.2.2 Complement of a Number
representing the same by making use of radix (which
is 10), we get Any given number will have two complements:
1. Radix minus one complement (R-1’s
5 × (10)1 + 7 × (10)0 + 1 × (10)-1 ­complement): It is obtained by subtracting the
given number from the highest possible number. For
example, if there is a two-digit decimal number, it
1.2.1 Conversions of Number System will be subtracted from 99; whereas a 3-bit number
in a binary system will be subtracted from 111.
A number of a particular number system can be con- Note: The 1’s complement of a binary number
verted into another number system, as follows: is obtained by interchanging the 1’s and 0’s. For
example, 1’s complement of (1011)2 is (0100)2.
1. Decimal number system to any number
system: Consider the example of (57.3)10. To find 2. Radix complement (R’s complement): This
the binary equivalent, we have is also known as true complement. It is obtained
by adding one to R-1’s complement. For example,
2 57 (57)10 − its 9’s complement is 42 and its 10’s com-
2 28 1 plement is 43.

2 14 0 2 × 0.3 = 0.6 0 1.2.2.1 Subtraction Using R-1’s Complement

27 0 2 × 0.6 = 1.2 1
23 1 2 × 0.2 = 0.4 0 For the following subtractions,
21 1 2 × 0.4 = 0.8 0 A

(111001)2 (0.0100)2 −B
----------
Therefore, (57.3)10 = (111001.0100)2 ----------
2. Any number system to decimal number the steps involved are as follows:
system: Consider the example of (111001.0100)2.
Step 1. Find R-1’s complement of B.
To find the decimal equivalent we have
Step 2. Add A and B.
(111001.0100)2 = 1 × 25 + 1 × 24 + 1 × 23 + 0 × 22
Step 3. If there is carry, then add this carry to the
+ 0 × 21 + 1 × 20 + 0 × 2-1 answer.
+ 1 × 2-2 + 0 × 2-3 + 0 × 2-4
= 32 + 16 + 8 + 0 + 0 + 1 + 0
+ 0.25 + 0 + 0 = (57.25)10

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 1.2 NUMBER SYSTEM     5

If there is no carry, then find the R-1’s complement

of the answer and place a negative sign in front of the Problem 1.4: (011)2 − (101)2
answer. Solution:
Step 1. 2’s complement of 101 is 011.
Problem 1.1: (101)2 − (011)2
Step 2. The addition of these two numbers is (011
Solution: + 011 = 0 110).
Step 1. 1’s Complement of 011 is 100. Step 3. There is a no carry, so now we will find 2’s
Step 2. The addition of these two numbers is (101 + complement of the answer obtained (which is 010)
100 = 1 001). and place a negative sign in front of it. So, the answer
is (−010)2.
Step 3. There is a carry of 1, so now we will add this
carry to the answer (1 + 001), which is (010)2.
1.2.3 Representation of Negative Numbers
Problem 1.2: (011)2 − (101)2
In−(57)10 = (1111001), the most significant bit is 1,
Solution: showing that the number is negative binary number.
Step 1. 1’s Complement of 101 is 010.
Step   2. The addition of these two numbers is 1.2.4 The IEEE Standard for Floating Point
(011 + 010 = 0 101). Numbers
Step 3. There is a no carry, so now we will find 1’s The IEEE (Institute of Electrical and Electronics
complement of the answer obtained (which is 010) Engineers) has provided a standard for floating point
and place a negative sign in front of it. So, the answer numbers and their arithmetic. This standard speci-
is (−010)2. fies how single precision (32-bit) and double precision
(64-bit) floating point numbers are to be represented.
1.2.2.2 Subtraction Using R’s Complement
1. Single Precision: The IEEE single precision
f loating point standard representation requires a
In this method, we find R’s complement of the subtra-
32-bit word. The first bit to the left is the sign bit,
hend and we do not add the carry, as in step 2. Rest of
the next eight bits are the exponent bits, and the
the steps are the same.
final 23 bits form the fraction part (Fig. 1.2).
of a normalized number = (−1)s ×
Problem 1.3: (101)2 − (011)2
The value
e-127
1.m × 2
Solution: where s = 1 for negative number, s = 0 for positive
Step 1. 2’s complement of 011 is 101. number, m = mantissa and e = exponent.
Step 2. The addition of these two numbers is (101 + 2. Double Precision: The IEEE double precision
101 = 1 010). f loating point standard representation requires a
Step 3. There is a carry of 1, so now we will not add 64-bit word. The first bit is the sign bit, the next
this carry to the answer (001), which is (010)2. eleven bits are the exponent bits, and the final
52 bits form the fraction part (Fig. 1.3).

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
s exponent significand/mantissa
1-bit 8-bits 23-bits
Figure 1.2 |   Single Precision (32 bits).

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
s exponent significand/mantissa
1-bit 11-bits 20-bits
significand (continued)
32-bits
Figure 1.3 |   Double Precision (64 bits).

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 6     Chapter 1: Digital Electronics 

its output can be represented by Boolean expression.

Problem 1.5: Consider the decimal number: +116.25.
The symbols used to represent logic gates are shown
Represent it using single precision IEEE floating
in Fig. 1.4.
point standard.
Solution: The equivalent binary representation is
+1110100.01
Normalizing number = +1.11010001 × 26
= +1.11010001 × 2133−127 AND gate NAND gate

=+
 1.11010001
× 210000101−01111111
In IEEE 754 format:
Sign Exponent Fraction OR gate NOR gate
0 10000101 11010001000000000000000

1.3 BOOLEAN LOGIC

XOR gate XNOR gate
NOT gate
The concept of Boolean logic was proposed by George
Boole, in which any information or data is represented
in the form of two states, which are complement to each

Figure 1.4 |   Logic gates symbols.

other (such as 0 and 1, hot and cold, black and white,
north and south, etc.).
Logic gates form the basic building block of the digi-
tal system. A logic gate is an electronic device that takes Table 1.2 represents 15 basic operations that can be
logical decisions based on given input combinations and performed.

Table 1.2 |   Basic operations in Boolean algebra

Inputs Operations
X Y Null Identity Inhibit Transfer
X Inhibit Y Y Inhibit X
0 0 0 1 0 0 0
0 1 0 1 0 1 1
1 0 0 1 1 0 0
1 1 0 1 0 0 1
Inputs Operations
X Y AND OR NOT XOR XNOR
NOT X NOT Y
0 0 0 0 1 1 0 1
0 1 0 1 1 0 1 0
1 0 0 1 0 1 1 0
1 1 1 1 0 0 0 1
(Continued)

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 1.3 BOOLEAN LOGIC     7

Table 1.2 |   Continued

Inputs Operations
X Y NAND NOR Implication
X Implication Y Y Implication X
0 0 1 1 1 1
0 1 1 0 1 0
1 0 1 0 0 1
1 1 0 0 1 1

Table 1.2 is interpreted as follows: 3. X + X = X

1. Null − All the outputs are zero. 4. X + 1 = 1
2. Identity − All the outputs are one. 5. X + Y = Y + X
3. X inhibit Y − Represented as (x ⋅ ∼y)
Y inhibit X − Represented as (y ⋅ ∼x)
6. X + (Y + Z ) = (X + Y ) + Z
4.
5. Transfer − Same as y 7. X ⋅ (Y + Z ) = X ⋅ Y + X ⋅ Z
6. AND − x ⋅ y (Similar to intersection in set theory) 8. ∼(X + Y ) = ∼X ⋅ ∼Y (Also called DeMorgan’s law)
7. OR − x + y (Similar to union in set theory)
9. X + (X ⋅ Y ) = X
8. NOT X − ∼x (Also known as complement of x)
9. NOT Y − ∼y (Also known as complement of y) 10. ∼(∼X ) = X
10. XOR − (∼x ⋅ y) + (x ⋅ ∼y) (Also known as parity
checker) 1.3.2 Duality Theorem
11. XNOR − (x ⋅ y) + (∼x ⋅ ∼y)
12. NAND − ∼(x ⋅ y) Every expression remains valid if we interchange the
13. NOR − ∼(x + y) operator and identity elements. Following laws are the
14. X implication Y (∼x + y) dual of the respective laws written above.
15. Y implication X (∼y + x)
1. X ⋅1 = X
(X ⋅ ∼X ) = X ⋅ X ′ = 0
Problem 1.6: It is defined that x * y = x ′y ′ + xy and
2.
z = x * y . Among the following P, Q and R, which 3. X ⋅X = X
statement is correct? 4. X ⋅0 = 0
P: x = y * z 5. X ⋅Y = Y ⋅X
Q: y = x * z 6. X ⋅ (Y ⋅ Z ) = (X ⋅ Y ) ⋅ Z

R: x * y * z = 1 7. X + (Y ⋅ Z ) = (X + Y ) ⋅ (X + Z )
8. (X ⋅ Y )′ = X ′ + Y ′
Solution:
9. X ⋅ (X + Y ) = X
x Y z P Q R
0 0 1 0 0 1 1.3.3 Consensus Theorem
0 1 0 0 1 1 It is applicable only if a Boolean function has
1 0 0 1 0 1 1. three variables
1 1 1 1 1 1 2. each variable is used two times
3. only one variable in complemented or non-­
complemented form
1.3.1 Boolean Algebra Laws (Huntington’s
Then, the term related to the complemented and non-
Postulates)
complemented variable is the answer.
The laws of Boolean Algebra are given by Huntington’s
postulates: Example 1.2
1. X + 0 = X AB + A ′C + BC = AB + A ′C
2. X + (∼X ) = 1

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1.3.4 Positive Logic and Negative Logic 1.3.4.2 Minimization of Expression

Usually, the two (binary) levels are represented in two A Boolean expression which cannot be further reduced
different ways: is said to be in minimal form. Each term in minimal
1 (signifying high) and 0 (signifying low) − Known as Boolean expression is called prime implicant. The follow-
positive logic ing are the two methods for minimization:
or 1. Boolean Theorems (postulates): Using the
1 (signifying low) and 0 (signifying high) − Known as Boolean postulates, we can simplify an expression
negative logic using algebraic method. This method is relatively
difficult as we need to remember all the postulates.

1.3.4.1 Canonical and Standard Forms Problem 1.7: Simplify the Boolean function X = (A + B)(A + C )
X = (A + B)(A + C ).
The minterms and the maxterms are given in Table 1.3.
Solution:
Product-of-sums (POS) form: X = AA + AC + AB + BC

F = (x ′y ′z ′) + (xy ′z ′) + (xyz)
= A + AC + AB + BC
= A(1 + C ) + AB + BC
= m0 + m4 + m7 = A(1) + AB + BC
= ∑ m(0, 4, 7) = A + AB + BC
= A(1 + B) + BC
Sum-of-products (SOP) form: = A(1) + BC
F = (X + Y + Z ) ⋅ (X ′ + Y + Z ) ⋅ (X + Y + Z ) = A + BC

= M 0 ⋅ M 4 ⋅ M7
Problem 1.8: Simplify the Boolean function X = A + A¢B
= ∏ M (0, 4, 7) X = A + A¢B.

In order to convert minterm to maxterm, put all those Solution:

numbers in maxterm which are not present in minterm, X = A(1 + B) + A ′B
and vice versa. = A ⋅ B + A + A ′B = A ⋅ B + A ′ B + A
= (A + A ′) ⋅ B + A = 1 ⋅ B + A = B + A
∑ m(0, 1, 5) = ∏ M (2, 3, 4, 6, 7)

Table 1.3 |   Minterms and Maxterms

Minterms (SOP) Maxterms (POS)
Decimal Binary Term Designation Term Designation
0 000 x′y′z′ m0 X+Y+Z M0
1 001 x′y′z m1 X + Y + Z′ M1
2 010 x′yz′ m2 X + Y′ + Z M2
3 011 x′yz m3 X + Y′ + Z′ M3
4 100 xy′z′ m4 X′ + Y + Z M4
5 101 xy′z m5 X′ + Y + Z′ M5
6 110 xyz′ m6 X′ + Y′ + Z M6
7 111 xyz m7 X′ + Y′ + Z′ M7

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 1.3 BOOLEAN LOGIC     9

2. Karnaugh-Map Method (K-Map method): Grouping of two adjacent cells removes one vari-
Karnaugh-map (K-map) involves graphical repre- able and output will contain common variables in
sentation for simplifying Boolean expressions. It two terms.
consists of group of adjacent cells in which each 2. Quads: We can group four adjacent cells in K-map
cell corresponds to one of the combinations of max- forming a quad. Grouping a quad eliminates the
terms or minterms of n variables and is represented two variables that appear in both normal and com-
by group of literals. For n-variable K-map, there plemented form. Resultant terms contain (n − 2)
are 2n cells required (Figs. 1.5−1.7). From one variables, where n is the number of variables.
cell to the neighbouring cell there must be only 3. Octet: A group of eight adjacent cells is called
one literal change. While solving the K-map from octet. Grouping of 1’s eliminates three variables.
higher-order group to lower-order group only, the Resultant terms contain (n − 3) variables, where
simplification must be done. In K-map, leftmost n is the number of variables.
column and rightmost column of the same row are
considered to be adjacent. 1.3.4.4 SOP Simplification Using K-Map
If K = 1, it represents that all the cells are 1 so
there is no need of circuit. A higher priority will be given to more possible covering,
that is, octet then to quad and then to pairs. The follow-
1.3.4.3 Grouping of Cells for Simplification ing procedure is followed:
1. Check the SOP expression and convert to standard
The grouping of cells for simplification is done in the and canonical form if required.
following ways: 2. Draw the K-map based on the number of variables.
1. Pairs: If two adjacent cells either in row or in 3. On the basis of SOP canonical form, 1’s are entered
column contain 1’s, they are said to be in pairs. to corresponding cells. Group the adjacent cells
and take the common variable from each grouping.
4. Combine each group variable to obtain simplified
B 0 1 B 0 1 expression.
A A
0 00 01 0 0 1
1 10 11 1 2 3 1.3.4.5 POS Simplification Using K-Map
Two-variable K-map Cell designation
1. Check the POS expression and convert it to stan-
dard and canonical form if required.
B B B´ 2. Draw the K-map based on the number of variables.
A
A A + A+ 3. Enter 0’s in corresponding cells and group the
B B´ B adjacent cells.
A B B´
A´ A´B´ A´B A´ A´ + A´ + 4. Take the common variable from each grouping and
A AB´ AB B B´ write terms in OR form. The uncomplemented vari-
able is assigned 0 and complemented is assigned 1.
Cells with minterm Cells with maxterm
5. Combine each OR term from the different groups
Figure 1.5 |   Two-variable K-map. to obtain simplified expression.

BC 00 01 11 10 BC 00 01 11 10
A A
0 000 001 011 010 0 0 1 3 2
1 100 101 111 110 1 4 5 7 6
Three-variable K-map Cell designation

BC B´C BC BC´ BC B + C B + C´ B´ + C´ B´ + C
B´C´
A A
A´ A´B´C´ A´B´C A´B C A´B C´ A A + B + C A + B + C´ A + B´ + C´ A + B´ + C
A AB´C´ AB´C AB C AB C´ A A´ + B + C A´ + B + C´ A´ + B´ + C´ A´ + B´ + C
Cells with minterm Cells with maxterm
Figure 1.6 |   Three-variable K-map.

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 10     Chapter 1: Digital Electronics 

CD 00 01 11 10 CD 00 01 11 10
AB AB
00 0000 0001 0011 0010 00 0 1 3 2
01 0100 0101 0111 0110 01 4 5 7 6
11 1100 1101 1111 1110 11 12 13 15 14
10 1000 1001 1011 1010 10 8 9 11 10
Four-variable K-map Cell designation

CD C´D´ C´D CD CD´

AB
A´B´ A´B´C´D´ A´B´C´D A´B´CD A´B´CD´
A´B A´BC´D´ A´BC´D A´BCD A´BCD´
AB ABC´D´ ABC´D ABCD ABCD´
AB´ AB´C´D´ AB´C´D AB´CD AB´CD´
Cells with minterm

CD
AB C+D C + D´ C´ + D´ C´ + D
A+B A+B+C+D A + B + C + D´ A + B + C´ + D´ A + B + C´ + D
A + B´ A + B´+ C + D A + B´+ C + D´ A + B´+ C´ + D´ A + B´ + C´+ D
A´+ B´ A´+ B´+ C + D A´+ B´+ C + D´ A´+ B´+ C´+ D´ A´+ B´+ C´+ D
A´+ B A´+ B + C + D A´+ B + C + D A´+ B + C´+ D´ A´+ B + C´+ D
Cells with maxterm
Figure 1.7 |   Four-variable K-map.

Problem 1.9: Simplify F (A, B, C , D) = ∑ m(0, 2, 5, 7, 13, 15Problem

) 1.10: Simplify F (A, B, C , D) = ACD + A ′B + D ′
D) = ∑ m(0, 2, 5, 7, 13, 15). F (A, B, C , D ) = ACD + A ′ B + D ′
Solution: Converting to standard SOP form. The first
Solution:
term ACD has one missing variable B.
CD
00 01 11 10 ACD = ACD(B + B ′) = ABCD + AB ′CD
AB
00 1 1 ABD Similarly,
0 1 3 2
A ′B = A ′B(C + C ′)(D + D ′)
01 1 1
4 5 7 6 = A ′BCD + A ′BCD ′ + A ′BC ′D + A ′BC ′D ′
BD
11 1 1 D ′ = D ′(B + B ′)(C + C ′) + (A + A ′)
12 13 15 14
Combining all terms, we get
10
8 9 11 10 F = ABCD + AB ¢CD + A¢BCD + A¢BCD ¢
+ A¢BC ¢D + A¢BC ¢D ¢ + ABC ¢D ¢
The simplified Boolean expression is
F = A¢B ¢D ¢ + BD. +AB ¢CD ¢ + AB ¢C ¢D ¢ + A¢B ¢CD ¢ + A¢B ¢C ¢D ¢

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 1.4 DIGITAL CIRCUITS     11

CD Problem 1.11: Simplify S = PM (0, 1, 2, 3, 4, 7)

00 01 11 10
AB
1
Solution:
00
D´
1
0 1 3 2 BC
A 00 01 11 10
01 1 1 1 1 A´B
4 5 7 6 0 0 0 0 0 Group 1 (A)
0 1 3 2
11 1 1 1 0 0
12 13 15 14 (B + C)1
4 5 7 6
10 1 1 11 1 10 AC Group 2
8 9 Group 3(B´ + C´)
The simplified Boolean expression is F = D ′ + A ′B + AC
The simplified Boolean expression is S = A ⋅ (B + C ) ⋅ (B ′ + C
F = D ′ + A ′B + AC . S = A ⋅ (B + C ) ⋅ (B ′ + C ′)

Problem 1.12: Simplify F (A, B, C , D) = ΠM (4, 5, 6, 7, 8, 12) ⋅ d(0, 1, 2, 3, 9, 11, 14)

Solution: A logic circuit output may be either 0 or 1 but some circuit has output that will never occur for certain
combinations of inputs. These conditions are don’t care conditions and represented by X in K-map.
CD
00 01 11 10
AB
00 X X X X A
0 1 3 2

01 O O O O
4 5 7 6

11 Need not worry about

O X
12 13 15 14 this don’t care case
C +D
10 O X X
8 9 11 10

Invalid grouping because it does

not have atleast one O
The simplified Boolean expression is F = A(C + D).

1.4 DIGITAL CIRCUITS 1.4.1 Combinational Circuits

A logic circuit whose output at any instant of time

The classification of digital circuitsis shown in Fig. 1.8. depends only on the present input is called combina-
tional circuit. It contains no memory element.
Digital circuits

1.4.1.1 Half Adder

Combinational circuits Sequential circuits
A half adder is a combinational circuit for the addi-
tion of two 1-bit numbers. X and Y are inputs and
outputs are sum (S) and carry (C) (Fig. 1.9 and
Synchronous Asynchronous Table 1.4).

Figure 1.8 |   Types of digital circuits.

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 12     Chapter 1: Digital Electronics 

X′
Y′
X
Sum (S)
Y Cin
X´
Carry (C) Y
C′in
Sum (S)
Figure 1.9 |   Logic diagram of a half adder. X
Y′
C′in
Table 1.4 |   Truth table X
Inputs Outputs Y
Cin
X Y Carry (C  ) Sum (S  )
0 0 0 0 X
0 1 0 1 Y
1 0 0 1 Y
Cin Carry (C)
1 1 1 0

X
The sum and carry are as follows: Cin

S = X ′ Y + XY ′ Figure 1.10 |   Logic diagram of a full adder.

C = XY
1.4.1.3 Half Subtractor
1.4.1.2 Full Adder
A half subtractor is a combinational circuit that subtracts
A full adder is a combinational circuit that performs 2 bits (minuend and subtrahend) and produces their dif-
the addition of 3 bits (2 significant bits and previous ferences and borrow as output (Fig. 1.11 and Table 1.6).
carry). It consists of three inputs and two outputs,
two input bits that are to be added, the third input X
is the carry from the previous position (Fig. 1.10 and Difference (D)
Y
Table 1.5).

Table 1.5 |   Truth table

Borrow (B)

Inputs Outputs Figure 1.11 |   Logic diagram of a half subtractor.

X Y Cin Sum (S) Cout
0 0 0 0 0 Table 1.6 |   Truth table
0 0 1 1 0 Inputs Outputs
0 1 0 1 0 X Y Difference (D) Borrow (B)
0 1 1 0 1
0 0 0 0
1 0 0 1 0
0 1 1 1
1 0 1 0 1
1 0 1 0
1 1 0 0 1
1 1 1 1 1 1 1 0 0

The difference and borrow are as follows:

The sum and carry are as follows:

S = X ′Y ′Cin + X ′YCin
′ + XYCin D = XY ′ + X ′Y
Cout = ACin + XY + YCin B = XY

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 1.4 DIGITAL CIRCUITS     13

X´
Y´
Bin X´

X´ Y
Y
B´in Y
Difference (D)
Bin Borrow
X
Y´ (Bout)
B´in X´
Bin
X
Y
Bin

Figure 1.12 |   Logic diagram of a full subtractor.

1.4.1.4 Full Subtractor adders and 1 OR gate, so n-bit parallel adder can be made
from (2n − 1) half adders and (n − 1) OR gates.
A full subtractor is a combinational circuit that per-
forms subtraction involving 3 bits (minuend bit, sub- Y3 X3 Y2 X2 Y1 X 1 Y0 X0
trahend bit and borrow from previous stage) (Table 1.7
and Fig. 1.12).

Table 1.7 |   Truth table Full adder Full adder Full adder Half adder
Inputs Outputs
X Y Bin Difference (D) Bout
Cout S3 S2 S1 S0
0 0 0 0 0
0 0 1 1 1 Figure 1.13 |   Block diagram of a parallel adder.
0 1 0 1 1
1.4.1.6 Look-Ahead Carry Header
0 1 1 0 1
1 0 0 1 0 In a parallel adder, carry propagation delay is present.
1 0 1 0 0 To overcome this difficulty, look-ahead carry adder is
1 1 0 0 0 used. It uses logic gates to look at lower-order bits of
augend and addend to check if higher-order carry is gen-
1 1 1 1 1 erated or not. It uses two functions, carry generate and
carry propagate, for the same (Fig. 1.14).
The difference and borrow are as follows:
D = X ′Y ′Bin + X ′YBin
′ + XY ′Bin
′ + XYBin Problem 1.13: How many AND and OR gates are
required to design 7-bit look-ahead carry adder.
B = X ′Y + X ′YBin + YBin
Solution: To design a 7-bit look-ahead carry adder,
we need
1.4.1.5 Parallel Adder (Ripple Carry Adder)
n(n + 1) 7(7 + 1)
A parallel adder consists of full adders connected in AND gate = = = 28
2 2
cascade, that is, carry output of each adder is connected to
OR gate = n = 7
the carry input of the next higher-order adder (Fig. 1.13).
An n-bit parallel adder is constructed using (n − 1) full
where n is the number of bits.
adders and 1 half adder. As full adder consists of 2 half

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 14     Chapter 1: Digital Electronics 

Ai Table 1.8 |   Truth table of 2X4 decoder

Bi Pi
Ci Si Inputs Outputs
A B Y3 Y2 Y1 Y0
Gi
0 0 0 0 0 1
Ci + 1 0 1 0 0 1 0
1 0 0 1 0 0
Full Adder circuit with Pi and Gi
1 1 1 0 0 0
Carry propagation Pi = Ai + Bi
1.4.1.8 Encoder
Carry generation Gi = AiBi
Output sum Si = Pi + Ci An encoder is a combinational circuit that has 2n (or
fewer) inputs and n output lines (Fig. 1.17). It accepts
Output carry Ci+1 = Gi + PiCi
an active level on one of its inputs representing a decimal
Figure 1.14 |   Logic diagram of a look-ahead adder. or octal digit and converts it to a coded output.

.
1.4.1.7 Decoder . .
2n input . 2n : n . n output
. .
lines . Encoder . lines
A decoder is a combinational circuit that converts
binary information from n input lines to a maximum of
2n unique output lines (Fig. 1.15). The size of a decoder
is n to m where m ≤ 2n. It is used to route input data to Figure 1.17 |   Block diagram of an encoder.
a specified output line for memory addressing (Fig. 1.16
and Table 1.8). 1.4.1.9 Multiplexer

A multiplexer is a combinational circuit that provides

. inputs one by one at single output; and which input will
.
n input . Decoder . be out at any instant depends upon the combination at
. (n : 2n) . 2n output select lines (Fig. 1.18). It converts parallel data to serial
lines
. .
.
lines
. data (Fig. 1.19 and Table 1.9).

..
2n inputs . MUX Output lines
Enable inputs .
Figure 1.15 |   Block diagram of a decoder.

n select lines
A B Enable Figure 1.18 |   Block diagram of a multiplexer.

Table 1.9 |   Truth table of 4 to 1 MUX

Y0
Select Lines Outputs
Y1 S1 S0 Y
Y2 0 0 I0
0 1 I1
Y3
1 0 I2

Figure 1.16 |   Logic diagram of a 2X4 decoder.

1 1 I3

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 1.4 DIGITAL CIRCUITS     15

The Boolean function is 1.4.1.10 Boolean Function Implementation

Using Multiplexers
Y = I 0S0′ S1′ + I1S0S1′ + I 0S0′ S1 + I 0S0S1
1. Take one variable for input lines and others for
selection lines.
S1 S0 2. Write the minterms with the variable in comple-
mented form in the first row and with variable
selected in uncomplemented form in the second row.
3. Then encircle the minterms which are present in
I0 the function.
••If there is circled variable in the column, then we
I1 put 0 on the corresponding line.
Y ••If there are circled variables, then we put 1 on
I2 the line.
••If bottom variable is circled and top is not cir-
I3 cled, A is used in input line.
••If bottom variable is not circled and top is cir-
Figure 1.19 |   Logic diagram of 4 to 1 MUX.
cled, A′ is used as input to that line.

Problem 1.14: Implement the function F(A, B, C, D) = Σm(1, 2, 5, 7, 9, 14) using MUX.
Solution: Select variable A for input as B, C and D for selection lines.
As there are four variables so size of MUX is 2N − 1 = 23 = 8 to 1 MUX.

1. Minterms with A′ are 0 - 7.

2. Minterms with A are 8 - 15.

I0 I1 I2 I3 I4 I5 I6 I7
A′ 0 1 2 3 4 5 6 7
A 8 9 10 11 12 13 14 25
0 1 A′ 0 0 A′ A A′

0 0
1 1
A´
2
0 3 8 to 1 Y
0 4 MUX
A´
5
A 6
A´ 7

B C D
Logic diagram

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 16     Chapter 1: Digital Electronics 

Problem 1.15: The combinatorial circuit below is Example 1.4

equivalent to ______. Design 8 × 256 decoders using 4 × 64 decoders
256/64 = 4
A I0 4/64 = 0
f(A,B,C) Total = 4
1 G: 1
1 2 MUX
0 3 Example 1.5
Design 6 × 64 decoders using 2 × 4 decoders
S1 S0 64/4 = 16
16/4 = 4
Solution:
4/4 = 1
I0 I1 I2 I3 Total = 21
A′ 0 1 2 3
A 4 5 6 7
1.4.2 Sequential Circuits
A A′ 1 0
A logic circuit whose output at any instant of time
It is equivalent to ∑m(1, 2, 4, 6). depends on the present input as well as past output is
known as sequential circuit. It contains memory element.

1.4.1.11 Demultiplexer 1.4.2.1 Flip−Flops

A demultiplexer is a combinational circuit that receives A flip−flop or bistable multivibrator is a synchronous

information on a single line and transmits this on one of 2n bistable circuit made up of logic gates that can exist in
of possible output line (Fig. 1.20). The selection of possi- either of two stable states in presence of a falling or rais-
ble output line is controlled by bit values of n select lines. ing edge of a clock signal. Flip−flops can change its state
by means of some external signal. It can “store” binary
information. There are different types of flip−flops based
on the manner the inputs affect their output state:
One
....

input
DEMUX 2n output lines 1. RS flip−flop
2. D flip−flop
3. JK flip−flop
....
4. T flip−flop
n select lines
Figure 1.20 |   Block diagram of a demultiplexer. RS Flip−Flop (Direct Coupled)
This sequential logic circuit has two stable states
Implementation of higher order decoders and multiplex- (Q = 1 set state and Q = 0 reset state) achieved by
ers by using lower order. Whenever odd number imple- giving proper inputs to R and S inputs (Figs. 1.21 and
mentation is there, one NOT gate is required. 1.22 and Table 1.10). If the circuit is in one particular
state it continues to remain in that state and can store
1-bit data.
Example 1.3
Design 4 ×16 decoders using 2 × 4 decoders
S Q
16/4 = 4 RS
flip—flop
4/4 = 1 R Q´
Total = 5
Figure 1.21 |   Block diagram of an RS flip−flop.

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 1.4 DIGITAL CIRCUITS     17

Clocked RS Flip−Flop
S
G3 G1 S
(Set) This circuit sets or resets the memory cell in synchro-
nization with the clock pulse (Figs. 1.23 and 1.24 and
Table 1.12). If clock pulse is not present, the gates G3
and G4 are inhibited; their outputs are 1.

R G4 G2 Q´
(Reset) S Q
SR
Figure 1.22 |   Logic diagram of an RS flip−flop.
CLK
flip−flop
R Q´
Table 1.10 |   Truth table of RS flip−flop
Figure 1.23 |   Block diagram of a clocked SR flip−flop.
Inputs Outputs
Sn Rn Qn+1 Table 1.12 |   Truth table of SR flip−flop
0 0 Qn (No change)
Clock Flip−Flop Inputs Outputs
0 1 0 (Reset)
CLK Sn Rn Qn+1
1 0 1 (Set)
1 0 0 Qn
1 1 Prohibited
1 0 1 0
1 1 0 1
The characteristic equation which gives the algebraic 1 1 1 Prohibited
description of the next state of a flip−flop obtained by 0 X X Qn
K-map simplification is as follows (see Table 1.11):

Qn +1 = S + R ′Qn
S G3
Table 1.11 |   Truth table
G1 Q

Present Next CLK

Flip−Flop Inputs
State State
R G4 G2 Q´
Rn Sn Qn Qn+1
0 0 0 0 Figure 1.24 |   Logic diagram of a clocked SR flip−flop.
0 0 1 1
0 1 0 1
0 1 1 1 D Flip−Flop
1 0 0 0
1 0 1 0 This circuit has only one input terminal, and output is
followed by input. It has delay of exactly one clock cycle
1 1 0 X
(Figs. 1.25 and 1.26 and Table 1.13). The input to R is
1 1 1 X
through an inverter from S.

S Qn
J or S
R 00 01 11 10 D Q
D
1 1 1 CLK
flip−flop
0 1 3 2
Q´
X X K or R
4 5 7 6 JK or SR Flip−Flop converted to D
Figure 1.25 |   Block diagram of a D flip−flop.
Qn+1 = S + R¢Qn

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 18     Chapter 1: Digital Electronics 

Table 1.13 |   Truth table of D flip−flop Table 1.14 |   Truth table of JK flip−flop
Flip−F lop Present Next Flip−Flop Present Next
­Inputs State State Inputs State State
Dn Qn Qn+1 Jn Kn Qn Qn+1
0 0 0 0 0 0 0
0 1 0 0 0 1 1
1 0 1 0 1 0 0
1 1 1 0 1 1 0
1 0 0 1
D S 1 0 1 1
Q
1 1 0 1
CLK 1 1 1 0

J G3 G1 Q
Q´
R Q´

Figure 1.26 |   Logic diagram of a D flip−flop.

CLK
Q
G4 G2 Q´
The characteristic equation is Qn+1 = D (Fig. 1.27) K

Qn 0 Figure 1.29 |   Logic diagram of a JK flip−flop.

1
The characteristic equation is Qn +1 = JQn′ + KQn
D
0 0 1
(Fig. 1.30).
1 1 D
1 2 3 K Qn
Qn+1 = D J 00 01 11 10

Figure 1.27 |   K-Map 1 1

0 0 1 3 2
JK Flip−Flop
The uncertainty in SR flip−flop when Sn = Rn = 1 can 1
1 1
be avoided by using JK flip−flop (Figs. 1.28 and 1.29 4 5 7 6
and Table 1.14). The output of JK flip−flop is con- T
nected back to the inputs of gate. The inputs J and K Qn+1 = K´Qn + JQ´n
are ANDed with Q and Q′ to obtain S and R inputs:
Figure 1.30 |   K-Map
S = JQ′ Repetition of toggle for a single-clock pulse is known
R = J ⋅Q as race-around problem. The output of JK flip−flop
will oscillate between 0 and 1 during a single-clock pulse
The flip−flop sets when input J is high and resets when so that at the end of clock pulse the value of Q is uncer-
input K is high. If J = K = 1, the flip−flop will toggle on tain. This problem can be avoided by decreasing the
the next positive clock. pulse width, by edge triggering or increasing propaga-
tion delay.
J Q
Master−Slave JK Flip−flop
CLK JK It is a cascade of two RS flip−flops (master and slave)
flip−flop with feedback from outputs of slave to input of master
K Q´ to avoid race-around problem. Positive clock pulses are
applied to first flip−flop and pulses are inverted before
Figure 1.28 |   Block diagram of a JK flip−flop. applying to slave flip−flop (Fig. 1.31).

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 1.4 DIGITAL CIRCUITS     19

Qm SS
J G3m G1m G3s G1s Q
CLK

G4m G2m G4s G2s Q′

K RS
Qm
Master FF
Slave FF
CLK

Figure 1.31 |   Block diagram of a master−slave JK flip−flop.

T Flip−flop
It is also known as toggle flip−flop, which is obtained Qn 0 1
by connecting both inputs of JK flip−flop (Fig. 1.32 and T
Table 1.15). 1
0 0 1
J
T Q
1
JK (T) 1 2 3
CLK
flip−flop
Q´ Qn+1 = T´Qn + T Q´n
K
Figure 1.32 |   Block diagram of a T flip−flop. Figure 1.33 |   K-Map

Table 1.15 |   Truth table of T flip−flop

Flip−Flop Inputs Present State Next State Excitation Table of Flip−Flop
The excitation table of flip−flop states is given in
Tn Qn Qn+1
Table 1.16.
0 0 0
0 1 1
1 0 1 Conversion Equation
1 1 0 The flip−flop conversion equations are given in Table 1.17.

Table 1.16 |   Excitation Table of Flip-flop States

Flip-Flop States RS Flip-Flop Inputs JK Flip-Flop Inputs D Flip-Flop T Flip-Flop

Inputs Inputs
Present Next R S J K
State State
(Qn) (Qn +1)
0 0 X 0 0 X 0 0
0 1 0 1 1 X 1 1
1 0 1 0 X 1 0 1
1 1 0 X X 0 1 0

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 20     Chapter 1: Digital Electronics 

Shift
registers

Based Based on
on direction input−output
of data
movement mode

Shift left Shift right Bidirectional Serial-in Serial-in Parallel-in Parallel-in Universal
register register shift serial-out parallel-out serial-out parallel-out register

Figure 1.34 |   Types of registers

Table 1.17 |   Flip−flop conversion equations computation. There are different types of registers as
shown in Fig. 1.34.
S = JQ′
1 SR to JK
R = K ⋅Q 1. Serial-In/Serial-Out Shift Register: It accepts
data serially on single input line and produces output
S =D in serial form. Data can be shifted right or left.
2 SR to D •• Shift right register: In shift right register,
R = D′ serial data is entered from the left side of a regis-
S = TQ′ ter and leaves from the right side. For example,
3 SR to T a 4-bit number 1101 (QDQCQBQA) is entered
R = TQ serially into first flip−flop D from the left side
(Fig. 1.35).
J =S
4 JK to SR
K =R
J =D FF1 FF2 FF3 FF4
5 JK to D Din D QD D QC D QB D QA Dout
K = D′
D C B A
J =T
6 JK to T
K=T
7 D to JK D = TQ′ + K ′Q CLK
Figure 1.35 |   4-Bit shift right register.
8 D to SR D = S + R ′Q

9 D to T D = T ⊕Q The content of register after each clock pulse is

shown in Table 1.18.
10 T to SR T = SQ′ + RQ
Table 1.18 |   Content of register after each clock pulse
11 T to D T =D⊕Q
Clock QD QC QB QA
12 T to JK T = JQ′ + KQ Pulse
0 0 0 0 0
Applications of Flip−Flops 1 1 0 0 0
Registers 2 0 1 0 0
Registers are collection of flip−flops, and each flip−flop 3 1 0 1 0
is capable of storing single bit of information. They make 4 1 1 0 1
stored information available to the logic elements for the

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 1.4 DIGITAL CIRCUITS     21

•• Shift left register: In shift left register, serial Note: A universal register can perform all the
data is entered from the right side of the register operations of shift register.
and leaves from the left side. For example, a
2. Serial-In to Parallel-Out (SIPO): The regis-
4-bit number 1101 (QDQCQBQA) is entered seri-
ter is loaded with data serially, one bit at a time,
ally into input of shift left register (Fig. 1.36).
with the stored data being available at the output
FF4 FF3 FF2 FF1 in parallel form (Fig. 1.37).
Dout Din
QD D QC D QB D The content of register after each clock pulse is
given in Table 1.20.
D C B A
Table 1.20|   Content of register after each clock pulse
CLK Clock Pulse QA QB QC QD
Figure 1.36 |   4-Bit shift left register. 0 0 0 0 0
The content of register after each clock pulse is 1 1 0 0 0
given in Table 1.19.
2 0 1 0 0
Table 1.19 |   Content of register after each clock pulse
3 0 0 1 0
Clock Pulse QD QC QB QA
4 0 0 0 1
0 0 0 0 0
5 0 0 0 0
1 0 0 0 1
2 0 0 1 1 3. Parallel-In to Serial-Out (PISO): The parallel
3 0 1 1 0 data is loaded simultaneously into the register and
is shifted out of the register serially, one bit at a
4 1 1 0 1
time (Fig. 1.38).

4-bit Parallel Data Output

QA QB QC QD

D Q D Q D Q D Q
Serial FFA FFB FFC FFD
Data In
CLK CLK CLK CLK
CLR CLR CLR CLR
Clear (CLR)
Clock (CLK)

Figure 1.37 |   4-Bit SIPO register.

1 Q Q
mux D Q mux D Q mux D Q mux D
FFA FFB FFC FFD Serial
Data Out
CLK CLK CLK CLK

Clock
PD PC PB PA
4-bit Parallel Data Input
Figure 1.38 |   4-Bit PISO register.

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 22     Chapter 1: Digital Electronics 

4-bit Parallel Data Output

QD QC QB QA

D Q D Q D Q D Q
FFA FFB FFC FFD

CLK CLK CLK CLK

Clock

PD PC PB PA

4-bit Parallel Data Input

Figure 1.39 |   4-Bit PIPO register.

4. Parallel-In to Parallel-Out (PIPO): The par- The counter with n flip−flops has a maximum modulus
allel data is loaded simultaneously into the register, 2n so it can count from 0 to 2n−1. It can also produce
and transferred together to their respective outputs MOD numbers less than 2n by skipping the states.
by the same clock pulse (Fig. 1.39).
1. 4-Bit Asynchronous Up Counter: Figures
1.40−1.42 show a 4-bit asynchronous counter con-
Counters
structed using JK flip−flops. The clock input of first
A counter is a sequential logic circuit that is capable
flip−flop (the one with the Q0 output) is connected
of counting the number of clock pulses arriving at its
to the external clock. The clock of second flip−flop
input in a cyclic sequence. It is just a register that shifts
drives from output Q0 of the first flip−flop and so
through a predetermined sequence of states upon the
on. Each flip-flop input (J = K = 1) is connected
application of input clock pulses. There are two differ-
to HIGH voltage so it toggles when negative edge is
ent types of counters − synchronous counter ­(parallel
arrived at clock input and counts from 0000 to 1111.
­counter) and asynchronous counter (serial or ripple
counter) (Table 1.21). 0000
1111 0001
Table 1.21 |   Differences between asynchronous and
0 1
1110 15
synchronous counter. 2 0010
14
Asynchronous Synchronous 0011
1101 13 3
Counter Counter
The output of first There is no connection
flip−flop drives the clock between output of first 1100 12 4 0100
for next flip−flop. So all flip−flop and clock input
flip−flops are not clocked of next flip−flop. All the 5 0101
simultaneously. flip−flops are clocked 1011 11
simultaneously.
10 6
Speed is low. Speed is high. 0110
1010
9 7
Simple logic circuit as Complex design as number 8
number of states increases. of states increases. 1001 0111
1000
Figure 1.40 |   State diagram of a 4-bit asynchronous
Example: Ring counter, Example: Binary ripple
Johnson counter. counter, Up-down counter.
counter.

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 1.4 DIGITAL CIRCUITS     23

Vcc = 5V

J0 Q0 J1 Q1 J2 Q2 J3 Q3
CLK

K0 Q´0 K1 Q´1 K2 Q´2 K3 Q´3

Figure 1.41 |   Logic diagram for a 4-bit asynchronous counter.

Count

QA 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0

QB 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0

QC 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0

QD 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0

Figure 1.42 |   Timing diagram for a 4-bit asynchronous counter.

2. MOD-10 Asynchronous Counter: A MOD-10 otherwise it maintains the previous state. The flip−
asynchronous counter has 10 states and number of flop 2 toggles when both Q1 and Q0 are 1. The flip−
flip−flops required are 24 ≥ 10 (Figs. 1.43 and 1.44). flop 3 toggles when Q2, Q1 and Q0 are 1 (Table 1.22).
It counts the sequence from 0000 to 1001 and after
that it returns to the initial state. Table 1.22 |   Truth table for 4-bit synchronous counter
0000 Count Q3 Q2 Q1 Q0
0001
15 0 1 0 0 0 0 0
2 0010
14 1 0 0 0 1
3 0011 2 0 0 1 0
13
3 0 0 1 1
12 4 0100 4 0 1 0 0

5 0101 5 0 1 0 1
11
6 0 1 1 0
10 6
0110 7 0 1 1 1
1010
9 7 8 1 0 0 0
8
1001 0111
1000 9 1 0 0 1
Figure 1.43 |   State diagram of a 4-bit MOD-10 counter. 10 1 0 1 0
3. 4-Bit Synchronous Counter: In a 4-bit synchro- 11 1 0 1 1
nous counter, the least significant bit of flip−flop is 12 1 1 0 0
connected at high level and other inputs of JK flip−
13 1 1 0 1
flop are driven by some combination of flip−flop out-
puts. Figure 1.45 shows the logic diagram of a 4-bit 14 1 1 0 0
synchronous counter. The output of flip−flop0 always 15 1 1 0 1
toggle, and that of flip−flop1 toggles when Q0 is 1,

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 24     Chapter 1: Digital Electronics 

Vcc
0 1 0 1

J0 Q0 J1 Q1 J2 Q2 J3 Q3
CLK

K0 Q´0 K1 Q´1 K2 Q´2 K3 Q´3

CLR CLR CLR CLR

1
Figure 1.44 |   Logic diagram for a MOD-10 asynchronous counter.

Q0 Q1 Q2 Q3
Vdd

J Q J Q J Q J Q

FF 0 FF 1 FF 2 FF 3
C C C C

K Q´ K Q´ K Q´ K Q´

This flip−flop This flip−flop This flip−flop This flip−flop

toggles on every toggles only if toggles only if toggles only if
clock pulse Q0 is “high” Q0 AND Q1 Q0 AND Q1 AND
are “high” Q2 are “high”
Figure 1.45 |   Logic diagram of a 4-bit synchronous counter.

4. MOD-5 Synchronous Counter: Table 1.23 |   Excitation table for JK flip−flop
Step 1: Number of states is five, so counting sequence
0 to 4. Flip−Flop States JK Flip−Flop Inputs
Flip−flops required are 2n ≥ 5, so n = 3. Present Next J K
Let us label these flip−flops as A, B and C. State State
Step 2: Obtain the excitation table for JK flip−flop (Qn) (Qn+1)
(Table 1.23). 0 0 0 X
Step 3: Develop state table using the excitation table
(Table 1.24). 0 1 1 X
Step 4: K-map simplification for finding expressions 1 0 X 1
corresponding to each input (Fig. 1.46). 1 1 X 0

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 1.4 DIGITAL CIRCUITS     25

Table 1.24 |   State table

Present State Next State Flip−Flop Inputs
QC QB QA QC+1 QB+1 QA+1 JC KC JB KB JA KA
0 0 0 0 0 1 0 X 0 X 1 X
0 0 1 0 1 0 0 X 1 X X 1
0 1 0 0 1 1 0 X X 0 1 X
0 1 1 1 0 0 1 X X 1 X 1
1 0 0 0 0 0 X 1 0 X 0 X
1 0 1 X X X X X X X X X
1 1 0 X X X X X X X X X
1 1 1 X X X X X X X X X

Expression for JC Expression for KC

QB Q A QBQA

QC 00 01 11 10 QC 00 01 11 10

0 1 0 X X X X
0 1 3 2 0 1 3 2

1 X X X X 1 1 X X X
4 5 7 6 4 5 7 6
J C = Q BQ A KC = 1

Expression for JB Expression for KB

QB QA QBQA

QC 00 01 11 10 QC 00 01 11 10

0 1 X X 0 X X 1
0 1 3 2 0 1 3 2

1 X X X 1 X X X X
4 5 7 6 4 5 7 6
J B = QB KB = QA

Expression for JA Expression for KA

QB QA QBQA

QC 00 01 11 10 QC 00 01 11 10

0 1 X X 1 0 X 1 1 X
0 1 3 2 0 1 3 2

1 X X X 1 X X X X
4 5 7 6 4 5 7 6
JA = Q´C KA = 1
Figure 1.46 |   K-map simplification.

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 26     Chapter 1: Digital Electronics 

Step 5: Logic diagram of MOD-5 counter (Fig. 1.47). Table 1.25 |   Continued

CLK CLR′ Q3(MSB) Q2 Q1 Q0

1 1 0 0 0 1
1 1 0 0 1 0
J A QA J B QB JC QC
1 1 0 1 0 0
1 1 1 0 0 0
KA Q´A KB Q´B KC Q´C
7. Johnson counter: A Johnson counter (switch-
High High

CLK tail ring counter, twisted-ring counter or walking-
Figure 1.47 |   Logic diagram of a MOD-5 counter. ring counter) is a variation of shift register counter,
where the complement of the output of the last
flip−flop is fed back as input to the first flip−flop
5. Shift register counter: It is basically a shift reg-
(Fig. 1.49 and Table 1.26). The counter has count-
ister whose serial output is connected back to serial
ing sequence length of twice the length of the shift
input in order to produce special sequences.
register, that is, number of flip−flops.
6. Ring counter: A ring counter is a circular shift
register in which output of last flip−flop is con- Q0 Q1 Q2 Q3
nected to the input of the first in a ring (Fig.
1.48 and Table 1.25). In this, only one flip−flop
is in state one while others are in their zero
states. Each state repeats after every n clock D3 Q3
D 0 Q0 D 1 Q1 D2 Q2
cycles, where n is the number of flip−flops used. FF4
Initially the counter is reset by applying low FF1 FF2 FF3 Q´3
signal to active low CLR input. All flip−flops
reset except the first flip−flop. CLK
Figure 1.49 |   4-Bit Johnson counter.
Q0 Q1 Q2 Q3
Table 1.26 |   Truth table of 4-bit Johnson counter
LSB MSB CLK Q0 Q1 Q2 Q3 Q3′
PRE
D 0 Q0 D 1 Q1 D 2 Q2 D 3 Q3 0 0 0 0 0 1
0FF 1FF 2FF 3FF 1 1 0 0 0 1
2 1 1 0 0 1
CLK
3 1 1 1 0 1
CLR´
4 1 1 1 1 0
Figure 1.48 |   Logic diagram of a 4-bit ring counter.
5 0 1 1 1 0

Table 1.25 |   Truth table of 4-bit ring counter

6 0 0 1 1 0
7 0 0 0 1 0
CLK CLR′ Q3(MSB) Q2 Q1 Q0
8 0 0 0 0 1
0 0 0 0 0 1
1 1 0 0 1 0
1.5 DIGITAL LOGIC FAMILIES
1 1 0 1 0 0
1 1 1 0 0 0
Refer Fig. 1.50 and Table 1.27 for classification and pros
(Continued) and cons of logic families.

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 1.5 DIGITAL LOGIC FAMILIES     27

Logic families

Bipolar Unipolar

Saturated Non- saturated PMOS

RTL (resistor ECL (emitter coupled

transistor logic) logic) NMOS

DTL (diode transistor

logic) Schottky TTL CMOS

HTL (high threshold

logic)

TTL (transistor
transistor logic)

I2L (integrated injection

logic)

Figure 1.50 |   Digital logic families.

Table 1.27 |   Pros and cons of logic families

Logic Families Pros Cons
RTL Economical and simple to design, can Low threshold and fan out, poor noise
easily interface with other logic families immunity, low speed and low power dissipation
DTL High speed with 30-ns propagation delay, Poor noise immunity and fan out
low power dissipation
TTL Fastest saturating logic family, high- Power dissipation is more than MOS gates,
speed Schottky, low-power Schottky, noise immunity is not very high
noise margin about 0.4 V, more fan out,
can drive up to 10 gates
ECL Highest speed because transistors operate Very low noise margin, highest power
in active region, propagation delay of dissipation, high cost
2-ns, parameters resistant to temperature
change
NMOS Very low power dissipation, large fan out High power dissipation than CMOS, low speed
up to 20, very high noise margin of operation, large propagation delay per gate
I2L Composed of BJT so high speed of Lower packing density than NMOS, lower noise
operation, low power dissipation, low margin, external resistance required for proper
power supply requirement functioning
CMOS Large fan out (>50), lowest power Increased cost, less packing density than NMOS
dissipation, very high noise immunity,
temperature resistant

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 28     Chapter 1: Digital Electronics 

IMPORTANT FORMULAS

1. Null − All the outputs are zero. 28. X⋅X = X

2. Identity − All the outputs are one. 29. X⋅0 = 0
3. X inhibit Y - Represented as (x ⋅ ∼y) 30. X⋅Y = Y⋅X
4. Y inhibit X - Represented as (y ⋅ ∼x) 31. X⋅(Y⋅Z) = (X⋅Y)⋅Z
5. Transfer - Same as y 32. X + (Y⋅Z) = (X + Y)⋅(X + Z)
6. AND - x ⋅ y (Similar to intersection in set theory) 33. (X⋅Y)′ = X′ + Y′
7. OR - x + y (Similar to union in set theory) 34. X⋅(X + Y) = X
8. NOT X− ∼x (Also known as complement of x)
9. NOT Y− ∼y (Also known as complement of y) Half Adder:

10. XOR − (∼x ⋅ y) + (x ⋅ ∼y) (Also known as parity

35. S = X′Y + XY′
checker) 36. C = XY
11. XNOR − (x ⋅ y) + (∼x ⋅ ∼y)
Full Adder:
12. NAND − ∼(x ⋅ y)
′ + XY ′Cin
37. S = X ′Y ′Cin + X ′YCin ′ + XYCin
13. NOR − ∼(x + y)
38. Cout = ACin+ XY + YCin
14. X implication Y (∼x + y)
15. Y implication X (∼y + x) Half Subtractor:
16. X + 0 = X 39. D = XY′ + X′Y
17. X + (∼X) = 1 40. B = X′Y
18. X + X = X
Full Subtractor:
19. X + 1 = 1
′ + XY ′Bin
41. D = X ′Y ′Bin + X ′YBin ′ + XYBin
20. X + Y = Y + X
42. B = X′Y + X′YBin + YBin
21. X + (Y + Z) = (X + Y) + Z
22. X ⋅ (Y + Z) = X ⋅Y + X⋅Z Characteristic Equations:
23. ∼(X + Y) = ∼X⋅∼Y (Also called DeMorgan’s law) 43. SR flip-flop: Qn+1= S + R′Qn
24. X + (X ⋅Y) = X 44. D flip-flop: Qn+1= D
25. ∼(∼X) = X
45. JK flip-flop: Qn +1 = JQn′ + KQn
46. T flip-flop: Qn +1 = TQn′ + T ′Qn
Duality Theorem:
26. X ⋅ 1 = X
27. (X⋅∼X) = X⋅X′ = 0

SOLVED EXAMPLES

1. A correct output is achieved from a master-slave Solution: The clock is high, only the flip-flops
JK flip-flop only if its inputs are stable while the are stable when the inputs are stable.
Ans. (d)
(a) Clock is LOW
(b) lave is ready to receive the input from master 2. An inverter circuit can be realized with how many
(c) Master gives a reset signal to slave NAND gates?
(d) Clock is HIGH

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