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SUMMER – 19 EXAMINATION (any other

Subject Name: MICROPROCESSOR Model Answer Subject Code: 22415 example
allowed)
Important Instructions to examiners: c List assembly language programming tools. 2M
1) The answers should be examined by key words and not as word-to-word as given in the Ans 1. Editors Each ½ M
model answer scheme. 2. Assembler
2) The model answer and the answer written by candidate may vary but the examiner may try 3. Linker
to assess the understanding level of the candidate.
4. Debugger.
3) The language errors such as grammatical, spelling errors should not be given more
Importance (Not applicable for subject English and Communication Skills. d Define Macro.Give syntax. 2M
4) While assessing figures, examiner may give credit for principal components indicated in the Ans Macro: Small sequence of the codes of the same pattern are repeated Definition1M
figure. The figures drawn by candidate and model answer may vary. The examiner may give frequently at different places which perform the same operation on the
credit for any equivalent figure drawn. different data of same data type, such repeated code can be written separately Syntax 1M
5) Credits may be given step wise for numerical problems. In some cases, the assumed called as Macro.
constant values may vary and there may be some difference in the candidate’s answers and
model answer. Syntax:
6) In case of some questions credit may be given by judgement on part of examiner of relevant
answer based on candidate’s understanding. Macro_name MACRO[arg1,arg2,…..argN)
7) For programming language papers, credit may be given to any other program based on
equivalent concept. …..

Q. Sub Answer Marking End

No. Q. Scheme e Draw flowchart for multiplication of two 16 bit numbers. 2M
N. Ans Correct
1. Attempt any Five of the following: 10M flowchart:
a State the function of READY and INTR pin of 8086 2M 2M(consider
Ans Ready: Each correct any relevant
It is used as acknowledgement from slower I/O device or memory. function 1M flowchart
It is Active high signal, when high; it indicates that the peripheral device is also)
ready to transfer data.
INTR
This is a level triggered interrupt request input, checked during last clock
cycle of each instruction to determine the availability of request. If any
interrupt request is occurred, the processor enters the interrupt acknowledge
cycle.
b What is role of XCHG instruction in assembly language program? 2M
Give example
Ans Role of XCHG: Correct
role:1M
This instruction exchanges the contents of a register with the contents of
another register or memory location. Correct
example : 1M
Example: f Draw machine language instruction format for Register-to-Register 2M
transfer.
XCHG AX, BX ; Exchange the word in AX with word in BX.

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Ans Correct 6. Example :- Call FAR PTR Example :- Call Delay

diagram 2M Delay

g State the use of STC and CMC instruction of 8086. 2M

Ans STC – This instruction is used to Set Carry Flag. CF1 Each correct b Draw flag register of 8086 and explain any four flags. 4M
use 1M Ans Flag Register of 8086 Correct
CMC – This instruction is used to Complement Carry Flag.
diagram 2M
CF ~ CF
Any 4 flag
2. Attempt any Three of the following: 12M explanation
a Give the difference between intersegment and intrasegment CALL 4M :1/2 M each
Ans Any 4 points
Sr.no Intersegment Call Intrasegment Call 1M each

1. It is also called Far It is also called Near

Conditional /Status Flags
procedure call procedure call.
C-Carry Flag : It is set when carry/borrow is generated out of MSB of
2. A far procedure refers to a A near procedure refers to a result. (i.e D7 bit for 8-bit operation, D15 bit for a 16 bit operation).
procedure which is in the procedure which is in the
different code segment same code segment from
from that of the call that of the call instruction P-Parity Flag This flag is set to 1 if the lower byte of the result contains even
number of 1’s otherwise it is reset.
instruction.
AC-Auxiliary Carry Flag This is set if a carry is generated out of the lower
3 This procedure call This procedure call replaces nibble, (i.e. From D3 to D4 bit)to the higher nibble
replaces the old CS:IP pairs the old IP with new IP.
with new CS:IP pairs Z-Zero Flag This flag is set if the result is zero after performing ALU
operations. Otherwise it is reset.
4. The value of the old CS:IP The value of old IP is
S-Sign Flag This flag is set if the MSB of the result is equal to 1 after
pairs are pushed on to the pushed on to the stack. performing ALU operation , otherwise it is reset.
stack
SP=SP-2 ;Save IP on O-Overflow Flag This flag is set if an overflow occurs, i.e. if the result of
SP=SP-2 ;Save CS on stack(address of procedure) a signed operation is large enough to be accommodated in destination
stack register.

SP=SP-2 ;Save IP (new Control Flags

offset address of called T-Trap Flag If this flag is set ,the processor enters the single step execution
procedure) mode.

5. More stack locations are Less stack locations are I-Interrupt Flag it is used to mask(disable) or unmask(enable)the INTR
required required interrupt. When this flag is set,8086 recognizes interrupt INTR. When it
is reset INTR is masked.

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D-Direction Flag It selects either increment or decrement mode for DI &/or Operation
SI register during string instructions.
Destination OR source
c Explain assembly language program development steps. 4M
Ans 1. Defining the problem: The first step in writing program is to think very Correct steps Flags Affected :CF=0,OF=0,PF,SF,ZF
carefully about the problem that the program must solve. 4M This instruction OR’s each bit in a source byte or word with the
2. Algorithm: The formula or sequence of operations to be performed by the corresponding bit in a destination byte or word. The result is put in a
program can be specified as a step in general English is called algorithm. specified destination.
3. Flowchart: The flowchart is a graphically representation of the program
operation or task. Example :
4. Initialization checklist: Initialization task is to make the checklist of
entire variables, constants, all the registers, flags and programmable ports • OR AL,BL
5. Choosing instructions: Choose those instructions that make program • AL 1111 1100
smaller in size and more importantly efficient in execution. • BL 0000 0011
6. Converting algorithms to assembly language program: Every step in ---------------------
the algorithm is converted into program statement using correct and efficient
• AL1111 1111
instructions or group of instructions.
d Explain logical instructions of 8086.(Any Four) 4M
3) NOT – Logical Invert
Ans Logical instructions. Any 4
instruction Syntax : NOT destination
1) AND- Logical AND correct
explanation Operation: Destination NOT destination
Syntax : AND destination, source
1M each
Flags Affected :None
Operation
The NOT instruction inverts each bit of the byte or words at the
Destination ←destination AND source
specified destination.
Flags Affected :CF=0,OF=0,PF,SF,ZF
Example
This instruction AND’s each bit in a source byte or word with the
NOT BL
same number bit in a destination byte or word. The result is put in
destination. BL = 0000 0011
Example: AND AX, BX NOT BL gives 1111 1100
• AND AL,BL 4) XOR – Logical Exclusive OR
• AL 1111 1100
• BL 0000 0011 Syntax : XOR destination, source
---------------------
Operation : Destination Destination XOR source
• AL0000 0000 (AND AL,BL)
Flags Affected :CF=0,OF=0,PF,SF,ZF

2) OR – Logical OR This instruction exclusive, OR’s each bit in a source byte or word
with the same number bit in a destination byte or word.
Syntax :OR destination, source

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Example(optional)
XOR AL,BL
• AL 1111 1100
• BL 0000 0011
---------------------

• AL1111 1111 (XOR AL,BL)

5)TEST
Syntax : TEST Destination, Source
This instruction AND’s the contents of a source byte or word with the
contents of specified destination byte or word and flags are updated, ,
flags are updated as result ,but neither operands are changed.
Operation performed:
Flags set for result of (destination AND source)

Example: (Any 1)
TEST AL, BL ; AND byte in BL with byte in AL, no result, Update PF,
SF, ZF.

e.g MOV AL, 00000101

TEST AL, 1 ; ZF = 0.
TEST AL, 10b ; ZF = 1

3. Attempt any Four of the following:

a Draw functional block diagram of 8086 microprocessor. 4M
Ans b Write an ALP to add two 16-bit numbers. 4M
Block
diagram 4M Ans DATA SEGMENT Data segment
initialization
NUMBER1 DW 6753H 1M, Code
segment 3M
NUMBER2 DW 5856H
SUM DW 0
DATA ENDS
CODE SEGMENT
ASSUME CS: CODE, DS: DATA
START: MOV AX, DATA

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MOV DS, AX JMP

MOV AX, NUMBER1 NEXT EXIT: MOV LEN,CL
MOV BX, NUMBER2 MOV AH,4CH
ADD AX, BX INT 21H
MOV SUM, AX CODE ENDS
MOV AH, 4CH d Write an assembly language program to solve p= x2+y2 using Macro.(x 4M
and y are 8 bit numbers.
INT 21H Ans .MODEL SMALL program - 4
CODE ENDS M
PROG MACRO a,b
END START
MOV al,a
c Write an ALP to find length of string. 4M
Ans Data Segment program - 4 MUL al
M
STRG DB 'GOOD MORNING$' MOV bl,al

LEN DB ? MOV al,b

DATA ENDS MUL al
CODE SEGMENT ADD al,bl
START:
ENDM
ASSUME CS: CODE, DS : DATA
.DATA
MOV DX, DATA
x DB 02H
MOV DS,DX
y DB 03H
LEA SI, STRG
p DB DUP()
MOV CL,00H
.CODE
MOV AL,'$'
NEXT: CMP AL,[SI] START:

JZ EXIT MOV ax,data

ADD CL,01H MOV ds,ax

INC SI PROG x, y

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MOV p,al DATA ENDS

CODE SEGMENT
MOV ah,4Ch ASSUME DS:DATA, CS:CODE
START:
Int 21H MOV DX,DATA
MOV DS,DX
END MOV AX, N
MOV CL,08
NEXT: ROL AX,01
4. Attempt any Three of the following: JC ONE
a What is pipelining? How it improves the processing speed. INC Z
Ans  In 8086, pipelining is the technique of overlapping instruction fetch Explanation 3 ONE: LOOP NEXT
and execution mechanism. M, Diagram HLT
 To speed up program execution, the BIU fetches as many as six 1M CODE ENDS
instruction bytes ahead of time from memory. The size of END START
instruction prefetching queue in 8086 is 6 bytes. c Write an ALP to find largest number in array of elements 10H, 24H, 4M
 While executing one instruction other instruction can be fetched. 02H, 05H, 17H.
Thus it avoids the waiting time for execution unit to receive other Ans DATA SEGMENT Program - 4
instruction. ARRAY DB 10H,24H,02H,05H,17H M
LARGEST DB 00H
 BIU stores the fetched instructions in a 6 level deep FIFO . The
DATA ENDS
BIU can be fetching instructions bytes while the EU is decoding an
CODE SEGMENT
instruction or executing an instruction which does not require use of START:
the buses. ASSUME CS:CODE,DS:DATA
 When the EU is ready for its next instruction, it simply reads the MOV DX,DATA
instruction from the queue in the BIU. MOV DS,DX
 This is much faster than sending out an address to the system MOV CX,04H
memory and waiting for memory to send back the next instruction MOV SI ,OFFSET
byte or bytes. ARRAY MOV AL,[SI]
 This improves overall speed of the processor UP: INC SI
CMP AL,[SI]
JNC NEXT
MOV AL,[SI]
NEXT: DEC CX
JNZ UP
MOV LARGEST,AL
MOV AX,4C00H
INT 21H
CODE ENDS
END START
d Write an ALP for addition of series of 8-bit number using procedure. 4M
b Write an ALP to count no.of 0’s in 16 bit number. 4M Ans DATA SEGMENT Program - 4
Ans DATA SEGMENT Program 4 M NUM1 DB 10H,20H,30H,40H,50H M
N DB 1237H RESULT DB 0H
Z DB 0 CARRY DB 0H

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DATA ENDS
CODE SEGMENT
ASSUME CS:CODE, DS:DATA
START: MOV DX,DATA
MOV DS, DX
MOV CL,05H
MOV SI, OFFSET NUM1
UP: CALL SUM
INC SI
LOOP UP
MOV AH,4CH
INT 21H

SUM PROC; Procedure to add two 8 bit numbers

MOV AL,[SI]
ADD RESULT, AL
JNC NEXT
INC CARRY
NEXT: RET
SUM ENDP
CODE ENDS
END START

e Describe re-entrant and recursive procedure with schematic diagram. 4M

Ans In some situation it may happen that Procedure 1is called from main program Re-entrant 2
Procrdure2 is called from procedure1And procrdure1 is again called from M, recursive
procdure2. In this situation program execution flow reenters in the 2 M
procedure1. These types of procedures are called re enterant procedures. The
RET instruction at the end of procrdure1 returns to procedure2. The RET
instruction at the end of procedure2 will return the execution to 5. Attempt any Two of the following: 12 M
procedure1.Procedure1 will again executed from where it had stopped at the a Define logical and effective address. Describe physical address 6M
time of calling procrdure2 and the RET instruction at the end of this will generation process in 8086. If DS=345AH and SI=13DCH. Calculate
return the program execution to main program. physical address.
The flow of program execution for re-entrant procedure is as shown in FIG.
Ans A logical address is the address at which an item (memory cell, storage Define each
element) appears to reside from the perspective of an executing application Term :1M.
program. A logical address may be different from the physical address due
to the operation of an address translator or mapping function. Physical
Address
Effective Address or Offset Address: The offset for a memory operand is Generation.
called the operand's effective address or EA. It is an unassigned 16 bit Description :
number that expresses the operand's distance in bytes from the beginning of 2 M
the segment in which it resides. In 8086 we have base registers and index &
registers. Calculation 2
M

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Generation of 20 bit physical address in 8086:- Example

Data SEGMENT
1. Segment registers carry 16 bit data, which is also known as base address. Num1 EQU 50H
Num2 EQU 66H
2. BIU appends four 0 bits to LSB of the base address. This address becomes
Data ENDS
20-bit address.
Numeric value 50H and 66H are assigned to Num1 and Num2.
3. Any base/pointer or index register carries 16 bit offset.
ASSUME
4. Offset address is added into 20-bit base address which finally forms 20 bit ASSUME tells the assembler what names have been chosen for Code, Data
physical address of memory location Extra and Stack segments. Informs the assembler that the register CS is to be
initialized with the address allotted by the loader to the label CODE and DS
is similarly initialized with the address of label DATA.

OFFSET
OFFSET is an operator, which tells the assembler to determine the offset or
displacement of a named data item (variable), a procedure from the start of
the segment, which contains it.
Example
MOV BX;
OFFSET PRICES;
It will determine the offset of the variable PRICES from the start of the
segment in which PRICES is defined and will load this value into BX.
SEGMENT
The SEGMENT directive is used to indicate the start of a logical segment.
DS=345AH and SI=13DCH
Preceding the SEGMENT directive is the name you want to give the
Physical adress = DS*10H + SI segment.
For example, the statement CODE SEGMENT indicates to the assembler
= 345AH * 10H + 13DCH the start of a logical segment called CODE. The SEGMENT and ENDS
directive are used to “bracket” a logical segment containing code of data
= 345A0+13DC
EVEN (ALIGN ON EVEN MEMORY ADDRESS)
= 3597CH As an assembler assembles a section of data declaration or instruction
b Explain the use of assembler directives. 1) DW 2) EQU 3) ASSUME 4) 2M statements, it uses a location counter to keep track of how many bytes it is
OFFSET 5) SEGMENT 6) EVEN from the start of a segment at any time. The EVEN directive tells the
Ans DW (DEFINE WORD)
assembler to increment the location counter to the next even address, if it is
Each
not already at an even address. A NOP instruction will be inserted in the
The DW directive is used to tell the assembler to define a variable of type Directive
location incremented over.
word or to reserve storage locations of type word in memory. The statement Use : 1M
MULTIPLIER DW 437AH, for example, declares a variable of type word each c Describe any four string instructions of 8086 assembly language. 2M
named MULTIPLIER, and initialized with the value 437AH when the Ans 1] REP: each correct
program is loaded into memory to be run. instruction
REP is a prefix which is written before one of the string instructions. It will 1½ M each
EQU (EQUATE) cause During length counter CX to be decremented and the string instruction
EQU is used to give a name to some value or symbol. Each time the to be repeated until CX becomes 0.
assembler finds the given name in the program, it replaces the name with
the value or symbol you equated with that name.

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Two more prefix. CMPSB destination, source

REPE/REPZ: Repeat if Equal /Repeat if Zero. CMPSW destination, source
It will cause string instructions to be repeated as long as the compared bytes Operation: Flags affected < ----- DS:[SI]- ES:[DI]
or words Are equal and CX≠0.
It compares a byte or word in one string with a byte or word in another string.
REPNE/REPNZ: Repeat if not equal/Repeat if not zero. SI Holds the offset of source and DI holds offset of destination strings. CS
contains counter and DF=0 or 1 to auto increment or auto decrement pointer
It repeats the strings instructions as long as compared bytes or words are not after comparing one byte/word.
equal
Example
And CX≠0.
LEA SI, Source
Example: REP MOVSB
LEA DI, destination
2] MOVS/ MOVSB/ MOVSW - Move String byte or word.
CLD
Syntax:
MOV CX, 100
MOVS destination, source
REPE CMPSB
MOVSB destination, source
4] SCAS/SCASB/SCASW: Scan a string byte or word.
MOVSW destination, source
Syntax:
Operation: ES:[DI]<----- DS:[SI]
SCAS/SCASB/SCASW
It copies a byte or word a location in data segment to a location in extra
segment. The offset of source is pointed by SI and offset of destination is Operation: Flags affected < ----- AL/AX-ES: [DI]
pointed by DI.CX register contain counter and direction flag (DE) will be set
or reset to auto increment or auto decrement pointers after one move. It compares a byte or word in AL/AX with a byte /word pointed by ES: DI.
The string to be scanned must be in the extra segment and pointed by DI. CX
Example contains counter and DF may be 0 or 1.
LEA SI, Source When the match is found in the string execution stops and ZF=1 otherwise
ZF=0.
LEA DI, destination
Example
CLD
LEA DI, destination
MOV CX, 04H
MOV Al, 0DH
REP MOVSB
MOV CX, 80H
3] CMPS /CMPSB/CMPSW: Compare string byte or Words.
CLD
Syntax:
REPNE SCASB
CMPS destination, source

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5] LODS/LODSB/LODSW: Example:
Load String byte into AL or Load String word into AX. MOV AX,CX
Syntax: 3. Direct addressing mode
LODS/LODSB/LODSW An instruction in which 16 bit effective address of an operand is specified in
the instruction, then the addressing mode of such instruction is known as
Operation: AL/AX < ----- DS: [SI] direct addressing mode.
IT copies a byte or word from string pointed by SI in data segment into AL Example:
or AX.CX
MOV CL,[2000H]
may contain the counter and DF may be either 0 or 1 4. Register Indirect addressing mode
Example An instruction in which address of an operand is specified in pointer register
or in index register or in BX, then the addressing mode is known as register
LEA SI, destination
indirect addressing mode.
CLD
Example:
LODSB
MOV AX, [BX]
6] STOS/STOSB/STOSW (Store Byte or Word in AL/AX)
5. Indexed addressing mode
Syntax STOS/STOSB/STOSW
An instruction in which the offset address of an operand is stored in index
Operation: ES:[DI] < ----- AL/AX registers (SI or DI) then the addressing mode of such instruction is known as
indexed addressing mode.
It copies a byte or word from AL or AX to a memory location pointed by DI
in extra DS is the default segment for SI and DI.

segment CX may contain the counter and DF may either set or reset For string instructions DS and ES are the default segments for SI and DI resp.
this is a special case of register indirect addressing mode.
6. Attempt any Two of the following: 12M
Example:
a Describe any 6 addressing modes of 8086 with one example each. 6M
Ans 1. Immediate addressing mode: Any 6 mode MOV AX,[SI]
with example
An instruction in which 8-bit or 16-bit operand (data) is specified in the 1 M each 6. Based Indexed addressing mode:
instruction, then the addressing mode of such instruction is known as
Immediate addressing mode. An instruction in which the address of an operand is obtained by adding the
content of base register (BX or BP) to the content of an index register (SI or
Example: DI) The default segment register may be DS or ES
MOV AX,67D3H Example:
2. Register addressing mode MOV AX, [BX][SI]
An instruction in which an operand (data) is specified in general purpose 7. Register relative addressing mode: An instruction in which the address
registers, then the addressing mode is known as register addressing mode. of the operand is obtained by adding the displacement (8-bit or 16 bit) with

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the contents of base registers or index registers (BX, BP, SI, DI). The default Or
segment register is DS or ES.
MOV CL, 04H
Example:
ROR AX, CL
MOV AX, 50H[BX]

8. Relative Based Indexed addressing mode

ii) MOV BL,04h
An instruction in which the address of the operand is obtained by adding the
displacement (8 bit or 16 bit) with the base registers (BX or BP) and index MUL BL
registers (SI or DI) to the default segment.

Example: iii) IDIV BL

MOV AX, 50H [BX][SI] iv) MOV BX,2000h

b Select assembly language for each of the following 6M v) INC AX

i) rotate register BL right 4 times vi) CMP AX,BX
ii) multiply AL by 04H c Write an ALP to reverse a string. Also draw flowchart for same.
iii) Signed division of AX by BL Ans Program: Program 4 M
iv) Move 2000h in BX register flowchart 2
DATA SEGMENT M
v) increment the counter of AX by 1
STRB DB 'GOOD MORNING$'
vi) compare AX with BX
REV DB 0FH DUP(?)
Ans i) MOV CL, 04H Each correct
DATA ENDS
instruction
RCL AX, CL1 1M CODE SEGMENT
START:ASSUME CS:CODE,DS:DATA
Or
MOV DX,DATA
MOV CL, 04H
MOV DS,DX
ROL AX, CL
LEA SI,STRB
MOV CL,0FH
Or
LEA DI,REV
MOV CL, 04H
ADD DI,0FH
RCR AX, CL1
UP:MOV AL,[SI]

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MOV [DI],AL
INC SI
DEC DI
LOOP UP
MOV AH,4CH
INT 21H
CODE ENDS
END START

Flowchart:

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