A micro project report on

ARITHMETIC CIRCUITS
Submitted to CMR Institute of Technology in partial fulfillment of the requirement for the
award of laboratory Digital Logic Design Lab Through Verilog HDL of II B. Tech I semester

CMR INSTITUTE OF TECHNOLOGY

(UGC AUTONOMOUS)
(Approved by AICTE, Affiliated to JNTUH, Kukatpally, Hyderabad)
Kandlakoya, Medchal Road, Hyderabad (2022-2023)

DEPARTMENT OF ELECTRONICS AND COMMUNICATION ENGINEERING

Submitted by

L.JAYA KUSUMA 22R01A0436

Under the Guidance of

Mrs. A. Padma Priya

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 CMR INSTITUTE OF TECHNOLOGY
(UGC AUTONOMOUS)
(Approved by AICTE, Affiliated to JNTUH, Kukatpally, Hyderabad)
Kandlakoya, Medchal Road, Hyderabad (2022-2023)

2022-2023
DEPARTMENT OF ELECTRONICS AND COMMUNICATION
ENGINEERING

CERTIFICATE
This to certify that a Micro Project entitled with “ARITHMETIC CIRCUITS” is being

Submitted by

L.JAYA KUSUMA 22R01A0436

In partial fulfilment of the requirement for award of the “Digital Logic Design Lab through Verilog
HDL” of II B. Tech I semester in ECE to the CMRIT, Hyderabad is a record of a bonafide work carried out
under our guidance and supervision.

Signature of Faculty Signature of HOD

Mrs.A.Padma Priya Dr. K. Niranjan Reddy
(Assistant professor) (Head Of Department)

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 ACKNOWLEDGEMENT

We are extremely grateful to Dr. M. Janga Reddy, Director, Dr. B. Satya Narayana, principal and
Dr.K.Nirangan Reddy, Head of Department, Dept of computer Science and Engineering, CMR Institute
of their inspiration and valuable guidance during entire duration.

We are extremely thankful to our DDVH Lab faculty in-charge Mrs.A.Padma Priya, dept of Electronics
and Communication Engineering, CMR Institute of Technology for her constant guidance,
encouragement and moral support throughout the project.

We express our thanks to all staff members and friends for all the help and coordination extended in
bringing out this project successfully in time.

Finally, we are very much thankful to our parents and relatives who guided directly or
indirectly for successful completion of the project.

L.JAYA KUSUMA 22R01A0436

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TABLE OF CONTENTS:

S.NO Particulars Page No

1 Introduction 5

2 Half adder 5

3 Full adder 6

4 Half subtractor 7

5 Full subtractor 8

6 2 bit comparator 10

7 4 bit comparator 11

8 References 12

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INTRODUCTION:

Arithmetic logic circuits are the logic circuits which perform arithmetic operations like addition,
subtraction in digital computers.

Half adder: It is a combinational logic circuit which performs the addition of two bits resulting in
two outputs - Sum and Carry.

Block diagram of half adder Logic diagram or logic circuit of half adder

Sum = A + B
A Sum B
Half
Inputs Outputs
Adder
B Carry
Carry = AB

Truth table of half ladder

Inputs Outputs
A B Sum = A + B Carry = AB
0 0 0 0
0 1 1 0
1 0 1 0
1 1 0 1
Timing Diagram
Half adder using universal NAND
gates
A
A

B Sum

B
S
Carry

Boolean expression:

Sum = A + B = 𝐀̅ B + A 𝐁̅

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Carry = AB

Full adder: It is a combinational logic circuit which performs the addition of three bits resulting
in two outputs - Sum and Carry.
Block diagram of full adder

A Sum
Full
Inputs B Outputs
Adder
C Carry

Truth table of full adder

Inputs Outputs
A B C Sum = A + B + C Carry = AB +BC +CA
0 0 0 0 0
0 0 1 1 0
0 1 0 1 0
0 1 1 0 1
1 0 0 1 0
1 0 1 0 1
1 1 0 0 1
1 1 1 1 1

Logic circuit of full adder

A
B Sum =A + B + C

C
Carry = AB + B C + AC

Boolean expression for the sum Boolean expression for the carry
Sum == A + B + C
Carry = AB + BC + AC
Sum = A̅ B̅ C + A̅ B C̅ + A B C̅ + AB C
Timing Diagram

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 A

Sum

Carry

Half Subtractor: It is combinational logic circuits which performs the subtraction of two bits
resulting in two outputs - Difference and Borrow.

Block diagram of half Subtractor Logic diagram or logic circuit of half ubtractor

A
Difference = A + B
B
A Half Difference
Subtractor

Inputs Outputs ̅ B
Borrow =A
Borrow
B

Truth table of half Subtractor

Inputs Outputs
A B Difference = A + B Borrow = A̅ B
0 0 0 0
0 1 1 1
1 0 1 0
1 1 0 0

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A B

Difference
B

Borrow

Boolean expression: Borrow Timing Diagram

Difference = A + B = 𝐀̅ B + A 𝐁̅
Borrow = 𝐀̅ B

Full subtractor: It is combinational logic circuits which performs the subtraction of three bits
resulting in two outputs difference and borrow.

Difference
A Full
Inputs
Subtractor
B Outputs

C Borrow

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 Input Output
A B C Difference Borrow = A̅ C
=A+B+C + A̅ B + B C A
0 0 0 0 0 B Difference = A + B + C
0 0 1 1 1
0 1 0 1 1
0 1 1 0 1
1 0 0 1 0
1 0 1 0 0
Borrow =
1 1 0 0 0 C B + BC
1 1 1 1 1

4 BIT PARALLEL BINARY ADDER:

A Parallel Adder is a digital circuit capable of finding the arithmetic sum of two binary numbers
that is greater than one bit in length by operating on corresponding pairs of bits in parallel. It
consists of full adders connected in cascade where the output carry from each full adder is
connected to the carry input of the next higher order full adder

Consider two 4-bit binary numbers B 4B 3B 2B 1 and A 4A 3A 2A 1 are to be added with a carry input C
1. This can be done by cascading four full adder circuits as shown in Figure. The least significant bits
A 1, B 1, and C 1 are added to the produce sum output S 1 and carry output C 2. Carry output C 2 is
then added to the next significant bits A 2 and B 2 producing sum output S 2 and carry output
C 3. C 3 is then added to A 3 and B 3 and so on. Thus finally producing the four-bit sum output S 4S 3S
2S 1 and final carry output Cout.

Magnitude Comparator
Data comparison is needed in digital systems while performing arithmetic or logical operations. This
comparison determines whether one number is greater than, equal, or less than the other number.

A Magnitude Comparator is a combinational circuit that compares two binary numbers in order to
find out whether one binary number is equal, less than or greater than the other binary number.

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The Block diagram of Magnitude Comparator is as shown below.

Types of Magnitude Comparator:

1. 1-bit magnitude comparator.

2. 2-bit magnitude comparator.
3. 3-bit magnitude comparator.
4. 4-bit magnitude comparator.

2-bit magnitude comparator:

A 2-bit comparator compares two binary numbers, each of two bits and produces their
relation such as one number is equal or greater than or less than the other. The figure below shows
the block diagram of a two-bit comparator which has four inputs and three outputs.

The first number A is designated as A = A1A0 and the second number is designated as B =
B1B0. This comparator produces three outputs as G (G = 1 if A>B), E (E = 1, if A = B) and L (L = 1
if A<B).

The truth table for a 2-bit comparator is given below:

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4-Bit Comparator
It can be used to compare two four-bit words. The two 4-bit numbers are A = A3 A2 A1 A0 and
B3 B2 B1 B0 where A3 and B3 are the most significant bits.
It compares each of these bits in one number with bits in that of other number and produces
one of the following outputs as A = B, A < B and A>B. The output logic statements of this
converter are

• If A3 = 1 and B3 = 0, then A is greater than B (A>B). Or

• If A3 and B3 are equal, and if A2 = 1 and B2 = 0, then A > B. Or
• If A3 and B3 are equal & A2 and B2 are equal, and if A1 = 1, and B1 = 0, then A>B. Or 
If A3 and B3 are equal, A2 and B2 are equal and A1 and B1 are equal, and if A0 = 1
and B0 = 0, then A > B.
Block diagram:

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Truth table

Reference Books:

1. Thomas L. Floyd, “Digital Fundamentals,” 11th Edition, Pearson Education, 2015.

2. A.P. Malvino, D. P. Leach, and Saha, “Digital Principles and Applications,” 8th Edition, TMH,
2014.
3. https://www.electronics-tutorials.ws/combination/comb_8.html
4. https://www.elprocus.com/digital-comparator-and-magnitude-comparator/

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