Advanced Sequential Circuit Design

Lecturer: Tzu-Hsuan, Hung

System Integration and Silicon Implementation (Si2) Lab
Institute of Electronics
National Yang Ming Chiao Tung University, Hsinchu, Taiwan

1
 Outline

Section 1- Timing

Section 2- Designware

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 Outline

Section 1- Timing
Setup/hold time
Pipeline

Section 2- Designware

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 Timing of D Flip-Flop

Term definition
Setup time (tsetup): The time that the input signal must be stabilized
before the clock edge.
Hold time (thold): The time that the input signal must be stabilized
after the clock edge.
Clk-to-Q contamination delay (tccq): The contamination time that Q
is first changed after the clock edge.
Clk-to-Q propagation delay (tpcq): The propagation time that Q
reaches steady state after the clock edge.

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 Timing Violation

Timing violation Q_1

D_2

Tpd: Logic Propagation Delay

Tcd: Logic Contamination Delay
Tskew: Difference between CLK_1 and CLK_2

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 Timing Check (1/2)

Setup time check

The $setup system task determines whether a data signal remains
stable for a minimum specified time before a transition in an
enabling, such as a clock event.

in this red region

Hold time check
The $hold system task determines whether a data signal remains
stable for a minimum specified time after a transition in an
enabling signal, such as a clock event.

in this red region

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 Timing Check (2/2)

Timing report: setup time

Timing report: hold time Slacks should be MET!

(non-negative)

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 Setup Time Criterion

Setup time margin: ( Tcycle + tskew ) > ( tpcq + tpd +

tsetup )

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 Hold Time Criterion

Hold time margin: ( tccq + tcd ) > ( thold + tskew )

tcc tc
q d

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Adjust data path to meet the constraints
Setup violation too many works in one cycle
Apply pipelining
Hold violation insufficient delay
add delays the violated path, such as buffers/inverters/Muxes

Increase clock period for setup violation

In most practical cases, hold violations are fixed
during the backend work (after clock tree synthesis)

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 Outline

Section 1- Timing
Setup/hold time
Pipeline

Section 2- Designware

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 Trade-off between Area and Timing

Area: 1 unit
Time: 40 mins (Wash: 20 mins + Dry: 20 mins)

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 Trade-off between Area and Timing

0 40 80 120 160

Wash and Dry = 40 mins

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 Trade-off between Area and Timing

0 40 80 120 160

Wash and Dry = 40 mins

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 Trade-off between Area and Timing

0 40 80 120 160

Wash and Dry = 40 mins

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 Trade-off between Area and Timing

0 40 80 120 160

Area: 1 unit
Time: 160 mins
Wash and Dry = 40 mins

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 Trade-off between Area and Timing

0 40 80 120 160

Area: 1 unit
Time: 160 mins
Wash and Dry = 40 mins

Wash and Dry = 40 mins

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 Trade-off between Area and Timing

0 40 80 120 160

Area: 1 unit
Time: 160 mins
Wash and Dry = 40 mins

Wash and Dry = 40 mins

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 Trade-off between Area and Timing

0 40 80 120 160

Area: 1 unit
Time: 160 mins
Wash and Dry = 40 mins

Area: 2 units
Time: 80 mins
Wash and Dry = 40 mins

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 Trade-off between Area and Timing

0 40 80 120 160

Area: 1 unit
Time: 160 mins
Wash 20 mins
Area 0.7 units

Dry 20 mins
Area 0.7 units

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 Trade-off between Area and Timing

0 20 40 80 120 160

Area: 1 unit
Time: 160 mins
Wash 20 mins

Dry 20 mins

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 Trade-off between Area and Timing

0 40 80 120 160

Area: 1 unit
Time: 160 mins
Wash 20 mins

Dry 20 mins

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 Trade-off between Area and Timing

0 40 60 80 120 160

Area: 1 unit
Time: 160 mins
Wash 20 mins

Dry 20 mins

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 Trade-off between Area and Timing

0 40 80 120 160

Area: 1 unit
Time: 160 mins
Wash 20 mins

Dry 20 mins

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 Trade-off between Area and Timing

0 40 80 100 120 160

Area: 1 unit
Time: 160 mins
Wash 20 mins

Area: 0.7+0.7 =1.4 units

Time: 100 mins
Dry 20 mins

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 Trade-off between Area and Timing

Area: 1 unit
Basic
Time: 160 mins

Area: 2 units
Parallel
Time: 80 mins

Area: 0.7+0.7 = 1.4 units

Pipeline
Time: 100 mins

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 Trade-off between Area and Timing

a [7:0] , b [7:0] , c [3:0] , d [3:0]

Q: (a + b + c + d) x 4 iterations ?

Basic

Parallel

Pipeline

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 Trade-off between Area and Timing

a [7:0] , b [7:0] , c [3:0] , d [3:0]

Q: (a + b + c + d) x 4 iterations ?
5

c 5-bit 9
Add 10
d 9-bit
Area: 24 units
er
Basic a Adder 10-bit output
Time: 24 x 4 = 96 units
b Adder

Parallel

Pipeline

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 Trade-off between Area and Timing

a [7:0] , b [7:0] , c [3:0] , d [3:0]

Q: (a + b + c + d) x 4 iterations ?
5
c 5-bit 9
Add 10
d 9-bit
Area: 24 units
er
Basic a Adder 10-bit output
Time: 24 x 4 = 96 units
b Adder

a 9-bit
c Adder 10-bit Area: 28 units
output
Parallel b 9-bit Adder
Adder
Time: 19 x 4 = 76 units
d

Pipeline

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 Trade-off between Area and Timing

a [7:0] , b [7:0] , c [3:0] , d [3:0]

Q: (a + b + c + d) x 4 iterations ?
5
c 5-bit 9
Add 10
d 9-bit
Area: 24 units
er
Basic a Adder 10-bit output
Time: 24 x 4 = 96 units
b Adder

a 9-bit
c Adder 10-bit Area: 28 units
output
Parallel b 9-bit Adder
Adder
Time: 19 x 4 = 76 units
d
c 5-bit
Add
d
Pipeline a
er 9-bit
Adder 10-bit output
b Adder

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 Trade-off between Area and Timing
5
9
c 5-bit 10
Pipe d Adder
9-bit
a Adder out
line 10-bit
b Adder put

T=0 c1 + d1

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 Trade-off between Area and Timing

c 5-bit
Pipe d Adder
9-bit
a Adder out
line 10-bit
b Adder put

T=0 c1 + d1

T=1 c2 + d2 a1 + (c1 + d1)

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 Trade-off between Area and Timing

c 5-bit
Pipe d Adder
9-bit
a Adder out
line 10-bit
b Adder put

T=0 c1 + d1

T=1 c2 + d2 a1 + (c1 + d1)

T=2 c3 + d3 a2 + (c2 + d2) b1 + (a1 + c1 + d1)

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 Trade-off between Area and Timing

c 5-bit
Pipe d Adder
9-bit
a Adder out
line 10-bit
b Adder put

T=0 c1 + d1

T=1 c2 + d2 a1 + (c1 + d1)

T=2 c3 + d3 a2 + (c2 + d2) b1 + (a1 + c1 + d1)

T=3 c4 + d4 a3 + (c3 + d3) b2 + (a2 + c2 + d2)

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 Trade-off between Area and Timing

c 5-bit
Pipe d Adder
9-bit
a Adder out
line 10-bit
b Adder put

T=0 c1 + d1

T=1 c2 + d2 a1 + (c1 + d1)

T=2 c3 + d3 a2 + (c2 + d2) b1 + (a1 + c1 + d1)

T=3 c4 + d4 a3 + (c3 + d3) b2 + (a2 + c2 + d2)

T=4 a4 + (c4 + d4) b3 + (a3 + c3 + d3)

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 Trade-off between Area and Timing

c 5-bit
Pipe d Adder
9-bit
a Adder out
line 10-bit
b Adder put

T=0 c1 + d1

T=1 c2 + d2 a1 + (c1 + d1)

T=2 c3 + d3 a2 + (c2 + d2) b1 + (a1 + c1 + d1)

T=3 c4 + d4 a3 + (c3 + d3) b2 + (a2 + c2 + d2)

T=4 a4 + (c4 + d4) b3 + (a3 + c3 + d3)

T=5 b4 + (a4 + c4 + d4)

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 Trade-off between Area and Timing

a [7:0] , b [7:0] , c [3:0] , d [3:0]

Q: (a + b + c + d) x 4 iterations ?
5
c 5-bit 9
Add 10
d 9-bit
Area: 24 units
er
Basic a Adder 10-bit output
Time: 24 x 4 = 96 units
b Adder

a 9-bit
c Adder 10-bit Area: 28 units
output
Parallel b 9-bit Adder
Adder
Time: 19 x 4 = 76 units
d
c 5-bit
Add Area: 24+ units
d
Pipeline a
er 9-bit
Adder 10-bit output Time: 60 units
b Adder

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 Outline

Section 1- Timing

Section 2- Designware

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 Overview of DesignWare
IP (Intellectual Property )
Hard IP : GDSII format, high performance but technology dependent.
Firm IP : Netlist resource, less used.
Soft IP : RTL design, requires verification.
DesignWare library
Provides synthesizable and verification IPs.
Supports the method to optimize the area or the speed and reduce the
timing.
DesignWare IP library categories
Building Block IPs (formally called Foundation Library)
CoreTools
Implementation IPs
Smart Model Library
Memory Models
AMBA OCB Family
Verification IPs

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 DesignWare Building Block IPs (1/2)
DesignWare building block IPs
A collection of reusable IP blocks integrated into the SYNOPSYS
synthesis environment.

Characteristics
Pre-verified for quality and better quality of results (QOR) in
synthesis, decreasing design and technology risk.
Allows high-level optimization of performance during synthesis.
Increased design reusability, productivity
Parameterized in size and also in functionality for some IP
Technology-independent
Provide synthesizable models, simulation models, datasheets, and
examples.

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 DesignWare Building Block IPs (2/2)
Library categories
Basic Library : A set of components bundled with HDL
Compiler that implements several common
arithmetic and logic functions.
Logic : Combinational and sequential components
Math : Arithmetic and trigonometric components
Memory : Registers, FIFOs, and FIFO controllers, sync. And
async. RAMs and stack components.
DSP Library : Digital filters for digital signal processing (DSP)
applications, ex: FIR, IIR filter
Application Specific: Data integrity, interface, and JTAG components.
GTECH Library : Genetic technology library, a technology-
Independent, gate-level library.

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Usage of DesignWare Building Block IP
Usage of DesignWare Building Block IP
Operator inference
Convenient, but sometimes it is inefficient when synthesizing.
Supply default function only, can not use special function.
Instantiate IP
Use SYNOPSYS design compiler shell script.
Supply different architecture for implementation.
Applying pre-compiling sub-blocks speeds up the synthesis for large design.

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 Operator Inference (1/3)
Operator inference
Use the HDL operator in description, and the operator
must include in synthetic operator definition.
HDL compiler will infer synthetic operator in HDL code.
HDL compiler supply high-level synthesis.
The / operator is required for the DesignWare license.
The HDL operator defined in standard synthetic operator:

Synthetic Operators HDL Operator

adder +, +1
subtractor -, -1
comparator ==, <, <=, >, >=
multiplier *
selector If, case

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 Operator Inference (2/3)
High-level synthesis
Arithmetic optimization
Arithmetic level optimization, ex: a+b+c+d -> (a+b)+(c+d)

Resource sharing
Allows similar operations that do not overlap in time to be carried out
by the same physical hardware.

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 Operator inference (3/3)
High-level synthesis flow

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 Instantiate IP (1/9)
Instantiation IP
To instantiate a synthetic module manually and explicitly.
Need to include a reference to the synthetic module in HDL code.

SYNOPSYS online document

Command:
evince /RAID2/EDA/synopsys/synthesis/2020.09/dw/doc/manuals/dwbb_userguide.pdf &
remember execute Xwin and setenv DISPLAY your_IP:0

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 Instantiate IP (2/9)
SYNOPSYS online document
Select section1.6

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 Instantiate IP (3/9)

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 Instantiate IP (4/9)
Module
name

input & output

Argument
assignment:
DW02_ mult #(N,N)

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 Instantiate IP (5/9)

User implementation type

specification

Simulation model path specification

Functional parameter specification

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 Instantiate IP (6/9)
Instantiate module
Instantiate the synthetic module and specify parameters defined in
document.

Table1-
2
Table1-1 I/O port

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 Instantiate IP (7/9)
RTL behavior simulation
Specify the behavioral simulation models (Table1-4).
Absolute path
Relative path
Absolute path
`include /usr/synthesis/dw/sim_ver/<model_name>.v

Relative path
`include <model_name>.v

Command: irun <file_name>.v incdir <directory>

Ex : irun DW02_multi_inst.v incdir /usr/synthesis/dw/sim_ver/

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 Instantiate IP (8/9)
Synthesis
Apply //synopsys translate_off
//synopsys translate_on
//synopsys translate_off (DA synthesis off)

//synopsys translate_on (DA synthesis on)

Set the implementation type of IP

User specify the implementation type of IP manually.

//synopsys dc_script_begin
//set_implementation wall U1 (instance name of IP)
implementation type from (Table1-3)
//synopsys dc_script_end

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 Instantiate IP (9/9)
Example
RTL/Gate simulation description

//synopsys translate_off
(Table1-4)
//synopsys translate_on

module SignedMultiplier(a, b, product);

input [7 : 0] a;
input [7 : 0] b;
output [15: 0] product;

(cell name) (Table1-2) (Table1-1)

//synopsys dc_script_begin
//set_implementation csa U1
(Table1-3)
//synopsys dc_script_end
Note : If you use Designware, you should use clean
command after each simulation. (./09_clean_up)!
endmodule

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