DSDE 152

Digital System Design

Lecture 5: SD, ASM Chart,

Transition Map, Timing
Diagram
Spring 2021
Dr. Shawkat S. Khairullah
Department of Computer Engineering 1
University of Mosul
Introductions
• Lecture Goals

• Understand the concepts of State Diagram (SD), ASM

Chart, Transition map, Timing diagram.

• Understand standard design techniques for designing

sequential logic circuits (synchronous and
asynchronous), and be able to design sequential logic
circuits for fundamental operations (e.g., counters).

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 Types of Logic Circuits
• Combinational logic circuits:
• Outputs depend only on its current inputs.
• A combinational circuit may contain an arbitrary number of logic gates
and inverters but no feedback loops.
• A feedback loop is a connection from the output of one gate to
propagate back into the input of that same gate.
• The function of a combinational circuit represented by a logic diagram is
formally described using logic expressions and truth tables.
• Sequential logic circuits:
• Outputs depend not only on the current inputs but also on the past
sequences of inputs.
• Sequential logic circuits contain combinational logic in addition to
memory elements formed with feedback loops.
• The behavior of sequential circuits is formally described by state
transition tables and diagrams. 3
 Logic Circuits

Combinational Sequential

Synchronous Asynchronous

Moore Mealy Fundamental Mode Pulse Mode

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Combinational circuits example:
9+5=14

1001+
0101
1110
B3 A3 B2 A2 B1 A1 B0 A0

0 1 1 0 0 0 1 1

C3 C2 C1 C0 C-1
Adder Adder Adder Adder
0 0 1 0
0

1 1 1 0 Least
significant bit
Z3 Z2 Z1 Z0

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Sequential circuits example:
Clock Clock
cycle cycle
1234 1234
1001 0111
A
Z
1010
B Adder 1000
0100
C
Least
Least significant bit
significant bit

Q
D
Flip-Flop

6
CLK
The Circuit Model

x1 Combinational
z1
: :
: logic :
xn zm

( a)

x1 z1
: :
: :
xn Combinational zm
logic
: :
: :

y1 yr Yr Y1

Memory
7

(b)
 Synchronous Circuit Model
ik
State or Feedback
secondary signals
variables k

Excitation or next k
Componential
External logic circuit state signals Edge-triggered k
Primary n (D1,…,Dk) Memory devices
input input
signals Present state
variables k
(I1,…,In) output signals
(q1,…,qk)

Control input
signals
(provided by
a system
clock) 8
1
T
f
 Asynchronous Circuit Model
ik
State or Feedback
secondary signals
variables k

Excitation or next K
Componential
External logic circuit state signals Propagation k
Primary n (D1,…,Dk) delays
input input
signals Present state
variables
(I1,…,In) output signals
(q1,…,qk)

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Bistable Memory Devices

Bistable devices
(flip-flops)
types
S-R, D, J-k and T

Latches Master-slave Edge triggered

(either basic or (pulse triggered) flip-flops
gated) flip-flops

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Multivibrator
• A multivibrator is an electronic circuit used to implement a
variety of simple two-state systems such as oscillators, timers
and flip-flops. It is characterized by two amplifying devices
(transistors, electron tubes or other devices) cross-coupled by
resistors and capacitors.

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Types of multivibrator circuit
• There are three types of multivibrator circuit:
• astable, in which the circuit is not stable in either state it
continuously oscillates from one state to the other.
• monostable, in which one of the states is stable, but the other
is not. This circuit is also known as a one shot. A common
application is in eliminating switch bounce.
• bistable, in which the circuit will remain in either state
indefinitely. The circuit can be flipped from one state to the
other by an external event or trigger. Such a circuit is important
as the fundamental building block of a register or memory
device. This circuit is also known as a flip-flop.

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 Unstable or astable
•Astable or free-running multivibrators switch back
and forth between two unstable states. This makes it
useful for generating clock signals for synchronous
circuits.
•Crystal control may be used if a very stable clock is
needed. Crystal control is used in microprocessor
based systems and microcomputers where accurate
timing intervals are essential.
tpd>0
1
X(t) 0/1 Z(t)
0/1

tpd
1 13
Z(t) 0
time
tpd
Thank you

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