About Coursera Coursera was founded by Daphne Koller and Andrew Ng in 2012 with a vision of providing life- transforming learning experiences to learners around the world. Today, Coursera is a global online learning platform that offers anyone, anywhere, access to online courses and degrees from leading universities and companies. Coursera received B Corp certification in February 2021, which means that we have a legal duty not only to our shareholders, but to also make a positive impact on society more broadly, as we continue our efforts to reduce barriers to world-class education for all Coursera partners with more than 200 leading universities and companies to bring flexible, affordable, job-relevant online learning to individuals and organizations worldwide. “Introduction to FPGA Design for Embedded Systems" is being taught by University of Colorado Boulder. About University of Colorado Boulder ‘The University of Colorado Boulder is a public research university in Boulder, Colorado. Founded in 1876, five months before Colorado became a state, it is the flagship university of the University of Colorado system. CU Boulder is a member of the Association of American Universities, a selective group of major research universities in North America, and is classified among Ru: Doctoral Universities - Very high research activity. In 2021, the university attracted support of over $634 million for research and spent $536 million on research and development according to the National Science Foundation, ranking it soth in the nation. PAGEwhat's all this programmable logic stuff about anyway? To help answer that question, let's look at a history of programmable logic devices to give us some perspective on programmable logic devices, PLDs in general, and field programmable gate arrays, or FPGAs in particular. FPGAs are a subset programmable logic devices The first programmable logic device was a PROM or a Programmable Read Only Memory Tt was invented in 1956 but not commercially available until 1969. Followed in quickly by EPROMS are Erasable Programmable Read Only Memory in 1971 — And then, PLAs, Programmable Logie Arrays in 1975. - And PALs, Programmal ble Array Logic in 1978, ‘The desire to have programmable hardware has been in existence ever since the very beginning of digital hardware. We can realize any logic equation to level some of product format Notion that we will adopt for two level programmable logic blocks ~ BCU Tela cl oe Hardwired Programmable Link — Not Connecter PAGE 2PROM Architecture 3 = the first programmable logic is a PROM The PROM has a fixed AND plane or product terms which is the address decoding logic ‘The OR plain or the sum terms is programmable through the change of memory contents. This is an eight by four PROM depicted here Cd Using this, we could implement up to 4 logic function with 3 variables each For eg. - to implement a logic function yr =A.B.C we need to store in the first column of PROM - oxo1 or obooo00001 Then only when all the inputs ~ A, B, and Care 1, output o1 will be ede) ROM PNreglice Uc} PAGE 3PAL Architecture = The PAL has a programmable AND plane or product terms, through the change of memory contents. = The OR plain or the sum terms is fixed. = this is a more efficient architecture since most of the logic functions we are interested in have a limited number of products and terms. devices are very popular and they're still used in many designs, with common part numbers like 22Vi0 or 16R8. 2. Further development led to CPLDs, which were devices with multiple PALs in the same package with registered outputs programmable fabric. Pupamie HO Pe Wuvy a aCe) ead PAGE 4CPLDs So recall the PAL, which created a sum of products logi and array followed by a fixed or array. functions using a programmable This allowed the replacement of up to a dozen different logic packages with a general logic solution because arbitrary logic functions could be implemented in a disjunctive normal form. Altera extended this concept by putting multiple PAL structures called macrocells into a single integrated circuit package in which all the input pins were available to each macrocell and any output pin could be driven by any macrocell CPLDs were also built in CMOS to be reprogrammable while Bi-polar PALs were not Although it didn’t seem to be a major attribute at the time, reprogrammability is now considered a very important aspect of PLD devices. Here's a picture of a CPLD Macrocell You can see that a CPLD Macrocell is just basically a registered PAL array. The mock symbols represent programmable configuration switches present in the device. The PIA is a matrix of interconnecting wires that connects the macrocells together, feeding the output of the cells to the inputs of other cells. his structure is good for problems that require a good deal of logic for every flip-flop, like a complex 16 state machine or a wide input decoder PAGE 5FPGAs Field Programmable Gate Arrays (FPGAs) are semiconductor devices that are based around a matrix of configurable logic blocks (CLBs) connected via programmable interconnects. FPGAs can be reprogrammed to desired application or functionality requirements after manufacturing. FPGA was invented to provide a general purpose digital logic device with great flexibility and utility. Semiconductor companies were good at making memories, which had regular highly optimized structures that were easily replicated The first FPGAs were an array of logic cells consisting of three input LUTs. FPGA architecture is different from CPLDs, as the logic element is smaller, usually implemented as a LUT. Logic Cell Here's a simplified schematic of an FPGA logic cell Can) Tar Atypical cell consists of a 4-input LUT, a full adder, the FA, and a D-type flip-flop. The LUTS in this figure are split into two 3-input LUTS, In normal mode, they're combined into a 4-input LUT through the left mux. In arithmetic mode the outputs are fed to the FA. ‘The selection of the mode is programmed into the middle multiplexer PAGE 6Look Up Tables (LUTs) = The figure shows a 4-LUT, which consists of 6 bits of SRAM, in a 16:1 multiplexer, implemented as a tree of 2:1 multiplexers. The 4-LUT can implement any function of four inputs, inputs being A, B, C, or D, by setting the appropriate value on the LUT mask, = It ean also be built from two 3-LUTs, connected by a 2:1 multiplexer = We can implement more logic in the larger LUT devices — However, there's a trade off between LUT size and the amount of routing needed. Bigger LUTs mean less routing, but also more memory locations. PAGE 7Quartus Prime Intel Quartus Prime is programmable logic device design software produced by Intel. Quartus Prime enables analysis and synthesis of HDL designs, which enables the developer to compile their designs, perform timing analysis, examine RTL diagrams, simulate a design's reaction to different stimuli, and configure the target device with the programmer. Quartus Prime includes an implementation of VHDL and Verilog for hardware description, visual editing of logic circuits, and vector waveform simulation. Here are some screenshots of the software, with an example project named pipemult. The completed pipemult schematic high level RTL view PAGE 8The Compilation Report Shobit ‘The ModelSim Simulation waveform window PAGE 9Topics to be covered in coming weeks - Hardware Description Languages for FPGA Design «Basics of VHDL * VHDL Logic Design Techniques © Basics of Verilog + Verilog and System Verilog Design Techniques — FPGA Softcore Processors and IP Acquisition ‘+ Softcore Processor Development Flow ‘+ Writing Software for Softcore Processors * IP Acquisition and Integration ‘* Introducing Modelsim and Simulation for Verification - FPGA Capstone: Building FPGA Projects Altera MAXio Hardware Setup * Develop a Mixed Signal System ‘+ Create a System on a Chip with NIOS II ‘+ Software for a System on a Chip PAGE 10