 Two types of FETs

 Junction field-effect transistor (JFET)

 Metal-oxide-semiconductor field-effect transistor (MOSFET).
Depletion MOSFET
Enhancement MOSFET
 JFET is Junction gate field-effect transistor.
 Normal BJT is a current controlled device which needs current for biasing,
whereas JFET is a voltage controlled device.
 Just as there are npn and pnp bipolar transistors, there are n-channel and p-
channel field-effect transistors.
 However BJT is a bipolar device—the prefix bi- revealing that the
conduction level is a function of two charge carriers, electrons and holes.
Whereas the FET is a unipolar device depending solely on either electron
(n-channel) or hole (p-channel) conduction.
 One of the most important characteristics of the FET as compared to BJTs
is its high input impedance – a very important characteristic in the design of
linear ac amplifier systems.
 In general, FETs are more temperature stable than BJTs, and FETs are
usually smaller in construction than BJTs, making them particularly useful
in integrated-circuit (IC) chips.
 FETs, however, are more sensitive to handling than BJTs.
 JFET provides low power consumption and fairly low power dissipations,
thus improving the overall efficiency of the circuit as compared to BJTs
 BJT’s have higher gains than FETs
 JFET is Junction gate field-effect transistor.
 It has three terminals Gate, Drain, and Source.
 JFET is a three-terminal device with one terminal capable of controlling the current
between the other two
 The two types are N-Channel JFET and P-Channel JFET as shown:
 The current flowing through the Drain and Source is dependable on the voltage
applied to the Gate terminal. For the N channel JFET, the Gate voltage is negative
and for the P channel JFET the Gate voltage is positive.
 The basic construction of the n-channel JFET is shown in Fig.
 Note that the major part of the structure is the n-type material that forms the channel
between the embedded layers of p-type material.
 The top of the n-type channel is connected through an ohmic contact to a terminal
referred to as the drain (D), while the lower end of the same material is connected
through an ohmic contact to a terminal referred to as the source (S).
 The two p-type materials are connected together to the gate (G) terminal. In
essence, therefore, the drain and source are connected to the ends of the n-type
channel and the gate to the two layers of p-type material.
 In the absence of any applied potentials the JFET
has two p-n junctions under no-bias conditions.
 The result is a depletion region at each junction as
shown in Fig.
 Recall also that a depletion region is that region
void of free carriers and therefore unable to
support conduction through the region.
 VGS = 0 V, VDS Some Positive Value:
 A positive voltage VDS has been applied across the channel and the gate has been
connected directly to the source to establish the condition VGS = 0 V.
 Since gate and source terminal are at the same potential the depletion region in the
low end of each p-material similar to the distribution of the no-bias conditions.
 The instant the voltage VDD (VDS) is applied, the electrons will be drawn to the drain
terminal, establishing the conventional current ID as shown is fig.
 The path of charge flow clearly reveals that the
drain and source currents are equivalent (ID = IS).
 It is important to note that the depletion region is
wider near the top of both p-type materials.
 The reason for the change in width of the region is
because the upper region experiences more
reverse bias and hence a wider depletion region
towards the drain
 VGS = 0 V, VDS Some Positive Value:
 As the voltage VDS is increased from 0 to a few volts, the current will increase as
determined by Ohm’s law and the plot of ID versus VDS will appear as shown in Fig
 The relative straightness of the plot reveals that for the region of low values of VDS,
the resistance is essentially constant.
 As VDS increases and approaches a level referred to as VP, the depletion regions of
will widen, causing a noticeable reduction in the channel width. The reduced path of
conduction causes the resistance to increase and the curve in the graph to occur.
 VGS = 0 V, VDS Some Positive Value:
 The more horizontal the curve, the higher the resistance, suggesting that the
resistance is approaching “infinite” ohms in the horizontal region.
 If VDS is increased to a level where it appears that the two depletion regions would
“touch”, a condition referred to as pinch-off will result. The level of VDS that
establishes this condition is referred to as the pinch-off voltage and is denoted by
VP, at this point current ID maintains a saturation level defined as IDSS
 VGS = 0 V, VDS Some Positive Value:
 In essence, therefore, once VDS=VP the JFET has the characteristics of a current
source, with a current fixed at ID = IDSS
 IDSS is the maximum drain current for a JFET and is defined by the conditions VGS
= 0 V and VDS = |VP|.
 VGS < 0 V:
 A negative voltage is now applied between the gate and source terminals for a low
level of VDS.
 The effect of the applied negative-bias VGS is to establish depletion regions similar
to those obtained with VGS = 0 V but at lower levels of VDS.
 Therefore, the result of applying a negative bias to the gate is to reach the saturation
level at a lower level of VDS as shown.
 The region to the right of the pinch-off locus is the region typically employed in
linear amplifiers (amplifiers with minimum distortion of the applied signal) and is
commonly referred to as the constant-current, saturation, or linear amplification
region.
 The region to the left of the pinch-off locus is referred to as the ohmic or voltage-
controlled resistance region. In this region the JFET can actually be employed as a
variable resistor , whose resistance is controlled by the applied gate-to-source
voltage, and is given by:
 The relationship between ID and VGS is defined by Shockley’s equation

 The transfer characteristics are a plot of an output (or drain) current versus an input-
controlling quantity. There is therefore a direct “transfer” from input to output
variables when employing the curve to the left.
 One is a plot of ID versus VDS, while the other is ID versus VGS.
 Using the drain characteristics on the right of the “y” axis, a horizontal line can be
drawn from the saturation region of the curve denoted VGS = 0 V to the ID axis.
 The resulting current level for both graphs is IDSS. The point of intersection on the ID
versus VGS curve will be as shown since the vertical axis is defined as VGS =0V.
 In review: When VGS = 0 V, ID = IDSS.
 When VGS = VP, ID = 0 mA.